projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 86a74ff2 NI |
1 | /* |
| 2 | * SuperH Ethernet device driver | |
| 3 | * | |
| 4 | * Copyright (C) 2006-2008 Nobuhiro Iwamatsu | |
| 380af9e3 | 5 | * Copyright (C) 2008-2009 Renesas Solutions Corp. |
| 86a74ff2 NI |
6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it | |
| 8 | * under the terms and conditions of the GNU General Public License, | |
| 9 | * version 2, as published by the Free Software Foundation. | |
| 10 | * | |
| 11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 14 | * more details. | |
| 15 | * You should have received a copy of the GNU General Public License along with | |
| 16 | * this program; if not, write to the Free Software Foundation, Inc., | |
| 17 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 | * | |
| 19 | * The full GNU General Public License is included in this distribution in | |
| 20 | * the file called "COPYING". | |
| 21 | */ | |
| 22 | ||
| 23 | #ifndef __SH_ETH_H__ | |
| 24 | #define __SH_ETH_H__ | |
| 25 | ||
| 26 | #include <linux/module.h> | |
| 27 | #include <linux/kernel.h> | |
| 28 | #include <linux/spinlock.h> | |
| 86a74ff2 NI |
29 | #include <linux/netdevice.h> |
| 30 | #include <linux/phy.h> | |
| 31 | ||
| 71557a37 YS |
32 | #include <asm/sh_eth.h> |
| 33 | ||
| 86a74ff2 NI |
34 | #define CARDNAME "sh-eth" |
| 35 | #define TX_TIMEOUT (5*HZ) | |
| b0ca2a21 NI |
36 | #define TX_RING_SIZE 64 /* Tx ring size */ |
| 37 | #define RX_RING_SIZE 64 /* Rx ring size */ | |
| 86a74ff2 NI |
38 | #define ETHERSMALL 60 |
| 39 | #define PKT_BUF_SZ 1538 | |
| 40 | ||
| 380af9e3 | 41 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) |
| 65ac8851 YS |
42 | /* This CPU register maps is very difference by other SH4 CPU */ |
| 43 | ||
| 86a74ff2 | 44 | /* Chip Base Address */ |
| 2e2a6a9f | 45 | # define SH_TSU_ADDR 0xFEE01800 |
| 380af9e3 | 46 | # define ARSTR SH_TSU_ADDR |
| b0ca2a21 NI |
47 | |
| 48 | /* Chip Registers */ | |
| 49 | /* E-DMAC */ | |
| 50 | # define EDSR 0x000 | |
| 51 | # define EDMR 0x400 | |
| 52 | # define EDTRR 0x408 | |
| 53 | # define EDRRR 0x410 | |
| 54 | # define EESR 0x428 | |
| 55 | # define EESIPR 0x430 | |
| 56 | # define TDLAR 0x010 | |
| 57 | # define TDFAR 0x014 | |
| 58 | # define TDFXR 0x018 | |
| 59 | # define TDFFR 0x01C | |
| 60 | # define RDLAR 0x030 | |
| 61 | # define RDFAR 0x034 | |
| 62 | # define RDFXR 0x038 | |
| 63 | # define RDFFR 0x03C | |
| 64 | # define TRSCER 0x438 | |
| 65 | # define RMFCR 0x440 | |
| 66 | # define TFTR 0x448 | |
| 67 | # define FDR 0x450 | |
| 68 | # define RMCR 0x458 | |
| 69 | # define RPADIR 0x460 | |
| 70 | # define FCFTR 0x468 | |
| 71 | ||
| 72 | /* Ether Register */ | |
| 73 | # define ECMR 0x500 | |
| 74 | # define ECSR 0x510 | |
| 75 | # define ECSIPR 0x518 | |
| 76 | # define PIR 0x520 | |
| 77 | # define PSR 0x528 | |
| 78 | # define PIPR 0x52C | |
| 79 | # define RFLR 0x508 | |
| 80 | # define APR 0x554 | |
| 81 | # define MPR 0x558 | |
| 82 | # define PFTCR 0x55C | |
| 83 | # define PFRCR 0x560 | |
| 84 | # define TPAUSER 0x564 | |
| 85 | # define GECMR 0x5B0 | |
| 86 | # define BCULR 0x5B4 | |
| 87 | # define MAHR 0x5C0 | |
| 88 | # define MALR 0x5C8 | |
| 89 | # define TROCR 0x700 | |
| 90 | # define CDCR 0x708 | |
| 91 | # define LCCR 0x710 | |
| 92 | # define CEFCR 0x740 | |
| 93 | # define FRECR 0x748 | |
| 94 | # define TSFRCR 0x750 | |
| 95 | # define TLFRCR 0x758 | |
| 96 | # define RFCR 0x760 | |
| 97 | # define CERCR 0x768 | |
| 98 | # define CEECR 0x770 | |
| 99 | # define MAFCR 0x778 | |
| 100 | ||
| 101 | /* TSU Absolute Address */ | |
| 102 | # define TSU_CTRST 0x004 | |
| 103 | # define TSU_FWEN0 0x010 | |
| 104 | # define TSU_FWEN1 0x014 | |
| 105 | # define TSU_FCM 0x18 | |
| 106 | # define TSU_BSYSL0 0x20 | |
| 107 | # define TSU_BSYSL1 0x24 | |
| 108 | # define TSU_PRISL0 0x28 | |
| 109 | # define TSU_PRISL1 0x2C | |
| 110 | # define TSU_FWSL0 0x30 | |
| 111 | # define TSU_FWSL1 0x34 | |
| 112 | # define TSU_FWSLC 0x38 | |
| 113 | # define TSU_QTAG0 0x40 | |
| 114 | # define TSU_QTAG1 0x44 | |
| 115 | # define TSU_FWSR 0x50 | |
| 116 | # define TSU_FWINMK 0x54 | |
| 117 | # define TSU_ADQT0 0x48 | |
| 118 | # define TSU_ADQT1 0x4C | |
| 119 | # define TSU_VTAG0 0x58 | |
| 120 | # define TSU_VTAG1 0x5C | |
| 121 | # define TSU_ADSBSY 0x60 | |
| 122 | # define TSU_TEN 0x64 | |
| 123 | # define TSU_POST1 0x70 | |
| 124 | # define TSU_POST2 0x74 | |
| 125 | # define TSU_POST3 0x78 | |
| 126 | # define TSU_POST4 0x7C | |
| 127 | # define TSU_ADRH0 0x100 | |
| 128 | # define TSU_ADRL0 0x104 | |
| 129 | # define TSU_ADRH31 0x1F8 | |
| 130 | # define TSU_ADRL31 0x1FC | |
| 131 | ||
| 132 | # define TXNLCR0 0x80 | |
| 133 | # define TXALCR0 0x84 | |
| 134 | # define RXNLCR0 0x88 | |
| 135 | # define RXALCR0 0x8C | |
| 136 | # define FWNLCR0 0x90 | |
| 137 | # define FWALCR0 0x94 | |
| 138 | # define TXNLCR1 0xA0 | |
| 139 | # define TXALCR1 0xA4 | |
| 140 | # define RXNLCR1 0xA8 | |
| 141 | # define RXALCR1 0xAC | |
| 142 | # define FWNLCR1 0xB0 | |
| 143 | # define FWALCR1 0x40 | |
| 144 | ||
| 65ac8851 YS |
145 | #elif defined(CONFIG_CPU_SH4) /* #if defined(CONFIG_CPU_SUBTYPE_SH7763) */ |
| 146 | /* EtherC */ | |
| 147 | #define ECMR 0x100 | |
| 148 | #define RFLR 0x108 | |
| 149 | #define ECSR 0x110 | |
| 150 | #define ECSIPR 0x118 | |
| 151 | #define PIR 0x120 | |
| 152 | #define PSR 0x128 | |
| 153 | #define RDMLR 0x140 | |
| 154 | #define IPGR 0x150 | |
| 155 | #define APR 0x154 | |
| 156 | #define MPR 0x158 | |
| 157 | #define TPAUSER 0x164 | |
| 158 | #define RFCF 0x160 | |
| 159 | #define TPAUSECR 0x168 | |
| 160 | #define BCFRR 0x16c | |
| 161 | #define MAHR 0x1c0 | |
| 162 | #define MALR 0x1c8 | |
| 163 | #define TROCR 0x1d0 | |
| 164 | #define CDCR 0x1d4 | |
| 165 | #define LCCR 0x1d8 | |
| 166 | #define CNDCR 0x1dc | |
| 167 | #define CEFCR 0x1e4 | |
| 168 | #define FRECR 0x1e8 | |
| 169 | #define TSFRCR 0x1ec | |
| 170 | #define TLFRCR 0x1f0 | |
| 171 | #define RFCR 0x1f4 | |
| 172 | #define MAFCR 0x1f8 | |
| 173 | #define RTRATE 0x1fc | |
| 174 | ||
| 175 | /* E-DMAC */ | |
| 176 | #define EDMR 0x000 | |
| 177 | #define EDTRR 0x008 | |
| 178 | #define EDRRR 0x010 | |
| 179 | #define TDLAR 0x018 | |
| 180 | #define RDLAR 0x020 | |
| 181 | #define EESR 0x028 | |
| 182 | #define EESIPR 0x030 | |
| 183 | #define TRSCER 0x038 | |
| 184 | #define RMFCR 0x040 | |
| 185 | #define TFTR 0x048 | |
| 186 | #define FDR 0x050 | |
| 187 | #define RMCR 0x058 | |
| 188 | #define TFUCR 0x064 | |
| 189 | #define RFOCR 0x068 | |
| 190 | #define FCFTR 0x070 | |
| 191 | #define RPADIR 0x078 | |
| 192 | #define TRIMD 0x07c | |
| 193 | #define RBWAR 0x0c8 | |
| 194 | #define RDFAR 0x0cc | |
| 195 | #define TBRAR 0x0d4 | |
| 196 | #define TDFAR 0x0d8 | |
| 197 | #else /* #elif defined(CONFIG_CPU_SH4) */ | |
| 380af9e3 | 198 | /* This section is SH3 or SH2 */ |
| 71557a37 | 199 | #ifndef CONFIG_CPU_SUBTYPE_SH7619 |
| b0ca2a21 NI |
200 | /* Chip base address */ |
| 201 | # define SH_TSU_ADDR 0xA7000804 | |
| 202 | # define ARSTR 0xA7000800 | |
| 71557a37 | 203 | #endif |
| 86a74ff2 NI |
204 | /* Chip Registers */ |
| 205 | /* E-DMAC */ | |
| b0ca2a21 NI |
206 | # define EDMR 0x0000 |
| 207 | # define EDTRR 0x0004 | |
| 208 | # define EDRRR 0x0008 | |
| 209 | # define TDLAR 0x000C | |
| 210 | # define RDLAR 0x0010 | |
| 211 | # define EESR 0x0014 | |
| 212 | # define EESIPR 0x0018 | |
| 213 | # define TRSCER 0x001C | |
| 214 | # define RMFCR 0x0020 | |
| 215 | # define TFTR 0x0024 | |
| 216 | # define FDR 0x0028 | |
| 217 | # define RMCR 0x002C | |
| 218 | # define EDOCR 0x0030 | |
| 219 | # define FCFTR 0x0034 | |
| 220 | # define RPADIR 0x0038 | |
| 221 | # define TRIMD 0x003C | |
| 222 | # define RBWAR 0x0040 | |
| 223 | # define RDFAR 0x0044 | |
| 224 | # define TBRAR 0x004C | |
| 225 | # define TDFAR 0x0050 | |
| 226 | ||
| 86a74ff2 | 227 | /* Ether Register */ |
| b0ca2a21 NI |
228 | # define ECMR 0x0160 |
| 229 | # define ECSR 0x0164 | |
| 230 | # define ECSIPR 0x0168 | |
| 231 | # define PIR 0x016C | |
| 232 | # define MAHR 0x0170 | |
| 233 | # define MALR 0x0174 | |
| 234 | # define RFLR 0x0178 | |
| 235 | # define PSR 0x017C | |
| 236 | # define TROCR 0x0180 | |
| 237 | # define CDCR 0x0184 | |
| 238 | # define LCCR 0x0188 | |
| 239 | # define CNDCR 0x018C | |
| 240 | # define CEFCR 0x0194 | |
| 241 | # define FRECR 0x0198 | |
| 242 | # define TSFRCR 0x019C | |
| 243 | # define TLFRCR 0x01A0 | |
| 244 | # define RFCR 0x01A4 | |
| 245 | # define MAFCR 0x01A8 | |
| 246 | # define IPGR 0x01B4 | |
| 247 | # if defined(CONFIG_CPU_SUBTYPE_SH7710) | |
| 248 | # define APR 0x01B8 | |
| 249 | # define MPR 0x01BC | |
| 250 | # define TPAUSER 0x1C4 | |
| 251 | # define BCFR 0x1CC | |
| 252 | # endif /* CONFIG_CPU_SH7710 */ | |
| 86a74ff2 NI |
253 | |
| 254 | /* TSU */ | |
| b0ca2a21 NI |
255 | # define TSU_CTRST 0x004 |
| 256 | # define TSU_FWEN0 0x010 | |
| 257 | # define TSU_FWEN1 0x014 | |
| 258 | # define TSU_FCM 0x018 | |
| 259 | # define TSU_BSYSL0 0x020 | |
| 260 | # define TSU_BSYSL1 0x024 | |
| 261 | # define TSU_PRISL0 0x028 | |
| 262 | # define TSU_PRISL1 0x02C | |
| 263 | # define TSU_FWSL0 0x030 | |
| 264 | # define TSU_FWSL1 0x034 | |
| 265 | # define TSU_FWSLC 0x038 | |
| 266 | # define TSU_QTAGM0 0x040 | |
| 267 | # define TSU_QTAGM1 0x044 | |
| 268 | # define TSU_ADQT0 0x048 | |
| 269 | # define TSU_ADQT1 0x04C | |
| 270 | # define TSU_FWSR 0x050 | |
| 271 | # define TSU_FWINMK 0x054 | |
| 272 | # define TSU_ADSBSY 0x060 | |
| 273 | # define TSU_TEN 0x064 | |
| 274 | # define TSU_POST1 0x070 | |
| 275 | # define TSU_POST2 0x074 | |
| 276 | # define TSU_POST3 0x078 | |
| 277 | # define TSU_POST4 0x07C | |
| 278 | # define TXNLCR0 0x080 | |
| 279 | # define TXALCR0 0x084 | |
| 280 | # define RXNLCR0 0x088 | |
| 281 | # define RXALCR0 0x08C | |
| 282 | # define FWNLCR0 0x090 | |
| 283 | # define FWALCR0 0x094 | |
| 284 | # define TXNLCR1 0x0A0 | |
| 285 | # define TXALCR1 0x0A4 | |
| 286 | # define RXNLCR1 0x0A8 | |
| 287 | # define RXALCR1 0x0AC | |
| 288 | # define FWNLCR1 0x0B0 | |
| 289 | # define FWALCR1 0x0B4 | |
| 86a74ff2 NI |
290 | |
| 291 | #define TSU_ADRH0 0x0100 | |
| 292 | #define TSU_ADRL0 0x0104 | |
| 293 | #define TSU_ADRL31 0x01FC | |
| 294 | ||
| b0ca2a21 NI |
295 | #endif /* CONFIG_CPU_SUBTYPE_SH7763 */ |
| 296 | ||
| 380af9e3 YS |
297 | /* There are avoid compile error... */ |
| 298 | #if !defined(BCULR) | |
| 299 | #define BCULR 0x0fc | |
| 300 | #endif | |
| 301 | #if !defined(TRIMD) | |
| 302 | #define TRIMD 0x0fc | |
| 303 | #endif | |
| 304 | #if !defined(APR) | |
| 305 | #define APR 0x0fc | |
| 306 | #endif | |
| 307 | #if !defined(MPR) | |
| 308 | #define MPR 0x0fc | |
| 309 | #endif | |
| 310 | #if !defined(TPAUSER) | |
| 311 | #define TPAUSER 0x0fc | |
| 312 | #endif | |
| 313 | ||
| 314 | /* Driver's parameters */ | |
| 315 | #if defined(CONFIG_CPU_SH4) | |
| 316 | #define SH4_SKB_RX_ALIGN 32 | |
| 317 | #else | |
| 318 | #define SH2_SH3_SKB_RX_ALIGN 2 | |
| 319 | #endif | |
| 320 | ||
| b0ca2a21 NI |
321 | /* |
| 322 | * Register's bits | |
| 323 | */ | |
| 324 | #ifdef CONFIG_CPU_SUBTYPE_SH7763 | |
| 325 | /* EDSR */ | |
| 326 | enum EDSR_BIT { | |
| 327 | EDSR_ENT = 0x01, EDSR_ENR = 0x02, | |
| 328 | }; | |
| 329 | #define EDSR_ENALL (EDSR_ENT|EDSR_ENR) | |
| 330 | ||
| 331 | /* GECMR */ | |
| 332 | enum GECMR_BIT { | |
| 333 | GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01, | |
| 334 | }; | |
| 335 | #endif | |
| 86a74ff2 NI |
336 | |
| 337 | /* EDMR */ | |
| 338 | enum DMAC_M_BIT { | |
| 380af9e3 | 339 | EDMR_EL = 0x40, /* Litte endian */ |
| b0ca2a21 NI |
340 | EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, |
| 341 | #ifdef CONFIG_CPU_SUBTYPE_SH7763 | |
| 380af9e3 | 342 | EDMR_SRST = 0x03, |
| b0ca2a21 NI |
343 | #else /* CONFIG_CPU_SUBTYPE_SH7763 */ |
| 344 | EDMR_SRST = 0x01, | |
| 345 | #endif | |
| 86a74ff2 NI |
346 | }; |
| 347 | ||
| 348 | /* EDTRR */ | |
| 349 | enum DMAC_T_BIT { | |
| b0ca2a21 NI |
350 | #ifdef CONFIG_CPU_SUBTYPE_SH7763 |
| 351 | EDTRR_TRNS = 0x03, | |
| 352 | #else | |
| 86a74ff2 | 353 | EDTRR_TRNS = 0x01, |
| b0ca2a21 | 354 | #endif |
| 86a74ff2 NI |
355 | }; |
| 356 | ||
| 357 | /* EDRRR*/ | |
| 358 | enum EDRRR_R_BIT { | |
| 359 | EDRRR_R = 0x01, | |
| 360 | }; | |
| 361 | ||
| 362 | /* TPAUSER */ | |
| 363 | enum TPAUSER_BIT { | |
| 364 | TPAUSER_TPAUSE = 0x0000ffff, | |
| 365 | TPAUSER_UNLIMITED = 0, | |
| 366 | }; | |
| 367 | ||
| 368 | /* BCFR */ | |
| 369 | enum BCFR_BIT { | |
| 370 | BCFR_RPAUSE = 0x0000ffff, | |
| 371 | BCFR_UNLIMITED = 0, | |
| 372 | }; | |
| 373 | ||
| 374 | /* PIR */ | |
| 375 | enum PIR_BIT { | |
| 376 | PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01, | |
| 377 | }; | |
| 378 | ||
| 379 | /* PSR */ | |
| 380 | enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; | |
| 381 | ||
| 382 | /* EESR */ | |
| 383 | enum EESR_BIT { | |
| 380af9e3 YS |
384 | EESR_TWB1 = 0x80000000, |
| 385 | EESR_TWB = 0x40000000, /* same as TWB0 */ | |
| 386 | EESR_TC1 = 0x20000000, | |
| 387 | EESR_TUC = 0x10000000, | |
| 388 | EESR_ROC = 0x08000000, | |
| 389 | EESR_TABT = 0x04000000, | |
| 390 | EESR_RABT = 0x02000000, | |
| 391 | EESR_RFRMER = 0x01000000, /* same as RFCOF */ | |
| 392 | EESR_ADE = 0x00800000, | |
| 393 | EESR_ECI = 0x00400000, | |
| 394 | EESR_FTC = 0x00200000, /* same as TC or TC0 */ | |
| 395 | EESR_TDE = 0x00100000, | |
| 396 | EESR_TFE = 0x00080000, /* same as TFUF */ | |
| 397 | EESR_FRC = 0x00040000, /* same as FR */ | |
| 398 | EESR_RDE = 0x00020000, | |
| 399 | EESR_RFE = 0x00010000, | |
| 400 | EESR_CND = 0x00000800, | |
| 401 | EESR_DLC = 0x00000400, | |
| 402 | EESR_CD = 0x00000200, | |
| 403 | EESR_RTO = 0x00000100, | |
| 404 | EESR_RMAF = 0x00000080, | |
| 405 | EESR_CEEF = 0x00000040, | |
| 406 | EESR_CELF = 0x00000020, | |
| 407 | EESR_RRF = 0x00000010, | |
| 408 | EESR_RTLF = 0x00000008, | |
| 409 | EESR_RTSF = 0x00000004, | |
| 410 | EESR_PRE = 0x00000002, | |
| 411 | EESR_CERF = 0x00000001, | |
| 412 | }; | |
| 413 | ||
| 414 | #define DEFAULT_TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \ | |
| 415 | EESR_RTO) | |
| 416 | #define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | \ | |
| 417 | EESR_RDE | EESR_RFRMER | EESR_ADE | \ | |
| 418 | EESR_TFE | EESR_TDE | EESR_ECI) | |
| 419 | #define DEFAULT_TX_ERROR_CHECK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | \ | |
| 420 | EESR_TFE) | |
| 86a74ff2 NI |
421 | |
| 422 | /* EESIPR */ | |
| 423 | enum DMAC_IM_BIT { | |
| 424 | DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000, | |
| 425 | DMAC_M_RABT = 0x02000000, | |
| 426 | DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000, | |
| 427 | DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000, | |
| 428 | DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000, | |
| 429 | DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000, | |
| 430 | DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800, | |
| 431 | DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200, | |
| 432 | DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080, | |
| 433 | DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008, | |
| 434 | DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002, | |
| 435 | DMAC_M_RINT1 = 0x00000001, | |
| 436 | }; | |
| 437 | ||
| 438 | /* Receive descriptor bit */ | |
| 439 | enum RD_STS_BIT { | |
| b0ca2a21 NI |
440 | RD_RACT = 0x80000000, RD_RDEL = 0x40000000, |
| 441 | RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000, | |
| 86a74ff2 NI |
442 | RD_RFE = 0x08000000, RD_RFS10 = 0x00000200, |
| 443 | RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080, | |
| 444 | RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020, | |
| 445 | RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008, | |
| 446 | RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002, | |
| 447 | RD_RFS1 = 0x00000001, | |
| 448 | }; | |
| b0ca2a21 NI |
449 | #define RDF1ST RD_RFP1 |
| 450 | #define RDFEND RD_RFP0 | |
| 451 | #define RD_RFP (RD_RFP1|RD_RFP0) | |
| 86a74ff2 NI |
452 | |
| 453 | /* FCFTR */ | |
| 454 | enum FCFTR_BIT { | |
| 455 | FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000, | |
| 456 | FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004, | |
| 457 | FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, | |
| 458 | }; | |
| 380af9e3 YS |
459 | #define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0) |
| 460 | #define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0) | |
| 86a74ff2 NI |
461 | |
| 462 | /* Transfer descriptor bit */ | |
| 463 | enum TD_STS_BIT { | |
| b0ca2a21 NI |
464 | TD_TACT = 0x80000000, |
| 465 | TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000, | |
| 86a74ff2 NI |
466 | TD_TFP0 = 0x10000000, |
| 467 | }; | |
| 468 | #define TDF1ST TD_TFP1 | |
| 469 | #define TDFEND TD_TFP0 | |
| 470 | #define TD_TFP (TD_TFP1|TD_TFP0) | |
| 471 | ||
| 472 | /* RMCR */ | |
| 380af9e3 YS |
473 | #define DEFAULT_RMCR_VALUE 0x00000000 |
| 474 | ||
| 86a74ff2 NI |
475 | /* ECMR */ |
| 476 | enum FELIC_MODE_BIT { | |
| b0ca2a21 NI |
477 | ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000, |
| 478 | ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000, | |
| 86a74ff2 NI |
479 | ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, |
| 480 | ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, | |
| 481 | ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, | |
| 65ac8851 | 482 | ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, |
| 380af9e3 | 483 | ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001, |
| 86a74ff2 NI |
484 | }; |
| 485 | ||
| 486 | /* ECSR */ | |
| 487 | enum ECSR_STATUS_BIT { | |
| b0ca2a21 | 488 | ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, |
| b0ca2a21 | 489 | ECSR_LCHNG = 0x04, |
| 86a74ff2 NI |
490 | ECSR_MPD = 0x02, ECSR_ICD = 0x01, |
| 491 | }; | |
| 492 | ||
| 380af9e3 YS |
493 | #define DEFAULT_ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \ |
| 494 | ECSR_ICD | ECSIPR_MPDIP) | |
| b0ca2a21 | 495 | |
| 86a74ff2 NI |
496 | /* ECSIPR */ |
| 497 | enum ECSIPR_STATUS_MASK_BIT { | |
| b0ca2a21 | 498 | ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10, |
| b0ca2a21 | 499 | ECSIPR_LCHNGIP = 0x04, |
| 86a74ff2 NI |
500 | ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01, |
| 501 | }; | |
| 502 | ||
| 380af9e3 YS |
503 | #define DEFAULT_ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \ |
| 504 | ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) | |
| b0ca2a21 | 505 | |
| 86a74ff2 NI |
506 | /* APR */ |
| 507 | enum APR_BIT { | |
| 508 | APR_AP = 0x00000001, | |
| 509 | }; | |
| 510 | ||
| 511 | /* MPR */ | |
| 512 | enum MPR_BIT { | |
| 513 | MPR_MP = 0x00000001, | |
| 514 | }; | |
| 515 | ||
| 516 | /* TRSCER */ | |
| 517 | enum DESC_I_BIT { | |
| 518 | DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200, | |
| 519 | DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010, | |
| 520 | DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002, | |
| 521 | DESC_I_RINT1 = 0x0001, | |
| 522 | }; | |
| 523 | ||
| 524 | /* RPADIR */ | |
| 525 | enum RPADIR_BIT { | |
| 526 | RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000, | |
| 527 | RPADIR_PADR = 0x0003f, | |
| 528 | }; | |
| 529 | ||
| b0ca2a21 NI |
530 | /* RFLR */ |
| 531 | #define RFLR_VALUE 0x1000 | |
| 532 | ||
| 86a74ff2 | 533 | /* FDR */ |
| 380af9e3 YS |
534 | #define DEFAULT_FDR_INIT 0x00000707 |
| 535 | ||
| 86a74ff2 NI |
536 | enum phy_offsets { |
| 537 | PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3, | |
| 538 | PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6, | |
| 539 | PHY_16 = 16, | |
| 540 | }; | |
| 541 | ||
| 542 | /* PHY_CTRL */ | |
| 543 | enum PHY_CTRL_BIT { | |
| 544 | PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000, | |
| 545 | PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400, | |
| 546 | PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080, | |
| 547 | }; | |
| 548 | #define DM9161_PHY_C_ANEGEN 0 /* auto nego special */ | |
| 549 | ||
| 550 | /* PHY_STAT */ | |
| 551 | enum PHY_STAT_BIT { | |
| 552 | PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000, | |
| 553 | PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020, | |
| 554 | PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004, | |
| 555 | PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001, | |
| 556 | }; | |
| 557 | ||
| 558 | /* PHY_ANA */ | |
| 559 | enum PHY_ANA_BIT { | |
| 560 | PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000, | |
| 561 | PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100, | |
| 562 | PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020, | |
| b0ca2a21 | 563 | PHY_A_SEL = 0x001e, |
| 86a74ff2 NI |
564 | }; |
| 565 | /* PHY_ANL */ | |
| 566 | enum PHY_ANL_BIT { | |
| 567 | PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000, | |
| 568 | PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100, | |
| 569 | PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020, | |
| 570 | PHY_L_SEL = 0x001f, | |
| 571 | }; | |
| 572 | ||
| 573 | /* PHY_ANE */ | |
| 574 | enum PHY_ANE_BIT { | |
| 575 | PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004, | |
| 576 | PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001, | |
| 577 | }; | |
| 578 | ||
| 579 | /* DM9161 */ | |
| 580 | enum PHY_16_BIT { | |
| 581 | PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000, | |
| 582 | PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800, | |
| 583 | PHY_16_TXselect = 0x0400, | |
| 584 | PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100, | |
| 585 | PHY_16_Force100LNK = 0x0080, | |
| 586 | PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020, | |
| 587 | PHY_16_RPDCTR_EN = 0x0010, | |
| 588 | PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004, | |
| 589 | PHY_16_Sleepmode = 0x0002, | |
| 590 | PHY_16_RemoteLoopOut = 0x0001, | |
| 591 | }; | |
| 592 | ||
| 593 | #define POST_RX 0x08 | |
| 594 | #define POST_FW 0x04 | |
| 595 | #define POST0_RX (POST_RX) | |
| 596 | #define POST0_FW (POST_FW) | |
| 597 | #define POST1_RX (POST_RX >> 2) | |
| 598 | #define POST1_FW (POST_FW >> 2) | |
| 599 | #define POST_ALL (POST0_RX | POST0_FW | POST1_RX | POST1_FW) | |
| 600 | ||
| 601 | /* ARSTR */ | |
| 602 | enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, }; | |
| 603 | ||
| 604 | /* TSU_FWEN0 */ | |
| 605 | enum TSU_FWEN0_BIT { | |
| 606 | TSU_FWEN0_0 = 0x00000001, | |
| 607 | }; | |
| 608 | ||
| 609 | /* TSU_ADSBSY */ | |
| 610 | enum TSU_ADSBSY_BIT { | |
| 611 | TSU_ADSBSY_0 = 0x00000001, | |
| 612 | }; | |
| 613 | ||
| 614 | /* TSU_TEN */ | |
| 615 | enum TSU_TEN_BIT { | |
| 616 | TSU_TEN_0 = 0x80000000, | |
| 617 | }; | |
| 618 | ||
| 619 | /* TSU_FWSL0 */ | |
| 620 | enum TSU_FWSL0_BIT { | |
| 621 | TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800, | |
| 622 | TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200, | |
| 623 | TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010, | |
| 624 | }; | |
| 625 | ||
| 626 | /* TSU_FWSLC */ | |
| 627 | enum TSU_FWSLC_BIT { | |
| 628 | TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000, | |
| 629 | TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040, | |
| 630 | TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010, | |
| 631 | TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004, | |
| 632 | TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001, | |
| 633 | }; | |
| 634 | ||
| 635 | /* | |
| 636 | * The sh ether Tx buffer descriptors. | |
| 637 | * This structure should be 20 bytes. | |
| 638 | */ | |
| 639 | struct sh_eth_txdesc { | |
| 640 | u32 status; /* TD0 */ | |
| 641 | #if defined(CONFIG_CPU_LITTLE_ENDIAN) | |
| 642 | u16 pad0; /* TD1 */ | |
| 643 | u16 buffer_length; /* TD1 */ | |
| 644 | #else | |
| 645 | u16 buffer_length; /* TD1 */ | |
| 646 | u16 pad0; /* TD1 */ | |
| 647 | #endif | |
| 648 | u32 addr; /* TD2 */ | |
| 649 | u32 pad1; /* padding data */ | |
| 71557a37 | 650 | } __attribute__((aligned(2), packed)); |
| 86a74ff2 NI |
651 | |
| 652 | /* | |
| 653 | * The sh ether Rx buffer descriptors. | |
| 654 | * This structure should be 20 bytes. | |
| 655 | */ | |
| 656 | struct sh_eth_rxdesc { | |
| 657 | u32 status; /* RD0 */ | |
| 658 | #if defined(CONFIG_CPU_LITTLE_ENDIAN) | |
| 659 | u16 frame_length; /* RD1 */ | |
| 660 | u16 buffer_length; /* RD1 */ | |
| 661 | #else | |
| 662 | u16 buffer_length; /* RD1 */ | |
| 663 | u16 frame_length; /* RD1 */ | |
| 664 | #endif | |
| 665 | u32 addr; /* RD2 */ | |
| 666 | u32 pad0; /* padding data */ | |
| 71557a37 | 667 | } __attribute__((aligned(2), packed)); |
| 86a74ff2 | 668 | |
| 380af9e3 YS |
669 | /* This structure is used by each CPU dependency handling. */ |
| 670 | struct sh_eth_cpu_data { | |
| 671 | /* optional functions */ | |
| 672 | void (*chip_reset)(struct net_device *ndev); | |
| 673 | void (*set_duplex)(struct net_device *ndev); | |
| 674 | void (*set_rate)(struct net_device *ndev); | |
| 675 | ||
| 676 | /* mandatory initialize value */ | |
| 677 | unsigned long eesipr_value; | |
| 678 | ||
| 679 | /* optional initialize value */ | |
| 680 | unsigned long ecsr_value; | |
| 681 | unsigned long ecsipr_value; | |
| 682 | unsigned long fdr_value; | |
| 683 | unsigned long fcftr_value; | |
| 684 | unsigned long rpadir_value; | |
| 685 | unsigned long rmcr_value; | |
| 686 | ||
| 687 | /* interrupt checking mask */ | |
| 688 | unsigned long tx_check; | |
| 689 | unsigned long eesr_err_check; | |
| 690 | unsigned long tx_error_check; | |
| 691 | ||
| 692 | /* hardware features */ | |
| 693 | unsigned no_psr:1; /* EtherC DO NOT have PSR */ | |
| 694 | unsigned apr:1; /* EtherC have APR */ | |
| 695 | unsigned mpr:1; /* EtherC have MPR */ | |
| 696 | unsigned tpauser:1; /* EtherC have TPAUSER */ | |
| 697 | unsigned bculr:1; /* EtherC have BCULR */ | |
| 698 | unsigned hw_swap:1; /* E-DMAC have DE bit in EDMR */ | |
| 699 | unsigned rpadir:1; /* E-DMAC have RPADIR */ | |
| 700 | unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */ | |
| 701 | unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */ | |
| 702 | }; | |
| 703 | ||
| 86a74ff2 | 704 | struct sh_eth_private { |
| bcd5149d | 705 | struct platform_device *pdev; |
| 380af9e3 | 706 | struct sh_eth_cpu_data *cd; |
| 86a74ff2 NI |
707 | dma_addr_t rx_desc_dma; |
| 708 | dma_addr_t tx_desc_dma; | |
| 709 | struct sh_eth_rxdesc *rx_ring; | |
| 710 | struct sh_eth_txdesc *tx_ring; | |
| 711 | struct sk_buff **rx_skbuff; | |
| 712 | struct sk_buff **tx_skbuff; | |
| 713 | struct net_device_stats stats; | |
| 714 | struct timer_list timer; | |
| 715 | spinlock_t lock; | |
| 716 | u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */ | |
| 717 | u32 cur_tx, dirty_tx; | |
| 718 | u32 rx_buf_sz; /* Based on MTU+slack. */ | |
| 71557a37 | 719 | int edmac_endian; |
| 86a74ff2 NI |
720 | /* MII transceiver section. */ |
| 721 | u32 phy_id; /* PHY ID */ | |
| 722 | struct mii_bus *mii_bus; /* MDIO bus control */ | |
| 723 | struct phy_device *phydev; /* PHY device control */ | |
| 724 | enum phy_state link; | |
| 725 | int msg_enable; | |
| 726 | int speed; | |
| 727 | int duplex; | |
| 728 | u32 rx_int_var, tx_int_var; /* interrupt control variables */ | |
| 729 | char post_rx; /* POST receive */ | |
| 730 | char post_fw; /* POST forward */ | |
| 731 | struct net_device_stats tsu_stats; /* TSU forward status */ | |
| 4923576b YS |
732 | |
| 733 | unsigned no_ether_link:1; | |
| 734 | unsigned ether_link_active_low:1; | |
| 86a74ff2 NI |
735 | }; |
| 736 | ||
| 380af9e3 | 737 | static inline void sh_eth_soft_swap(char *src, int len) |
| 86a74ff2 NI |
738 | { |
| 739 | #ifdef __LITTLE_ENDIAN__ | |
| 740 | u32 *p = (u32 *)src; | |
| 741 | u32 *maxp; | |
| 742 | maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32)); | |
| 743 | ||
| 744 | for (; p < maxp; p++) | |
| 745 | *p = swab32(*p); | |
| 746 | #endif | |
| 747 | } | |
| 380af9e3 YS |
748 | |
| 749 | #endif /* #ifndef __SH_ETH_H__ */ |