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net: fix protocol sk_buff field
[deliverable/linux.git] / drivers / net / sis190.c
CommitLineData
890e8d0a
FR		 1/*
2 sis190.c: Silicon Integrated Systems SiS190 ethernet driver
3
4 Copyright (c) 2003 K.M. Liu <kmliu@sis.com>
5 Copyright (c) 2003, 2004 Jeff Garzik <jgarzik@pobox.com>
6 Copyright (c) 2003, 2004, 2005 Francois Romieu <romieu@fr.zoreil.com>
7
40292fb0
FR		 8 Based on r8169.c, tg3.c, 8139cp.c, skge.c, epic100.c and SiS 190/191
9 genuine driver.
890e8d0a
FR		 10
11 This software may be used and distributed according to the terms of
12 the GNU General Public License (GPL), incorporated herein by reference.
13 Drivers based on or derived from this code fall under the GPL and must
14 retain the authorship, copyright and license notice. This file is not
15 a complete program and may only be used when the entire operating
16 system is licensed under the GPL.
17
18 See the file COPYING in this distribution for more information.
19
ad06ab2a
JP		 20*/
21
22#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
890e8d0a
FR		 23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/netdevice.h>
43afb949 27#include <linux/rtnetlink.h>
890e8d0a
FR		 28#include <linux/etherdevice.h>
29#include <linux/ethtool.h>
30#include <linux/pci.h>
31#include <linux/mii.h>
32#include <linux/delay.h>
33#include <linux/crc32.h>
34#include <linux/dma-mapping.h>
35#include <asm/irq.h>
36
fcb9821d
FR		 37#define PHY_MAX_ADDR 32
38#define PHY_ID_ANY 0x1f
39#define MII_REG_ANY 0x1f
40
08326dbe 41#define DRV_VERSION "1.4"
890e8d0a
FR		 42#define DRV_NAME "sis190"
43#define SIS190_DRIVER_NAME DRV_NAME " Gigabit Ethernet driver " DRV_VERSION
890e8d0a 44
890e8d0a
FR		 45#define sis190_rx_skb netif_rx
46#define sis190_rx_quota(count, quota) count
890e8d0a
FR		 47
48#define MAC_ADDR_LEN 6
49
bcad5e53
FR		 50#define NUM_TX_DESC 64 /* [8..1024] */
51#define NUM_RX_DESC 64 /* [8..8192] */
890e8d0a
FR		 52#define TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
53#define RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
54#define RX_BUF_SIZE 1536
8b5641d4 55#define RX_BUF_MASK 0xfff8
890e8d0a
FR		 56
57#define SIS190_REGS_SIZE 0x80
58#define SIS190_TX_TIMEOUT (6*HZ)
59#define SIS190_PHY_TIMEOUT (10*HZ)
60#define SIS190_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
61 NETIF_MSG_LINK | NETIF_MSG_IFUP | \
62 NETIF_MSG_IFDOWN)
63
64/* Enhanced PHY access register bit definitions */
65#define EhnMIIread 0x0000
66#define EhnMIIwrite 0x0020
67#define EhnMIIdataShift 16
68#define EhnMIIpmdShift 6 /* 7016 only */
69#define EhnMIIregShift 11
70#define EhnMIIreq 0x0010
71#define EhnMIInotDone 0x0010
72
73/* Write/read MMIO register */
74#define SIS_W8(reg, val) writeb ((val), ioaddr + (reg))
75#define SIS_W16(reg, val) writew ((val), ioaddr + (reg))
76#define SIS_W32(reg, val) writel ((val), ioaddr + (reg))
77#define SIS_R8(reg) readb (ioaddr + (reg))
78#define SIS_R16(reg) readw (ioaddr + (reg))
79#define SIS_R32(reg) readl (ioaddr + (reg))
80
81#define SIS_PCI_COMMIT() SIS_R32(IntrControl)
82
83enum sis190_registers {
84 TxControl = 0x00,
85 TxDescStartAddr = 0x04,
188f23ba
FR		 86 rsv0 = 0x08, // reserved
87 TxSts = 0x0c, // unused (Control/Status)
890e8d0a
FR		 88 RxControl = 0x10,
89 RxDescStartAddr = 0x14,
188f23ba
FR		 90 rsv1 = 0x18, // reserved
91 RxSts = 0x1c, // unused
890e8d0a
FR		 92 IntrStatus = 0x20,
93 IntrMask = 0x24,
94 IntrControl = 0x28,
188f23ba
FR		 95 IntrTimer = 0x2c, // unused (Interupt Timer)
96 PMControl = 0x30, // unused (Power Mgmt Control/Status)
97 rsv2 = 0x34, // reserved
890e8d0a
FR		 98 ROMControl = 0x38,
99 ROMInterface = 0x3c,
100 StationControl = 0x40,
101 GMIIControl = 0x44,
188f23ba
FR		 102 GIoCR = 0x48, // unused (GMAC IO Compensation)
103 GIoCtrl = 0x4c, // unused (GMAC IO Control)
890e8d0a 104 TxMacControl = 0x50,
188f23ba
FR		 105 TxLimit = 0x54, // unused (Tx MAC Timer/TryLimit)
106 RGDelay = 0x58, // unused (RGMII Tx Internal Delay)
107 rsv3 = 0x5c, // reserved
890e8d0a
FR		 108 RxMacControl = 0x60,
109 RxMacAddr = 0x62,
110 RxHashTable = 0x68,
111 // Undocumented = 0x6c,
188f23ba
FR		 112 RxWolCtrl = 0x70,
113 RxWolData = 0x74, // unused (Rx WOL Data Access)
114 RxMPSControl = 0x78, // unused (Rx MPS Control)
115 rsv4 = 0x7c, // reserved
890e8d0a
FR		 116};
117
118enum sis190_register_content {
119 /* IntrStatus */
120 SoftInt = 0x40000000, // unused
121 Timeup = 0x20000000, // unused
122 PauseFrame = 0x00080000, // unused
123 MagicPacket = 0x00040000, // unused
124 WakeupFrame = 0x00020000, // unused
125 LinkChange = 0x00010000,
126 RxQEmpty = 0x00000080,
127 RxQInt = 0x00000040,
128 TxQ1Empty = 0x00000020, // unused
129 TxQ1Int = 0x00000010,
130 TxQ0Empty = 0x00000008, // unused
131 TxQ0Int = 0x00000004,
132 RxHalt = 0x00000002,
133 TxHalt = 0x00000001,
134
890e8d0a
FR		 135 /* {Rx/Tx}CmdBits */
136 CmdReset = 0x10,
137 CmdRxEnb = 0x08, // unused
138 CmdTxEnb = 0x01,
139 RxBufEmpty = 0x01, // unused
140
141 /* Cfg9346Bits */
142 Cfg9346_Lock = 0x00, // unused
143 Cfg9346_Unlock = 0xc0, // unused
144
145 /* RxMacControl */
146 AcceptErr = 0x20, // unused
147 AcceptRunt = 0x10, // unused
148 AcceptBroadcast = 0x0800,
149 AcceptMulticast = 0x0400,
150 AcceptMyPhys = 0x0200,
151 AcceptAllPhys = 0x0100,
152
153 /* RxConfigBits */
154 RxCfgFIFOShift = 13,
155 RxCfgDMAShift = 8, // 0x1a in RxControl ?
156
157 /* TxConfigBits */
158 TxInterFrameGapShift = 24,
159 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
160
890e8d0a
FR		 161 LinkStatus = 0x02, // unused
162 FullDup = 0x01, // unused
163
164 /* TBICSRBit */
165 TBILinkOK = 0x02000000, // unused
166};
167
168struct TxDesc {
3cec93c7
FR		 169 __le32 PSize;
170 __le32 status;
171 __le32 addr;
172 __le32 size;
890e8d0a
FR		 173};
174
175struct RxDesc {
3cec93c7
FR		 176 __le32 PSize;
177 __le32 status;
178 __le32 addr;
179 __le32 size;
890e8d0a
FR		 180};
181
182enum _DescStatusBit {
183 /* _Desc.status */
bcad5e53
FR		 184 OWNbit = 0x80000000, // RXOWN/TXOWN
185 INTbit = 0x40000000, // RXINT/TXINT
186 CRCbit = 0x00020000, // CRCOFF/CRCEN
187 PADbit = 0x00010000, // PREADD/PADEN
890e8d0a 188 /* _Desc.size */
bcad5e53
FR		 189 RingEnd = 0x80000000,
190 /* TxDesc.status */
191 LSEN = 0x08000000, // TSO ? -- FR
192 IPCS = 0x04000000,
193 TCPCS = 0x02000000,
194 UDPCS = 0x01000000,
195 BSTEN = 0x00800000,
196 EXTEN = 0x00400000,
197 DEFEN = 0x00200000,
198 BKFEN = 0x00100000,
199 CRSEN = 0x00080000,
200 COLEN = 0x00040000,
201 THOL3 = 0x30000000,
202 THOL2 = 0x20000000,
203 THOL1 = 0x10000000,
204 THOL0 = 0x00000000,
697c2696
FR		 205
206 WND = 0x00080000,
207 TABRT = 0x00040000,
208 FIFO = 0x00020000,
209 LINK = 0x00010000,
210 ColCountMask = 0x0000ffff,
bcad5e53
FR		 211 /* RxDesc.status */
212 IPON = 0x20000000,
213 TCPON = 0x10000000,
214 UDPON = 0x08000000,
215 Wakup = 0x00400000,
216 Magic = 0x00200000,
217 Pause = 0x00100000,
218 DEFbit = 0x00200000,
219 BCAST = 0x000c0000,
220 MCAST = 0x00080000,
221 UCAST = 0x00040000,
222 /* RxDesc.PSize */
223 TAGON = 0x80000000,
224 RxDescCountMask = 0x7f000000, // multi-desc pkt when > 1 ? -- FR
225 ABORT = 0x00800000,
226 SHORT = 0x00400000,
227 LIMIT = 0x00200000,
228 MIIER = 0x00100000,
229 OVRUN = 0x00080000,
230 NIBON = 0x00040000,
231 COLON = 0x00020000,
232 CRCOK = 0x00010000,
890e8d0a 233 RxSizeMask = 0x0000ffff
bcad5e53
FR		 234 /*
235 * The asic could apparently do vlan, TSO, jumbo (sis191 only) and
236 * provide two (unused with Linux) Tx queues. No publically
237 * available documentation alas.
238 */
890e8d0a
FR		 239};
240
40292fb0
FR		 241enum sis190_eeprom_access_register_bits {
242 EECS = 0x00000001, // unused
243 EECLK = 0x00000002, // unused
244 EEDO = 0x00000008, // unused
245 EEDI = 0x00000004, // unused
246 EEREQ = 0x00000080,
247 EEROP = 0x00000200,
248 EEWOP = 0x00000100 // unused
249};
250
830fb7d2
FR		 251/* EEPROM Addresses */
252enum sis190_eeprom_address {
253 EEPROMSignature = 0x00,
254 EEPROMCLK = 0x01, // unused
255 EEPROMInfo = 0x02,
256 EEPROMMACAddr = 0x03
257};
258
900eb9d6
FR		 259enum sis190_feature {
260 F_HAS_RGMII = 1,
c3d6f1f2
FR		 261 F_PHY_88E1111 = 2,
262 F_PHY_BCM5461 = 4
900eb9d6
FR		 263};
264
890e8d0a
FR		 265struct sis190_private {
266 void __iomem *mmio_addr;
267 struct pci_dev *pci_dev;
c4028958 268 struct net_device *dev;
890e8d0a
FR		 269 spinlock_t lock;
270 u32 rx_buf_sz;
271 u32 cur_rx;
272 u32 cur_tx;
273 u32 dirty_rx;
274 u32 dirty_tx;
275 dma_addr_t rx_dma;
276 dma_addr_t tx_dma;
277 struct RxDesc *RxDescRing;
278 struct TxDesc *TxDescRing;
279 struct sk_buff *Rx_skbuff[NUM_RX_DESC];
280 struct sk_buff *Tx_skbuff[NUM_TX_DESC];
281 struct work_struct phy_task;
282 struct timer_list timer;
283 u32 msg_enable;
43afb949 284 struct mii_if_info mii_if;
fcb9821d 285 struct list_head first_phy;
900eb9d6 286 u32 features;
08326dbe 287 u32 negotiated_lpa;
fcb9821d
FR		 288};
289
290struct sis190_phy {
291 struct list_head list;
292 int phy_id;
293 u16 id[2];
294 u16 status;
295 u8 type;
296};
297
298enum sis190_phy_type {
299 UNKNOWN = 0x00,
300 HOME = 0x01,
301 LAN = 0x02,
302 MIX = 0x03
303};
304
305static struct mii_chip_info {
306 const char *name;
307 u16 id[2];
308 unsigned int type;
900eb9d6 309 u32 feature;
fcb9821d 310} mii_chip_table[] = {
856f8f41 311 { "Atheros PHY", { 0x004d, 0xd010 }, LAN, 0 },
708f6e27 312 { "Atheros PHY AR8012", { 0x004d, 0xd020 }, LAN, 0 },
c3d6f1f2 313 { "Broadcom PHY BCM5461", { 0x0020, 0x60c0 }, LAN, F_PHY_BCM5461 },
bd7a4448 314 { "Broadcom PHY AC131", { 0x0143, 0xbc70 }, LAN, 0 },
900eb9d6
FR		 315 { "Agere PHY ET1101B", { 0x0282, 0xf010 }, LAN, 0 },
316 { "Marvell PHY 88E1111", { 0x0141, 0x0cc0 }, LAN, F_PHY_88E1111 },
317 { "Realtek PHY RTL8201", { 0x0000, 0x8200 }, LAN, 0 },
fcb9821d 318 { NULL, }
890e8d0a
FR		 319};
320
3c6bee1d 321static const struct {
890e8d0a 322 const char *name;
890e8d0a 323} sis_chip_info[] = {
e797637f
FR		 324 { "SiS 190 PCI Fast Ethernet adapter" },
325 { "SiS 191 PCI Gigabit Ethernet adapter" },
890e8d0a
FR		 326};
327
a3aa1884 328static DEFINE_PCI_DEVICE_TABLE(sis190_pci_tbl) = {
890e8d0a 329 { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x0190), 0, 0, 0 },
e797637f 330 { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x0191), 0, 0, 1 },
890e8d0a
FR		 331 { 0, },
332};
333
334MODULE_DEVICE_TABLE(pci, sis190_pci_tbl);
335
336static int rx_copybreak = 200;
337
338static struct {
339 u32 msg_enable;
340} debug = { -1 };
341
c3223d24 342MODULE_DESCRIPTION("SiS sis190/191 Gigabit Ethernet driver");
890e8d0a
FR		 343module_param(rx_copybreak, int, 0);
344MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
345module_param_named(debug, debug.msg_enable, int, 0);
346MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
347MODULE_AUTHOR("K.M. Liu <kmliu@sis.com>, Ueimor <romieu@fr.zoreil.com>");
348MODULE_VERSION(DRV_VERSION);
349MODULE_LICENSE("GPL");
350
351static const u32 sis190_intr_mask =
21461380 352 RxQEmpty | RxQInt | TxQ1Int | TxQ0Int | RxHalt | TxHalt | LinkChange;
890e8d0a
FR		 353
354/*
355 * Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
356 * The chips use a 64 element hash table based on the Ethernet CRC.
357 */
f71e1309 358static const int multicast_filter_limit = 32;
890e8d0a
FR		 359
360static void __mdio_cmd(void __iomem *ioaddr, u32 ctl)
361{
362 unsigned int i;
363
364 SIS_W32(GMIIControl, ctl);
365
366 msleep(1);
367
368 for (i = 0; i < 100; i++) {
369 if (!(SIS_R32(GMIIControl) & EhnMIInotDone))
370 break;
371 msleep(1);
372 }
373
7bf3f232 374 if (i > 99)
ad06ab2a 375 pr_err("PHY command failed !\n");
890e8d0a
FR		 376}
377
9ede109b 378static void mdio_write(void __iomem *ioaddr, int phy_id, int reg, int val)
890e8d0a 379{
890e8d0a 380 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIwrite |
9ede109b 381 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift) |
890e8d0a
FR		 382 (((u32) val) << EhnMIIdataShift));
383}
384
9ede109b 385static int mdio_read(void __iomem *ioaddr, int phy_id, int reg)
890e8d0a 386{
890e8d0a 387 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIread |
9ede109b 388 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift));
890e8d0a
FR		 389
390 return (u16) (SIS_R32(GMIIControl) >> EhnMIIdataShift);
391}
392
43afb949
FR		 393static void __mdio_write(struct net_device *dev, int phy_id, int reg, int val)
394{
395 struct sis190_private *tp = netdev_priv(dev);
396
9ede109b 397 mdio_write(tp->mmio_addr, phy_id, reg, val);
43afb949
FR		 398}
399
400static int __mdio_read(struct net_device *dev, int phy_id, int reg)
401{
402 struct sis190_private *tp = netdev_priv(dev);
403
9ede109b 404 return mdio_read(tp->mmio_addr, phy_id, reg);
43afb949
FR		 405}
406
fc10c39d
FR		 407static u16 mdio_read_latched(void __iomem *ioaddr, int phy_id, int reg)
408{
409 mdio_read(ioaddr, phy_id, reg);
410 return mdio_read(ioaddr, phy_id, reg);
411}
412
40292fb0 413static u16 __devinit sis190_read_eeprom(void __iomem *ioaddr, u32 reg)
890e8d0a 414{
40292fb0 415 u16 data = 0xffff;
890e8d0a 416 unsigned int i;
890e8d0a
FR		 417
418 if (!(SIS_R32(ROMControl) & 0x0002))
419 return 0;
420
40292fb0 421 SIS_W32(ROMInterface, EEREQ | EEROP | (reg << 10));
890e8d0a
FR		 422
423 for (i = 0; i < 200; i++) {
40292fb0
FR		 424 if (!(SIS_R32(ROMInterface) & EEREQ)) {
425 data = (SIS_R32(ROMInterface) & 0xffff0000) >> 16;
890e8d0a 426 break;
40292fb0 427 }
890e8d0a
FR		 428 msleep(1);
429 }
430
890e8d0a
FR		 431 return data;
432}
433
434static void sis190_irq_mask_and_ack(void __iomem *ioaddr)
435{
436 SIS_W32(IntrMask, 0x00);
437 SIS_W32(IntrStatus, 0xffffffff);
438 SIS_PCI_COMMIT();
439}
440
441static void sis190_asic_down(void __iomem *ioaddr)
442{
443 /* Stop the chip's Tx and Rx DMA processes. */
444
445 SIS_W32(TxControl, 0x1a00);
446 SIS_W32(RxControl, 0x1a00);
447
448 sis190_irq_mask_and_ack(ioaddr);
449}
450
451static void sis190_mark_as_last_descriptor(struct RxDesc *desc)
452{
453 desc->size |= cpu_to_le32(RingEnd);
454}
455
456static inline void sis190_give_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
457{
458 u32 eor = le32_to_cpu(desc->size) & RingEnd;
459
460 desc->PSize = 0x0;
8b5641d4 461 desc->size = cpu_to_le32((rx_buf_sz & RX_BUF_MASK) | eor);
890e8d0a
FR		 462 wmb();
463 desc->status = cpu_to_le32(OWNbit | INTbit);
464}
465
466static inline void sis190_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
467 u32 rx_buf_sz)
468{
469 desc->addr = cpu_to_le32(mapping);
470 sis190_give_to_asic(desc, rx_buf_sz);
471}
472
473static inline void sis190_make_unusable_by_asic(struct RxDesc *desc)
474{
475 desc->PSize = 0x0;
961994a0 476 desc->addr = cpu_to_le32(0xdeadbeef);
890e8d0a
FR		 477 desc->size &= cpu_to_le32(RingEnd);
478 wmb();
479 desc->status = 0x0;
480}
481
35aeb780
SH		 482static struct sk_buff *sis190_alloc_rx_skb(struct sis190_private *tp,
483 struct RxDesc *desc)
890e8d0a 484{
35aeb780 485 u32 rx_buf_sz = tp->rx_buf_sz;
890e8d0a 486 struct sk_buff *skb;
e382c301 487 dma_addr_t mapping;
890e8d0a 488
35aeb780 489 skb = netdev_alloc_skb(tp->dev, rx_buf_sz);
e382c301 490 if (unlikely(!skb))
491 goto skb_alloc_failed;
492 mapping = pci_map_single(tp->pci_dev, skb->data, tp->rx_buf_sz,
493 PCI_DMA_FROMDEVICE);
494 if (pci_dma_mapping_error(tp->pci_dev, mapping))
495 goto out;
496 sis190_map_to_asic(desc, mapping, rx_buf_sz);
890e8d0a 497
4709aa59 498 return skb;
e382c301 499
500out:
501 dev_kfree_skb_any(skb);
502skb_alloc_failed:
503 sis190_make_unusable_by_asic(desc);
504 return NULL;
890e8d0a
FR		 505}
506
507static u32 sis190_rx_fill(struct sis190_private *tp, struct net_device *dev,
508 u32 start, u32 end)
509{
510 u32 cur;
511
512 for (cur = start; cur < end; cur++) {
4709aa59 513 unsigned int i = cur % NUM_RX_DESC;
890e8d0a
FR		 514
515 if (tp->Rx_skbuff[i])
516 continue;
517
35aeb780
SH		 518 tp->Rx_skbuff[i] = sis190_alloc_rx_skb(tp, tp->RxDescRing + i);
519
4709aa59 520 if (!tp->Rx_skbuff[i])
890e8d0a
FR		 521 break;
522 }
523 return cur - start;
524}
525
47e47815
FR		 526static bool sis190_try_rx_copy(struct sis190_private *tp,
527 struct sk_buff **sk_buff, int pkt_size,
528 dma_addr_t addr)
890e8d0a 529{
47e47815
FR		 530 struct sk_buff *skb;
531 bool done = false;
532
533 if (pkt_size >= rx_copybreak)
534 goto out;
535
89d71a66 536 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
47e47815
FR		 537 if (!skb)
538 goto out;
539
744c6b29
RG		 540 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, tp->rx_buf_sz,
541 PCI_DMA_FROMDEVICE);
47e47815
FR		 542 skb_copy_to_linear_data(skb, sk_buff[0]->data, pkt_size);
543 *sk_buff = skb;
544 done = true;
545out:
546 return done;
890e8d0a
FR		 547}
548
bcad5e53
FR		 549static inline int sis190_rx_pkt_err(u32 status, struct net_device_stats *stats)
550{
551#define ErrMask (OVRUN | SHORT | LIMIT | MIIER | NIBON | COLON | ABORT)
552
553 if ((status & CRCOK) && !(status & ErrMask))
554 return 0;
555
556 if (!(status & CRCOK))
557 stats->rx_crc_errors++;
558 else if (status & OVRUN)
559 stats->rx_over_errors++;
560 else if (status & (SHORT | LIMIT))
561 stats->rx_length_errors++;
562 else if (status & (MIIER | NIBON | COLON))
563 stats->rx_frame_errors++;
564
565 stats->rx_errors++;
566 return -1;
567}
568
890e8d0a
FR		 569static int sis190_rx_interrupt(struct net_device *dev,
570 struct sis190_private *tp, void __iomem *ioaddr)
571{
09f75cd7 572 struct net_device_stats *stats = &dev->stats;
890e8d0a
FR		 573 u32 rx_left, cur_rx = tp->cur_rx;
574 u32 delta, count;
575
576 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
577 rx_left = sis190_rx_quota(rx_left, (u32) dev->quota);
578
579 for (; rx_left > 0; rx_left--, cur_rx++) {
580 unsigned int entry = cur_rx % NUM_RX_DESC;
581 struct RxDesc *desc = tp->RxDescRing + entry;
582 u32 status;
583
961994a0 584 if (le32_to_cpu(desc->status) & OWNbit)
890e8d0a
FR		 585 break;
586
587 status = le32_to_cpu(desc->PSize);
588
ad06ab2a 589 //netif_info(tp, intr, dev, "Rx PSize = %08x\n", status);
890e8d0a 590
bcad5e53 591 if (sis190_rx_pkt_err(status, stats) < 0)
890e8d0a 592 sis190_give_to_asic(desc, tp->rx_buf_sz);
bcad5e53 593 else {
890e8d0a 594 struct sk_buff *skb = tp->Rx_skbuff[entry];
47e47815 595 dma_addr_t addr = le32_to_cpu(desc->addr);
890e8d0a 596 int pkt_size = (status & RxSizeMask) - 4;
47e47815 597 struct pci_dev *pdev = tp->pci_dev;
890e8d0a
FR		 598
599 if (unlikely(pkt_size > tp->rx_buf_sz)) {
ad06ab2a
JP		 600 netif_info(tp, intr, dev,
601 "(frag) status = %08x\n", status);
890e8d0a
FR		 602 stats->rx_dropped++;
603 stats->rx_length_errors++;
604 sis190_give_to_asic(desc, tp->rx_buf_sz);
605 continue;
606 }
607
890e8d0a 608
47e47815
FR		 609 if (sis190_try_rx_copy(tp, &skb, pkt_size, addr)) {
610 pci_dma_sync_single_for_device(pdev, addr,
611 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
612 sis190_give_to_asic(desc, tp->rx_buf_sz);
613 } else {
614 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
615 PCI_DMA_FROMDEVICE);
890e8d0a
FR		 616 tp->Rx_skbuff[entry] = NULL;
617 sis190_make_unusable_by_asic(desc);
618 }
619
890e8d0a
FR		 620 skb_put(skb, pkt_size);
621 skb->protocol = eth_type_trans(skb, dev);
622
623 sis190_rx_skb(skb);
624
890e8d0a 625 stats->rx_packets++;
bcad5e53
FR		 626 stats->rx_bytes += pkt_size;
627 if ((status & BCAST) == MCAST)
628 stats->multicast++;
890e8d0a
FR		 629 }
630 }
631 count = cur_rx - tp->cur_rx;
632 tp->cur_rx = cur_rx;
633
634 delta = sis190_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
ad06ab2a
JP		 635 if (!delta && count)
636 netif_info(tp, intr, dev, "no Rx buffer allocated\n");
890e8d0a
FR		 637 tp->dirty_rx += delta;
638
ad06ab2a
JP		 639 if ((tp->dirty_rx + NUM_RX_DESC) == tp->cur_rx)
640 netif_emerg(tp, intr, dev, "Rx buffers exhausted\n");
890e8d0a
FR		 641
642 return count;
643}
644
645static void sis190_unmap_tx_skb(struct pci_dev *pdev, struct sk_buff *skb,
646 struct TxDesc *desc)
647{
648 unsigned int len;
649
650 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
651
652 pci_unmap_single(pdev, le32_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
653
654 memset(desc, 0x00, sizeof(*desc));
655}
656
697c2696
FR		 657static inline int sis190_tx_pkt_err(u32 status, struct net_device_stats *stats)
658{
659#define TxErrMask (WND | TABRT | FIFO | LINK)
660
661 if (!unlikely(status & TxErrMask))
662 return 0;
663
664 if (status & WND)
665 stats->tx_window_errors++;
666 if (status & TABRT)
667 stats->tx_aborted_errors++;
668 if (status & FIFO)
669 stats->tx_fifo_errors++;
670 if (status & LINK)
671 stats->tx_carrier_errors++;
672
673 stats->tx_errors++;
674
675 return -1;
676}
677
890e8d0a
FR		 678static void sis190_tx_interrupt(struct net_device *dev,
679 struct sis190_private *tp, void __iomem *ioaddr)
680{
697c2696 681 struct net_device_stats *stats = &dev->stats;
890e8d0a
FR		 682 u32 pending, dirty_tx = tp->dirty_tx;
683 /*
684 * It would not be needed if queueing was allowed to be enabled
685 * again too early (hint: think preempt and unclocked smp systems).
686 */
687 unsigned int queue_stopped;
688
689 smp_rmb();
690 pending = tp->cur_tx - dirty_tx;
691 queue_stopped = (pending == NUM_TX_DESC);
692
693 for (; pending; pending--, dirty_tx++) {
694 unsigned int entry = dirty_tx % NUM_TX_DESC;
695 struct TxDesc *txd = tp->TxDescRing + entry;
697c2696 696 u32 status = le32_to_cpu(txd->status);
890e8d0a
FR		 697 struct sk_buff *skb;
698
697c2696 699 if (status & OWNbit)
890e8d0a
FR		 700 break;
701
702 skb = tp->Tx_skbuff[entry];
703
697c2696
FR		 704 if (likely(sis190_tx_pkt_err(status, stats) == 0)) {
705 stats->tx_packets++;
706 stats->tx_bytes += skb->len;
707 stats->collisions += ((status & ColCountMask) - 1);
708 }
890e8d0a
FR		 709
710 sis190_unmap_tx_skb(tp->pci_dev, skb, txd);
711 tp->Tx_skbuff[entry] = NULL;
712 dev_kfree_skb_irq(skb);
713 }
714
715 if (tp->dirty_tx != dirty_tx) {
716 tp->dirty_tx = dirty_tx;
717 smp_wmb();
718 if (queue_stopped)
719 netif_wake_queue(dev);
720 }
721}
722
723/*
724 * The interrupt handler does all of the Rx thread work and cleans up after
725 * the Tx thread.
726 */
7d12e780 727static irqreturn_t sis190_interrupt(int irq, void *__dev)
890e8d0a
FR		 728{
729 struct net_device *dev = __dev;
730 struct sis190_private *tp = netdev_priv(dev);
731 void __iomem *ioaddr = tp->mmio_addr;
732 unsigned int handled = 0;
733 u32 status;
734
735 status = SIS_R32(IntrStatus);
736
737 if ((status == 0xffffffff) || !status)
738 goto out;
739
740 handled = 1;
741
742 if (unlikely(!netif_running(dev))) {
743 sis190_asic_down(ioaddr);
744 goto out;
745 }
746
747 SIS_W32(IntrStatus, status);
748
ad06ab2a 749// netif_info(tp, intr, dev, "status = %08x\n", status);
890e8d0a
FR		 750
751 if (status & LinkChange) {
ad06ab2a 752 netif_info(tp, intr, dev, "link change\n");
890e8d0a
FR		 753 schedule_work(&tp->phy_task);
754 }
755
756 if (status & RxQInt)
757 sis190_rx_interrupt(dev, tp, ioaddr);
758
759 if (status & TxQ0Int)
760 sis190_tx_interrupt(dev, tp, ioaddr);
761out:
762 return IRQ_RETVAL(handled);
763}
764
4405d3b5
FR		 765#ifdef CONFIG_NET_POLL_CONTROLLER
766static void sis190_netpoll(struct net_device *dev)
767{
768 struct sis190_private *tp = netdev_priv(dev);
769 struct pci_dev *pdev = tp->pci_dev;
770
771 disable_irq(pdev->irq);
7d12e780 772 sis190_interrupt(pdev->irq, dev);
4405d3b5
FR		 773 enable_irq(pdev->irq);
774}
775#endif
776
890e8d0a
FR		 777static void sis190_free_rx_skb(struct sis190_private *tp,
778 struct sk_buff **sk_buff, struct RxDesc *desc)
779{
780 struct pci_dev *pdev = tp->pci_dev;
781
782 pci_unmap_single(pdev, le32_to_cpu(desc->addr), tp->rx_buf_sz,
783 PCI_DMA_FROMDEVICE);
784 dev_kfree_skb(*sk_buff);
785 *sk_buff = NULL;
786 sis190_make_unusable_by_asic(desc);
787}
788
789static void sis190_rx_clear(struct sis190_private *tp)
790{
791 unsigned int i;
792
793 for (i = 0; i < NUM_RX_DESC; i++) {
794 if (!tp->Rx_skbuff[i])
795 continue;
796 sis190_free_rx_skb(tp, tp->Rx_skbuff + i, tp->RxDescRing + i);
797 }
798}
799
800static void sis190_init_ring_indexes(struct sis190_private *tp)
801{
802 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
803}
804
805static int sis190_init_ring(struct net_device *dev)
806{
807 struct sis190_private *tp = netdev_priv(dev);
808
809 sis190_init_ring_indexes(tp);
810
811 memset(tp->Tx_skbuff, 0x0, NUM_TX_DESC * sizeof(struct sk_buff *));
812 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
813
814 if (sis190_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
815 goto err_rx_clear;
816
817 sis190_mark_as_last_descriptor(tp->RxDescRing + NUM_RX_DESC - 1);
818
819 return 0;
820
821err_rx_clear:
822 sis190_rx_clear(tp);
823 return -ENOMEM;
824}
825
826static void sis190_set_rx_mode(struct net_device *dev)
827{
828 struct sis190_private *tp = netdev_priv(dev);
829 void __iomem *ioaddr = tp->mmio_addr;
830 unsigned long flags;
831 u32 mc_filter[2]; /* Multicast hash filter */
832 u16 rx_mode;
833
834 if (dev->flags & IFF_PROMISC) {
890e8d0a
FR		 835 rx_mode =
836 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
837 AcceptAllPhys;
838 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 839 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
890e8d0a
FR		 840 (dev->flags & IFF_ALLMULTI)) {
841 /* Too many to filter perfectly -- accept all multicasts. */
842 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
843 mc_filter[1] = mc_filter[0] = 0xffffffff;
844 } else {
845 struct dev_mc_list *mclist;
890e8d0a
FR		 846
847 rx_mode = AcceptBroadcast | AcceptMyPhys;
848 mc_filter[1] = mc_filter[0] = 0;
5508590c 849 netdev_for_each_mc_addr(mclist, dev) {
890e8d0a 850 int bit_nr =
8fee5f51 851 ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3f;
890e8d0a
FR		 852 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
853 rx_mode |= AcceptMulticast;
854 }
855 }
856
857 spin_lock_irqsave(&tp->lock, flags);
858
859 SIS_W16(RxMacControl, rx_mode | 0x2);
860 SIS_W32(RxHashTable, mc_filter[0]);
861 SIS_W32(RxHashTable + 4, mc_filter[1]);
862
863 spin_unlock_irqrestore(&tp->lock, flags);
864}
865
866static void sis190_soft_reset(void __iomem *ioaddr)
867{
868 SIS_W32(IntrControl, 0x8000);
869 SIS_PCI_COMMIT();
890e8d0a
FR		 870 SIS_W32(IntrControl, 0x0);
871 sis190_asic_down(ioaddr);
890e8d0a
FR		 872}
873
874static void sis190_hw_start(struct net_device *dev)
875{
876 struct sis190_private *tp = netdev_priv(dev);
877 void __iomem *ioaddr = tp->mmio_addr;
878
879 sis190_soft_reset(ioaddr);
880
881 SIS_W32(TxDescStartAddr, tp->tx_dma);
882 SIS_W32(RxDescStartAddr, tp->rx_dma);
883
884 SIS_W32(IntrStatus, 0xffffffff);
885 SIS_W32(IntrMask, 0x0);
890e8d0a
FR		 886 SIS_W32(GMIIControl, 0x0);
887 SIS_W32(TxMacControl, 0x60);
888 SIS_W16(RxMacControl, 0x02);
889 SIS_W32(RxHashTable, 0x0);
890 SIS_W32(0x6c, 0x0);
188f23ba
FR		 891 SIS_W32(RxWolCtrl, 0x0);
892 SIS_W32(RxWolData, 0x0);
890e8d0a
FR		 893
894 SIS_PCI_COMMIT();
895
896 sis190_set_rx_mode(dev);
897
898 /* Enable all known interrupts by setting the interrupt mask. */
899 SIS_W32(IntrMask, sis190_intr_mask);
900
901 SIS_W32(TxControl, 0x1a00 | CmdTxEnb);
902 SIS_W32(RxControl, 0x1a1d);
903
904 netif_start_queue(dev);
905}
906
c4028958 907static void sis190_phy_task(struct work_struct *work)
890e8d0a 908{
c4028958
DH		 909 struct sis190_private *tp =
910 container_of(work, struct sis190_private, phy_task);
911 struct net_device *dev = tp->dev;
890e8d0a 912 void __iomem *ioaddr = tp->mmio_addr;
9ede109b 913 int phy_id = tp->mii_if.phy_id;
890e8d0a
FR		 914 u16 val;
915
43afb949
FR		 916 rtnl_lock();
917
c014f6c8
FR		 918 if (!netif_running(dev))
919 goto out_unlock;
920
9ede109b 921 val = mdio_read(ioaddr, phy_id, MII_BMCR);
890e8d0a
FR		 922 if (val & BMCR_RESET) {
923 // FIXME: needlessly high ? -- FR 02/07/2005
924 mod_timer(&tp->timer, jiffies + HZ/10);
fc10c39d
FR		 925 } else if (!(mdio_read_latched(ioaddr, phy_id, MII_BMSR) &
926 BMSR_ANEGCOMPLETE)) {
21461380 927 netif_carrier_off(dev);
ad06ab2a 928 netif_warn(tp, link, dev, "auto-negotiating...\n");
890e8d0a
FR		 929 mod_timer(&tp->timer, jiffies + SIS190_PHY_TIMEOUT);
930 } else {
931 /* Rejoice ! */
932 struct {
933 int val;
6614a6dc 934 u32 ctl;
890e8d0a 935 const char *msg;
890e8d0a 936 } reg31[] = {
1feede01 937 { LPA_1000FULL, 0x07000c00 | 0x00001000,
6614a6dc 938 "1000 Mbps Full Duplex" },
1feede01 939 { LPA_1000HALF, 0x07000c00,
6614a6dc
FR		 940 "1000 Mbps Half Duplex" },
941 { LPA_100FULL, 0x04000800 | 0x00001000,
942 "100 Mbps Full Duplex" },
943 { LPA_100HALF, 0x04000800,
944 "100 Mbps Half Duplex" },
945 { LPA_10FULL, 0x04000400 | 0x00001000,
946 "10 Mbps Full Duplex" },
947 { LPA_10HALF, 0x04000400,
948 "10 Mbps Half Duplex" },
949 { 0, 0x04000400, "unknown" }
1feede01
RG		 950 }, *p = NULL;
951 u16 adv, autoexp, gigadv, gigrec;
890e8d0a 952
9ede109b 953 val = mdio_read(ioaddr, phy_id, 0x1f);
ad06ab2a 954 netif_info(tp, link, dev, "mii ext = %04x\n", val);
890e8d0a 955
9ede109b 956 val = mdio_read(ioaddr, phy_id, MII_LPA);
8348b4db 957 adv = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
1feede01 958 autoexp = mdio_read(ioaddr, phy_id, MII_EXPANSION);
ad06ab2a
JP		 959 netif_info(tp, link, dev, "mii lpa=%04x adv=%04x exp=%04x\n",
960 val, adv, autoexp);
1feede01
RG		 961
962 if (val & LPA_NPAGE && autoexp & EXPANSION_NWAY) {
963 /* check for gigabit speed */
964 gigadv = mdio_read(ioaddr, phy_id, MII_CTRL1000);
965 gigrec = mdio_read(ioaddr, phy_id, MII_STAT1000);
966 val = (gigadv & (gigrec >> 2));
967 if (val & ADVERTISE_1000FULL)
968 p = reg31;
969 else if (val & ADVERTISE_1000HALF)
970 p = reg31 + 1;
971 }
972 if (!p) {
973 val &= adv;
890e8d0a 974
1feede01
RG		 975 for (p = reg31; p->val; p++) {
976 if ((val & p->val) == p->val)
977 break;
978 }
890e8d0a 979 }
6614a6dc
FR		 980
981 p->ctl |= SIS_R32(StationControl) & ~0x0f001c00;
982
c3d6f1f2
FR		 983 if ((tp->features & F_HAS_RGMII) &&
984 (tp->features & F_PHY_BCM5461)) {
985 // Set Tx Delay in RGMII mode.
986 mdio_write(ioaddr, phy_id, 0x18, 0xf1c7);
987 udelay(200);
988 mdio_write(ioaddr, phy_id, 0x1c, 0x8c00);
989 p->ctl |= 0x03000000;
990 }
991
6614a6dc
FR		 992 SIS_W32(StationControl, p->ctl);
993
c3d6f1f2
FR		 994 if (tp->features & F_HAS_RGMII) {
995 SIS_W32(RGDelay, 0x0441);
996 SIS_W32(RGDelay, 0x0440);
997 }
998
08326dbe
RG		 999 tp->negotiated_lpa = p->val;
1000
ad06ab2a 1001 netif_info(tp, link, dev, "link on %s mode\n", p->msg);
890e8d0a
FR		 1002 netif_carrier_on(dev);
1003 }
43afb949 1004
c014f6c8 1005out_unlock:
43afb949 1006 rtnl_unlock();
890e8d0a
FR		 1007}
1008
1009static void sis190_phy_timer(unsigned long __opaque)
1010{
1011 struct net_device *dev = (struct net_device *)__opaque;
1012 struct sis190_private *tp = netdev_priv(dev);
1013
1014 if (likely(netif_running(dev)))
1015 schedule_work(&tp->phy_task);
1016}
1017
1018static inline void sis190_delete_timer(struct net_device *dev)
1019{
1020 struct sis190_private *tp = netdev_priv(dev);
1021
1022 del_timer_sync(&tp->timer);
1023}
1024
1025static inline void sis190_request_timer(struct net_device *dev)
1026{
1027 struct sis190_private *tp = netdev_priv(dev);
1028 struct timer_list *timer = &tp->timer;
1029
1030 init_timer(timer);
1031 timer->expires = jiffies + SIS190_PHY_TIMEOUT;
1032 timer->data = (unsigned long)dev;
1033 timer->function = sis190_phy_timer;
1034 add_timer(timer);
1035}
1036
1037static void sis190_set_rxbufsize(struct sis190_private *tp,
1038 struct net_device *dev)
1039{
1040 unsigned int mtu = dev->mtu;
1041
1042 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
8b5641d4
FR		 1043 /* RxDesc->size has a licence to kill the lower bits */
1044 if (tp->rx_buf_sz & 0x07) {
1045 tp->rx_buf_sz += 8;
1046 tp->rx_buf_sz &= RX_BUF_MASK;
1047 }
890e8d0a
FR		 1048}
1049
1050static int sis190_open(struct net_device *dev)
1051{
1052 struct sis190_private *tp = netdev_priv(dev);
1053 struct pci_dev *pdev = tp->pci_dev;
1054 int rc = -ENOMEM;
1055
1056 sis190_set_rxbufsize(tp, dev);
1057
1058 /*
1059 * Rx and Tx descriptors need 256 bytes alignment.
1060 * pci_alloc_consistent() guarantees a stronger alignment.
1061 */
1062 tp->TxDescRing = pci_alloc_consistent(pdev, TX_RING_BYTES, &tp->tx_dma);
1063 if (!tp->TxDescRing)
1064 goto out;
1065
1066 tp->RxDescRing = pci_alloc_consistent(pdev, RX_RING_BYTES, &tp->rx_dma);
1067 if (!tp->RxDescRing)
1068 goto err_free_tx_0;
1069
1070 rc = sis190_init_ring(dev);
1071 if (rc < 0)
1072 goto err_free_rx_1;
1073
890e8d0a
FR		 1074 sis190_request_timer(dev);
1075
1fb9df5d 1076 rc = request_irq(dev->irq, sis190_interrupt, IRQF_SHARED, dev->name, dev);
890e8d0a
FR		 1077 if (rc < 0)
1078 goto err_release_timer_2;
1079
1080 sis190_hw_start(dev);
1081out:
1082 return rc;
1083
1084err_release_timer_2:
1085 sis190_delete_timer(dev);
1086 sis190_rx_clear(tp);
1087err_free_rx_1:
1088 pci_free_consistent(tp->pci_dev, RX_RING_BYTES, tp->RxDescRing,
1089 tp->rx_dma);
1090err_free_tx_0:
1091 pci_free_consistent(tp->pci_dev, TX_RING_BYTES, tp->TxDescRing,
1092 tp->tx_dma);
1093 goto out;
1094}
1095
1096static void sis190_tx_clear(struct sis190_private *tp)
1097{
1098 unsigned int i;
1099
1100 for (i = 0; i < NUM_TX_DESC; i++) {
1101 struct sk_buff *skb = tp->Tx_skbuff[i];
1102
1103 if (!skb)
1104 continue;
1105
1106 sis190_unmap_tx_skb(tp->pci_dev, skb, tp->TxDescRing + i);
1107 tp->Tx_skbuff[i] = NULL;
1108 dev_kfree_skb(skb);
1109
09f75cd7 1110 tp->dev->stats.tx_dropped++;
890e8d0a
FR		 1111 }
1112 tp->cur_tx = tp->dirty_tx = 0;
1113}
1114
1115static void sis190_down(struct net_device *dev)
1116{
1117 struct sis190_private *tp = netdev_priv(dev);
1118 void __iomem *ioaddr = tp->mmio_addr;
1119 unsigned int poll_locked = 0;
1120
1121 sis190_delete_timer(dev);
1122
1123 netif_stop_queue(dev);
1124
890e8d0a
FR		 1125 do {
1126 spin_lock_irq(&tp->lock);
1127
1128 sis190_asic_down(ioaddr);
1129
1130 spin_unlock_irq(&tp->lock);
1131
1132 synchronize_irq(dev->irq);
1133
bea3348e 1134 if (!poll_locked)
890e8d0a 1135 poll_locked++;
890e8d0a
FR		 1136
1137 synchronize_sched();
1138
1139 } while (SIS_R32(IntrMask));
1140
1141 sis190_tx_clear(tp);
1142 sis190_rx_clear(tp);
1143}
1144
1145static int sis190_close(struct net_device *dev)
1146{
1147 struct sis190_private *tp = netdev_priv(dev);
1148 struct pci_dev *pdev = tp->pci_dev;
1149
1150 sis190_down(dev);
1151
1152 free_irq(dev->irq, dev);
1153
890e8d0a
FR		 1154 pci_free_consistent(pdev, TX_RING_BYTES, tp->TxDescRing, tp->tx_dma);
1155 pci_free_consistent(pdev, RX_RING_BYTES, tp->RxDescRing, tp->rx_dma);
1156
1157 tp->TxDescRing = NULL;
1158 tp->RxDescRing = NULL;
1159
1160 return 0;
1161}
1162
61357325
SH		 1163static netdev_tx_t sis190_start_xmit(struct sk_buff *skb,
1164 struct net_device *dev)
890e8d0a
FR		 1165{
1166 struct sis190_private *tp = netdev_priv(dev);
1167 void __iomem *ioaddr = tp->mmio_addr;
1168 u32 len, entry, dirty_tx;
1169 struct TxDesc *desc;
1170 dma_addr_t mapping;
1171
1172 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 1173 if (skb_padto(skb, ETH_ZLEN)) {
09f75cd7 1174 dev->stats.tx_dropped++;
890e8d0a
FR		 1175 goto out;
1176 }
1177 len = ETH_ZLEN;
1178 } else {
1179 len = skb->len;
1180 }
1181
1182 entry = tp->cur_tx % NUM_TX_DESC;
1183 desc = tp->TxDescRing + entry;
1184
1185 if (unlikely(le32_to_cpu(desc->status) & OWNbit)) {
1186 netif_stop_queue(dev);
ad06ab2a
JP		 1187 netif_err(tp, tx_err, dev,
1188 "BUG! Tx Ring full when queue awake!\n");
890e8d0a
FR		 1189 return NETDEV_TX_BUSY;
1190 }
1191
1192 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
e382c301 1193 if (pci_dma_mapping_error(tp->pci_dev, mapping)) {
1194 netif_err(tp, tx_err, dev,
1195 "PCI mapping failed, dropping packet");
1196 return NETDEV_TX_BUSY;
1197 }
890e8d0a
FR		 1198
1199 tp->Tx_skbuff[entry] = skb;
1200
1201 desc->PSize = cpu_to_le32(len);
1202 desc->addr = cpu_to_le32(mapping);
1203
1204 desc->size = cpu_to_le32(len);
1205 if (entry == (NUM_TX_DESC - 1))
1206 desc->size |= cpu_to_le32(RingEnd);
1207
1208 wmb();
1209
1210 desc->status = cpu_to_le32(OWNbit | INTbit | DEFbit | CRCbit | PADbit);
08326dbe
RG		 1211 if (tp->negotiated_lpa & (LPA_1000HALF | LPA_100HALF | LPA_10HALF)) {
1212 /* Half Duplex */
1213 desc->status |= cpu_to_le32(COLEN | CRSEN | BKFEN);
1214 if (tp->negotiated_lpa & (LPA_1000HALF | LPA_1000FULL))
1215 desc->status |= cpu_to_le32(EXTEN | BSTEN); /* gigabit HD */
1216 }
890e8d0a
FR		 1217
1218 tp->cur_tx++;
1219
1220 smp_wmb();
1221
1222 SIS_W32(TxControl, 0x1a00 | CmdReset | CmdTxEnb);
1223
890e8d0a
FR		 1224 dirty_tx = tp->dirty_tx;
1225 if ((tp->cur_tx - NUM_TX_DESC) == dirty_tx) {
1226 netif_stop_queue(dev);
1227 smp_rmb();
1228 if (dirty_tx != tp->dirty_tx)
1229 netif_wake_queue(dev);
1230 }
1231out:
1232 return NETDEV_TX_OK;
1233}
1234
fcb9821d
FR		 1235static void sis190_free_phy(struct list_head *first_phy)
1236{
1237 struct sis190_phy *cur, *next;
1238
1239 list_for_each_entry_safe(cur, next, first_phy, list) {
1240 kfree(cur);
1241 }
1242}
1243
1244/**
1245 * sis190_default_phy - Select default PHY for sis190 mac.
1246 * @dev: the net device to probe for
1247 *
1248 * Select first detected PHY with link as default.
1249 * If no one is link on, select PHY whose types is HOME as default.
1250 * If HOME doesn't exist, select LAN.
1251 */
1252static u16 sis190_default_phy(struct net_device *dev)
1253{
1254 struct sis190_phy *phy, *phy_home, *phy_default, *phy_lan;
1255 struct sis190_private *tp = netdev_priv(dev);
1256 struct mii_if_info *mii_if = &tp->mii_if;
1257 void __iomem *ioaddr = tp->mmio_addr;
1258 u16 status;
1259
1260 phy_home = phy_default = phy_lan = NULL;
1261
1262 list_for_each_entry(phy, &tp->first_phy, list) {
1263 status = mdio_read_latched(ioaddr, phy->phy_id, MII_BMSR);
1264
1265 // Link ON & Not select default PHY & not ghost PHY.
1266 if ((status & BMSR_LSTATUS) &&
1267 !phy_default &&
1268 (phy->type != UNKNOWN)) {
1269 phy_default = phy;
1270 } else {
1271 status = mdio_read(ioaddr, phy->phy_id, MII_BMCR);
1272 mdio_write(ioaddr, phy->phy_id, MII_BMCR,
1273 status | BMCR_ANENABLE | BMCR_ISOLATE);
1274 if (phy->type == HOME)
1275 phy_home = phy;
1276 else if (phy->type == LAN)
1277 phy_lan = phy;
1278 }
1279 }
1280
1281 if (!phy_default) {
1282 if (phy_home)
1283 phy_default = phy_home;
1284 else if (phy_lan)
1285 phy_default = phy_lan;
1286 else
c2f3f3a2 1287 phy_default = list_first_entry(&tp->first_phy,
fcb9821d
FR		 1288 struct sis190_phy, list);
1289 }
1290
1291 if (mii_if->phy_id != phy_default->phy_id) {
1292 mii_if->phy_id = phy_default->phy_id;
ad06ab2a
JP		 1293 if (netif_msg_probe(tp))
1294 pr_info("%s: Using transceiver at address %d as default\n",
1295 pci_name(tp->pci_dev), mii_if->phy_id);
fcb9821d
FR		 1296 }
1297
1298 status = mdio_read(ioaddr, mii_if->phy_id, MII_BMCR);
1299 status &= (~BMCR_ISOLATE);
1300
1301 mdio_write(ioaddr, mii_if->phy_id, MII_BMCR, status);
1302 status = mdio_read_latched(ioaddr, mii_if->phy_id, MII_BMSR);
1303
1304 return status;
1305}
1306
1307static void sis190_init_phy(struct net_device *dev, struct sis190_private *tp,
1308 struct sis190_phy *phy, unsigned int phy_id,
1309 u16 mii_status)
1310{
1311 void __iomem *ioaddr = tp->mmio_addr;
1312 struct mii_chip_info *p;
1313
1314 INIT_LIST_HEAD(&phy->list);
1315 phy->status = mii_status;
1316 phy->phy_id = phy_id;
1317
1318 phy->id[0] = mdio_read(ioaddr, phy_id, MII_PHYSID1);
1319 phy->id[1] = mdio_read(ioaddr, phy_id, MII_PHYSID2);
1320
1321 for (p = mii_chip_table; p->type; p++) {
1322 if ((p->id[0] == phy->id[0]) &&
1323 (p->id[1] == (phy->id[1] & 0xfff0))) {
1324 break;
1325 }
1326 }
1327
1328 if (p->id[1]) {
1329 phy->type = (p->type == MIX) ?
1330 ((mii_status & (BMSR_100FULL | BMSR_100HALF)) ?
1331 LAN : HOME) : p->type;
900eb9d6 1332 tp->features |= p->feature;
ad06ab2a
JP		 1333 if (netif_msg_probe(tp))
1334 pr_info("%s: %s transceiver at address %d\n",
1335 pci_name(tp->pci_dev), p->name, phy_id);
c3223d24 1336 } else {
fcb9821d 1337 phy->type = UNKNOWN;
ad06ab2a
JP		 1338 if (netif_msg_probe(tp))
1339 pr_info("%s: unknown PHY 0x%x:0x%x transceiver at address %d\n",
1340 pci_name(tp->pci_dev),
1341 phy->id[0], (phy->id[1] & 0xfff0), phy_id);
c3223d24 1342 }
fcb9821d
FR		 1343}
1344
900eb9d6
FR		 1345static void sis190_mii_probe_88e1111_fixup(struct sis190_private *tp)
1346{
1347 if (tp->features & F_PHY_88E1111) {
1348 void __iomem *ioaddr = tp->mmio_addr;
1349 int phy_id = tp->mii_if.phy_id;
1350 u16 reg[2][2] = {
1351 { 0x808b, 0x0ce1 },
1352 { 0x808f, 0x0c60 }
1353 }, *p;
1354
1355 p = (tp->features & F_HAS_RGMII) ? reg[0] : reg[1];
1356
1357 mdio_write(ioaddr, phy_id, 0x1b, p[0]);
1358 udelay(200);
1359 mdio_write(ioaddr, phy_id, 0x14, p[1]);
1360 udelay(200);
1361 }
1362}
1363
fcb9821d
FR		 1364/**
1365 * sis190_mii_probe - Probe MII PHY for sis190
1366 * @dev: the net device to probe for
1367 *
1368 * Search for total of 32 possible mii phy addresses.
1369 * Identify and set current phy if found one,
1370 * return error if it failed to found.
1371 */
1372static int __devinit sis190_mii_probe(struct net_device *dev)
1373{
1374 struct sis190_private *tp = netdev_priv(dev);
1375 struct mii_if_info *mii_if = &tp->mii_if;
1376 void __iomem *ioaddr = tp->mmio_addr;
1377 int phy_id;
1378 int rc = 0;
1379
1380 INIT_LIST_HEAD(&tp->first_phy);
1381
1382 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1383 struct sis190_phy *phy;
1384 u16 status;
1385
1386 status = mdio_read_latched(ioaddr, phy_id, MII_BMSR);
1387
1388 // Try next mii if the current one is not accessible.
1389 if (status == 0xffff || status == 0x0000)
1390 continue;
1391
1392 phy = kmalloc(sizeof(*phy), GFP_KERNEL);
1393 if (!phy) {
1394 sis190_free_phy(&tp->first_phy);
1395 rc = -ENOMEM;
1396 goto out;
1397 }
1398
1399 sis190_init_phy(dev, tp, phy, phy_id, status);
1400
1401 list_add(&tp->first_phy, &phy->list);
1402 }
1403
1404 if (list_empty(&tp->first_phy)) {
ad06ab2a
JP		 1405 if (netif_msg_probe(tp))
1406 pr_info("%s: No MII transceivers found!\n",
1407 pci_name(tp->pci_dev));
fcb9821d
FR		 1408 rc = -EIO;
1409 goto out;
1410 }
1411
1412 /* Select default PHY for mac */
1413 sis190_default_phy(dev);
1414
900eb9d6
FR		 1415 sis190_mii_probe_88e1111_fixup(tp);
1416
fcb9821d
FR		 1417 mii_if->dev = dev;
1418 mii_if->mdio_read = __mdio_read;
1419 mii_if->mdio_write = __mdio_write;
1420 mii_if->phy_id_mask = PHY_ID_ANY;
1421 mii_if->reg_num_mask = MII_REG_ANY;
1422out:
1423 return rc;
1424}
1425
c2b75f0c 1426static void sis190_mii_remove(struct net_device *dev)
fcb9821d
FR		 1427{
1428 struct sis190_private *tp = netdev_priv(dev);
1429
1430 sis190_free_phy(&tp->first_phy);
1431}
1432
890e8d0a
FR		 1433static void sis190_release_board(struct pci_dev *pdev)
1434{
1435 struct net_device *dev = pci_get_drvdata(pdev);
1436 struct sis190_private *tp = netdev_priv(dev);
1437
1438 iounmap(tp->mmio_addr);
1439 pci_release_regions(pdev);
1440 pci_disable_device(pdev);
1441 free_netdev(dev);
1442}
1443
1444static struct net_device * __devinit sis190_init_board(struct pci_dev *pdev)
1445{
1446 struct sis190_private *tp;
1447 struct net_device *dev;
1448 void __iomem *ioaddr;
1449 int rc;
1450
1451 dev = alloc_etherdev(sizeof(*tp));
1452 if (!dev) {
ad06ab2a
JP		 1453 if (netif_msg_drv(&debug))
1454 pr_err("unable to alloc new ethernet\n");
890e8d0a
FR		 1455 rc = -ENOMEM;
1456 goto err_out_0;
1457 }
1458
890e8d0a
FR		 1459 SET_NETDEV_DEV(dev, &pdev->dev);
1460
1461 tp = netdev_priv(dev);
c4028958 1462 tp->dev = dev;
890e8d0a
FR		 1463 tp->msg_enable = netif_msg_init(debug.msg_enable, SIS190_MSG_DEFAULT);
1464
1465 rc = pci_enable_device(pdev);
1466 if (rc < 0) {
ad06ab2a
JP		 1467 if (netif_msg_probe(tp))
1468 pr_err("%s: enable failure\n", pci_name(pdev));
890e8d0a
FR		 1469 goto err_free_dev_1;
1470 }
1471
1472 rc = -ENODEV;
1473
1474 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
ad06ab2a
JP		 1475 if (netif_msg_probe(tp))
1476 pr_err("%s: region #0 is no MMIO resource\n",
1477 pci_name(pdev));
890e8d0a
FR		 1478 goto err_pci_disable_2;
1479 }
1480 if (pci_resource_len(pdev, 0) < SIS190_REGS_SIZE) {
ad06ab2a
JP		 1481 if (netif_msg_probe(tp))
1482 pr_err("%s: invalid PCI region size(s)\n",
1483 pci_name(pdev));
890e8d0a
FR		 1484 goto err_pci_disable_2;
1485 }
1486
1487 rc = pci_request_regions(pdev, DRV_NAME);
1488 if (rc < 0) {
ad06ab2a
JP		 1489 if (netif_msg_probe(tp))
1490 pr_err("%s: could not request regions\n",
1491 pci_name(pdev));
890e8d0a
FR		 1492 goto err_pci_disable_2;
1493 }
1494
284901a9 1495 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
890e8d0a 1496 if (rc < 0) {
ad06ab2a
JP		 1497 if (netif_msg_probe(tp))
1498 pr_err("%s: DMA configuration failed\n",
1499 pci_name(pdev));
890e8d0a
FR		 1500 goto err_free_res_3;
1501 }
1502
1503 pci_set_master(pdev);
1504
1505 ioaddr = ioremap(pci_resource_start(pdev, 0), SIS190_REGS_SIZE);
1506 if (!ioaddr) {
ad06ab2a
JP		 1507 if (netif_msg_probe(tp))
1508 pr_err("%s: cannot remap MMIO, aborting\n",
1509 pci_name(pdev));
890e8d0a
FR		 1510 rc = -EIO;
1511 goto err_free_res_3;
1512 }
1513
1514 tp->pci_dev = pdev;
1515 tp->mmio_addr = ioaddr;
1516
1517 sis190_irq_mask_and_ack(ioaddr);
1518
1519 sis190_soft_reset(ioaddr);
1520out:
1521 return dev;
1522
1523err_free_res_3:
1524 pci_release_regions(pdev);
1525err_pci_disable_2:
1526 pci_disable_device(pdev);
1527err_free_dev_1:
1528 free_netdev(dev);
1529err_out_0:
1530 dev = ERR_PTR(rc);
1531 goto out;
1532}
1533
1534static void sis190_tx_timeout(struct net_device *dev)
1535{
1536 struct sis190_private *tp = netdev_priv(dev);
1537 void __iomem *ioaddr = tp->mmio_addr;
1538 u8 tmp8;
1539
1540 /* Disable Tx, if not already */
1541 tmp8 = SIS_R8(TxControl);
1542 if (tmp8 & CmdTxEnb)
1543 SIS_W8(TxControl, tmp8 & ~CmdTxEnb);
1544
ad06ab2a
JP		 1545 netif_info(tp, tx_err, dev, "Transmit timeout, status %08x %08x\n",
1546 SIS_R32(TxControl), SIS_R32(TxSts));
188f23ba 1547
890e8d0a
FR		 1548 /* Disable interrupts by clearing the interrupt mask. */
1549 SIS_W32(IntrMask, 0x0000);
1550
1551 /* Stop a shared interrupt from scavenging while we are. */
1552 spin_lock_irq(&tp->lock);
1553 sis190_tx_clear(tp);
1554 spin_unlock_irq(&tp->lock);
1555
1556 /* ...and finally, reset everything. */
1557 sis190_hw_start(dev);
1558
1559 netif_wake_queue(dev);
1560}
1561
900eb9d6
FR		 1562static void sis190_set_rgmii(struct sis190_private *tp, u8 reg)
1563{
1564 tp->features |= (reg & 0x80) ? F_HAS_RGMII : 0;
1565}
1566
830fb7d2
FR		 1567static int __devinit sis190_get_mac_addr_from_eeprom(struct pci_dev *pdev,
1568 struct net_device *dev)
1569{
1570 struct sis190_private *tp = netdev_priv(dev);
1571 void __iomem *ioaddr = tp->mmio_addr;
1572 u16 sig;
1573 int i;
1574
ad06ab2a
JP		 1575 if (netif_msg_probe(tp))
1576 pr_info("%s: Read MAC address from EEPROM\n", pci_name(pdev));
830fb7d2
FR		 1577
1578 /* Check to see if there is a sane EEPROM */
1579 sig = (u16) sis190_read_eeprom(ioaddr, EEPROMSignature);
1580
1581 if ((sig == 0xffff) || (sig == 0x0000)) {
ad06ab2a
JP		 1582 if (netif_msg_probe(tp))
1583 pr_info("%s: Error EEPROM read %x\n",
1584 pci_name(pdev), sig);
830fb7d2
FR		 1585 return -EIO;
1586 }
1587
1588 /* Get MAC address from EEPROM */
1589 for (i = 0; i < MAC_ADDR_LEN / 2; i++) {
961994a0 1590 u16 w = sis190_read_eeprom(ioaddr, EEPROMMACAddr + i);
830fb7d2 1591
961994a0 1592 ((__le16 *)dev->dev_addr)[i] = cpu_to_le16(w);
830fb7d2
FR		 1593 }
1594
900eb9d6
FR		 1595 sis190_set_rgmii(tp, sis190_read_eeprom(ioaddr, EEPROMInfo));
1596
830fb7d2
FR		 1597 return 0;
1598}
1599
1600/**
ebc71647 1601 * sis190_get_mac_addr_from_apc - Get MAC address for SiS96x model
830fb7d2
FR		 1602 * @pdev: PCI device
1603 * @dev: network device to get address for
1604 *
ebc71647 1605 * SiS96x model, use APC CMOS RAM to store MAC address.
830fb7d2
FR		 1606 * APC CMOS RAM is accessed through ISA bridge.
1607 * MAC address is read into @net_dev->dev_addr.
1608 */
1609static int __devinit sis190_get_mac_addr_from_apc(struct pci_dev *pdev,
1610 struct net_device *dev)
1611{
ebc71647 1612 static const u16 __devinitdata ids[] = { 0x0965, 0x0966, 0x0968 };
830fb7d2
FR		 1613 struct sis190_private *tp = netdev_priv(dev);
1614 struct pci_dev *isa_bridge;
1615 u8 reg, tmp8;
ebc71647 1616 unsigned int i;
830fb7d2 1617
ad06ab2a
JP		 1618 if (netif_msg_probe(tp))
1619 pr_info("%s: Read MAC address from APC\n", pci_name(pdev));
830fb7d2 1620
ebc71647
FR		 1621 for (i = 0; i < ARRAY_SIZE(ids); i++) {
1622 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, ids[i], NULL);
1623 if (isa_bridge)
1624 break;
1625 }
8eb7ad68 1626
830fb7d2 1627 if (!isa_bridge) {
ad06ab2a
JP		 1628 if (netif_msg_probe(tp))
1629 pr_info("%s: Can not find ISA bridge\n",
1630 pci_name(pdev));
830fb7d2
FR		 1631 return -EIO;
1632 }
1633
1634 /* Enable port 78h & 79h to access APC Registers. */
1635 pci_read_config_byte(isa_bridge, 0x48, &tmp8);
1636 reg = (tmp8 & ~0x02);
1637 pci_write_config_byte(isa_bridge, 0x48, reg);
1638 udelay(50);
1639 pci_read_config_byte(isa_bridge, 0x48, &reg);
1640
1641 for (i = 0; i < MAC_ADDR_LEN; i++) {
1642 outb(0x9 + i, 0x78);
1643 dev->dev_addr[i] = inb(0x79);
1644 }
1645
1646 outb(0x12, 0x78);
1647 reg = inb(0x79);
1648
900eb9d6
FR		 1649 sis190_set_rgmii(tp, reg);
1650
830fb7d2
FR		 1651 /* Restore the value to ISA Bridge */
1652 pci_write_config_byte(isa_bridge, 0x48, tmp8);
1653 pci_dev_put(isa_bridge);
1654
1655 return 0;
1656}
1657
1658/**
1659 * sis190_init_rxfilter - Initialize the Rx filter
1660 * @dev: network device to initialize
1661 *
1662 * Set receive filter address to our MAC address
1663 * and enable packet filtering.
1664 */
1665static inline void sis190_init_rxfilter(struct net_device *dev)
1666{
1667 struct sis190_private *tp = netdev_priv(dev);
1668 void __iomem *ioaddr = tp->mmio_addr;
1669 u16 ctl;
1670 int i;
1671
1672 ctl = SIS_R16(RxMacControl);
1673 /*
1674 * Disable packet filtering before setting filter.
1675 * Note: SiS's driver writes 32 bits but RxMacControl is 16 bits
1676 * only and followed by RxMacAddr (6 bytes). Strange. -- FR
1677 */
1678 SIS_W16(RxMacControl, ctl & ~0x0f00);
1679
1680 for (i = 0; i < MAC_ADDR_LEN; i++)
1681 SIS_W8(RxMacAddr + i, dev->dev_addr[i]);
1682
1683 SIS_W16(RxMacControl, ctl);
1684 SIS_PCI_COMMIT();
1685}
1686
7d2e3cb7 1687static int __devinit sis190_get_mac_addr(struct pci_dev *pdev,
d785ad74 1688 struct net_device *dev)
830fb7d2 1689{
563e0ae0
FR		 1690 int rc;
1691
1692 rc = sis190_get_mac_addr_from_eeprom(pdev, dev);
1693 if (rc < 0) {
1694 u8 reg;
830fb7d2 1695
563e0ae0 1696 pci_read_config_byte(pdev, 0x73, &reg);
830fb7d2 1697
563e0ae0
FR		 1698 if (reg & 0x00000001)
1699 rc = sis190_get_mac_addr_from_apc(pdev, dev);
1700 }
1701 return rc;
830fb7d2
FR		 1702}
1703
890e8d0a
FR		 1704static void sis190_set_speed_auto(struct net_device *dev)
1705{
1706 struct sis190_private *tp = netdev_priv(dev);
1707 void __iomem *ioaddr = tp->mmio_addr;
9ede109b 1708 int phy_id = tp->mii_if.phy_id;
890e8d0a
FR		 1709 int val;
1710
ad06ab2a 1711 netif_info(tp, link, dev, "Enabling Auto-negotiation\n");
890e8d0a 1712
9ede109b 1713 val = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
890e8d0a
FR		 1714
1715 // Enable 10/100 Full/Half Mode, leave MII_ADVERTISE bit4:0
1716 // unchanged.
9ede109b 1717 mdio_write(ioaddr, phy_id, MII_ADVERTISE, (val & ADVERTISE_SLCT) |
890e8d0a
FR		 1718 ADVERTISE_100FULL | ADVERTISE_10FULL |
1719 ADVERTISE_100HALF | ADVERTISE_10HALF);
1720
1721 // Enable 1000 Full Mode.
9ede109b 1722 mdio_write(ioaddr, phy_id, MII_CTRL1000, ADVERTISE_1000FULL);
890e8d0a
FR		 1723
1724 // Enable auto-negotiation and restart auto-negotiation.
9ede109b 1725 mdio_write(ioaddr, phy_id, MII_BMCR,
890e8d0a
FR		 1726 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET);
1727}
1728
43afb949
FR		 1729static int sis190_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1730{
1731 struct sis190_private *tp = netdev_priv(dev);
1732
1733 return mii_ethtool_gset(&tp->mii_if, cmd);
1734}
1735
1736static int sis190_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1737{
1738 struct sis190_private *tp = netdev_priv(dev);
1739
1740 return mii_ethtool_sset(&tp->mii_if, cmd);
1741}
1742
890e8d0a
FR		 1743static void sis190_get_drvinfo(struct net_device *dev,
1744 struct ethtool_drvinfo *info)
1745{
1746 struct sis190_private *tp = netdev_priv(dev);
1747
1748 strcpy(info->driver, DRV_NAME);
1749 strcpy(info->version, DRV_VERSION);
1750 strcpy(info->bus_info, pci_name(tp->pci_dev));
1751}
1752
1753static int sis190_get_regs_len(struct net_device *dev)
1754{
1755 return SIS190_REGS_SIZE;
1756}
1757
1758static void sis190_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1759 void *p)
1760{
1761 struct sis190_private *tp = netdev_priv(dev);
1762 unsigned long flags;
1763
1764 if (regs->len > SIS190_REGS_SIZE)
1765 regs->len = SIS190_REGS_SIZE;
1766
1767 spin_lock_irqsave(&tp->lock, flags);
1768 memcpy_fromio(p, tp->mmio_addr, regs->len);
1769 spin_unlock_irqrestore(&tp->lock, flags);
1770}
1771
43afb949
FR		 1772static int sis190_nway_reset(struct net_device *dev)
1773{
1774 struct sis190_private *tp = netdev_priv(dev);
1775
1776 return mii_nway_restart(&tp->mii_if);
1777}
1778
890e8d0a
FR		 1779static u32 sis190_get_msglevel(struct net_device *dev)
1780{
1781 struct sis190_private *tp = netdev_priv(dev);
1782
1783 return tp->msg_enable;
1784}
1785
1786static void sis190_set_msglevel(struct net_device *dev, u32 value)
1787{
1788 struct sis190_private *tp = netdev_priv(dev);
1789
1790 tp->msg_enable = value;
1791}
1792
7282d491 1793static const struct ethtool_ops sis190_ethtool_ops = {
43afb949
FR		 1794 .get_settings = sis190_get_settings,
1795 .set_settings = sis190_set_settings,
890e8d0a
FR		 1796 .get_drvinfo = sis190_get_drvinfo,
1797 .get_regs_len = sis190_get_regs_len,
1798 .get_regs = sis190_get_regs,
1799 .get_link = ethtool_op_get_link,
1800 .get_msglevel = sis190_get_msglevel,
1801 .set_msglevel = sis190_set_msglevel,
43afb949 1802 .nway_reset = sis190_nway_reset,
890e8d0a
FR		 1803};
1804
43afb949
FR		 1805static int sis190_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1806{
1807 struct sis190_private *tp = netdev_priv(dev);
1808
1809 return !netif_running(dev) ? -EINVAL :
1810 generic_mii_ioctl(&tp->mii_if, if_mii(ifr), cmd, NULL);
1811}
1812
97488c5b
SH		 1813static const struct net_device_ops sis190_netdev_ops = {
1814 .ndo_open = sis190_open,
1815 .ndo_stop = sis190_close,
1816 .ndo_do_ioctl = sis190_ioctl,
1817 .ndo_start_xmit = sis190_start_xmit,
1818 .ndo_tx_timeout = sis190_tx_timeout,
1819 .ndo_set_multicast_list = sis190_set_rx_mode,
1820 .ndo_change_mtu = eth_change_mtu,
1821 .ndo_set_mac_address = eth_mac_addr,
1822 .ndo_validate_addr = eth_validate_addr,
1823#ifdef CONFIG_NET_POLL_CONTROLLER
1824 .ndo_poll_controller = sis190_netpoll,
1825#endif
1826};
1827
890e8d0a
FR		 1828static int __devinit sis190_init_one(struct pci_dev *pdev,
1829 const struct pci_device_id *ent)
1830{
1831 static int printed_version = 0;
1832 struct sis190_private *tp;
1833 struct net_device *dev;
1834 void __iomem *ioaddr;
830fb7d2 1835 int rc;
890e8d0a
FR		 1836
1837 if (!printed_version) {
ad06ab2a
JP		 1838 if (netif_msg_drv(&debug))
1839 pr_info(SIS190_DRIVER_NAME " loaded\n");
890e8d0a
FR		 1840 printed_version = 1;
1841 }
1842
1843 dev = sis190_init_board(pdev);
1844 if (IS_ERR(dev)) {
1845 rc = PTR_ERR(dev);
1846 goto out;
1847 }
1848
10487fbd
FR		 1849 pci_set_drvdata(pdev, dev);
1850
890e8d0a
FR		 1851 tp = netdev_priv(dev);
1852 ioaddr = tp->mmio_addr;
1853
830fb7d2
FR		 1854 rc = sis190_get_mac_addr(pdev, dev);
1855 if (rc < 0)
1856 goto err_release_board;
890e8d0a 1857
830fb7d2 1858 sis190_init_rxfilter(dev);
890e8d0a 1859
c4028958 1860 INIT_WORK(&tp->phy_task, sis190_phy_task);
890e8d0a 1861
97488c5b
SH		 1862 dev->netdev_ops = &sis190_netdev_ops;
1863
890e8d0a
FR		 1864 SET_ETHTOOL_OPS(dev, &sis190_ethtool_ops);
1865 dev->irq = pdev->irq;
1866 dev->base_addr = (unsigned long) 0xdead;
97488c5b 1867 dev->watchdog_timeo = SIS190_TX_TIMEOUT;
890e8d0a
FR		 1868
1869 spin_lock_init(&tp->lock);
3690b6c1
FR		 1870
1871 rc = sis190_mii_probe(dev);
830fb7d2
FR		 1872 if (rc < 0)
1873 goto err_release_board;
890e8d0a 1874
3690b6c1 1875 rc = register_netdev(dev);
fcb9821d 1876 if (rc < 0)
3690b6c1
FR		 1877 goto err_remove_mii;
1878
ad06ab2a
JP		 1879 if (netif_msg_probe(tp)) {
1880 netdev_info(dev, "%s: %s at %p (IRQ: %d), %pM\n",
1881 pci_name(pdev),
1882 sis_chip_info[ent->driver_data].name,
1883 ioaddr, dev->irq, dev->dev_addr);
1884 netdev_info(dev, "%s mode.\n",
1885 (tp->features & F_HAS_RGMII) ? "RGMII" : "GMII");
1886 }
900eb9d6 1887
890e8d0a
FR		 1888 netif_carrier_off(dev);
1889
1890 sis190_set_speed_auto(dev);
1891out:
1892 return rc;
830fb7d2 1893
3690b6c1
FR		 1894err_remove_mii:
1895 sis190_mii_remove(dev);
830fb7d2
FR		 1896err_release_board:
1897 sis190_release_board(pdev);
1898 goto out;
890e8d0a
FR		 1899}
1900
1901static void __devexit sis190_remove_one(struct pci_dev *pdev)
1902{
1903 struct net_device *dev = pci_get_drvdata(pdev);
1904
fcb9821d 1905 sis190_mii_remove(dev);
c014f6c8 1906 flush_scheduled_work();
890e8d0a
FR		 1907 unregister_netdev(dev);
1908 sis190_release_board(pdev);
1909 pci_set_drvdata(pdev, NULL);
1910}
1911
1912static struct pci_driver sis190_pci_driver = {
1913 .name = DRV_NAME,
1914 .id_table = sis190_pci_tbl,
1915 .probe = sis190_init_one,
1916 .remove = __devexit_p(sis190_remove_one),
1917};
1918
1919static int __init sis190_init_module(void)
1920{
29917620 1921 return pci_register_driver(&sis190_pci_driver);
890e8d0a
FR		 1922}
1923
1924static void __exit sis190_cleanup_module(void)
1925{
1926 pci_unregister_driver(&sis190_pci_driver);
1927}
1928
1929module_init(sis190_init_module);
1930module_exit(sis190_cleanup_module);
Linux kernel - Deliverables
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