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Merge branches 'kbuild', 'packaging' and 'misc' of git://git.kernel.org/pub/scm/linux...
[deliverable/linux.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
798b6b19 14 * the Free Software Foundation; either version 2 of the License.
baef58b1
SH		 15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
f15063cd
JP		 26#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27
14c85021 28#include <linux/in.h>
baef58b1
SH		 29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/moduleparam.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/pci.h>
36#include <linux/if_vlan.h>
37#include <linux/ip.h>
38#include <linux/delay.h>
39#include <linux/crc32.h>
4075400b 40#include <linux/dma-mapping.h>
678aa1f6 41#include <linux/debugfs.h>
d43c36dc 42#include <linux/sched.h>
678aa1f6 43#include <linux/seq_file.h>
2cd8e5d3 44#include <linux/mii.h>
5a0e3ad6 45#include <linux/slab.h>
392bd0cb 46#include <linux/dmi.h>
70c71606 47#include <linux/prefetch.h>
baef58b1
SH		 48#include <asm/irq.h>
49
50#include "skge.h"
51
52#define DRV_NAME "skge"
5a9d6917 53#define DRV_VERSION "1.14"
baef58b1
SH		 54
55#define DEFAULT_TX_RING_SIZE 128
56#define DEFAULT_RX_RING_SIZE 512
57#define MAX_TX_RING_SIZE 1024
9db96479 58#define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
baef58b1 59#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 60#define RX_COPY_THRESHOLD 128
61#define RX_BUF_SIZE 1536
baef58b1
SH		 62#define PHY_RETRIES 1000
63#define ETH_JUMBO_MTU 9000
64#define TX_WATCHDOG (5 * HZ)
65#define NAPI_WEIGHT 64
6abebb53 66#define BLINK_MS 250
501fb72d 67#define LINK_HZ HZ
baef58b1 68
afa151b9
SH		 69#define SKGE_EEPROM_MAGIC 0x9933aabb
70
71
baef58b1 72MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
65ebe634 73MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
baef58b1
SH		 74MODULE_LICENSE("GPL");
75MODULE_VERSION(DRV_VERSION);
76
67777f9b
JP		 77static const u32 default_msg = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
78 NETIF_MSG_LINK | NETIF_MSG_IFUP |
79 NETIF_MSG_IFDOWN);
baef58b1
SH		 80
81static int debug = -1; /* defaults above */
82module_param(debug, int, 0);
83MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
84
a3aa1884 85static DEFINE_PCI_DEVICE_TABLE(skge_id_table) = {
6f7d32f4 86 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x1700) }, /* 3Com 3C940 */
87 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x80EB) }, /* 3Com 3C940B */
57d6fa37 88#ifdef CONFIG_SKGE_GENESIS
89 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4300) }, /* SK-9xx */
90#endif
6f7d32f4 91 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4320) }, /* SK-98xx V2.0 */
92 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* D-Link DGE-530T (rev.B) */
93 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4c00) }, /* D-Link DGE-530T */
c074304c 94 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302) }, /* D-Link DGE-530T Rev C1 */
6f7d32f4 95 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) }, /* Marvell Yukon 88E8001/8003/8010 */
96 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
97 { PCI_DEVICE(PCI_VENDOR_ID_CNET, 0x434E) }, /* CNet PowerG-2000 */
98 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, 0x1064) }, /* Linksys EG1064 v2 */
99 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 }, /* Linksys EG1032 v2 */
baef58b1
SH		 100 { 0 }
101};
102MODULE_DEVICE_TABLE(pci, skge_id_table);
103
104static int skge_up(struct net_device *dev);
105static int skge_down(struct net_device *dev);
ee294dcd 106static void skge_phy_reset(struct skge_port *skge);
513f533e 107static void skge_tx_clean(struct net_device *dev);
2cd8e5d3
SH		 108static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
109static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 110static void genesis_get_stats(struct skge_port *skge, u64 *data);
111static void yukon_get_stats(struct skge_port *skge, u64 *data);
112static void yukon_init(struct skge_hw *hw, int port);
baef58b1 113static void genesis_mac_init(struct skge_hw *hw, int port);
45bada65 114static void genesis_link_up(struct skge_port *skge);
f80d032b 115static void skge_set_multicast(struct net_device *dev);
baef58b1 116
7e676d91 117/* Avoid conditionals by using array */
baef58b1
SH		 118static const int txqaddr[] = { Q_XA1, Q_XA2 };
119static const int rxqaddr[] = { Q_R1, Q_R2 };
120static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
121static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
4ebabfcb
SH		 122static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
123static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
baef58b1 124
57d6fa37 125static inline bool is_genesis(const struct skge_hw *hw)
126{
127#ifdef CONFIG_SKGE_GENESIS
128 return hw->chip_id == CHIP_ID_GENESIS;
129#else
130 return false;
131#endif
132}
133
baef58b1
SH		 134static int skge_get_regs_len(struct net_device *dev)
135{
c3f8be96 136 return 0x4000;
baef58b1
SH		 137}
138
139/*
c3f8be96
SH		 140 * Returns copy of whole control register region
141 * Note: skip RAM address register because accessing it will
142 * cause bus hangs!
baef58b1
SH		 143 */
144static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
145 void *p)
146{
147 const struct skge_port *skge = netdev_priv(dev);
baef58b1 148 const void __iomem *io = skge->hw->regs;
baef58b1
SH		 149
150 regs->version = 1;
c3f8be96
SH		 151 memset(p, 0, regs->len);
152 memcpy_fromio(p, io, B3_RAM_ADDR);
baef58b1 153
c3f8be96
SH		 154 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
155 regs->len - B3_RI_WTO_R1);
baef58b1
SH		 156}
157
8f3f8193 158/* Wake on Lan only supported on Yukon chips with rev 1 or above */
a504e64a 159static u32 wol_supported(const struct skge_hw *hw)
baef58b1 160{
57d6fa37 161 if (is_genesis(hw))
a504e64a 162 return 0;
d17ecb23
SH		 163
164 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
165 return 0;
166
167 return WAKE_MAGIC | WAKE_PHY;
a504e64a
SH		 168}
169
a504e64a
SH		 170static void skge_wol_init(struct skge_port *skge)
171{
172 struct skge_hw *hw = skge->hw;
173 int port = skge->port;
692412b3 174 u16 ctrl;
a504e64a 175
a504e64a
SH		 176 skge_write16(hw, B0_CTST, CS_RST_CLR);
177 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
178
692412b3
SH		 179 /* Turn on Vaux */
180 skge_write8(hw, B0_POWER_CTRL,
181 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
a504e64a 182
692412b3
SH		 183 /* WA code for COMA mode -- clear PHY reset */
184 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
185 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
186 u32 reg = skge_read32(hw, B2_GP_IO);
187 reg |= GP_DIR_9;
188 reg &= ~GP_IO_9;
189 skge_write32(hw, B2_GP_IO, reg);
190 }
a504e64a 191
692412b3
SH		 192 skge_write32(hw, SK_REG(port, GPHY_CTRL),
193 GPC_DIS_SLEEP |
194 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
195 GPC_ANEG_1 | GPC_RST_SET);
a504e64a 196
692412b3
SH		 197 skge_write32(hw, SK_REG(port, GPHY_CTRL),
198 GPC_DIS_SLEEP |
199 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
200 GPC_ANEG_1 | GPC_RST_CLR);
201
202 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
203
204 /* Force to 10/100 skge_reset will re-enable on resume */
205 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
67777f9b
JP		 206 (PHY_AN_100FULL | PHY_AN_100HALF |
207 PHY_AN_10FULL | PHY_AN_10HALF | PHY_AN_CSMA));
692412b3
SH		 208 /* no 1000 HD/FD */
209 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
210 gm_phy_write(hw, port, PHY_MARV_CTRL,
211 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
212 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
a504e64a 213
a504e64a
SH		 214
215 /* Set GMAC to no flow control and auto update for speed/duplex */
216 gma_write16(hw, port, GM_GP_CTRL,
217 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
218 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
219
220 /* Set WOL address */
221 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
222 skge->netdev->dev_addr, ETH_ALEN);
223
224 /* Turn on appropriate WOL control bits */
225 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
226 ctrl = 0;
227 if (skge->wol & WAKE_PHY)
228 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
229 else
230 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
231
232 if (skge->wol & WAKE_MAGIC)
233 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
234 else
a419aef8 235 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
a504e64a
SH		 236
237 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
238 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
239
240 /* block receiver */
241 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 242}
243
244static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
245{
246 struct skge_port *skge = netdev_priv(dev);
247
a504e64a
SH		 248 wol->supported = wol_supported(skge->hw);
249 wol->wolopts = skge->wol;
baef58b1
SH		 250}
251
252static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
253{
254 struct skge_port *skge = netdev_priv(dev);
255 struct skge_hw *hw = skge->hw;
256
8e95a202
JP		 257 if ((wol->wolopts & ~wol_supported(hw)) ||
258 !device_can_wakeup(&hw->pdev->dev))
baef58b1
SH		 259 return -EOPNOTSUPP;
260
a504e64a 261 skge->wol = wol->wolopts;
5177b324
RW		 262
263 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
264
baef58b1
SH		 265 return 0;
266}
267
8f3f8193
SH		 268/* Determine supported/advertised modes based on hardware.
269 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
31b619c5
SH		 270 */
271static u32 skge_supported_modes(const struct skge_hw *hw)
272{
273 u32 supported;
274
5e1705dd 275 if (hw->copper) {
67777f9b
JP		 276 supported = (SUPPORTED_10baseT_Half |
277 SUPPORTED_10baseT_Full |
278 SUPPORTED_100baseT_Half |
279 SUPPORTED_100baseT_Full |
280 SUPPORTED_1000baseT_Half |
281 SUPPORTED_1000baseT_Full |
282 SUPPORTED_Autoneg |
283 SUPPORTED_TP);
31b619c5 284
57d6fa37 285 if (is_genesis(hw))
67777f9b
JP		 286 supported &= ~(SUPPORTED_10baseT_Half |
287 SUPPORTED_10baseT_Full |
288 SUPPORTED_100baseT_Half |
289 SUPPORTED_100baseT_Full);
31b619c5
SH		 290
291 else if (hw->chip_id == CHIP_ID_YUKON)
292 supported &= ~SUPPORTED_1000baseT_Half;
293 } else
67777f9b
JP		 294 supported = (SUPPORTED_1000baseT_Full |
295 SUPPORTED_1000baseT_Half |
296 SUPPORTED_FIBRE |
297 SUPPORTED_Autoneg);
31b619c5
SH		 298
299 return supported;
300}
baef58b1
SH		 301
302static int skge_get_settings(struct net_device *dev,
303 struct ethtool_cmd *ecmd)
304{
305 struct skge_port *skge = netdev_priv(dev);
306 struct skge_hw *hw = skge->hw;
307
308 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 309 ecmd->supported = skge_supported_modes(hw);
baef58b1 310
5e1705dd 311 if (hw->copper) {
baef58b1
SH		 312 ecmd->port = PORT_TP;
313 ecmd->phy_address = hw->phy_addr;
31b619c5 314 } else
baef58b1 315 ecmd->port = PORT_FIBRE;
baef58b1
SH		 316
317 ecmd->advertising = skge->advertising;
318 ecmd->autoneg = skge->autoneg;
70739497 319 ethtool_cmd_speed_set(ecmd, skge->speed);
baef58b1
SH		 320 ecmd->duplex = skge->duplex;
321 return 0;
322}
323
baef58b1
SH		 324static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
325{
326 struct skge_port *skge = netdev_priv(dev);
327 const struct skge_hw *hw = skge->hw;
31b619c5 328 u32 supported = skge_supported_modes(hw);
9ac1353f 329 int err = 0;
baef58b1
SH		 330
331 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 332 ecmd->advertising = supported;
333 skge->duplex = -1;
334 skge->speed = -1;
baef58b1 335 } else {
31b619c5 336 u32 setting;
25db0338 337 u32 speed = ethtool_cmd_speed(ecmd);
31b619c5 338
25db0338 339 switch (speed) {
baef58b1 340 case SPEED_1000:
31b619c5
SH		 341 if (ecmd->duplex == DUPLEX_FULL)
342 setting = SUPPORTED_1000baseT_Full;
343 else if (ecmd->duplex == DUPLEX_HALF)
344 setting = SUPPORTED_1000baseT_Half;
345 else
346 return -EINVAL;
baef58b1
SH		 347 break;
348 case SPEED_100:
31b619c5
SH		 349 if (ecmd->duplex == DUPLEX_FULL)
350 setting = SUPPORTED_100baseT_Full;
351 else if (ecmd->duplex == DUPLEX_HALF)
352 setting = SUPPORTED_100baseT_Half;
353 else
354 return -EINVAL;
355 break;
356
baef58b1 357 case SPEED_10:
31b619c5
SH		 358 if (ecmd->duplex == DUPLEX_FULL)
359 setting = SUPPORTED_10baseT_Full;
360 else if (ecmd->duplex == DUPLEX_HALF)
361 setting = SUPPORTED_10baseT_Half;
362 else
baef58b1
SH		 363 return -EINVAL;
364 break;
365 default:
366 return -EINVAL;
367 }
31b619c5
SH		 368
369 if ((setting & supported) == 0)
370 return -EINVAL;
371
25db0338 372 skge->speed = speed;
31b619c5 373 skge->duplex = ecmd->duplex;
baef58b1
SH		 374 }
375
376 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 377 skge->advertising = ecmd->advertising;
378
9ac1353f
XZ		 379 if (netif_running(dev)) {
380 skge_down(dev);
381 err = skge_up(dev);
382 if (err) {
383 dev_close(dev);
384 return err;
385 }
386 }
ee294dcd 387
67777f9b 388 return 0;
baef58b1
SH		 389}
390
391static void skge_get_drvinfo(struct net_device *dev,
392 struct ethtool_drvinfo *info)
393{
394 struct skge_port *skge = netdev_priv(dev);
395
396 strcpy(info->driver, DRV_NAME);
397 strcpy(info->version, DRV_VERSION);
398 strcpy(info->fw_version, "N/A");
399 strcpy(info->bus_info, pci_name(skge->hw->pdev));
400}
401
402static const struct skge_stat {
403 char name[ETH_GSTRING_LEN];
404 u16 xmac_offset;
405 u16 gma_offset;
406} skge_stats[] = {
407 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
408 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
409
410 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
411 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
412 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
413 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
414 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
415 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
416 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
417 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
418
419 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
420 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
421 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
422 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
423 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
424 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
425
426 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
427 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
428 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
429 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
430 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
431};
432
b9f2c044 433static int skge_get_sset_count(struct net_device *dev, int sset)
baef58b1 434{
b9f2c044
JG		 435 switch (sset) {
436 case ETH_SS_STATS:
437 return ARRAY_SIZE(skge_stats);
438 default:
439 return -EOPNOTSUPP;
440 }
baef58b1
SH		 441}
442
443static void skge_get_ethtool_stats(struct net_device *dev,
444 struct ethtool_stats *stats, u64 *data)
445{
446 struct skge_port *skge = netdev_priv(dev);
447
57d6fa37 448 if (is_genesis(skge->hw))
baef58b1
SH		 449 genesis_get_stats(skge, data);
450 else
451 yukon_get_stats(skge, data);
452}
453
454/* Use hardware MIB variables for critical path statistics and
455 * transmit feedback not reported at interrupt.
456 * Other errors are accounted for in interrupt handler.
457 */
458static struct net_device_stats *skge_get_stats(struct net_device *dev)
459{
460 struct skge_port *skge = netdev_priv(dev);
461 u64 data[ARRAY_SIZE(skge_stats)];
462
57d6fa37 463 if (is_genesis(skge->hw))
baef58b1
SH		 464 genesis_get_stats(skge, data);
465 else
466 yukon_get_stats(skge, data);
467
da00772f
SH		 468 dev->stats.tx_bytes = data[0];
469 dev->stats.rx_bytes = data[1];
470 dev->stats.tx_packets = data[2] + data[4] + data[6];
471 dev->stats.rx_packets = data[3] + data[5] + data[7];
472 dev->stats.multicast = data[3] + data[5];
473 dev->stats.collisions = data[10];
474 dev->stats.tx_aborted_errors = data[12];
baef58b1 475
da00772f 476 return &dev->stats;
baef58b1
SH		 477}
478
479static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
480{
481 int i;
482
95566065 483 switch (stringset) {
baef58b1
SH		 484 case ETH_SS_STATS:
485 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
486 memcpy(data + i * ETH_GSTRING_LEN,
487 skge_stats[i].name, ETH_GSTRING_LEN);
488 break;
489 }
490}
491
492static void skge_get_ring_param(struct net_device *dev,
493 struct ethtool_ringparam *p)
494{
495 struct skge_port *skge = netdev_priv(dev);
496
497 p->rx_max_pending = MAX_RX_RING_SIZE;
498 p->tx_max_pending = MAX_TX_RING_SIZE;
499 p->rx_mini_max_pending = 0;
500 p->rx_jumbo_max_pending = 0;
501
502 p->rx_pending = skge->rx_ring.count;
503 p->tx_pending = skge->tx_ring.count;
504 p->rx_mini_pending = 0;
505 p->rx_jumbo_pending = 0;
506}
507
508static int skge_set_ring_param(struct net_device *dev,
509 struct ethtool_ringparam *p)
510{
511 struct skge_port *skge = netdev_priv(dev);
e824b3eb 512 int err = 0;
baef58b1
SH		 513
514 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
9db96479 515 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
baef58b1
SH		 516 return -EINVAL;
517
518 skge->rx_ring.count = p->rx_pending;
519 skge->tx_ring.count = p->tx_pending;
520
521 if (netif_running(dev)) {
522 skge_down(dev);
3b8bb472
SH		 523 err = skge_up(dev);
524 if (err)
525 dev_close(dev);
baef58b1
SH		 526 }
527
e824b3eb 528 return err;
baef58b1
SH		 529}
530
531static u32 skge_get_msglevel(struct net_device *netdev)
532{
533 struct skge_port *skge = netdev_priv(netdev);
534 return skge->msg_enable;
535}
536
537static void skge_set_msglevel(struct net_device *netdev, u32 value)
538{
539 struct skge_port *skge = netdev_priv(netdev);
540 skge->msg_enable = value;
541}
542
543static int skge_nway_reset(struct net_device *dev)
544{
545 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 546
547 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
548 return -EINVAL;
549
ee294dcd 550 skge_phy_reset(skge);
baef58b1
SH		 551 return 0;
552}
553
baef58b1
SH		 554static void skge_get_pauseparam(struct net_device *dev,
555 struct ethtool_pauseparam *ecmd)
556{
557 struct skge_port *skge = netdev_priv(dev);
558
8e95a202
JP		 559 ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) ||
560 (skge->flow_control == FLOW_MODE_SYM_OR_REM));
561 ecmd->tx_pause = (ecmd->rx_pause ||
562 (skge->flow_control == FLOW_MODE_LOC_SEND));
baef58b1 563
5d5c8e03 564 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
baef58b1
SH		 565}
566
567static int skge_set_pauseparam(struct net_device *dev,
568 struct ethtool_pauseparam *ecmd)
569{
570 struct skge_port *skge = netdev_priv(dev);
5d5c8e03 571 struct ethtool_pauseparam old;
9ac1353f 572 int err = 0;
baef58b1 573
5d5c8e03
SH		 574 skge_get_pauseparam(dev, &old);
575
576 if (ecmd->autoneg != old.autoneg)
577 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
578 else {
579 if (ecmd->rx_pause && ecmd->tx_pause)
580 skge->flow_control = FLOW_MODE_SYMMETRIC;
581 else if (ecmd->rx_pause && !ecmd->tx_pause)
582 skge->flow_control = FLOW_MODE_SYM_OR_REM;
583 else if (!ecmd->rx_pause && ecmd->tx_pause)
584 skge->flow_control = FLOW_MODE_LOC_SEND;
585 else
586 skge->flow_control = FLOW_MODE_NONE;
587 }
baef58b1 588
9ac1353f
XZ		 589 if (netif_running(dev)) {
590 skge_down(dev);
591 err = skge_up(dev);
592 if (err) {
593 dev_close(dev);
594 return err;
595 }
596 }
5d5c8e03 597
baef58b1
SH		 598 return 0;
599}
600
601/* Chip internal frequency for clock calculations */
602static inline u32 hwkhz(const struct skge_hw *hw)
603{
57d6fa37 604 return is_genesis(hw) ? 53125 : 78125;
baef58b1
SH		 605}
606
8f3f8193 607/* Chip HZ to microseconds */
baef58b1
SH		 608static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
609{
610 return (ticks * 1000) / hwkhz(hw);
611}
612
8f3f8193 613/* Microseconds to chip HZ */
baef58b1
SH		 614static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
615{
616 return hwkhz(hw) * usec / 1000;
617}
618
619static int skge_get_coalesce(struct net_device *dev,
620 struct ethtool_coalesce *ecmd)
621{
622 struct skge_port *skge = netdev_priv(dev);
623 struct skge_hw *hw = skge->hw;
624 int port = skge->port;
625
626 ecmd->rx_coalesce_usecs = 0;
627 ecmd->tx_coalesce_usecs = 0;
628
629 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
630 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
631 u32 msk = skge_read32(hw, B2_IRQM_MSK);
632
633 if (msk & rxirqmask[port])
634 ecmd->rx_coalesce_usecs = delay;
635 if (msk & txirqmask[port])
636 ecmd->tx_coalesce_usecs = delay;
637 }
638
639 return 0;
640}
641
642/* Note: interrupt timer is per board, but can turn on/off per port */
643static int skge_set_coalesce(struct net_device *dev,
644 struct ethtool_coalesce *ecmd)
645{
646 struct skge_port *skge = netdev_priv(dev);
647 struct skge_hw *hw = skge->hw;
648 int port = skge->port;
649 u32 msk = skge_read32(hw, B2_IRQM_MSK);
650 u32 delay = 25;
651
652 if (ecmd->rx_coalesce_usecs == 0)
653 msk &= ~rxirqmask[port];
654 else if (ecmd->rx_coalesce_usecs < 25 ||
655 ecmd->rx_coalesce_usecs > 33333)
656 return -EINVAL;
657 else {
658 msk |= rxirqmask[port];
659 delay = ecmd->rx_coalesce_usecs;
660 }
661
662 if (ecmd->tx_coalesce_usecs == 0)
663 msk &= ~txirqmask[port];
664 else if (ecmd->tx_coalesce_usecs < 25 ||
665 ecmd->tx_coalesce_usecs > 33333)
666 return -EINVAL;
667 else {
668 msk |= txirqmask[port];
669 delay = min(delay, ecmd->rx_coalesce_usecs);
670 }
671
672 skge_write32(hw, B2_IRQM_MSK, msk);
673 if (msk == 0)
674 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
675 else {
676 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
677 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
678 }
679 return 0;
680}
681
6abebb53
SH		 682enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
683static void skge_led(struct skge_port *skge, enum led_mode mode)
baef58b1 684{
6abebb53
SH		 685 struct skge_hw *hw = skge->hw;
686 int port = skge->port;
687
9cbe330f 688 spin_lock_bh(&hw->phy_lock);
57d6fa37 689 if (is_genesis(hw)) {
6abebb53
SH		 690 switch (mode) {
691 case LED_MODE_OFF:
64f6b64d
SH		 692 if (hw->phy_type == SK_PHY_BCOM)
693 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
694 else {
695 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
696 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
697 }
6abebb53
SH		 698 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
699 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
700 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
701 break;
baef58b1 702
6abebb53
SH		 703 case LED_MODE_ON:
704 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
705 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 706
6abebb53
SH		 707 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
708 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1 709
6abebb53 710 break;
baef58b1 711
6abebb53
SH		 712 case LED_MODE_TST:
713 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
714 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
715 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 716
64f6b64d
SH		 717 if (hw->phy_type == SK_PHY_BCOM)
718 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
719 else {
720 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
721 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
722 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
723 }
724
6abebb53 725 }
baef58b1 726 } else {
6abebb53
SH		 727 switch (mode) {
728 case LED_MODE_OFF:
729 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
730 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
731 PHY_M_LED_MO_DUP(MO_LED_OFF) |
732 PHY_M_LED_MO_10(MO_LED_OFF) |
733 PHY_M_LED_MO_100(MO_LED_OFF) |
734 PHY_M_LED_MO_1000(MO_LED_OFF) |
735 PHY_M_LED_MO_RX(MO_LED_OFF));
736 break;
737 case LED_MODE_ON:
738 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
739 PHY_M_LED_PULS_DUR(PULS_170MS) |
740 PHY_M_LED_BLINK_RT(BLINK_84MS) |
741 PHY_M_LEDC_TX_CTRL |
742 PHY_M_LEDC_DP_CTRL);
46a60f2d 743
6abebb53
SH		 744 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
745 PHY_M_LED_MO_RX(MO_LED_OFF) |
746 (skge->speed == SPEED_100 ?
747 PHY_M_LED_MO_100(MO_LED_ON) : 0));
748 break;
749 case LED_MODE_TST:
750 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
751 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
752 PHY_M_LED_MO_DUP(MO_LED_ON) |
753 PHY_M_LED_MO_10(MO_LED_ON) |
754 PHY_M_LED_MO_100(MO_LED_ON) |
755 PHY_M_LED_MO_1000(MO_LED_ON) |
756 PHY_M_LED_MO_RX(MO_LED_ON));
757 }
baef58b1 758 }
9cbe330f 759 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 760}
761
762/* blink LED's for finding board */
a5b9f41c 763static int skge_set_phys_id(struct net_device *dev,
764 enum ethtool_phys_id_state state)
baef58b1
SH		 765{
766 struct skge_port *skge = netdev_priv(dev);
767
a5b9f41c 768 switch (state) {
769 case ETHTOOL_ID_ACTIVE:
fce55922 770 return 2; /* cycle on/off twice per second */
baef58b1 771
a5b9f41c 772 case ETHTOOL_ID_ON:
773 skge_led(skge, LED_MODE_TST);
774 break;
baef58b1 775
a5b9f41c 776 case ETHTOOL_ID_OFF:
777 skge_led(skge, LED_MODE_OFF);
778 break;
baef58b1 779
a5b9f41c 780 case ETHTOOL_ID_INACTIVE:
781 /* back to regular LED state */
782 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
783 }
baef58b1
SH		 784
785 return 0;
786}
787
afa151b9
SH		 788static int skge_get_eeprom_len(struct net_device *dev)
789{
790 struct skge_port *skge = netdev_priv(dev);
791 u32 reg2;
792
793 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, &reg2);
67777f9b 794 return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
afa151b9
SH		 795}
796
797static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
798{
799 u32 val;
800
801 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
802
803 do {
804 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
805 } while (!(offset & PCI_VPD_ADDR_F));
806
807 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
808 return val;
809}
810
811static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
812{
813 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
814 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
815 offset | PCI_VPD_ADDR_F);
816
817 do {
818 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
819 } while (offset & PCI_VPD_ADDR_F);
820}
821
822static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
823 u8 *data)
824{
825 struct skge_port *skge = netdev_priv(dev);
826 struct pci_dev *pdev = skge->hw->pdev;
827 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
828 int length = eeprom->len;
829 u16 offset = eeprom->offset;
830
831 if (!cap)
832 return -EINVAL;
833
834 eeprom->magic = SKGE_EEPROM_MAGIC;
835
836 while (length > 0) {
837 u32 val = skge_vpd_read(pdev, cap, offset);
838 int n = min_t(int, length, sizeof(val));
839
840 memcpy(data, &val, n);
841 length -= n;
842 data += n;
843 offset += n;
844 }
845 return 0;
846}
847
848static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
849 u8 *data)
850{
851 struct skge_port *skge = netdev_priv(dev);
852 struct pci_dev *pdev = skge->hw->pdev;
853 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
854 int length = eeprom->len;
855 u16 offset = eeprom->offset;
856
857 if (!cap)
858 return -EINVAL;
859
860 if (eeprom->magic != SKGE_EEPROM_MAGIC)
861 return -EINVAL;
862
863 while (length > 0) {
864 u32 val;
865 int n = min_t(int, length, sizeof(val));
866
867 if (n < sizeof(val))
868 val = skge_vpd_read(pdev, cap, offset);
869 memcpy(&val, data, n);
870
871 skge_vpd_write(pdev, cap, offset, val);
872
873 length -= n;
874 data += n;
875 offset += n;
876 }
877 return 0;
878}
879
7282d491 880static const struct ethtool_ops skge_ethtool_ops = {
baef58b1
SH		 881 .get_settings = skge_get_settings,
882 .set_settings = skge_set_settings,
883 .get_drvinfo = skge_get_drvinfo,
884 .get_regs_len = skge_get_regs_len,
885 .get_regs = skge_get_regs,
886 .get_wol = skge_get_wol,
887 .set_wol = skge_set_wol,
888 .get_msglevel = skge_get_msglevel,
889 .set_msglevel = skge_set_msglevel,
890 .nway_reset = skge_nway_reset,
891 .get_link = ethtool_op_get_link,
afa151b9
SH		 892 .get_eeprom_len = skge_get_eeprom_len,
893 .get_eeprom = skge_get_eeprom,
894 .set_eeprom = skge_set_eeprom,
baef58b1
SH		 895 .get_ringparam = skge_get_ring_param,
896 .set_ringparam = skge_set_ring_param,
897 .get_pauseparam = skge_get_pauseparam,
898 .set_pauseparam = skge_set_pauseparam,
899 .get_coalesce = skge_get_coalesce,
900 .set_coalesce = skge_set_coalesce,
baef58b1 901 .get_strings = skge_get_strings,
a5b9f41c 902 .set_phys_id = skge_set_phys_id,
b9f2c044 903 .get_sset_count = skge_get_sset_count,
baef58b1
SH		 904 .get_ethtool_stats = skge_get_ethtool_stats,
905};
906
907/*
908 * Allocate ring elements and chain them together
909 * One-to-one association of board descriptors with ring elements
910 */
c3da1447 911static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
baef58b1
SH		 912{
913 struct skge_tx_desc *d;
914 struct skge_element *e;
915 int i;
916
cd861280 917 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
baef58b1
SH		 918 if (!ring->start)
919 return -ENOMEM;
920
921 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
922 e->desc = d;
923 if (i == ring->count - 1) {
924 e->next = ring->start;
925 d->next_offset = base;
926 } else {
927 e->next = e + 1;
928 d->next_offset = base + (i+1) * sizeof(*d);
929 }
930 }
931 ring->to_use = ring->to_clean = ring->start;
932
933 return 0;
934}
935
19a33d4e
SH		 936/* Allocate and setup a new buffer for receiving */
937static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
938 struct sk_buff *skb, unsigned int bufsize)
939{
940 struct skge_rx_desc *rd = e->desc;
941 u64 map;
baef58b1
SH		 942
943 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
944 PCI_DMA_FROMDEVICE);
945
946 rd->dma_lo = map;
947 rd->dma_hi = map >> 32;
948 e->skb = skb;
949 rd->csum1_start = ETH_HLEN;
950 rd->csum2_start = ETH_HLEN;
951 rd->csum1 = 0;
952 rd->csum2 = 0;
953
954 wmb();
955
956 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
10fc51b9
FT		 957 dma_unmap_addr_set(e, mapaddr, map);
958 dma_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 959}
960
19a33d4e
SH		 961/* Resume receiving using existing skb,
962 * Note: DMA address is not changed by chip.
963 * MTU not changed while receiver active.
964 */
5a011447 965static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
19a33d4e
SH		 966{
967 struct skge_rx_desc *rd = e->desc;
968
969 rd->csum2 = 0;
970 rd->csum2_start = ETH_HLEN;
971
972 wmb();
973
974 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
975}
976
977
978/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 979static void skge_rx_clean(struct skge_port *skge)
980{
981 struct skge_hw *hw = skge->hw;
982 struct skge_ring *ring = &skge->rx_ring;
983 struct skge_element *e;
984
19a33d4e
SH		 985 e = ring->start;
986 do {
baef58b1
SH		 987 struct skge_rx_desc *rd = e->desc;
988 rd->control = 0;
19a33d4e
SH		 989 if (e->skb) {
990 pci_unmap_single(hw->pdev,
10fc51b9
FT		 991 dma_unmap_addr(e, mapaddr),
992 dma_unmap_len(e, maplen),
19a33d4e
SH		 993 PCI_DMA_FROMDEVICE);
994 dev_kfree_skb(e->skb);
995 e->skb = NULL;
996 }
997 } while ((e = e->next) != ring->start);
baef58b1
SH		 998}
999
19a33d4e 1000
baef58b1 1001/* Allocate buffers for receive ring
19a33d4e 1002 * For receive: to_clean is next received frame.
baef58b1 1003 */
c54f9765 1004static int skge_rx_fill(struct net_device *dev)
baef58b1 1005{
c54f9765 1006 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 1007 struct skge_ring *ring = &skge->rx_ring;
1008 struct skge_element *e;
baef58b1 1009
19a33d4e
SH		 1010 e = ring->start;
1011 do {
383181ac 1012 struct sk_buff *skb;
baef58b1 1013
c54f9765
SH		 1014 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1015 GFP_KERNEL);
19a33d4e
SH		 1016 if (!skb)
1017 return -ENOMEM;
1018
383181ac
SH		 1019 skb_reserve(skb, NET_IP_ALIGN);
1020 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
67777f9b 1021 } while ((e = e->next) != ring->start);
baef58b1 1022
19a33d4e
SH		 1023 ring->to_clean = ring->start;
1024 return 0;
baef58b1
SH		 1025}
1026
5d5c8e03
SH		 1027static const char *skge_pause(enum pause_status status)
1028{
67777f9b 1029 switch (status) {
5d5c8e03
SH		 1030 case FLOW_STAT_NONE:
1031 return "none";
1032 case FLOW_STAT_REM_SEND:
1033 return "rx only";
1034 case FLOW_STAT_LOC_SEND:
1035 return "tx_only";
1036 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1037 return "both";
1038 default:
1039 return "indeterminated";
1040 }
1041}
1042
1043
baef58b1
SH		 1044static void skge_link_up(struct skge_port *skge)
1045{
46a60f2d 1046 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
54cfb5aa
SH		 1047 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
1048
baef58b1 1049 netif_carrier_on(skge->netdev);
29b4e886 1050 netif_wake_queue(skge->netdev);
baef58b1 1051
d707204c
JP		 1052 netif_info(skge, link, skge->netdev,
1053 "Link is up at %d Mbps, %s duplex, flow control %s\n",
1054 skge->speed,
1055 skge->duplex == DUPLEX_FULL ? "full" : "half",
1056 skge_pause(skge->flow_status));
baef58b1
SH		 1057}
1058
1059static void skge_link_down(struct skge_port *skge)
1060{
54cfb5aa 1061 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
baef58b1
SH		 1062 netif_carrier_off(skge->netdev);
1063 netif_stop_queue(skge->netdev);
1064
d707204c 1065 netif_info(skge, link, skge->netdev, "Link is down\n");
baef58b1
SH		 1066}
1067
a1bc9b87
SH		 1068static void xm_link_down(struct skge_hw *hw, int port)
1069{
1070 struct net_device *dev = hw->dev[port];
1071 struct skge_port *skge = netdev_priv(dev);
a1bc9b87 1072
501fb72d 1073 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
a1bc9b87 1074
a1bc9b87
SH		 1075 if (netif_carrier_ok(dev))
1076 skge_link_down(skge);
1077}
1078
2cd8e5d3 1079static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
baef58b1
SH		 1080{
1081 int i;
baef58b1 1082
6b0c1480 1083 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
0781191c 1084 *val = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 1085
64f6b64d
SH		 1086 if (hw->phy_type == SK_PHY_XMAC)
1087 goto ready;
1088
89bf5f23 1089 for (i = 0; i < PHY_RETRIES; i++) {
2cd8e5d3 1090 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
89bf5f23 1091 goto ready;
0781191c 1092 udelay(1);
baef58b1
SH		 1093 }
1094
2cd8e5d3 1095 return -ETIMEDOUT;
89bf5f23 1096 ready:
2cd8e5d3 1097 *val = xm_read16(hw, port, XM_PHY_DATA);
89bf5f23 1098
2cd8e5d3
SH		 1099 return 0;
1100}
1101
1102static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1103{
1104 u16 v = 0;
1105 if (__xm_phy_read(hw, port, reg, &v))
f15063cd 1106 pr_warning("%s: phy read timed out\n", hw->dev[port]->name);
baef58b1
SH		 1107 return v;
1108}
1109
2cd8e5d3 1110static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 1111{
1112 int i;
1113
6b0c1480 1114 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 1115 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 1116 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 1117 goto ready;
89bf5f23 1118 udelay(1);
baef58b1 1119 }
2cd8e5d3 1120 return -EIO;
baef58b1
SH		 1121
1122 ready:
6b0c1480 1123 xm_write16(hw, port, XM_PHY_DATA, val);
0781191c
SH		 1124 for (i = 0; i < PHY_RETRIES; i++) {
1125 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1126 return 0;
1127 udelay(1);
1128 }
1129 return -ETIMEDOUT;
baef58b1
SH		 1130}
1131
1132static void genesis_init(struct skge_hw *hw)
1133{
1134 /* set blink source counter */
1135 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1136 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1137
1138 /* configure mac arbiter */
1139 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1140
1141 /* configure mac arbiter timeout values */
1142 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1143 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1144 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1145 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1146
1147 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1148 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1149 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1150 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1151
1152 /* configure packet arbiter timeout */
1153 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1154 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1155 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1156 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1157 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1158}
1159
1160static void genesis_reset(struct skge_hw *hw, int port)
1161{
b6bc7650 1162 static const u8 zero[8] = { 0 };
21d7f677 1163 u32 reg;
baef58b1 1164
46a60f2d
SH		 1165 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1166
baef58b1 1167 /* reset the statistics module */
6b0c1480 1168 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
501fb72d 1169 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
6b0c1480
SH		 1170 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1171 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1172 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 1173
89bf5f23 1174 /* disable Broadcom PHY IRQ */
64f6b64d
SH		 1175 if (hw->phy_type == SK_PHY_BCOM)
1176 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 1177
45bada65 1178 xm_outhash(hw, port, XM_HSM, zero);
21d7f677
SH		 1179
1180 /* Flush TX and RX fifo */
1181 reg = xm_read32(hw, port, XM_MODE);
1182 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1183 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
baef58b1
SH		 1184}
1185
45bada65
SH		 1186/* Convert mode to MII values */
1187static const u16 phy_pause_map[] = {
1188 [FLOW_MODE_NONE] = 0,
1189 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1190 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
5d5c8e03 1191 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
45bada65
SH		 1192};
1193
4b67be99
SH		 1194/* special defines for FIBER (88E1011S only) */
1195static const u16 fiber_pause_map[] = {
1196 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1197 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1198 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
5d5c8e03 1199 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
4b67be99
SH		 1200};
1201
45bada65
SH		 1202
1203/* Check status of Broadcom phy link */
1204static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 1205{
45bada65
SH		 1206 struct net_device *dev = hw->dev[port];
1207 struct skge_port *skge = netdev_priv(dev);
1208 u16 status;
1209
1210 /* read twice because of latch */
501fb72d 1211 xm_phy_read(hw, port, PHY_BCOM_STAT);
45bada65
SH		 1212 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1213
45bada65 1214 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1215 xm_link_down(hw, port);
64f6b64d
SH		 1216 return;
1217 }
45bada65 1218
64f6b64d
SH		 1219 if (skge->autoneg == AUTONEG_ENABLE) {
1220 u16 lpa, aux;
45bada65 1221
64f6b64d
SH		 1222 if (!(status & PHY_ST_AN_OVER))
1223 return;
45bada65 1224
64f6b64d
SH		 1225 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1226 if (lpa & PHY_B_AN_RF) {
f15063cd 1227 netdev_notice(dev, "remote fault\n");
64f6b64d
SH		 1228 return;
1229 }
45bada65 1230
64f6b64d
SH		 1231 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1232
1233 /* Check Duplex mismatch */
1234 switch (aux & PHY_B_AS_AN_RES_MSK) {
1235 case PHY_B_RES_1000FD:
1236 skge->duplex = DUPLEX_FULL;
1237 break;
1238 case PHY_B_RES_1000HD:
1239 skge->duplex = DUPLEX_HALF;
1240 break;
1241 default:
f15063cd 1242 netdev_notice(dev, "duplex mismatch\n");
64f6b64d 1243 return;
45bada65
SH		 1244 }
1245
64f6b64d
SH		 1246 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1247 switch (aux & PHY_B_AS_PAUSE_MSK) {
1248 case PHY_B_AS_PAUSE_MSK:
5d5c8e03 1249 skge->flow_status = FLOW_STAT_SYMMETRIC;
64f6b64d
SH		 1250 break;
1251 case PHY_B_AS_PRR:
5d5c8e03 1252 skge->flow_status = FLOW_STAT_REM_SEND;
64f6b64d
SH		 1253 break;
1254 case PHY_B_AS_PRT:
5d5c8e03 1255 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d
SH		 1256 break;
1257 default:
5d5c8e03 1258 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1259 }
1260 skge->speed = SPEED_1000;
45bada65 1261 }
64f6b64d
SH		 1262
1263 if (!netif_carrier_ok(dev))
1264 genesis_link_up(skge);
45bada65
SH		 1265}
1266
1267/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1268 * Phy on for 100 or 10Mbit operation
1269 */
64f6b64d 1270static void bcom_phy_init(struct skge_port *skge)
45bada65
SH		 1271{
1272 struct skge_hw *hw = skge->hw;
1273 int port = skge->port;
baef58b1 1274 int i;
45bada65 1275 u16 id1, r, ext, ctl;
baef58b1
SH		 1276
1277 /* magic workaround patterns for Broadcom */
1278 static const struct {
1279 u16 reg;
1280 u16 val;
1281 } A1hack[] = {
1282 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1283 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1284 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1285 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1286 }, C0hack[] = {
1287 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1288 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1289 };
1290
45bada65
SH		 1291 /* read Id from external PHY (all have the same address) */
1292 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1293
1294 /* Optimize MDIO transfer by suppressing preamble. */
1295 r = xm_read16(hw, port, XM_MMU_CMD);
1296 r |= XM_MMU_NO_PRE;
67777f9b 1297 xm_write16(hw, port, XM_MMU_CMD, r);
45bada65 1298
2c668514 1299 switch (id1) {
45bada65
SH		 1300 case PHY_BCOM_ID1_C0:
1301 /*
1302 * Workaround BCOM Errata for the C0 type.
1303 * Write magic patterns to reserved registers.
1304 */
1305 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1306 xm_phy_write(hw, port,
1307 C0hack[i].reg, C0hack[i].val);
1308
1309 break;
1310 case PHY_BCOM_ID1_A1:
1311 /*
1312 * Workaround BCOM Errata for the A1 type.
1313 * Write magic patterns to reserved registers.
1314 */
1315 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1316 xm_phy_write(hw, port,
1317 A1hack[i].reg, A1hack[i].val);
1318 break;
1319 }
1320
1321 /*
1322 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1323 * Disable Power Management after reset.
1324 */
1325 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1326 r |= PHY_B_AC_DIS_PM;
1327 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1328
1329 /* Dummy read */
1330 xm_read16(hw, port, XM_ISRC);
1331
1332 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1333 ctl = PHY_CT_SP1000; /* always 1000mbit */
1334
1335 if (skge->autoneg == AUTONEG_ENABLE) {
1336 /*
1337 * Workaround BCOM Errata #1 for the C5 type.
1338 * 1000Base-T Link Acquisition Failure in Slave Mode
1339 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1340 */
1341 u16 adv = PHY_B_1000C_RD;
1342 if (skge->advertising & ADVERTISED_1000baseT_Half)
1343 adv |= PHY_B_1000C_AHD;
1344 if (skge->advertising & ADVERTISED_1000baseT_Full)
1345 adv |= PHY_B_1000C_AFD;
1346 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1347
1348 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1349 } else {
1350 if (skge->duplex == DUPLEX_FULL)
1351 ctl |= PHY_CT_DUP_MD;
1352 /* Force to slave */
1353 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1354 }
1355
1356 /* Set autonegotiation pause parameters */
1357 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1358 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1359
1360 /* Handle Jumbo frames */
64f6b64d 1361 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
45bada65
SH		 1362 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1363 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1364
1365 ext |= PHY_B_PEC_HIGH_LA;
1366
1367 }
1368
1369 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1370 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1371
8f3f8193 1372 /* Use link status change interrupt */
45bada65 1373 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
64f6b64d 1374}
45bada65 1375
64f6b64d
SH		 1376static void xm_phy_init(struct skge_port *skge)
1377{
1378 struct skge_hw *hw = skge->hw;
1379 int port = skge->port;
1380 u16 ctrl = 0;
1381
1382 if (skge->autoneg == AUTONEG_ENABLE) {
1383 if (skge->advertising & ADVERTISED_1000baseT_Half)
1384 ctrl |= PHY_X_AN_HD;
1385 if (skge->advertising & ADVERTISED_1000baseT_Full)
1386 ctrl |= PHY_X_AN_FD;
1387
4b67be99 1388 ctrl |= fiber_pause_map[skge->flow_control];
64f6b64d
SH		 1389
1390 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1391
1392 /* Restart Auto-negotiation */
1393 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1394 } else {
1395 /* Set DuplexMode in Config register */
1396 if (skge->duplex == DUPLEX_FULL)
1397 ctrl |= PHY_CT_DUP_MD;
1398 /*
1399 * Do NOT enable Auto-negotiation here. This would hold
1400 * the link down because no IDLEs are transmitted
1401 */
1402 }
1403
1404 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1405
1406 /* Poll PHY for status changes */
9cbe330f 1407 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
64f6b64d
SH		 1408}
1409
501fb72d 1410static int xm_check_link(struct net_device *dev)
64f6b64d
SH		 1411{
1412 struct skge_port *skge = netdev_priv(dev);
1413 struct skge_hw *hw = skge->hw;
1414 int port = skge->port;
1415 u16 status;
1416
1417 /* read twice because of latch */
501fb72d 1418 xm_phy_read(hw, port, PHY_XMAC_STAT);
64f6b64d
SH		 1419 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1420
1421 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1422 xm_link_down(hw, port);
501fb72d 1423 return 0;
64f6b64d
SH		 1424 }
1425
1426 if (skge->autoneg == AUTONEG_ENABLE) {
1427 u16 lpa, res;
1428
1429 if (!(status & PHY_ST_AN_OVER))
501fb72d 1430 return 0;
64f6b64d
SH		 1431
1432 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1433 if (lpa & PHY_B_AN_RF) {
f15063cd 1434 netdev_notice(dev, "remote fault\n");
501fb72d 1435 return 0;
64f6b64d
SH		 1436 }
1437
1438 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1439
1440 /* Check Duplex mismatch */
1441 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1442 case PHY_X_RS_FD:
1443 skge->duplex = DUPLEX_FULL;
1444 break;
1445 case PHY_X_RS_HD:
1446 skge->duplex = DUPLEX_HALF;
1447 break;
1448 default:
f15063cd 1449 netdev_notice(dev, "duplex mismatch\n");
501fb72d 1450 return 0;
64f6b64d
SH		 1451 }
1452
1453 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
5d5c8e03
SH		 1454 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1455 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1456 (lpa & PHY_X_P_SYM_MD))
1457 skge->flow_status = FLOW_STAT_SYMMETRIC;
1458 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1459 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1460 /* Enable PAUSE receive, disable PAUSE transmit */
1461 skge->flow_status = FLOW_STAT_REM_SEND;
1462 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1463 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1464 /* Disable PAUSE receive, enable PAUSE transmit */
1465 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d 1466 else
5d5c8e03 1467 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1468
1469 skge->speed = SPEED_1000;
1470 }
1471
1472 if (!netif_carrier_ok(dev))
1473 genesis_link_up(skge);
501fb72d 1474 return 1;
64f6b64d
SH		 1475}
1476
1477/* Poll to check for link coming up.
501fb72d 1478 *
64f6b64d 1479 * Since internal PHY is wired to a level triggered pin, can't
501fb72d
SH		 1480 * get an interrupt when carrier is detected, need to poll for
1481 * link coming up.
64f6b64d 1482 */
9cbe330f 1483static void xm_link_timer(unsigned long arg)
64f6b64d 1484{
9cbe330f 1485 struct skge_port *skge = (struct skge_port *) arg;
c4028958 1486 struct net_device *dev = skge->netdev;
67777f9b 1487 struct skge_hw *hw = skge->hw;
64f6b64d 1488 int port = skge->port;
501fb72d
SH		 1489 int i;
1490 unsigned long flags;
64f6b64d
SH		 1491
1492 if (!netif_running(dev))
1493 return;
1494
501fb72d
SH		 1495 spin_lock_irqsave(&hw->phy_lock, flags);
1496
1497 /*
1498 * Verify that the link by checking GPIO register three times.
1499 * This pin has the signal from the link_sync pin connected to it.
1500 */
1501 for (i = 0; i < 3; i++) {
1502 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1503 goto link_down;
1504 }
1505
67777f9b 1506 /* Re-enable interrupt to detect link down */
501fb72d
SH		 1507 if (xm_check_link(dev)) {
1508 u16 msk = xm_read16(hw, port, XM_IMSK);
1509 msk &= ~XM_IS_INP_ASS;
1510 xm_write16(hw, port, XM_IMSK, msk);
64f6b64d 1511 xm_read16(hw, port, XM_ISRC);
64f6b64d 1512 } else {
501fb72d
SH		 1513link_down:
1514 mod_timer(&skge->link_timer,
1515 round_jiffies(jiffies + LINK_HZ));
64f6b64d 1516 }
501fb72d 1517 spin_unlock_irqrestore(&hw->phy_lock, flags);
45bada65
SH		 1518}
1519
1520static void genesis_mac_init(struct skge_hw *hw, int port)
1521{
1522 struct net_device *dev = hw->dev[port];
1523 struct skge_port *skge = netdev_priv(dev);
1524 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1525 int i;
1526 u32 r;
b6bc7650 1527 static const u8 zero[6] = { 0 };
45bada65 1528
0781191c
SH		 1529 for (i = 0; i < 10; i++) {
1530 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1531 MFF_SET_MAC_RST);
1532 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1533 goto reset_ok;
1534 udelay(1);
1535 }
baef58b1 1536
f15063cd 1537 netdev_warn(dev, "genesis reset failed\n");
0781191c
SH		 1538
1539 reset_ok:
baef58b1 1540 /* Unreset the XMAC. */
6b0c1480 1541 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1542
1543 /*
1544 * Perform additional initialization for external PHYs,
1545 * namely for the 1000baseTX cards that use the XMAC's
1546 * GMII mode.
1547 */
64f6b64d
SH		 1548 if (hw->phy_type != SK_PHY_XMAC) {
1549 /* Take external Phy out of reset */
1550 r = skge_read32(hw, B2_GP_IO);
1551 if (port == 0)
1552 r |= GP_DIR_0|GP_IO_0;
1553 else
1554 r |= GP_DIR_2|GP_IO_2;
89bf5f23 1555
64f6b64d 1556 skge_write32(hw, B2_GP_IO, r);
0781191c 1557
64f6b64d
SH		 1558 /* Enable GMII interface */
1559 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1560 }
89bf5f23 1561
89bf5f23 1562
67777f9b 1563 switch (hw->phy_type) {
64f6b64d
SH		 1564 case SK_PHY_XMAC:
1565 xm_phy_init(skge);
1566 break;
1567 case SK_PHY_BCOM:
1568 bcom_phy_init(skge);
1569 bcom_check_link(hw, port);
1570 }
89bf5f23 1571
45bada65
SH		 1572 /* Set Station Address */
1573 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1574
45bada65
SH		 1575 /* We don't use match addresses so clear */
1576 for (i = 1; i < 16; i++)
1577 xm_outaddr(hw, port, XM_EXM(i), zero);
1578
0781191c
SH		 1579 /* Clear MIB counters */
1580 xm_write16(hw, port, XM_STAT_CMD,
1581 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1582 /* Clear two times according to Errata #3 */
1583 xm_write16(hw, port, XM_STAT_CMD,
1584 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1585
45bada65
SH		 1586 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1587 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1588
1589 /* We don't need the FCS appended to the packet. */
1590 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1591 if (jumbo)
1592 r |= XM_RX_BIG_PK_OK;
89bf5f23 1593
45bada65 1594 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1595 /*
45bada65
SH		 1596 * If in manual half duplex mode the other side might be in
1597 * full duplex mode, so ignore if a carrier extension is not seen
1598 * on frames received
89bf5f23 1599 */
45bada65 1600 r |= XM_RX_DIS_CEXT;
baef58b1 1601 }
45bada65 1602 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1603
baef58b1 1604 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1605 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1606
485982a9
SH		 1607 /* Increase threshold for jumbo frames on dual port */
1608 if (hw->ports > 1 && jumbo)
1609 xm_write16(hw, port, XM_TX_THR, 1020);
1610 else
1611 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1612
1613 /*
1614 * Enable the reception of all error frames. This is is
1615 * a necessary evil due to the design of the XMAC. The
1616 * XMAC's receive FIFO is only 8K in size, however jumbo
1617 * frames can be up to 9000 bytes in length. When bad
1618 * frame filtering is enabled, the XMAC's RX FIFO operates
1619 * in 'store and forward' mode. For this to work, the
1620 * entire frame has to fit into the FIFO, but that means
1621 * that jumbo frames larger than 8192 bytes will be
1622 * truncated. Disabling all bad frame filtering causes
1623 * the RX FIFO to operate in streaming mode, in which
8f3f8193 1624 * case the XMAC will start transferring frames out of the
baef58b1
SH		 1625 * RX FIFO as soon as the FIFO threshold is reached.
1626 */
45bada65 1627 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1628
baef58b1
SH		 1629
1630 /*
45bada65
SH		 1631 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1632 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1633 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1634 */
45bada65
SH		 1635 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1636
1637 /*
1638 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1639 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1640 * and 'Octets Tx OK Hi Cnt Ov'.
1641 */
1642 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1643
1644 /* Configure MAC arbiter */
1645 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1646
1647 /* configure timeout values */
1648 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1649 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1650 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1651 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1652
1653 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1654 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1655 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1656 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1657
1658 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1659 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1660 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1661 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1662
1663 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1664 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1665 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1666 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1667
45bada65 1668 if (jumbo) {
baef58b1 1669 /* Enable frame flushing if jumbo frames used */
67777f9b 1670 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1671 } else {
1672 /* enable timeout timers if normal frames */
1673 skge_write16(hw, B3_PA_CTRL,
45bada65 1674 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1675 }
baef58b1
SH		 1676}
1677
1678static void genesis_stop(struct skge_port *skge)
1679{
1680 struct skge_hw *hw = skge->hw;
1681 int port = skge->port;
799b21d2 1682 unsigned retries = 1000;
21d7f677
SH		 1683 u16 cmd;
1684
67777f9b 1685 /* Disable Tx and Rx */
21d7f677
SH		 1686 cmd = xm_read16(hw, port, XM_MMU_CMD);
1687 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1688 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1689
46a60f2d
SH		 1690 genesis_reset(hw, port);
1691
baef58b1
SH		 1692 /* Clear Tx packet arbiter timeout IRQ */
1693 skge_write16(hw, B3_PA_CTRL,
1694 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1695
baef58b1 1696 /* Reset the MAC */
799b21d2
SH		 1697 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1698 do {
1699 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1700 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1701 break;
1702 } while (--retries > 0);
baef58b1
SH		 1703
1704 /* For external PHYs there must be special handling */
64f6b64d 1705 if (hw->phy_type != SK_PHY_XMAC) {
799b21d2 1706 u32 reg = skge_read32(hw, B2_GP_IO);
64f6b64d
SH		 1707 if (port == 0) {
1708 reg |= GP_DIR_0;
1709 reg &= ~GP_IO_0;
1710 } else {
1711 reg |= GP_DIR_2;
1712 reg &= ~GP_IO_2;
1713 }
1714 skge_write32(hw, B2_GP_IO, reg);
1715 skge_read32(hw, B2_GP_IO);
baef58b1
SH		 1716 }
1717
6b0c1480
SH		 1718 xm_write16(hw, port, XM_MMU_CMD,
1719 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1720 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1721
6b0c1480 1722 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1723}
1724
1725
1726static void genesis_get_stats(struct skge_port *skge, u64 *data)
1727{
1728 struct skge_hw *hw = skge->hw;
1729 int port = skge->port;
1730 int i;
1731 unsigned long timeout = jiffies + HZ;
1732
6b0c1480 1733 xm_write16(hw, port,
baef58b1
SH		 1734 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1735
1736 /* wait for update to complete */
6b0c1480 1737 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1738 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1739 if (time_after(jiffies, timeout))
1740 break;
1741 udelay(10);
1742 }
1743
1744 /* special case for 64 bit octet counter */
6b0c1480
SH		 1745 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1746 | xm_read32(hw, port, XM_TXO_OK_LO);
1747 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1748 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1749
1750 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1751 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1752}
1753
1754static void genesis_mac_intr(struct skge_hw *hw, int port)
1755{
da00772f
SH		 1756 struct net_device *dev = hw->dev[port];
1757 struct skge_port *skge = netdev_priv(dev);
6b0c1480 1758 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1759
d707204c
JP		 1760 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1761 "mac interrupt status 0x%x\n", status);
baef58b1 1762
501fb72d 1763 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
67777f9b 1764 xm_link_down(hw, port);
501fb72d
SH		 1765 mod_timer(&skge->link_timer, jiffies + 1);
1766 }
a1bc9b87 1767
baef58b1 1768 if (status & XM_IS_TXF_UR) {
6b0c1480 1769 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
da00772f 1770 ++dev->stats.tx_fifo_errors;
baef58b1 1771 }
baef58b1
SH		 1772}
1773
baef58b1
SH		 1774static void genesis_link_up(struct skge_port *skge)
1775{
1776 struct skge_hw *hw = skge->hw;
1777 int port = skge->port;
a1bc9b87 1778 u16 cmd, msk;
64f6b64d 1779 u32 mode;
baef58b1 1780
6b0c1480 1781 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1782
1783 /*
1784 * enabling pause frame reception is required for 1000BT
1785 * because the XMAC is not reset if the link is going down
1786 */
5d5c8e03
SH		 1787 if (skge->flow_status == FLOW_STAT_NONE ||
1788 skge->flow_status == FLOW_STAT_LOC_SEND)
7e676d91 1789 /* Disable Pause Frame Reception */
baef58b1
SH		 1790 cmd |= XM_MMU_IGN_PF;
1791 else
1792 /* Enable Pause Frame Reception */
1793 cmd &= ~XM_MMU_IGN_PF;
1794
6b0c1480 1795 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1796
6b0c1480 1797 mode = xm_read32(hw, port, XM_MODE);
67777f9b 1798 if (skge->flow_status == FLOW_STAT_SYMMETRIC ||
5d5c8e03 1799 skge->flow_status == FLOW_STAT_LOC_SEND) {
baef58b1
SH		 1800 /*
1801 * Configure Pause Frame Generation
1802 * Use internal and external Pause Frame Generation.
1803 * Sending pause frames is edge triggered.
1804 * Send a Pause frame with the maximum pause time if
1805 * internal oder external FIFO full condition occurs.
1806 * Send a zero pause time frame to re-start transmission.
1807 */
1808 /* XM_PAUSE_DA = '010000C28001' (default) */
1809 /* XM_MAC_PTIME = 0xffff (maximum) */
1810 /* remember this value is defined in big endian (!) */
6b0c1480 1811 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1812
1813 mode |= XM_PAUSE_MODE;
6b0c1480 1814 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1815 } else {
1816 /*
1817 * disable pause frame generation is required for 1000BT
1818 * because the XMAC is not reset if the link is going down
1819 */
1820 /* Disable Pause Mode in Mode Register */
1821 mode &= ~XM_PAUSE_MODE;
1822
6b0c1480 1823 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1824 }
1825
6b0c1480 1826 xm_write32(hw, port, XM_MODE, mode);
a1bc9b87 1827
d08b9bdf 1828 /* Turn on detection of Tx underrun */
501fb72d 1829 msk = xm_read16(hw, port, XM_IMSK);
d08b9bdf 1830 msk &= ~XM_IS_TXF_UR;
a1bc9b87 1831 xm_write16(hw, port, XM_IMSK, msk);
501fb72d 1832
6b0c1480 1833 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1834
1835 /* get MMU Command Reg. */
6b0c1480 1836 cmd = xm_read16(hw, port, XM_MMU_CMD);
64f6b64d 1837 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1838 cmd |= XM_MMU_GMII_FD;
1839
89bf5f23
SH		 1840 /*
1841 * Workaround BCOM Errata (#10523) for all BCom Phys
1842 * Enable Power Management after link up
1843 */
64f6b64d
SH		 1844 if (hw->phy_type == SK_PHY_BCOM) {
1845 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1846 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1847 & ~PHY_B_AC_DIS_PM);
1848 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1849 }
baef58b1
SH		 1850
1851 /* enable Rx/Tx */
6b0c1480 1852 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1853 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1854 skge_link_up(skge);
1855}
1856
1857
45bada65 1858static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1859{
1860 struct skge_hw *hw = skge->hw;
1861 int port = skge->port;
45bada65
SH		 1862 u16 isrc;
1863
1864 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
d707204c
JP		 1865 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1866 "phy interrupt status 0x%x\n", isrc);
baef58b1 1867
45bada65 1868 if (isrc & PHY_B_IS_PSE)
f15063cd 1869 pr_err("%s: uncorrectable pair swap error\n",
45bada65 1870 hw->dev[port]->name);
baef58b1
SH		 1871
1872 /* Workaround BCom Errata:
1873 * enable and disable loopback mode if "NO HCD" occurs.
1874 */
45bada65 1875 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1876 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1877 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1878 ctrl | PHY_CT_LOOP);
6b0c1480 1879 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1880 ctrl & ~PHY_CT_LOOP);
1881 }
1882
45bada65
SH		 1883 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1884 bcom_check_link(hw, port);
baef58b1 1885
baef58b1
SH		 1886}
1887
2cd8e5d3
SH		 1888static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1889{
1890 int i;
1891
1892 gma_write16(hw, port, GM_SMI_DATA, val);
1893 gma_write16(hw, port, GM_SMI_CTRL,
1894 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1895 for (i = 0; i < PHY_RETRIES; i++) {
1896 udelay(1);
1897
1898 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1899 return 0;
1900 }
1901
f15063cd 1902 pr_warning("%s: phy write timeout\n", hw->dev[port]->name);
2cd8e5d3
SH		 1903 return -EIO;
1904}
1905
1906static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1907{
1908 int i;
1909
1910 gma_write16(hw, port, GM_SMI_CTRL,
1911 GM_SMI_CT_PHY_AD(hw->phy_addr)
1912 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1913
1914 for (i = 0; i < PHY_RETRIES; i++) {
1915 udelay(1);
1916 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1917 goto ready;
1918 }
1919
1920 return -ETIMEDOUT;
1921 ready:
1922 *val = gma_read16(hw, port, GM_SMI_DATA);
1923 return 0;
1924}
1925
1926static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1927{
1928 u16 v = 0;
1929 if (__gm_phy_read(hw, port, reg, &v))
f15063cd 1930 pr_warning("%s: phy read timeout\n", hw->dev[port]->name);
2cd8e5d3
SH		 1931 return v;
1932}
1933
8f3f8193 1934/* Marvell Phy Initialization */
baef58b1
SH		 1935static void yukon_init(struct skge_hw *hw, int port)
1936{
1937 struct skge_port *skge = netdev_priv(hw->dev[port]);
1938 u16 ctrl, ct1000, adv;
baef58b1 1939
baef58b1 1940 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1941 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1942
1943 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1944 PHY_M_EC_MAC_S_MSK);
1945 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1946
c506a509 1947 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1948
6b0c1480 1949 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1950 }
1951
6b0c1480 1952 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1953 if (skge->autoneg == AUTONEG_DISABLE)
1954 ctrl &= ~PHY_CT_ANE;
1955
1956 ctrl |= PHY_CT_RESET;
6b0c1480 1957 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1958
1959 ctrl = 0;
1960 ct1000 = 0;
b18f2091 1961 adv = PHY_AN_CSMA;
baef58b1
SH		 1962
1963 if (skge->autoneg == AUTONEG_ENABLE) {
5e1705dd 1964 if (hw->copper) {
baef58b1
SH		 1965 if (skge->advertising & ADVERTISED_1000baseT_Full)
1966 ct1000 |= PHY_M_1000C_AFD;
1967 if (skge->advertising & ADVERTISED_1000baseT_Half)
1968 ct1000 |= PHY_M_1000C_AHD;
1969 if (skge->advertising & ADVERTISED_100baseT_Full)
1970 adv |= PHY_M_AN_100_FD;
1971 if (skge->advertising & ADVERTISED_100baseT_Half)
1972 adv |= PHY_M_AN_100_HD;
1973 if (skge->advertising & ADVERTISED_10baseT_Full)
1974 adv |= PHY_M_AN_10_FD;
1975 if (skge->advertising & ADVERTISED_10baseT_Half)
1976 adv |= PHY_M_AN_10_HD;
baef58b1 1977
4b67be99
SH		 1978 /* Set Flow-control capabilities */
1979 adv |= phy_pause_map[skge->flow_control];
1980 } else {
1981 if (skge->advertising & ADVERTISED_1000baseT_Full)
1982 adv |= PHY_M_AN_1000X_AFD;
1983 if (skge->advertising & ADVERTISED_1000baseT_Half)
1984 adv |= PHY_M_AN_1000X_AHD;
1985
1986 adv |= fiber_pause_map[skge->flow_control];
1987 }
45bada65 1988
baef58b1
SH		 1989 /* Restart Auto-negotiation */
1990 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1991 } else {
1992 /* forced speed/duplex settings */
1993 ct1000 = PHY_M_1000C_MSE;
1994
1995 if (skge->duplex == DUPLEX_FULL)
1996 ctrl |= PHY_CT_DUP_MD;
1997
1998 switch (skge->speed) {
1999 case SPEED_1000:
2000 ctrl |= PHY_CT_SP1000;
2001 break;
2002 case SPEED_100:
2003 ctrl |= PHY_CT_SP100;
2004 break;
2005 }
2006
2007 ctrl |= PHY_CT_RESET;
2008 }
2009
c506a509 2010 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 2011
6b0c1480
SH		 2012 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2013 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1 2014
baef58b1
SH		 2015 /* Enable phy interrupt on autonegotiation complete (or link up) */
2016 if (skge->autoneg == AUTONEG_ENABLE)
4cde06ed 2017 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
baef58b1 2018 else
4cde06ed 2019 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 2020}
2021
2022static void yukon_reset(struct skge_hw *hw, int port)
2023{
6b0c1480
SH		 2024 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2025 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2026 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2027 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2028 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 2029
6b0c1480
SH		 2030 gma_write16(hw, port, GM_RX_CTRL,
2031 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 2032 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2033}
2034
c8868611
SH		 2035/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2036static int is_yukon_lite_a0(struct skge_hw *hw)
2037{
2038 u32 reg;
2039 int ret;
2040
2041 if (hw->chip_id != CHIP_ID_YUKON)
2042 return 0;
2043
2044 reg = skge_read32(hw, B2_FAR);
2045 skge_write8(hw, B2_FAR + 3, 0xff);
2046 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2047 skge_write32(hw, B2_FAR, reg);
2048 return ret;
2049}
2050
baef58b1
SH		 2051static void yukon_mac_init(struct skge_hw *hw, int port)
2052{
2053 struct skge_port *skge = netdev_priv(hw->dev[port]);
2054 int i;
2055 u32 reg;
2056 const u8 *addr = hw->dev[port]->dev_addr;
2057
2058 /* WA code for COMA mode -- set PHY reset */
2059 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 2060 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2061 reg = skge_read32(hw, B2_GP_IO);
2062 reg |= GP_DIR_9 | GP_IO_9;
2063 skge_write32(hw, B2_GP_IO, reg);
2064 }
baef58b1
SH		 2065
2066 /* hard reset */
6b0c1480
SH		 2067 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2068 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 2069
2070 /* WA code for COMA mode -- clear PHY reset */
2071 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 2072 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2073 reg = skge_read32(hw, B2_GP_IO);
2074 reg |= GP_DIR_9;
2075 reg &= ~GP_IO_9;
2076 skge_write32(hw, B2_GP_IO, reg);
2077 }
baef58b1
SH		 2078
2079 /* Set hardware config mode */
2080 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2081 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
5e1705dd 2082 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
baef58b1
SH		 2083
2084 /* Clear GMC reset */
6b0c1480
SH		 2085 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2086 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2087 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
564f9abb 2088
baef58b1
SH		 2089 if (skge->autoneg == AUTONEG_DISABLE) {
2090 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 2091 gma_write16(hw, port, GM_GP_CTRL,
2092 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 2093
2094 switch (skge->speed) {
2095 case SPEED_1000:
564f9abb 2096 reg &= ~GM_GPCR_SPEED_100;
baef58b1 2097 reg |= GM_GPCR_SPEED_1000;
564f9abb 2098 break;
baef58b1 2099 case SPEED_100:
564f9abb 2100 reg &= ~GM_GPCR_SPEED_1000;
baef58b1 2101 reg |= GM_GPCR_SPEED_100;
564f9abb
SH		 2102 break;
2103 case SPEED_10:
2104 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2105 break;
baef58b1
SH		 2106 }
2107
2108 if (skge->duplex == DUPLEX_FULL)
2109 reg |= GM_GPCR_DUP_FULL;
2110 } else
2111 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
564f9abb 2112
baef58b1
SH		 2113 switch (skge->flow_control) {
2114 case FLOW_MODE_NONE:
6b0c1480 2115 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 2116 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2117 break;
2118 case FLOW_MODE_LOC_SEND:
2119 /* disable Rx flow-control */
2120 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
5d5c8e03
SH		 2121 break;
2122 case FLOW_MODE_SYMMETRIC:
2123 case FLOW_MODE_SYM_OR_REM:
2124 /* enable Tx & Rx flow-control */
2125 break;
baef58b1
SH		 2126 }
2127
6b0c1480 2128 gma_write16(hw, port, GM_GP_CTRL, reg);
46a60f2d 2129 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2130
baef58b1 2131 yukon_init(hw, port);
baef58b1
SH		 2132
2133 /* MIB clear */
6b0c1480
SH		 2134 reg = gma_read16(hw, port, GM_PHY_ADDR);
2135 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 2136
2137 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 2138 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2139 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 2140
2141 /* transmit control */
6b0c1480 2142 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 2143
2144 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 2145 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 2146 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2147
2148 /* transmit flow control */
6b0c1480 2149 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 2150
2151 /* transmit parameter */
6b0c1480 2152 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 2153 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2154 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2155 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2156
44c7fcce
SH		 2157 /* configure the Serial Mode Register */
2158 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2159 | GM_SMOD_VLAN_ENA
2160 | IPG_DATA_VAL(IPG_DATA_DEF);
2161
2162 if (hw->dev[port]->mtu > ETH_DATA_LEN)
baef58b1
SH		 2163 reg |= GM_SMOD_JUMBO_ENA;
2164
6b0c1480 2165 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 2166
2167 /* physical address: used for pause frames */
6b0c1480 2168 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 2169 /* virtual address for data */
6b0c1480 2170 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 2171
2172 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 2173 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2174 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2175 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 2176
2177 /* Initialize Mac Fifo */
2178
2179 /* Configure Rx MAC FIFO */
6b0c1480 2180 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1 2181 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
c8868611
SH		 2182
2183 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2184 if (is_yukon_lite_a0(hw))
baef58b1 2185 reg &= ~GMF_RX_F_FL_ON;
c8868611 2186
6b0c1480
SH		 2187 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2188 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
c5923081
SH		 2189 /*
2190 * because Pause Packet Truncation in GMAC is not working
2191 * we have to increase the Flush Threshold to 64 bytes
2192 * in order to flush pause packets in Rx FIFO on Yukon-1
2193 */
2194 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
baef58b1
SH		 2195
2196 /* Configure Tx MAC FIFO */
6b0c1480
SH		 2197 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2198 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 2199}
2200
355ec572
SH		 2201/* Go into power down mode */
2202static void yukon_suspend(struct skge_hw *hw, int port)
2203{
2204 u16 ctrl;
2205
2206 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2207 ctrl |= PHY_M_PC_POL_R_DIS;
2208 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2209
2210 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2211 ctrl |= PHY_CT_RESET;
2212 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2213
2214 /* switch IEEE compatible power down mode on */
2215 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2216 ctrl |= PHY_CT_PDOWN;
2217 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2218}
2219
baef58b1
SH		 2220static void yukon_stop(struct skge_port *skge)
2221{
2222 struct skge_hw *hw = skge->hw;
2223 int port = skge->port;
2224
46a60f2d
SH		 2225 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2226 yukon_reset(hw, port);
baef58b1 2227
6b0c1480
SH		 2228 gma_write16(hw, port, GM_GP_CTRL,
2229 gma_read16(hw, port, GM_GP_CTRL)
0eedf4ac 2230 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
6b0c1480 2231 gma_read16(hw, port, GM_GP_CTRL);
baef58b1 2232
355ec572 2233 yukon_suspend(hw, port);
46a60f2d 2234
baef58b1 2235 /* set GPHY Control reset */
46a60f2d
SH		 2236 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2237 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 2238}
2239
2240static void yukon_get_stats(struct skge_port *skge, u64 *data)
2241{
2242 struct skge_hw *hw = skge->hw;
2243 int port = skge->port;
2244 int i;
2245
6b0c1480
SH		 2246 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2247 | gma_read32(hw, port, GM_TXO_OK_LO);
2248 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2249 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 2250
2251 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 2252 data[i] = gma_read32(hw, port,
baef58b1
SH		 2253 skge_stats[i].gma_offset);
2254}
2255
2256static void yukon_mac_intr(struct skge_hw *hw, int port)
2257{
7e676d91
SH		 2258 struct net_device *dev = hw->dev[port];
2259 struct skge_port *skge = netdev_priv(dev);
6b0c1480 2260 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2261
d707204c
JP		 2262 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2263 "mac interrupt status 0x%x\n", status);
7e676d91 2264
baef58b1 2265 if (status & GM_IS_RX_FF_OR) {
da00772f 2266 ++dev->stats.rx_fifo_errors;
d8a09943 2267 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
baef58b1 2268 }
d8a09943 2269
baef58b1 2270 if (status & GM_IS_TX_FF_UR) {
da00772f 2271 ++dev->stats.tx_fifo_errors;
d8a09943 2272 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
baef58b1
SH		 2273 }
2274
2275}
2276
2277static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2278{
95566065 2279 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 2280 case PHY_M_PS_SPEED_1000:
2281 return SPEED_1000;
2282 case PHY_M_PS_SPEED_100:
2283 return SPEED_100;
2284 default:
2285 return SPEED_10;
2286 }
2287}
2288
2289static void yukon_link_up(struct skge_port *skge)
2290{
2291 struct skge_hw *hw = skge->hw;
2292 int port = skge->port;
2293 u16 reg;
2294
baef58b1 2295 /* Enable Transmit FIFO Underrun */
46a60f2d 2296 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
baef58b1 2297
6b0c1480 2298 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 2299 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2300 reg |= GM_GPCR_DUP_FULL;
2301
2302 /* enable Rx/Tx */
2303 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 2304 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 2305
4cde06ed 2306 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 2307 skge_link_up(skge);
2308}
2309
2310static void yukon_link_down(struct skge_port *skge)
2311{
2312 struct skge_hw *hw = skge->hw;
2313 int port = skge->port;
d8a09943 2314 u16 ctrl;
baef58b1 2315
d8a09943
SH		 2316 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2317 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2318 gma_write16(hw, port, GM_GP_CTRL, ctrl);
baef58b1 2319
5d5c8e03
SH		 2320 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2321 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2322 ctrl |= PHY_M_AN_ASP;
baef58b1 2323 /* restore Asymmetric Pause bit */
5d5c8e03 2324 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
baef58b1
SH		 2325 }
2326
baef58b1
SH		 2327 skge_link_down(skge);
2328
2329 yukon_init(hw, port);
2330}
2331
2332static void yukon_phy_intr(struct skge_port *skge)
2333{
2334 struct skge_hw *hw = skge->hw;
2335 int port = skge->port;
2336 const char *reason = NULL;
2337 u16 istatus, phystat;
2338
6b0c1480
SH		 2339 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2340 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91 2341
d707204c
JP		 2342 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2343 "phy interrupt status 0x%x 0x%x\n", istatus, phystat);
baef58b1
SH		 2344
2345 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 2346 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 2347 & PHY_M_AN_RF) {
2348 reason = "remote fault";
2349 goto failed;
2350 }
2351
c506a509 2352 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 2353 reason = "master/slave fault";
2354 goto failed;
2355 }
2356
2357 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2358 reason = "speed/duplex";
2359 goto failed;
2360 }
2361
2362 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2363 ? DUPLEX_FULL : DUPLEX_HALF;
2364 skge->speed = yukon_speed(hw, phystat);
2365
baef58b1
SH		 2366 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2367 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2368 case PHY_M_PS_PAUSE_MSK:
5d5c8e03 2369 skge->flow_status = FLOW_STAT_SYMMETRIC;
baef58b1
SH		 2370 break;
2371 case PHY_M_PS_RX_P_EN:
5d5c8e03 2372 skge->flow_status = FLOW_STAT_REM_SEND;
baef58b1
SH		 2373 break;
2374 case PHY_M_PS_TX_P_EN:
5d5c8e03 2375 skge->flow_status = FLOW_STAT_LOC_SEND;
baef58b1
SH		 2376 break;
2377 default:
5d5c8e03 2378 skge->flow_status = FLOW_STAT_NONE;
baef58b1
SH		 2379 }
2380
5d5c8e03 2381 if (skge->flow_status == FLOW_STAT_NONE ||
baef58b1 2382 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 2383 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 2384 else
6b0c1480 2385 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 2386 yukon_link_up(skge);
2387 return;
2388 }
2389
2390 if (istatus & PHY_M_IS_LSP_CHANGE)
2391 skge->speed = yukon_speed(hw, phystat);
2392
2393 if (istatus & PHY_M_IS_DUP_CHANGE)
2394 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2395 if (istatus & PHY_M_IS_LST_CHANGE) {
2396 if (phystat & PHY_M_PS_LINK_UP)
2397 yukon_link_up(skge);
2398 else
2399 yukon_link_down(skge);
2400 }
2401 return;
2402 failed:
f15063cd 2403 pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason);
baef58b1
SH		 2404
2405 /* XXX restart autonegotiation? */
2406}
2407
ee294dcd
SH		 2408static void skge_phy_reset(struct skge_port *skge)
2409{
2410 struct skge_hw *hw = skge->hw;
2411 int port = skge->port;
aae343d4 2412 struct net_device *dev = hw->dev[port];
ee294dcd
SH		 2413
2414 netif_stop_queue(skge->netdev);
2415 netif_carrier_off(skge->netdev);
2416
9cbe330f 2417 spin_lock_bh(&hw->phy_lock);
57d6fa37 2418 if (is_genesis(hw)) {
ee294dcd
SH		 2419 genesis_reset(hw, port);
2420 genesis_mac_init(hw, port);
2421 } else {
2422 yukon_reset(hw, port);
2423 yukon_init(hw, port);
2424 }
9cbe330f 2425 spin_unlock_bh(&hw->phy_lock);
75814090 2426
f80d032b 2427 skge_set_multicast(dev);
ee294dcd
SH		 2428}
2429
2cd8e5d3
SH		 2430/* Basic MII support */
2431static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2432{
2433 struct mii_ioctl_data *data = if_mii(ifr);
2434 struct skge_port *skge = netdev_priv(dev);
2435 struct skge_hw *hw = skge->hw;
2436 int err = -EOPNOTSUPP;
2437
2438 if (!netif_running(dev))
2439 return -ENODEV; /* Phy still in reset */
2440
67777f9b 2441 switch (cmd) {
2cd8e5d3
SH		 2442 case SIOCGMIIPHY:
2443 data->phy_id = hw->phy_addr;
2444
2445 /* fallthru */
2446 case SIOCGMIIREG: {
2447 u16 val = 0;
9cbe330f 2448 spin_lock_bh(&hw->phy_lock);
57d6fa37 2449
2450 if (is_genesis(hw))
2cd8e5d3
SH		 2451 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2452 else
2453 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
9cbe330f 2454 spin_unlock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2455 data->val_out = val;
2456 break;
2457 }
2458
2459 case SIOCSMIIREG:
9cbe330f 2460 spin_lock_bh(&hw->phy_lock);
57d6fa37 2461 if (is_genesis(hw))
2cd8e5d3
SH		 2462 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2463 data->val_in);
2464 else
2465 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2466 data->val_in);
9cbe330f 2467 spin_unlock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2468 break;
2469 }
2470 return err;
2471}
2472
279e1dab 2473static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
baef58b1
SH		 2474{
2475 u32 end;
2476
279e1dab
LT		 2477 start /= 8;
2478 len /= 8;
2479 end = start + len - 1;
baef58b1
SH		 2480
2481 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2482 skge_write32(hw, RB_ADDR(q, RB_START), start);
2483 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2484 skge_write32(hw, RB_ADDR(q, RB_RP), start);
279e1dab 2485 skge_write32(hw, RB_ADDR(q, RB_END), end);
baef58b1
SH		 2486
2487 if (q == Q_R1 || q == Q_R2) {
2488 /* Set thresholds on receive queue's */
279e1dab
LT		 2489 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2490 start + (2*len)/3);
2491 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2492 start + (len/3));
2493 } else {
2494 /* Enable store & forward on Tx queue's because
2495 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2496 */
baef58b1 2497 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
279e1dab 2498 }
baef58b1
SH		 2499
2500 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2501}
2502
2503/* Setup Bus Memory Interface */
2504static void skge_qset(struct skge_port *skge, u16 q,
2505 const struct skge_element *e)
2506{
2507 struct skge_hw *hw = skge->hw;
2508 u32 watermark = 0x600;
2509 u64 base = skge->dma + (e->desc - skge->mem);
2510
2511 /* optimization to reduce window on 32bit/33mhz */
2512 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2513 watermark /= 2;
2514
2515 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2516 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2517 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2518 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2519}
2520
2521static int skge_up(struct net_device *dev)
2522{
2523 struct skge_port *skge = netdev_priv(dev);
2524 struct skge_hw *hw = skge->hw;
2525 int port = skge->port;
279e1dab 2526 u32 chunk, ram_addr;
baef58b1
SH		 2527 size_t rx_size, tx_size;
2528 int err;
2529
fae87592
SH		 2530 if (!is_valid_ether_addr(dev->dev_addr))
2531 return -EINVAL;
2532
d707204c 2533 netif_info(skge, ifup, skge->netdev, "enabling interface\n");
baef58b1 2534
19a33d4e 2535 if (dev->mtu > RX_BUF_SIZE)
901ccefb 2536 skge->rx_buf_size = dev->mtu + ETH_HLEN;
19a33d4e
SH		 2537 else
2538 skge->rx_buf_size = RX_BUF_SIZE;
2539
2540
baef58b1
SH		 2541 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2542 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2543 skge->mem_size = tx_size + rx_size;
2544 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2545 if (!skge->mem)
2546 return -ENOMEM;
2547
c3da1447
SH		 2548 BUG_ON(skge->dma & 7);
2549
2550 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
1479d13c 2551 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
c3da1447
SH		 2552 err = -EINVAL;
2553 goto free_pci_mem;
2554 }
2555
baef58b1
SH		 2556 memset(skge->mem, 0, skge->mem_size);
2557
203babb6
SH		 2558 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2559 if (err)
baef58b1
SH		 2560 goto free_pci_mem;
2561
c54f9765 2562 err = skge_rx_fill(dev);
19a33d4e 2563 if (err)
baef58b1
SH		 2564 goto free_rx_ring;
2565
203babb6
SH		 2566 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2567 skge->dma + rx_size);
2568 if (err)
baef58b1
SH		 2569 goto free_rx_ring;
2570
8f3f8193 2571 /* Initialize MAC */
9cbe330f 2572 spin_lock_bh(&hw->phy_lock);
57d6fa37 2573 if (is_genesis(hw))
baef58b1
SH		 2574 genesis_mac_init(hw, port);
2575 else
2576 yukon_mac_init(hw, port);
9cbe330f 2577 spin_unlock_bh(&hw->phy_lock);
baef58b1 2578
29816d9a
SH		 2579 /* Configure RAMbuffers - equally between ports and tx/rx */
2580 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
279e1dab 2581 ram_addr = hw->ram_offset + 2 * chunk * port;
baef58b1 2582
279e1dab 2583 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
7fb7ac24 2584 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
279e1dab 2585
baef58b1 2586 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
279e1dab 2587 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
baef58b1
SH		 2588 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2589
2590 /* Start receiver BMU */
2591 wmb();
2592 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
6abebb53 2593 skge_led(skge, LED_MODE_ON);
baef58b1 2594
4ebabfcb
SH		 2595 spin_lock_irq(&hw->hw_lock);
2596 hw->intr_mask |= portmask[port];
2597 skge_write32(hw, B0_IMSK, hw->intr_mask);
2598 spin_unlock_irq(&hw->hw_lock);
2599
bea3348e 2600 napi_enable(&skge->napi);
baef58b1
SH		 2601 return 0;
2602
2603 free_rx_ring:
2604 skge_rx_clean(skge);
2605 kfree(skge->rx_ring.start);
2606 free_pci_mem:
2607 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2608 skge->mem = NULL;
baef58b1
SH		 2609
2610 return err;
2611}
2612
60b24b51
SH		 2613/* stop receiver */
2614static void skge_rx_stop(struct skge_hw *hw, int port)
2615{
2616 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2617 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2618 RB_RST_SET|RB_DIS_OP_MD);
2619 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2620}
2621
baef58b1
SH		 2622static int skge_down(struct net_device *dev)
2623{
2624 struct skge_port *skge = netdev_priv(dev);
2625 struct skge_hw *hw = skge->hw;
2626 int port = skge->port;
2627
7731a4ea
SH		 2628 if (skge->mem == NULL)
2629 return 0;
2630
d707204c 2631 netif_info(skge, ifdown, skge->netdev, "disabling interface\n");
baef58b1 2632
d119b392 2633 netif_tx_disable(dev);
692412b3 2634
57d6fa37 2635 if (is_genesis(hw) && hw->phy_type == SK_PHY_XMAC)
9cbe330f 2636 del_timer_sync(&skge->link_timer);
baef58b1 2637
bea3348e 2638 napi_disable(&skge->napi);
692412b3 2639 netif_carrier_off(dev);
4ebabfcb
SH		 2640
2641 spin_lock_irq(&hw->hw_lock);
2642 hw->intr_mask &= ~portmask[port];
2643 skge_write32(hw, B0_IMSK, hw->intr_mask);
2644 spin_unlock_irq(&hw->hw_lock);
2645
46a60f2d 2646 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
57d6fa37 2647 if (is_genesis(hw))
46a60f2d
SH		 2648 genesis_stop(skge);
2649 else
2650 yukon_stop(skge);
2651
baef58b1
SH		 2652 /* Stop transmitter */
2653 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2654 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2655 RB_RST_SET|RB_DIS_OP_MD);
2656
baef58b1
SH		 2657
2658 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2659 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2660 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2661
2662 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2663 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2664 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2665
2666 /* Reset PCI FIFO */
2667 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2668 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2669
2670 /* Reset the RAM Buffer async Tx queue */
2671 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
60b24b51
SH		 2672
2673 skge_rx_stop(hw, port);
baef58b1 2674
57d6fa37 2675 if (is_genesis(hw)) {
6b0c1480
SH		 2676 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2677 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
baef58b1 2678 } else {
6b0c1480
SH		 2679 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2680 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2681 }
2682
6abebb53 2683 skge_led(skge, LED_MODE_OFF);
baef58b1 2684
e3a1b99f 2685 netif_tx_lock_bh(dev);
513f533e 2686 skge_tx_clean(dev);
e3a1b99f
SH		 2687 netif_tx_unlock_bh(dev);
2688
baef58b1
SH		 2689 skge_rx_clean(skge);
2690
2691 kfree(skge->rx_ring.start);
2692 kfree(skge->tx_ring.start);
2693 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2694 skge->mem = NULL;
baef58b1
SH		 2695 return 0;
2696}
2697
29b4e886
SH		 2698static inline int skge_avail(const struct skge_ring *ring)
2699{
992c9623 2700 smp_mb();
29b4e886
SH		 2701 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2702 + (ring->to_clean - ring->to_use) - 1;
2703}
2704
61357325
SH		 2705static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
2706 struct net_device *dev)
baef58b1
SH		 2707{
2708 struct skge_port *skge = netdev_priv(dev);
2709 struct skge_hw *hw = skge->hw;
baef58b1
SH		 2710 struct skge_element *e;
2711 struct skge_tx_desc *td;
2712 int i;
2713 u32 control, len;
2714 u64 map;
baef58b1 2715
5b057c6b 2716 if (skb_padto(skb, ETH_ZLEN))
baef58b1
SH		 2717 return NETDEV_TX_OK;
2718
513f533e 2719 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
baef58b1 2720 return NETDEV_TX_BUSY;
baef58b1 2721
7c442fa1 2722 e = skge->tx_ring.to_use;
baef58b1 2723 td = e->desc;
7c442fa1 2724 BUG_ON(td->control & BMU_OWN);
baef58b1
SH		 2725 e->skb = skb;
2726 len = skb_headlen(skb);
2727 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
10fc51b9
FT		 2728 dma_unmap_addr_set(e, mapaddr, map);
2729 dma_unmap_len_set(e, maplen, len);
baef58b1
SH		 2730
2731 td->dma_lo = map;
2732 td->dma_hi = map >> 32;
2733
84fa7933 2734 if (skb->ip_summed == CHECKSUM_PARTIAL) {
0d0b1672 2735 const int offset = skb_checksum_start_offset(skb);
baef58b1
SH		 2736
2737 /* This seems backwards, but it is what the sk98lin
2738 * does. Looks like hardware is wrong?
2739 */
8e95a202 2740 if (ipip_hdr(skb)->protocol == IPPROTO_UDP &&
67777f9b 2741 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2742 control = BMU_TCP_CHECK;
2743 else
2744 control = BMU_UDP_CHECK;
2745
2746 td->csum_offs = 0;
2747 td->csum_start = offset;
ff1dcadb 2748 td->csum_write = offset + skb->csum_offset;
baef58b1
SH		 2749 } else
2750 control = BMU_CHECK;
2751
2752 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
67777f9b 2753 control |= BMU_EOF | BMU_IRQ_EOF;
baef58b1
SH		 2754 else {
2755 struct skge_tx_desc *tf = td;
2756
2757 control |= BMU_STFWD;
2758 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2759 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2760
2761 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2762 frag->size, PCI_DMA_TODEVICE);
2763
2764 e = e->next;
7c442fa1 2765 e->skb = skb;
baef58b1 2766 tf = e->desc;
7c442fa1
SH		 2767 BUG_ON(tf->control & BMU_OWN);
2768
baef58b1
SH		 2769 tf->dma_lo = map;
2770 tf->dma_hi = (u64) map >> 32;
10fc51b9
FT		 2771 dma_unmap_addr_set(e, mapaddr, map);
2772 dma_unmap_len_set(e, maplen, frag->size);
baef58b1
SH		 2773
2774 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2775 }
2776 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2777 }
2778 /* Make sure all the descriptors written */
2779 wmb();
2780 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2781 wmb();
2782
2783 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2784
d707204c
JP		 2785 netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev,
2786 "tx queued, slot %td, len %d\n",
2787 e - skge->tx_ring.start, skb->len);
baef58b1 2788
7c442fa1 2789 skge->tx_ring.to_use = e->next;
992c9623
SH		 2790 smp_wmb();
2791
9db96479 2792 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
f15063cd 2793 netdev_dbg(dev, "transmit queue full\n");
baef58b1
SH		 2794 netif_stop_queue(dev);
2795 }
2796
baef58b1
SH		 2797 return NETDEV_TX_OK;
2798}
2799
7c442fa1
SH		 2800
2801/* Free resources associated with this reing element */
2802static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2803 u32 control)
866b4f3e
SH		 2804{
2805 struct pci_dev *pdev = skge->hw->pdev;
866b4f3e 2806
7c442fa1
SH		 2807 /* skb header vs. fragment */
2808 if (control & BMU_STF)
10fc51b9
FT		 2809 pci_unmap_single(pdev, dma_unmap_addr(e, mapaddr),
2810 dma_unmap_len(e, maplen),
7c442fa1
SH		 2811 PCI_DMA_TODEVICE);
2812 else
10fc51b9
FT		 2813 pci_unmap_page(pdev, dma_unmap_addr(e, mapaddr),
2814 dma_unmap_len(e, maplen),
7c442fa1 2815 PCI_DMA_TODEVICE);
866b4f3e 2816
7c442fa1 2817 if (control & BMU_EOF) {
d707204c
JP		 2818 netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev,
2819 "tx done slot %td\n", e - skge->tx_ring.start);
866b4f3e 2820
513f533e 2821 dev_kfree_skb(e->skb);
baef58b1
SH		 2822 }
2823}
2824
7c442fa1 2825/* Free all buffers in transmit ring */
513f533e 2826static void skge_tx_clean(struct net_device *dev)
baef58b1 2827{
513f533e 2828 struct skge_port *skge = netdev_priv(dev);
7c442fa1 2829 struct skge_element *e;
baef58b1 2830
7c442fa1
SH		 2831 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2832 struct skge_tx_desc *td = e->desc;
2833 skge_tx_free(skge, e, td->control);
2834 td->control = 0;
2835 }
2836
2837 skge->tx_ring.to_clean = e;
baef58b1
SH		 2838}
2839
2840static void skge_tx_timeout(struct net_device *dev)
2841{
2842 struct skge_port *skge = netdev_priv(dev);
2843
d707204c 2844 netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n");
baef58b1
SH		 2845
2846 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
513f533e 2847 skge_tx_clean(dev);
d119b392 2848 netif_wake_queue(dev);
baef58b1
SH		 2849}
2850
2851static int skge_change_mtu(struct net_device *dev, int new_mtu)
2852{
7731a4ea 2853 int err;
baef58b1 2854
95566065 2855 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2856 return -EINVAL;
2857
7731a4ea
SH		 2858 if (!netif_running(dev)) {
2859 dev->mtu = new_mtu;
2860 return 0;
2861 }
2862
1a8098be 2863 skge_down(dev);
baef58b1 2864
19a33d4e 2865 dev->mtu = new_mtu;
7731a4ea 2866
1a8098be 2867 err = skge_up(dev);
7731a4ea
SH		 2868 if (err)
2869 dev_close(dev);
baef58b1
SH		 2870
2871 return err;
2872}
2873
c4cd29d2
SH		 2874static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2875
2876static void genesis_add_filter(u8 filter[8], const u8 *addr)
2877{
2878 u32 crc, bit;
2879
2880 crc = ether_crc_le(ETH_ALEN, addr);
2881 bit = ~crc & 0x3f;
2882 filter[bit/8] |= 1 << (bit%8);
2883}
2884
baef58b1
SH		 2885static void genesis_set_multicast(struct net_device *dev)
2886{
2887 struct skge_port *skge = netdev_priv(dev);
2888 struct skge_hw *hw = skge->hw;
2889 int port = skge->port;
22bedad3 2890 struct netdev_hw_addr *ha;
baef58b1
SH		 2891 u32 mode;
2892 u8 filter[8];
2893
6b0c1480 2894 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2895 mode |= XM_MD_ENA_HASH;
2896 if (dev->flags & IFF_PROMISC)
2897 mode |= XM_MD_ENA_PROM;
2898 else
2899 mode &= ~XM_MD_ENA_PROM;
2900
2901 if (dev->flags & IFF_ALLMULTI)
2902 memset(filter, 0xff, sizeof(filter));
2903 else {
2904 memset(filter, 0, sizeof(filter));
c4cd29d2 2905
8e95a202
JP		 2906 if (skge->flow_status == FLOW_STAT_REM_SEND ||
2907 skge->flow_status == FLOW_STAT_SYMMETRIC)
c4cd29d2
SH		 2908 genesis_add_filter(filter, pause_mc_addr);
2909
22bedad3
JP		 2910 netdev_for_each_mc_addr(ha, dev)
2911 genesis_add_filter(filter, ha->addr);
baef58b1
SH		 2912 }
2913
6b0c1480 2914 xm_write32(hw, port, XM_MODE, mode);
45bada65 2915 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2916}
2917
c4cd29d2
SH		 2918static void yukon_add_filter(u8 filter[8], const u8 *addr)
2919{
2920 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2921 filter[bit/8] |= 1 << (bit%8);
2922}
2923
baef58b1
SH		 2924static void yukon_set_multicast(struct net_device *dev)
2925{
2926 struct skge_port *skge = netdev_priv(dev);
2927 struct skge_hw *hw = skge->hw;
2928 int port = skge->port;
22bedad3 2929 struct netdev_hw_addr *ha;
8e95a202
JP		 2930 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND ||
2931 skge->flow_status == FLOW_STAT_SYMMETRIC);
baef58b1
SH		 2932 u16 reg;
2933 u8 filter[8];
2934
2935 memset(filter, 0, sizeof(filter));
2936
6b0c1480 2937 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2938 reg |= GM_RXCR_UCF_ENA;
2939
8f3f8193 2940 if (dev->flags & IFF_PROMISC) /* promiscuous */
baef58b1
SH		 2941 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2942 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2943 memset(filter, 0xff, sizeof(filter));
4cd24eaf 2944 else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */
baef58b1
SH		 2945 reg &= ~GM_RXCR_MCF_ENA;
2946 else {
baef58b1
SH		 2947 reg |= GM_RXCR_MCF_ENA;
2948
c4cd29d2
SH		 2949 if (rx_pause)
2950 yukon_add_filter(filter, pause_mc_addr);
2951
22bedad3
JP		 2952 netdev_for_each_mc_addr(ha, dev)
2953 yukon_add_filter(filter, ha->addr);
baef58b1
SH		 2954 }
2955
2956
6b0c1480 2957 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2958 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2959 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2960 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2961 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2962 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2963 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2964 (u16)filter[6] | ((u16)filter[7] << 8));
2965
6b0c1480 2966 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2967}
2968
383181ac
SH		 2969static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2970{
57d6fa37 2971 if (is_genesis(hw))
383181ac
SH		 2972 return status >> XMR_FS_LEN_SHIFT;
2973 else
2974 return status >> GMR_FS_LEN_SHIFT;
2975}
2976
baef58b1
SH		 2977static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2978{
57d6fa37 2979 if (is_genesis(hw))
baef58b1
SH		 2980 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2981 else
2982 return (status & GMR_FS_ANY_ERR) ||
2983 (status & GMR_FS_RX_OK) == 0;
2984}
2985
f80d032b
SH		 2986static void skge_set_multicast(struct net_device *dev)
2987{
2988 struct skge_port *skge = netdev_priv(dev);
f80d032b 2989
57d6fa37 2990 if (is_genesis(skge->hw))
f80d032b
SH		 2991 genesis_set_multicast(dev);
2992 else
2993 yukon_set_multicast(dev);
2994
2995}
2996
19a33d4e
SH		 2997
2998/* Get receive buffer from descriptor.
2999 * Handles copy of small buffers and reallocation failures
3000 */
c54f9765
SH		 3001static struct sk_buff *skge_rx_get(struct net_device *dev,
3002 struct skge_element *e,
3003 u32 control, u32 status, u16 csum)
19a33d4e 3004{
c54f9765 3005 struct skge_port *skge = netdev_priv(dev);
383181ac
SH		 3006 struct sk_buff *skb;
3007 u16 len = control & BMU_BBC;
3008
d707204c
JP		 3009 netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev,
3010 "rx slot %td status 0x%x len %d\n",
3011 e - skge->rx_ring.start, status, len);
383181ac
SH		 3012
3013 if (len > skge->rx_buf_size)
3014 goto error;
3015
3016 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3017 goto error;
3018
3019 if (bad_phy_status(skge->hw, status))
3020 goto error;
3021
3022 if (phy_length(skge->hw, status) != len)
3023 goto error;
19a33d4e
SH		 3024
3025 if (len < RX_COPY_THRESHOLD) {
89d71a66 3026 skb = netdev_alloc_skb_ip_align(dev, len);
383181ac
SH		 3027 if (!skb)
3028 goto resubmit;
19a33d4e
SH		 3029
3030 pci_dma_sync_single_for_cpu(skge->hw->pdev,
10fc51b9 3031 dma_unmap_addr(e, mapaddr),
19a33d4e 3032 len, PCI_DMA_FROMDEVICE);
d626f62b 3033 skb_copy_from_linear_data(e->skb, skb->data, len);
19a33d4e 3034 pci_dma_sync_single_for_device(skge->hw->pdev,
10fc51b9 3035 dma_unmap_addr(e, mapaddr),
19a33d4e 3036 len, PCI_DMA_FROMDEVICE);
19a33d4e 3037 skge_rx_reuse(e, skge->rx_buf_size);
19a33d4e 3038 } else {
383181ac 3039 struct sk_buff *nskb;
89d71a66
ED		 3040
3041 nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size);
383181ac
SH		 3042 if (!nskb)
3043 goto resubmit;
19a33d4e
SH		 3044
3045 pci_unmap_single(skge->hw->pdev,
10fc51b9
FT		 3046 dma_unmap_addr(e, mapaddr),
3047 dma_unmap_len(e, maplen),
19a33d4e
SH		 3048 PCI_DMA_FROMDEVICE);
3049 skb = e->skb;
67777f9b 3050 prefetch(skb->data);
19a33d4e 3051 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
baef58b1 3052 }
383181ac
SH		 3053
3054 skb_put(skb, len);
e92702b1
MM		 3055
3056 if (dev->features & NETIF_F_RXCSUM) {
383181ac 3057 skb->csum = csum;
84fa7933 3058 skb->ip_summed = CHECKSUM_COMPLETE;
383181ac
SH		 3059 }
3060
c54f9765 3061 skb->protocol = eth_type_trans(skb, dev);
383181ac
SH		 3062
3063 return skb;
3064error:
3065
d707204c
JP		 3066 netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev,
3067 "rx err, slot %td control 0x%x status 0x%x\n",
3068 e - skge->rx_ring.start, control, status);
383181ac 3069
57d6fa37 3070 if (is_genesis(skge->hw)) {
383181ac 3071 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
da00772f 3072 dev->stats.rx_length_errors++;
383181ac 3073 if (status & XMR_FS_FRA_ERR)
da00772f 3074 dev->stats.rx_frame_errors++;
383181ac 3075 if (status & XMR_FS_FCS_ERR)
da00772f 3076 dev->stats.rx_crc_errors++;
383181ac
SH		 3077 } else {
3078 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
da00772f 3079 dev->stats.rx_length_errors++;
383181ac 3080 if (status & GMR_FS_FRAGMENT)
da00772f 3081 dev->stats.rx_frame_errors++;
383181ac 3082 if (status & GMR_FS_CRC_ERR)
da00772f 3083 dev->stats.rx_crc_errors++;
383181ac
SH		 3084 }
3085
3086resubmit:
3087 skge_rx_reuse(e, skge->rx_buf_size);
3088 return NULL;
baef58b1
SH		 3089}
3090
7c442fa1 3091/* Free all buffers in Tx ring which are no longer owned by device */
513f533e 3092static void skge_tx_done(struct net_device *dev)
00a6cae2 3093{
7c442fa1 3094 struct skge_port *skge = netdev_priv(dev);
00a6cae2 3095 struct skge_ring *ring = &skge->tx_ring;
7c442fa1
SH		 3096 struct skge_element *e;
3097
513f533e 3098 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
00a6cae2 3099
866b4f3e 3100 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
992c9623 3101 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
00a6cae2 3102
992c9623 3103 if (control & BMU_OWN)
00a6cae2
SH		 3104 break;
3105
992c9623 3106 skge_tx_free(skge, e, control);
00a6cae2 3107 }
7c442fa1 3108 skge->tx_ring.to_clean = e;
866b4f3e 3109
992c9623
SH		 3110 /* Can run lockless until we need to synchronize to restart queue. */
3111 smp_mb();
3112
3113 if (unlikely(netif_queue_stopped(dev) &&
3114 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3115 netif_tx_lock(dev);
3116 if (unlikely(netif_queue_stopped(dev) &&
3117 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3118 netif_wake_queue(dev);
00a6cae2 3119
992c9623
SH		 3120 }
3121 netif_tx_unlock(dev);
3122 }
00a6cae2 3123}
19a33d4e 3124
bea3348e 3125static int skge_poll(struct napi_struct *napi, int to_do)
baef58b1 3126{
bea3348e
SH		 3127 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3128 struct net_device *dev = skge->netdev;
baef58b1
SH		 3129 struct skge_hw *hw = skge->hw;
3130 struct skge_ring *ring = &skge->rx_ring;
3131 struct skge_element *e;
00a6cae2
SH		 3132 int work_done = 0;
3133
513f533e
SH		 3134 skge_tx_done(dev);
3135
3136 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3137
1631aef1 3138 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
baef58b1 3139 struct skge_rx_desc *rd = e->desc;
19a33d4e 3140 struct sk_buff *skb;
383181ac 3141 u32 control;
baef58b1
SH		 3142
3143 rmb();
3144 control = rd->control;
3145 if (control & BMU_OWN)
3146 break;
3147
c54f9765 3148 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
19a33d4e 3149 if (likely(skb)) {
86cac58b 3150 napi_gro_receive(napi, skb);
19a33d4e 3151 ++work_done;
5a011447 3152 }
baef58b1
SH		 3153 }
3154 ring->to_clean = e;
3155
baef58b1
SH		 3156 /* restart receiver */
3157 wmb();
a9cdab86 3158 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
baef58b1 3159
bea3348e 3160 if (work_done < to_do) {
6ef2977d 3161 unsigned long flags;
f0c88f9c 3162
86cac58b 3163 napi_gro_flush(napi);
6ef2977d 3164 spin_lock_irqsave(&hw->hw_lock, flags);
288379f0 3165 __napi_complete(napi);
bea3348e
SH		 3166 hw->intr_mask |= napimask[skge->port];
3167 skge_write32(hw, B0_IMSK, hw->intr_mask);
3168 skge_read32(hw, B0_IMSK);
6ef2977d 3169 spin_unlock_irqrestore(&hw->hw_lock, flags);
bea3348e 3170 }
1631aef1 3171
bea3348e 3172 return work_done;
baef58b1
SH		 3173}
3174
f6620cab
SH		 3175/* Parity errors seem to happen when Genesis is connected to a switch
3176 * with no other ports present. Heartbeat error??
3177 */
baef58b1
SH		 3178static void skge_mac_parity(struct skge_hw *hw, int port)
3179{
f6620cab
SH		 3180 struct net_device *dev = hw->dev[port];
3181
da00772f 3182 ++dev->stats.tx_heartbeat_errors;
baef58b1 3183
57d6fa37 3184 if (is_genesis(hw))
6b0c1480 3185 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 3186 MFF_CLR_PERR);
3187 else
3188 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 3189 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 3190 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 3191 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3192}
3193
baef58b1
SH		 3194static void skge_mac_intr(struct skge_hw *hw, int port)
3195{
57d6fa37 3196 if (is_genesis(hw))
baef58b1
SH		 3197 genesis_mac_intr(hw, port);
3198 else
3199 yukon_mac_intr(hw, port);
3200}
3201
3202/* Handle device specific framing and timeout interrupts */
3203static void skge_error_irq(struct skge_hw *hw)
3204{
1479d13c 3205 struct pci_dev *pdev = hw->pdev;
baef58b1
SH		 3206 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3207
57d6fa37 3208 if (is_genesis(hw)) {
baef58b1
SH		 3209 /* clear xmac errors */
3210 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
46a60f2d 3211 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
baef58b1 3212 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
46a60f2d 3213 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
baef58b1
SH		 3214 } else {
3215 /* Timestamp (unused) overflow */
3216 if (hwstatus & IS_IRQ_TIST_OV)
3217 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
baef58b1
SH		 3218 }
3219
3220 if (hwstatus & IS_RAM_RD_PAR) {
1479d13c 3221 dev_err(&pdev->dev, "Ram read data parity error\n");
baef58b1
SH		 3222 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3223 }
3224
3225 if (hwstatus & IS_RAM_WR_PAR) {
1479d13c 3226 dev_err(&pdev->dev, "Ram write data parity error\n");
baef58b1
SH		 3227 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3228 }
3229
3230 if (hwstatus & IS_M1_PAR_ERR)
3231 skge_mac_parity(hw, 0);
3232
3233 if (hwstatus & IS_M2_PAR_ERR)
3234 skge_mac_parity(hw, 1);
3235
b9d64acc 3236 if (hwstatus & IS_R1_PAR_ERR) {
1479d13c
SH		 3237 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3238 hw->dev[0]->name);
baef58b1 3239 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
b9d64acc 3240 }
baef58b1 3241
b9d64acc 3242 if (hwstatus & IS_R2_PAR_ERR) {
1479d13c
SH		 3243 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3244 hw->dev[1]->name);
baef58b1 3245 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
b9d64acc 3246 }
baef58b1
SH		 3247
3248 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
b9d64acc
SH		 3249 u16 pci_status, pci_cmd;
3250
1479d13c
SH		 3251 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3252 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
baef58b1 3253
1479d13c
SH		 3254 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3255 pci_cmd, pci_status);
b9d64acc
SH		 3256
3257 /* Write the error bits back to clear them. */
3258 pci_status &= PCI_STATUS_ERROR_BITS;
3259 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1479d13c 3260 pci_write_config_word(pdev, PCI_COMMAND,
b9d64acc 3261 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
1479d13c 3262 pci_write_config_word(pdev, PCI_STATUS, pci_status);
b9d64acc 3263 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1 3264
050ec18a 3265 /* if error still set then just ignore it */
baef58b1
SH		 3266 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3267 if (hwstatus & IS_IRQ_STAT) {
1479d13c 3268 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
baef58b1
SH		 3269 hw->intr_mask &= ~IS_HW_ERR;
3270 }
3271 }
3272}
3273
3274/*
9cbe330f 3275 * Interrupt from PHY are handled in tasklet (softirq)
baef58b1
SH		 3276 * because accessing phy registers requires spin wait which might
3277 * cause excess interrupt latency.
3278 */
9cbe330f 3279static void skge_extirq(unsigned long arg)
baef58b1 3280{
9cbe330f 3281 struct skge_hw *hw = (struct skge_hw *) arg;
baef58b1
SH		 3282 int port;
3283
cfc3ed79 3284 for (port = 0; port < hw->ports; port++) {
baef58b1
SH		 3285 struct net_device *dev = hw->dev[port];
3286
cfc3ed79 3287 if (netif_running(dev)) {
9cbe330f
SH		 3288 struct skge_port *skge = netdev_priv(dev);
3289
3290 spin_lock(&hw->phy_lock);
57d6fa37 3291 if (!is_genesis(hw))
baef58b1 3292 yukon_phy_intr(skge);
64f6b64d 3293 else if (hw->phy_type == SK_PHY_BCOM)
45bada65 3294 bcom_phy_intr(skge);
9cbe330f 3295 spin_unlock(&hw->phy_lock);
baef58b1
SH		 3296 }
3297 }
baef58b1 3298
7c442fa1 3299 spin_lock_irq(&hw->hw_lock);
baef58b1
SH		 3300 hw->intr_mask |= IS_EXT_REG;
3301 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3302 skge_read32(hw, B0_IMSK);
7c442fa1 3303 spin_unlock_irq(&hw->hw_lock);
baef58b1
SH		 3304}
3305
7d12e780 3306static irqreturn_t skge_intr(int irq, void *dev_id)
baef58b1
SH		 3307{
3308 struct skge_hw *hw = dev_id;
cfc3ed79 3309 u32 status;
29365c90 3310 int handled = 0;
baef58b1 3311
29365c90 3312 spin_lock(&hw->hw_lock);
cfc3ed79
SH		 3313 /* Reading this register masks IRQ */
3314 status = skge_read32(hw, B0_SP_ISRC);
0486a8c8 3315 if (status == 0 || status == ~0)
29365c90 3316 goto out;
baef58b1 3317
29365c90 3318 handled = 1;
7c442fa1 3319 status &= hw->intr_mask;
cfc3ed79
SH		 3320 if (status & IS_EXT_REG) {
3321 hw->intr_mask &= ~IS_EXT_REG;
9cbe330f 3322 tasklet_schedule(&hw->phy_task);
cfc3ed79
SH		 3323 }
3324
513f533e 3325 if (status & (IS_XA1_F|IS_R1_F)) {
bea3348e 3326 struct skge_port *skge = netdev_priv(hw->dev[0]);
513f533e 3327 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
288379f0 3328 napi_schedule(&skge->napi);
baef58b1
SH		 3329 }
3330
7c442fa1
SH		 3331 if (status & IS_PA_TO_TX1)
3332 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
cfc3ed79 3333
d25f5a67 3334 if (status & IS_PA_TO_RX1) {
da00772f 3335 ++hw->dev[0]->stats.rx_over_errors;
7c442fa1 3336 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
d25f5a67
SH		 3337 }
3338
d25f5a67 3339
baef58b1
SH		 3340 if (status & IS_MAC1)
3341 skge_mac_intr(hw, 0);
95566065 3342
7c442fa1 3343 if (hw->dev[1]) {
bea3348e
SH		 3344 struct skge_port *skge = netdev_priv(hw->dev[1]);
3345
513f533e
SH		 3346 if (status & (IS_XA2_F|IS_R2_F)) {
3347 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
288379f0 3348 napi_schedule(&skge->napi);
7c442fa1
SH		 3349 }
3350
3351 if (status & IS_PA_TO_RX2) {
da00772f 3352 ++hw->dev[1]->stats.rx_over_errors;
7c442fa1
SH		 3353 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3354 }
3355
3356 if (status & IS_PA_TO_TX2)
3357 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3358
3359 if (status & IS_MAC2)
3360 skge_mac_intr(hw, 1);
3361 }
baef58b1
SH		 3362
3363 if (status & IS_HW_ERR)
3364 skge_error_irq(hw);
3365
7e676d91 3366 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3367 skge_read32(hw, B0_IMSK);
29365c90 3368out:
7c442fa1 3369 spin_unlock(&hw->hw_lock);
baef58b1 3370
29365c90 3371 return IRQ_RETVAL(handled);
baef58b1
SH		 3372}
3373
3374#ifdef CONFIG_NET_POLL_CONTROLLER
3375static void skge_netpoll(struct net_device *dev)
3376{
3377 struct skge_port *skge = netdev_priv(dev);
3378
3379 disable_irq(dev->irq);
7d12e780 3380 skge_intr(dev->irq, skge->hw);
baef58b1
SH		 3381 enable_irq(dev->irq);
3382}
3383#endif
3384
3385static int skge_set_mac_address(struct net_device *dev, void *p)
3386{
3387 struct skge_port *skge = netdev_priv(dev);
c2681dd8
SH		 3388 struct skge_hw *hw = skge->hw;
3389 unsigned port = skge->port;
3390 const struct sockaddr *addr = p;
2eb3e621 3391 u16 ctrl;
baef58b1
SH		 3392
3393 if (!is_valid_ether_addr(addr->sa_data))
3394 return -EADDRNOTAVAIL;
3395
baef58b1 3396 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
c2681dd8 3397
9cbe330f
SH		 3398 if (!netif_running(dev)) {
3399 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3400 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3401 } else {
3402 /* disable Rx */
3403 spin_lock_bh(&hw->phy_lock);
3404 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3405 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
2eb3e621 3406
9cbe330f
SH		 3407 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3408 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
2eb3e621 3409
57d6fa37 3410 if (is_genesis(hw))
2eb3e621
SH		 3411 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3412 else {
3413 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3414 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3415 }
2eb3e621 3416
9cbe330f
SH		 3417 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3418 spin_unlock_bh(&hw->phy_lock);
3419 }
c2681dd8
SH		 3420
3421 return 0;
baef58b1
SH		 3422}
3423
3424static const struct {
3425 u8 id;
3426 const char *name;
3427} skge_chips[] = {
3428 { CHIP_ID_GENESIS, "Genesis" },
3429 { CHIP_ID_YUKON, "Yukon" },
3430 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3431 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 3432};
3433
3434static const char *skge_board_name(const struct skge_hw *hw)
3435{
3436 int i;
3437 static char buf[16];
3438
3439 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3440 if (skge_chips[i].id == hw->chip_id)
3441 return skge_chips[i].name;
3442
3443 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3444 return buf;
3445}
3446
3447
3448/*
3449 * Setup the board data structure, but don't bring up
3450 * the port(s)
3451 */
3452static int skge_reset(struct skge_hw *hw)
3453{
adba9e23 3454 u32 reg;
b9d64acc 3455 u16 ctst, pci_status;
64f6b64d 3456 u8 t8, mac_cfg, pmd_type;
981d0377 3457 int i;
baef58b1
SH		 3458
3459 ctst = skge_read16(hw, B0_CTST);
3460
3461 /* do a SW reset */
3462 skge_write8(hw, B0_CTST, CS_RST_SET);
3463 skge_write8(hw, B0_CTST, CS_RST_CLR);
3464
3465 /* clear PCI errors, if any */
b9d64acc
SH		 3466 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3467 skge_write8(hw, B2_TST_CTRL2, 0);
baef58b1 3468
b9d64acc
SH		 3469 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3470 pci_write_config_word(hw->pdev, PCI_STATUS,
3471 pci_status | PCI_STATUS_ERROR_BITS);
3472 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1
SH		 3473 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3474
3475 /* restore CLK_RUN bits (for Yukon-Lite) */
3476 skge_write16(hw, B0_CTST,
3477 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3478
3479 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
64f6b64d 3480 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
5e1705dd
SH		 3481 pmd_type = skge_read8(hw, B2_PMD_TYP);
3482 hw->copper = (pmd_type == 'T' || pmd_type == '1');
baef58b1 3483
95566065 3484 switch (hw->chip_id) {
baef58b1 3485 case CHIP_ID_GENESIS:
57d6fa37 3486#ifdef CONFIG_SKGE_GENESIS
64f6b64d
SH		 3487 switch (hw->phy_type) {
3488 case SK_PHY_XMAC:
3489 hw->phy_addr = PHY_ADDR_XMAC;
3490 break;
baef58b1
SH		 3491 case SK_PHY_BCOM:
3492 hw->phy_addr = PHY_ADDR_BCOM;
3493 break;
3494 default:
1479d13c
SH		 3495 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3496 hw->phy_type);
baef58b1
SH		 3497 return -EOPNOTSUPP;
3498 }
3499 break;
57d6fa37 3500#else
3501 dev_err(&hw->pdev->dev, "Genesis chip detected but not configured\n");
3502 return -EOPNOTSUPP;
3503#endif
baef58b1
SH		 3504
3505 case CHIP_ID_YUKON:
3506 case CHIP_ID_YUKON_LITE:
3507 case CHIP_ID_YUKON_LP:
64f6b64d 3508 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
5e1705dd 3509 hw->copper = 1;
baef58b1
SH		 3510
3511 hw->phy_addr = PHY_ADDR_MARV;
baef58b1
SH		 3512 break;
3513
3514 default:
1479d13c
SH		 3515 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3516 hw->chip_id);
baef58b1
SH		 3517 return -EOPNOTSUPP;
3518 }
3519
981d0377
SH		 3520 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3521 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3522 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 3523
3524 /* read the adapters RAM size */
3525 t8 = skge_read8(hw, B2_E_0);
57d6fa37 3526 if (is_genesis(hw)) {
baef58b1
SH		 3527 if (t8 == 3) {
3528 /* special case: 4 x 64k x 36, offset = 0x80000 */
279e1dab
LT		 3529 hw->ram_size = 0x100000;
3530 hw->ram_offset = 0x80000;
baef58b1
SH		 3531 } else
3532 hw->ram_size = t8 * 512;
67777f9b 3533 } else if (t8 == 0)
279e1dab
LT		 3534 hw->ram_size = 0x20000;
3535 else
3536 hw->ram_size = t8 * 4096;
baef58b1 3537
4ebabfcb 3538 hw->intr_mask = IS_HW_ERR;
cfc3ed79 3539
4ebabfcb 3540 /* Use PHY IRQ for all but fiber based Genesis board */
57d6fa37 3541 if (!(is_genesis(hw) && hw->phy_type == SK_PHY_XMAC))
64f6b64d
SH		 3542 hw->intr_mask |= IS_EXT_REG;
3543
57d6fa37 3544 if (is_genesis(hw))
baef58b1
SH		 3545 genesis_init(hw);
3546 else {
3547 /* switch power to VCC (WA for VAUX problem) */
3548 skge_write8(hw, B0_POWER_CTRL,
3549 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
adba9e23 3550
050ec18a
SH		 3551 /* avoid boards with stuck Hardware error bits */
3552 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3553 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
1479d13c 3554 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
050ec18a
SH		 3555 hw->intr_mask &= ~IS_HW_ERR;
3556 }
3557
adba9e23
SH		 3558 /* Clear PHY COMA */
3559 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3560 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3561 reg &= ~PCI_PHY_COMA;
3562 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3563 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3564
3565
981d0377 3566 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 3567 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3568 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 3569 }
3570 }
3571
3572 /* turn off hardware timer (unused) */
3573 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3574 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3575 skge_write8(hw, B0_LED, LED_STAT_ON);
3576
3577 /* enable the Tx Arbiters */
981d0377 3578 for (i = 0; i < hw->ports; i++)
6b0c1480 3579 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 3580
3581 /* Initialize ram interface */
3582 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3583
3584 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3585 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3586 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3587 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3588 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3589 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3590 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3591 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3592 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3593 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3594 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3595 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3596
3597 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3598
3599 /* Set interrupt moderation for Transmit only
3600 * Receive interrupts avoided by NAPI
3601 */
3602 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3603 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3604 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3605
baef58b1
SH		 3606 skge_write32(hw, B0_IMSK, hw->intr_mask);
3607
981d0377 3608 for (i = 0; i < hw->ports; i++) {
57d6fa37 3609 if (is_genesis(hw))
baef58b1
SH		 3610 genesis_reset(hw, i);
3611 else
3612 yukon_reset(hw, i);
3613 }
baef58b1
SH		 3614
3615 return 0;
3616}
3617
678aa1f6
SH		 3618
3619#ifdef CONFIG_SKGE_DEBUG
3620
3621static struct dentry *skge_debug;
3622
3623static int skge_debug_show(struct seq_file *seq, void *v)
3624{
3625 struct net_device *dev = seq->private;
3626 const struct skge_port *skge = netdev_priv(dev);
3627 const struct skge_hw *hw = skge->hw;
3628 const struct skge_element *e;
3629
3630 if (!netif_running(dev))
3631 return -ENETDOWN;
3632
3633 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3634 skge_read32(hw, B0_IMSK));
3635
3636 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3637 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3638 const struct skge_tx_desc *t = e->desc;
3639 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3640 t->control, t->dma_hi, t->dma_lo, t->status,
3641 t->csum_offs, t->csum_write, t->csum_start);
3642 }
3643
2381a55c 3644 seq_printf(seq, "\nRx Ring:\n");
678aa1f6
SH		 3645 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3646 const struct skge_rx_desc *r = e->desc;
3647
3648 if (r->control & BMU_OWN)
3649 break;
3650
3651 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3652 r->control, r->dma_hi, r->dma_lo, r->status,
3653 r->timestamp, r->csum1, r->csum1_start);
3654 }
3655
3656 return 0;
3657}
3658
3659static int skge_debug_open(struct inode *inode, struct file *file)
3660{
3661 return single_open(file, skge_debug_show, inode->i_private);
3662}
3663
3664static const struct file_operations skge_debug_fops = {
3665 .owner = THIS_MODULE,
3666 .open = skge_debug_open,
3667 .read = seq_read,
3668 .llseek = seq_lseek,
3669 .release = single_release,
3670};
3671
3672/*
3673 * Use network device events to create/remove/rename
3674 * debugfs file entries
3675 */
3676static int skge_device_event(struct notifier_block *unused,
3677 unsigned long event, void *ptr)
3678{
3679 struct net_device *dev = ptr;
3680 struct skge_port *skge;
3681 struct dentry *d;
3682
f80d032b 3683 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
678aa1f6
SH		 3684 goto done;
3685
3686 skge = netdev_priv(dev);
67777f9b 3687 switch (event) {
678aa1f6
SH		 3688 case NETDEV_CHANGENAME:
3689 if (skge->debugfs) {
3690 d = debugfs_rename(skge_debug, skge->debugfs,
3691 skge_debug, dev->name);
3692 if (d)
3693 skge->debugfs = d;
3694 else {
f15063cd 3695 netdev_info(dev, "rename failed\n");
678aa1f6
SH		 3696 debugfs_remove(skge->debugfs);
3697 }
3698 }
3699 break;
3700
3701 case NETDEV_GOING_DOWN:
3702 if (skge->debugfs) {
3703 debugfs_remove(skge->debugfs);
3704 skge->debugfs = NULL;
3705 }
3706 break;
3707
3708 case NETDEV_UP:
3709 d = debugfs_create_file(dev->name, S_IRUGO,
3710 skge_debug, dev,
3711 &skge_debug_fops);
3712 if (!d || IS_ERR(d))
f15063cd 3713 netdev_info(dev, "debugfs create failed\n");
678aa1f6
SH		 3714 else
3715 skge->debugfs = d;
3716 break;
3717 }
3718
3719done:
3720 return NOTIFY_DONE;
3721}
3722
3723static struct notifier_block skge_notifier = {
3724 .notifier_call = skge_device_event,
3725};
3726
3727
3728static __init void skge_debug_init(void)
3729{
3730 struct dentry *ent;
3731
3732 ent = debugfs_create_dir("skge", NULL);
3733 if (!ent || IS_ERR(ent)) {
f15063cd 3734 pr_info("debugfs create directory failed\n");
678aa1f6
SH		 3735 return;
3736 }
3737
3738 skge_debug = ent;
3739 register_netdevice_notifier(&skge_notifier);
3740}
3741
3742static __exit void skge_debug_cleanup(void)
3743{
3744 if (skge_debug) {
3745 unregister_netdevice_notifier(&skge_notifier);
3746 debugfs_remove(skge_debug);
3747 skge_debug = NULL;
3748 }
3749}
3750
3751#else
3752#define skge_debug_init()
3753#define skge_debug_cleanup()
3754#endif
3755
f80d032b
SH		 3756static const struct net_device_ops skge_netdev_ops = {
3757 .ndo_open = skge_up,
3758 .ndo_stop = skge_down,
00829823 3759 .ndo_start_xmit = skge_xmit_frame,
f80d032b
SH		 3760 .ndo_do_ioctl = skge_ioctl,
3761 .ndo_get_stats = skge_get_stats,
3762 .ndo_tx_timeout = skge_tx_timeout,
3763 .ndo_change_mtu = skge_change_mtu,
3764 .ndo_validate_addr = eth_validate_addr,
3765 .ndo_set_multicast_list = skge_set_multicast,
3766 .ndo_set_mac_address = skge_set_mac_address,
3767#ifdef CONFIG_NET_POLL_CONTROLLER
3768 .ndo_poll_controller = skge_netpoll,
3769#endif
3770};
3771
3772
baef58b1 3773/* Initialize network device */
981d0377
SH		 3774static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3775 int highmem)
baef58b1
SH		 3776{
3777 struct skge_port *skge;
3778 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3779
3780 if (!dev) {
1479d13c 3781 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
baef58b1
SH		 3782 return NULL;
3783 }
3784
baef58b1 3785 SET_NETDEV_DEV(dev, &hw->pdev->dev);
f80d032b
SH		 3786 dev->netdev_ops = &skge_netdev_ops;
3787 dev->ethtool_ops = &skge_ethtool_ops;
baef58b1 3788 dev->watchdog_timeo = TX_WATCHDOG;
baef58b1 3789 dev->irq = hw->pdev->irq;
513f533e 3790
981d0377
SH		 3791 if (highmem)
3792 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3793
3794 skge = netdev_priv(dev);
bea3348e 3795 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
baef58b1
SH		 3796 skge->netdev = dev;
3797 skge->hw = hw;
3798 skge->msg_enable = netif_msg_init(debug, default_msg);
9cbe330f 3799
baef58b1
SH		 3800 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3801 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3802
3803 /* Auto speed and flow control */
3804 skge->autoneg = AUTONEG_ENABLE;
5d5c8e03 3805 skge->flow_control = FLOW_MODE_SYM_OR_REM;
baef58b1
SH		 3806 skge->duplex = -1;
3807 skge->speed = -1;
31b619c5 3808 skge->advertising = skge_supported_modes(hw);
5b982c5b 3809
7b55a4a3 3810 if (device_can_wakeup(&hw->pdev->dev)) {
5b982c5b 3811 skge->wol = wol_supported(hw) & WAKE_MAGIC;
7b55a4a3
RW		 3812 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3813 }
baef58b1
SH		 3814
3815 hw->dev[port] = dev;
3816
3817 skge->port = port;
3818
64f6b64d 3819 /* Only used for Genesis XMAC */
57d6fa37 3820 if (is_genesis(hw))
3821 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
3822 else {
e92702b1
MM		 3823 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3824 NETIF_F_RXCSUM;
3825 dev->features |= dev->hw_features;
baef58b1
SH		 3826 }
3827
3828 /* read the mac address */
3829 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
56230d53 3830 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
baef58b1 3831
baef58b1
SH		 3832 return dev;
3833}
3834
3835static void __devinit skge_show_addr(struct net_device *dev)
3836{
3837 const struct skge_port *skge = netdev_priv(dev);
3838
d707204c 3839 netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr);
baef58b1
SH		 3840}
3841
392bd0cb
SG		 3842static int only_32bit_dma;
3843
baef58b1
SH		 3844static int __devinit skge_probe(struct pci_dev *pdev,
3845 const struct pci_device_id *ent)
3846{
3847 struct net_device *dev, *dev1;
3848 struct skge_hw *hw;
3849 int err, using_dac = 0;
3850
203babb6
SH		 3851 err = pci_enable_device(pdev);
3852 if (err) {
1479d13c 3853 dev_err(&pdev->dev, "cannot enable PCI device\n");
baef58b1
SH		 3854 goto err_out;
3855 }
3856
203babb6
SH		 3857 err = pci_request_regions(pdev, DRV_NAME);
3858 if (err) {
1479d13c 3859 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
baef58b1
SH		 3860 goto err_out_disable_pdev;
3861 }
3862
3863 pci_set_master(pdev);
3864
392bd0cb 3865 if (!only_32bit_dma && !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
baef58b1 3866 using_dac = 1;
6a35528a 3867 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
284901a9 3868 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
93aea718 3869 using_dac = 0;
284901a9 3870 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
93aea718
SH		 3871 }
3872
3873 if (err) {
1479d13c 3874 dev_err(&pdev->dev, "no usable DMA configuration\n");
93aea718 3875 goto err_out_free_regions;
baef58b1
SH		 3876 }
3877
3878#ifdef __BIG_ENDIAN
8f3f8193 3879 /* byte swap descriptors in hardware */
baef58b1
SH		 3880 {
3881 u32 reg;
3882
3883 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3884 reg |= PCI_REV_DESC;
3885 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3886 }
3887#endif
3888
3889 err = -ENOMEM;
415e69e6 3890 /* space for skge@pci:0000:04:00.0 */
67777f9b 3891 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
415e69e6 3892 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
baef58b1 3893 if (!hw) {
1479d13c 3894 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
baef58b1
SH		 3895 goto err_out_free_regions;
3896 }
415e69e6 3897 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
baef58b1 3898
baef58b1 3899 hw->pdev = pdev;
d38efdd6 3900 spin_lock_init(&hw->hw_lock);
9cbe330f 3901 spin_lock_init(&hw->phy_lock);
164165da 3902 tasklet_init(&hw->phy_task, skge_extirq, (unsigned long) hw);
baef58b1
SH		 3903
3904 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3905 if (!hw->regs) {
1479d13c 3906 dev_err(&pdev->dev, "cannot map device registers\n");
baef58b1
SH		 3907 goto err_out_free_hw;
3908 }
3909
baef58b1
SH		 3910 err = skge_reset(hw);
3911 if (err)
ccdaa2a9 3912 goto err_out_iounmap;
baef58b1 3913
f15063cd
JP		 3914 pr_info("%s addr 0x%llx irq %d chip %s rev %d\n",
3915 DRV_VERSION,
3916 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3917 skge_board_name(hw), hw->chip_rev);
baef58b1 3918
ccdaa2a9
SH		 3919 dev = skge_devinit(hw, 0, using_dac);
3920 if (!dev)
baef58b1
SH		 3921 goto err_out_led_off;
3922
fae87592 3923 /* Some motherboards are broken and has zero in ROM. */
1479d13c
SH		 3924 if (!is_valid_ether_addr(dev->dev_addr))
3925 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
631ae320 3926
203babb6
SH		 3927 err = register_netdev(dev);
3928 if (err) {
1479d13c 3929 dev_err(&pdev->dev, "cannot register net device\n");
baef58b1
SH		 3930 goto err_out_free_netdev;
3931 }
3932
415e69e6 3933 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, hw->irq_name, hw);
ccdaa2a9 3934 if (err) {
1479d13c 3935 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
ccdaa2a9
SH		 3936 dev->name, pdev->irq);
3937 goto err_out_unregister;
3938 }
baef58b1
SH		 3939 skge_show_addr(dev);
3940
f1914226
MM		 3941 if (hw->ports > 1) {
3942 dev1 = skge_devinit(hw, 1, using_dac);
3943 if (dev1 && register_netdev(dev1) == 0)
baef58b1
SH		 3944 skge_show_addr(dev1);
3945 else {
3946 /* Failure to register second port need not be fatal */
1479d13c 3947 dev_warn(&pdev->dev, "register of second port failed\n");
baef58b1 3948 hw->dev[1] = NULL;
f1914226
MM		 3949 hw->ports = 1;
3950 if (dev1)
3951 free_netdev(dev1);
baef58b1
SH		 3952 }
3953 }
ccdaa2a9 3954 pci_set_drvdata(pdev, hw);
baef58b1
SH		 3955
3956 return 0;
3957
ccdaa2a9
SH		 3958err_out_unregister:
3959 unregister_netdev(dev);
baef58b1
SH		 3960err_out_free_netdev:
3961 free_netdev(dev);
3962err_out_led_off:
3963 skge_write16(hw, B0_LED, LED_STAT_OFF);
baef58b1
SH		 3964err_out_iounmap:
3965 iounmap(hw->regs);
3966err_out_free_hw:
3967 kfree(hw);
3968err_out_free_regions:
3969 pci_release_regions(pdev);
3970err_out_disable_pdev:
3971 pci_disable_device(pdev);
3972 pci_set_drvdata(pdev, NULL);
3973err_out:
3974 return err;
3975}
3976
3977static void __devexit skge_remove(struct pci_dev *pdev)
3978{
3979 struct skge_hw *hw = pci_get_drvdata(pdev);
3980 struct net_device *dev0, *dev1;
3981
95566065 3982 if (!hw)
baef58b1
SH		 3983 return;
3984
67777f9b
JP		 3985 dev1 = hw->dev[1];
3986 if (dev1)
baef58b1
SH		 3987 unregister_netdev(dev1);
3988 dev0 = hw->dev[0];
3989 unregister_netdev(dev0);
3990
9cbe330f
SH		 3991 tasklet_disable(&hw->phy_task);
3992
7c442fa1
SH		 3993 spin_lock_irq(&hw->hw_lock);
3994 hw->intr_mask = 0;
46a60f2d 3995 skge_write32(hw, B0_IMSK, 0);
78bc2186 3996 skge_read32(hw, B0_IMSK);
7c442fa1
SH		 3997 spin_unlock_irq(&hw->hw_lock);
3998
46a60f2d 3999 skge_write16(hw, B0_LED, LED_STAT_OFF);
46a60f2d
SH		 4000 skge_write8(hw, B0_CTST, CS_RST_SET);
4001
baef58b1
SH		 4002 free_irq(pdev->irq, hw);
4003 pci_release_regions(pdev);
4004 pci_disable_device(pdev);
4005 if (dev1)
4006 free_netdev(dev1);
4007 free_netdev(dev0);
46a60f2d 4008
baef58b1
SH		 4009 iounmap(hw->regs);
4010 kfree(hw);
4011 pci_set_drvdata(pdev, NULL);
4012}
4013
4014#ifdef CONFIG_PM
7dbf6acd 4015static int skge_suspend(struct device *dev)
baef58b1 4016{
7dbf6acd 4017 struct pci_dev *pdev = to_pci_dev(dev);
baef58b1 4018 struct skge_hw *hw = pci_get_drvdata(pdev);
7dbf6acd 4019 int i;
a504e64a 4020
e3b7df17
SH		 4021 if (!hw)
4022 return 0;
4023
d38efdd6 4024 for (i = 0; i < hw->ports; i++) {
baef58b1 4025 struct net_device *dev = hw->dev[i];
a504e64a 4026 struct skge_port *skge = netdev_priv(dev);
baef58b1 4027
a504e64a
SH		 4028 if (netif_running(dev))
4029 skge_down(dev);
7dbf6acd 4030
a504e64a
SH		 4031 if (skge->wol)
4032 skge_wol_init(skge);
baef58b1
SH		 4033 }
4034
d38efdd6 4035 skge_write32(hw, B0_IMSK, 0);
5177b324 4036
baef58b1
SH		 4037 return 0;
4038}
4039
7dbf6acd 4040static int skge_resume(struct device *dev)
baef58b1 4041{
7dbf6acd 4042 struct pci_dev *pdev = to_pci_dev(dev);
baef58b1 4043 struct skge_hw *hw = pci_get_drvdata(pdev);
d38efdd6 4044 int i, err;
baef58b1 4045
e3b7df17
SH		 4046 if (!hw)
4047 return 0;
4048
d38efdd6
SH		 4049 err = skge_reset(hw);
4050 if (err)
4051 goto out;
baef58b1 4052
d38efdd6 4053 for (i = 0; i < hw->ports; i++) {
baef58b1 4054 struct net_device *dev = hw->dev[i];
d38efdd6 4055
d38efdd6
SH		 4056 if (netif_running(dev)) {
4057 err = skge_up(dev);
4058
4059 if (err) {
f15063cd 4060 netdev_err(dev, "could not up: %d\n", err);
edd702e8 4061 dev_close(dev);
d38efdd6
SH		 4062 goto out;
4063 }
baef58b1
SH		 4064 }
4065 }
d38efdd6
SH		 4066out:
4067 return err;
baef58b1 4068}
7dbf6acd 4069
4070static SIMPLE_DEV_PM_OPS(skge_pm_ops, skge_suspend, skge_resume);
4071#define SKGE_PM_OPS (&skge_pm_ops)
4072
4073#else
4074
4075#define SKGE_PM_OPS NULL
baef58b1
SH		 4076#endif
4077
692412b3
SH		 4078static void skge_shutdown(struct pci_dev *pdev)
4079{
4080 struct skge_hw *hw = pci_get_drvdata(pdev);
7dbf6acd 4081 int i;
692412b3 4082
e3b7df17
SH		 4083 if (!hw)
4084 return;
4085
692412b3
SH		 4086 for (i = 0; i < hw->ports; i++) {
4087 struct net_device *dev = hw->dev[i];
4088 struct skge_port *skge = netdev_priv(dev);
4089
4090 if (skge->wol)
4091 skge_wol_init(skge);
692412b3
SH		 4092 }
4093
7dbf6acd 4094 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
692412b3 4095 pci_set_power_state(pdev, PCI_D3hot);
692412b3
SH		 4096}
4097
baef58b1
SH		 4098static struct pci_driver skge_driver = {
4099 .name = DRV_NAME,
4100 .id_table = skge_id_table,
4101 .probe = skge_probe,
4102 .remove = __devexit_p(skge_remove),
692412b3 4103 .shutdown = skge_shutdown,
7dbf6acd 4104 .driver.pm = SKGE_PM_OPS,
baef58b1
SH		 4105};
4106
392bd0cb
SG		 4107static struct dmi_system_id skge_32bit_dma_boards[] = {
4108 {
4109 .ident = "Gigabyte nForce boards",
4110 .matches = {
4111 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co"),
4112 DMI_MATCH(DMI_BOARD_NAME, "nForce"),
4113 },
4114 },
4115 {}
4116};
4117
baef58b1
SH		 4118static int __init skge_init_module(void)
4119{
392bd0cb
SG		 4120 if (dmi_check_system(skge_32bit_dma_boards))
4121 only_32bit_dma = 1;
678aa1f6 4122 skge_debug_init();
29917620 4123 return pci_register_driver(&skge_driver);
baef58b1
SH		 4124}
4125
4126static void __exit skge_cleanup_module(void)
4127{
4128 pci_unregister_driver(&skge_driver);
678aa1f6 4129 skge_debug_cleanup();
baef58b1
SH		 4130}
4131
4132module_init(skge_init_module);
4133module_exit(skge_cleanup_module);
Linux kernel - Deliverables
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