Commit | Line | Data |
---|---|---|
baef58b1 SH |
1 | /* |
2 | * New driver for Marvell Yukon chipset and SysKonnect Gigabit | |
3 | * Ethernet adapters. Based on earlier sk98lin, e100 and | |
4 | * FreeBSD if_sk drivers. | |
5 | * | |
6 | * This driver intentionally does not support all the features | |
7 | * of the original driver such as link fail-over and link management because | |
8 | * those should be done at higher levels. | |
9 | * | |
747802ab | 10 | * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org> |
baef58b1 SH |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
798b6b19 | 14 | * the Free Software Foundation; either version 2 of the License. |
baef58b1 SH |
15 | * |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | */ | |
25 | ||
f15063cd JP |
26 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
27 | ||
14c85021 | 28 | #include <linux/in.h> |
baef58b1 SH |
29 | #include <linux/kernel.h> |
30 | #include <linux/module.h> | |
31 | #include <linux/moduleparam.h> | |
32 | #include <linux/netdevice.h> | |
33 | #include <linux/etherdevice.h> | |
34 | #include <linux/ethtool.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/if_vlan.h> | |
37 | #include <linux/ip.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/crc32.h> | |
4075400b | 40 | #include <linux/dma-mapping.h> |
678aa1f6 | 41 | #include <linux/debugfs.h> |
d43c36dc | 42 | #include <linux/sched.h> |
678aa1f6 | 43 | #include <linux/seq_file.h> |
2cd8e5d3 | 44 | #include <linux/mii.h> |
5a0e3ad6 | 45 | #include <linux/slab.h> |
392bd0cb | 46 | #include <linux/dmi.h> |
70c71606 | 47 | #include <linux/prefetch.h> |
baef58b1 SH |
48 | #include <asm/irq.h> |
49 | ||
50 | #include "skge.h" | |
51 | ||
52 | #define DRV_NAME "skge" | |
bf9f56d5 | 53 | #define DRV_VERSION "1.13" |
baef58b1 SH |
54 | |
55 | #define DEFAULT_TX_RING_SIZE 128 | |
56 | #define DEFAULT_RX_RING_SIZE 512 | |
57 | #define MAX_TX_RING_SIZE 1024 | |
9db96479 | 58 | #define TX_LOW_WATER (MAX_SKB_FRAGS + 1) |
baef58b1 | 59 | #define MAX_RX_RING_SIZE 4096 |
19a33d4e SH |
60 | #define RX_COPY_THRESHOLD 128 |
61 | #define RX_BUF_SIZE 1536 | |
baef58b1 SH |
62 | #define PHY_RETRIES 1000 |
63 | #define ETH_JUMBO_MTU 9000 | |
64 | #define TX_WATCHDOG (5 * HZ) | |
65 | #define NAPI_WEIGHT 64 | |
6abebb53 | 66 | #define BLINK_MS 250 |
501fb72d | 67 | #define LINK_HZ HZ |
baef58b1 | 68 | |
afa151b9 SH |
69 | #define SKGE_EEPROM_MAGIC 0x9933aabb |
70 | ||
71 | ||
baef58b1 | 72 | MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver"); |
65ebe634 | 73 | MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>"); |
baef58b1 SH |
74 | MODULE_LICENSE("GPL"); |
75 | MODULE_VERSION(DRV_VERSION); | |
76 | ||
67777f9b JP |
77 | static const u32 default_msg = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
78 | NETIF_MSG_LINK | NETIF_MSG_IFUP | | |
79 | NETIF_MSG_IFDOWN); | |
baef58b1 SH |
80 | |
81 | static int debug = -1; /* defaults above */ | |
82 | module_param(debug, int, 0); | |
83 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
84 | ||
a3aa1884 | 85 | static DEFINE_PCI_DEVICE_TABLE(skge_id_table) = { |
275834d1 SH |
86 | { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) }, |
87 | { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) }, | |
88 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) }, | |
89 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) }, | |
f19841f5 | 90 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) }, |
2d2a3871 | 91 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */ |
275834d1 SH |
92 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) }, |
93 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */ | |
94 | { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) }, | |
275834d1 | 95 | { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) }, |
f19841f5 | 96 | { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 }, |
baef58b1 SH |
97 | { 0 } |
98 | }; | |
99 | MODULE_DEVICE_TABLE(pci, skge_id_table); | |
100 | ||
101 | static int skge_up(struct net_device *dev); | |
102 | static int skge_down(struct net_device *dev); | |
ee294dcd | 103 | static void skge_phy_reset(struct skge_port *skge); |
513f533e | 104 | static void skge_tx_clean(struct net_device *dev); |
2cd8e5d3 SH |
105 | static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); |
106 | static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); | |
baef58b1 SH |
107 | static void genesis_get_stats(struct skge_port *skge, u64 *data); |
108 | static void yukon_get_stats(struct skge_port *skge, u64 *data); | |
109 | static void yukon_init(struct skge_hw *hw, int port); | |
baef58b1 | 110 | static void genesis_mac_init(struct skge_hw *hw, int port); |
45bada65 | 111 | static void genesis_link_up(struct skge_port *skge); |
f80d032b | 112 | static void skge_set_multicast(struct net_device *dev); |
baef58b1 | 113 | |
7e676d91 | 114 | /* Avoid conditionals by using array */ |
baef58b1 SH |
115 | static const int txqaddr[] = { Q_XA1, Q_XA2 }; |
116 | static const int rxqaddr[] = { Q_R1, Q_R2 }; | |
117 | static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F }; | |
118 | static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F }; | |
4ebabfcb SH |
119 | static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F }; |
120 | static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 }; | |
baef58b1 | 121 | |
baef58b1 SH |
122 | static int skge_get_regs_len(struct net_device *dev) |
123 | { | |
c3f8be96 | 124 | return 0x4000; |
baef58b1 SH |
125 | } |
126 | ||
127 | /* | |
c3f8be96 SH |
128 | * Returns copy of whole control register region |
129 | * Note: skip RAM address register because accessing it will | |
130 | * cause bus hangs! | |
baef58b1 SH |
131 | */ |
132 | static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
133 | void *p) | |
134 | { | |
135 | const struct skge_port *skge = netdev_priv(dev); | |
baef58b1 | 136 | const void __iomem *io = skge->hw->regs; |
baef58b1 SH |
137 | |
138 | regs->version = 1; | |
c3f8be96 SH |
139 | memset(p, 0, regs->len); |
140 | memcpy_fromio(p, io, B3_RAM_ADDR); | |
baef58b1 | 141 | |
c3f8be96 SH |
142 | memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, |
143 | regs->len - B3_RI_WTO_R1); | |
baef58b1 SH |
144 | } |
145 | ||
8f3f8193 | 146 | /* Wake on Lan only supported on Yukon chips with rev 1 or above */ |
a504e64a | 147 | static u32 wol_supported(const struct skge_hw *hw) |
baef58b1 | 148 | { |
d17ecb23 | 149 | if (hw->chip_id == CHIP_ID_GENESIS) |
a504e64a | 150 | return 0; |
d17ecb23 SH |
151 | |
152 | if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) | |
153 | return 0; | |
154 | ||
155 | return WAKE_MAGIC | WAKE_PHY; | |
a504e64a SH |
156 | } |
157 | ||
a504e64a SH |
158 | static void skge_wol_init(struct skge_port *skge) |
159 | { | |
160 | struct skge_hw *hw = skge->hw; | |
161 | int port = skge->port; | |
692412b3 | 162 | u16 ctrl; |
a504e64a | 163 | |
a504e64a SH |
164 | skge_write16(hw, B0_CTST, CS_RST_CLR); |
165 | skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
166 | ||
692412b3 SH |
167 | /* Turn on Vaux */ |
168 | skge_write8(hw, B0_POWER_CTRL, | |
169 | PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); | |
a504e64a | 170 | |
692412b3 SH |
171 | /* WA code for COMA mode -- clear PHY reset */ |
172 | if (hw->chip_id == CHIP_ID_YUKON_LITE && | |
173 | hw->chip_rev >= CHIP_REV_YU_LITE_A3) { | |
174 | u32 reg = skge_read32(hw, B2_GP_IO); | |
175 | reg |= GP_DIR_9; | |
176 | reg &= ~GP_IO_9; | |
177 | skge_write32(hw, B2_GP_IO, reg); | |
178 | } | |
a504e64a | 179 | |
692412b3 SH |
180 | skge_write32(hw, SK_REG(port, GPHY_CTRL), |
181 | GPC_DIS_SLEEP | | |
182 | GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 | | |
183 | GPC_ANEG_1 | GPC_RST_SET); | |
a504e64a | 184 | |
692412b3 SH |
185 | skge_write32(hw, SK_REG(port, GPHY_CTRL), |
186 | GPC_DIS_SLEEP | | |
187 | GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 | | |
188 | GPC_ANEG_1 | GPC_RST_CLR); | |
189 | ||
190 | skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); | |
191 | ||
192 | /* Force to 10/100 skge_reset will re-enable on resume */ | |
193 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, | |
67777f9b JP |
194 | (PHY_AN_100FULL | PHY_AN_100HALF | |
195 | PHY_AN_10FULL | PHY_AN_10HALF | PHY_AN_CSMA)); | |
692412b3 SH |
196 | /* no 1000 HD/FD */ |
197 | gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0); | |
198 | gm_phy_write(hw, port, PHY_MARV_CTRL, | |
199 | PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE | | |
200 | PHY_CT_RE_CFG | PHY_CT_DUP_MD); | |
a504e64a | 201 | |
a504e64a SH |
202 | |
203 | /* Set GMAC to no flow control and auto update for speed/duplex */ | |
204 | gma_write16(hw, port, GM_GP_CTRL, | |
205 | GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA| | |
206 | GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS); | |
207 | ||
208 | /* Set WOL address */ | |
209 | memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), | |
210 | skge->netdev->dev_addr, ETH_ALEN); | |
211 | ||
212 | /* Turn on appropriate WOL control bits */ | |
213 | skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); | |
214 | ctrl = 0; | |
215 | if (skge->wol & WAKE_PHY) | |
216 | ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT; | |
217 | else | |
218 | ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT; | |
219 | ||
220 | if (skge->wol & WAKE_MAGIC) | |
221 | ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT; | |
222 | else | |
a419aef8 | 223 | ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT; |
a504e64a SH |
224 | |
225 | ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT; | |
226 | skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); | |
227 | ||
228 | /* block receiver */ | |
229 | skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); | |
baef58b1 SH |
230 | } |
231 | ||
232 | static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
233 | { | |
234 | struct skge_port *skge = netdev_priv(dev); | |
235 | ||
a504e64a SH |
236 | wol->supported = wol_supported(skge->hw); |
237 | wol->wolopts = skge->wol; | |
baef58b1 SH |
238 | } |
239 | ||
240 | static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
241 | { | |
242 | struct skge_port *skge = netdev_priv(dev); | |
243 | struct skge_hw *hw = skge->hw; | |
244 | ||
8e95a202 JP |
245 | if ((wol->wolopts & ~wol_supported(hw)) || |
246 | !device_can_wakeup(&hw->pdev->dev)) | |
baef58b1 SH |
247 | return -EOPNOTSUPP; |
248 | ||
a504e64a | 249 | skge->wol = wol->wolopts; |
5177b324 RW |
250 | |
251 | device_set_wakeup_enable(&hw->pdev->dev, skge->wol); | |
252 | ||
baef58b1 SH |
253 | return 0; |
254 | } | |
255 | ||
8f3f8193 SH |
256 | /* Determine supported/advertised modes based on hardware. |
257 | * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx | |
31b619c5 SH |
258 | */ |
259 | static u32 skge_supported_modes(const struct skge_hw *hw) | |
260 | { | |
261 | u32 supported; | |
262 | ||
5e1705dd | 263 | if (hw->copper) { |
67777f9b JP |
264 | supported = (SUPPORTED_10baseT_Half | |
265 | SUPPORTED_10baseT_Full | | |
266 | SUPPORTED_100baseT_Half | | |
267 | SUPPORTED_100baseT_Full | | |
268 | SUPPORTED_1000baseT_Half | | |
269 | SUPPORTED_1000baseT_Full | | |
270 | SUPPORTED_Autoneg | | |
271 | SUPPORTED_TP); | |
31b619c5 SH |
272 | |
273 | if (hw->chip_id == CHIP_ID_GENESIS) | |
67777f9b JP |
274 | supported &= ~(SUPPORTED_10baseT_Half | |
275 | SUPPORTED_10baseT_Full | | |
276 | SUPPORTED_100baseT_Half | | |
277 | SUPPORTED_100baseT_Full); | |
31b619c5 SH |
278 | |
279 | else if (hw->chip_id == CHIP_ID_YUKON) | |
280 | supported &= ~SUPPORTED_1000baseT_Half; | |
281 | } else | |
67777f9b JP |
282 | supported = (SUPPORTED_1000baseT_Full | |
283 | SUPPORTED_1000baseT_Half | | |
284 | SUPPORTED_FIBRE | | |
285 | SUPPORTED_Autoneg); | |
31b619c5 SH |
286 | |
287 | return supported; | |
288 | } | |
baef58b1 SH |
289 | |
290 | static int skge_get_settings(struct net_device *dev, | |
291 | struct ethtool_cmd *ecmd) | |
292 | { | |
293 | struct skge_port *skge = netdev_priv(dev); | |
294 | struct skge_hw *hw = skge->hw; | |
295 | ||
296 | ecmd->transceiver = XCVR_INTERNAL; | |
31b619c5 | 297 | ecmd->supported = skge_supported_modes(hw); |
baef58b1 | 298 | |
5e1705dd | 299 | if (hw->copper) { |
baef58b1 SH |
300 | ecmd->port = PORT_TP; |
301 | ecmd->phy_address = hw->phy_addr; | |
31b619c5 | 302 | } else |
baef58b1 | 303 | ecmd->port = PORT_FIBRE; |
baef58b1 SH |
304 | |
305 | ecmd->advertising = skge->advertising; | |
306 | ecmd->autoneg = skge->autoneg; | |
70739497 | 307 | ethtool_cmd_speed_set(ecmd, skge->speed); |
baef58b1 SH |
308 | ecmd->duplex = skge->duplex; |
309 | return 0; | |
310 | } | |
311 | ||
baef58b1 SH |
312 | static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
313 | { | |
314 | struct skge_port *skge = netdev_priv(dev); | |
315 | const struct skge_hw *hw = skge->hw; | |
31b619c5 | 316 | u32 supported = skge_supported_modes(hw); |
9ac1353f | 317 | int err = 0; |
baef58b1 SH |
318 | |
319 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
31b619c5 SH |
320 | ecmd->advertising = supported; |
321 | skge->duplex = -1; | |
322 | skge->speed = -1; | |
baef58b1 | 323 | } else { |
31b619c5 | 324 | u32 setting; |
25db0338 | 325 | u32 speed = ethtool_cmd_speed(ecmd); |
31b619c5 | 326 | |
25db0338 | 327 | switch (speed) { |
baef58b1 | 328 | case SPEED_1000: |
31b619c5 SH |
329 | if (ecmd->duplex == DUPLEX_FULL) |
330 | setting = SUPPORTED_1000baseT_Full; | |
331 | else if (ecmd->duplex == DUPLEX_HALF) | |
332 | setting = SUPPORTED_1000baseT_Half; | |
333 | else | |
334 | return -EINVAL; | |
baef58b1 SH |
335 | break; |
336 | case SPEED_100: | |
31b619c5 SH |
337 | if (ecmd->duplex == DUPLEX_FULL) |
338 | setting = SUPPORTED_100baseT_Full; | |
339 | else if (ecmd->duplex == DUPLEX_HALF) | |
340 | setting = SUPPORTED_100baseT_Half; | |
341 | else | |
342 | return -EINVAL; | |
343 | break; | |
344 | ||
baef58b1 | 345 | case SPEED_10: |
31b619c5 SH |
346 | if (ecmd->duplex == DUPLEX_FULL) |
347 | setting = SUPPORTED_10baseT_Full; | |
348 | else if (ecmd->duplex == DUPLEX_HALF) | |
349 | setting = SUPPORTED_10baseT_Half; | |
350 | else | |
baef58b1 SH |
351 | return -EINVAL; |
352 | break; | |
353 | default: | |
354 | return -EINVAL; | |
355 | } | |
31b619c5 SH |
356 | |
357 | if ((setting & supported) == 0) | |
358 | return -EINVAL; | |
359 | ||
25db0338 | 360 | skge->speed = speed; |
31b619c5 | 361 | skge->duplex = ecmd->duplex; |
baef58b1 SH |
362 | } |
363 | ||
364 | skge->autoneg = ecmd->autoneg; | |
baef58b1 SH |
365 | skge->advertising = ecmd->advertising; |
366 | ||
9ac1353f XZ |
367 | if (netif_running(dev)) { |
368 | skge_down(dev); | |
369 | err = skge_up(dev); | |
370 | if (err) { | |
371 | dev_close(dev); | |
372 | return err; | |
373 | } | |
374 | } | |
ee294dcd | 375 | |
67777f9b | 376 | return 0; |
baef58b1 SH |
377 | } |
378 | ||
379 | static void skge_get_drvinfo(struct net_device *dev, | |
380 | struct ethtool_drvinfo *info) | |
381 | { | |
382 | struct skge_port *skge = netdev_priv(dev); | |
383 | ||
384 | strcpy(info->driver, DRV_NAME); | |
385 | strcpy(info->version, DRV_VERSION); | |
386 | strcpy(info->fw_version, "N/A"); | |
387 | strcpy(info->bus_info, pci_name(skge->hw->pdev)); | |
388 | } | |
389 | ||
390 | static const struct skge_stat { | |
391 | char name[ETH_GSTRING_LEN]; | |
392 | u16 xmac_offset; | |
393 | u16 gma_offset; | |
394 | } skge_stats[] = { | |
395 | { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI }, | |
396 | { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI }, | |
397 | ||
398 | { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK }, | |
399 | { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK }, | |
400 | { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK }, | |
401 | { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK }, | |
402 | { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK }, | |
403 | { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK }, | |
404 | { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE }, | |
405 | { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE }, | |
406 | ||
407 | { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL }, | |
408 | { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL }, | |
409 | { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL }, | |
410 | { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL }, | |
411 | { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR }, | |
412 | { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV }, | |
413 | ||
414 | { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR }, | |
415 | { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT }, | |
416 | { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG }, | |
417 | { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR }, | |
418 | { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR }, | |
419 | }; | |
420 | ||
b9f2c044 | 421 | static int skge_get_sset_count(struct net_device *dev, int sset) |
baef58b1 | 422 | { |
b9f2c044 JG |
423 | switch (sset) { |
424 | case ETH_SS_STATS: | |
425 | return ARRAY_SIZE(skge_stats); | |
426 | default: | |
427 | return -EOPNOTSUPP; | |
428 | } | |
baef58b1 SH |
429 | } |
430 | ||
431 | static void skge_get_ethtool_stats(struct net_device *dev, | |
432 | struct ethtool_stats *stats, u64 *data) | |
433 | { | |
434 | struct skge_port *skge = netdev_priv(dev); | |
435 | ||
436 | if (skge->hw->chip_id == CHIP_ID_GENESIS) | |
437 | genesis_get_stats(skge, data); | |
438 | else | |
439 | yukon_get_stats(skge, data); | |
440 | } | |
441 | ||
442 | /* Use hardware MIB variables for critical path statistics and | |
443 | * transmit feedback not reported at interrupt. | |
444 | * Other errors are accounted for in interrupt handler. | |
445 | */ | |
446 | static struct net_device_stats *skge_get_stats(struct net_device *dev) | |
447 | { | |
448 | struct skge_port *skge = netdev_priv(dev); | |
449 | u64 data[ARRAY_SIZE(skge_stats)]; | |
450 | ||
451 | if (skge->hw->chip_id == CHIP_ID_GENESIS) | |
452 | genesis_get_stats(skge, data); | |
453 | else | |
454 | yukon_get_stats(skge, data); | |
455 | ||
da00772f SH |
456 | dev->stats.tx_bytes = data[0]; |
457 | dev->stats.rx_bytes = data[1]; | |
458 | dev->stats.tx_packets = data[2] + data[4] + data[6]; | |
459 | dev->stats.rx_packets = data[3] + data[5] + data[7]; | |
460 | dev->stats.multicast = data[3] + data[5]; | |
461 | dev->stats.collisions = data[10]; | |
462 | dev->stats.tx_aborted_errors = data[12]; | |
baef58b1 | 463 | |
da00772f | 464 | return &dev->stats; |
baef58b1 SH |
465 | } |
466 | ||
467 | static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
468 | { | |
469 | int i; | |
470 | ||
95566065 | 471 | switch (stringset) { |
baef58b1 SH |
472 | case ETH_SS_STATS: |
473 | for (i = 0; i < ARRAY_SIZE(skge_stats); i++) | |
474 | memcpy(data + i * ETH_GSTRING_LEN, | |
475 | skge_stats[i].name, ETH_GSTRING_LEN); | |
476 | break; | |
477 | } | |
478 | } | |
479 | ||
480 | static void skge_get_ring_param(struct net_device *dev, | |
481 | struct ethtool_ringparam *p) | |
482 | { | |
483 | struct skge_port *skge = netdev_priv(dev); | |
484 | ||
485 | p->rx_max_pending = MAX_RX_RING_SIZE; | |
486 | p->tx_max_pending = MAX_TX_RING_SIZE; | |
487 | p->rx_mini_max_pending = 0; | |
488 | p->rx_jumbo_max_pending = 0; | |
489 | ||
490 | p->rx_pending = skge->rx_ring.count; | |
491 | p->tx_pending = skge->tx_ring.count; | |
492 | p->rx_mini_pending = 0; | |
493 | p->rx_jumbo_pending = 0; | |
494 | } | |
495 | ||
496 | static int skge_set_ring_param(struct net_device *dev, | |
497 | struct ethtool_ringparam *p) | |
498 | { | |
499 | struct skge_port *skge = netdev_priv(dev); | |
e824b3eb | 500 | int err = 0; |
baef58b1 SH |
501 | |
502 | if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE || | |
9db96479 | 503 | p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE) |
baef58b1 SH |
504 | return -EINVAL; |
505 | ||
506 | skge->rx_ring.count = p->rx_pending; | |
507 | skge->tx_ring.count = p->tx_pending; | |
508 | ||
509 | if (netif_running(dev)) { | |
510 | skge_down(dev); | |
3b8bb472 SH |
511 | err = skge_up(dev); |
512 | if (err) | |
513 | dev_close(dev); | |
baef58b1 SH |
514 | } |
515 | ||
e824b3eb | 516 | return err; |
baef58b1 SH |
517 | } |
518 | ||
519 | static u32 skge_get_msglevel(struct net_device *netdev) | |
520 | { | |
521 | struct skge_port *skge = netdev_priv(netdev); | |
522 | return skge->msg_enable; | |
523 | } | |
524 | ||
525 | static void skge_set_msglevel(struct net_device *netdev, u32 value) | |
526 | { | |
527 | struct skge_port *skge = netdev_priv(netdev); | |
528 | skge->msg_enable = value; | |
529 | } | |
530 | ||
531 | static int skge_nway_reset(struct net_device *dev) | |
532 | { | |
533 | struct skge_port *skge = netdev_priv(dev); | |
baef58b1 SH |
534 | |
535 | if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev)) | |
536 | return -EINVAL; | |
537 | ||
ee294dcd | 538 | skge_phy_reset(skge); |
baef58b1 SH |
539 | return 0; |
540 | } | |
541 | ||
baef58b1 SH |
542 | static void skge_get_pauseparam(struct net_device *dev, |
543 | struct ethtool_pauseparam *ecmd) | |
544 | { | |
545 | struct skge_port *skge = netdev_priv(dev); | |
546 | ||
8e95a202 JP |
547 | ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) || |
548 | (skge->flow_control == FLOW_MODE_SYM_OR_REM)); | |
549 | ecmd->tx_pause = (ecmd->rx_pause || | |
550 | (skge->flow_control == FLOW_MODE_LOC_SEND)); | |
baef58b1 | 551 | |
5d5c8e03 | 552 | ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause; |
baef58b1 SH |
553 | } |
554 | ||
555 | static int skge_set_pauseparam(struct net_device *dev, | |
556 | struct ethtool_pauseparam *ecmd) | |
557 | { | |
558 | struct skge_port *skge = netdev_priv(dev); | |
5d5c8e03 | 559 | struct ethtool_pauseparam old; |
9ac1353f | 560 | int err = 0; |
baef58b1 | 561 | |
5d5c8e03 SH |
562 | skge_get_pauseparam(dev, &old); |
563 | ||
564 | if (ecmd->autoneg != old.autoneg) | |
565 | skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC; | |
566 | else { | |
567 | if (ecmd->rx_pause && ecmd->tx_pause) | |
568 | skge->flow_control = FLOW_MODE_SYMMETRIC; | |
569 | else if (ecmd->rx_pause && !ecmd->tx_pause) | |
570 | skge->flow_control = FLOW_MODE_SYM_OR_REM; | |
571 | else if (!ecmd->rx_pause && ecmd->tx_pause) | |
572 | skge->flow_control = FLOW_MODE_LOC_SEND; | |
573 | else | |
574 | skge->flow_control = FLOW_MODE_NONE; | |
575 | } | |
baef58b1 | 576 | |
9ac1353f XZ |
577 | if (netif_running(dev)) { |
578 | skge_down(dev); | |
579 | err = skge_up(dev); | |
580 | if (err) { | |
581 | dev_close(dev); | |
582 | return err; | |
583 | } | |
584 | } | |
5d5c8e03 | 585 | |
baef58b1 SH |
586 | return 0; |
587 | } | |
588 | ||
589 | /* Chip internal frequency for clock calculations */ | |
590 | static inline u32 hwkhz(const struct skge_hw *hw) | |
591 | { | |
187ff3b8 | 592 | return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125; |
baef58b1 SH |
593 | } |
594 | ||
8f3f8193 | 595 | /* Chip HZ to microseconds */ |
baef58b1 SH |
596 | static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks) |
597 | { | |
598 | return (ticks * 1000) / hwkhz(hw); | |
599 | } | |
600 | ||
8f3f8193 | 601 | /* Microseconds to chip HZ */ |
baef58b1 SH |
602 | static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec) |
603 | { | |
604 | return hwkhz(hw) * usec / 1000; | |
605 | } | |
606 | ||
607 | static int skge_get_coalesce(struct net_device *dev, | |
608 | struct ethtool_coalesce *ecmd) | |
609 | { | |
610 | struct skge_port *skge = netdev_priv(dev); | |
611 | struct skge_hw *hw = skge->hw; | |
612 | int port = skge->port; | |
613 | ||
614 | ecmd->rx_coalesce_usecs = 0; | |
615 | ecmd->tx_coalesce_usecs = 0; | |
616 | ||
617 | if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) { | |
618 | u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI)); | |
619 | u32 msk = skge_read32(hw, B2_IRQM_MSK); | |
620 | ||
621 | if (msk & rxirqmask[port]) | |
622 | ecmd->rx_coalesce_usecs = delay; | |
623 | if (msk & txirqmask[port]) | |
624 | ecmd->tx_coalesce_usecs = delay; | |
625 | } | |
626 | ||
627 | return 0; | |
628 | } | |
629 | ||
630 | /* Note: interrupt timer is per board, but can turn on/off per port */ | |
631 | static int skge_set_coalesce(struct net_device *dev, | |
632 | struct ethtool_coalesce *ecmd) | |
633 | { | |
634 | struct skge_port *skge = netdev_priv(dev); | |
635 | struct skge_hw *hw = skge->hw; | |
636 | int port = skge->port; | |
637 | u32 msk = skge_read32(hw, B2_IRQM_MSK); | |
638 | u32 delay = 25; | |
639 | ||
640 | if (ecmd->rx_coalesce_usecs == 0) | |
641 | msk &= ~rxirqmask[port]; | |
642 | else if (ecmd->rx_coalesce_usecs < 25 || | |
643 | ecmd->rx_coalesce_usecs > 33333) | |
644 | return -EINVAL; | |
645 | else { | |
646 | msk |= rxirqmask[port]; | |
647 | delay = ecmd->rx_coalesce_usecs; | |
648 | } | |
649 | ||
650 | if (ecmd->tx_coalesce_usecs == 0) | |
651 | msk &= ~txirqmask[port]; | |
652 | else if (ecmd->tx_coalesce_usecs < 25 || | |
653 | ecmd->tx_coalesce_usecs > 33333) | |
654 | return -EINVAL; | |
655 | else { | |
656 | msk |= txirqmask[port]; | |
657 | delay = min(delay, ecmd->rx_coalesce_usecs); | |
658 | } | |
659 | ||
660 | skge_write32(hw, B2_IRQM_MSK, msk); | |
661 | if (msk == 0) | |
662 | skge_write32(hw, B2_IRQM_CTRL, TIM_STOP); | |
663 | else { | |
664 | skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay)); | |
665 | skge_write32(hw, B2_IRQM_CTRL, TIM_START); | |
666 | } | |
667 | return 0; | |
668 | } | |
669 | ||
6abebb53 SH |
670 | enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST }; |
671 | static void skge_led(struct skge_port *skge, enum led_mode mode) | |
baef58b1 | 672 | { |
6abebb53 SH |
673 | struct skge_hw *hw = skge->hw; |
674 | int port = skge->port; | |
675 | ||
9cbe330f | 676 | spin_lock_bh(&hw->phy_lock); |
baef58b1 | 677 | if (hw->chip_id == CHIP_ID_GENESIS) { |
6abebb53 SH |
678 | switch (mode) { |
679 | case LED_MODE_OFF: | |
64f6b64d SH |
680 | if (hw->phy_type == SK_PHY_BCOM) |
681 | xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF); | |
682 | else { | |
683 | skge_write32(hw, SK_REG(port, TX_LED_VAL), 0); | |
684 | skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF); | |
685 | } | |
6abebb53 SH |
686 | skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); |
687 | skge_write32(hw, SK_REG(port, RX_LED_VAL), 0); | |
688 | skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF); | |
689 | break; | |
baef58b1 | 690 | |
6abebb53 SH |
691 | case LED_MODE_ON: |
692 | skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON); | |
693 | skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON); | |
baef58b1 | 694 | |
6abebb53 SH |
695 | skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); |
696 | skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); | |
baef58b1 | 697 | |
6abebb53 | 698 | break; |
baef58b1 | 699 | |
6abebb53 SH |
700 | case LED_MODE_TST: |
701 | skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON); | |
702 | skge_write32(hw, SK_REG(port, RX_LED_VAL), 100); | |
703 | skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); | |
baef58b1 | 704 | |
64f6b64d SH |
705 | if (hw->phy_type == SK_PHY_BCOM) |
706 | xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON); | |
707 | else { | |
708 | skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON); | |
709 | skge_write32(hw, SK_REG(port, TX_LED_VAL), 100); | |
710 | skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); | |
711 | } | |
712 | ||
6abebb53 | 713 | } |
baef58b1 | 714 | } else { |
6abebb53 SH |
715 | switch (mode) { |
716 | case LED_MODE_OFF: | |
717 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); | |
718 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, | |
719 | PHY_M_LED_MO_DUP(MO_LED_OFF) | | |
720 | PHY_M_LED_MO_10(MO_LED_OFF) | | |
721 | PHY_M_LED_MO_100(MO_LED_OFF) | | |
722 | PHY_M_LED_MO_1000(MO_LED_OFF) | | |
723 | PHY_M_LED_MO_RX(MO_LED_OFF)); | |
724 | break; | |
725 | case LED_MODE_ON: | |
726 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, | |
727 | PHY_M_LED_PULS_DUR(PULS_170MS) | | |
728 | PHY_M_LED_BLINK_RT(BLINK_84MS) | | |
729 | PHY_M_LEDC_TX_CTRL | | |
730 | PHY_M_LEDC_DP_CTRL); | |
46a60f2d | 731 | |
6abebb53 SH |
732 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, |
733 | PHY_M_LED_MO_RX(MO_LED_OFF) | | |
734 | (skge->speed == SPEED_100 ? | |
735 | PHY_M_LED_MO_100(MO_LED_ON) : 0)); | |
736 | break; | |
737 | case LED_MODE_TST: | |
738 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); | |
739 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, | |
740 | PHY_M_LED_MO_DUP(MO_LED_ON) | | |
741 | PHY_M_LED_MO_10(MO_LED_ON) | | |
742 | PHY_M_LED_MO_100(MO_LED_ON) | | |
743 | PHY_M_LED_MO_1000(MO_LED_ON) | | |
744 | PHY_M_LED_MO_RX(MO_LED_ON)); | |
745 | } | |
baef58b1 | 746 | } |
9cbe330f | 747 | spin_unlock_bh(&hw->phy_lock); |
baef58b1 SH |
748 | } |
749 | ||
750 | /* blink LED's for finding board */ | |
a5b9f41c | 751 | static int skge_set_phys_id(struct net_device *dev, |
752 | enum ethtool_phys_id_state state) | |
baef58b1 SH |
753 | { |
754 | struct skge_port *skge = netdev_priv(dev); | |
755 | ||
a5b9f41c | 756 | switch (state) { |
757 | case ETHTOOL_ID_ACTIVE: | |
fce55922 | 758 | return 2; /* cycle on/off twice per second */ |
baef58b1 | 759 | |
a5b9f41c | 760 | case ETHTOOL_ID_ON: |
761 | skge_led(skge, LED_MODE_TST); | |
762 | break; | |
baef58b1 | 763 | |
a5b9f41c | 764 | case ETHTOOL_ID_OFF: |
765 | skge_led(skge, LED_MODE_OFF); | |
766 | break; | |
baef58b1 | 767 | |
a5b9f41c | 768 | case ETHTOOL_ID_INACTIVE: |
769 | /* back to regular LED state */ | |
770 | skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF); | |
771 | } | |
baef58b1 SH |
772 | |
773 | return 0; | |
774 | } | |
775 | ||
afa151b9 SH |
776 | static int skge_get_eeprom_len(struct net_device *dev) |
777 | { | |
778 | struct skge_port *skge = netdev_priv(dev); | |
779 | u32 reg2; | |
780 | ||
781 | pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2); | |
67777f9b | 782 | return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); |
afa151b9 SH |
783 | } |
784 | ||
785 | static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset) | |
786 | { | |
787 | u32 val; | |
788 | ||
789 | pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset); | |
790 | ||
791 | do { | |
792 | pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset); | |
793 | } while (!(offset & PCI_VPD_ADDR_F)); | |
794 | ||
795 | pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val); | |
796 | return val; | |
797 | } | |
798 | ||
799 | static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val) | |
800 | { | |
801 | pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val); | |
802 | pci_write_config_word(pdev, cap + PCI_VPD_ADDR, | |
803 | offset | PCI_VPD_ADDR_F); | |
804 | ||
805 | do { | |
806 | pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset); | |
807 | } while (offset & PCI_VPD_ADDR_F); | |
808 | } | |
809 | ||
810 | static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | |
811 | u8 *data) | |
812 | { | |
813 | struct skge_port *skge = netdev_priv(dev); | |
814 | struct pci_dev *pdev = skge->hw->pdev; | |
815 | int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD); | |
816 | int length = eeprom->len; | |
817 | u16 offset = eeprom->offset; | |
818 | ||
819 | if (!cap) | |
820 | return -EINVAL; | |
821 | ||
822 | eeprom->magic = SKGE_EEPROM_MAGIC; | |
823 | ||
824 | while (length > 0) { | |
825 | u32 val = skge_vpd_read(pdev, cap, offset); | |
826 | int n = min_t(int, length, sizeof(val)); | |
827 | ||
828 | memcpy(data, &val, n); | |
829 | length -= n; | |
830 | data += n; | |
831 | offset += n; | |
832 | } | |
833 | return 0; | |
834 | } | |
835 | ||
836 | static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | |
837 | u8 *data) | |
838 | { | |
839 | struct skge_port *skge = netdev_priv(dev); | |
840 | struct pci_dev *pdev = skge->hw->pdev; | |
841 | int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD); | |
842 | int length = eeprom->len; | |
843 | u16 offset = eeprom->offset; | |
844 | ||
845 | if (!cap) | |
846 | return -EINVAL; | |
847 | ||
848 | if (eeprom->magic != SKGE_EEPROM_MAGIC) | |
849 | return -EINVAL; | |
850 | ||
851 | while (length > 0) { | |
852 | u32 val; | |
853 | int n = min_t(int, length, sizeof(val)); | |
854 | ||
855 | if (n < sizeof(val)) | |
856 | val = skge_vpd_read(pdev, cap, offset); | |
857 | memcpy(&val, data, n); | |
858 | ||
859 | skge_vpd_write(pdev, cap, offset, val); | |
860 | ||
861 | length -= n; | |
862 | data += n; | |
863 | offset += n; | |
864 | } | |
865 | return 0; | |
866 | } | |
867 | ||
7282d491 | 868 | static const struct ethtool_ops skge_ethtool_ops = { |
baef58b1 SH |
869 | .get_settings = skge_get_settings, |
870 | .set_settings = skge_set_settings, | |
871 | .get_drvinfo = skge_get_drvinfo, | |
872 | .get_regs_len = skge_get_regs_len, | |
873 | .get_regs = skge_get_regs, | |
874 | .get_wol = skge_get_wol, | |
875 | .set_wol = skge_set_wol, | |
876 | .get_msglevel = skge_get_msglevel, | |
877 | .set_msglevel = skge_set_msglevel, | |
878 | .nway_reset = skge_nway_reset, | |
879 | .get_link = ethtool_op_get_link, | |
afa151b9 SH |
880 | .get_eeprom_len = skge_get_eeprom_len, |
881 | .get_eeprom = skge_get_eeprom, | |
882 | .set_eeprom = skge_set_eeprom, | |
baef58b1 SH |
883 | .get_ringparam = skge_get_ring_param, |
884 | .set_ringparam = skge_set_ring_param, | |
885 | .get_pauseparam = skge_get_pauseparam, | |
886 | .set_pauseparam = skge_set_pauseparam, | |
887 | .get_coalesce = skge_get_coalesce, | |
888 | .set_coalesce = skge_set_coalesce, | |
baef58b1 | 889 | .get_strings = skge_get_strings, |
a5b9f41c | 890 | .set_phys_id = skge_set_phys_id, |
b9f2c044 | 891 | .get_sset_count = skge_get_sset_count, |
baef58b1 SH |
892 | .get_ethtool_stats = skge_get_ethtool_stats, |
893 | }; | |
894 | ||
895 | /* | |
896 | * Allocate ring elements and chain them together | |
897 | * One-to-one association of board descriptors with ring elements | |
898 | */ | |
c3da1447 | 899 | static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base) |
baef58b1 SH |
900 | { |
901 | struct skge_tx_desc *d; | |
902 | struct skge_element *e; | |
903 | int i; | |
904 | ||
cd861280 | 905 | ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL); |
baef58b1 SH |
906 | if (!ring->start) |
907 | return -ENOMEM; | |
908 | ||
909 | for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) { | |
910 | e->desc = d; | |
911 | if (i == ring->count - 1) { | |
912 | e->next = ring->start; | |
913 | d->next_offset = base; | |
914 | } else { | |
915 | e->next = e + 1; | |
916 | d->next_offset = base + (i+1) * sizeof(*d); | |
917 | } | |
918 | } | |
919 | ring->to_use = ring->to_clean = ring->start; | |
920 | ||
921 | return 0; | |
922 | } | |
923 | ||
19a33d4e SH |
924 | /* Allocate and setup a new buffer for receiving */ |
925 | static void skge_rx_setup(struct skge_port *skge, struct skge_element *e, | |
926 | struct sk_buff *skb, unsigned int bufsize) | |
927 | { | |
928 | struct skge_rx_desc *rd = e->desc; | |
929 | u64 map; | |
baef58b1 SH |
930 | |
931 | map = pci_map_single(skge->hw->pdev, skb->data, bufsize, | |
932 | PCI_DMA_FROMDEVICE); | |
933 | ||
934 | rd->dma_lo = map; | |
935 | rd->dma_hi = map >> 32; | |
936 | e->skb = skb; | |
937 | rd->csum1_start = ETH_HLEN; | |
938 | rd->csum2_start = ETH_HLEN; | |
939 | rd->csum1 = 0; | |
940 | rd->csum2 = 0; | |
941 | ||
942 | wmb(); | |
943 | ||
944 | rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize; | |
10fc51b9 FT |
945 | dma_unmap_addr_set(e, mapaddr, map); |
946 | dma_unmap_len_set(e, maplen, bufsize); | |
baef58b1 SH |
947 | } |
948 | ||
19a33d4e SH |
949 | /* Resume receiving using existing skb, |
950 | * Note: DMA address is not changed by chip. | |
951 | * MTU not changed while receiver active. | |
952 | */ | |
5a011447 | 953 | static inline void skge_rx_reuse(struct skge_element *e, unsigned int size) |
19a33d4e SH |
954 | { |
955 | struct skge_rx_desc *rd = e->desc; | |
956 | ||
957 | rd->csum2 = 0; | |
958 | rd->csum2_start = ETH_HLEN; | |
959 | ||
960 | wmb(); | |
961 | ||
962 | rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size; | |
963 | } | |
964 | ||
965 | ||
966 | /* Free all buffers in receive ring, assumes receiver stopped */ | |
baef58b1 SH |
967 | static void skge_rx_clean(struct skge_port *skge) |
968 | { | |
969 | struct skge_hw *hw = skge->hw; | |
970 | struct skge_ring *ring = &skge->rx_ring; | |
971 | struct skge_element *e; | |
972 | ||
19a33d4e SH |
973 | e = ring->start; |
974 | do { | |
baef58b1 SH |
975 | struct skge_rx_desc *rd = e->desc; |
976 | rd->control = 0; | |
19a33d4e SH |
977 | if (e->skb) { |
978 | pci_unmap_single(hw->pdev, | |
10fc51b9 FT |
979 | dma_unmap_addr(e, mapaddr), |
980 | dma_unmap_len(e, maplen), | |
19a33d4e SH |
981 | PCI_DMA_FROMDEVICE); |
982 | dev_kfree_skb(e->skb); | |
983 | e->skb = NULL; | |
984 | } | |
985 | } while ((e = e->next) != ring->start); | |
baef58b1 SH |
986 | } |
987 | ||
19a33d4e | 988 | |
baef58b1 | 989 | /* Allocate buffers for receive ring |
19a33d4e | 990 | * For receive: to_clean is next received frame. |
baef58b1 | 991 | */ |
c54f9765 | 992 | static int skge_rx_fill(struct net_device *dev) |
baef58b1 | 993 | { |
c54f9765 | 994 | struct skge_port *skge = netdev_priv(dev); |
baef58b1 SH |
995 | struct skge_ring *ring = &skge->rx_ring; |
996 | struct skge_element *e; | |
baef58b1 | 997 | |
19a33d4e SH |
998 | e = ring->start; |
999 | do { | |
383181ac | 1000 | struct sk_buff *skb; |
baef58b1 | 1001 | |
c54f9765 SH |
1002 | skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN, |
1003 | GFP_KERNEL); | |
19a33d4e SH |
1004 | if (!skb) |
1005 | return -ENOMEM; | |
1006 | ||
383181ac SH |
1007 | skb_reserve(skb, NET_IP_ALIGN); |
1008 | skge_rx_setup(skge, e, skb, skge->rx_buf_size); | |
67777f9b | 1009 | } while ((e = e->next) != ring->start); |
baef58b1 | 1010 | |
19a33d4e SH |
1011 | ring->to_clean = ring->start; |
1012 | return 0; | |
baef58b1 SH |
1013 | } |
1014 | ||
5d5c8e03 SH |
1015 | static const char *skge_pause(enum pause_status status) |
1016 | { | |
67777f9b | 1017 | switch (status) { |
5d5c8e03 SH |
1018 | case FLOW_STAT_NONE: |
1019 | return "none"; | |
1020 | case FLOW_STAT_REM_SEND: | |
1021 | return "rx only"; | |
1022 | case FLOW_STAT_LOC_SEND: | |
1023 | return "tx_only"; | |
1024 | case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */ | |
1025 | return "both"; | |
1026 | default: | |
1027 | return "indeterminated"; | |
1028 | } | |
1029 | } | |
1030 | ||
1031 | ||
baef58b1 SH |
1032 | static void skge_link_up(struct skge_port *skge) |
1033 | { | |
46a60f2d | 1034 | skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), |
54cfb5aa SH |
1035 | LED_BLK_OFF|LED_SYNC_OFF|LED_ON); |
1036 | ||
baef58b1 | 1037 | netif_carrier_on(skge->netdev); |
29b4e886 | 1038 | netif_wake_queue(skge->netdev); |
baef58b1 | 1039 | |
d707204c JP |
1040 | netif_info(skge, link, skge->netdev, |
1041 | "Link is up at %d Mbps, %s duplex, flow control %s\n", | |
1042 | skge->speed, | |
1043 | skge->duplex == DUPLEX_FULL ? "full" : "half", | |
1044 | skge_pause(skge->flow_status)); | |
baef58b1 SH |
1045 | } |
1046 | ||
1047 | static void skge_link_down(struct skge_port *skge) | |
1048 | { | |
54cfb5aa | 1049 | skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF); |
baef58b1 SH |
1050 | netif_carrier_off(skge->netdev); |
1051 | netif_stop_queue(skge->netdev); | |
1052 | ||
d707204c | 1053 | netif_info(skge, link, skge->netdev, "Link is down\n"); |
baef58b1 SH |
1054 | } |
1055 | ||
a1bc9b87 SH |
1056 | |
1057 | static void xm_link_down(struct skge_hw *hw, int port) | |
1058 | { | |
1059 | struct net_device *dev = hw->dev[port]; | |
1060 | struct skge_port *skge = netdev_priv(dev); | |
a1bc9b87 | 1061 | |
501fb72d | 1062 | xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE); |
a1bc9b87 | 1063 | |
a1bc9b87 SH |
1064 | if (netif_carrier_ok(dev)) |
1065 | skge_link_down(skge); | |
1066 | } | |
1067 | ||
2cd8e5d3 | 1068 | static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) |
baef58b1 SH |
1069 | { |
1070 | int i; | |
baef58b1 | 1071 | |
6b0c1480 | 1072 | xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); |
0781191c | 1073 | *val = xm_read16(hw, port, XM_PHY_DATA); |
baef58b1 | 1074 | |
64f6b64d SH |
1075 | if (hw->phy_type == SK_PHY_XMAC) |
1076 | goto ready; | |
1077 | ||
89bf5f23 | 1078 | for (i = 0; i < PHY_RETRIES; i++) { |
2cd8e5d3 | 1079 | if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY) |
89bf5f23 | 1080 | goto ready; |
0781191c | 1081 | udelay(1); |
baef58b1 SH |
1082 | } |
1083 | ||
2cd8e5d3 | 1084 | return -ETIMEDOUT; |
89bf5f23 | 1085 | ready: |
2cd8e5d3 | 1086 | *val = xm_read16(hw, port, XM_PHY_DATA); |
89bf5f23 | 1087 | |
2cd8e5d3 SH |
1088 | return 0; |
1089 | } | |
1090 | ||
1091 | static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg) | |
1092 | { | |
1093 | u16 v = 0; | |
1094 | if (__xm_phy_read(hw, port, reg, &v)) | |
f15063cd | 1095 | pr_warning("%s: phy read timed out\n", hw->dev[port]->name); |
baef58b1 SH |
1096 | return v; |
1097 | } | |
1098 | ||
2cd8e5d3 | 1099 | static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) |
baef58b1 SH |
1100 | { |
1101 | int i; | |
1102 | ||
6b0c1480 | 1103 | xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); |
baef58b1 | 1104 | for (i = 0; i < PHY_RETRIES; i++) { |
6b0c1480 | 1105 | if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) |
baef58b1 | 1106 | goto ready; |
89bf5f23 | 1107 | udelay(1); |
baef58b1 | 1108 | } |
2cd8e5d3 | 1109 | return -EIO; |
baef58b1 SH |
1110 | |
1111 | ready: | |
6b0c1480 | 1112 | xm_write16(hw, port, XM_PHY_DATA, val); |
0781191c SH |
1113 | for (i = 0; i < PHY_RETRIES; i++) { |
1114 | if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) | |
1115 | return 0; | |
1116 | udelay(1); | |
1117 | } | |
1118 | return -ETIMEDOUT; | |
baef58b1 SH |
1119 | } |
1120 | ||
1121 | static void genesis_init(struct skge_hw *hw) | |
1122 | { | |
1123 | /* set blink source counter */ | |
1124 | skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100); | |
1125 | skge_write8(hw, B2_BSC_CTRL, BSC_START); | |
1126 | ||
1127 | /* configure mac arbiter */ | |
1128 | skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); | |
1129 | ||
1130 | /* configure mac arbiter timeout values */ | |
1131 | skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53); | |
1132 | skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53); | |
1133 | skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53); | |
1134 | skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53); | |
1135 | ||
1136 | skge_write8(hw, B3_MA_RCINI_RX1, 0); | |
1137 | skge_write8(hw, B3_MA_RCINI_RX2, 0); | |
1138 | skge_write8(hw, B3_MA_RCINI_TX1, 0); | |
1139 | skge_write8(hw, B3_MA_RCINI_TX2, 0); | |
1140 | ||
1141 | /* configure packet arbiter timeout */ | |
1142 | skge_write16(hw, B3_PA_CTRL, PA_RST_CLR); | |
1143 | skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX); | |
1144 | skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX); | |
1145 | skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX); | |
1146 | skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX); | |
1147 | } | |
1148 | ||
1149 | static void genesis_reset(struct skge_hw *hw, int port) | |
1150 | { | |
b6bc7650 | 1151 | static const u8 zero[8] = { 0 }; |
21d7f677 | 1152 | u32 reg; |
baef58b1 | 1153 | |
46a60f2d SH |
1154 | skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); |
1155 | ||
baef58b1 | 1156 | /* reset the statistics module */ |
6b0c1480 | 1157 | xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT); |
501fb72d | 1158 | xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE); |
6b0c1480 SH |
1159 | xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */ |
1160 | xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */ | |
1161 | xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */ | |
baef58b1 | 1162 | |
89bf5f23 | 1163 | /* disable Broadcom PHY IRQ */ |
64f6b64d SH |
1164 | if (hw->phy_type == SK_PHY_BCOM) |
1165 | xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff); | |
baef58b1 | 1166 | |
45bada65 | 1167 | xm_outhash(hw, port, XM_HSM, zero); |
21d7f677 SH |
1168 | |
1169 | /* Flush TX and RX fifo */ | |
1170 | reg = xm_read32(hw, port, XM_MODE); | |
1171 | xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF); | |
1172 | xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF); | |
baef58b1 SH |
1173 | } |
1174 | ||
1175 | ||
45bada65 SH |
1176 | /* Convert mode to MII values */ |
1177 | static const u16 phy_pause_map[] = { | |
1178 | [FLOW_MODE_NONE] = 0, | |
1179 | [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM, | |
1180 | [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP, | |
5d5c8e03 | 1181 | [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM, |
45bada65 SH |
1182 | }; |
1183 | ||
4b67be99 SH |
1184 | /* special defines for FIBER (88E1011S only) */ |
1185 | static const u16 fiber_pause_map[] = { | |
1186 | [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE, | |
1187 | [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD, | |
1188 | [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD, | |
5d5c8e03 | 1189 | [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD, |
4b67be99 SH |
1190 | }; |
1191 | ||
45bada65 SH |
1192 | |
1193 | /* Check status of Broadcom phy link */ | |
1194 | static void bcom_check_link(struct skge_hw *hw, int port) | |
baef58b1 | 1195 | { |
45bada65 SH |
1196 | struct net_device *dev = hw->dev[port]; |
1197 | struct skge_port *skge = netdev_priv(dev); | |
1198 | u16 status; | |
1199 | ||
1200 | /* read twice because of latch */ | |
501fb72d | 1201 | xm_phy_read(hw, port, PHY_BCOM_STAT); |
45bada65 SH |
1202 | status = xm_phy_read(hw, port, PHY_BCOM_STAT); |
1203 | ||
45bada65 | 1204 | if ((status & PHY_ST_LSYNC) == 0) { |
a1bc9b87 | 1205 | xm_link_down(hw, port); |
64f6b64d SH |
1206 | return; |
1207 | } | |
45bada65 | 1208 | |
64f6b64d SH |
1209 | if (skge->autoneg == AUTONEG_ENABLE) { |
1210 | u16 lpa, aux; | |
45bada65 | 1211 | |
64f6b64d SH |
1212 | if (!(status & PHY_ST_AN_OVER)) |
1213 | return; | |
45bada65 | 1214 | |
64f6b64d SH |
1215 | lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP); |
1216 | if (lpa & PHY_B_AN_RF) { | |
f15063cd | 1217 | netdev_notice(dev, "remote fault\n"); |
64f6b64d SH |
1218 | return; |
1219 | } | |
45bada65 | 1220 | |
64f6b64d SH |
1221 | aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT); |
1222 | ||
1223 | /* Check Duplex mismatch */ | |
1224 | switch (aux & PHY_B_AS_AN_RES_MSK) { | |
1225 | case PHY_B_RES_1000FD: | |
1226 | skge->duplex = DUPLEX_FULL; | |
1227 | break; | |
1228 | case PHY_B_RES_1000HD: | |
1229 | skge->duplex = DUPLEX_HALF; | |
1230 | break; | |
1231 | default: | |
f15063cd | 1232 | netdev_notice(dev, "duplex mismatch\n"); |
64f6b64d | 1233 | return; |
45bada65 SH |
1234 | } |
1235 | ||
64f6b64d SH |
1236 | /* We are using IEEE 802.3z/D5.0 Table 37-4 */ |
1237 | switch (aux & PHY_B_AS_PAUSE_MSK) { | |
1238 | case PHY_B_AS_PAUSE_MSK: | |
5d5c8e03 | 1239 | skge->flow_status = FLOW_STAT_SYMMETRIC; |
64f6b64d SH |
1240 | break; |
1241 | case PHY_B_AS_PRR: | |
5d5c8e03 | 1242 | skge->flow_status = FLOW_STAT_REM_SEND; |
64f6b64d SH |
1243 | break; |
1244 | case PHY_B_AS_PRT: | |
5d5c8e03 | 1245 | skge->flow_status = FLOW_STAT_LOC_SEND; |
64f6b64d SH |
1246 | break; |
1247 | default: | |
5d5c8e03 | 1248 | skge->flow_status = FLOW_STAT_NONE; |
64f6b64d SH |
1249 | } |
1250 | skge->speed = SPEED_1000; | |
45bada65 | 1251 | } |
64f6b64d SH |
1252 | |
1253 | if (!netif_carrier_ok(dev)) | |
1254 | genesis_link_up(skge); | |
45bada65 SH |
1255 | } |
1256 | ||
1257 | /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional | |
1258 | * Phy on for 100 or 10Mbit operation | |
1259 | */ | |
64f6b64d | 1260 | static void bcom_phy_init(struct skge_port *skge) |
45bada65 SH |
1261 | { |
1262 | struct skge_hw *hw = skge->hw; | |
1263 | int port = skge->port; | |
baef58b1 | 1264 | int i; |
45bada65 | 1265 | u16 id1, r, ext, ctl; |
baef58b1 SH |
1266 | |
1267 | /* magic workaround patterns for Broadcom */ | |
1268 | static const struct { | |
1269 | u16 reg; | |
1270 | u16 val; | |
1271 | } A1hack[] = { | |
1272 | { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, | |
1273 | { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 }, | |
1274 | { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 }, | |
1275 | { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, | |
1276 | }, C0hack[] = { | |
1277 | { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 }, | |
1278 | { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 }, | |
1279 | }; | |
1280 | ||
45bada65 SH |
1281 | /* read Id from external PHY (all have the same address) */ |
1282 | id1 = xm_phy_read(hw, port, PHY_XMAC_ID1); | |
1283 | ||
1284 | /* Optimize MDIO transfer by suppressing preamble. */ | |
1285 | r = xm_read16(hw, port, XM_MMU_CMD); | |
1286 | r |= XM_MMU_NO_PRE; | |
67777f9b | 1287 | xm_write16(hw, port, XM_MMU_CMD, r); |
45bada65 | 1288 | |
2c668514 | 1289 | switch (id1) { |
45bada65 SH |
1290 | case PHY_BCOM_ID1_C0: |
1291 | /* | |
1292 | * Workaround BCOM Errata for the C0 type. | |
1293 | * Write magic patterns to reserved registers. | |
1294 | */ | |
1295 | for (i = 0; i < ARRAY_SIZE(C0hack); i++) | |
1296 | xm_phy_write(hw, port, | |
1297 | C0hack[i].reg, C0hack[i].val); | |
1298 | ||
1299 | break; | |
1300 | case PHY_BCOM_ID1_A1: | |
1301 | /* | |
1302 | * Workaround BCOM Errata for the A1 type. | |
1303 | * Write magic patterns to reserved registers. | |
1304 | */ | |
1305 | for (i = 0; i < ARRAY_SIZE(A1hack); i++) | |
1306 | xm_phy_write(hw, port, | |
1307 | A1hack[i].reg, A1hack[i].val); | |
1308 | break; | |
1309 | } | |
1310 | ||
1311 | /* | |
1312 | * Workaround BCOM Errata (#10523) for all BCom PHYs. | |
1313 | * Disable Power Management after reset. | |
1314 | */ | |
1315 | r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL); | |
1316 | r |= PHY_B_AC_DIS_PM; | |
1317 | xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r); | |
1318 | ||
1319 | /* Dummy read */ | |
1320 | xm_read16(hw, port, XM_ISRC); | |
1321 | ||
1322 | ext = PHY_B_PEC_EN_LTR; /* enable tx led */ | |
1323 | ctl = PHY_CT_SP1000; /* always 1000mbit */ | |
1324 | ||
1325 | if (skge->autoneg == AUTONEG_ENABLE) { | |
1326 | /* | |
1327 | * Workaround BCOM Errata #1 for the C5 type. | |
1328 | * 1000Base-T Link Acquisition Failure in Slave Mode | |
1329 | * Set Repeater/DTE bit 10 of the 1000Base-T Control Register | |
1330 | */ | |
1331 | u16 adv = PHY_B_1000C_RD; | |
1332 | if (skge->advertising & ADVERTISED_1000baseT_Half) | |
1333 | adv |= PHY_B_1000C_AHD; | |
1334 | if (skge->advertising & ADVERTISED_1000baseT_Full) | |
1335 | adv |= PHY_B_1000C_AFD; | |
1336 | xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv); | |
1337 | ||
1338 | ctl |= PHY_CT_ANE | PHY_CT_RE_CFG; | |
1339 | } else { | |
1340 | if (skge->duplex == DUPLEX_FULL) | |
1341 | ctl |= PHY_CT_DUP_MD; | |
1342 | /* Force to slave */ | |
1343 | xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE); | |
1344 | } | |
1345 | ||
1346 | /* Set autonegotiation pause parameters */ | |
1347 | xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, | |
1348 | phy_pause_map[skge->flow_control] | PHY_AN_CSMA); | |
1349 | ||
1350 | /* Handle Jumbo frames */ | |
64f6b64d | 1351 | if (hw->dev[port]->mtu > ETH_DATA_LEN) { |
45bada65 SH |
1352 | xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, |
1353 | PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK); | |
1354 | ||
1355 | ext |= PHY_B_PEC_HIGH_LA; | |
1356 | ||
1357 | } | |
1358 | ||
1359 | xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext); | |
1360 | xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl); | |
1361 | ||
8f3f8193 | 1362 | /* Use link status change interrupt */ |
45bada65 | 1363 | xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); |
64f6b64d | 1364 | } |
45bada65 | 1365 | |
64f6b64d SH |
1366 | static void xm_phy_init(struct skge_port *skge) |
1367 | { | |
1368 | struct skge_hw *hw = skge->hw; | |
1369 | int port = skge->port; | |
1370 | u16 ctrl = 0; | |
1371 | ||
1372 | if (skge->autoneg == AUTONEG_ENABLE) { | |
1373 | if (skge->advertising & ADVERTISED_1000baseT_Half) | |
1374 | ctrl |= PHY_X_AN_HD; | |
1375 | if (skge->advertising & ADVERTISED_1000baseT_Full) | |
1376 | ctrl |= PHY_X_AN_FD; | |
1377 | ||
4b67be99 | 1378 | ctrl |= fiber_pause_map[skge->flow_control]; |
64f6b64d SH |
1379 | |
1380 | xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl); | |
1381 | ||
1382 | /* Restart Auto-negotiation */ | |
1383 | ctrl = PHY_CT_ANE | PHY_CT_RE_CFG; | |
1384 | } else { | |
1385 | /* Set DuplexMode in Config register */ | |
1386 | if (skge->duplex == DUPLEX_FULL) | |
1387 | ctrl |= PHY_CT_DUP_MD; | |
1388 | /* | |
1389 | * Do NOT enable Auto-negotiation here. This would hold | |
1390 | * the link down because no IDLEs are transmitted | |
1391 | */ | |
1392 | } | |
1393 | ||
1394 | xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl); | |
1395 | ||
1396 | /* Poll PHY for status changes */ | |
9cbe330f | 1397 | mod_timer(&skge->link_timer, jiffies + LINK_HZ); |
64f6b64d SH |
1398 | } |
1399 | ||
501fb72d | 1400 | static int xm_check_link(struct net_device *dev) |
64f6b64d SH |
1401 | { |
1402 | struct skge_port *skge = netdev_priv(dev); | |
1403 | struct skge_hw *hw = skge->hw; | |
1404 | int port = skge->port; | |
1405 | u16 status; | |
1406 | ||
1407 | /* read twice because of latch */ | |
501fb72d | 1408 | xm_phy_read(hw, port, PHY_XMAC_STAT); |
64f6b64d SH |
1409 | status = xm_phy_read(hw, port, PHY_XMAC_STAT); |
1410 | ||
1411 | if ((status & PHY_ST_LSYNC) == 0) { | |
a1bc9b87 | 1412 | xm_link_down(hw, port); |
501fb72d | 1413 | return 0; |
64f6b64d SH |
1414 | } |
1415 | ||
1416 | if (skge->autoneg == AUTONEG_ENABLE) { | |
1417 | u16 lpa, res; | |
1418 | ||
1419 | if (!(status & PHY_ST_AN_OVER)) | |
501fb72d | 1420 | return 0; |
64f6b64d SH |
1421 | |
1422 | lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP); | |
1423 | if (lpa & PHY_B_AN_RF) { | |
f15063cd | 1424 | netdev_notice(dev, "remote fault\n"); |
501fb72d | 1425 | return 0; |
64f6b64d SH |
1426 | } |
1427 | ||
1428 | res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI); | |
1429 | ||
1430 | /* Check Duplex mismatch */ | |
1431 | switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) { | |
1432 | case PHY_X_RS_FD: | |
1433 | skge->duplex = DUPLEX_FULL; | |
1434 | break; | |
1435 | case PHY_X_RS_HD: | |
1436 | skge->duplex = DUPLEX_HALF; | |
1437 | break; | |
1438 | default: | |
f15063cd | 1439 | netdev_notice(dev, "duplex mismatch\n"); |
501fb72d | 1440 | return 0; |
64f6b64d SH |
1441 | } |
1442 | ||
1443 | /* We are using IEEE 802.3z/D5.0 Table 37-4 */ | |
5d5c8e03 SH |
1444 | if ((skge->flow_control == FLOW_MODE_SYMMETRIC || |
1445 | skge->flow_control == FLOW_MODE_SYM_OR_REM) && | |
1446 | (lpa & PHY_X_P_SYM_MD)) | |
1447 | skge->flow_status = FLOW_STAT_SYMMETRIC; | |
1448 | else if (skge->flow_control == FLOW_MODE_SYM_OR_REM && | |
1449 | (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD) | |
1450 | /* Enable PAUSE receive, disable PAUSE transmit */ | |
1451 | skge->flow_status = FLOW_STAT_REM_SEND; | |
1452 | else if (skge->flow_control == FLOW_MODE_LOC_SEND && | |
1453 | (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD) | |
1454 | /* Disable PAUSE receive, enable PAUSE transmit */ | |
1455 | skge->flow_status = FLOW_STAT_LOC_SEND; | |
64f6b64d | 1456 | else |
5d5c8e03 | 1457 | skge->flow_status = FLOW_STAT_NONE; |
64f6b64d SH |
1458 | |
1459 | skge->speed = SPEED_1000; | |
1460 | } | |
1461 | ||
1462 | if (!netif_carrier_ok(dev)) | |
1463 | genesis_link_up(skge); | |
501fb72d | 1464 | return 1; |
64f6b64d SH |
1465 | } |
1466 | ||
1467 | /* Poll to check for link coming up. | |
501fb72d | 1468 | * |
64f6b64d | 1469 | * Since internal PHY is wired to a level triggered pin, can't |
501fb72d SH |
1470 | * get an interrupt when carrier is detected, need to poll for |
1471 | * link coming up. | |
64f6b64d | 1472 | */ |
9cbe330f | 1473 | static void xm_link_timer(unsigned long arg) |
64f6b64d | 1474 | { |
9cbe330f | 1475 | struct skge_port *skge = (struct skge_port *) arg; |
c4028958 | 1476 | struct net_device *dev = skge->netdev; |
67777f9b | 1477 | struct skge_hw *hw = skge->hw; |
64f6b64d | 1478 | int port = skge->port; |
501fb72d SH |
1479 | int i; |
1480 | unsigned long flags; | |
64f6b64d SH |
1481 | |
1482 | if (!netif_running(dev)) | |
1483 | return; | |
1484 | ||
501fb72d SH |
1485 | spin_lock_irqsave(&hw->phy_lock, flags); |
1486 | ||
1487 | /* | |
1488 | * Verify that the link by checking GPIO register three times. | |
1489 | * This pin has the signal from the link_sync pin connected to it. | |
1490 | */ | |
1491 | for (i = 0; i < 3; i++) { | |
1492 | if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS) | |
1493 | goto link_down; | |
1494 | } | |
1495 | ||
67777f9b | 1496 | /* Re-enable interrupt to detect link down */ |
501fb72d SH |
1497 | if (xm_check_link(dev)) { |
1498 | u16 msk = xm_read16(hw, port, XM_IMSK); | |
1499 | msk &= ~XM_IS_INP_ASS; | |
1500 | xm_write16(hw, port, XM_IMSK, msk); | |
64f6b64d | 1501 | xm_read16(hw, port, XM_ISRC); |
64f6b64d | 1502 | } else { |
501fb72d SH |
1503 | link_down: |
1504 | mod_timer(&skge->link_timer, | |
1505 | round_jiffies(jiffies + LINK_HZ)); | |
64f6b64d | 1506 | } |
501fb72d | 1507 | spin_unlock_irqrestore(&hw->phy_lock, flags); |
45bada65 SH |
1508 | } |
1509 | ||
1510 | static void genesis_mac_init(struct skge_hw *hw, int port) | |
1511 | { | |
1512 | struct net_device *dev = hw->dev[port]; | |
1513 | struct skge_port *skge = netdev_priv(dev); | |
1514 | int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN; | |
1515 | int i; | |
1516 | u32 r; | |
b6bc7650 | 1517 | static const u8 zero[6] = { 0 }; |
45bada65 | 1518 | |
0781191c SH |
1519 | for (i = 0; i < 10; i++) { |
1520 | skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), | |
1521 | MFF_SET_MAC_RST); | |
1522 | if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST) | |
1523 | goto reset_ok; | |
1524 | udelay(1); | |
1525 | } | |
baef58b1 | 1526 | |
f15063cd | 1527 | netdev_warn(dev, "genesis reset failed\n"); |
0781191c SH |
1528 | |
1529 | reset_ok: | |
baef58b1 | 1530 | /* Unreset the XMAC. */ |
6b0c1480 | 1531 | skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); |
baef58b1 SH |
1532 | |
1533 | /* | |
1534 | * Perform additional initialization for external PHYs, | |
1535 | * namely for the 1000baseTX cards that use the XMAC's | |
1536 | * GMII mode. | |
1537 | */ | |
64f6b64d SH |
1538 | if (hw->phy_type != SK_PHY_XMAC) { |
1539 | /* Take external Phy out of reset */ | |
1540 | r = skge_read32(hw, B2_GP_IO); | |
1541 | if (port == 0) | |
1542 | r |= GP_DIR_0|GP_IO_0; | |
1543 | else | |
1544 | r |= GP_DIR_2|GP_IO_2; | |
89bf5f23 | 1545 | |
64f6b64d | 1546 | skge_write32(hw, B2_GP_IO, r); |
0781191c | 1547 | |
64f6b64d SH |
1548 | /* Enable GMII interface */ |
1549 | xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD); | |
1550 | } | |
89bf5f23 | 1551 | |
89bf5f23 | 1552 | |
67777f9b | 1553 | switch (hw->phy_type) { |
64f6b64d SH |
1554 | case SK_PHY_XMAC: |
1555 | xm_phy_init(skge); | |
1556 | break; | |
1557 | case SK_PHY_BCOM: | |
1558 | bcom_phy_init(skge); | |
1559 | bcom_check_link(hw, port); | |
1560 | } | |
89bf5f23 | 1561 | |
45bada65 SH |
1562 | /* Set Station Address */ |
1563 | xm_outaddr(hw, port, XM_SA, dev->dev_addr); | |
89bf5f23 | 1564 | |
45bada65 SH |
1565 | /* We don't use match addresses so clear */ |
1566 | for (i = 1; i < 16; i++) | |
1567 | xm_outaddr(hw, port, XM_EXM(i), zero); | |
1568 | ||
0781191c SH |
1569 | /* Clear MIB counters */ |
1570 | xm_write16(hw, port, XM_STAT_CMD, | |
1571 | XM_SC_CLR_RXC | XM_SC_CLR_TXC); | |
1572 | /* Clear two times according to Errata #3 */ | |
1573 | xm_write16(hw, port, XM_STAT_CMD, | |
1574 | XM_SC_CLR_RXC | XM_SC_CLR_TXC); | |
1575 | ||
45bada65 SH |
1576 | /* configure Rx High Water Mark (XM_RX_HI_WM) */ |
1577 | xm_write16(hw, port, XM_RX_HI_WM, 1450); | |
1578 | ||
1579 | /* We don't need the FCS appended to the packet. */ | |
1580 | r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS; | |
1581 | if (jumbo) | |
1582 | r |= XM_RX_BIG_PK_OK; | |
89bf5f23 | 1583 | |
45bada65 | 1584 | if (skge->duplex == DUPLEX_HALF) { |
89bf5f23 | 1585 | /* |
45bada65 SH |
1586 | * If in manual half duplex mode the other side might be in |
1587 | * full duplex mode, so ignore if a carrier extension is not seen | |
1588 | * on frames received | |
89bf5f23 | 1589 | */ |
45bada65 | 1590 | r |= XM_RX_DIS_CEXT; |
baef58b1 | 1591 | } |
45bada65 | 1592 | xm_write16(hw, port, XM_RX_CMD, r); |
baef58b1 | 1593 | |
baef58b1 | 1594 | /* We want short frames padded to 60 bytes. */ |
45bada65 SH |
1595 | xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD); |
1596 | ||
485982a9 SH |
1597 | /* Increase threshold for jumbo frames on dual port */ |
1598 | if (hw->ports > 1 && jumbo) | |
1599 | xm_write16(hw, port, XM_TX_THR, 1020); | |
1600 | else | |
1601 | xm_write16(hw, port, XM_TX_THR, 512); | |
baef58b1 SH |
1602 | |
1603 | /* | |
1604 | * Enable the reception of all error frames. This is is | |
1605 | * a necessary evil due to the design of the XMAC. The | |
1606 | * XMAC's receive FIFO is only 8K in size, however jumbo | |
1607 | * frames can be up to 9000 bytes in length. When bad | |
1608 | * frame filtering is enabled, the XMAC's RX FIFO operates | |
1609 | * in 'store and forward' mode. For this to work, the | |
1610 | * entire frame has to fit into the FIFO, but that means | |
1611 | * that jumbo frames larger than 8192 bytes will be | |
1612 | * truncated. Disabling all bad frame filtering causes | |
1613 | * the RX FIFO to operate in streaming mode, in which | |
8f3f8193 | 1614 | * case the XMAC will start transferring frames out of the |
baef58b1 SH |
1615 | * RX FIFO as soon as the FIFO threshold is reached. |
1616 | */ | |
45bada65 | 1617 | xm_write32(hw, port, XM_MODE, XM_DEF_MODE); |
baef58b1 | 1618 | |
baef58b1 SH |
1619 | |
1620 | /* | |
45bada65 SH |
1621 | * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK) |
1622 | * - Enable all bits excepting 'Octets Rx OK Low CntOv' | |
1623 | * and 'Octets Rx OK Hi Cnt Ov'. | |
baef58b1 | 1624 | */ |
45bada65 SH |
1625 | xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK); |
1626 | ||
1627 | /* | |
1628 | * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK) | |
1629 | * - Enable all bits excepting 'Octets Tx OK Low CntOv' | |
1630 | * and 'Octets Tx OK Hi Cnt Ov'. | |
1631 | */ | |
1632 | xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK); | |
baef58b1 SH |
1633 | |
1634 | /* Configure MAC arbiter */ | |
1635 | skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); | |
1636 | ||
1637 | /* configure timeout values */ | |
1638 | skge_write8(hw, B3_MA_TOINI_RX1, 72); | |
1639 | skge_write8(hw, B3_MA_TOINI_RX2, 72); | |
1640 | skge_write8(hw, B3_MA_TOINI_TX1, 72); | |
1641 | skge_write8(hw, B3_MA_TOINI_TX2, 72); | |
1642 | ||
1643 | skge_write8(hw, B3_MA_RCINI_RX1, 0); | |
1644 | skge_write8(hw, B3_MA_RCINI_RX2, 0); | |
1645 | skge_write8(hw, B3_MA_RCINI_TX1, 0); | |
1646 | skge_write8(hw, B3_MA_RCINI_TX2, 0); | |
1647 | ||
1648 | /* Configure Rx MAC FIFO */ | |
6b0c1480 SH |
1649 | skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR); |
1650 | skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT); | |
1651 | skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD); | |
baef58b1 SH |
1652 | |
1653 | /* Configure Tx MAC FIFO */ | |
6b0c1480 SH |
1654 | skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR); |
1655 | skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF); | |
1656 | skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD); | |
baef58b1 | 1657 | |
45bada65 | 1658 | if (jumbo) { |
baef58b1 | 1659 | /* Enable frame flushing if jumbo frames used */ |
67777f9b | 1660 | skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH); |
baef58b1 SH |
1661 | } else { |
1662 | /* enable timeout timers if normal frames */ | |
1663 | skge_write16(hw, B3_PA_CTRL, | |
45bada65 | 1664 | (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2); |
baef58b1 | 1665 | } |
baef58b1 SH |
1666 | } |
1667 | ||
1668 | static void genesis_stop(struct skge_port *skge) | |
1669 | { | |
1670 | struct skge_hw *hw = skge->hw; | |
1671 | int port = skge->port; | |
799b21d2 | 1672 | unsigned retries = 1000; |
21d7f677 SH |
1673 | u16 cmd; |
1674 | ||
67777f9b | 1675 | /* Disable Tx and Rx */ |
21d7f677 SH |
1676 | cmd = xm_read16(hw, port, XM_MMU_CMD); |
1677 | cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX); | |
1678 | xm_write16(hw, port, XM_MMU_CMD, cmd); | |
baef58b1 | 1679 | |
46a60f2d SH |
1680 | genesis_reset(hw, port); |
1681 | ||
baef58b1 SH |
1682 | /* Clear Tx packet arbiter timeout IRQ */ |
1683 | skge_write16(hw, B3_PA_CTRL, | |
1684 | port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2); | |
1685 | ||
baef58b1 | 1686 | /* Reset the MAC */ |
799b21d2 SH |
1687 | skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); |
1688 | do { | |
1689 | skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST); | |
1690 | if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)) | |
1691 | break; | |
1692 | } while (--retries > 0); | |
baef58b1 SH |
1693 | |
1694 | /* For external PHYs there must be special handling */ | |
64f6b64d | 1695 | if (hw->phy_type != SK_PHY_XMAC) { |
799b21d2 | 1696 | u32 reg = skge_read32(hw, B2_GP_IO); |
64f6b64d SH |
1697 | if (port == 0) { |
1698 | reg |= GP_DIR_0; | |
1699 | reg &= ~GP_IO_0; | |
1700 | } else { | |
1701 | reg |= GP_DIR_2; | |
1702 | reg &= ~GP_IO_2; | |
1703 | } | |
1704 | skge_write32(hw, B2_GP_IO, reg); | |
1705 | skge_read32(hw, B2_GP_IO); | |
baef58b1 SH |
1706 | } |
1707 | ||
6b0c1480 SH |
1708 | xm_write16(hw, port, XM_MMU_CMD, |
1709 | xm_read16(hw, port, XM_MMU_CMD) | |
baef58b1 SH |
1710 | & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX)); |
1711 | ||
6b0c1480 | 1712 | xm_read16(hw, port, XM_MMU_CMD); |
baef58b1 SH |
1713 | } |
1714 | ||
1715 | ||
1716 | static void genesis_get_stats(struct skge_port *skge, u64 *data) | |
1717 | { | |
1718 | struct skge_hw *hw = skge->hw; | |
1719 | int port = skge->port; | |
1720 | int i; | |
1721 | unsigned long timeout = jiffies + HZ; | |
1722 | ||
6b0c1480 | 1723 | xm_write16(hw, port, |
baef58b1 SH |
1724 | XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC); |
1725 | ||
1726 | /* wait for update to complete */ | |
6b0c1480 | 1727 | while (xm_read16(hw, port, XM_STAT_CMD) |
baef58b1 SH |
1728 | & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) { |
1729 | if (time_after(jiffies, timeout)) | |
1730 | break; | |
1731 | udelay(10); | |
1732 | } | |
1733 | ||
1734 | /* special case for 64 bit octet counter */ | |
6b0c1480 SH |
1735 | data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32 |
1736 | | xm_read32(hw, port, XM_TXO_OK_LO); | |
1737 | data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32 | |
1738 | | xm_read32(hw, port, XM_RXO_OK_LO); | |
baef58b1 SH |
1739 | |
1740 | for (i = 2; i < ARRAY_SIZE(skge_stats); i++) | |
6b0c1480 | 1741 | data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset); |
baef58b1 SH |
1742 | } |
1743 | ||
1744 | static void genesis_mac_intr(struct skge_hw *hw, int port) | |
1745 | { | |
da00772f SH |
1746 | struct net_device *dev = hw->dev[port]; |
1747 | struct skge_port *skge = netdev_priv(dev); | |
6b0c1480 | 1748 | u16 status = xm_read16(hw, port, XM_ISRC); |
baef58b1 | 1749 | |
d707204c JP |
1750 | netif_printk(skge, intr, KERN_DEBUG, skge->netdev, |
1751 | "mac interrupt status 0x%x\n", status); | |
baef58b1 | 1752 | |
501fb72d | 1753 | if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) { |
67777f9b | 1754 | xm_link_down(hw, port); |
501fb72d SH |
1755 | mod_timer(&skge->link_timer, jiffies + 1); |
1756 | } | |
a1bc9b87 | 1757 | |
baef58b1 | 1758 | if (status & XM_IS_TXF_UR) { |
6b0c1480 | 1759 | xm_write32(hw, port, XM_MODE, XM_MD_FTF); |
da00772f | 1760 | ++dev->stats.tx_fifo_errors; |
baef58b1 | 1761 | } |
baef58b1 SH |
1762 | } |
1763 | ||
baef58b1 SH |
1764 | static void genesis_link_up(struct skge_port *skge) |
1765 | { | |
1766 | struct skge_hw *hw = skge->hw; | |
1767 | int port = skge->port; | |
a1bc9b87 | 1768 | u16 cmd, msk; |
64f6b64d | 1769 | u32 mode; |
baef58b1 | 1770 | |
6b0c1480 | 1771 | cmd = xm_read16(hw, port, XM_MMU_CMD); |
baef58b1 SH |
1772 | |
1773 | /* | |
1774 | * enabling pause frame reception is required for 1000BT | |
1775 | * because the XMAC is not reset if the link is going down | |
1776 | */ | |
5d5c8e03 SH |
1777 | if (skge->flow_status == FLOW_STAT_NONE || |
1778 | skge->flow_status == FLOW_STAT_LOC_SEND) | |
7e676d91 | 1779 | /* Disable Pause Frame Reception */ |
baef58b1 SH |
1780 | cmd |= XM_MMU_IGN_PF; |
1781 | else | |
1782 | /* Enable Pause Frame Reception */ | |
1783 | cmd &= ~XM_MMU_IGN_PF; | |
1784 | ||
6b0c1480 | 1785 | xm_write16(hw, port, XM_MMU_CMD, cmd); |
baef58b1 | 1786 | |
6b0c1480 | 1787 | mode = xm_read32(hw, port, XM_MODE); |
67777f9b | 1788 | if (skge->flow_status == FLOW_STAT_SYMMETRIC || |
5d5c8e03 | 1789 | skge->flow_status == FLOW_STAT_LOC_SEND) { |
baef58b1 SH |
1790 | /* |
1791 | * Configure Pause Frame Generation | |
1792 | * Use internal and external Pause Frame Generation. | |
1793 | * Sending pause frames is edge triggered. | |
1794 | * Send a Pause frame with the maximum pause time if | |
1795 | * internal oder external FIFO full condition occurs. | |
1796 | * Send a zero pause time frame to re-start transmission. | |
1797 | */ | |
1798 | /* XM_PAUSE_DA = '010000C28001' (default) */ | |
1799 | /* XM_MAC_PTIME = 0xffff (maximum) */ | |
1800 | /* remember this value is defined in big endian (!) */ | |
6b0c1480 | 1801 | xm_write16(hw, port, XM_MAC_PTIME, 0xffff); |
baef58b1 SH |
1802 | |
1803 | mode |= XM_PAUSE_MODE; | |
6b0c1480 | 1804 | skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE); |
baef58b1 SH |
1805 | } else { |
1806 | /* | |
1807 | * disable pause frame generation is required for 1000BT | |
1808 | * because the XMAC is not reset if the link is going down | |
1809 | */ | |
1810 | /* Disable Pause Mode in Mode Register */ | |
1811 | mode &= ~XM_PAUSE_MODE; | |
1812 | ||
6b0c1480 | 1813 | skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE); |
baef58b1 SH |
1814 | } |
1815 | ||
6b0c1480 | 1816 | xm_write32(hw, port, XM_MODE, mode); |
a1bc9b87 | 1817 | |
d08b9bdf | 1818 | /* Turn on detection of Tx underrun */ |
501fb72d | 1819 | msk = xm_read16(hw, port, XM_IMSK); |
d08b9bdf | 1820 | msk &= ~XM_IS_TXF_UR; |
a1bc9b87 | 1821 | xm_write16(hw, port, XM_IMSK, msk); |
501fb72d | 1822 | |
6b0c1480 | 1823 | xm_read16(hw, port, XM_ISRC); |
baef58b1 SH |
1824 | |
1825 | /* get MMU Command Reg. */ | |
6b0c1480 | 1826 | cmd = xm_read16(hw, port, XM_MMU_CMD); |
64f6b64d | 1827 | if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL) |
baef58b1 SH |
1828 | cmd |= XM_MMU_GMII_FD; |
1829 | ||
89bf5f23 SH |
1830 | /* |
1831 | * Workaround BCOM Errata (#10523) for all BCom Phys | |
1832 | * Enable Power Management after link up | |
1833 | */ | |
64f6b64d SH |
1834 | if (hw->phy_type == SK_PHY_BCOM) { |
1835 | xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, | |
1836 | xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL) | |
1837 | & ~PHY_B_AC_DIS_PM); | |
1838 | xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); | |
1839 | } | |
baef58b1 SH |
1840 | |
1841 | /* enable Rx/Tx */ | |
6b0c1480 | 1842 | xm_write16(hw, port, XM_MMU_CMD, |
baef58b1 SH |
1843 | cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX); |
1844 | skge_link_up(skge); | |
1845 | } | |
1846 | ||
1847 | ||
45bada65 | 1848 | static inline void bcom_phy_intr(struct skge_port *skge) |
baef58b1 SH |
1849 | { |
1850 | struct skge_hw *hw = skge->hw; | |
1851 | int port = skge->port; | |
45bada65 SH |
1852 | u16 isrc; |
1853 | ||
1854 | isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT); | |
d707204c JP |
1855 | netif_printk(skge, intr, KERN_DEBUG, skge->netdev, |
1856 | "phy interrupt status 0x%x\n", isrc); | |
baef58b1 | 1857 | |
45bada65 | 1858 | if (isrc & PHY_B_IS_PSE) |
f15063cd | 1859 | pr_err("%s: uncorrectable pair swap error\n", |
45bada65 | 1860 | hw->dev[port]->name); |
baef58b1 SH |
1861 | |
1862 | /* Workaround BCom Errata: | |
1863 | * enable and disable loopback mode if "NO HCD" occurs. | |
1864 | */ | |
45bada65 | 1865 | if (isrc & PHY_B_IS_NO_HDCL) { |
6b0c1480 SH |
1866 | u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL); |
1867 | xm_phy_write(hw, port, PHY_BCOM_CTRL, | |
baef58b1 | 1868 | ctrl | PHY_CT_LOOP); |
6b0c1480 | 1869 | xm_phy_write(hw, port, PHY_BCOM_CTRL, |
baef58b1 SH |
1870 | ctrl & ~PHY_CT_LOOP); |
1871 | } | |
1872 | ||
45bada65 SH |
1873 | if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) |
1874 | bcom_check_link(hw, port); | |
baef58b1 | 1875 | |
baef58b1 SH |
1876 | } |
1877 | ||
2cd8e5d3 SH |
1878 | static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) |
1879 | { | |
1880 | int i; | |
1881 | ||
1882 | gma_write16(hw, port, GM_SMI_DATA, val); | |
1883 | gma_write16(hw, port, GM_SMI_CTRL, | |
1884 | GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg)); | |
1885 | for (i = 0; i < PHY_RETRIES; i++) { | |
1886 | udelay(1); | |
1887 | ||
1888 | if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) | |
1889 | return 0; | |
1890 | } | |
1891 | ||
f15063cd | 1892 | pr_warning("%s: phy write timeout\n", hw->dev[port]->name); |
2cd8e5d3 SH |
1893 | return -EIO; |
1894 | } | |
1895 | ||
1896 | static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) | |
1897 | { | |
1898 | int i; | |
1899 | ||
1900 | gma_write16(hw, port, GM_SMI_CTRL, | |
1901 | GM_SMI_CT_PHY_AD(hw->phy_addr) | |
1902 | | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); | |
1903 | ||
1904 | for (i = 0; i < PHY_RETRIES; i++) { | |
1905 | udelay(1); | |
1906 | if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) | |
1907 | goto ready; | |
1908 | } | |
1909 | ||
1910 | return -ETIMEDOUT; | |
1911 | ready: | |
1912 | *val = gma_read16(hw, port, GM_SMI_DATA); | |
1913 | return 0; | |
1914 | } | |
1915 | ||
1916 | static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg) | |
1917 | { | |
1918 | u16 v = 0; | |
1919 | if (__gm_phy_read(hw, port, reg, &v)) | |
f15063cd | 1920 | pr_warning("%s: phy read timeout\n", hw->dev[port]->name); |
2cd8e5d3 SH |
1921 | return v; |
1922 | } | |
1923 | ||
8f3f8193 | 1924 | /* Marvell Phy Initialization */ |
baef58b1 SH |
1925 | static void yukon_init(struct skge_hw *hw, int port) |
1926 | { | |
1927 | struct skge_port *skge = netdev_priv(hw->dev[port]); | |
1928 | u16 ctrl, ct1000, adv; | |
baef58b1 | 1929 | |
baef58b1 | 1930 | if (skge->autoneg == AUTONEG_ENABLE) { |
6b0c1480 | 1931 | u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); |
baef58b1 SH |
1932 | |
1933 | ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | | |
1934 | PHY_M_EC_MAC_S_MSK); | |
1935 | ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); | |
1936 | ||
c506a509 | 1937 | ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); |
baef58b1 | 1938 | |
6b0c1480 | 1939 | gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); |
baef58b1 SH |
1940 | } |
1941 | ||
6b0c1480 | 1942 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); |
baef58b1 SH |
1943 | if (skge->autoneg == AUTONEG_DISABLE) |
1944 | ctrl &= ~PHY_CT_ANE; | |
1945 | ||
1946 | ctrl |= PHY_CT_RESET; | |
6b0c1480 | 1947 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); |
baef58b1 SH |
1948 | |
1949 | ctrl = 0; | |
1950 | ct1000 = 0; | |
b18f2091 | 1951 | adv = PHY_AN_CSMA; |
baef58b1 SH |
1952 | |
1953 | if (skge->autoneg == AUTONEG_ENABLE) { | |
5e1705dd | 1954 | if (hw->copper) { |
baef58b1 SH |
1955 | if (skge->advertising & ADVERTISED_1000baseT_Full) |
1956 | ct1000 |= PHY_M_1000C_AFD; | |
1957 | if (skge->advertising & ADVERTISED_1000baseT_Half) | |
1958 | ct1000 |= PHY_M_1000C_AHD; | |
1959 | if (skge->advertising & ADVERTISED_100baseT_Full) | |
1960 | adv |= PHY_M_AN_100_FD; | |
1961 | if (skge->advertising & ADVERTISED_100baseT_Half) | |
1962 | adv |= PHY_M_AN_100_HD; | |
1963 | if (skge->advertising & ADVERTISED_10baseT_Full) | |
1964 | adv |= PHY_M_AN_10_FD; | |
1965 | if (skge->advertising & ADVERTISED_10baseT_Half) | |
1966 | adv |= PHY_M_AN_10_HD; | |
baef58b1 | 1967 | |
4b67be99 SH |
1968 | /* Set Flow-control capabilities */ |
1969 | adv |= phy_pause_map[skge->flow_control]; | |
1970 | } else { | |
1971 | if (skge->advertising & ADVERTISED_1000baseT_Full) | |
1972 | adv |= PHY_M_AN_1000X_AFD; | |
1973 | if (skge->advertising & ADVERTISED_1000baseT_Half) | |
1974 | adv |= PHY_M_AN_1000X_AHD; | |
1975 | ||
1976 | adv |= fiber_pause_map[skge->flow_control]; | |
1977 | } | |
45bada65 | 1978 | |
baef58b1 SH |
1979 | /* Restart Auto-negotiation */ |
1980 | ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; | |
1981 | } else { | |
1982 | /* forced speed/duplex settings */ | |
1983 | ct1000 = PHY_M_1000C_MSE; | |
1984 | ||
1985 | if (skge->duplex == DUPLEX_FULL) | |
1986 | ctrl |= PHY_CT_DUP_MD; | |
1987 | ||
1988 | switch (skge->speed) { | |
1989 | case SPEED_1000: | |
1990 | ctrl |= PHY_CT_SP1000; | |
1991 | break; | |
1992 | case SPEED_100: | |
1993 | ctrl |= PHY_CT_SP100; | |
1994 | break; | |
1995 | } | |
1996 | ||
1997 | ctrl |= PHY_CT_RESET; | |
1998 | } | |
1999 | ||
c506a509 | 2000 | gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); |
baef58b1 | 2001 | |
6b0c1480 SH |
2002 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); |
2003 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
baef58b1 | 2004 | |
baef58b1 SH |
2005 | /* Enable phy interrupt on autonegotiation complete (or link up) */ |
2006 | if (skge->autoneg == AUTONEG_ENABLE) | |
4cde06ed | 2007 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK); |
baef58b1 | 2008 | else |
4cde06ed | 2009 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); |
baef58b1 SH |
2010 | } |
2011 | ||
2012 | static void yukon_reset(struct skge_hw *hw, int port) | |
2013 | { | |
6b0c1480 SH |
2014 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */ |
2015 | gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ | |
2016 | gma_write16(hw, port, GM_MC_ADDR_H2, 0); | |
2017 | gma_write16(hw, port, GM_MC_ADDR_H3, 0); | |
2018 | gma_write16(hw, port, GM_MC_ADDR_H4, 0); | |
baef58b1 | 2019 | |
6b0c1480 SH |
2020 | gma_write16(hw, port, GM_RX_CTRL, |
2021 | gma_read16(hw, port, GM_RX_CTRL) | |
baef58b1 SH |
2022 | | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); |
2023 | } | |
2024 | ||
c8868611 SH |
2025 | /* Apparently, early versions of Yukon-Lite had wrong chip_id? */ |
2026 | static int is_yukon_lite_a0(struct skge_hw *hw) | |
2027 | { | |
2028 | u32 reg; | |
2029 | int ret; | |
2030 | ||
2031 | if (hw->chip_id != CHIP_ID_YUKON) | |
2032 | return 0; | |
2033 | ||
2034 | reg = skge_read32(hw, B2_FAR); | |
2035 | skge_write8(hw, B2_FAR + 3, 0xff); | |
2036 | ret = (skge_read8(hw, B2_FAR + 3) != 0); | |
2037 | skge_write32(hw, B2_FAR, reg); | |
2038 | return ret; | |
2039 | } | |
2040 | ||
baef58b1 SH |
2041 | static void yukon_mac_init(struct skge_hw *hw, int port) |
2042 | { | |
2043 | struct skge_port *skge = netdev_priv(hw->dev[port]); | |
2044 | int i; | |
2045 | u32 reg; | |
2046 | const u8 *addr = hw->dev[port]->dev_addr; | |
2047 | ||
2048 | /* WA code for COMA mode -- set PHY reset */ | |
2049 | if (hw->chip_id == CHIP_ID_YUKON_LITE && | |
46a60f2d SH |
2050 | hw->chip_rev >= CHIP_REV_YU_LITE_A3) { |
2051 | reg = skge_read32(hw, B2_GP_IO); | |
2052 | reg |= GP_DIR_9 | GP_IO_9; | |
2053 | skge_write32(hw, B2_GP_IO, reg); | |
2054 | } | |
baef58b1 SH |
2055 | |
2056 | /* hard reset */ | |
6b0c1480 SH |
2057 | skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
2058 | skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); | |
baef58b1 SH |
2059 | |
2060 | /* WA code for COMA mode -- clear PHY reset */ | |
2061 | if (hw->chip_id == CHIP_ID_YUKON_LITE && | |
46a60f2d SH |
2062 | hw->chip_rev >= CHIP_REV_YU_LITE_A3) { |
2063 | reg = skge_read32(hw, B2_GP_IO); | |
2064 | reg |= GP_DIR_9; | |
2065 | reg &= ~GP_IO_9; | |
2066 | skge_write32(hw, B2_GP_IO, reg); | |
2067 | } | |
baef58b1 SH |
2068 | |
2069 | /* Set hardware config mode */ | |
2070 | reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP | | |
2071 | GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE; | |
5e1705dd | 2072 | reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB; |
baef58b1 SH |
2073 | |
2074 | /* Clear GMC reset */ | |
6b0c1480 SH |
2075 | skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET); |
2076 | skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR); | |
2077 | skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR); | |
564f9abb | 2078 | |
baef58b1 SH |
2079 | if (skge->autoneg == AUTONEG_DISABLE) { |
2080 | reg = GM_GPCR_AU_ALL_DIS; | |
6b0c1480 SH |
2081 | gma_write16(hw, port, GM_GP_CTRL, |
2082 | gma_read16(hw, port, GM_GP_CTRL) | reg); | |
baef58b1 SH |
2083 | |
2084 | switch (skge->speed) { | |
2085 | case SPEED_1000: | |
564f9abb | 2086 | reg &= ~GM_GPCR_SPEED_100; |
baef58b1 | 2087 | reg |= GM_GPCR_SPEED_1000; |
564f9abb | 2088 | break; |
baef58b1 | 2089 | case SPEED_100: |
564f9abb | 2090 | reg &= ~GM_GPCR_SPEED_1000; |
baef58b1 | 2091 | reg |= GM_GPCR_SPEED_100; |
564f9abb SH |
2092 | break; |
2093 | case SPEED_10: | |
2094 | reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); | |
2095 | break; | |
baef58b1 SH |
2096 | } |
2097 | ||
2098 | if (skge->duplex == DUPLEX_FULL) | |
2099 | reg |= GM_GPCR_DUP_FULL; | |
2100 | } else | |
2101 | reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; | |
564f9abb | 2102 | |
baef58b1 SH |
2103 | switch (skge->flow_control) { |
2104 | case FLOW_MODE_NONE: | |
6b0c1480 | 2105 | skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); |
baef58b1 SH |
2106 | reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; |
2107 | break; | |
2108 | case FLOW_MODE_LOC_SEND: | |
2109 | /* disable Rx flow-control */ | |
2110 | reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
5d5c8e03 SH |
2111 | break; |
2112 | case FLOW_MODE_SYMMETRIC: | |
2113 | case FLOW_MODE_SYM_OR_REM: | |
2114 | /* enable Tx & Rx flow-control */ | |
2115 | break; | |
baef58b1 SH |
2116 | } |
2117 | ||
6b0c1480 | 2118 | gma_write16(hw, port, GM_GP_CTRL, reg); |
46a60f2d | 2119 | skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); |
baef58b1 | 2120 | |
baef58b1 | 2121 | yukon_init(hw, port); |
baef58b1 SH |
2122 | |
2123 | /* MIB clear */ | |
6b0c1480 SH |
2124 | reg = gma_read16(hw, port, GM_PHY_ADDR); |
2125 | gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); | |
baef58b1 SH |
2126 | |
2127 | for (i = 0; i < GM_MIB_CNT_SIZE; i++) | |
6b0c1480 SH |
2128 | gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i); |
2129 | gma_write16(hw, port, GM_PHY_ADDR, reg); | |
baef58b1 SH |
2130 | |
2131 | /* transmit control */ | |
6b0c1480 | 2132 | gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); |
baef58b1 SH |
2133 | |
2134 | /* receive control reg: unicast + multicast + no FCS */ | |
6b0c1480 | 2135 | gma_write16(hw, port, GM_RX_CTRL, |
baef58b1 SH |
2136 | GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); |
2137 | ||
2138 | /* transmit flow control */ | |
6b0c1480 | 2139 | gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); |
baef58b1 SH |
2140 | |
2141 | /* transmit parameter */ | |
6b0c1480 | 2142 | gma_write16(hw, port, GM_TX_PARAM, |
baef58b1 SH |
2143 | TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | |
2144 | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | | |
2145 | TX_IPG_JAM_DATA(TX_IPG_JAM_DEF)); | |
2146 | ||
44c7fcce SH |
2147 | /* configure the Serial Mode Register */ |
2148 | reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | |
2149 | | GM_SMOD_VLAN_ENA | |
2150 | | IPG_DATA_VAL(IPG_DATA_DEF); | |
2151 | ||
2152 | if (hw->dev[port]->mtu > ETH_DATA_LEN) | |
baef58b1 SH |
2153 | reg |= GM_SMOD_JUMBO_ENA; |
2154 | ||
6b0c1480 | 2155 | gma_write16(hw, port, GM_SERIAL_MODE, reg); |
baef58b1 SH |
2156 | |
2157 | /* physical address: used for pause frames */ | |
6b0c1480 | 2158 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); |
baef58b1 | 2159 | /* virtual address for data */ |
6b0c1480 | 2160 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); |
baef58b1 SH |
2161 | |
2162 | /* enable interrupt mask for counter overflows */ | |
6b0c1480 SH |
2163 | gma_write16(hw, port, GM_TX_IRQ_MSK, 0); |
2164 | gma_write16(hw, port, GM_RX_IRQ_MSK, 0); | |
2165 | gma_write16(hw, port, GM_TR_IRQ_MSK, 0); | |
baef58b1 SH |
2166 | |
2167 | /* Initialize Mac Fifo */ | |
2168 | ||
2169 | /* Configure Rx MAC FIFO */ | |
6b0c1480 | 2170 | skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK); |
baef58b1 | 2171 | reg = GMF_OPER_ON | GMF_RX_F_FL_ON; |
c8868611 SH |
2172 | |
2173 | /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */ | |
2174 | if (is_yukon_lite_a0(hw)) | |
baef58b1 | 2175 | reg &= ~GMF_RX_F_FL_ON; |
c8868611 | 2176 | |
6b0c1480 SH |
2177 | skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); |
2178 | skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg); | |
c5923081 SH |
2179 | /* |
2180 | * because Pause Packet Truncation in GMAC is not working | |
2181 | * we have to increase the Flush Threshold to 64 bytes | |
2182 | * in order to flush pause packets in Rx FIFO on Yukon-1 | |
2183 | */ | |
2184 | skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1); | |
baef58b1 SH |
2185 | |
2186 | /* Configure Tx MAC FIFO */ | |
6b0c1480 SH |
2187 | skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); |
2188 | skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); | |
baef58b1 SH |
2189 | } |
2190 | ||
355ec572 SH |
2191 | /* Go into power down mode */ |
2192 | static void yukon_suspend(struct skge_hw *hw, int port) | |
2193 | { | |
2194 | u16 ctrl; | |
2195 | ||
2196 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
2197 | ctrl |= PHY_M_PC_POL_R_DIS; | |
2198 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
2199 | ||
2200 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); | |
2201 | ctrl |= PHY_CT_RESET; | |
2202 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
2203 | ||
2204 | /* switch IEEE compatible power down mode on */ | |
2205 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); | |
2206 | ctrl |= PHY_CT_PDOWN; | |
2207 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
2208 | } | |
2209 | ||
baef58b1 SH |
2210 | static void yukon_stop(struct skge_port *skge) |
2211 | { | |
2212 | struct skge_hw *hw = skge->hw; | |
2213 | int port = skge->port; | |
2214 | ||
46a60f2d SH |
2215 | skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); |
2216 | yukon_reset(hw, port); | |
baef58b1 | 2217 | |
6b0c1480 SH |
2218 | gma_write16(hw, port, GM_GP_CTRL, |
2219 | gma_read16(hw, port, GM_GP_CTRL) | |
0eedf4ac | 2220 | & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA)); |
6b0c1480 | 2221 | gma_read16(hw, port, GM_GP_CTRL); |
baef58b1 | 2222 | |
355ec572 | 2223 | yukon_suspend(hw, port); |
46a60f2d | 2224 | |
baef58b1 | 2225 | /* set GPHY Control reset */ |
46a60f2d SH |
2226 | skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
2227 | skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); | |
baef58b1 SH |
2228 | } |
2229 | ||
2230 | static void yukon_get_stats(struct skge_port *skge, u64 *data) | |
2231 | { | |
2232 | struct skge_hw *hw = skge->hw; | |
2233 | int port = skge->port; | |
2234 | int i; | |
2235 | ||
6b0c1480 SH |
2236 | data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 |
2237 | | gma_read32(hw, port, GM_TXO_OK_LO); | |
2238 | data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 | |
2239 | | gma_read32(hw, port, GM_RXO_OK_LO); | |
baef58b1 SH |
2240 | |
2241 | for (i = 2; i < ARRAY_SIZE(skge_stats); i++) | |
6b0c1480 | 2242 | data[i] = gma_read32(hw, port, |
baef58b1 SH |
2243 | skge_stats[i].gma_offset); |
2244 | } | |
2245 | ||
2246 | static void yukon_mac_intr(struct skge_hw *hw, int port) | |
2247 | { | |
7e676d91 SH |
2248 | struct net_device *dev = hw->dev[port]; |
2249 | struct skge_port *skge = netdev_priv(dev); | |
6b0c1480 | 2250 | u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); |
baef58b1 | 2251 | |
d707204c JP |
2252 | netif_printk(skge, intr, KERN_DEBUG, skge->netdev, |
2253 | "mac interrupt status 0x%x\n", status); | |
7e676d91 | 2254 | |
baef58b1 | 2255 | if (status & GM_IS_RX_FF_OR) { |
da00772f | 2256 | ++dev->stats.rx_fifo_errors; |
d8a09943 | 2257 | skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); |
baef58b1 | 2258 | } |
d8a09943 | 2259 | |
baef58b1 | 2260 | if (status & GM_IS_TX_FF_UR) { |
da00772f | 2261 | ++dev->stats.tx_fifo_errors; |
d8a09943 | 2262 | skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); |
baef58b1 SH |
2263 | } |
2264 | ||
2265 | } | |
2266 | ||
2267 | static u16 yukon_speed(const struct skge_hw *hw, u16 aux) | |
2268 | { | |
95566065 | 2269 | switch (aux & PHY_M_PS_SPEED_MSK) { |
baef58b1 SH |
2270 | case PHY_M_PS_SPEED_1000: |
2271 | return SPEED_1000; | |
2272 | case PHY_M_PS_SPEED_100: | |
2273 | return SPEED_100; | |
2274 | default: | |
2275 | return SPEED_10; | |
2276 | } | |
2277 | } | |
2278 | ||
2279 | static void yukon_link_up(struct skge_port *skge) | |
2280 | { | |
2281 | struct skge_hw *hw = skge->hw; | |
2282 | int port = skge->port; | |
2283 | u16 reg; | |
2284 | ||
baef58b1 | 2285 | /* Enable Transmit FIFO Underrun */ |
46a60f2d | 2286 | skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); |
baef58b1 | 2287 | |
6b0c1480 | 2288 | reg = gma_read16(hw, port, GM_GP_CTRL); |
baef58b1 SH |
2289 | if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE) |
2290 | reg |= GM_GPCR_DUP_FULL; | |
2291 | ||
2292 | /* enable Rx/Tx */ | |
2293 | reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; | |
6b0c1480 | 2294 | gma_write16(hw, port, GM_GP_CTRL, reg); |
baef58b1 | 2295 | |
4cde06ed | 2296 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); |
baef58b1 SH |
2297 | skge_link_up(skge); |
2298 | } | |
2299 | ||
2300 | static void yukon_link_down(struct skge_port *skge) | |
2301 | { | |
2302 | struct skge_hw *hw = skge->hw; | |
2303 | int port = skge->port; | |
d8a09943 | 2304 | u16 ctrl; |
baef58b1 | 2305 | |
d8a09943 SH |
2306 | ctrl = gma_read16(hw, port, GM_GP_CTRL); |
2307 | ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); | |
2308 | gma_write16(hw, port, GM_GP_CTRL, ctrl); | |
baef58b1 | 2309 | |
5d5c8e03 SH |
2310 | if (skge->flow_status == FLOW_STAT_REM_SEND) { |
2311 | ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); | |
2312 | ctrl |= PHY_M_AN_ASP; | |
baef58b1 | 2313 | /* restore Asymmetric Pause bit */ |
5d5c8e03 | 2314 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl); |
baef58b1 SH |
2315 | } |
2316 | ||
baef58b1 SH |
2317 | skge_link_down(skge); |
2318 | ||
2319 | yukon_init(hw, port); | |
2320 | } | |
2321 | ||
2322 | static void yukon_phy_intr(struct skge_port *skge) | |
2323 | { | |
2324 | struct skge_hw *hw = skge->hw; | |
2325 | int port = skge->port; | |
2326 | const char *reason = NULL; | |
2327 | u16 istatus, phystat; | |
2328 | ||
6b0c1480 SH |
2329 | istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); |
2330 | phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); | |
7e676d91 | 2331 | |
d707204c JP |
2332 | netif_printk(skge, intr, KERN_DEBUG, skge->netdev, |
2333 | "phy interrupt status 0x%x 0x%x\n", istatus, phystat); | |
baef58b1 SH |
2334 | |
2335 | if (istatus & PHY_M_IS_AN_COMPL) { | |
6b0c1480 | 2336 | if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP) |
baef58b1 SH |
2337 | & PHY_M_AN_RF) { |
2338 | reason = "remote fault"; | |
2339 | goto failed; | |
2340 | } | |
2341 | ||
c506a509 | 2342 | if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { |
baef58b1 SH |
2343 | reason = "master/slave fault"; |
2344 | goto failed; | |
2345 | } | |
2346 | ||
2347 | if (!(phystat & PHY_M_PS_SPDUP_RES)) { | |
2348 | reason = "speed/duplex"; | |
2349 | goto failed; | |
2350 | } | |
2351 | ||
2352 | skge->duplex = (phystat & PHY_M_PS_FULL_DUP) | |
2353 | ? DUPLEX_FULL : DUPLEX_HALF; | |
2354 | skge->speed = yukon_speed(hw, phystat); | |
2355 | ||
baef58b1 SH |
2356 | /* We are using IEEE 802.3z/D5.0 Table 37-4 */ |
2357 | switch (phystat & PHY_M_PS_PAUSE_MSK) { | |
2358 | case PHY_M_PS_PAUSE_MSK: | |
5d5c8e03 | 2359 | skge->flow_status = FLOW_STAT_SYMMETRIC; |
baef58b1 SH |
2360 | break; |
2361 | case PHY_M_PS_RX_P_EN: | |
5d5c8e03 | 2362 | skge->flow_status = FLOW_STAT_REM_SEND; |
baef58b1 SH |
2363 | break; |
2364 | case PHY_M_PS_TX_P_EN: | |
5d5c8e03 | 2365 | skge->flow_status = FLOW_STAT_LOC_SEND; |
baef58b1 SH |
2366 | break; |
2367 | default: | |
5d5c8e03 | 2368 | skge->flow_status = FLOW_STAT_NONE; |
baef58b1 SH |
2369 | } |
2370 | ||
5d5c8e03 | 2371 | if (skge->flow_status == FLOW_STAT_NONE || |
baef58b1 | 2372 | (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF)) |
6b0c1480 | 2373 | skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); |
baef58b1 | 2374 | else |
6b0c1480 | 2375 | skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); |
baef58b1 SH |
2376 | yukon_link_up(skge); |
2377 | return; | |
2378 | } | |
2379 | ||
2380 | if (istatus & PHY_M_IS_LSP_CHANGE) | |
2381 | skge->speed = yukon_speed(hw, phystat); | |
2382 | ||
2383 | if (istatus & PHY_M_IS_DUP_CHANGE) | |
2384 | skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
2385 | if (istatus & PHY_M_IS_LST_CHANGE) { | |
2386 | if (phystat & PHY_M_PS_LINK_UP) | |
2387 | yukon_link_up(skge); | |
2388 | else | |
2389 | yukon_link_down(skge); | |
2390 | } | |
2391 | return; | |
2392 | failed: | |
f15063cd | 2393 | pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason); |
baef58b1 SH |
2394 | |
2395 | /* XXX restart autonegotiation? */ | |
2396 | } | |
2397 | ||
ee294dcd SH |
2398 | static void skge_phy_reset(struct skge_port *skge) |
2399 | { | |
2400 | struct skge_hw *hw = skge->hw; | |
2401 | int port = skge->port; | |
aae343d4 | 2402 | struct net_device *dev = hw->dev[port]; |
ee294dcd SH |
2403 | |
2404 | netif_stop_queue(skge->netdev); | |
2405 | netif_carrier_off(skge->netdev); | |
2406 | ||
9cbe330f | 2407 | spin_lock_bh(&hw->phy_lock); |
ee294dcd SH |
2408 | if (hw->chip_id == CHIP_ID_GENESIS) { |
2409 | genesis_reset(hw, port); | |
2410 | genesis_mac_init(hw, port); | |
2411 | } else { | |
2412 | yukon_reset(hw, port); | |
2413 | yukon_init(hw, port); | |
2414 | } | |
9cbe330f | 2415 | spin_unlock_bh(&hw->phy_lock); |
75814090 | 2416 | |
f80d032b | 2417 | skge_set_multicast(dev); |
ee294dcd SH |
2418 | } |
2419 | ||
2cd8e5d3 SH |
2420 | /* Basic MII support */ |
2421 | static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
2422 | { | |
2423 | struct mii_ioctl_data *data = if_mii(ifr); | |
2424 | struct skge_port *skge = netdev_priv(dev); | |
2425 | struct skge_hw *hw = skge->hw; | |
2426 | int err = -EOPNOTSUPP; | |
2427 | ||
2428 | if (!netif_running(dev)) | |
2429 | return -ENODEV; /* Phy still in reset */ | |
2430 | ||
67777f9b | 2431 | switch (cmd) { |
2cd8e5d3 SH |
2432 | case SIOCGMIIPHY: |
2433 | data->phy_id = hw->phy_addr; | |
2434 | ||
2435 | /* fallthru */ | |
2436 | case SIOCGMIIREG: { | |
2437 | u16 val = 0; | |
9cbe330f | 2438 | spin_lock_bh(&hw->phy_lock); |
2cd8e5d3 SH |
2439 | if (hw->chip_id == CHIP_ID_GENESIS) |
2440 | err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); | |
2441 | else | |
2442 | err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); | |
9cbe330f | 2443 | spin_unlock_bh(&hw->phy_lock); |
2cd8e5d3 SH |
2444 | data->val_out = val; |
2445 | break; | |
2446 | } | |
2447 | ||
2448 | case SIOCSMIIREG: | |
9cbe330f | 2449 | spin_lock_bh(&hw->phy_lock); |
2cd8e5d3 SH |
2450 | if (hw->chip_id == CHIP_ID_GENESIS) |
2451 | err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f, | |
2452 | data->val_in); | |
2453 | else | |
2454 | err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f, | |
2455 | data->val_in); | |
9cbe330f | 2456 | spin_unlock_bh(&hw->phy_lock); |
2cd8e5d3 SH |
2457 | break; |
2458 | } | |
2459 | return err; | |
2460 | } | |
2461 | ||
279e1dab | 2462 | static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len) |
baef58b1 SH |
2463 | { |
2464 | u32 end; | |
2465 | ||
279e1dab LT |
2466 | start /= 8; |
2467 | len /= 8; | |
2468 | end = start + len - 1; | |
baef58b1 SH |
2469 | |
2470 | skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); | |
2471 | skge_write32(hw, RB_ADDR(q, RB_START), start); | |
2472 | skge_write32(hw, RB_ADDR(q, RB_WP), start); | |
2473 | skge_write32(hw, RB_ADDR(q, RB_RP), start); | |
279e1dab | 2474 | skge_write32(hw, RB_ADDR(q, RB_END), end); |
baef58b1 SH |
2475 | |
2476 | if (q == Q_R1 || q == Q_R2) { | |
2477 | /* Set thresholds on receive queue's */ | |
279e1dab LT |
2478 | skge_write32(hw, RB_ADDR(q, RB_RX_UTPP), |
2479 | start + (2*len)/3); | |
2480 | skge_write32(hw, RB_ADDR(q, RB_RX_LTPP), | |
2481 | start + (len/3)); | |
2482 | } else { | |
2483 | /* Enable store & forward on Tx queue's because | |
2484 | * Tx FIFO is only 4K on Genesis and 1K on Yukon | |
2485 | */ | |
baef58b1 | 2486 | skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); |
279e1dab | 2487 | } |
baef58b1 SH |
2488 | |
2489 | skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); | |
2490 | } | |
2491 | ||
2492 | /* Setup Bus Memory Interface */ | |
2493 | static void skge_qset(struct skge_port *skge, u16 q, | |
2494 | const struct skge_element *e) | |
2495 | { | |
2496 | struct skge_hw *hw = skge->hw; | |
2497 | u32 watermark = 0x600; | |
2498 | u64 base = skge->dma + (e->desc - skge->mem); | |
2499 | ||
2500 | /* optimization to reduce window on 32bit/33mhz */ | |
2501 | if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0) | |
2502 | watermark /= 2; | |
2503 | ||
2504 | skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); | |
2505 | skge_write32(hw, Q_ADDR(q, Q_F), watermark); | |
2506 | skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); | |
2507 | skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); | |
2508 | } | |
2509 | ||
2510 | static int skge_up(struct net_device *dev) | |
2511 | { | |
2512 | struct skge_port *skge = netdev_priv(dev); | |
2513 | struct skge_hw *hw = skge->hw; | |
2514 | int port = skge->port; | |
279e1dab | 2515 | u32 chunk, ram_addr; |
baef58b1 SH |
2516 | size_t rx_size, tx_size; |
2517 | int err; | |
2518 | ||
fae87592 SH |
2519 | if (!is_valid_ether_addr(dev->dev_addr)) |
2520 | return -EINVAL; | |
2521 | ||
d707204c | 2522 | netif_info(skge, ifup, skge->netdev, "enabling interface\n"); |
baef58b1 | 2523 | |
19a33d4e | 2524 | if (dev->mtu > RX_BUF_SIZE) |
901ccefb | 2525 | skge->rx_buf_size = dev->mtu + ETH_HLEN; |
19a33d4e SH |
2526 | else |
2527 | skge->rx_buf_size = RX_BUF_SIZE; | |
2528 | ||
2529 | ||
baef58b1 SH |
2530 | rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc); |
2531 | tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc); | |
2532 | skge->mem_size = tx_size + rx_size; | |
2533 | skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma); | |
2534 | if (!skge->mem) | |
2535 | return -ENOMEM; | |
2536 | ||
c3da1447 SH |
2537 | BUG_ON(skge->dma & 7); |
2538 | ||
2539 | if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) { | |
1479d13c | 2540 | dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n"); |
c3da1447 SH |
2541 | err = -EINVAL; |
2542 | goto free_pci_mem; | |
2543 | } | |
2544 | ||
baef58b1 SH |
2545 | memset(skge->mem, 0, skge->mem_size); |
2546 | ||
203babb6 SH |
2547 | err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma); |
2548 | if (err) | |
baef58b1 SH |
2549 | goto free_pci_mem; |
2550 | ||
c54f9765 | 2551 | err = skge_rx_fill(dev); |
19a33d4e | 2552 | if (err) |
baef58b1 SH |
2553 | goto free_rx_ring; |
2554 | ||
203babb6 SH |
2555 | err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size, |
2556 | skge->dma + rx_size); | |
2557 | if (err) | |
baef58b1 SH |
2558 | goto free_rx_ring; |
2559 | ||
8f3f8193 | 2560 | /* Initialize MAC */ |
9cbe330f | 2561 | spin_lock_bh(&hw->phy_lock); |
baef58b1 SH |
2562 | if (hw->chip_id == CHIP_ID_GENESIS) |
2563 | genesis_mac_init(hw, port); | |
2564 | else | |
2565 | yukon_mac_init(hw, port); | |
9cbe330f | 2566 | spin_unlock_bh(&hw->phy_lock); |
baef58b1 | 2567 | |
29816d9a SH |
2568 | /* Configure RAMbuffers - equally between ports and tx/rx */ |
2569 | chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2); | |
279e1dab | 2570 | ram_addr = hw->ram_offset + 2 * chunk * port; |
baef58b1 | 2571 | |
279e1dab | 2572 | skge_ramset(hw, rxqaddr[port], ram_addr, chunk); |
7fb7ac24 | 2573 | skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean); |
279e1dab | 2574 | |
baef58b1 | 2575 | BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean); |
279e1dab | 2576 | skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk); |
baef58b1 SH |
2577 | skge_qset(skge, txqaddr[port], skge->tx_ring.to_use); |
2578 | ||
2579 | /* Start receiver BMU */ | |
2580 | wmb(); | |
2581 | skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F); | |
6abebb53 | 2582 | skge_led(skge, LED_MODE_ON); |
baef58b1 | 2583 | |
4ebabfcb SH |
2584 | spin_lock_irq(&hw->hw_lock); |
2585 | hw->intr_mask |= portmask[port]; | |
2586 | skge_write32(hw, B0_IMSK, hw->intr_mask); | |
2587 | spin_unlock_irq(&hw->hw_lock); | |
2588 | ||
bea3348e | 2589 | napi_enable(&skge->napi); |
baef58b1 SH |
2590 | return 0; |
2591 | ||
2592 | free_rx_ring: | |
2593 | skge_rx_clean(skge); | |
2594 | kfree(skge->rx_ring.start); | |
2595 | free_pci_mem: | |
2596 | pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma); | |
7731a4ea | 2597 | skge->mem = NULL; |
baef58b1 SH |
2598 | |
2599 | return err; | |
2600 | } | |
2601 | ||
60b24b51 SH |
2602 | /* stop receiver */ |
2603 | static void skge_rx_stop(struct skge_hw *hw, int port) | |
2604 | { | |
2605 | skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); | |
2606 | skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL), | |
2607 | RB_RST_SET|RB_DIS_OP_MD); | |
2608 | skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); | |
2609 | } | |
2610 | ||
baef58b1 SH |
2611 | static int skge_down(struct net_device *dev) |
2612 | { | |
2613 | struct skge_port *skge = netdev_priv(dev); | |
2614 | struct skge_hw *hw = skge->hw; | |
2615 | int port = skge->port; | |
2616 | ||
7731a4ea SH |
2617 | if (skge->mem == NULL) |
2618 | return 0; | |
2619 | ||
d707204c | 2620 | netif_info(skge, ifdown, skge->netdev, "disabling interface\n"); |
baef58b1 | 2621 | |
d119b392 | 2622 | netif_tx_disable(dev); |
692412b3 | 2623 | |
64f6b64d | 2624 | if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC) |
9cbe330f | 2625 | del_timer_sync(&skge->link_timer); |
baef58b1 | 2626 | |
bea3348e | 2627 | napi_disable(&skge->napi); |
692412b3 | 2628 | netif_carrier_off(dev); |
4ebabfcb SH |
2629 | |
2630 | spin_lock_irq(&hw->hw_lock); | |
2631 | hw->intr_mask &= ~portmask[port]; | |
2632 | skge_write32(hw, B0_IMSK, hw->intr_mask); | |
2633 | spin_unlock_irq(&hw->hw_lock); | |
2634 | ||
46a60f2d SH |
2635 | skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF); |
2636 | if (hw->chip_id == CHIP_ID_GENESIS) | |
2637 | genesis_stop(skge); | |
2638 | else | |
2639 | yukon_stop(skge); | |
2640 | ||
baef58b1 SH |
2641 | /* Stop transmitter */ |
2642 | skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); | |
2643 | skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), | |
2644 | RB_RST_SET|RB_DIS_OP_MD); | |
2645 | ||
baef58b1 SH |
2646 | |
2647 | /* Disable Force Sync bit and Enable Alloc bit */ | |
6b0c1480 | 2648 | skge_write8(hw, SK_REG(port, TXA_CTRL), |
baef58b1 SH |
2649 | TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); |
2650 | ||
2651 | /* Stop Interval Timer and Limit Counter of Tx Arbiter */ | |
6b0c1480 SH |
2652 | skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); |
2653 | skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); | |
baef58b1 SH |
2654 | |
2655 | /* Reset PCI FIFO */ | |
2656 | skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); | |
2657 | skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); | |
2658 | ||
2659 | /* Reset the RAM Buffer async Tx queue */ | |
2660 | skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET); | |
60b24b51 SH |
2661 | |
2662 | skge_rx_stop(hw, port); | |
baef58b1 SH |
2663 | |
2664 | if (hw->chip_id == CHIP_ID_GENESIS) { | |
6b0c1480 SH |
2665 | skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET); |
2666 | skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET); | |
baef58b1 | 2667 | } else { |
6b0c1480 SH |
2668 | skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); |
2669 | skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); | |
baef58b1 SH |
2670 | } |
2671 | ||
6abebb53 | 2672 | skge_led(skge, LED_MODE_OFF); |
baef58b1 | 2673 | |
e3a1b99f | 2674 | netif_tx_lock_bh(dev); |
513f533e | 2675 | skge_tx_clean(dev); |
e3a1b99f SH |
2676 | netif_tx_unlock_bh(dev); |
2677 | ||
baef58b1 SH |
2678 | skge_rx_clean(skge); |
2679 | ||
2680 | kfree(skge->rx_ring.start); | |
2681 | kfree(skge->tx_ring.start); | |
2682 | pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma); | |
7731a4ea | 2683 | skge->mem = NULL; |
baef58b1 SH |
2684 | return 0; |
2685 | } | |
2686 | ||
29b4e886 SH |
2687 | static inline int skge_avail(const struct skge_ring *ring) |
2688 | { | |
992c9623 | 2689 | smp_mb(); |
29b4e886 SH |
2690 | return ((ring->to_clean > ring->to_use) ? 0 : ring->count) |
2691 | + (ring->to_clean - ring->to_use) - 1; | |
2692 | } | |
2693 | ||
61357325 SH |
2694 | static netdev_tx_t skge_xmit_frame(struct sk_buff *skb, |
2695 | struct net_device *dev) | |
baef58b1 SH |
2696 | { |
2697 | struct skge_port *skge = netdev_priv(dev); | |
2698 | struct skge_hw *hw = skge->hw; | |
baef58b1 SH |
2699 | struct skge_element *e; |
2700 | struct skge_tx_desc *td; | |
2701 | int i; | |
2702 | u32 control, len; | |
2703 | u64 map; | |
baef58b1 | 2704 | |
5b057c6b | 2705 | if (skb_padto(skb, ETH_ZLEN)) |
baef58b1 SH |
2706 | return NETDEV_TX_OK; |
2707 | ||
513f533e | 2708 | if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1)) |
baef58b1 | 2709 | return NETDEV_TX_BUSY; |
baef58b1 | 2710 | |
7c442fa1 | 2711 | e = skge->tx_ring.to_use; |
baef58b1 | 2712 | td = e->desc; |
7c442fa1 | 2713 | BUG_ON(td->control & BMU_OWN); |
baef58b1 SH |
2714 | e->skb = skb; |
2715 | len = skb_headlen(skb); | |
2716 | map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
10fc51b9 FT |
2717 | dma_unmap_addr_set(e, mapaddr, map); |
2718 | dma_unmap_len_set(e, maplen, len); | |
baef58b1 SH |
2719 | |
2720 | td->dma_lo = map; | |
2721 | td->dma_hi = map >> 32; | |
2722 | ||
84fa7933 | 2723 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
0d0b1672 | 2724 | const int offset = skb_checksum_start_offset(skb); |
baef58b1 SH |
2725 | |
2726 | /* This seems backwards, but it is what the sk98lin | |
2727 | * does. Looks like hardware is wrong? | |
2728 | */ | |
8e95a202 | 2729 | if (ipip_hdr(skb)->protocol == IPPROTO_UDP && |
67777f9b | 2730 | hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON) |
baef58b1 SH |
2731 | control = BMU_TCP_CHECK; |
2732 | else | |
2733 | control = BMU_UDP_CHECK; | |
2734 | ||
2735 | td->csum_offs = 0; | |
2736 | td->csum_start = offset; | |
ff1dcadb | 2737 | td->csum_write = offset + skb->csum_offset; |
baef58b1 SH |
2738 | } else |
2739 | control = BMU_CHECK; | |
2740 | ||
2741 | if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */ | |
67777f9b | 2742 | control |= BMU_EOF | BMU_IRQ_EOF; |
baef58b1 SH |
2743 | else { |
2744 | struct skge_tx_desc *tf = td; | |
2745 | ||
2746 | control |= BMU_STFWD; | |
2747 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
2748 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
2749 | ||
2750 | map = pci_map_page(hw->pdev, frag->page, frag->page_offset, | |
2751 | frag->size, PCI_DMA_TODEVICE); | |
2752 | ||
2753 | e = e->next; | |
7c442fa1 | 2754 | e->skb = skb; |
baef58b1 | 2755 | tf = e->desc; |
7c442fa1 SH |
2756 | BUG_ON(tf->control & BMU_OWN); |
2757 | ||
baef58b1 SH |
2758 | tf->dma_lo = map; |
2759 | tf->dma_hi = (u64) map >> 32; | |
10fc51b9 FT |
2760 | dma_unmap_addr_set(e, mapaddr, map); |
2761 | dma_unmap_len_set(e, maplen, frag->size); | |
baef58b1 SH |
2762 | |
2763 | tf->control = BMU_OWN | BMU_SW | control | frag->size; | |
2764 | } | |
2765 | tf->control |= BMU_EOF | BMU_IRQ_EOF; | |
2766 | } | |
2767 | /* Make sure all the descriptors written */ | |
2768 | wmb(); | |
2769 | td->control = BMU_OWN | BMU_SW | BMU_STF | control | len; | |
2770 | wmb(); | |
2771 | ||
2772 | skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); | |
2773 | ||
d707204c JP |
2774 | netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev, |
2775 | "tx queued, slot %td, len %d\n", | |
2776 | e - skge->tx_ring.start, skb->len); | |
baef58b1 | 2777 | |
7c442fa1 | 2778 | skge->tx_ring.to_use = e->next; |
992c9623 SH |
2779 | smp_wmb(); |
2780 | ||
9db96479 | 2781 | if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) { |
f15063cd | 2782 | netdev_dbg(dev, "transmit queue full\n"); |
baef58b1 SH |
2783 | netif_stop_queue(dev); |
2784 | } | |
2785 | ||
baef58b1 SH |
2786 | return NETDEV_TX_OK; |
2787 | } | |
2788 | ||
7c442fa1 SH |
2789 | |
2790 | /* Free resources associated with this reing element */ | |
2791 | static void skge_tx_free(struct skge_port *skge, struct skge_element *e, | |
2792 | u32 control) | |
866b4f3e SH |
2793 | { |
2794 | struct pci_dev *pdev = skge->hw->pdev; | |
866b4f3e | 2795 | |
7c442fa1 SH |
2796 | /* skb header vs. fragment */ |
2797 | if (control & BMU_STF) | |
10fc51b9 FT |
2798 | pci_unmap_single(pdev, dma_unmap_addr(e, mapaddr), |
2799 | dma_unmap_len(e, maplen), | |
7c442fa1 SH |
2800 | PCI_DMA_TODEVICE); |
2801 | else | |
10fc51b9 FT |
2802 | pci_unmap_page(pdev, dma_unmap_addr(e, mapaddr), |
2803 | dma_unmap_len(e, maplen), | |
7c442fa1 | 2804 | PCI_DMA_TODEVICE); |
866b4f3e | 2805 | |
7c442fa1 | 2806 | if (control & BMU_EOF) { |
d707204c JP |
2807 | netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev, |
2808 | "tx done slot %td\n", e - skge->tx_ring.start); | |
866b4f3e | 2809 | |
513f533e | 2810 | dev_kfree_skb(e->skb); |
baef58b1 SH |
2811 | } |
2812 | } | |
2813 | ||
7c442fa1 | 2814 | /* Free all buffers in transmit ring */ |
513f533e | 2815 | static void skge_tx_clean(struct net_device *dev) |
baef58b1 | 2816 | { |
513f533e | 2817 | struct skge_port *skge = netdev_priv(dev); |
7c442fa1 | 2818 | struct skge_element *e; |
baef58b1 | 2819 | |
7c442fa1 SH |
2820 | for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) { |
2821 | struct skge_tx_desc *td = e->desc; | |
2822 | skge_tx_free(skge, e, td->control); | |
2823 | td->control = 0; | |
2824 | } | |
2825 | ||
2826 | skge->tx_ring.to_clean = e; | |
baef58b1 SH |
2827 | } |
2828 | ||
2829 | static void skge_tx_timeout(struct net_device *dev) | |
2830 | { | |
2831 | struct skge_port *skge = netdev_priv(dev); | |
2832 | ||
d707204c | 2833 | netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n"); |
baef58b1 SH |
2834 | |
2835 | skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP); | |
513f533e | 2836 | skge_tx_clean(dev); |
d119b392 | 2837 | netif_wake_queue(dev); |
baef58b1 SH |
2838 | } |
2839 | ||
2840 | static int skge_change_mtu(struct net_device *dev, int new_mtu) | |
2841 | { | |
7731a4ea | 2842 | int err; |
baef58b1 | 2843 | |
95566065 | 2844 | if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) |
baef58b1 SH |
2845 | return -EINVAL; |
2846 | ||
7731a4ea SH |
2847 | if (!netif_running(dev)) { |
2848 | dev->mtu = new_mtu; | |
2849 | return 0; | |
2850 | } | |
2851 | ||
1a8098be | 2852 | skge_down(dev); |
baef58b1 | 2853 | |
19a33d4e | 2854 | dev->mtu = new_mtu; |
7731a4ea | 2855 | |
1a8098be | 2856 | err = skge_up(dev); |
7731a4ea SH |
2857 | if (err) |
2858 | dev_close(dev); | |
baef58b1 SH |
2859 | |
2860 | return err; | |
2861 | } | |
2862 | ||
c4cd29d2 SH |
2863 | static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 }; |
2864 | ||
2865 | static void genesis_add_filter(u8 filter[8], const u8 *addr) | |
2866 | { | |
2867 | u32 crc, bit; | |
2868 | ||
2869 | crc = ether_crc_le(ETH_ALEN, addr); | |
2870 | bit = ~crc & 0x3f; | |
2871 | filter[bit/8] |= 1 << (bit%8); | |
2872 | } | |
2873 | ||
baef58b1 SH |
2874 | static void genesis_set_multicast(struct net_device *dev) |
2875 | { | |
2876 | struct skge_port *skge = netdev_priv(dev); | |
2877 | struct skge_hw *hw = skge->hw; | |
2878 | int port = skge->port; | |
22bedad3 | 2879 | struct netdev_hw_addr *ha; |
baef58b1 SH |
2880 | u32 mode; |
2881 | u8 filter[8]; | |
2882 | ||
6b0c1480 | 2883 | mode = xm_read32(hw, port, XM_MODE); |
baef58b1 SH |
2884 | mode |= XM_MD_ENA_HASH; |
2885 | if (dev->flags & IFF_PROMISC) | |
2886 | mode |= XM_MD_ENA_PROM; | |
2887 | else | |
2888 | mode &= ~XM_MD_ENA_PROM; | |
2889 | ||
2890 | if (dev->flags & IFF_ALLMULTI) | |
2891 | memset(filter, 0xff, sizeof(filter)); | |
2892 | else { | |
2893 | memset(filter, 0, sizeof(filter)); | |
c4cd29d2 | 2894 | |
8e95a202 JP |
2895 | if (skge->flow_status == FLOW_STAT_REM_SEND || |
2896 | skge->flow_status == FLOW_STAT_SYMMETRIC) | |
c4cd29d2 SH |
2897 | genesis_add_filter(filter, pause_mc_addr); |
2898 | ||
22bedad3 JP |
2899 | netdev_for_each_mc_addr(ha, dev) |
2900 | genesis_add_filter(filter, ha->addr); | |
baef58b1 SH |
2901 | } |
2902 | ||
6b0c1480 | 2903 | xm_write32(hw, port, XM_MODE, mode); |
45bada65 | 2904 | xm_outhash(hw, port, XM_HSM, filter); |
baef58b1 SH |
2905 | } |
2906 | ||
c4cd29d2 SH |
2907 | static void yukon_add_filter(u8 filter[8], const u8 *addr) |
2908 | { | |
2909 | u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f; | |
2910 | filter[bit/8] |= 1 << (bit%8); | |
2911 | } | |
2912 | ||
baef58b1 SH |
2913 | static void yukon_set_multicast(struct net_device *dev) |
2914 | { | |
2915 | struct skge_port *skge = netdev_priv(dev); | |
2916 | struct skge_hw *hw = skge->hw; | |
2917 | int port = skge->port; | |
22bedad3 | 2918 | struct netdev_hw_addr *ha; |
8e95a202 JP |
2919 | int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND || |
2920 | skge->flow_status == FLOW_STAT_SYMMETRIC); | |
baef58b1 SH |
2921 | u16 reg; |
2922 | u8 filter[8]; | |
2923 | ||
2924 | memset(filter, 0, sizeof(filter)); | |
2925 | ||
6b0c1480 | 2926 | reg = gma_read16(hw, port, GM_RX_CTRL); |
baef58b1 SH |
2927 | reg |= GM_RXCR_UCF_ENA; |
2928 | ||
8f3f8193 | 2929 | if (dev->flags & IFF_PROMISC) /* promiscuous */ |
baef58b1 SH |
2930 | reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); |
2931 | else if (dev->flags & IFF_ALLMULTI) /* all multicast */ | |
2932 | memset(filter, 0xff, sizeof(filter)); | |
4cd24eaf | 2933 | else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */ |
baef58b1 SH |
2934 | reg &= ~GM_RXCR_MCF_ENA; |
2935 | else { | |
baef58b1 SH |
2936 | reg |= GM_RXCR_MCF_ENA; |
2937 | ||
c4cd29d2 SH |
2938 | if (rx_pause) |
2939 | yukon_add_filter(filter, pause_mc_addr); | |
2940 | ||
22bedad3 JP |
2941 | netdev_for_each_mc_addr(ha, dev) |
2942 | yukon_add_filter(filter, ha->addr); | |
baef58b1 SH |
2943 | } |
2944 | ||
2945 | ||
6b0c1480 | 2946 | gma_write16(hw, port, GM_MC_ADDR_H1, |
baef58b1 | 2947 | (u16)filter[0] | ((u16)filter[1] << 8)); |
6b0c1480 | 2948 | gma_write16(hw, port, GM_MC_ADDR_H2, |
baef58b1 | 2949 | (u16)filter[2] | ((u16)filter[3] << 8)); |
6b0c1480 | 2950 | gma_write16(hw, port, GM_MC_ADDR_H3, |
baef58b1 | 2951 | (u16)filter[4] | ((u16)filter[5] << 8)); |
6b0c1480 | 2952 | gma_write16(hw, port, GM_MC_ADDR_H4, |
baef58b1 SH |
2953 | (u16)filter[6] | ((u16)filter[7] << 8)); |
2954 | ||
6b0c1480 | 2955 | gma_write16(hw, port, GM_RX_CTRL, reg); |
baef58b1 SH |
2956 | } |
2957 | ||
383181ac SH |
2958 | static inline u16 phy_length(const struct skge_hw *hw, u32 status) |
2959 | { | |
2960 | if (hw->chip_id == CHIP_ID_GENESIS) | |
2961 | return status >> XMR_FS_LEN_SHIFT; | |
2962 | else | |
2963 | return status >> GMR_FS_LEN_SHIFT; | |
2964 | } | |
2965 | ||
baef58b1 SH |
2966 | static inline int bad_phy_status(const struct skge_hw *hw, u32 status) |
2967 | { | |
2968 | if (hw->chip_id == CHIP_ID_GENESIS) | |
2969 | return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0; | |
2970 | else | |
2971 | return (status & GMR_FS_ANY_ERR) || | |
2972 | (status & GMR_FS_RX_OK) == 0; | |
2973 | } | |
2974 | ||
f80d032b SH |
2975 | static void skge_set_multicast(struct net_device *dev) |
2976 | { | |
2977 | struct skge_port *skge = netdev_priv(dev); | |
2978 | struct skge_hw *hw = skge->hw; | |
2979 | ||
2980 | if (hw->chip_id == CHIP_ID_GENESIS) | |
2981 | genesis_set_multicast(dev); | |
2982 | else | |
2983 | yukon_set_multicast(dev); | |
2984 | ||
2985 | } | |
2986 | ||
19a33d4e SH |
2987 | |
2988 | /* Get receive buffer from descriptor. | |
2989 | * Handles copy of small buffers and reallocation failures | |
2990 | */ | |
c54f9765 SH |
2991 | static struct sk_buff *skge_rx_get(struct net_device *dev, |
2992 | struct skge_element *e, | |
2993 | u32 control, u32 status, u16 csum) | |
19a33d4e | 2994 | { |
c54f9765 | 2995 | struct skge_port *skge = netdev_priv(dev); |
383181ac SH |
2996 | struct sk_buff *skb; |
2997 | u16 len = control & BMU_BBC; | |
2998 | ||
d707204c JP |
2999 | netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev, |
3000 | "rx slot %td status 0x%x len %d\n", | |
3001 | e - skge->rx_ring.start, status, len); | |
383181ac SH |
3002 | |
3003 | if (len > skge->rx_buf_size) | |
3004 | goto error; | |
3005 | ||
3006 | if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)) | |
3007 | goto error; | |
3008 | ||
3009 | if (bad_phy_status(skge->hw, status)) | |
3010 | goto error; | |
3011 | ||
3012 | if (phy_length(skge->hw, status) != len) | |
3013 | goto error; | |
19a33d4e SH |
3014 | |
3015 | if (len < RX_COPY_THRESHOLD) { | |
89d71a66 | 3016 | skb = netdev_alloc_skb_ip_align(dev, len); |
383181ac SH |
3017 | if (!skb) |
3018 | goto resubmit; | |
19a33d4e SH |
3019 | |
3020 | pci_dma_sync_single_for_cpu(skge->hw->pdev, | |
10fc51b9 | 3021 | dma_unmap_addr(e, mapaddr), |
19a33d4e | 3022 | len, PCI_DMA_FROMDEVICE); |
d626f62b | 3023 | skb_copy_from_linear_data(e->skb, skb->data, len); |
19a33d4e | 3024 | pci_dma_sync_single_for_device(skge->hw->pdev, |
10fc51b9 | 3025 | dma_unmap_addr(e, mapaddr), |
19a33d4e | 3026 | len, PCI_DMA_FROMDEVICE); |
19a33d4e | 3027 | skge_rx_reuse(e, skge->rx_buf_size); |
19a33d4e | 3028 | } else { |
383181ac | 3029 | struct sk_buff *nskb; |
89d71a66 ED |
3030 | |
3031 | nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size); | |
383181ac SH |
3032 | if (!nskb) |
3033 | goto resubmit; | |
19a33d4e SH |
3034 | |
3035 | pci_unmap_single(skge->hw->pdev, | |
10fc51b9 FT |
3036 | dma_unmap_addr(e, mapaddr), |
3037 | dma_unmap_len(e, maplen), | |
19a33d4e SH |
3038 | PCI_DMA_FROMDEVICE); |
3039 | skb = e->skb; | |
67777f9b | 3040 | prefetch(skb->data); |
19a33d4e | 3041 | skge_rx_setup(skge, e, nskb, skge->rx_buf_size); |
baef58b1 | 3042 | } |
383181ac SH |
3043 | |
3044 | skb_put(skb, len); | |
e92702b1 MM |
3045 | |
3046 | if (dev->features & NETIF_F_RXCSUM) { | |
383181ac | 3047 | skb->csum = csum; |
84fa7933 | 3048 | skb->ip_summed = CHECKSUM_COMPLETE; |
383181ac SH |
3049 | } |
3050 | ||
c54f9765 | 3051 | skb->protocol = eth_type_trans(skb, dev); |
383181ac SH |
3052 | |
3053 | return skb; | |
3054 | error: | |
3055 | ||
d707204c JP |
3056 | netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev, |
3057 | "rx err, slot %td control 0x%x status 0x%x\n", | |
3058 | e - skge->rx_ring.start, control, status); | |
383181ac SH |
3059 | |
3060 | if (skge->hw->chip_id == CHIP_ID_GENESIS) { | |
3061 | if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR)) | |
da00772f | 3062 | dev->stats.rx_length_errors++; |
383181ac | 3063 | if (status & XMR_FS_FRA_ERR) |
da00772f | 3064 | dev->stats.rx_frame_errors++; |
383181ac | 3065 | if (status & XMR_FS_FCS_ERR) |
da00772f | 3066 | dev->stats.rx_crc_errors++; |
383181ac SH |
3067 | } else { |
3068 | if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE)) | |
da00772f | 3069 | dev->stats.rx_length_errors++; |
383181ac | 3070 | if (status & GMR_FS_FRAGMENT) |
da00772f | 3071 | dev->stats.rx_frame_errors++; |
383181ac | 3072 | if (status & GMR_FS_CRC_ERR) |
da00772f | 3073 | dev->stats.rx_crc_errors++; |
383181ac SH |
3074 | } |
3075 | ||
3076 | resubmit: | |
3077 | skge_rx_reuse(e, skge->rx_buf_size); | |
3078 | return NULL; | |
baef58b1 SH |
3079 | } |
3080 | ||
7c442fa1 | 3081 | /* Free all buffers in Tx ring which are no longer owned by device */ |
513f533e | 3082 | static void skge_tx_done(struct net_device *dev) |
00a6cae2 | 3083 | { |
7c442fa1 | 3084 | struct skge_port *skge = netdev_priv(dev); |
00a6cae2 | 3085 | struct skge_ring *ring = &skge->tx_ring; |
7c442fa1 SH |
3086 | struct skge_element *e; |
3087 | ||
513f533e | 3088 | skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); |
00a6cae2 | 3089 | |
866b4f3e | 3090 | for (e = ring->to_clean; e != ring->to_use; e = e->next) { |
992c9623 | 3091 | u32 control = ((const struct skge_tx_desc *) e->desc)->control; |
00a6cae2 | 3092 | |
992c9623 | 3093 | if (control & BMU_OWN) |
00a6cae2 SH |
3094 | break; |
3095 | ||
992c9623 | 3096 | skge_tx_free(skge, e, control); |
00a6cae2 | 3097 | } |
7c442fa1 | 3098 | skge->tx_ring.to_clean = e; |
866b4f3e | 3099 | |
992c9623 SH |
3100 | /* Can run lockless until we need to synchronize to restart queue. */ |
3101 | smp_mb(); | |
3102 | ||
3103 | if (unlikely(netif_queue_stopped(dev) && | |
3104 | skge_avail(&skge->tx_ring) > TX_LOW_WATER)) { | |
3105 | netif_tx_lock(dev); | |
3106 | if (unlikely(netif_queue_stopped(dev) && | |
3107 | skge_avail(&skge->tx_ring) > TX_LOW_WATER)) { | |
3108 | netif_wake_queue(dev); | |
00a6cae2 | 3109 | |
992c9623 SH |
3110 | } |
3111 | netif_tx_unlock(dev); | |
3112 | } | |
00a6cae2 | 3113 | } |
19a33d4e | 3114 | |
bea3348e | 3115 | static int skge_poll(struct napi_struct *napi, int to_do) |
baef58b1 | 3116 | { |
bea3348e SH |
3117 | struct skge_port *skge = container_of(napi, struct skge_port, napi); |
3118 | struct net_device *dev = skge->netdev; | |
baef58b1 SH |
3119 | struct skge_hw *hw = skge->hw; |
3120 | struct skge_ring *ring = &skge->rx_ring; | |
3121 | struct skge_element *e; | |
00a6cae2 SH |
3122 | int work_done = 0; |
3123 | ||
513f533e SH |
3124 | skge_tx_done(dev); |
3125 | ||
3126 | skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); | |
3127 | ||
1631aef1 | 3128 | for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) { |
baef58b1 | 3129 | struct skge_rx_desc *rd = e->desc; |
19a33d4e | 3130 | struct sk_buff *skb; |
383181ac | 3131 | u32 control; |
baef58b1 SH |
3132 | |
3133 | rmb(); | |
3134 | control = rd->control; | |
3135 | if (control & BMU_OWN) | |
3136 | break; | |
3137 | ||
c54f9765 | 3138 | skb = skge_rx_get(dev, e, control, rd->status, rd->csum2); |
19a33d4e | 3139 | if (likely(skb)) { |
86cac58b | 3140 | napi_gro_receive(napi, skb); |
19a33d4e | 3141 | ++work_done; |
5a011447 | 3142 | } |
baef58b1 SH |
3143 | } |
3144 | ring->to_clean = e; | |
3145 | ||
baef58b1 SH |
3146 | /* restart receiver */ |
3147 | wmb(); | |
a9cdab86 | 3148 | skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START); |
baef58b1 | 3149 | |
bea3348e | 3150 | if (work_done < to_do) { |
6ef2977d | 3151 | unsigned long flags; |
f0c88f9c | 3152 | |
86cac58b | 3153 | napi_gro_flush(napi); |
6ef2977d | 3154 | spin_lock_irqsave(&hw->hw_lock, flags); |
288379f0 | 3155 | __napi_complete(napi); |
bea3348e SH |
3156 | hw->intr_mask |= napimask[skge->port]; |
3157 | skge_write32(hw, B0_IMSK, hw->intr_mask); | |
3158 | skge_read32(hw, B0_IMSK); | |
6ef2977d | 3159 | spin_unlock_irqrestore(&hw->hw_lock, flags); |
bea3348e | 3160 | } |
1631aef1 | 3161 | |
bea3348e | 3162 | return work_done; |
baef58b1 SH |
3163 | } |
3164 | ||
f6620cab SH |
3165 | /* Parity errors seem to happen when Genesis is connected to a switch |
3166 | * with no other ports present. Heartbeat error?? | |
3167 | */ | |
baef58b1 SH |
3168 | static void skge_mac_parity(struct skge_hw *hw, int port) |
3169 | { | |
f6620cab SH |
3170 | struct net_device *dev = hw->dev[port]; |
3171 | ||
da00772f | 3172 | ++dev->stats.tx_heartbeat_errors; |
baef58b1 SH |
3173 | |
3174 | if (hw->chip_id == CHIP_ID_GENESIS) | |
6b0c1480 | 3175 | skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), |
baef58b1 SH |
3176 | MFF_CLR_PERR); |
3177 | else | |
3178 | /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */ | |
6b0c1480 | 3179 | skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), |
981d0377 | 3180 | (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) |
baef58b1 SH |
3181 | ? GMF_CLI_TX_FC : GMF_CLI_TX_PE); |
3182 | } | |
3183 | ||
baef58b1 SH |
3184 | static void skge_mac_intr(struct skge_hw *hw, int port) |
3185 | { | |
95566065 | 3186 | if (hw->chip_id == CHIP_ID_GENESIS) |
baef58b1 SH |
3187 | genesis_mac_intr(hw, port); |
3188 | else | |
3189 | yukon_mac_intr(hw, port); | |
3190 | } | |
3191 | ||
3192 | /* Handle device specific framing and timeout interrupts */ | |
3193 | static void skge_error_irq(struct skge_hw *hw) | |
3194 | { | |
1479d13c | 3195 | struct pci_dev *pdev = hw->pdev; |
baef58b1 SH |
3196 | u32 hwstatus = skge_read32(hw, B0_HWE_ISRC); |
3197 | ||
3198 | if (hw->chip_id == CHIP_ID_GENESIS) { | |
3199 | /* clear xmac errors */ | |
3200 | if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1)) | |
46a60f2d | 3201 | skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT); |
baef58b1 | 3202 | if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2)) |
46a60f2d | 3203 | skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT); |
baef58b1 SH |
3204 | } else { |
3205 | /* Timestamp (unused) overflow */ | |
3206 | if (hwstatus & IS_IRQ_TIST_OV) | |
3207 | skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); | |
baef58b1 SH |
3208 | } |
3209 | ||
3210 | if (hwstatus & IS_RAM_RD_PAR) { | |
1479d13c | 3211 | dev_err(&pdev->dev, "Ram read data parity error\n"); |
baef58b1 SH |
3212 | skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR); |
3213 | } | |
3214 | ||
3215 | if (hwstatus & IS_RAM_WR_PAR) { | |
1479d13c | 3216 | dev_err(&pdev->dev, "Ram write data parity error\n"); |
baef58b1 SH |
3217 | skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR); |
3218 | } | |
3219 | ||
3220 | if (hwstatus & IS_M1_PAR_ERR) | |
3221 | skge_mac_parity(hw, 0); | |
3222 | ||
3223 | if (hwstatus & IS_M2_PAR_ERR) | |
3224 | skge_mac_parity(hw, 1); | |
3225 | ||
b9d64acc | 3226 | if (hwstatus & IS_R1_PAR_ERR) { |
1479d13c SH |
3227 | dev_err(&pdev->dev, "%s: receive queue parity error\n", |
3228 | hw->dev[0]->name); | |
baef58b1 | 3229 | skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P); |
b9d64acc | 3230 | } |
baef58b1 | 3231 | |
b9d64acc | 3232 | if (hwstatus & IS_R2_PAR_ERR) { |
1479d13c SH |
3233 | dev_err(&pdev->dev, "%s: receive queue parity error\n", |
3234 | hw->dev[1]->name); | |
baef58b1 | 3235 | skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P); |
b9d64acc | 3236 | } |
baef58b1 SH |
3237 | |
3238 | if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) { | |
b9d64acc SH |
3239 | u16 pci_status, pci_cmd; |
3240 | ||
1479d13c SH |
3241 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); |
3242 | pci_read_config_word(pdev, PCI_STATUS, &pci_status); | |
baef58b1 | 3243 | |
1479d13c SH |
3244 | dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n", |
3245 | pci_cmd, pci_status); | |
b9d64acc SH |
3246 | |
3247 | /* Write the error bits back to clear them. */ | |
3248 | pci_status &= PCI_STATUS_ERROR_BITS; | |
3249 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
1479d13c | 3250 | pci_write_config_word(pdev, PCI_COMMAND, |
b9d64acc | 3251 | pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY); |
1479d13c | 3252 | pci_write_config_word(pdev, PCI_STATUS, pci_status); |
b9d64acc | 3253 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
baef58b1 | 3254 | |
050ec18a | 3255 | /* if error still set then just ignore it */ |
baef58b1 SH |
3256 | hwstatus = skge_read32(hw, B0_HWE_ISRC); |
3257 | if (hwstatus & IS_IRQ_STAT) { | |
1479d13c | 3258 | dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n"); |
baef58b1 SH |
3259 | hw->intr_mask &= ~IS_HW_ERR; |
3260 | } | |
3261 | } | |
3262 | } | |
3263 | ||
3264 | /* | |
9cbe330f | 3265 | * Interrupt from PHY are handled in tasklet (softirq) |
baef58b1 SH |
3266 | * because accessing phy registers requires spin wait which might |
3267 | * cause excess interrupt latency. | |
3268 | */ | |
9cbe330f | 3269 | static void skge_extirq(unsigned long arg) |
baef58b1 | 3270 | { |
9cbe330f | 3271 | struct skge_hw *hw = (struct skge_hw *) arg; |
baef58b1 SH |
3272 | int port; |
3273 | ||
cfc3ed79 | 3274 | for (port = 0; port < hw->ports; port++) { |
baef58b1 SH |
3275 | struct net_device *dev = hw->dev[port]; |
3276 | ||
cfc3ed79 | 3277 | if (netif_running(dev)) { |
9cbe330f SH |
3278 | struct skge_port *skge = netdev_priv(dev); |
3279 | ||
3280 | spin_lock(&hw->phy_lock); | |
baef58b1 SH |
3281 | if (hw->chip_id != CHIP_ID_GENESIS) |
3282 | yukon_phy_intr(skge); | |
64f6b64d | 3283 | else if (hw->phy_type == SK_PHY_BCOM) |
45bada65 | 3284 | bcom_phy_intr(skge); |
9cbe330f | 3285 | spin_unlock(&hw->phy_lock); |
baef58b1 SH |
3286 | } |
3287 | } | |
baef58b1 | 3288 | |
7c442fa1 | 3289 | spin_lock_irq(&hw->hw_lock); |
baef58b1 SH |
3290 | hw->intr_mask |= IS_EXT_REG; |
3291 | skge_write32(hw, B0_IMSK, hw->intr_mask); | |
78bc2186 | 3292 | skge_read32(hw, B0_IMSK); |
7c442fa1 | 3293 | spin_unlock_irq(&hw->hw_lock); |
baef58b1 SH |
3294 | } |
3295 | ||
7d12e780 | 3296 | static irqreturn_t skge_intr(int irq, void *dev_id) |
baef58b1 SH |
3297 | { |
3298 | struct skge_hw *hw = dev_id; | |
cfc3ed79 | 3299 | u32 status; |
29365c90 | 3300 | int handled = 0; |
baef58b1 | 3301 | |
29365c90 | 3302 | spin_lock(&hw->hw_lock); |
cfc3ed79 SH |
3303 | /* Reading this register masks IRQ */ |
3304 | status = skge_read32(hw, B0_SP_ISRC); | |
0486a8c8 | 3305 | if (status == 0 || status == ~0) |
29365c90 | 3306 | goto out; |
baef58b1 | 3307 | |
29365c90 | 3308 | handled = 1; |
7c442fa1 | 3309 | status &= hw->intr_mask; |
cfc3ed79 SH |
3310 | if (status & IS_EXT_REG) { |
3311 | hw->intr_mask &= ~IS_EXT_REG; | |
9cbe330f | 3312 | tasklet_schedule(&hw->phy_task); |
cfc3ed79 SH |
3313 | } |
3314 | ||
513f533e | 3315 | if (status & (IS_XA1_F|IS_R1_F)) { |
bea3348e | 3316 | struct skge_port *skge = netdev_priv(hw->dev[0]); |
513f533e | 3317 | hw->intr_mask &= ~(IS_XA1_F|IS_R1_F); |
288379f0 | 3318 | napi_schedule(&skge->napi); |
baef58b1 SH |
3319 | } |
3320 | ||
7c442fa1 SH |
3321 | if (status & IS_PA_TO_TX1) |
3322 | skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1); | |
cfc3ed79 | 3323 | |
d25f5a67 | 3324 | if (status & IS_PA_TO_RX1) { |
da00772f | 3325 | ++hw->dev[0]->stats.rx_over_errors; |
7c442fa1 | 3326 | skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1); |
d25f5a67 SH |
3327 | } |
3328 | ||
d25f5a67 | 3329 | |
baef58b1 SH |
3330 | if (status & IS_MAC1) |
3331 | skge_mac_intr(hw, 0); | |
95566065 | 3332 | |
7c442fa1 | 3333 | if (hw->dev[1]) { |
bea3348e SH |
3334 | struct skge_port *skge = netdev_priv(hw->dev[1]); |
3335 | ||
513f533e SH |
3336 | if (status & (IS_XA2_F|IS_R2_F)) { |
3337 | hw->intr_mask &= ~(IS_XA2_F|IS_R2_F); | |
288379f0 | 3338 | napi_schedule(&skge->napi); |
7c442fa1 SH |
3339 | } |
3340 | ||
3341 | if (status & IS_PA_TO_RX2) { | |
da00772f | 3342 | ++hw->dev[1]->stats.rx_over_errors; |
7c442fa1 SH |
3343 | skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2); |
3344 | } | |
3345 | ||
3346 | if (status & IS_PA_TO_TX2) | |
3347 | skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2); | |
3348 | ||
3349 | if (status & IS_MAC2) | |
3350 | skge_mac_intr(hw, 1); | |
3351 | } | |
baef58b1 SH |
3352 | |
3353 | if (status & IS_HW_ERR) | |
3354 | skge_error_irq(hw); | |
3355 | ||
7e676d91 | 3356 | skge_write32(hw, B0_IMSK, hw->intr_mask); |
78bc2186 | 3357 | skge_read32(hw, B0_IMSK); |
29365c90 | 3358 | out: |
7c442fa1 | 3359 | spin_unlock(&hw->hw_lock); |
baef58b1 | 3360 | |
29365c90 | 3361 | return IRQ_RETVAL(handled); |
baef58b1 SH |
3362 | } |
3363 | ||
3364 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3365 | static void skge_netpoll(struct net_device *dev) | |
3366 | { | |
3367 | struct skge_port *skge = netdev_priv(dev); | |
3368 | ||
3369 | disable_irq(dev->irq); | |
7d12e780 | 3370 | skge_intr(dev->irq, skge->hw); |
baef58b1 SH |
3371 | enable_irq(dev->irq); |
3372 | } | |
3373 | #endif | |
3374 | ||
3375 | static int skge_set_mac_address(struct net_device *dev, void *p) | |
3376 | { | |
3377 | struct skge_port *skge = netdev_priv(dev); | |
c2681dd8 SH |
3378 | struct skge_hw *hw = skge->hw; |
3379 | unsigned port = skge->port; | |
3380 | const struct sockaddr *addr = p; | |
2eb3e621 | 3381 | u16 ctrl; |
baef58b1 SH |
3382 | |
3383 | if (!is_valid_ether_addr(addr->sa_data)) | |
3384 | return -EADDRNOTAVAIL; | |
3385 | ||
baef58b1 | 3386 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); |
c2681dd8 | 3387 | |
9cbe330f SH |
3388 | if (!netif_running(dev)) { |
3389 | memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN); | |
3390 | memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN); | |
3391 | } else { | |
3392 | /* disable Rx */ | |
3393 | spin_lock_bh(&hw->phy_lock); | |
3394 | ctrl = gma_read16(hw, port, GM_GP_CTRL); | |
3395 | gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA); | |
2eb3e621 | 3396 | |
9cbe330f SH |
3397 | memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN); |
3398 | memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN); | |
2eb3e621 | 3399 | |
2eb3e621 SH |
3400 | if (hw->chip_id == CHIP_ID_GENESIS) |
3401 | xm_outaddr(hw, port, XM_SA, dev->dev_addr); | |
3402 | else { | |
3403 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); | |
3404 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); | |
3405 | } | |
2eb3e621 | 3406 | |
9cbe330f SH |
3407 | gma_write16(hw, port, GM_GP_CTRL, ctrl); |
3408 | spin_unlock_bh(&hw->phy_lock); | |
3409 | } | |
c2681dd8 SH |
3410 | |
3411 | return 0; | |
baef58b1 SH |
3412 | } |
3413 | ||
3414 | static const struct { | |
3415 | u8 id; | |
3416 | const char *name; | |
3417 | } skge_chips[] = { | |
3418 | { CHIP_ID_GENESIS, "Genesis" }, | |
3419 | { CHIP_ID_YUKON, "Yukon" }, | |
3420 | { CHIP_ID_YUKON_LITE, "Yukon-Lite"}, | |
3421 | { CHIP_ID_YUKON_LP, "Yukon-LP"}, | |
baef58b1 SH |
3422 | }; |
3423 | ||
3424 | static const char *skge_board_name(const struct skge_hw *hw) | |
3425 | { | |
3426 | int i; | |
3427 | static char buf[16]; | |
3428 | ||
3429 | for (i = 0; i < ARRAY_SIZE(skge_chips); i++) | |
3430 | if (skge_chips[i].id == hw->chip_id) | |
3431 | return skge_chips[i].name; | |
3432 | ||
3433 | snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id); | |
3434 | return buf; | |
3435 | } | |
3436 | ||
3437 | ||
3438 | /* | |
3439 | * Setup the board data structure, but don't bring up | |
3440 | * the port(s) | |
3441 | */ | |
3442 | static int skge_reset(struct skge_hw *hw) | |
3443 | { | |
adba9e23 | 3444 | u32 reg; |
b9d64acc | 3445 | u16 ctst, pci_status; |
64f6b64d | 3446 | u8 t8, mac_cfg, pmd_type; |
981d0377 | 3447 | int i; |
baef58b1 SH |
3448 | |
3449 | ctst = skge_read16(hw, B0_CTST); | |
3450 | ||
3451 | /* do a SW reset */ | |
3452 | skge_write8(hw, B0_CTST, CS_RST_SET); | |
3453 | skge_write8(hw, B0_CTST, CS_RST_CLR); | |
3454 | ||
3455 | /* clear PCI errors, if any */ | |
b9d64acc SH |
3456 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
3457 | skge_write8(hw, B2_TST_CTRL2, 0); | |
baef58b1 | 3458 | |
b9d64acc SH |
3459 | pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status); |
3460 | pci_write_config_word(hw->pdev, PCI_STATUS, | |
3461 | pci_status | PCI_STATUS_ERROR_BITS); | |
3462 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
baef58b1 SH |
3463 | skge_write8(hw, B0_CTST, CS_MRST_CLR); |
3464 | ||
3465 | /* restore CLK_RUN bits (for Yukon-Lite) */ | |
3466 | skge_write16(hw, B0_CTST, | |
3467 | ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA)); | |
3468 | ||
3469 | hw->chip_id = skge_read8(hw, B2_CHIP_ID); | |
64f6b64d | 3470 | hw->phy_type = skge_read8(hw, B2_E_1) & 0xf; |
5e1705dd SH |
3471 | pmd_type = skge_read8(hw, B2_PMD_TYP); |
3472 | hw->copper = (pmd_type == 'T' || pmd_type == '1'); | |
baef58b1 | 3473 | |
95566065 | 3474 | switch (hw->chip_id) { |
baef58b1 | 3475 | case CHIP_ID_GENESIS: |
64f6b64d SH |
3476 | switch (hw->phy_type) { |
3477 | case SK_PHY_XMAC: | |
3478 | hw->phy_addr = PHY_ADDR_XMAC; | |
3479 | break; | |
baef58b1 SH |
3480 | case SK_PHY_BCOM: |
3481 | hw->phy_addr = PHY_ADDR_BCOM; | |
3482 | break; | |
3483 | default: | |
1479d13c SH |
3484 | dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n", |
3485 | hw->phy_type); | |
baef58b1 SH |
3486 | return -EOPNOTSUPP; |
3487 | } | |
3488 | break; | |
3489 | ||
3490 | case CHIP_ID_YUKON: | |
3491 | case CHIP_ID_YUKON_LITE: | |
3492 | case CHIP_ID_YUKON_LP: | |
64f6b64d | 3493 | if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S') |
5e1705dd | 3494 | hw->copper = 1; |
baef58b1 SH |
3495 | |
3496 | hw->phy_addr = PHY_ADDR_MARV; | |
baef58b1 SH |
3497 | break; |
3498 | ||
3499 | default: | |
1479d13c SH |
3500 | dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", |
3501 | hw->chip_id); | |
baef58b1 SH |
3502 | return -EOPNOTSUPP; |
3503 | } | |
3504 | ||
981d0377 SH |
3505 | mac_cfg = skge_read8(hw, B2_MAC_CFG); |
3506 | hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2; | |
3507 | hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4; | |
baef58b1 SH |
3508 | |
3509 | /* read the adapters RAM size */ | |
3510 | t8 = skge_read8(hw, B2_E_0); | |
3511 | if (hw->chip_id == CHIP_ID_GENESIS) { | |
3512 | if (t8 == 3) { | |
3513 | /* special case: 4 x 64k x 36, offset = 0x80000 */ | |
279e1dab LT |
3514 | hw->ram_size = 0x100000; |
3515 | hw->ram_offset = 0x80000; | |
baef58b1 SH |
3516 | } else |
3517 | hw->ram_size = t8 * 512; | |
67777f9b | 3518 | } else if (t8 == 0) |
279e1dab LT |
3519 | hw->ram_size = 0x20000; |
3520 | else | |
3521 | hw->ram_size = t8 * 4096; | |
baef58b1 | 3522 | |
4ebabfcb | 3523 | hw->intr_mask = IS_HW_ERR; |
cfc3ed79 | 3524 | |
4ebabfcb | 3525 | /* Use PHY IRQ for all but fiber based Genesis board */ |
64f6b64d SH |
3526 | if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)) |
3527 | hw->intr_mask |= IS_EXT_REG; | |
3528 | ||
baef58b1 SH |
3529 | if (hw->chip_id == CHIP_ID_GENESIS) |
3530 | genesis_init(hw); | |
3531 | else { | |
3532 | /* switch power to VCC (WA for VAUX problem) */ | |
3533 | skge_write8(hw, B0_POWER_CTRL, | |
3534 | PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); | |
adba9e23 | 3535 | |
050ec18a SH |
3536 | /* avoid boards with stuck Hardware error bits */ |
3537 | if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) && | |
3538 | (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) { | |
1479d13c | 3539 | dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n"); |
050ec18a SH |
3540 | hw->intr_mask &= ~IS_HW_ERR; |
3541 | } | |
3542 | ||
adba9e23 SH |
3543 | /* Clear PHY COMA */ |
3544 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
3545 | pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®); | |
3546 | reg &= ~PCI_PHY_COMA; | |
3547 | pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg); | |
3548 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
3549 | ||
3550 | ||
981d0377 | 3551 | for (i = 0; i < hw->ports; i++) { |
6b0c1480 SH |
3552 | skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); |
3553 | skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
baef58b1 SH |
3554 | } |
3555 | } | |
3556 | ||
3557 | /* turn off hardware timer (unused) */ | |
3558 | skge_write8(hw, B2_TI_CTRL, TIM_STOP); | |
3559 | skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); | |
3560 | skge_write8(hw, B0_LED, LED_STAT_ON); | |
3561 | ||
3562 | /* enable the Tx Arbiters */ | |
981d0377 | 3563 | for (i = 0; i < hw->ports; i++) |
6b0c1480 | 3564 | skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); |
baef58b1 SH |
3565 | |
3566 | /* Initialize ram interface */ | |
3567 | skge_write16(hw, B3_RI_CTRL, RI_RST_CLR); | |
3568 | ||
3569 | skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53); | |
3570 | skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53); | |
3571 | skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53); | |
3572 | skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53); | |
3573 | skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53); | |
3574 | skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53); | |
3575 | skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53); | |
3576 | skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53); | |
3577 | skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53); | |
3578 | skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53); | |
3579 | skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53); | |
3580 | skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53); | |
3581 | ||
3582 | skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK); | |
3583 | ||
3584 | /* Set interrupt moderation for Transmit only | |
3585 | * Receive interrupts avoided by NAPI | |
3586 | */ | |
3587 | skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F); | |
3588 | skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100)); | |
3589 | skge_write32(hw, B2_IRQM_CTRL, TIM_START); | |
3590 | ||
baef58b1 SH |
3591 | skge_write32(hw, B0_IMSK, hw->intr_mask); |
3592 | ||
981d0377 | 3593 | for (i = 0; i < hw->ports; i++) { |
baef58b1 SH |
3594 | if (hw->chip_id == CHIP_ID_GENESIS) |
3595 | genesis_reset(hw, i); | |
3596 | else | |
3597 | yukon_reset(hw, i); | |
3598 | } | |
baef58b1 SH |
3599 | |
3600 | return 0; | |
3601 | } | |
3602 | ||
678aa1f6 SH |
3603 | |
3604 | #ifdef CONFIG_SKGE_DEBUG | |
3605 | ||
3606 | static struct dentry *skge_debug; | |
3607 | ||
3608 | static int skge_debug_show(struct seq_file *seq, void *v) | |
3609 | { | |
3610 | struct net_device *dev = seq->private; | |
3611 | const struct skge_port *skge = netdev_priv(dev); | |
3612 | const struct skge_hw *hw = skge->hw; | |
3613 | const struct skge_element *e; | |
3614 | ||
3615 | if (!netif_running(dev)) | |
3616 | return -ENETDOWN; | |
3617 | ||
3618 | seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC), | |
3619 | skge_read32(hw, B0_IMSK)); | |
3620 | ||
3621 | seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring)); | |
3622 | for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) { | |
3623 | const struct skge_tx_desc *t = e->desc; | |
3624 | seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n", | |
3625 | t->control, t->dma_hi, t->dma_lo, t->status, | |
3626 | t->csum_offs, t->csum_write, t->csum_start); | |
3627 | } | |
3628 | ||
2381a55c | 3629 | seq_printf(seq, "\nRx Ring:\n"); |
678aa1f6 SH |
3630 | for (e = skge->rx_ring.to_clean; ; e = e->next) { |
3631 | const struct skge_rx_desc *r = e->desc; | |
3632 | ||
3633 | if (r->control & BMU_OWN) | |
3634 | break; | |
3635 | ||
3636 | seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n", | |
3637 | r->control, r->dma_hi, r->dma_lo, r->status, | |
3638 | r->timestamp, r->csum1, r->csum1_start); | |
3639 | } | |
3640 | ||
3641 | return 0; | |
3642 | } | |
3643 | ||
3644 | static int skge_debug_open(struct inode *inode, struct file *file) | |
3645 | { | |
3646 | return single_open(file, skge_debug_show, inode->i_private); | |
3647 | } | |
3648 | ||
3649 | static const struct file_operations skge_debug_fops = { | |
3650 | .owner = THIS_MODULE, | |
3651 | .open = skge_debug_open, | |
3652 | .read = seq_read, | |
3653 | .llseek = seq_lseek, | |
3654 | .release = single_release, | |
3655 | }; | |
3656 | ||
3657 | /* | |
3658 | * Use network device events to create/remove/rename | |
3659 | * debugfs file entries | |
3660 | */ | |
3661 | static int skge_device_event(struct notifier_block *unused, | |
3662 | unsigned long event, void *ptr) | |
3663 | { | |
3664 | struct net_device *dev = ptr; | |
3665 | struct skge_port *skge; | |
3666 | struct dentry *d; | |
3667 | ||
f80d032b | 3668 | if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug) |
678aa1f6 SH |
3669 | goto done; |
3670 | ||
3671 | skge = netdev_priv(dev); | |
67777f9b | 3672 | switch (event) { |
678aa1f6 SH |
3673 | case NETDEV_CHANGENAME: |
3674 | if (skge->debugfs) { | |
3675 | d = debugfs_rename(skge_debug, skge->debugfs, | |
3676 | skge_debug, dev->name); | |
3677 | if (d) | |
3678 | skge->debugfs = d; | |
3679 | else { | |
f15063cd | 3680 | netdev_info(dev, "rename failed\n"); |
678aa1f6 SH |
3681 | debugfs_remove(skge->debugfs); |
3682 | } | |
3683 | } | |
3684 | break; | |
3685 | ||
3686 | case NETDEV_GOING_DOWN: | |
3687 | if (skge->debugfs) { | |
3688 | debugfs_remove(skge->debugfs); | |
3689 | skge->debugfs = NULL; | |
3690 | } | |
3691 | break; | |
3692 | ||
3693 | case NETDEV_UP: | |
3694 | d = debugfs_create_file(dev->name, S_IRUGO, | |
3695 | skge_debug, dev, | |
3696 | &skge_debug_fops); | |
3697 | if (!d || IS_ERR(d)) | |
f15063cd | 3698 | netdev_info(dev, "debugfs create failed\n"); |
678aa1f6 SH |
3699 | else |
3700 | skge->debugfs = d; | |
3701 | break; | |
3702 | } | |
3703 | ||
3704 | done: | |
3705 | return NOTIFY_DONE; | |
3706 | } | |
3707 | ||
3708 | static struct notifier_block skge_notifier = { | |
3709 | .notifier_call = skge_device_event, | |
3710 | }; | |
3711 | ||
3712 | ||
3713 | static __init void skge_debug_init(void) | |
3714 | { | |
3715 | struct dentry *ent; | |
3716 | ||
3717 | ent = debugfs_create_dir("skge", NULL); | |
3718 | if (!ent || IS_ERR(ent)) { | |
f15063cd | 3719 | pr_info("debugfs create directory failed\n"); |
678aa1f6 SH |
3720 | return; |
3721 | } | |
3722 | ||
3723 | skge_debug = ent; | |
3724 | register_netdevice_notifier(&skge_notifier); | |
3725 | } | |
3726 | ||
3727 | static __exit void skge_debug_cleanup(void) | |
3728 | { | |
3729 | if (skge_debug) { | |
3730 | unregister_netdevice_notifier(&skge_notifier); | |
3731 | debugfs_remove(skge_debug); | |
3732 | skge_debug = NULL; | |
3733 | } | |
3734 | } | |
3735 | ||
3736 | #else | |
3737 | #define skge_debug_init() | |
3738 | #define skge_debug_cleanup() | |
3739 | #endif | |
3740 | ||
f80d032b SH |
3741 | static const struct net_device_ops skge_netdev_ops = { |
3742 | .ndo_open = skge_up, | |
3743 | .ndo_stop = skge_down, | |
00829823 | 3744 | .ndo_start_xmit = skge_xmit_frame, |
f80d032b SH |
3745 | .ndo_do_ioctl = skge_ioctl, |
3746 | .ndo_get_stats = skge_get_stats, | |
3747 | .ndo_tx_timeout = skge_tx_timeout, | |
3748 | .ndo_change_mtu = skge_change_mtu, | |
3749 | .ndo_validate_addr = eth_validate_addr, | |
3750 | .ndo_set_multicast_list = skge_set_multicast, | |
3751 | .ndo_set_mac_address = skge_set_mac_address, | |
3752 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3753 | .ndo_poll_controller = skge_netpoll, | |
3754 | #endif | |
3755 | }; | |
3756 | ||
3757 | ||
baef58b1 | 3758 | /* Initialize network device */ |
981d0377 SH |
3759 | static struct net_device *skge_devinit(struct skge_hw *hw, int port, |
3760 | int highmem) | |
baef58b1 SH |
3761 | { |
3762 | struct skge_port *skge; | |
3763 | struct net_device *dev = alloc_etherdev(sizeof(*skge)); | |
3764 | ||
3765 | if (!dev) { | |
1479d13c | 3766 | dev_err(&hw->pdev->dev, "etherdev alloc failed\n"); |
baef58b1 SH |
3767 | return NULL; |
3768 | } | |
3769 | ||
baef58b1 | 3770 | SET_NETDEV_DEV(dev, &hw->pdev->dev); |
f80d032b SH |
3771 | dev->netdev_ops = &skge_netdev_ops; |
3772 | dev->ethtool_ops = &skge_ethtool_ops; | |
baef58b1 | 3773 | dev->watchdog_timeo = TX_WATCHDOG; |
baef58b1 | 3774 | dev->irq = hw->pdev->irq; |
513f533e | 3775 | |
981d0377 SH |
3776 | if (highmem) |
3777 | dev->features |= NETIF_F_HIGHDMA; | |
baef58b1 SH |
3778 | |
3779 | skge = netdev_priv(dev); | |
bea3348e | 3780 | netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT); |
baef58b1 SH |
3781 | skge->netdev = dev; |
3782 | skge->hw = hw; | |
3783 | skge->msg_enable = netif_msg_init(debug, default_msg); | |
9cbe330f | 3784 | |
baef58b1 SH |
3785 | skge->tx_ring.count = DEFAULT_TX_RING_SIZE; |
3786 | skge->rx_ring.count = DEFAULT_RX_RING_SIZE; | |
3787 | ||
3788 | /* Auto speed and flow control */ | |
3789 | skge->autoneg = AUTONEG_ENABLE; | |
5d5c8e03 | 3790 | skge->flow_control = FLOW_MODE_SYM_OR_REM; |
baef58b1 SH |
3791 | skge->duplex = -1; |
3792 | skge->speed = -1; | |
31b619c5 | 3793 | skge->advertising = skge_supported_modes(hw); |
5b982c5b | 3794 | |
7b55a4a3 | 3795 | if (device_can_wakeup(&hw->pdev->dev)) { |
5b982c5b | 3796 | skge->wol = wol_supported(hw) & WAKE_MAGIC; |
7b55a4a3 RW |
3797 | device_set_wakeup_enable(&hw->pdev->dev, skge->wol); |
3798 | } | |
baef58b1 SH |
3799 | |
3800 | hw->dev[port] = dev; | |
3801 | ||
3802 | skge->port = port; | |
3803 | ||
64f6b64d | 3804 | /* Only used for Genesis XMAC */ |
9cbe330f | 3805 | setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge); |
64f6b64d | 3806 | |
baef58b1 | 3807 | if (hw->chip_id != CHIP_ID_GENESIS) { |
e92702b1 MM |
3808 | dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | |
3809 | NETIF_F_RXCSUM; | |
3810 | dev->features |= dev->hw_features; | |
baef58b1 SH |
3811 | } |
3812 | ||
3813 | /* read the mac address */ | |
3814 | memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN); | |
56230d53 | 3815 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
baef58b1 | 3816 | |
baef58b1 SH |
3817 | return dev; |
3818 | } | |
3819 | ||
3820 | static void __devinit skge_show_addr(struct net_device *dev) | |
3821 | { | |
3822 | const struct skge_port *skge = netdev_priv(dev); | |
3823 | ||
d707204c | 3824 | netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr); |
baef58b1 SH |
3825 | } |
3826 | ||
392bd0cb SG |
3827 | static int only_32bit_dma; |
3828 | ||
baef58b1 SH |
3829 | static int __devinit skge_probe(struct pci_dev *pdev, |
3830 | const struct pci_device_id *ent) | |
3831 | { | |
3832 | struct net_device *dev, *dev1; | |
3833 | struct skge_hw *hw; | |
3834 | int err, using_dac = 0; | |
3835 | ||
203babb6 SH |
3836 | err = pci_enable_device(pdev); |
3837 | if (err) { | |
1479d13c | 3838 | dev_err(&pdev->dev, "cannot enable PCI device\n"); |
baef58b1 SH |
3839 | goto err_out; |
3840 | } | |
3841 | ||
203babb6 SH |
3842 | err = pci_request_regions(pdev, DRV_NAME); |
3843 | if (err) { | |
1479d13c | 3844 | dev_err(&pdev->dev, "cannot obtain PCI resources\n"); |
baef58b1 SH |
3845 | goto err_out_disable_pdev; |
3846 | } | |
3847 | ||
3848 | pci_set_master(pdev); | |
3849 | ||
392bd0cb | 3850 | if (!only_32bit_dma && !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { |
baef58b1 | 3851 | using_dac = 1; |
6a35528a | 3852 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
284901a9 | 3853 | } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) { |
93aea718 | 3854 | using_dac = 0; |
284901a9 | 3855 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
93aea718 SH |
3856 | } |
3857 | ||
3858 | if (err) { | |
1479d13c | 3859 | dev_err(&pdev->dev, "no usable DMA configuration\n"); |
93aea718 | 3860 | goto err_out_free_regions; |
baef58b1 SH |
3861 | } |
3862 | ||
3863 | #ifdef __BIG_ENDIAN | |
8f3f8193 | 3864 | /* byte swap descriptors in hardware */ |
baef58b1 SH |
3865 | { |
3866 | u32 reg; | |
3867 | ||
3868 | pci_read_config_dword(pdev, PCI_DEV_REG2, ®); | |
3869 | reg |= PCI_REV_DESC; | |
3870 | pci_write_config_dword(pdev, PCI_DEV_REG2, reg); | |
3871 | } | |
3872 | #endif | |
3873 | ||
3874 | err = -ENOMEM; | |
415e69e6 | 3875 | /* space for skge@pci:0000:04:00.0 */ |
67777f9b | 3876 | hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:") |
415e69e6 | 3877 | + strlen(pci_name(pdev)) + 1, GFP_KERNEL); |
baef58b1 | 3878 | if (!hw) { |
1479d13c | 3879 | dev_err(&pdev->dev, "cannot allocate hardware struct\n"); |
baef58b1 SH |
3880 | goto err_out_free_regions; |
3881 | } | |
415e69e6 | 3882 | sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); |
baef58b1 | 3883 | |
baef58b1 | 3884 | hw->pdev = pdev; |
d38efdd6 | 3885 | spin_lock_init(&hw->hw_lock); |
9cbe330f | 3886 | spin_lock_init(&hw->phy_lock); |
164165da | 3887 | tasklet_init(&hw->phy_task, skge_extirq, (unsigned long) hw); |
baef58b1 SH |
3888 | |
3889 | hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); | |
3890 | if (!hw->regs) { | |
1479d13c | 3891 | dev_err(&pdev->dev, "cannot map device registers\n"); |
baef58b1 SH |
3892 | goto err_out_free_hw; |
3893 | } | |
3894 | ||
baef58b1 SH |
3895 | err = skge_reset(hw); |
3896 | if (err) | |
ccdaa2a9 | 3897 | goto err_out_iounmap; |
baef58b1 | 3898 | |
f15063cd JP |
3899 | pr_info("%s addr 0x%llx irq %d chip %s rev %d\n", |
3900 | DRV_VERSION, | |
3901 | (unsigned long long)pci_resource_start(pdev, 0), pdev->irq, | |
3902 | skge_board_name(hw), hw->chip_rev); | |
baef58b1 | 3903 | |
ccdaa2a9 SH |
3904 | dev = skge_devinit(hw, 0, using_dac); |
3905 | if (!dev) | |
baef58b1 SH |
3906 | goto err_out_led_off; |
3907 | ||
fae87592 | 3908 | /* Some motherboards are broken and has zero in ROM. */ |
1479d13c SH |
3909 | if (!is_valid_ether_addr(dev->dev_addr)) |
3910 | dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n"); | |
631ae320 | 3911 | |
203babb6 SH |
3912 | err = register_netdev(dev); |
3913 | if (err) { | |
1479d13c | 3914 | dev_err(&pdev->dev, "cannot register net device\n"); |
baef58b1 SH |
3915 | goto err_out_free_netdev; |
3916 | } | |
3917 | ||
415e69e6 | 3918 | err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, hw->irq_name, hw); |
ccdaa2a9 | 3919 | if (err) { |
1479d13c | 3920 | dev_err(&pdev->dev, "%s: cannot assign irq %d\n", |
ccdaa2a9 SH |
3921 | dev->name, pdev->irq); |
3922 | goto err_out_unregister; | |
3923 | } | |
baef58b1 SH |
3924 | skge_show_addr(dev); |
3925 | ||
f1914226 MM |
3926 | if (hw->ports > 1) { |
3927 | dev1 = skge_devinit(hw, 1, using_dac); | |
3928 | if (dev1 && register_netdev(dev1) == 0) | |
baef58b1 SH |
3929 | skge_show_addr(dev1); |
3930 | else { | |
3931 | /* Failure to register second port need not be fatal */ | |
1479d13c | 3932 | dev_warn(&pdev->dev, "register of second port failed\n"); |
baef58b1 | 3933 | hw->dev[1] = NULL; |
f1914226 MM |
3934 | hw->ports = 1; |
3935 | if (dev1) | |
3936 | free_netdev(dev1); | |
baef58b1 SH |
3937 | } |
3938 | } | |
ccdaa2a9 | 3939 | pci_set_drvdata(pdev, hw); |
baef58b1 SH |
3940 | |
3941 | return 0; | |
3942 | ||
ccdaa2a9 SH |
3943 | err_out_unregister: |
3944 | unregister_netdev(dev); | |
baef58b1 SH |
3945 | err_out_free_netdev: |
3946 | free_netdev(dev); | |
3947 | err_out_led_off: | |
3948 | skge_write16(hw, B0_LED, LED_STAT_OFF); | |
baef58b1 SH |
3949 | err_out_iounmap: |
3950 | iounmap(hw->regs); | |
3951 | err_out_free_hw: | |
3952 | kfree(hw); | |
3953 | err_out_free_regions: | |
3954 | pci_release_regions(pdev); | |
3955 | err_out_disable_pdev: | |
3956 | pci_disable_device(pdev); | |
3957 | pci_set_drvdata(pdev, NULL); | |
3958 | err_out: | |
3959 | return err; | |
3960 | } | |
3961 | ||
3962 | static void __devexit skge_remove(struct pci_dev *pdev) | |
3963 | { | |
3964 | struct skge_hw *hw = pci_get_drvdata(pdev); | |
3965 | struct net_device *dev0, *dev1; | |
3966 | ||
95566065 | 3967 | if (!hw) |
baef58b1 SH |
3968 | return; |
3969 | ||
67777f9b JP |
3970 | dev1 = hw->dev[1]; |
3971 | if (dev1) | |
baef58b1 SH |
3972 | unregister_netdev(dev1); |
3973 | dev0 = hw->dev[0]; | |
3974 | unregister_netdev(dev0); | |
3975 | ||
9cbe330f SH |
3976 | tasklet_disable(&hw->phy_task); |
3977 | ||
7c442fa1 SH |
3978 | spin_lock_irq(&hw->hw_lock); |
3979 | hw->intr_mask = 0; | |
46a60f2d | 3980 | skge_write32(hw, B0_IMSK, 0); |
78bc2186 | 3981 | skge_read32(hw, B0_IMSK); |
7c442fa1 SH |
3982 | spin_unlock_irq(&hw->hw_lock); |
3983 | ||
46a60f2d | 3984 | skge_write16(hw, B0_LED, LED_STAT_OFF); |
46a60f2d SH |
3985 | skge_write8(hw, B0_CTST, CS_RST_SET); |
3986 | ||
baef58b1 SH |
3987 | free_irq(pdev->irq, hw); |
3988 | pci_release_regions(pdev); | |
3989 | pci_disable_device(pdev); | |
3990 | if (dev1) | |
3991 | free_netdev(dev1); | |
3992 | free_netdev(dev0); | |
46a60f2d | 3993 | |
baef58b1 SH |
3994 | iounmap(hw->regs); |
3995 | kfree(hw); | |
3996 | pci_set_drvdata(pdev, NULL); | |
3997 | } | |
3998 | ||
3999 | #ifdef CONFIG_PM | |
7dbf6acd | 4000 | static int skge_suspend(struct device *dev) |
baef58b1 | 4001 | { |
7dbf6acd | 4002 | struct pci_dev *pdev = to_pci_dev(dev); |
baef58b1 | 4003 | struct skge_hw *hw = pci_get_drvdata(pdev); |
7dbf6acd | 4004 | int i; |
a504e64a | 4005 | |
e3b7df17 SH |
4006 | if (!hw) |
4007 | return 0; | |
4008 | ||
d38efdd6 | 4009 | for (i = 0; i < hw->ports; i++) { |
baef58b1 | 4010 | struct net_device *dev = hw->dev[i]; |
a504e64a | 4011 | struct skge_port *skge = netdev_priv(dev); |
baef58b1 | 4012 | |
a504e64a SH |
4013 | if (netif_running(dev)) |
4014 | skge_down(dev); | |
7dbf6acd | 4015 | |
a504e64a SH |
4016 | if (skge->wol) |
4017 | skge_wol_init(skge); | |
baef58b1 SH |
4018 | } |
4019 | ||
d38efdd6 | 4020 | skge_write32(hw, B0_IMSK, 0); |
5177b324 | 4021 | |
baef58b1 SH |
4022 | return 0; |
4023 | } | |
4024 | ||
7dbf6acd | 4025 | static int skge_resume(struct device *dev) |
baef58b1 | 4026 | { |
7dbf6acd | 4027 | struct pci_dev *pdev = to_pci_dev(dev); |
baef58b1 | 4028 | struct skge_hw *hw = pci_get_drvdata(pdev); |
d38efdd6 | 4029 | int i, err; |
baef58b1 | 4030 | |
e3b7df17 SH |
4031 | if (!hw) |
4032 | return 0; | |
4033 | ||
d38efdd6 SH |
4034 | err = skge_reset(hw); |
4035 | if (err) | |
4036 | goto out; | |
baef58b1 | 4037 | |
d38efdd6 | 4038 | for (i = 0; i < hw->ports; i++) { |
baef58b1 | 4039 | struct net_device *dev = hw->dev[i]; |
d38efdd6 | 4040 | |
d38efdd6 SH |
4041 | if (netif_running(dev)) { |
4042 | err = skge_up(dev); | |
4043 | ||
4044 | if (err) { | |
f15063cd | 4045 | netdev_err(dev, "could not up: %d\n", err); |
edd702e8 | 4046 | dev_close(dev); |
d38efdd6 SH |
4047 | goto out; |
4048 | } | |
baef58b1 SH |
4049 | } |
4050 | } | |
d38efdd6 SH |
4051 | out: |
4052 | return err; | |
baef58b1 | 4053 | } |
7dbf6acd | 4054 | |
4055 | static SIMPLE_DEV_PM_OPS(skge_pm_ops, skge_suspend, skge_resume); | |
4056 | #define SKGE_PM_OPS (&skge_pm_ops) | |
4057 | ||
4058 | #else | |
4059 | ||
4060 | #define SKGE_PM_OPS NULL | |
baef58b1 SH |
4061 | #endif |
4062 | ||
692412b3 SH |
4063 | static void skge_shutdown(struct pci_dev *pdev) |
4064 | { | |
4065 | struct skge_hw *hw = pci_get_drvdata(pdev); | |
7dbf6acd | 4066 | int i; |
692412b3 | 4067 | |
e3b7df17 SH |
4068 | if (!hw) |
4069 | return; | |
4070 | ||
692412b3 SH |
4071 | for (i = 0; i < hw->ports; i++) { |
4072 | struct net_device *dev = hw->dev[i]; | |
4073 | struct skge_port *skge = netdev_priv(dev); | |
4074 | ||
4075 | if (skge->wol) | |
4076 | skge_wol_init(skge); | |
692412b3 SH |
4077 | } |
4078 | ||
7dbf6acd | 4079 | pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev)); |
692412b3 | 4080 | pci_set_power_state(pdev, PCI_D3hot); |
692412b3 SH |
4081 | } |
4082 | ||
baef58b1 SH |
4083 | static struct pci_driver skge_driver = { |
4084 | .name = DRV_NAME, | |
4085 | .id_table = skge_id_table, | |
4086 | .probe = skge_probe, | |
4087 | .remove = __devexit_p(skge_remove), | |
692412b3 | 4088 | .shutdown = skge_shutdown, |
7dbf6acd | 4089 | .driver.pm = SKGE_PM_OPS, |
baef58b1 SH |
4090 | }; |
4091 | ||
392bd0cb SG |
4092 | static struct dmi_system_id skge_32bit_dma_boards[] = { |
4093 | { | |
4094 | .ident = "Gigabyte nForce boards", | |
4095 | .matches = { | |
4096 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co"), | |
4097 | DMI_MATCH(DMI_BOARD_NAME, "nForce"), | |
4098 | }, | |
4099 | }, | |
4100 | {} | |
4101 | }; | |
4102 | ||
baef58b1 SH |
4103 | static int __init skge_init_module(void) |
4104 | { | |
392bd0cb SG |
4105 | if (dmi_check_system(skge_32bit_dma_boards)) |
4106 | only_32bit_dma = 1; | |
678aa1f6 | 4107 | skge_debug_init(); |
29917620 | 4108 | return pci_register_driver(&skge_driver); |
baef58b1 SH |
4109 | } |
4110 | ||
4111 | static void __exit skge_cleanup_module(void) | |
4112 | { | |
4113 | pci_unregister_driver(&skge_driver); | |
678aa1f6 | 4114 | skge_debug_cleanup(); |
baef58b1 SH |
4115 | } |
4116 | ||
4117 | module_init(skge_init_module); | |
4118 | module_exit(skge_cleanup_module); |