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skge: eeprom support
[deliverable/linux.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
798b6b19 14 * the Free Software Foundation; either version 2 of the License.
baef58b1
SH		 15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
14c85021 26#include <linux/in.h>
baef58b1
SH		 27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/if_vlan.h>
35#include <linux/ip.h>
36#include <linux/delay.h>
37#include <linux/crc32.h>
4075400b 38#include <linux/dma-mapping.h>
2cd8e5d3 39#include <linux/mii.h>
baef58b1
SH		 40#include <asm/irq.h>
41
42#include "skge.h"
43
44#define DRV_NAME "skge"
a5f8f3b6 45#define DRV_VERSION "1.11"
baef58b1
SH		 46#define PFX DRV_NAME " "
47
48#define DEFAULT_TX_RING_SIZE 128
49#define DEFAULT_RX_RING_SIZE 512
50#define MAX_TX_RING_SIZE 1024
9db96479 51#define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
baef58b1 52#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 53#define RX_COPY_THRESHOLD 128
54#define RX_BUF_SIZE 1536
baef58b1
SH		 55#define PHY_RETRIES 1000
56#define ETH_JUMBO_MTU 9000
57#define TX_WATCHDOG (5 * HZ)
58#define NAPI_WEIGHT 64
6abebb53 59#define BLINK_MS 250
501fb72d 60#define LINK_HZ HZ
baef58b1 61
afa151b9
SH		 62#define SKGE_EEPROM_MAGIC 0x9933aabb
63
64
baef58b1 65MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
65ebe634 66MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
baef58b1
SH		 67MODULE_LICENSE("GPL");
68MODULE_VERSION(DRV_VERSION);
69
70static const u32 default_msg
71 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
72 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
73
74static int debug = -1; /* defaults above */
75module_param(debug, int, 0);
76MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
77
78static const struct pci_device_id skge_id_table[] = {
275834d1
SH		 79 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
80 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
81 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
82 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
f19841f5 83 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
2d2a3871 84 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
275834d1
SH		 85 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
86 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
87 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
275834d1 88 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
f19841f5 89 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
baef58b1
SH		 90 { 0 }
91};
92MODULE_DEVICE_TABLE(pci, skge_id_table);
93
94static int skge_up(struct net_device *dev);
95static int skge_down(struct net_device *dev);
ee294dcd 96static void skge_phy_reset(struct skge_port *skge);
513f533e 97static void skge_tx_clean(struct net_device *dev);
2cd8e5d3
SH		 98static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
99static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 100static void genesis_get_stats(struct skge_port *skge, u64 *data);
101static void yukon_get_stats(struct skge_port *skge, u64 *data);
102static void yukon_init(struct skge_hw *hw, int port);
baef58b1 103static void genesis_mac_init(struct skge_hw *hw, int port);
45bada65 104static void genesis_link_up(struct skge_port *skge);
baef58b1 105
7e676d91 106/* Avoid conditionals by using array */
baef58b1
SH		 107static const int txqaddr[] = { Q_XA1, Q_XA2 };
108static const int rxqaddr[] = { Q_R1, Q_R2 };
109static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
110static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
4ebabfcb
SH		 111static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
112static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
baef58b1 113
baef58b1
SH		 114static int skge_get_regs_len(struct net_device *dev)
115{
c3f8be96 116 return 0x4000;
baef58b1
SH		 117}
118
119/*
c3f8be96
SH		 120 * Returns copy of whole control register region
121 * Note: skip RAM address register because accessing it will
122 * cause bus hangs!
baef58b1
SH		 123 */
124static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
125 void *p)
126{
127 const struct skge_port *skge = netdev_priv(dev);
baef58b1 128 const void __iomem *io = skge->hw->regs;
baef58b1
SH		 129
130 regs->version = 1;
c3f8be96
SH		 131 memset(p, 0, regs->len);
132 memcpy_fromio(p, io, B3_RAM_ADDR);
baef58b1 133
c3f8be96
SH		 134 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
135 regs->len - B3_RI_WTO_R1);
baef58b1
SH		 136}
137
8f3f8193 138/* Wake on Lan only supported on Yukon chips with rev 1 or above */
a504e64a 139static u32 wol_supported(const struct skge_hw *hw)
baef58b1 140{
d17ecb23 141 if (hw->chip_id == CHIP_ID_GENESIS)
a504e64a 142 return 0;
d17ecb23
SH		 143
144 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
145 return 0;
146
147 return WAKE_MAGIC | WAKE_PHY;
a504e64a
SH		 148}
149
150static u32 pci_wake_enabled(struct pci_dev *dev)
151{
152 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
153 u16 value;
154
155 /* If device doesn't support PM Capabilities, but request is to disable
156 * wake events, it's a nop; otherwise fail */
157 if (!pm)
158 return 0;
159
160 pci_read_config_word(dev, pm + PCI_PM_PMC, &value);
161
162 value &= PCI_PM_CAP_PME_MASK;
163 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
164
165 return value != 0;
166}
167
168static void skge_wol_init(struct skge_port *skge)
169{
170 struct skge_hw *hw = skge->hw;
171 int port = skge->port;
692412b3 172 u16 ctrl;
a504e64a 173
a504e64a
SH		 174 skge_write16(hw, B0_CTST, CS_RST_CLR);
175 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
176
692412b3
SH		 177 /* Turn on Vaux */
178 skge_write8(hw, B0_POWER_CTRL,
179 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
a504e64a 180
692412b3
SH		 181 /* WA code for COMA mode -- clear PHY reset */
182 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
183 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
184 u32 reg = skge_read32(hw, B2_GP_IO);
185 reg |= GP_DIR_9;
186 reg &= ~GP_IO_9;
187 skge_write32(hw, B2_GP_IO, reg);
188 }
a504e64a 189
692412b3
SH		 190 skge_write32(hw, SK_REG(port, GPHY_CTRL),
191 GPC_DIS_SLEEP |
192 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
193 GPC_ANEG_1 | GPC_RST_SET);
a504e64a 194
692412b3
SH		 195 skge_write32(hw, SK_REG(port, GPHY_CTRL),
196 GPC_DIS_SLEEP |
197 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
198 GPC_ANEG_1 | GPC_RST_CLR);
199
200 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
201
202 /* Force to 10/100 skge_reset will re-enable on resume */
203 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
204 PHY_AN_100FULL | PHY_AN_100HALF |
205 PHY_AN_10FULL | PHY_AN_10HALF| PHY_AN_CSMA);
206 /* no 1000 HD/FD */
207 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
208 gm_phy_write(hw, port, PHY_MARV_CTRL,
209 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
210 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
a504e64a 211
a504e64a
SH		 212
213 /* Set GMAC to no flow control and auto update for speed/duplex */
214 gma_write16(hw, port, GM_GP_CTRL,
215 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
216 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
217
218 /* Set WOL address */
219 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
220 skge->netdev->dev_addr, ETH_ALEN);
221
222 /* Turn on appropriate WOL control bits */
223 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
224 ctrl = 0;
225 if (skge->wol & WAKE_PHY)
226 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
227 else
228 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
229
230 if (skge->wol & WAKE_MAGIC)
231 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
232 else
233 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
234
235 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
236 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
237
238 /* block receiver */
239 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 240}
241
242static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
243{
244 struct skge_port *skge = netdev_priv(dev);
245
a504e64a
SH		 246 wol->supported = wol_supported(skge->hw);
247 wol->wolopts = skge->wol;
baef58b1
SH		 248}
249
250static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
251{
252 struct skge_port *skge = netdev_priv(dev);
253 struct skge_hw *hw = skge->hw;
254
692412b3 255 if (wol->wolopts & ~wol_supported(hw))
baef58b1
SH		 256 return -EOPNOTSUPP;
257
a504e64a 258 skge->wol = wol->wolopts;
baef58b1
SH		 259 return 0;
260}
261
8f3f8193
SH		 262/* Determine supported/advertised modes based on hardware.
263 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
31b619c5
SH		 264 */
265static u32 skge_supported_modes(const struct skge_hw *hw)
266{
267 u32 supported;
268
5e1705dd 269 if (hw->copper) {
31b619c5
SH		 270 supported = SUPPORTED_10baseT_Half
271 | SUPPORTED_10baseT_Full
272 | SUPPORTED_100baseT_Half
273 | SUPPORTED_100baseT_Full
274 | SUPPORTED_1000baseT_Half
275 | SUPPORTED_1000baseT_Full
276 | SUPPORTED_Autoneg| SUPPORTED_TP;
277
278 if (hw->chip_id == CHIP_ID_GENESIS)
279 supported &= ~(SUPPORTED_10baseT_Half
280 | SUPPORTED_10baseT_Full
281 | SUPPORTED_100baseT_Half
282 | SUPPORTED_100baseT_Full);
283
284 else if (hw->chip_id == CHIP_ID_YUKON)
285 supported &= ~SUPPORTED_1000baseT_Half;
286 } else
4b67be99
SH		 287 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
288 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
31b619c5
SH		 289
290 return supported;
291}
baef58b1
SH		 292
293static int skge_get_settings(struct net_device *dev,
294 struct ethtool_cmd *ecmd)
295{
296 struct skge_port *skge = netdev_priv(dev);
297 struct skge_hw *hw = skge->hw;
298
299 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 300 ecmd->supported = skge_supported_modes(hw);
baef58b1 301
5e1705dd 302 if (hw->copper) {
baef58b1
SH		 303 ecmd->port = PORT_TP;
304 ecmd->phy_address = hw->phy_addr;
31b619c5 305 } else
baef58b1 306 ecmd->port = PORT_FIBRE;
baef58b1
SH		 307
308 ecmd->advertising = skge->advertising;
309 ecmd->autoneg = skge->autoneg;
310 ecmd->speed = skge->speed;
311 ecmd->duplex = skge->duplex;
312 return 0;
313}
314
baef58b1
SH		 315static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
316{
317 struct skge_port *skge = netdev_priv(dev);
318 const struct skge_hw *hw = skge->hw;
31b619c5 319 u32 supported = skge_supported_modes(hw);
baef58b1
SH		 320
321 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 322 ecmd->advertising = supported;
323 skge->duplex = -1;
324 skge->speed = -1;
baef58b1 325 } else {
31b619c5
SH		 326 u32 setting;
327
2c668514 328 switch (ecmd->speed) {
baef58b1 329 case SPEED_1000:
31b619c5
SH		 330 if (ecmd->duplex == DUPLEX_FULL)
331 setting = SUPPORTED_1000baseT_Full;
332 else if (ecmd->duplex == DUPLEX_HALF)
333 setting = SUPPORTED_1000baseT_Half;
334 else
335 return -EINVAL;
baef58b1
SH		 336 break;
337 case SPEED_100:
31b619c5
SH		 338 if (ecmd->duplex == DUPLEX_FULL)
339 setting = SUPPORTED_100baseT_Full;
340 else if (ecmd->duplex == DUPLEX_HALF)
341 setting = SUPPORTED_100baseT_Half;
342 else
343 return -EINVAL;
344 break;
345
baef58b1 346 case SPEED_10:
31b619c5
SH		 347 if (ecmd->duplex == DUPLEX_FULL)
348 setting = SUPPORTED_10baseT_Full;
349 else if (ecmd->duplex == DUPLEX_HALF)
350 setting = SUPPORTED_10baseT_Half;
351 else
baef58b1
SH		 352 return -EINVAL;
353 break;
354 default:
355 return -EINVAL;
356 }
31b619c5
SH		 357
358 if ((setting & supported) == 0)
359 return -EINVAL;
360
361 skge->speed = ecmd->speed;
362 skge->duplex = ecmd->duplex;
baef58b1
SH		 363 }
364
365 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 366 skge->advertising = ecmd->advertising;
367
ee294dcd
SH		 368 if (netif_running(dev))
369 skge_phy_reset(skge);
370
baef58b1
SH		 371 return (0);
372}
373
374static void skge_get_drvinfo(struct net_device *dev,
375 struct ethtool_drvinfo *info)
376{
377 struct skge_port *skge = netdev_priv(dev);
378
379 strcpy(info->driver, DRV_NAME);
380 strcpy(info->version, DRV_VERSION);
381 strcpy(info->fw_version, "N/A");
382 strcpy(info->bus_info, pci_name(skge->hw->pdev));
383}
384
385static const struct skge_stat {
386 char name[ETH_GSTRING_LEN];
387 u16 xmac_offset;
388 u16 gma_offset;
389} skge_stats[] = {
390 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
391 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
392
393 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
394 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
395 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
396 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
397 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
398 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
399 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
400 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
401
402 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
403 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
404 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
405 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
406 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
407 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
408
409 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
410 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
411 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
412 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
413 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
414};
415
b9f2c044 416static int skge_get_sset_count(struct net_device *dev, int sset)
baef58b1 417{
b9f2c044
JG		 418 switch (sset) {
419 case ETH_SS_STATS:
420 return ARRAY_SIZE(skge_stats);
421 default:
422 return -EOPNOTSUPP;
423 }
baef58b1
SH		 424}
425
426static void skge_get_ethtool_stats(struct net_device *dev,
427 struct ethtool_stats *stats, u64 *data)
428{
429 struct skge_port *skge = netdev_priv(dev);
430
431 if (skge->hw->chip_id == CHIP_ID_GENESIS)
432 genesis_get_stats(skge, data);
433 else
434 yukon_get_stats(skge, data);
435}
436
437/* Use hardware MIB variables for critical path statistics and
438 * transmit feedback not reported at interrupt.
439 * Other errors are accounted for in interrupt handler.
440 */
441static struct net_device_stats *skge_get_stats(struct net_device *dev)
442{
443 struct skge_port *skge = netdev_priv(dev);
444 u64 data[ARRAY_SIZE(skge_stats)];
445
446 if (skge->hw->chip_id == CHIP_ID_GENESIS)
447 genesis_get_stats(skge, data);
448 else
449 yukon_get_stats(skge, data);
450
da00772f
SH		 451 dev->stats.tx_bytes = data[0];
452 dev->stats.rx_bytes = data[1];
453 dev->stats.tx_packets = data[2] + data[4] + data[6];
454 dev->stats.rx_packets = data[3] + data[5] + data[7];
455 dev->stats.multicast = data[3] + data[5];
456 dev->stats.collisions = data[10];
457 dev->stats.tx_aborted_errors = data[12];
baef58b1 458
da00772f 459 return &dev->stats;
baef58b1
SH		 460}
461
462static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
463{
464 int i;
465
95566065 466 switch (stringset) {
baef58b1
SH		 467 case ETH_SS_STATS:
468 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
469 memcpy(data + i * ETH_GSTRING_LEN,
470 skge_stats[i].name, ETH_GSTRING_LEN);
471 break;
472 }
473}
474
475static void skge_get_ring_param(struct net_device *dev,
476 struct ethtool_ringparam *p)
477{
478 struct skge_port *skge = netdev_priv(dev);
479
480 p->rx_max_pending = MAX_RX_RING_SIZE;
481 p->tx_max_pending = MAX_TX_RING_SIZE;
482 p->rx_mini_max_pending = 0;
483 p->rx_jumbo_max_pending = 0;
484
485 p->rx_pending = skge->rx_ring.count;
486 p->tx_pending = skge->tx_ring.count;
487 p->rx_mini_pending = 0;
488 p->rx_jumbo_pending = 0;
489}
490
491static int skge_set_ring_param(struct net_device *dev,
492 struct ethtool_ringparam *p)
493{
494 struct skge_port *skge = netdev_priv(dev);
3b8bb472 495 int err;
baef58b1
SH		 496
497 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
9db96479 498 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
baef58b1
SH		 499 return -EINVAL;
500
501 skge->rx_ring.count = p->rx_pending;
502 skge->tx_ring.count = p->tx_pending;
503
504 if (netif_running(dev)) {
505 skge_down(dev);
3b8bb472
SH		 506 err = skge_up(dev);
507 if (err)
508 dev_close(dev);
baef58b1
SH		 509 }
510
511 return 0;
512}
513
514static u32 skge_get_msglevel(struct net_device *netdev)
515{
516 struct skge_port *skge = netdev_priv(netdev);
517 return skge->msg_enable;
518}
519
520static void skge_set_msglevel(struct net_device *netdev, u32 value)
521{
522 struct skge_port *skge = netdev_priv(netdev);
523 skge->msg_enable = value;
524}
525
526static int skge_nway_reset(struct net_device *dev)
527{
528 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 529
530 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
531 return -EINVAL;
532
ee294dcd 533 skge_phy_reset(skge);
baef58b1
SH		 534 return 0;
535}
536
537static int skge_set_sg(struct net_device *dev, u32 data)
538{
539 struct skge_port *skge = netdev_priv(dev);
540 struct skge_hw *hw = skge->hw;
541
542 if (hw->chip_id == CHIP_ID_GENESIS && data)
543 return -EOPNOTSUPP;
544 return ethtool_op_set_sg(dev, data);
545}
546
547static int skge_set_tx_csum(struct net_device *dev, u32 data)
548{
549 struct skge_port *skge = netdev_priv(dev);
550 struct skge_hw *hw = skge->hw;
551
552 if (hw->chip_id == CHIP_ID_GENESIS && data)
553 return -EOPNOTSUPP;
554
555 return ethtool_op_set_tx_csum(dev, data);
556}
557
558static u32 skge_get_rx_csum(struct net_device *dev)
559{
560 struct skge_port *skge = netdev_priv(dev);
561
562 return skge->rx_csum;
563}
564
565/* Only Yukon supports checksum offload. */
566static int skge_set_rx_csum(struct net_device *dev, u32 data)
567{
568 struct skge_port *skge = netdev_priv(dev);
569
570 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
571 return -EOPNOTSUPP;
572
573 skge->rx_csum = data;
574 return 0;
575}
576
baef58b1
SH		 577static void skge_get_pauseparam(struct net_device *dev,
578 struct ethtool_pauseparam *ecmd)
579{
580 struct skge_port *skge = netdev_priv(dev);
581
5d5c8e03
SH		 582 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_SYMMETRIC)
583 || (skge->flow_control == FLOW_MODE_SYM_OR_REM);
584 ecmd->tx_pause = ecmd->rx_pause || (skge->flow_control == FLOW_MODE_LOC_SEND);
baef58b1 585
5d5c8e03 586 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
baef58b1
SH		 587}
588
589static int skge_set_pauseparam(struct net_device *dev,
590 struct ethtool_pauseparam *ecmd)
591{
592 struct skge_port *skge = netdev_priv(dev);
5d5c8e03 593 struct ethtool_pauseparam old;
baef58b1 594
5d5c8e03
SH		 595 skge_get_pauseparam(dev, &old);
596
597 if (ecmd->autoneg != old.autoneg)
598 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
599 else {
600 if (ecmd->rx_pause && ecmd->tx_pause)
601 skge->flow_control = FLOW_MODE_SYMMETRIC;
602 else if (ecmd->rx_pause && !ecmd->tx_pause)
603 skge->flow_control = FLOW_MODE_SYM_OR_REM;
604 else if (!ecmd->rx_pause && ecmd->tx_pause)
605 skge->flow_control = FLOW_MODE_LOC_SEND;
606 else
607 skge->flow_control = FLOW_MODE_NONE;
608 }
baef58b1 609
e8df8554
SH		 610 if (netif_running(dev))
611 skge_phy_reset(skge);
5d5c8e03 612
baef58b1
SH		 613 return 0;
614}
615
616/* Chip internal frequency for clock calculations */
617static inline u32 hwkhz(const struct skge_hw *hw)
618{
187ff3b8 619 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
baef58b1
SH		 620}
621
8f3f8193 622/* Chip HZ to microseconds */
baef58b1
SH		 623static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
624{
625 return (ticks * 1000) / hwkhz(hw);
626}
627
8f3f8193 628/* Microseconds to chip HZ */
baef58b1
SH		 629static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
630{
631 return hwkhz(hw) * usec / 1000;
632}
633
634static int skge_get_coalesce(struct net_device *dev,
635 struct ethtool_coalesce *ecmd)
636{
637 struct skge_port *skge = netdev_priv(dev);
638 struct skge_hw *hw = skge->hw;
639 int port = skge->port;
640
641 ecmd->rx_coalesce_usecs = 0;
642 ecmd->tx_coalesce_usecs = 0;
643
644 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
645 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
646 u32 msk = skge_read32(hw, B2_IRQM_MSK);
647
648 if (msk & rxirqmask[port])
649 ecmd->rx_coalesce_usecs = delay;
650 if (msk & txirqmask[port])
651 ecmd->tx_coalesce_usecs = delay;
652 }
653
654 return 0;
655}
656
657/* Note: interrupt timer is per board, but can turn on/off per port */
658static int skge_set_coalesce(struct net_device *dev,
659 struct ethtool_coalesce *ecmd)
660{
661 struct skge_port *skge = netdev_priv(dev);
662 struct skge_hw *hw = skge->hw;
663 int port = skge->port;
664 u32 msk = skge_read32(hw, B2_IRQM_MSK);
665 u32 delay = 25;
666
667 if (ecmd->rx_coalesce_usecs == 0)
668 msk &= ~rxirqmask[port];
669 else if (ecmd->rx_coalesce_usecs < 25 ||
670 ecmd->rx_coalesce_usecs > 33333)
671 return -EINVAL;
672 else {
673 msk |= rxirqmask[port];
674 delay = ecmd->rx_coalesce_usecs;
675 }
676
677 if (ecmd->tx_coalesce_usecs == 0)
678 msk &= ~txirqmask[port];
679 else if (ecmd->tx_coalesce_usecs < 25 ||
680 ecmd->tx_coalesce_usecs > 33333)
681 return -EINVAL;
682 else {
683 msk |= txirqmask[port];
684 delay = min(delay, ecmd->rx_coalesce_usecs);
685 }
686
687 skge_write32(hw, B2_IRQM_MSK, msk);
688 if (msk == 0)
689 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
690 else {
691 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
692 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
693 }
694 return 0;
695}
696
6abebb53
SH		 697enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
698static void skge_led(struct skge_port *skge, enum led_mode mode)
baef58b1 699{
6abebb53
SH		 700 struct skge_hw *hw = skge->hw;
701 int port = skge->port;
702
9cbe330f 703 spin_lock_bh(&hw->phy_lock);
baef58b1 704 if (hw->chip_id == CHIP_ID_GENESIS) {
6abebb53
SH		 705 switch (mode) {
706 case LED_MODE_OFF:
64f6b64d
SH		 707 if (hw->phy_type == SK_PHY_BCOM)
708 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
709 else {
710 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
711 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
712 }
6abebb53
SH		 713 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
714 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
715 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
716 break;
baef58b1 717
6abebb53
SH		 718 case LED_MODE_ON:
719 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
720 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 721
6abebb53
SH		 722 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
723 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1 724
6abebb53 725 break;
baef58b1 726
6abebb53
SH		 727 case LED_MODE_TST:
728 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
729 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
730 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 731
64f6b64d
SH		 732 if (hw->phy_type == SK_PHY_BCOM)
733 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
734 else {
735 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
736 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
737 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
738 }
739
6abebb53 740 }
baef58b1 741 } else {
6abebb53
SH		 742 switch (mode) {
743 case LED_MODE_OFF:
744 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
745 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
746 PHY_M_LED_MO_DUP(MO_LED_OFF) |
747 PHY_M_LED_MO_10(MO_LED_OFF) |
748 PHY_M_LED_MO_100(MO_LED_OFF) |
749 PHY_M_LED_MO_1000(MO_LED_OFF) |
750 PHY_M_LED_MO_RX(MO_LED_OFF));
751 break;
752 case LED_MODE_ON:
753 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
754 PHY_M_LED_PULS_DUR(PULS_170MS) |
755 PHY_M_LED_BLINK_RT(BLINK_84MS) |
756 PHY_M_LEDC_TX_CTRL |
757 PHY_M_LEDC_DP_CTRL);
46a60f2d 758
6abebb53
SH		 759 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
760 PHY_M_LED_MO_RX(MO_LED_OFF) |
761 (skge->speed == SPEED_100 ?
762 PHY_M_LED_MO_100(MO_LED_ON) : 0));
763 break;
764 case LED_MODE_TST:
765 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
766 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
767 PHY_M_LED_MO_DUP(MO_LED_ON) |
768 PHY_M_LED_MO_10(MO_LED_ON) |
769 PHY_M_LED_MO_100(MO_LED_ON) |
770 PHY_M_LED_MO_1000(MO_LED_ON) |
771 PHY_M_LED_MO_RX(MO_LED_ON));
772 }
baef58b1 773 }
9cbe330f 774 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 775}
776
777/* blink LED's for finding board */
778static int skge_phys_id(struct net_device *dev, u32 data)
779{
780 struct skge_port *skge = netdev_priv(dev);
6abebb53
SH		 781 unsigned long ms;
782 enum led_mode mode = LED_MODE_TST;
baef58b1 783
95566065 784 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
6abebb53
SH		 785 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
786 else
787 ms = data * 1000;
baef58b1 788
6abebb53
SH		 789 while (ms > 0) {
790 skge_led(skge, mode);
791 mode ^= LED_MODE_TST;
baef58b1 792
6abebb53
SH		 793 if (msleep_interruptible(BLINK_MS))
794 break;
795 ms -= BLINK_MS;
796 }
baef58b1 797
6abebb53
SH		 798 /* back to regular LED state */
799 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
baef58b1
SH		 800
801 return 0;
802}
803
afa151b9
SH		 804static int skge_get_eeprom_len(struct net_device *dev)
805{
806 struct skge_port *skge = netdev_priv(dev);
807 u32 reg2;
808
809 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, &reg2);
810 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
811}
812
813static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
814{
815 u32 val;
816
817 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
818
819 do {
820 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
821 } while (!(offset & PCI_VPD_ADDR_F));
822
823 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
824 return val;
825}
826
827static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
828{
829 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
830 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
831 offset | PCI_VPD_ADDR_F);
832
833 do {
834 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
835 } while (offset & PCI_VPD_ADDR_F);
836}
837
838static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
839 u8 *data)
840{
841 struct skge_port *skge = netdev_priv(dev);
842 struct pci_dev *pdev = skge->hw->pdev;
843 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
844 int length = eeprom->len;
845 u16 offset = eeprom->offset;
846
847 if (!cap)
848 return -EINVAL;
849
850 eeprom->magic = SKGE_EEPROM_MAGIC;
851
852 while (length > 0) {
853 u32 val = skge_vpd_read(pdev, cap, offset);
854 int n = min_t(int, length, sizeof(val));
855
856 memcpy(data, &val, n);
857 length -= n;
858 data += n;
859 offset += n;
860 }
861 return 0;
862}
863
864static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
865 u8 *data)
866{
867 struct skge_port *skge = netdev_priv(dev);
868 struct pci_dev *pdev = skge->hw->pdev;
869 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
870 int length = eeprom->len;
871 u16 offset = eeprom->offset;
872
873 if (!cap)
874 return -EINVAL;
875
876 if (eeprom->magic != SKGE_EEPROM_MAGIC)
877 return -EINVAL;
878
879 while (length > 0) {
880 u32 val;
881 int n = min_t(int, length, sizeof(val));
882
883 if (n < sizeof(val))
884 val = skge_vpd_read(pdev, cap, offset);
885 memcpy(&val, data, n);
886
887 skge_vpd_write(pdev, cap, offset, val);
888
889 length -= n;
890 data += n;
891 offset += n;
892 }
893 return 0;
894}
895
7282d491 896static const struct ethtool_ops skge_ethtool_ops = {
baef58b1
SH		 897 .get_settings = skge_get_settings,
898 .set_settings = skge_set_settings,
899 .get_drvinfo = skge_get_drvinfo,
900 .get_regs_len = skge_get_regs_len,
901 .get_regs = skge_get_regs,
902 .get_wol = skge_get_wol,
903 .set_wol = skge_set_wol,
904 .get_msglevel = skge_get_msglevel,
905 .set_msglevel = skge_set_msglevel,
906 .nway_reset = skge_nway_reset,
907 .get_link = ethtool_op_get_link,
afa151b9
SH		 908 .get_eeprom_len = skge_get_eeprom_len,
909 .get_eeprom = skge_get_eeprom,
910 .set_eeprom = skge_set_eeprom,
baef58b1
SH		 911 .get_ringparam = skge_get_ring_param,
912 .set_ringparam = skge_set_ring_param,
913 .get_pauseparam = skge_get_pauseparam,
914 .set_pauseparam = skge_set_pauseparam,
915 .get_coalesce = skge_get_coalesce,
916 .set_coalesce = skge_set_coalesce,
baef58b1 917 .set_sg = skge_set_sg,
baef58b1
SH		 918 .set_tx_csum = skge_set_tx_csum,
919 .get_rx_csum = skge_get_rx_csum,
920 .set_rx_csum = skge_set_rx_csum,
921 .get_strings = skge_get_strings,
922 .phys_id = skge_phys_id,
b9f2c044 923 .get_sset_count = skge_get_sset_count,
baef58b1
SH		 924 .get_ethtool_stats = skge_get_ethtool_stats,
925};
926
927/*
928 * Allocate ring elements and chain them together
929 * One-to-one association of board descriptors with ring elements
930 */
c3da1447 931static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
baef58b1
SH		 932{
933 struct skge_tx_desc *d;
934 struct skge_element *e;
935 int i;
936
cd861280 937 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
baef58b1
SH		 938 if (!ring->start)
939 return -ENOMEM;
940
941 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
942 e->desc = d;
943 if (i == ring->count - 1) {
944 e->next = ring->start;
945 d->next_offset = base;
946 } else {
947 e->next = e + 1;
948 d->next_offset = base + (i+1) * sizeof(*d);
949 }
950 }
951 ring->to_use = ring->to_clean = ring->start;
952
953 return 0;
954}
955
19a33d4e
SH		 956/* Allocate and setup a new buffer for receiving */
957static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
958 struct sk_buff *skb, unsigned int bufsize)
959{
960 struct skge_rx_desc *rd = e->desc;
961 u64 map;
baef58b1
SH		 962
963 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
964 PCI_DMA_FROMDEVICE);
965
966 rd->dma_lo = map;
967 rd->dma_hi = map >> 32;
968 e->skb = skb;
969 rd->csum1_start = ETH_HLEN;
970 rd->csum2_start = ETH_HLEN;
971 rd->csum1 = 0;
972 rd->csum2 = 0;
973
974 wmb();
975
976 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
977 pci_unmap_addr_set(e, mapaddr, map);
978 pci_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 979}
980
19a33d4e
SH		 981/* Resume receiving using existing skb,
982 * Note: DMA address is not changed by chip.
983 * MTU not changed while receiver active.
984 */
5a011447 985static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
19a33d4e
SH		 986{
987 struct skge_rx_desc *rd = e->desc;
988
989 rd->csum2 = 0;
990 rd->csum2_start = ETH_HLEN;
991
992 wmb();
993
994 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
995}
996
997
998/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 999static void skge_rx_clean(struct skge_port *skge)
1000{
1001 struct skge_hw *hw = skge->hw;
1002 struct skge_ring *ring = &skge->rx_ring;
1003 struct skge_element *e;
1004
19a33d4e
SH		 1005 e = ring->start;
1006 do {
baef58b1
SH		 1007 struct skge_rx_desc *rd = e->desc;
1008 rd->control = 0;
19a33d4e
SH		 1009 if (e->skb) {
1010 pci_unmap_single(hw->pdev,
1011 pci_unmap_addr(e, mapaddr),
1012 pci_unmap_len(e, maplen),
1013 PCI_DMA_FROMDEVICE);
1014 dev_kfree_skb(e->skb);
1015 e->skb = NULL;
1016 }
1017 } while ((e = e->next) != ring->start);
baef58b1
SH		 1018}
1019
19a33d4e 1020
baef58b1 1021/* Allocate buffers for receive ring
19a33d4e 1022 * For receive: to_clean is next received frame.
baef58b1 1023 */
c54f9765 1024static int skge_rx_fill(struct net_device *dev)
baef58b1 1025{
c54f9765 1026 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 1027 struct skge_ring *ring = &skge->rx_ring;
1028 struct skge_element *e;
baef58b1 1029
19a33d4e
SH		 1030 e = ring->start;
1031 do {
383181ac 1032 struct sk_buff *skb;
baef58b1 1033
c54f9765
SH		 1034 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1035 GFP_KERNEL);
19a33d4e
SH		 1036 if (!skb)
1037 return -ENOMEM;
1038
383181ac
SH		 1039 skb_reserve(skb, NET_IP_ALIGN);
1040 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
19a33d4e 1041 } while ( (e = e->next) != ring->start);
baef58b1 1042
19a33d4e
SH		 1043 ring->to_clean = ring->start;
1044 return 0;
baef58b1
SH		 1045}
1046
5d5c8e03
SH		 1047static const char *skge_pause(enum pause_status status)
1048{
1049 switch(status) {
1050 case FLOW_STAT_NONE:
1051 return "none";
1052 case FLOW_STAT_REM_SEND:
1053 return "rx only";
1054 case FLOW_STAT_LOC_SEND:
1055 return "tx_only";
1056 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1057 return "both";
1058 default:
1059 return "indeterminated";
1060 }
1061}
1062
1063
baef58b1
SH		 1064static void skge_link_up(struct skge_port *skge)
1065{
46a60f2d 1066 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
54cfb5aa
SH		 1067 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
1068
baef58b1 1069 netif_carrier_on(skge->netdev);
29b4e886 1070 netif_wake_queue(skge->netdev);
baef58b1 1071
5d5c8e03 1072 if (netif_msg_link(skge)) {
baef58b1
SH		 1073 printk(KERN_INFO PFX
1074 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1075 skge->netdev->name, skge->speed,
1076 skge->duplex == DUPLEX_FULL ? "full" : "half",
5d5c8e03
SH		 1077 skge_pause(skge->flow_status));
1078 }
baef58b1
SH		 1079}
1080
1081static void skge_link_down(struct skge_port *skge)
1082{
54cfb5aa 1083 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
baef58b1
SH		 1084 netif_carrier_off(skge->netdev);
1085 netif_stop_queue(skge->netdev);
1086
1087 if (netif_msg_link(skge))
1088 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
1089}
1090
a1bc9b87
SH		 1091
1092static void xm_link_down(struct skge_hw *hw, int port)
1093{
1094 struct net_device *dev = hw->dev[port];
1095 struct skge_port *skge = netdev_priv(dev);
501fb72d 1096 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
a1bc9b87 1097
501fb72d 1098 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
a1bc9b87 1099
a1bc9b87
SH		 1100 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1101 xm_write16(hw, port, XM_MMU_CMD, cmd);
501fb72d 1102
a1bc9b87 1103 /* dummy read to ensure writing */
501fb72d 1104 xm_read16(hw, port, XM_MMU_CMD);
a1bc9b87
SH		 1105
1106 if (netif_carrier_ok(dev))
1107 skge_link_down(skge);
1108}
1109
2cd8e5d3 1110static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
baef58b1
SH		 1111{
1112 int i;
baef58b1 1113
6b0c1480 1114 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
0781191c 1115 *val = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 1116
64f6b64d
SH		 1117 if (hw->phy_type == SK_PHY_XMAC)
1118 goto ready;
1119
89bf5f23 1120 for (i = 0; i < PHY_RETRIES; i++) {
2cd8e5d3 1121 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
89bf5f23 1122 goto ready;
0781191c 1123 udelay(1);
baef58b1
SH		 1124 }
1125
2cd8e5d3 1126 return -ETIMEDOUT;
89bf5f23 1127 ready:
2cd8e5d3 1128 *val = xm_read16(hw, port, XM_PHY_DATA);
89bf5f23 1129
2cd8e5d3
SH		 1130 return 0;
1131}
1132
1133static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1134{
1135 u16 v = 0;
1136 if (__xm_phy_read(hw, port, reg, &v))
1137 printk(KERN_WARNING PFX "%s: phy read timed out\n",
1138 hw->dev[port]->name);
baef58b1
SH		 1139 return v;
1140}
1141
2cd8e5d3 1142static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 1143{
1144 int i;
1145
6b0c1480 1146 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 1147 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 1148 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 1149 goto ready;
89bf5f23 1150 udelay(1);
baef58b1 1151 }
2cd8e5d3 1152 return -EIO;
baef58b1
SH		 1153
1154 ready:
6b0c1480 1155 xm_write16(hw, port, XM_PHY_DATA, val);
0781191c
SH		 1156 for (i = 0; i < PHY_RETRIES; i++) {
1157 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1158 return 0;
1159 udelay(1);
1160 }
1161 return -ETIMEDOUT;
baef58b1
SH		 1162}
1163
1164static void genesis_init(struct skge_hw *hw)
1165{
1166 /* set blink source counter */
1167 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1168 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1169
1170 /* configure mac arbiter */
1171 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1172
1173 /* configure mac arbiter timeout values */
1174 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1175 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1176 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1177 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1178
1179 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1180 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1181 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1182 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1183
1184 /* configure packet arbiter timeout */
1185 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1186 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1187 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1188 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1189 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1190}
1191
1192static void genesis_reset(struct skge_hw *hw, int port)
1193{
45bada65 1194 const u8 zero[8] = { 0 };
baef58b1 1195
46a60f2d
SH		 1196 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1197
baef58b1 1198 /* reset the statistics module */
6b0c1480 1199 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
501fb72d 1200 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
6b0c1480
SH		 1201 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1202 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1203 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 1204
89bf5f23 1205 /* disable Broadcom PHY IRQ */
64f6b64d
SH		 1206 if (hw->phy_type == SK_PHY_BCOM)
1207 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 1208
45bada65 1209 xm_outhash(hw, port, XM_HSM, zero);
baef58b1
SH		 1210}
1211
1212
45bada65
SH		 1213/* Convert mode to MII values */
1214static const u16 phy_pause_map[] = {
1215 [FLOW_MODE_NONE] = 0,
1216 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1217 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
5d5c8e03 1218 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
45bada65
SH		 1219};
1220
4b67be99
SH		 1221/* special defines for FIBER (88E1011S only) */
1222static const u16 fiber_pause_map[] = {
1223 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1224 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1225 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
5d5c8e03 1226 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
4b67be99
SH		 1227};
1228
45bada65
SH		 1229
1230/* Check status of Broadcom phy link */
1231static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 1232{
45bada65
SH		 1233 struct net_device *dev = hw->dev[port];
1234 struct skge_port *skge = netdev_priv(dev);
1235 u16 status;
1236
1237 /* read twice because of latch */
501fb72d 1238 xm_phy_read(hw, port, PHY_BCOM_STAT);
45bada65
SH		 1239 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1240
45bada65 1241 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1242 xm_link_down(hw, port);
64f6b64d
SH		 1243 return;
1244 }
45bada65 1245
64f6b64d
SH		 1246 if (skge->autoneg == AUTONEG_ENABLE) {
1247 u16 lpa, aux;
45bada65 1248
64f6b64d
SH		 1249 if (!(status & PHY_ST_AN_OVER))
1250 return;
45bada65 1251
64f6b64d
SH		 1252 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1253 if (lpa & PHY_B_AN_RF) {
1254 printk(KERN_NOTICE PFX "%s: remote fault\n",
1255 dev->name);
1256 return;
1257 }
45bada65 1258
64f6b64d
SH		 1259 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1260
1261 /* Check Duplex mismatch */
1262 switch (aux & PHY_B_AS_AN_RES_MSK) {
1263 case PHY_B_RES_1000FD:
1264 skge->duplex = DUPLEX_FULL;
1265 break;
1266 case PHY_B_RES_1000HD:
1267 skge->duplex = DUPLEX_HALF;
1268 break;
1269 default:
1270 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1271 dev->name);
1272 return;
45bada65
SH		 1273 }
1274
64f6b64d
SH		 1275 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1276 switch (aux & PHY_B_AS_PAUSE_MSK) {
1277 case PHY_B_AS_PAUSE_MSK:
5d5c8e03 1278 skge->flow_status = FLOW_STAT_SYMMETRIC;
64f6b64d
SH		 1279 break;
1280 case PHY_B_AS_PRR:
5d5c8e03 1281 skge->flow_status = FLOW_STAT_REM_SEND;
64f6b64d
SH		 1282 break;
1283 case PHY_B_AS_PRT:
5d5c8e03 1284 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d
SH		 1285 break;
1286 default:
5d5c8e03 1287 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1288 }
1289 skge->speed = SPEED_1000;
45bada65 1290 }
64f6b64d
SH		 1291
1292 if (!netif_carrier_ok(dev))
1293 genesis_link_up(skge);
45bada65
SH		 1294}
1295
1296/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1297 * Phy on for 100 or 10Mbit operation
1298 */
64f6b64d 1299static void bcom_phy_init(struct skge_port *skge)
45bada65
SH		 1300{
1301 struct skge_hw *hw = skge->hw;
1302 int port = skge->port;
baef58b1 1303 int i;
45bada65 1304 u16 id1, r, ext, ctl;
baef58b1
SH		 1305
1306 /* magic workaround patterns for Broadcom */
1307 static const struct {
1308 u16 reg;
1309 u16 val;
1310 } A1hack[] = {
1311 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1312 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1313 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1314 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1315 }, C0hack[] = {
1316 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1317 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1318 };
1319
45bada65
SH		 1320 /* read Id from external PHY (all have the same address) */
1321 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1322
1323 /* Optimize MDIO transfer by suppressing preamble. */
1324 r = xm_read16(hw, port, XM_MMU_CMD);
1325 r |= XM_MMU_NO_PRE;
1326 xm_write16(hw, port, XM_MMU_CMD,r);
1327
2c668514 1328 switch (id1) {
45bada65
SH		 1329 case PHY_BCOM_ID1_C0:
1330 /*
1331 * Workaround BCOM Errata for the C0 type.
1332 * Write magic patterns to reserved registers.
1333 */
1334 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1335 xm_phy_write(hw, port,
1336 C0hack[i].reg, C0hack[i].val);
1337
1338 break;
1339 case PHY_BCOM_ID1_A1:
1340 /*
1341 * Workaround BCOM Errata for the A1 type.
1342 * Write magic patterns to reserved registers.
1343 */
1344 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1345 xm_phy_write(hw, port,
1346 A1hack[i].reg, A1hack[i].val);
1347 break;
1348 }
1349
1350 /*
1351 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1352 * Disable Power Management after reset.
1353 */
1354 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1355 r |= PHY_B_AC_DIS_PM;
1356 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1357
1358 /* Dummy read */
1359 xm_read16(hw, port, XM_ISRC);
1360
1361 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1362 ctl = PHY_CT_SP1000; /* always 1000mbit */
1363
1364 if (skge->autoneg == AUTONEG_ENABLE) {
1365 /*
1366 * Workaround BCOM Errata #1 for the C5 type.
1367 * 1000Base-T Link Acquisition Failure in Slave Mode
1368 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1369 */
1370 u16 adv = PHY_B_1000C_RD;
1371 if (skge->advertising & ADVERTISED_1000baseT_Half)
1372 adv |= PHY_B_1000C_AHD;
1373 if (skge->advertising & ADVERTISED_1000baseT_Full)
1374 adv |= PHY_B_1000C_AFD;
1375 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1376
1377 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1378 } else {
1379 if (skge->duplex == DUPLEX_FULL)
1380 ctl |= PHY_CT_DUP_MD;
1381 /* Force to slave */
1382 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1383 }
1384
1385 /* Set autonegotiation pause parameters */
1386 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1387 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1388
1389 /* Handle Jumbo frames */
64f6b64d 1390 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
45bada65
SH		 1391 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1392 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1393
1394 ext |= PHY_B_PEC_HIGH_LA;
1395
1396 }
1397
1398 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1399 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1400
8f3f8193 1401 /* Use link status change interrupt */
45bada65 1402 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
64f6b64d 1403}
45bada65 1404
64f6b64d
SH		 1405static void xm_phy_init(struct skge_port *skge)
1406{
1407 struct skge_hw *hw = skge->hw;
1408 int port = skge->port;
1409 u16 ctrl = 0;
1410
1411 if (skge->autoneg == AUTONEG_ENABLE) {
1412 if (skge->advertising & ADVERTISED_1000baseT_Half)
1413 ctrl |= PHY_X_AN_HD;
1414 if (skge->advertising & ADVERTISED_1000baseT_Full)
1415 ctrl |= PHY_X_AN_FD;
1416
4b67be99 1417 ctrl |= fiber_pause_map[skge->flow_control];
64f6b64d
SH		 1418
1419 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1420
1421 /* Restart Auto-negotiation */
1422 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1423 } else {
1424 /* Set DuplexMode in Config register */
1425 if (skge->duplex == DUPLEX_FULL)
1426 ctrl |= PHY_CT_DUP_MD;
1427 /*
1428 * Do NOT enable Auto-negotiation here. This would hold
1429 * the link down because no IDLEs are transmitted
1430 */
1431 }
1432
1433 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1434
1435 /* Poll PHY for status changes */
9cbe330f 1436 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
64f6b64d
SH		 1437}
1438
501fb72d 1439static int xm_check_link(struct net_device *dev)
64f6b64d
SH		 1440{
1441 struct skge_port *skge = netdev_priv(dev);
1442 struct skge_hw *hw = skge->hw;
1443 int port = skge->port;
1444 u16 status;
1445
1446 /* read twice because of latch */
501fb72d 1447 xm_phy_read(hw, port, PHY_XMAC_STAT);
64f6b64d
SH		 1448 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1449
1450 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1451 xm_link_down(hw, port);
501fb72d 1452 return 0;
64f6b64d
SH		 1453 }
1454
1455 if (skge->autoneg == AUTONEG_ENABLE) {
1456 u16 lpa, res;
1457
1458 if (!(status & PHY_ST_AN_OVER))
501fb72d 1459 return 0;
64f6b64d
SH		 1460
1461 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1462 if (lpa & PHY_B_AN_RF) {
1463 printk(KERN_NOTICE PFX "%s: remote fault\n",
1464 dev->name);
501fb72d 1465 return 0;
64f6b64d
SH		 1466 }
1467
1468 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1469
1470 /* Check Duplex mismatch */
1471 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1472 case PHY_X_RS_FD:
1473 skge->duplex = DUPLEX_FULL;
1474 break;
1475 case PHY_X_RS_HD:
1476 skge->duplex = DUPLEX_HALF;
1477 break;
1478 default:
1479 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1480 dev->name);
501fb72d 1481 return 0;
64f6b64d
SH		 1482 }
1483
1484 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
5d5c8e03
SH		 1485 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1486 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1487 (lpa & PHY_X_P_SYM_MD))
1488 skge->flow_status = FLOW_STAT_SYMMETRIC;
1489 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1490 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1491 /* Enable PAUSE receive, disable PAUSE transmit */
1492 skge->flow_status = FLOW_STAT_REM_SEND;
1493 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1494 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1495 /* Disable PAUSE receive, enable PAUSE transmit */
1496 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d 1497 else
5d5c8e03 1498 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1499
1500 skge->speed = SPEED_1000;
1501 }
1502
1503 if (!netif_carrier_ok(dev))
1504 genesis_link_up(skge);
501fb72d 1505 return 1;
64f6b64d
SH		 1506}
1507
1508/* Poll to check for link coming up.
501fb72d 1509 *
64f6b64d 1510 * Since internal PHY is wired to a level triggered pin, can't
501fb72d
SH		 1511 * get an interrupt when carrier is detected, need to poll for
1512 * link coming up.
64f6b64d 1513 */
9cbe330f 1514static void xm_link_timer(unsigned long arg)
64f6b64d 1515{
9cbe330f 1516 struct skge_port *skge = (struct skge_port *) arg;
c4028958 1517 struct net_device *dev = skge->netdev;
64f6b64d
SH		 1518 struct skge_hw *hw = skge->hw;
1519 int port = skge->port;
501fb72d
SH		 1520 int i;
1521 unsigned long flags;
64f6b64d
SH		 1522
1523 if (!netif_running(dev))
1524 return;
1525
501fb72d
SH		 1526 spin_lock_irqsave(&hw->phy_lock, flags);
1527
1528 /*
1529 * Verify that the link by checking GPIO register three times.
1530 * This pin has the signal from the link_sync pin connected to it.
1531 */
1532 for (i = 0; i < 3; i++) {
1533 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1534 goto link_down;
1535 }
1536
1537 /* Re-enable interrupt to detect link down */
1538 if (xm_check_link(dev)) {
1539 u16 msk = xm_read16(hw, port, XM_IMSK);
1540 msk &= ~XM_IS_INP_ASS;
1541 xm_write16(hw, port, XM_IMSK, msk);
64f6b64d 1542 xm_read16(hw, port, XM_ISRC);
64f6b64d 1543 } else {
501fb72d
SH		 1544link_down:
1545 mod_timer(&skge->link_timer,
1546 round_jiffies(jiffies + LINK_HZ));
64f6b64d 1547 }
501fb72d 1548 spin_unlock_irqrestore(&hw->phy_lock, flags);
45bada65
SH		 1549}
1550
1551static void genesis_mac_init(struct skge_hw *hw, int port)
1552{
1553 struct net_device *dev = hw->dev[port];
1554 struct skge_port *skge = netdev_priv(dev);
1555 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1556 int i;
1557 u32 r;
1558 const u8 zero[6] = { 0 };
1559
0781191c
SH		 1560 for (i = 0; i < 10; i++) {
1561 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1562 MFF_SET_MAC_RST);
1563 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1564 goto reset_ok;
1565 udelay(1);
1566 }
baef58b1 1567
0781191c
SH		 1568 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1569
1570 reset_ok:
baef58b1 1571 /* Unreset the XMAC. */
6b0c1480 1572 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1573
1574 /*
1575 * Perform additional initialization for external PHYs,
1576 * namely for the 1000baseTX cards that use the XMAC's
1577 * GMII mode.
1578 */
64f6b64d
SH		 1579 if (hw->phy_type != SK_PHY_XMAC) {
1580 /* Take external Phy out of reset */
1581 r = skge_read32(hw, B2_GP_IO);
1582 if (port == 0)
1583 r |= GP_DIR_0|GP_IO_0;
1584 else
1585 r |= GP_DIR_2|GP_IO_2;
89bf5f23 1586
64f6b64d 1587 skge_write32(hw, B2_GP_IO, r);
0781191c 1588
64f6b64d
SH		 1589 /* Enable GMII interface */
1590 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1591 }
89bf5f23 1592
89bf5f23 1593
64f6b64d
SH		 1594 switch(hw->phy_type) {
1595 case SK_PHY_XMAC:
1596 xm_phy_init(skge);
1597 break;
1598 case SK_PHY_BCOM:
1599 bcom_phy_init(skge);
1600 bcom_check_link(hw, port);
1601 }
89bf5f23 1602
45bada65
SH		 1603 /* Set Station Address */
1604 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1605
45bada65
SH		 1606 /* We don't use match addresses so clear */
1607 for (i = 1; i < 16; i++)
1608 xm_outaddr(hw, port, XM_EXM(i), zero);
1609
0781191c
SH		 1610 /* Clear MIB counters */
1611 xm_write16(hw, port, XM_STAT_CMD,
1612 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1613 /* Clear two times according to Errata #3 */
1614 xm_write16(hw, port, XM_STAT_CMD,
1615 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1616
45bada65
SH		 1617 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1618 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1619
1620 /* We don't need the FCS appended to the packet. */
1621 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1622 if (jumbo)
1623 r |= XM_RX_BIG_PK_OK;
89bf5f23 1624
45bada65 1625 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1626 /*
45bada65
SH		 1627 * If in manual half duplex mode the other side might be in
1628 * full duplex mode, so ignore if a carrier extension is not seen
1629 * on frames received
89bf5f23 1630 */
45bada65 1631 r |= XM_RX_DIS_CEXT;
baef58b1 1632 }
45bada65 1633 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1634
baef58b1
SH		 1635
1636 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1637 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1638
1639 /*
1640 * Bump up the transmit threshold. This helps hold off transmit
1641 * underruns when we're blasting traffic from both ports at once.
1642 */
1643 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1644
1645 /*
1646 * Enable the reception of all error frames. This is is
1647 * a necessary evil due to the design of the XMAC. The
1648 * XMAC's receive FIFO is only 8K in size, however jumbo
1649 * frames can be up to 9000 bytes in length. When bad
1650 * frame filtering is enabled, the XMAC's RX FIFO operates
1651 * in 'store and forward' mode. For this to work, the
1652 * entire frame has to fit into the FIFO, but that means
1653 * that jumbo frames larger than 8192 bytes will be
1654 * truncated. Disabling all bad frame filtering causes
1655 * the RX FIFO to operate in streaming mode, in which
8f3f8193 1656 * case the XMAC will start transferring frames out of the
baef58b1
SH		 1657 * RX FIFO as soon as the FIFO threshold is reached.
1658 */
45bada65 1659 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1660
baef58b1
SH		 1661
1662 /*
45bada65
SH		 1663 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1664 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1665 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1666 */
45bada65
SH		 1667 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1668
1669 /*
1670 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1671 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1672 * and 'Octets Tx OK Hi Cnt Ov'.
1673 */
1674 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1675
1676 /* Configure MAC arbiter */
1677 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1678
1679 /* configure timeout values */
1680 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1681 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1682 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1683 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1684
1685 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1686 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1687 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1688 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1689
1690 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1691 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1692 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1693 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1694
1695 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1696 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1697 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1698 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1699
45bada65 1700 if (jumbo) {
baef58b1 1701 /* Enable frame flushing if jumbo frames used */
6b0c1480 1702 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1703 } else {
1704 /* enable timeout timers if normal frames */
1705 skge_write16(hw, B3_PA_CTRL,
45bada65 1706 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1707 }
baef58b1
SH		 1708}
1709
1710static void genesis_stop(struct skge_port *skge)
1711{
1712 struct skge_hw *hw = skge->hw;
1713 int port = skge->port;
89bf5f23 1714 u32 reg;
baef58b1 1715
46a60f2d
SH		 1716 genesis_reset(hw, port);
1717
baef58b1
SH		 1718 /* Clear Tx packet arbiter timeout IRQ */
1719 skge_write16(hw, B3_PA_CTRL,
1720 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1721
1722 /*
8f3f8193 1723 * If the transfer sticks at the MAC the STOP command will not
baef58b1
SH		 1724 * terminate if we don't flush the XMAC's transmit FIFO !
1725 */
6b0c1480
SH		 1726 xm_write32(hw, port, XM_MODE,
1727 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
baef58b1
SH		 1728
1729
1730 /* Reset the MAC */
6b0c1480 1731 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
baef58b1
SH		 1732
1733 /* For external PHYs there must be special handling */
64f6b64d
SH		 1734 if (hw->phy_type != SK_PHY_XMAC) {
1735 reg = skge_read32(hw, B2_GP_IO);
1736 if (port == 0) {
1737 reg |= GP_DIR_0;
1738 reg &= ~GP_IO_0;
1739 } else {
1740 reg |= GP_DIR_2;
1741 reg &= ~GP_IO_2;
1742 }
1743 skge_write32(hw, B2_GP_IO, reg);
1744 skge_read32(hw, B2_GP_IO);
baef58b1
SH		 1745 }
1746
6b0c1480
SH		 1747 xm_write16(hw, port, XM_MMU_CMD,
1748 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1749 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1750
6b0c1480 1751 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1752}
1753
1754
1755static void genesis_get_stats(struct skge_port *skge, u64 *data)
1756{
1757 struct skge_hw *hw = skge->hw;
1758 int port = skge->port;
1759 int i;
1760 unsigned long timeout = jiffies + HZ;
1761
6b0c1480 1762 xm_write16(hw, port,
baef58b1
SH		 1763 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1764
1765 /* wait for update to complete */
6b0c1480 1766 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1767 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1768 if (time_after(jiffies, timeout))
1769 break;
1770 udelay(10);
1771 }
1772
1773 /* special case for 64 bit octet counter */
6b0c1480
SH		 1774 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1775 | xm_read32(hw, port, XM_TXO_OK_LO);
1776 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1777 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1778
1779 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1780 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1781}
1782
1783static void genesis_mac_intr(struct skge_hw *hw, int port)
1784{
da00772f
SH		 1785 struct net_device *dev = hw->dev[port];
1786 struct skge_port *skge = netdev_priv(dev);
6b0c1480 1787 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1788
7e676d91
SH		 1789 if (netif_msg_intr(skge))
1790 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
da00772f 1791 dev->name, status);
baef58b1 1792
501fb72d
SH		 1793 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1794 xm_link_down(hw, port);
1795 mod_timer(&skge->link_timer, jiffies + 1);
1796 }
a1bc9b87 1797
baef58b1 1798 if (status & XM_IS_TXF_UR) {
6b0c1480 1799 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
da00772f 1800 ++dev->stats.tx_fifo_errors;
baef58b1 1801 }
501fb72d 1802
baef58b1 1803 if (status & XM_IS_RXF_OV) {
6b0c1480 1804 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
da00772f 1805 ++dev->stats.rx_fifo_errors;
baef58b1
SH		 1806 }
1807}
1808
baef58b1
SH		 1809static void genesis_link_up(struct skge_port *skge)
1810{
1811 struct skge_hw *hw = skge->hw;
1812 int port = skge->port;
a1bc9b87 1813 u16 cmd, msk;
64f6b64d 1814 u32 mode;
baef58b1 1815
6b0c1480 1816 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1817
1818 /*
1819 * enabling pause frame reception is required for 1000BT
1820 * because the XMAC is not reset if the link is going down
1821 */
5d5c8e03
SH		 1822 if (skge->flow_status == FLOW_STAT_NONE ||
1823 skge->flow_status == FLOW_STAT_LOC_SEND)
7e676d91 1824 /* Disable Pause Frame Reception */
baef58b1
SH		 1825 cmd |= XM_MMU_IGN_PF;
1826 else
1827 /* Enable Pause Frame Reception */
1828 cmd &= ~XM_MMU_IGN_PF;
1829
6b0c1480 1830 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1831
6b0c1480 1832 mode = xm_read32(hw, port, XM_MODE);
5d5c8e03
SH		 1833 if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
1834 skge->flow_status == FLOW_STAT_LOC_SEND) {
baef58b1
SH		 1835 /*
1836 * Configure Pause Frame Generation
1837 * Use internal and external Pause Frame Generation.
1838 * Sending pause frames is edge triggered.
1839 * Send a Pause frame with the maximum pause time if
1840 * internal oder external FIFO full condition occurs.
1841 * Send a zero pause time frame to re-start transmission.
1842 */
1843 /* XM_PAUSE_DA = '010000C28001' (default) */
1844 /* XM_MAC_PTIME = 0xffff (maximum) */
1845 /* remember this value is defined in big endian (!) */
6b0c1480 1846 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1847
1848 mode |= XM_PAUSE_MODE;
6b0c1480 1849 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1850 } else {
1851 /*
1852 * disable pause frame generation is required for 1000BT
1853 * because the XMAC is not reset if the link is going down
1854 */
1855 /* Disable Pause Mode in Mode Register */
1856 mode &= ~XM_PAUSE_MODE;
1857
6b0c1480 1858 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1859 }
1860
6b0c1480 1861 xm_write32(hw, port, XM_MODE, mode);
a1bc9b87 1862
501fb72d
SH		 1863 /* Turn on detection of Tx underrun, Rx overrun */
1864 msk = xm_read16(hw, port, XM_IMSK);
1865 msk &= ~(XM_IS_RXF_OV | XM_IS_TXF_UR);
a1bc9b87 1866 xm_write16(hw, port, XM_IMSK, msk);
501fb72d 1867
6b0c1480 1868 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1869
1870 /* get MMU Command Reg. */
6b0c1480 1871 cmd = xm_read16(hw, port, XM_MMU_CMD);
64f6b64d 1872 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1873 cmd |= XM_MMU_GMII_FD;
1874
89bf5f23
SH		 1875 /*
1876 * Workaround BCOM Errata (#10523) for all BCom Phys
1877 * Enable Power Management after link up
1878 */
64f6b64d
SH		 1879 if (hw->phy_type == SK_PHY_BCOM) {
1880 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1881 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1882 & ~PHY_B_AC_DIS_PM);
1883 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1884 }
baef58b1
SH		 1885
1886 /* enable Rx/Tx */
6b0c1480 1887 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1888 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1889 skge_link_up(skge);
1890}
1891
1892
45bada65 1893static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1894{
1895 struct skge_hw *hw = skge->hw;
1896 int port = skge->port;
45bada65
SH		 1897 u16 isrc;
1898
1899 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
7e676d91
SH		 1900 if (netif_msg_intr(skge))
1901 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1902 skge->netdev->name, isrc);
baef58b1 1903
45bada65
SH		 1904 if (isrc & PHY_B_IS_PSE)
1905 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1906 hw->dev[port]->name);
baef58b1
SH		 1907
1908 /* Workaround BCom Errata:
1909 * enable and disable loopback mode if "NO HCD" occurs.
1910 */
45bada65 1911 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1912 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1913 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1914 ctrl | PHY_CT_LOOP);
6b0c1480 1915 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1916 ctrl & ~PHY_CT_LOOP);
1917 }
1918
45bada65
SH		 1919 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1920 bcom_check_link(hw, port);
baef58b1 1921
baef58b1
SH		 1922}
1923
2cd8e5d3
SH		 1924static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1925{
1926 int i;
1927
1928 gma_write16(hw, port, GM_SMI_DATA, val);
1929 gma_write16(hw, port, GM_SMI_CTRL,
1930 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1931 for (i = 0; i < PHY_RETRIES; i++) {
1932 udelay(1);
1933
1934 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1935 return 0;
1936 }
1937
1938 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1939 hw->dev[port]->name);
1940 return -EIO;
1941}
1942
1943static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1944{
1945 int i;
1946
1947 gma_write16(hw, port, GM_SMI_CTRL,
1948 GM_SMI_CT_PHY_AD(hw->phy_addr)
1949 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1950
1951 for (i = 0; i < PHY_RETRIES; i++) {
1952 udelay(1);
1953 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1954 goto ready;
1955 }
1956
1957 return -ETIMEDOUT;
1958 ready:
1959 *val = gma_read16(hw, port, GM_SMI_DATA);
1960 return 0;
1961}
1962
1963static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1964{
1965 u16 v = 0;
1966 if (__gm_phy_read(hw, port, reg, &v))
1967 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1968 hw->dev[port]->name);
1969 return v;
1970}
1971
8f3f8193 1972/* Marvell Phy Initialization */
baef58b1
SH		 1973static void yukon_init(struct skge_hw *hw, int port)
1974{
1975 struct skge_port *skge = netdev_priv(hw->dev[port]);
1976 u16 ctrl, ct1000, adv;
baef58b1 1977
baef58b1 1978 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1979 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1980
1981 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1982 PHY_M_EC_MAC_S_MSK);
1983 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1984
c506a509 1985 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1986
6b0c1480 1987 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1988 }
1989
6b0c1480 1990 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1991 if (skge->autoneg == AUTONEG_DISABLE)
1992 ctrl &= ~PHY_CT_ANE;
1993
1994 ctrl |= PHY_CT_RESET;
6b0c1480 1995 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1996
1997 ctrl = 0;
1998 ct1000 = 0;
b18f2091 1999 adv = PHY_AN_CSMA;
baef58b1
SH		 2000
2001 if (skge->autoneg == AUTONEG_ENABLE) {
5e1705dd 2002 if (hw->copper) {
baef58b1
SH		 2003 if (skge->advertising & ADVERTISED_1000baseT_Full)
2004 ct1000 |= PHY_M_1000C_AFD;
2005 if (skge->advertising & ADVERTISED_1000baseT_Half)
2006 ct1000 |= PHY_M_1000C_AHD;
2007 if (skge->advertising & ADVERTISED_100baseT_Full)
2008 adv |= PHY_M_AN_100_FD;
2009 if (skge->advertising & ADVERTISED_100baseT_Half)
2010 adv |= PHY_M_AN_100_HD;
2011 if (skge->advertising & ADVERTISED_10baseT_Full)
2012 adv |= PHY_M_AN_10_FD;
2013 if (skge->advertising & ADVERTISED_10baseT_Half)
2014 adv |= PHY_M_AN_10_HD;
baef58b1 2015
4b67be99
SH		 2016 /* Set Flow-control capabilities */
2017 adv |= phy_pause_map[skge->flow_control];
2018 } else {
2019 if (skge->advertising & ADVERTISED_1000baseT_Full)
2020 adv |= PHY_M_AN_1000X_AFD;
2021 if (skge->advertising & ADVERTISED_1000baseT_Half)
2022 adv |= PHY_M_AN_1000X_AHD;
2023
2024 adv |= fiber_pause_map[skge->flow_control];
2025 }
45bada65 2026
baef58b1
SH		 2027 /* Restart Auto-negotiation */
2028 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
2029 } else {
2030 /* forced speed/duplex settings */
2031 ct1000 = PHY_M_1000C_MSE;
2032
2033 if (skge->duplex == DUPLEX_FULL)
2034 ctrl |= PHY_CT_DUP_MD;
2035
2036 switch (skge->speed) {
2037 case SPEED_1000:
2038 ctrl |= PHY_CT_SP1000;
2039 break;
2040 case SPEED_100:
2041 ctrl |= PHY_CT_SP100;
2042 break;
2043 }
2044
2045 ctrl |= PHY_CT_RESET;
2046 }
2047
c506a509 2048 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 2049
6b0c1480
SH		 2050 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2051 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1 2052
baef58b1
SH		 2053 /* Enable phy interrupt on autonegotiation complete (or link up) */
2054 if (skge->autoneg == AUTONEG_ENABLE)
4cde06ed 2055 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
baef58b1 2056 else
4cde06ed 2057 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 2058}
2059
2060static void yukon_reset(struct skge_hw *hw, int port)
2061{
6b0c1480
SH		 2062 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2063 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2064 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2065 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2066 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 2067
6b0c1480
SH		 2068 gma_write16(hw, port, GM_RX_CTRL,
2069 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 2070 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2071}
2072
c8868611
SH		 2073/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2074static int is_yukon_lite_a0(struct skge_hw *hw)
2075{
2076 u32 reg;
2077 int ret;
2078
2079 if (hw->chip_id != CHIP_ID_YUKON)
2080 return 0;
2081
2082 reg = skge_read32(hw, B2_FAR);
2083 skge_write8(hw, B2_FAR + 3, 0xff);
2084 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2085 skge_write32(hw, B2_FAR, reg);
2086 return ret;
2087}
2088
baef58b1
SH		 2089static void yukon_mac_init(struct skge_hw *hw, int port)
2090{
2091 struct skge_port *skge = netdev_priv(hw->dev[port]);
2092 int i;
2093 u32 reg;
2094 const u8 *addr = hw->dev[port]->dev_addr;
2095
2096 /* WA code for COMA mode -- set PHY reset */
2097 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 2098 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2099 reg = skge_read32(hw, B2_GP_IO);
2100 reg |= GP_DIR_9 | GP_IO_9;
2101 skge_write32(hw, B2_GP_IO, reg);
2102 }
baef58b1
SH		 2103
2104 /* hard reset */
6b0c1480
SH		 2105 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2106 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 2107
2108 /* WA code for COMA mode -- clear PHY reset */
2109 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 2110 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2111 reg = skge_read32(hw, B2_GP_IO);
2112 reg |= GP_DIR_9;
2113 reg &= ~GP_IO_9;
2114 skge_write32(hw, B2_GP_IO, reg);
2115 }
baef58b1
SH		 2116
2117 /* Set hardware config mode */
2118 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2119 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
5e1705dd 2120 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
baef58b1
SH		 2121
2122 /* Clear GMC reset */
6b0c1480
SH		 2123 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2124 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2125 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
564f9abb 2126
baef58b1
SH		 2127 if (skge->autoneg == AUTONEG_DISABLE) {
2128 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 2129 gma_write16(hw, port, GM_GP_CTRL,
2130 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 2131
2132 switch (skge->speed) {
2133 case SPEED_1000:
564f9abb 2134 reg &= ~GM_GPCR_SPEED_100;
baef58b1 2135 reg |= GM_GPCR_SPEED_1000;
564f9abb 2136 break;
baef58b1 2137 case SPEED_100:
564f9abb 2138 reg &= ~GM_GPCR_SPEED_1000;
baef58b1 2139 reg |= GM_GPCR_SPEED_100;
564f9abb
SH		 2140 break;
2141 case SPEED_10:
2142 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2143 break;
baef58b1
SH		 2144 }
2145
2146 if (skge->duplex == DUPLEX_FULL)
2147 reg |= GM_GPCR_DUP_FULL;
2148 } else
2149 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
564f9abb 2150
baef58b1
SH		 2151 switch (skge->flow_control) {
2152 case FLOW_MODE_NONE:
6b0c1480 2153 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 2154 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2155 break;
2156 case FLOW_MODE_LOC_SEND:
2157 /* disable Rx flow-control */
2158 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
5d5c8e03
SH		 2159 break;
2160 case FLOW_MODE_SYMMETRIC:
2161 case FLOW_MODE_SYM_OR_REM:
2162 /* enable Tx & Rx flow-control */
2163 break;
baef58b1
SH		 2164 }
2165
6b0c1480 2166 gma_write16(hw, port, GM_GP_CTRL, reg);
46a60f2d 2167 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2168
baef58b1 2169 yukon_init(hw, port);
baef58b1
SH		 2170
2171 /* MIB clear */
6b0c1480
SH		 2172 reg = gma_read16(hw, port, GM_PHY_ADDR);
2173 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 2174
2175 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 2176 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2177 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 2178
2179 /* transmit control */
6b0c1480 2180 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 2181
2182 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 2183 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 2184 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2185
2186 /* transmit flow control */
6b0c1480 2187 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 2188
2189 /* transmit parameter */
6b0c1480 2190 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 2191 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2192 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2193 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2194
2195 /* serial mode register */
2196 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2197 if (hw->dev[port]->mtu > 1500)
2198 reg |= GM_SMOD_JUMBO_ENA;
2199
6b0c1480 2200 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 2201
2202 /* physical address: used for pause frames */
6b0c1480 2203 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 2204 /* virtual address for data */
6b0c1480 2205 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 2206
2207 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 2208 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2209 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2210 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 2211
2212 /* Initialize Mac Fifo */
2213
2214 /* Configure Rx MAC FIFO */
6b0c1480 2215 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1 2216 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
c8868611
SH		 2217
2218 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2219 if (is_yukon_lite_a0(hw))
baef58b1 2220 reg &= ~GMF_RX_F_FL_ON;
c8868611 2221
6b0c1480
SH		 2222 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2223 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
c5923081
SH		 2224 /*
2225 * because Pause Packet Truncation in GMAC is not working
2226 * we have to increase the Flush Threshold to 64 bytes
2227 * in order to flush pause packets in Rx FIFO on Yukon-1
2228 */
2229 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
baef58b1
SH		 2230
2231 /* Configure Tx MAC FIFO */
6b0c1480
SH		 2232 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2233 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 2234}
2235
355ec572
SH		 2236/* Go into power down mode */
2237static void yukon_suspend(struct skge_hw *hw, int port)
2238{
2239 u16 ctrl;
2240
2241 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2242 ctrl |= PHY_M_PC_POL_R_DIS;
2243 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2244
2245 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2246 ctrl |= PHY_CT_RESET;
2247 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2248
2249 /* switch IEEE compatible power down mode on */
2250 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2251 ctrl |= PHY_CT_PDOWN;
2252 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2253}
2254
baef58b1
SH		 2255static void yukon_stop(struct skge_port *skge)
2256{
2257 struct skge_hw *hw = skge->hw;
2258 int port = skge->port;
2259
46a60f2d
SH		 2260 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2261 yukon_reset(hw, port);
baef58b1 2262
6b0c1480
SH		 2263 gma_write16(hw, port, GM_GP_CTRL,
2264 gma_read16(hw, port, GM_GP_CTRL)
0eedf4ac 2265 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
6b0c1480 2266 gma_read16(hw, port, GM_GP_CTRL);
baef58b1 2267
355ec572 2268 yukon_suspend(hw, port);
46a60f2d 2269
baef58b1 2270 /* set GPHY Control reset */
46a60f2d
SH		 2271 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2272 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 2273}
2274
2275static void yukon_get_stats(struct skge_port *skge, u64 *data)
2276{
2277 struct skge_hw *hw = skge->hw;
2278 int port = skge->port;
2279 int i;
2280
6b0c1480
SH		 2281 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2282 | gma_read32(hw, port, GM_TXO_OK_LO);
2283 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2284 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 2285
2286 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 2287 data[i] = gma_read32(hw, port,
baef58b1
SH		 2288 skge_stats[i].gma_offset);
2289}
2290
2291static void yukon_mac_intr(struct skge_hw *hw, int port)
2292{
7e676d91
SH		 2293 struct net_device *dev = hw->dev[port];
2294 struct skge_port *skge = netdev_priv(dev);
6b0c1480 2295 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2296
7e676d91
SH		 2297 if (netif_msg_intr(skge))
2298 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
2299 dev->name, status);
2300
baef58b1 2301 if (status & GM_IS_RX_FF_OR) {
da00772f 2302 ++dev->stats.rx_fifo_errors;
d8a09943 2303 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
baef58b1 2304 }
d8a09943 2305
baef58b1 2306 if (status & GM_IS_TX_FF_UR) {
da00772f 2307 ++dev->stats.tx_fifo_errors;
d8a09943 2308 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
baef58b1
SH		 2309 }
2310
2311}
2312
2313static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2314{
95566065 2315 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 2316 case PHY_M_PS_SPEED_1000:
2317 return SPEED_1000;
2318 case PHY_M_PS_SPEED_100:
2319 return SPEED_100;
2320 default:
2321 return SPEED_10;
2322 }
2323}
2324
2325static void yukon_link_up(struct skge_port *skge)
2326{
2327 struct skge_hw *hw = skge->hw;
2328 int port = skge->port;
2329 u16 reg;
2330
baef58b1 2331 /* Enable Transmit FIFO Underrun */
46a60f2d 2332 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
baef58b1 2333
6b0c1480 2334 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 2335 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2336 reg |= GM_GPCR_DUP_FULL;
2337
2338 /* enable Rx/Tx */
2339 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 2340 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 2341
4cde06ed 2342 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 2343 skge_link_up(skge);
2344}
2345
2346static void yukon_link_down(struct skge_port *skge)
2347{
2348 struct skge_hw *hw = skge->hw;
2349 int port = skge->port;
d8a09943 2350 u16 ctrl;
baef58b1 2351
d8a09943
SH		 2352 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2353 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2354 gma_write16(hw, port, GM_GP_CTRL, ctrl);
baef58b1 2355
5d5c8e03
SH		 2356 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2357 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2358 ctrl |= PHY_M_AN_ASP;
baef58b1 2359 /* restore Asymmetric Pause bit */
5d5c8e03 2360 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
baef58b1
SH		 2361 }
2362
baef58b1
SH		 2363 skge_link_down(skge);
2364
2365 yukon_init(hw, port);
2366}
2367
2368static void yukon_phy_intr(struct skge_port *skge)
2369{
2370 struct skge_hw *hw = skge->hw;
2371 int port = skge->port;
2372 const char *reason = NULL;
2373 u16 istatus, phystat;
2374
6b0c1480
SH		 2375 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2376 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91
SH		 2377
2378 if (netif_msg_intr(skge))
2379 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
2380 skge->netdev->name, istatus, phystat);
baef58b1
SH		 2381
2382 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 2383 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 2384 & PHY_M_AN_RF) {
2385 reason = "remote fault";
2386 goto failed;
2387 }
2388
c506a509 2389 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 2390 reason = "master/slave fault";
2391 goto failed;
2392 }
2393
2394 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2395 reason = "speed/duplex";
2396 goto failed;
2397 }
2398
2399 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2400 ? DUPLEX_FULL : DUPLEX_HALF;
2401 skge->speed = yukon_speed(hw, phystat);
2402
baef58b1
SH		 2403 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2404 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2405 case PHY_M_PS_PAUSE_MSK:
5d5c8e03 2406 skge->flow_status = FLOW_STAT_SYMMETRIC;
baef58b1
SH		 2407 break;
2408 case PHY_M_PS_RX_P_EN:
5d5c8e03 2409 skge->flow_status = FLOW_STAT_REM_SEND;
baef58b1
SH		 2410 break;
2411 case PHY_M_PS_TX_P_EN:
5d5c8e03 2412 skge->flow_status = FLOW_STAT_LOC_SEND;
baef58b1
SH		 2413 break;
2414 default:
5d5c8e03 2415 skge->flow_status = FLOW_STAT_NONE;
baef58b1
SH		 2416 }
2417
5d5c8e03 2418 if (skge->flow_status == FLOW_STAT_NONE ||
baef58b1 2419 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 2420 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 2421 else
6b0c1480 2422 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 2423 yukon_link_up(skge);
2424 return;
2425 }
2426
2427 if (istatus & PHY_M_IS_LSP_CHANGE)
2428 skge->speed = yukon_speed(hw, phystat);
2429
2430 if (istatus & PHY_M_IS_DUP_CHANGE)
2431 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2432 if (istatus & PHY_M_IS_LST_CHANGE) {
2433 if (phystat & PHY_M_PS_LINK_UP)
2434 yukon_link_up(skge);
2435 else
2436 yukon_link_down(skge);
2437 }
2438 return;
2439 failed:
2440 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2441 skge->netdev->name, reason);
2442
2443 /* XXX restart autonegotiation? */
2444}
2445
ee294dcd
SH		 2446static void skge_phy_reset(struct skge_port *skge)
2447{
2448 struct skge_hw *hw = skge->hw;
2449 int port = skge->port;
aae343d4 2450 struct net_device *dev = hw->dev[port];
ee294dcd
SH		 2451
2452 netif_stop_queue(skge->netdev);
2453 netif_carrier_off(skge->netdev);
2454
9cbe330f 2455 spin_lock_bh(&hw->phy_lock);
ee294dcd
SH		 2456 if (hw->chip_id == CHIP_ID_GENESIS) {
2457 genesis_reset(hw, port);
2458 genesis_mac_init(hw, port);
2459 } else {
2460 yukon_reset(hw, port);
2461 yukon_init(hw, port);
2462 }
9cbe330f 2463 spin_unlock_bh(&hw->phy_lock);
75814090
SH		 2464
2465 dev->set_multicast_list(dev);
ee294dcd
SH		 2466}
2467
2cd8e5d3
SH		 2468/* Basic MII support */
2469static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2470{
2471 struct mii_ioctl_data *data = if_mii(ifr);
2472 struct skge_port *skge = netdev_priv(dev);
2473 struct skge_hw *hw = skge->hw;
2474 int err = -EOPNOTSUPP;
2475
2476 if (!netif_running(dev))
2477 return -ENODEV; /* Phy still in reset */
2478
2479 switch(cmd) {
2480 case SIOCGMIIPHY:
2481 data->phy_id = hw->phy_addr;
2482
2483 /* fallthru */
2484 case SIOCGMIIREG: {
2485 u16 val = 0;
9cbe330f 2486 spin_lock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2487 if (hw->chip_id == CHIP_ID_GENESIS)
2488 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2489 else
2490 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
9cbe330f 2491 spin_unlock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2492 data->val_out = val;
2493 break;
2494 }
2495
2496 case SIOCSMIIREG:
2497 if (!capable(CAP_NET_ADMIN))
2498 return -EPERM;
2499
9cbe330f 2500 spin_lock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2501 if (hw->chip_id == CHIP_ID_GENESIS)
2502 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2503 data->val_in);
2504 else
2505 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2506 data->val_in);
9cbe330f 2507 spin_unlock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2508 break;
2509 }
2510 return err;
2511}
2512
7fb7ac24
SH		 2513/* Assign Ram Buffer allocation to queue */
2514static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, u32 space)
baef58b1
SH		 2515{
2516 u32 end;
2517
7fb7ac24
SH		 2518 /* convert from K bytes to qwords used for hw register */
2519 start *= 1024/8;
2520 space *= 1024/8;
2521 end = start + space - 1;
baef58b1
SH		 2522
2523 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2524 skge_write32(hw, RB_ADDR(q, RB_START), start);
7fb7ac24 2525 skge_write32(hw, RB_ADDR(q, RB_END), end);
baef58b1
SH		 2526 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2527 skge_write32(hw, RB_ADDR(q, RB_RP), start);
baef58b1
SH		 2528
2529 if (q == Q_R1 || q == Q_R2) {
7fb7ac24
SH		 2530 u32 tp = space - space/4;
2531
baef58b1 2532 /* Set thresholds on receive queue's */
7fb7ac24
SH		 2533 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
2534 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
2535 } else if (hw->chip_id != CHIP_ID_GENESIS)
2536 /* Genesis Tx Fifo is too small for normal store/forward */
baef58b1 2537 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
baef58b1
SH		 2538
2539 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2540}
2541
2542/* Setup Bus Memory Interface */
2543static void skge_qset(struct skge_port *skge, u16 q,
2544 const struct skge_element *e)
2545{
2546 struct skge_hw *hw = skge->hw;
2547 u32 watermark = 0x600;
2548 u64 base = skge->dma + (e->desc - skge->mem);
2549
2550 /* optimization to reduce window on 32bit/33mhz */
2551 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2552 watermark /= 2;
2553
2554 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2555 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2556 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2557 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2558}
2559
2560static int skge_up(struct net_device *dev)
2561{
2562 struct skge_port *skge = netdev_priv(dev);
2563 struct skge_hw *hw = skge->hw;
2564 int port = skge->port;
7fb7ac24 2565 u32 ramaddr, ramsize, rxspace;
baef58b1
SH		 2566 size_t rx_size, tx_size;
2567 int err;
2568
fae87592
SH		 2569 if (!is_valid_ether_addr(dev->dev_addr))
2570 return -EINVAL;
2571
baef58b1
SH		 2572 if (netif_msg_ifup(skge))
2573 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2574
19a33d4e 2575 if (dev->mtu > RX_BUF_SIZE)
901ccefb 2576 skge->rx_buf_size = dev->mtu + ETH_HLEN;
19a33d4e
SH		 2577 else
2578 skge->rx_buf_size = RX_BUF_SIZE;
2579
2580
baef58b1
SH		 2581 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2582 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2583 skge->mem_size = tx_size + rx_size;
2584 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2585 if (!skge->mem)
2586 return -ENOMEM;
2587
c3da1447
SH		 2588 BUG_ON(skge->dma & 7);
2589
2590 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
1479d13c 2591 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
c3da1447
SH		 2592 err = -EINVAL;
2593 goto free_pci_mem;
2594 }
2595
baef58b1
SH		 2596 memset(skge->mem, 0, skge->mem_size);
2597
203babb6
SH		 2598 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2599 if (err)
baef58b1
SH		 2600 goto free_pci_mem;
2601
c54f9765 2602 err = skge_rx_fill(dev);
19a33d4e 2603 if (err)
baef58b1
SH		 2604 goto free_rx_ring;
2605
203babb6
SH		 2606 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2607 skge->dma + rx_size);
2608 if (err)
baef58b1
SH		 2609 goto free_rx_ring;
2610
8f3f8193 2611 /* Initialize MAC */
9cbe330f 2612 spin_lock_bh(&hw->phy_lock);
baef58b1
SH		 2613 if (hw->chip_id == CHIP_ID_GENESIS)
2614 genesis_mac_init(hw, port);
2615 else
2616 yukon_mac_init(hw, port);
9cbe330f 2617 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 2618
2619 /* Configure RAMbuffers */
7fb7ac24
SH		 2620 ramsize = (hw->ram_size - hw->ram_offset) / hw->ports;
2621 ramaddr = hw->ram_offset + port * ramsize;
2622 rxspace = 8 + (2*(ramsize - 16))/3;
baef58b1 2623
7fb7ac24
SH		 2624 skge_ramset(hw, rxqaddr[port], ramaddr, rxspace);
2625 skge_ramset(hw, txqaddr[port], ramaddr + rxspace, ramsize - rxspace);
baef58b1 2626
7fb7ac24 2627 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
baef58b1 2628 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
baef58b1
SH		 2629 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2630
2631 /* Start receiver BMU */
2632 wmb();
2633 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
6abebb53 2634 skge_led(skge, LED_MODE_ON);
baef58b1 2635
4ebabfcb
SH		 2636 spin_lock_irq(&hw->hw_lock);
2637 hw->intr_mask |= portmask[port];
2638 skge_write32(hw, B0_IMSK, hw->intr_mask);
2639 spin_unlock_irq(&hw->hw_lock);
2640
bea3348e 2641 napi_enable(&skge->napi);
baef58b1
SH		 2642 return 0;
2643
2644 free_rx_ring:
2645 skge_rx_clean(skge);
2646 kfree(skge->rx_ring.start);
2647 free_pci_mem:
2648 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2649 skge->mem = NULL;
baef58b1
SH		 2650
2651 return err;
2652}
2653
60b24b51
SH		 2654/* stop receiver */
2655static void skge_rx_stop(struct skge_hw *hw, int port)
2656{
2657 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2658 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2659 RB_RST_SET|RB_DIS_OP_MD);
2660 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2661}
2662
baef58b1
SH		 2663static int skge_down(struct net_device *dev)
2664{
2665 struct skge_port *skge = netdev_priv(dev);
2666 struct skge_hw *hw = skge->hw;
2667 int port = skge->port;
2668
7731a4ea
SH		 2669 if (skge->mem == NULL)
2670 return 0;
2671
baef58b1
SH		 2672 if (netif_msg_ifdown(skge))
2673 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2674
2675 netif_stop_queue(dev);
692412b3 2676
64f6b64d 2677 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
9cbe330f 2678 del_timer_sync(&skge->link_timer);
baef58b1 2679
bea3348e 2680 napi_disable(&skge->napi);
692412b3 2681 netif_carrier_off(dev);
4ebabfcb
SH		 2682
2683 spin_lock_irq(&hw->hw_lock);
2684 hw->intr_mask &= ~portmask[port];
2685 skge_write32(hw, B0_IMSK, hw->intr_mask);
2686 spin_unlock_irq(&hw->hw_lock);
2687
46a60f2d
SH		 2688 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2689 if (hw->chip_id == CHIP_ID_GENESIS)
2690 genesis_stop(skge);
2691 else
2692 yukon_stop(skge);
2693
baef58b1
SH		 2694 /* Stop transmitter */
2695 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2696 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2697 RB_RST_SET|RB_DIS_OP_MD);
2698
baef58b1
SH		 2699
2700 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2701 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2702 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2703
2704 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2705 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2706 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2707
2708 /* Reset PCI FIFO */
2709 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2710 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2711
2712 /* Reset the RAM Buffer async Tx queue */
2713 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
60b24b51
SH		 2714
2715 skge_rx_stop(hw, port);
baef58b1
SH		 2716
2717 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2718 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2719 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
baef58b1 2720 } else {
6b0c1480
SH		 2721 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2722 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2723 }
2724
6abebb53 2725 skge_led(skge, LED_MODE_OFF);
baef58b1 2726
e3a1b99f 2727 netif_tx_lock_bh(dev);
513f533e 2728 skge_tx_clean(dev);
e3a1b99f
SH		 2729 netif_tx_unlock_bh(dev);
2730
baef58b1
SH		 2731 skge_rx_clean(skge);
2732
2733 kfree(skge->rx_ring.start);
2734 kfree(skge->tx_ring.start);
2735 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2736 skge->mem = NULL;
baef58b1
SH		 2737 return 0;
2738}
2739
29b4e886
SH		 2740static inline int skge_avail(const struct skge_ring *ring)
2741{
992c9623 2742 smp_mb();
29b4e886
SH		 2743 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2744 + (ring->to_clean - ring->to_use) - 1;
2745}
2746
baef58b1
SH		 2747static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2748{
2749 struct skge_port *skge = netdev_priv(dev);
2750 struct skge_hw *hw = skge->hw;
baef58b1
SH		 2751 struct skge_element *e;
2752 struct skge_tx_desc *td;
2753 int i;
2754 u32 control, len;
2755 u64 map;
baef58b1 2756
5b057c6b 2757 if (skb_padto(skb, ETH_ZLEN))
baef58b1
SH		 2758 return NETDEV_TX_OK;
2759
513f533e 2760 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
baef58b1 2761 return NETDEV_TX_BUSY;
baef58b1 2762
7c442fa1 2763 e = skge->tx_ring.to_use;
baef58b1 2764 td = e->desc;
7c442fa1 2765 BUG_ON(td->control & BMU_OWN);
baef58b1
SH		 2766 e->skb = skb;
2767 len = skb_headlen(skb);
2768 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2769 pci_unmap_addr_set(e, mapaddr, map);
2770 pci_unmap_len_set(e, maplen, len);
2771
2772 td->dma_lo = map;
2773 td->dma_hi = map >> 32;
2774
84fa7933 2775 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ea2ae17d 2776 const int offset = skb_transport_offset(skb);
baef58b1
SH		 2777
2778 /* This seems backwards, but it is what the sk98lin
2779 * does. Looks like hardware is wrong?
2780 */
b0061ce4 2781 if (ipip_hdr(skb)->protocol == IPPROTO_UDP
981d0377 2782 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2783 control = BMU_TCP_CHECK;
2784 else
2785 control = BMU_UDP_CHECK;
2786
2787 td->csum_offs = 0;
2788 td->csum_start = offset;
ff1dcadb 2789 td->csum_write = offset + skb->csum_offset;
baef58b1
SH		 2790 } else
2791 control = BMU_CHECK;
2792
2793 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2794 control |= BMU_EOF| BMU_IRQ_EOF;
2795 else {
2796 struct skge_tx_desc *tf = td;
2797
2798 control |= BMU_STFWD;
2799 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2800 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2801
2802 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2803 frag->size, PCI_DMA_TODEVICE);
2804
2805 e = e->next;
7c442fa1 2806 e->skb = skb;
baef58b1 2807 tf = e->desc;
7c442fa1
SH		 2808 BUG_ON(tf->control & BMU_OWN);
2809
baef58b1
SH		 2810 tf->dma_lo = map;
2811 tf->dma_hi = (u64) map >> 32;
2812 pci_unmap_addr_set(e, mapaddr, map);
2813 pci_unmap_len_set(e, maplen, frag->size);
2814
2815 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2816 }
2817 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2818 }
2819 /* Make sure all the descriptors written */
2820 wmb();
2821 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2822 wmb();
2823
2824 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2825
7c442fa1 2826 if (unlikely(netif_msg_tx_queued(skge)))
0b2d7fea 2827 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
7c442fa1 2828 dev->name, e - skge->tx_ring.start, skb->len);
baef58b1 2829
7c442fa1 2830 skge->tx_ring.to_use = e->next;
992c9623
SH		 2831 smp_wmb();
2832
9db96479 2833 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
baef58b1
SH		 2834 pr_debug("%s: transmit queue full\n", dev->name);
2835 netif_stop_queue(dev);
2836 }
2837
c68ce71a
SH		 2838 dev->trans_start = jiffies;
2839
baef58b1
SH		 2840 return NETDEV_TX_OK;
2841}
2842
7c442fa1
SH		 2843
2844/* Free resources associated with this reing element */
2845static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2846 u32 control)
866b4f3e
SH		 2847{
2848 struct pci_dev *pdev = skge->hw->pdev;
866b4f3e 2849
7c442fa1
SH		 2850 /* skb header vs. fragment */
2851 if (control & BMU_STF)
866b4f3e 2852 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
7c442fa1
SH		 2853 pci_unmap_len(e, maplen),
2854 PCI_DMA_TODEVICE);
2855 else
2856 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2857 pci_unmap_len(e, maplen),
2858 PCI_DMA_TODEVICE);
866b4f3e 2859
7c442fa1
SH		 2860 if (control & BMU_EOF) {
2861 if (unlikely(netif_msg_tx_done(skge)))
2862 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2863 skge->netdev->name, e - skge->tx_ring.start);
866b4f3e 2864
513f533e 2865 dev_kfree_skb(e->skb);
baef58b1
SH		 2866 }
2867}
2868
7c442fa1 2869/* Free all buffers in transmit ring */
513f533e 2870static void skge_tx_clean(struct net_device *dev)
baef58b1 2871{
513f533e 2872 struct skge_port *skge = netdev_priv(dev);
7c442fa1 2873 struct skge_element *e;
baef58b1 2874
7c442fa1
SH		 2875 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2876 struct skge_tx_desc *td = e->desc;
2877 skge_tx_free(skge, e, td->control);
2878 td->control = 0;
2879 }
2880
2881 skge->tx_ring.to_clean = e;
513f533e 2882 netif_wake_queue(dev);
baef58b1
SH		 2883}
2884
2885static void skge_tx_timeout(struct net_device *dev)
2886{
2887 struct skge_port *skge = netdev_priv(dev);
2888
2889 if (netif_msg_timer(skge))
2890 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2891
2892 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
513f533e 2893 skge_tx_clean(dev);
baef58b1
SH		 2894}
2895
2896static int skge_change_mtu(struct net_device *dev, int new_mtu)
2897{
60b24b51
SH		 2898 struct skge_port *skge = netdev_priv(dev);
2899 struct skge_hw *hw = skge->hw;
2900 int port = skge->port;
7731a4ea 2901 int err;
60b24b51 2902 u16 ctl, reg;
baef58b1 2903
95566065 2904 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2905 return -EINVAL;
2906
7731a4ea
SH		 2907 if (!netif_running(dev)) {
2908 dev->mtu = new_mtu;
2909 return 0;
2910 }
2911
60b24b51
SH		 2912 skge_write32(hw, B0_IMSK, 0);
2913 dev->trans_start = jiffies; /* prevent tx timeout */
2914 netif_stop_queue(dev);
2915 napi_disable(&skge->napi);
2916
2917 ctl = gma_read16(hw, port, GM_GP_CTRL);
2918 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2919
2920 skge_rx_clean(skge);
2921 skge_rx_stop(hw, port);
baef58b1 2922
19a33d4e 2923 dev->mtu = new_mtu;
7731a4ea 2924
60b24b51
SH		 2925 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2926 if (new_mtu > 1500)
2927 reg |= GM_SMOD_JUMBO_ENA;
2928 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2929
2930 skge_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2931
2932 err = skge_rx_fill(dev);
2933 wmb();
2934 if (!err)
2935 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2936 skge_write32(hw, B0_IMSK, hw->intr_mask);
2937
7731a4ea
SH		 2938 if (err)
2939 dev_close(dev);
60b24b51
SH		 2940 else {
2941 gma_write16(hw, port, GM_GP_CTRL, ctl);
2942
2943 napi_enable(&skge->napi);
2944 netif_wake_queue(dev);
2945 }
baef58b1
SH		 2946
2947 return err;
2948}
2949
c4cd29d2
SH		 2950static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2951
2952static void genesis_add_filter(u8 filter[8], const u8 *addr)
2953{
2954 u32 crc, bit;
2955
2956 crc = ether_crc_le(ETH_ALEN, addr);
2957 bit = ~crc & 0x3f;
2958 filter[bit/8] |= 1 << (bit%8);
2959}
2960
baef58b1
SH		 2961static void genesis_set_multicast(struct net_device *dev)
2962{
2963 struct skge_port *skge = netdev_priv(dev);
2964 struct skge_hw *hw = skge->hw;
2965 int port = skge->port;
2966 int i, count = dev->mc_count;
2967 struct dev_mc_list *list = dev->mc_list;
2968 u32 mode;
2969 u8 filter[8];
2970
6b0c1480 2971 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2972 mode |= XM_MD_ENA_HASH;
2973 if (dev->flags & IFF_PROMISC)
2974 mode |= XM_MD_ENA_PROM;
2975 else
2976 mode &= ~XM_MD_ENA_PROM;
2977
2978 if (dev->flags & IFF_ALLMULTI)
2979 memset(filter, 0xff, sizeof(filter));
2980 else {
2981 memset(filter, 0, sizeof(filter));
c4cd29d2
SH		 2982
2983 if (skge->flow_status == FLOW_STAT_REM_SEND
2984 || skge->flow_status == FLOW_STAT_SYMMETRIC)
2985 genesis_add_filter(filter, pause_mc_addr);
2986
2987 for (i = 0; list && i < count; i++, list = list->next)
2988 genesis_add_filter(filter, list->dmi_addr);
baef58b1
SH		 2989 }
2990
6b0c1480 2991 xm_write32(hw, port, XM_MODE, mode);
45bada65 2992 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2993}
2994
c4cd29d2
SH		 2995static void yukon_add_filter(u8 filter[8], const u8 *addr)
2996{
2997 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2998 filter[bit/8] |= 1 << (bit%8);
2999}
3000
baef58b1
SH		 3001static void yukon_set_multicast(struct net_device *dev)
3002{
3003 struct skge_port *skge = netdev_priv(dev);
3004 struct skge_hw *hw = skge->hw;
3005 int port = skge->port;
3006 struct dev_mc_list *list = dev->mc_list;
c4cd29d2
SH		 3007 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND
3008 || skge->flow_status == FLOW_STAT_SYMMETRIC);
baef58b1
SH		 3009 u16 reg;
3010 u8 filter[8];
3011
3012 memset(filter, 0, sizeof(filter));
3013
6b0c1480 3014 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 3015 reg |= GM_RXCR_UCF_ENA;
3016
8f3f8193 3017 if (dev->flags & IFF_PROMISC) /* promiscuous */
baef58b1
SH		 3018 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3019 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
3020 memset(filter, 0xff, sizeof(filter));
c4cd29d2 3021 else if (dev->mc_count == 0 && !rx_pause)/* no multicast */
baef58b1
SH		 3022 reg &= ~GM_RXCR_MCF_ENA;
3023 else {
3024 int i;
3025 reg |= GM_RXCR_MCF_ENA;
3026
c4cd29d2
SH		 3027 if (rx_pause)
3028 yukon_add_filter(filter, pause_mc_addr);
3029
3030 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3031 yukon_add_filter(filter, list->dmi_addr);
baef58b1
SH		 3032 }
3033
3034
6b0c1480 3035 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 3036 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 3037 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 3038 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 3039 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 3040 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 3041 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 3042 (u16)filter[6] | ((u16)filter[7] << 8));
3043
6b0c1480 3044 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 3045}
3046
383181ac
SH		 3047static inline u16 phy_length(const struct skge_hw *hw, u32 status)
3048{
3049 if (hw->chip_id == CHIP_ID_GENESIS)
3050 return status >> XMR_FS_LEN_SHIFT;
3051 else
3052 return status >> GMR_FS_LEN_SHIFT;
3053}
3054
baef58b1
SH		 3055static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
3056{
3057 if (hw->chip_id == CHIP_ID_GENESIS)
3058 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
3059 else
3060 return (status & GMR_FS_ANY_ERR) ||
3061 (status & GMR_FS_RX_OK) == 0;
3062}
3063
19a33d4e
SH		 3064
3065/* Get receive buffer from descriptor.
3066 * Handles copy of small buffers and reallocation failures
3067 */
c54f9765
SH		 3068static struct sk_buff *skge_rx_get(struct net_device *dev,
3069 struct skge_element *e,
3070 u32 control, u32 status, u16 csum)
19a33d4e 3071{
c54f9765 3072 struct skge_port *skge = netdev_priv(dev);
383181ac
SH		 3073 struct sk_buff *skb;
3074 u16 len = control & BMU_BBC;
3075
3076 if (unlikely(netif_msg_rx_status(skge)))
3077 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
c54f9765 3078 dev->name, e - skge->rx_ring.start,
383181ac
SH		 3079 status, len);
3080
3081 if (len > skge->rx_buf_size)
3082 goto error;
3083
3084 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3085 goto error;
3086
3087 if (bad_phy_status(skge->hw, status))
3088 goto error;
3089
3090 if (phy_length(skge->hw, status) != len)
3091 goto error;
19a33d4e
SH		 3092
3093 if (len < RX_COPY_THRESHOLD) {
c54f9765 3094 skb = netdev_alloc_skb(dev, len + 2);
383181ac
SH		 3095 if (!skb)
3096 goto resubmit;
19a33d4e 3097
383181ac 3098 skb_reserve(skb, 2);
19a33d4e
SH		 3099 pci_dma_sync_single_for_cpu(skge->hw->pdev,
3100 pci_unmap_addr(e, mapaddr),
3101 len, PCI_DMA_FROMDEVICE);
d626f62b 3102 skb_copy_from_linear_data(e->skb, skb->data, len);
19a33d4e
SH		 3103 pci_dma_sync_single_for_device(skge->hw->pdev,
3104 pci_unmap_addr(e, mapaddr),
3105 len, PCI_DMA_FROMDEVICE);
19a33d4e 3106 skge_rx_reuse(e, skge->rx_buf_size);
19a33d4e 3107 } else {
383181ac 3108 struct sk_buff *nskb;
c54f9765 3109 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
383181ac
SH		 3110 if (!nskb)
3111 goto resubmit;
19a33d4e 3112
901ccefb 3113 skb_reserve(nskb, NET_IP_ALIGN);
19a33d4e
SH		 3114 pci_unmap_single(skge->hw->pdev,
3115 pci_unmap_addr(e, mapaddr),
3116 pci_unmap_len(e, maplen),
3117 PCI_DMA_FROMDEVICE);
3118 skb = e->skb;
383181ac 3119 prefetch(skb->data);
19a33d4e 3120 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
baef58b1 3121 }
383181ac
SH		 3122
3123 skb_put(skb, len);
383181ac
SH		 3124 if (skge->rx_csum) {
3125 skb->csum = csum;
84fa7933 3126 skb->ip_summed = CHECKSUM_COMPLETE;
383181ac
SH		 3127 }
3128
c54f9765 3129 skb->protocol = eth_type_trans(skb, dev);
383181ac
SH		 3130
3131 return skb;
3132error:
3133
3134 if (netif_msg_rx_err(skge))
3135 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
c54f9765 3136 dev->name, e - skge->rx_ring.start,
383181ac
SH		 3137 control, status);
3138
3139 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
3140 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
da00772f 3141 dev->stats.rx_length_errors++;
383181ac 3142 if (status & XMR_FS_FRA_ERR)
da00772f 3143 dev->stats.rx_frame_errors++;
383181ac 3144 if (status & XMR_FS_FCS_ERR)
da00772f 3145 dev->stats.rx_crc_errors++;
383181ac
SH		 3146 } else {
3147 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
da00772f 3148 dev->stats.rx_length_errors++;
383181ac 3149 if (status & GMR_FS_FRAGMENT)
da00772f 3150 dev->stats.rx_frame_errors++;
383181ac 3151 if (status & GMR_FS_CRC_ERR)
da00772f 3152 dev->stats.rx_crc_errors++;
383181ac
SH		 3153 }
3154
3155resubmit:
3156 skge_rx_reuse(e, skge->rx_buf_size);
3157 return NULL;
baef58b1
SH		 3158}
3159
7c442fa1 3160/* Free all buffers in Tx ring which are no longer owned by device */
513f533e 3161static void skge_tx_done(struct net_device *dev)
00a6cae2 3162{
7c442fa1 3163 struct skge_port *skge = netdev_priv(dev);
00a6cae2 3164 struct skge_ring *ring = &skge->tx_ring;
7c442fa1
SH		 3165 struct skge_element *e;
3166
513f533e 3167 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
00a6cae2 3168
866b4f3e 3169 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
992c9623 3170 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
00a6cae2 3171
992c9623 3172 if (control & BMU_OWN)
00a6cae2
SH		 3173 break;
3174
992c9623 3175 skge_tx_free(skge, e, control);
00a6cae2 3176 }
7c442fa1 3177 skge->tx_ring.to_clean = e;
866b4f3e 3178
992c9623
SH		 3179 /* Can run lockless until we need to synchronize to restart queue. */
3180 smp_mb();
3181
3182 if (unlikely(netif_queue_stopped(dev) &&
3183 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3184 netif_tx_lock(dev);
3185 if (unlikely(netif_queue_stopped(dev) &&
3186 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3187 netif_wake_queue(dev);
00a6cae2 3188
992c9623
SH		 3189 }
3190 netif_tx_unlock(dev);
3191 }
00a6cae2 3192}
19a33d4e 3193
bea3348e 3194static int skge_poll(struct napi_struct *napi, int to_do)
baef58b1 3195{
bea3348e
SH		 3196 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3197 struct net_device *dev = skge->netdev;
baef58b1
SH		 3198 struct skge_hw *hw = skge->hw;
3199 struct skge_ring *ring = &skge->rx_ring;
3200 struct skge_element *e;
00a6cae2
SH		 3201 int work_done = 0;
3202
513f533e
SH		 3203 skge_tx_done(dev);
3204
3205 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3206
1631aef1 3207 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
baef58b1 3208 struct skge_rx_desc *rd = e->desc;
19a33d4e 3209 struct sk_buff *skb;
383181ac 3210 u32 control;
baef58b1
SH		 3211
3212 rmb();
3213 control = rd->control;
3214 if (control & BMU_OWN)
3215 break;
3216
c54f9765 3217 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
19a33d4e 3218 if (likely(skb)) {
19a33d4e
SH		 3219 dev->last_rx = jiffies;
3220 netif_receive_skb(skb);
baef58b1 3221
19a33d4e 3222 ++work_done;
5a011447 3223 }
baef58b1
SH		 3224 }
3225 ring->to_clean = e;
3226
baef58b1
SH		 3227 /* restart receiver */
3228 wmb();
a9cdab86 3229 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
baef58b1 3230
bea3348e
SH		 3231 if (work_done < to_do) {
3232 spin_lock_irq(&hw->hw_lock);
3233 __netif_rx_complete(dev, napi);
3234 hw->intr_mask |= napimask[skge->port];
3235 skge_write32(hw, B0_IMSK, hw->intr_mask);
3236 skge_read32(hw, B0_IMSK);
3237 spin_unlock_irq(&hw->hw_lock);
3238 }
1631aef1 3239
bea3348e 3240 return work_done;
baef58b1
SH		 3241}
3242
f6620cab
SH		 3243/* Parity errors seem to happen when Genesis is connected to a switch
3244 * with no other ports present. Heartbeat error??
3245 */
baef58b1
SH		 3246static void skge_mac_parity(struct skge_hw *hw, int port)
3247{
f6620cab
SH		 3248 struct net_device *dev = hw->dev[port];
3249
da00772f 3250 ++dev->stats.tx_heartbeat_errors;
baef58b1
SH		 3251
3252 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 3253 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 3254 MFF_CLR_PERR);
3255 else
3256 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 3257 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 3258 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 3259 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3260}
3261
baef58b1
SH		 3262static void skge_mac_intr(struct skge_hw *hw, int port)
3263{
95566065 3264 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 3265 genesis_mac_intr(hw, port);
3266 else
3267 yukon_mac_intr(hw, port);
3268}
3269
3270/* Handle device specific framing and timeout interrupts */
3271static void skge_error_irq(struct skge_hw *hw)
3272{
1479d13c 3273 struct pci_dev *pdev = hw->pdev;
baef58b1
SH		 3274 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3275
3276 if (hw->chip_id == CHIP_ID_GENESIS) {
3277 /* clear xmac errors */
3278 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
46a60f2d 3279 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
baef58b1 3280 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
46a60f2d 3281 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
baef58b1
SH		 3282 } else {
3283 /* Timestamp (unused) overflow */
3284 if (hwstatus & IS_IRQ_TIST_OV)
3285 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
baef58b1
SH		 3286 }
3287
3288 if (hwstatus & IS_RAM_RD_PAR) {
1479d13c 3289 dev_err(&pdev->dev, "Ram read data parity error\n");
baef58b1
SH		 3290 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3291 }
3292
3293 if (hwstatus & IS_RAM_WR_PAR) {
1479d13c 3294 dev_err(&pdev->dev, "Ram write data parity error\n");
baef58b1
SH		 3295 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3296 }
3297
3298 if (hwstatus & IS_M1_PAR_ERR)
3299 skge_mac_parity(hw, 0);
3300
3301 if (hwstatus & IS_M2_PAR_ERR)
3302 skge_mac_parity(hw, 1);
3303
b9d64acc 3304 if (hwstatus & IS_R1_PAR_ERR) {
1479d13c
SH		 3305 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3306 hw->dev[0]->name);
baef58b1 3307 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
b9d64acc 3308 }
baef58b1 3309
b9d64acc 3310 if (hwstatus & IS_R2_PAR_ERR) {
1479d13c
SH		 3311 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3312 hw->dev[1]->name);
baef58b1 3313 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
b9d64acc 3314 }
baef58b1
SH		 3315
3316 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
b9d64acc
SH		 3317 u16 pci_status, pci_cmd;
3318
1479d13c
SH		 3319 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3320 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
baef58b1 3321
1479d13c
SH		 3322 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3323 pci_cmd, pci_status);
b9d64acc
SH		 3324
3325 /* Write the error bits back to clear them. */
3326 pci_status &= PCI_STATUS_ERROR_BITS;
3327 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1479d13c 3328 pci_write_config_word(pdev, PCI_COMMAND,
b9d64acc 3329 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
1479d13c 3330 pci_write_config_word(pdev, PCI_STATUS, pci_status);
b9d64acc 3331 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1 3332
050ec18a 3333 /* if error still set then just ignore it */
baef58b1
SH		 3334 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3335 if (hwstatus & IS_IRQ_STAT) {
1479d13c 3336 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
baef58b1
SH		 3337 hw->intr_mask &= ~IS_HW_ERR;
3338 }
3339 }
3340}
3341
3342/*
9cbe330f 3343 * Interrupt from PHY are handled in tasklet (softirq)
baef58b1
SH		 3344 * because accessing phy registers requires spin wait which might
3345 * cause excess interrupt latency.
3346 */
9cbe330f 3347static void skge_extirq(unsigned long arg)
baef58b1 3348{
9cbe330f 3349 struct skge_hw *hw = (struct skge_hw *) arg;
baef58b1
SH		 3350 int port;
3351
cfc3ed79 3352 for (port = 0; port < hw->ports; port++) {
baef58b1
SH		 3353 struct net_device *dev = hw->dev[port];
3354
cfc3ed79 3355 if (netif_running(dev)) {
9cbe330f
SH		 3356 struct skge_port *skge = netdev_priv(dev);
3357
3358 spin_lock(&hw->phy_lock);
baef58b1
SH		 3359 if (hw->chip_id != CHIP_ID_GENESIS)
3360 yukon_phy_intr(skge);
64f6b64d 3361 else if (hw->phy_type == SK_PHY_BCOM)
45bada65 3362 bcom_phy_intr(skge);
9cbe330f 3363 spin_unlock(&hw->phy_lock);
baef58b1
SH		 3364 }
3365 }
baef58b1 3366
7c442fa1 3367 spin_lock_irq(&hw->hw_lock);
baef58b1
SH		 3368 hw->intr_mask |= IS_EXT_REG;
3369 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3370 skge_read32(hw, B0_IMSK);
7c442fa1 3371 spin_unlock_irq(&hw->hw_lock);
baef58b1
SH		 3372}
3373
7d12e780 3374static irqreturn_t skge_intr(int irq, void *dev_id)
baef58b1
SH		 3375{
3376 struct skge_hw *hw = dev_id;
cfc3ed79 3377 u32 status;
29365c90 3378 int handled = 0;
baef58b1 3379
29365c90 3380 spin_lock(&hw->hw_lock);
cfc3ed79
SH		 3381 /* Reading this register masks IRQ */
3382 status = skge_read32(hw, B0_SP_ISRC);
0486a8c8 3383 if (status == 0 || status == ~0)
29365c90 3384 goto out;
baef58b1 3385
29365c90 3386 handled = 1;
7c442fa1 3387 status &= hw->intr_mask;
cfc3ed79
SH		 3388 if (status & IS_EXT_REG) {
3389 hw->intr_mask &= ~IS_EXT_REG;
9cbe330f 3390 tasklet_schedule(&hw->phy_task);
cfc3ed79
SH		 3391 }
3392
513f533e 3393 if (status & (IS_XA1_F|IS_R1_F)) {
bea3348e 3394 struct skge_port *skge = netdev_priv(hw->dev[0]);
513f533e 3395 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
bea3348e 3396 netif_rx_schedule(hw->dev[0], &skge->napi);
baef58b1
SH		 3397 }
3398
7c442fa1
SH		 3399 if (status & IS_PA_TO_TX1)
3400 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
cfc3ed79 3401
d25f5a67 3402 if (status & IS_PA_TO_RX1) {
da00772f 3403 ++hw->dev[0]->stats.rx_over_errors;
7c442fa1 3404 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
d25f5a67
SH		 3405 }
3406
d25f5a67 3407
baef58b1
SH		 3408 if (status & IS_MAC1)
3409 skge_mac_intr(hw, 0);
95566065 3410
7c442fa1 3411 if (hw->dev[1]) {
bea3348e
SH		 3412 struct skge_port *skge = netdev_priv(hw->dev[1]);
3413
513f533e
SH		 3414 if (status & (IS_XA2_F|IS_R2_F)) {
3415 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
bea3348e 3416 netif_rx_schedule(hw->dev[1], &skge->napi);
7c442fa1
SH		 3417 }
3418
3419 if (status & IS_PA_TO_RX2) {
da00772f 3420 ++hw->dev[1]->stats.rx_over_errors;
7c442fa1
SH		 3421 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3422 }
3423
3424 if (status & IS_PA_TO_TX2)
3425 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3426
3427 if (status & IS_MAC2)
3428 skge_mac_intr(hw, 1);
3429 }
baef58b1
SH		 3430
3431 if (status & IS_HW_ERR)
3432 skge_error_irq(hw);
3433
7e676d91 3434 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3435 skge_read32(hw, B0_IMSK);
29365c90 3436out:
7c442fa1 3437 spin_unlock(&hw->hw_lock);
baef58b1 3438
29365c90 3439 return IRQ_RETVAL(handled);
baef58b1
SH		 3440}
3441
3442#ifdef CONFIG_NET_POLL_CONTROLLER
3443static void skge_netpoll(struct net_device *dev)
3444{
3445 struct skge_port *skge = netdev_priv(dev);
3446
3447 disable_irq(dev->irq);
7d12e780 3448 skge_intr(dev->irq, skge->hw);
baef58b1
SH		 3449 enable_irq(dev->irq);
3450}
3451#endif
3452
3453static int skge_set_mac_address(struct net_device *dev, void *p)
3454{
3455 struct skge_port *skge = netdev_priv(dev);
c2681dd8
SH		 3456 struct skge_hw *hw = skge->hw;
3457 unsigned port = skge->port;
3458 const struct sockaddr *addr = p;
2eb3e621 3459 u16 ctrl;
baef58b1
SH		 3460
3461 if (!is_valid_ether_addr(addr->sa_data))
3462 return -EADDRNOTAVAIL;
3463
baef58b1 3464 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
c2681dd8 3465
9cbe330f
SH		 3466 if (!netif_running(dev)) {
3467 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3468 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3469 } else {
3470 /* disable Rx */
3471 spin_lock_bh(&hw->phy_lock);
3472 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3473 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
2eb3e621 3474
9cbe330f
SH		 3475 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3476 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
2eb3e621 3477
2eb3e621
SH		 3478 if (hw->chip_id == CHIP_ID_GENESIS)
3479 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3480 else {
3481 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3482 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3483 }
2eb3e621 3484
9cbe330f
SH		 3485 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3486 spin_unlock_bh(&hw->phy_lock);
3487 }
c2681dd8
SH		 3488
3489 return 0;
baef58b1
SH		 3490}
3491
3492static const struct {
3493 u8 id;
3494 const char *name;
3495} skge_chips[] = {
3496 { CHIP_ID_GENESIS, "Genesis" },
3497 { CHIP_ID_YUKON, "Yukon" },
3498 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3499 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 3500};
3501
3502static const char *skge_board_name(const struct skge_hw *hw)
3503{
3504 int i;
3505 static char buf[16];
3506
3507 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3508 if (skge_chips[i].id == hw->chip_id)
3509 return skge_chips[i].name;
3510
3511 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3512 return buf;
3513}
3514
3515
3516/*
3517 * Setup the board data structure, but don't bring up
3518 * the port(s)
3519 */
3520static int skge_reset(struct skge_hw *hw)
3521{
adba9e23 3522 u32 reg;
b9d64acc 3523 u16 ctst, pci_status;
64f6b64d 3524 u8 t8, mac_cfg, pmd_type;
981d0377 3525 int i;
baef58b1
SH		 3526
3527 ctst = skge_read16(hw, B0_CTST);
3528
3529 /* do a SW reset */
3530 skge_write8(hw, B0_CTST, CS_RST_SET);
3531 skge_write8(hw, B0_CTST, CS_RST_CLR);
3532
3533 /* clear PCI errors, if any */
b9d64acc
SH		 3534 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3535 skge_write8(hw, B2_TST_CTRL2, 0);
baef58b1 3536
b9d64acc
SH		 3537 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3538 pci_write_config_word(hw->pdev, PCI_STATUS,
3539 pci_status | PCI_STATUS_ERROR_BITS);
3540 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1
SH		 3541 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3542
3543 /* restore CLK_RUN bits (for Yukon-Lite) */
3544 skge_write16(hw, B0_CTST,
3545 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3546
3547 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
64f6b64d 3548 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
5e1705dd
SH		 3549 pmd_type = skge_read8(hw, B2_PMD_TYP);
3550 hw->copper = (pmd_type == 'T' || pmd_type == '1');
baef58b1 3551
95566065 3552 switch (hw->chip_id) {
baef58b1 3553 case CHIP_ID_GENESIS:
64f6b64d
SH		 3554 switch (hw->phy_type) {
3555 case SK_PHY_XMAC:
3556 hw->phy_addr = PHY_ADDR_XMAC;
3557 break;
baef58b1
SH		 3558 case SK_PHY_BCOM:
3559 hw->phy_addr = PHY_ADDR_BCOM;
3560 break;
3561 default:
1479d13c
SH		 3562 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3563 hw->phy_type);
baef58b1
SH		 3564 return -EOPNOTSUPP;
3565 }
3566 break;
3567
3568 case CHIP_ID_YUKON:
3569 case CHIP_ID_YUKON_LITE:
3570 case CHIP_ID_YUKON_LP:
64f6b64d 3571 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
5e1705dd 3572 hw->copper = 1;
baef58b1
SH		 3573
3574 hw->phy_addr = PHY_ADDR_MARV;
baef58b1
SH		 3575 break;
3576
3577 default:
1479d13c
SH		 3578 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3579 hw->chip_id);
baef58b1
SH		 3580 return -EOPNOTSUPP;
3581 }
3582
981d0377
SH		 3583 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3584 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3585 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 3586
3587 /* read the adapters RAM size */
3588 t8 = skge_read8(hw, B2_E_0);
3589 if (hw->chip_id == CHIP_ID_GENESIS) {
3590 if (t8 == 3) {
3591 /* special case: 4 x 64k x 36, offset = 0x80000 */
7fb7ac24
SH		 3592 hw->ram_size = 1024;
3593 hw->ram_offset = 512;
baef58b1
SH		 3594 } else
3595 hw->ram_size = t8 * 512;
7fb7ac24
SH		 3596 } else /* Yukon */
3597 hw->ram_size = t8 ? t8 * 4 : 128;
baef58b1 3598
4ebabfcb 3599 hw->intr_mask = IS_HW_ERR;
cfc3ed79 3600
4ebabfcb 3601 /* Use PHY IRQ for all but fiber based Genesis board */
64f6b64d
SH		 3602 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3603 hw->intr_mask |= IS_EXT_REG;
3604
baef58b1
SH		 3605 if (hw->chip_id == CHIP_ID_GENESIS)
3606 genesis_init(hw);
3607 else {
3608 /* switch power to VCC (WA for VAUX problem) */
3609 skge_write8(hw, B0_POWER_CTRL,
3610 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
adba9e23 3611
050ec18a
SH		 3612 /* avoid boards with stuck Hardware error bits */
3613 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3614 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
1479d13c 3615 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
050ec18a
SH		 3616 hw->intr_mask &= ~IS_HW_ERR;
3617 }
3618
adba9e23
SH		 3619 /* Clear PHY COMA */
3620 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3621 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3622 reg &= ~PCI_PHY_COMA;
3623 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3624 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3625
3626
981d0377 3627 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 3628 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3629 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 3630 }
3631 }
3632
3633 /* turn off hardware timer (unused) */
3634 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3635 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3636 skge_write8(hw, B0_LED, LED_STAT_ON);
3637
3638 /* enable the Tx Arbiters */
981d0377 3639 for (i = 0; i < hw->ports; i++)
6b0c1480 3640 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 3641
3642 /* Initialize ram interface */
3643 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3644
3645 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3646 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3647 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3648 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3649 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3650 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3651 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3652 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3653 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3654 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3655 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3656 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3657
3658 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3659
3660 /* Set interrupt moderation for Transmit only
3661 * Receive interrupts avoided by NAPI
3662 */
3663 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3664 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3665 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3666
baef58b1
SH		 3667 skge_write32(hw, B0_IMSK, hw->intr_mask);
3668
981d0377 3669 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3670 if (hw->chip_id == CHIP_ID_GENESIS)
3671 genesis_reset(hw, i);
3672 else
3673 yukon_reset(hw, i);
3674 }
baef58b1
SH		 3675
3676 return 0;
3677}
3678
3679/* Initialize network device */
981d0377
SH		 3680static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3681 int highmem)
baef58b1
SH		 3682{
3683 struct skge_port *skge;
3684 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3685
3686 if (!dev) {
1479d13c 3687 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
baef58b1
SH		 3688 return NULL;
3689 }
3690
baef58b1
SH		 3691 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3692 dev->open = skge_up;
3693 dev->stop = skge_down;
2cd8e5d3 3694 dev->do_ioctl = skge_ioctl;
baef58b1
SH		 3695 dev->hard_start_xmit = skge_xmit_frame;
3696 dev->get_stats = skge_get_stats;
3697 if (hw->chip_id == CHIP_ID_GENESIS)
3698 dev->set_multicast_list = genesis_set_multicast;
3699 else
3700 dev->set_multicast_list = yukon_set_multicast;
3701
3702 dev->set_mac_address = skge_set_mac_address;
3703 dev->change_mtu = skge_change_mtu;
3704 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3705 dev->tx_timeout = skge_tx_timeout;
3706 dev->watchdog_timeo = TX_WATCHDOG;
baef58b1
SH		 3707#ifdef CONFIG_NET_POLL_CONTROLLER
3708 dev->poll_controller = skge_netpoll;
3709#endif
3710 dev->irq = hw->pdev->irq;
513f533e 3711
981d0377
SH		 3712 if (highmem)
3713 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3714
3715 skge = netdev_priv(dev);
bea3348e 3716 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
baef58b1
SH		 3717 skge->netdev = dev;
3718 skge->hw = hw;
3719 skge->msg_enable = netif_msg_init(debug, default_msg);
9cbe330f 3720
baef58b1
SH		 3721 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3722 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3723
3724 /* Auto speed and flow control */
3725 skge->autoneg = AUTONEG_ENABLE;
5d5c8e03 3726 skge->flow_control = FLOW_MODE_SYM_OR_REM;
baef58b1
SH		 3727 skge->duplex = -1;
3728 skge->speed = -1;
31b619c5 3729 skge->advertising = skge_supported_modes(hw);
5b982c5b
SH		 3730
3731 if (pci_wake_enabled(hw->pdev))
3732 skge->wol = wol_supported(hw) & WAKE_MAGIC;
baef58b1
SH		 3733
3734 hw->dev[port] = dev;
3735
3736 skge->port = port;
3737
64f6b64d 3738 /* Only used for Genesis XMAC */
9cbe330f 3739 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
64f6b64d 3740
baef58b1
SH		 3741 if (hw->chip_id != CHIP_ID_GENESIS) {
3742 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3743 skge->rx_csum = 1;
3744 }
3745
3746 /* read the mac address */
3747 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
56230d53 3748 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
baef58b1
SH		 3749
3750 /* device is off until link detection */
3751 netif_carrier_off(dev);
3752 netif_stop_queue(dev);
3753
3754 return dev;
3755}
3756
3757static void __devinit skge_show_addr(struct net_device *dev)
3758{
3759 const struct skge_port *skge = netdev_priv(dev);
0795af57 3760 DECLARE_MAC_BUF(mac);
baef58b1
SH		 3761
3762 if (netif_msg_probe(skge))
0795af57
JP		 3763 printk(KERN_INFO PFX "%s: addr %s\n",
3764 dev->name, print_mac(mac, dev->dev_addr));
baef58b1
SH		 3765}
3766
3767static int __devinit skge_probe(struct pci_dev *pdev,
3768 const struct pci_device_id *ent)
3769{
3770 struct net_device *dev, *dev1;
3771 struct skge_hw *hw;
3772 int err, using_dac = 0;
3773
203babb6
SH		 3774 err = pci_enable_device(pdev);
3775 if (err) {
1479d13c 3776 dev_err(&pdev->dev, "cannot enable PCI device\n");
baef58b1
SH		 3777 goto err_out;
3778 }
3779
203babb6
SH		 3780 err = pci_request_regions(pdev, DRV_NAME);
3781 if (err) {
1479d13c 3782 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
baef58b1
SH		 3783 goto err_out_disable_pdev;
3784 }
3785
3786 pci_set_master(pdev);
3787
93aea718 3788 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
baef58b1 3789 using_dac = 1;
77783a78 3790 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
93aea718
SH		 3791 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3792 using_dac = 0;
3793 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3794 }
3795
3796 if (err) {
1479d13c 3797 dev_err(&pdev->dev, "no usable DMA configuration\n");
93aea718 3798 goto err_out_free_regions;
baef58b1
SH		 3799 }
3800
3801#ifdef __BIG_ENDIAN
8f3f8193 3802 /* byte swap descriptors in hardware */
baef58b1
SH		 3803 {
3804 u32 reg;
3805
3806 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3807 reg |= PCI_REV_DESC;
3808 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3809 }
3810#endif
3811
3812 err = -ENOMEM;
7e863061 3813 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
baef58b1 3814 if (!hw) {
1479d13c 3815 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
baef58b1
SH		 3816 goto err_out_free_regions;
3817 }
3818
baef58b1 3819 hw->pdev = pdev;
d38efdd6 3820 spin_lock_init(&hw->hw_lock);
9cbe330f
SH		 3821 spin_lock_init(&hw->phy_lock);
3822 tasklet_init(&hw->phy_task, &skge_extirq, (unsigned long) hw);
baef58b1
SH		 3823
3824 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3825 if (!hw->regs) {
1479d13c 3826 dev_err(&pdev->dev, "cannot map device registers\n");
baef58b1
SH		 3827 goto err_out_free_hw;
3828 }
3829
baef58b1
SH		 3830 err = skge_reset(hw);
3831 if (err)
ccdaa2a9 3832 goto err_out_iounmap;
baef58b1 3833
7c7459d1
GKH		 3834 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3835 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
981d0377 3836 skge_board_name(hw), hw->chip_rev);
baef58b1 3837
ccdaa2a9
SH		 3838 dev = skge_devinit(hw, 0, using_dac);
3839 if (!dev)
baef58b1
SH		 3840 goto err_out_led_off;
3841
fae87592 3842 /* Some motherboards are broken and has zero in ROM. */
1479d13c
SH		 3843 if (!is_valid_ether_addr(dev->dev_addr))
3844 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
631ae320 3845
203babb6
SH		 3846 err = register_netdev(dev);
3847 if (err) {
1479d13c 3848 dev_err(&pdev->dev, "cannot register net device\n");
baef58b1
SH		 3849 goto err_out_free_netdev;
3850 }
3851
ccdaa2a9
SH		 3852 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3853 if (err) {
1479d13c 3854 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
ccdaa2a9
SH		 3855 dev->name, pdev->irq);
3856 goto err_out_unregister;
3857 }
baef58b1
SH		 3858 skge_show_addr(dev);
3859
981d0377 3860 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
baef58b1
SH		 3861 if (register_netdev(dev1) == 0)
3862 skge_show_addr(dev1);
3863 else {
3864 /* Failure to register second port need not be fatal */
1479d13c 3865 dev_warn(&pdev->dev, "register of second port failed\n");
baef58b1
SH		 3866 hw->dev[1] = NULL;
3867 free_netdev(dev1);
3868 }
3869 }
ccdaa2a9 3870 pci_set_drvdata(pdev, hw);
baef58b1
SH		 3871
3872 return 0;
3873
ccdaa2a9
SH		 3874err_out_unregister:
3875 unregister_netdev(dev);
baef58b1
SH		 3876err_out_free_netdev:
3877 free_netdev(dev);
3878err_out_led_off:
3879 skge_write16(hw, B0_LED, LED_STAT_OFF);
baef58b1
SH		 3880err_out_iounmap:
3881 iounmap(hw->regs);
3882err_out_free_hw:
3883 kfree(hw);
3884err_out_free_regions:
3885 pci_release_regions(pdev);
3886err_out_disable_pdev:
3887 pci_disable_device(pdev);
3888 pci_set_drvdata(pdev, NULL);
3889err_out:
3890 return err;
3891}
3892
3893static void __devexit skge_remove(struct pci_dev *pdev)
3894{
3895 struct skge_hw *hw = pci_get_drvdata(pdev);
3896 struct net_device *dev0, *dev1;
3897
95566065 3898 if (!hw)
baef58b1
SH		 3899 return;
3900
208491d8
SH		 3901 flush_scheduled_work();
3902
baef58b1
SH		 3903 if ((dev1 = hw->dev[1]))
3904 unregister_netdev(dev1);
3905 dev0 = hw->dev[0];
3906 unregister_netdev(dev0);
3907
9cbe330f
SH		 3908 tasklet_disable(&hw->phy_task);
3909
7c442fa1
SH		 3910 spin_lock_irq(&hw->hw_lock);
3911 hw->intr_mask = 0;
46a60f2d 3912 skge_write32(hw, B0_IMSK, 0);
78bc2186 3913 skge_read32(hw, B0_IMSK);
7c442fa1
SH		 3914 spin_unlock_irq(&hw->hw_lock);
3915
46a60f2d 3916 skge_write16(hw, B0_LED, LED_STAT_OFF);
46a60f2d
SH		 3917 skge_write8(hw, B0_CTST, CS_RST_SET);
3918
baef58b1
SH		 3919 free_irq(pdev->irq, hw);
3920 pci_release_regions(pdev);
3921 pci_disable_device(pdev);
3922 if (dev1)
3923 free_netdev(dev1);
3924 free_netdev(dev0);
46a60f2d 3925
baef58b1
SH		 3926 iounmap(hw->regs);
3927 kfree(hw);
3928 pci_set_drvdata(pdev, NULL);
3929}
3930
3931#ifdef CONFIG_PM
2a569579 3932static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
baef58b1
SH		 3933{
3934 struct skge_hw *hw = pci_get_drvdata(pdev);
a504e64a
SH		 3935 int i, err, wol = 0;
3936
e3b7df17
SH		 3937 if (!hw)
3938 return 0;
3939
a504e64a
SH		 3940 err = pci_save_state(pdev);
3941 if (err)
3942 return err;
baef58b1 3943
d38efdd6 3944 for (i = 0; i < hw->ports; i++) {
baef58b1 3945 struct net_device *dev = hw->dev[i];
a504e64a 3946 struct skge_port *skge = netdev_priv(dev);
baef58b1 3947
a504e64a
SH		 3948 if (netif_running(dev))
3949 skge_down(dev);
3950 if (skge->wol)
3951 skge_wol_init(skge);
d38efdd6 3952
a504e64a 3953 wol |= skge->wol;
baef58b1
SH		 3954 }
3955
d38efdd6 3956 skge_write32(hw, B0_IMSK, 0);
2a569579 3957 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
baef58b1
SH		 3958 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3959
3960 return 0;
3961}
3962
3963static int skge_resume(struct pci_dev *pdev)
3964{
3965 struct skge_hw *hw = pci_get_drvdata(pdev);
d38efdd6 3966 int i, err;
baef58b1 3967
e3b7df17
SH		 3968 if (!hw)
3969 return 0;
3970
a504e64a
SH		 3971 err = pci_set_power_state(pdev, PCI_D0);
3972 if (err)
3973 goto out;
3974
3975 err = pci_restore_state(pdev);
3976 if (err)
3977 goto out;
3978
baef58b1
SH		 3979 pci_enable_wake(pdev, PCI_D0, 0);
3980
d38efdd6
SH		 3981 err = skge_reset(hw);
3982 if (err)
3983 goto out;
baef58b1 3984
d38efdd6 3985 for (i = 0; i < hw->ports; i++) {
baef58b1 3986 struct net_device *dev = hw->dev[i];
d38efdd6 3987
d38efdd6
SH		 3988 if (netif_running(dev)) {
3989 err = skge_up(dev);
3990
3991 if (err) {
3992 printk(KERN_ERR PFX "%s: could not up: %d\n",
3993 dev->name, err);
edd702e8 3994 dev_close(dev);
d38efdd6
SH		 3995 goto out;
3996 }
baef58b1
SH		 3997 }
3998 }
d38efdd6
SH		 3999out:
4000 return err;
baef58b1
SH		 4001}
4002#endif
4003
692412b3
SH		 4004static void skge_shutdown(struct pci_dev *pdev)
4005{
4006 struct skge_hw *hw = pci_get_drvdata(pdev);
4007 int i, wol = 0;
4008
e3b7df17
SH		 4009 if (!hw)
4010 return;
4011
692412b3
SH		 4012 for (i = 0; i < hw->ports; i++) {
4013 struct net_device *dev = hw->dev[i];
4014 struct skge_port *skge = netdev_priv(dev);
4015
4016 if (skge->wol)
4017 skge_wol_init(skge);
4018 wol |= skge->wol;
4019 }
4020
4021 pci_enable_wake(pdev, PCI_D3hot, wol);
4022 pci_enable_wake(pdev, PCI_D3cold, wol);
4023
4024 pci_disable_device(pdev);
4025 pci_set_power_state(pdev, PCI_D3hot);
4026
4027}
4028
baef58b1
SH		 4029static struct pci_driver skge_driver = {
4030 .name = DRV_NAME,
4031 .id_table = skge_id_table,
4032 .probe = skge_probe,
4033 .remove = __devexit_p(skge_remove),
4034#ifdef CONFIG_PM
4035 .suspend = skge_suspend,
4036 .resume = skge_resume,
4037#endif
692412b3 4038 .shutdown = skge_shutdown,
baef58b1
SH		 4039};
4040
4041static int __init skge_init_module(void)
4042{
29917620 4043 return pci_register_driver(&skge_driver);
baef58b1
SH		 4044}
4045
4046static void __exit skge_cleanup_module(void)
4047{
4048 pci_unregister_driver(&skge_driver);
4049}
4050
4051module_init(skge_init_module);
4052module_exit(skge_cleanup_module);
Linux kernel - Deliverables
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