Commit | Line | Data |
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cd28ab6a SH |
1 | /* |
2 | * New driver for Marvell Yukon 2 chipset. | |
3 | * Based on earlier sk98lin, and skge driver. | |
4 | * | |
5 | * This driver intentionally does not support all the features | |
6 | * of the original driver such as link fail-over and link management because | |
7 | * those should be done at higher levels. | |
8 | * | |
9 | * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
793b883e | 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
cd28ab6a SH |
19 | * GNU General Public License for more details. |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | */ | |
25 | ||
793b883e | 26 | #include <linux/crc32.h> |
cd28ab6a SH |
27 | #include <linux/kernel.h> |
28 | #include <linux/version.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/netdevice.h> | |
d0bbccfa | 31 | #include <linux/dma-mapping.h> |
cd28ab6a SH |
32 | #include <linux/etherdevice.h> |
33 | #include <linux/ethtool.h> | |
34 | #include <linux/pci.h> | |
35 | #include <linux/ip.h> | |
36 | #include <linux/tcp.h> | |
37 | #include <linux/in.h> | |
38 | #include <linux/delay.h> | |
91c86df5 | 39 | #include <linux/workqueue.h> |
d1f13708 | 40 | #include <linux/if_vlan.h> |
d70cd51a | 41 | #include <linux/prefetch.h> |
ef743d33 | 42 | #include <linux/mii.h> |
cd28ab6a SH |
43 | |
44 | #include <asm/irq.h> | |
45 | ||
d1f13708 | 46 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) |
47 | #define SKY2_VLAN_TAG_USED 1 | |
48 | #endif | |
49 | ||
cd28ab6a SH |
50 | #include "sky2.h" |
51 | ||
52 | #define DRV_NAME "sky2" | |
e981d47b | 53 | #define DRV_VERSION "1.7" |
cd28ab6a SH |
54 | #define PFX DRV_NAME " " |
55 | ||
56 | /* | |
57 | * The Yukon II chipset takes 64 bit command blocks (called list elements) | |
58 | * that are organized into three (receive, transmit, status) different rings | |
59 | * similar to Tigon3. A transmit can require several elements; | |
60 | * a receive requires one (or two if using 64 bit dma). | |
61 | */ | |
62 | ||
13210ce5 | 63 | #define RX_LE_SIZE 512 |
cd28ab6a | 64 | #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) |
bea86103 | 65 | #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2) |
13210ce5 | 66 | #define RX_DEF_PENDING RX_MAX_PENDING |
82788c7a | 67 | #define RX_SKB_ALIGN 8 |
22e11703 | 68 | #define RX_BUF_WRITE 16 |
793b883e SH |
69 | |
70 | #define TX_RING_SIZE 512 | |
71 | #define TX_DEF_PENDING (TX_RING_SIZE - 1) | |
72 | #define TX_MIN_PENDING 64 | |
b19666d9 | 73 | #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS) |
cd28ab6a | 74 | |
793b883e | 75 | #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */ |
cd28ab6a SH |
76 | #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le)) |
77 | #define ETH_JUMBO_MTU 9000 | |
78 | #define TX_WATCHDOG (5 * HZ) | |
79 | #define NAPI_WEIGHT 64 | |
80 | #define PHY_RETRIES 1000 | |
81 | ||
cb5d9547 SH |
82 | #define RING_NEXT(x,s) (((x)+1) & ((s)-1)) |
83 | ||
cd28ab6a | 84 | static const u32 default_msg = |
793b883e SH |
85 | NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
86 | | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR | |
3be92a70 | 87 | | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN; |
cd28ab6a | 88 | |
793b883e | 89 | static int debug = -1; /* defaults above */ |
cd28ab6a SH |
90 | module_param(debug, int, 0); |
91 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
92 | ||
bdb5c58e SH |
93 | static int copybreak __read_mostly = 256; |
94 | module_param(copybreak, int, 0); | |
95 | MODULE_PARM_DESC(copybreak, "Receive copy threshold"); | |
96 | ||
fb2690a9 SH |
97 | static int disable_msi = 0; |
98 | module_param(disable_msi, int, 0); | |
99 | MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); | |
100 | ||
01bd7564 SH |
101 | static int idle_timeout = 100; |
102 | module_param(idle_timeout, int, 0); | |
103 | MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)"); | |
104 | ||
cd28ab6a | 105 | static const struct pci_device_id sky2_id_table[] = { |
793b883e | 106 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, |
cd28ab6a | 107 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, |
2d2a3871 | 108 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */ |
2f4a66ad | 109 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */ |
cd28ab6a SH |
110 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, |
111 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, | |
112 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, | |
113 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, | |
114 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, | |
115 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, | |
116 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, | |
117 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, | |
118 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, | |
119 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, | |
5a5b1ea0 | 120 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, |
2f4a66ad | 121 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, |
cd28ab6a SH |
122 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, |
123 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, | |
124 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, | |
5a5b1ea0 | 125 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, |
5f5d83fd | 126 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, |
57fa442c SH |
127 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, |
128 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, | |
129 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, | |
130 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, | |
2f4a66ad | 131 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, |
cd28ab6a SH |
132 | { 0 } |
133 | }; | |
793b883e | 134 | |
cd28ab6a SH |
135 | MODULE_DEVICE_TABLE(pci, sky2_id_table); |
136 | ||
137 | /* Avoid conditionals by using array */ | |
138 | static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; | |
139 | static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; | |
f4ea431b | 140 | static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 }; |
cd28ab6a | 141 | |
92f965e8 SH |
142 | /* This driver supports yukon2 chipset only */ |
143 | static const char *yukon2_name[] = { | |
144 | "XL", /* 0xb3 */ | |
145 | "EC Ultra", /* 0xb4 */ | |
146 | "UNKNOWN", /* 0xb5 */ | |
147 | "EC", /* 0xb6 */ | |
148 | "FE", /* 0xb7 */ | |
793b883e SH |
149 | }; |
150 | ||
793b883e | 151 | /* Access to external PHY */ |
ef743d33 | 152 | static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) |
cd28ab6a SH |
153 | { |
154 | int i; | |
155 | ||
156 | gma_write16(hw, port, GM_SMI_DATA, val); | |
157 | gma_write16(hw, port, GM_SMI_CTRL, | |
158 | GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); | |
159 | ||
160 | for (i = 0; i < PHY_RETRIES; i++) { | |
cd28ab6a | 161 | if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) |
ef743d33 | 162 | return 0; |
793b883e | 163 | udelay(1); |
cd28ab6a | 164 | } |
ef743d33 | 165 | |
793b883e | 166 | printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name); |
ef743d33 | 167 | return -ETIMEDOUT; |
cd28ab6a SH |
168 | } |
169 | ||
ef743d33 | 170 | static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) |
cd28ab6a SH |
171 | { |
172 | int i; | |
173 | ||
793b883e | 174 | gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) |
cd28ab6a SH |
175 | | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); |
176 | ||
177 | for (i = 0; i < PHY_RETRIES; i++) { | |
ef743d33 | 178 | if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) { |
179 | *val = gma_read16(hw, port, GM_SMI_DATA); | |
180 | return 0; | |
181 | } | |
182 | ||
793b883e | 183 | udelay(1); |
cd28ab6a SH |
184 | } |
185 | ||
ef743d33 | 186 | return -ETIMEDOUT; |
187 | } | |
188 | ||
189 | static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) | |
190 | { | |
191 | u16 v; | |
192 | ||
193 | if (__gm_phy_read(hw, port, reg, &v) != 0) | |
194 | printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name); | |
195 | return v; | |
cd28ab6a SH |
196 | } |
197 | ||
2ccc99b7 | 198 | static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state) |
5afa0a9c | 199 | { |
200 | u16 power_control; | |
5afa0a9c | 201 | int vaux; |
5afa0a9c | 202 | |
203 | pr_debug("sky2_set_power_state %d\n", state); | |
204 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
205 | ||
56a645cc | 206 | power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC); |
08c06d8a | 207 | vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) && |
5afa0a9c | 208 | (power_control & PCI_PM_CAP_PME_D3cold); |
209 | ||
56a645cc | 210 | power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL); |
5afa0a9c | 211 | |
212 | power_control |= PCI_PM_CTRL_PME_STATUS; | |
213 | power_control &= ~(PCI_PM_CTRL_STATE_MASK); | |
214 | ||
215 | switch (state) { | |
216 | case PCI_D0: | |
217 | /* switch power to VCC (WA for VAUX problem) */ | |
218 | sky2_write8(hw, B0_POWER_CTRL, | |
219 | PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); | |
220 | ||
221 | /* disable Core Clock Division, */ | |
222 | sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); | |
223 | ||
224 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | |
225 | /* enable bits are inverted */ | |
226 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
227 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
228 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
229 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
230 | else | |
231 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | |
232 | ||
977bdf06 | 233 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { |
d3bcfbeb | 234 | u32 reg1; |
235 | ||
56a645cc SH |
236 | sky2_pci_write32(hw, PCI_DEV_REG3, 0); |
237 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG4); | |
977bdf06 | 238 | reg1 &= P_ASPM_CONTROL_MSK; |
56a645cc SH |
239 | sky2_pci_write32(hw, PCI_DEV_REG4, reg1); |
240 | sky2_pci_write32(hw, PCI_DEV_REG5, 0); | |
977bdf06 SH |
241 | } |
242 | ||
5afa0a9c | 243 | break; |
244 | ||
245 | case PCI_D3hot: | |
246 | case PCI_D3cold: | |
5afa0a9c | 247 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) |
248 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | |
249 | else | |
250 | /* enable bits are inverted */ | |
251 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
252 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
253 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
254 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
255 | ||
256 | /* switch power to VAUX */ | |
257 | if (vaux && state != PCI_D3cold) | |
258 | sky2_write8(hw, B0_POWER_CTRL, | |
259 | (PC_VAUX_ENA | PC_VCC_ENA | | |
260 | PC_VAUX_ON | PC_VCC_OFF)); | |
261 | break; | |
262 | default: | |
263 | printk(KERN_ERR PFX "Unknown power state %d\n", state); | |
5afa0a9c | 264 | } |
265 | ||
56a645cc | 266 | sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control); |
5afa0a9c | 267 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
5afa0a9c | 268 | } |
269 | ||
d3bcfbeb | 270 | static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port) |
cd28ab6a SH |
271 | { |
272 | u16 reg; | |
273 | ||
274 | /* disable all GMAC IRQ's */ | |
275 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); | |
276 | /* disable PHY IRQs */ | |
277 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
793b883e | 278 | |
cd28ab6a SH |
279 | gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ |
280 | gma_write16(hw, port, GM_MC_ADDR_H2, 0); | |
281 | gma_write16(hw, port, GM_MC_ADDR_H3, 0); | |
282 | gma_write16(hw, port, GM_MC_ADDR_H4, 0); | |
283 | ||
284 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
285 | reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; | |
286 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
287 | } | |
288 | ||
289 | static void sky2_phy_init(struct sky2_hw *hw, unsigned port) | |
290 | { | |
291 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
793b883e | 292 | u16 ctrl, ct1000, adv, pg, ledctrl, ledover; |
cd28ab6a | 293 | |
ed6d32c7 | 294 | if (sky2->autoneg == AUTONEG_ENABLE && |
86a31a75 | 295 | !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) { |
cd28ab6a SH |
296 | u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); |
297 | ||
298 | ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | | |
793b883e | 299 | PHY_M_EC_MAC_S_MSK); |
cd28ab6a SH |
300 | ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); |
301 | ||
302 | if (hw->chip_id == CHIP_ID_YUKON_EC) | |
303 | ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; | |
304 | else | |
305 | ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3); | |
306 | ||
307 | gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); | |
308 | } | |
309 | ||
310 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
311 | if (hw->copper) { | |
312 | if (hw->chip_id == CHIP_ID_YUKON_FE) { | |
313 | /* enable automatic crossover */ | |
314 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; | |
315 | } else { | |
316 | /* disable energy detect */ | |
317 | ctrl &= ~PHY_M_PC_EN_DET_MSK; | |
318 | ||
319 | /* enable automatic crossover */ | |
320 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); | |
321 | ||
322 | if (sky2->autoneg == AUTONEG_ENABLE && | |
ed6d32c7 | 323 | (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) { |
cd28ab6a SH |
324 | ctrl &= ~PHY_M_PC_DSC_MSK; |
325 | ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; | |
326 | } | |
327 | } | |
328 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
329 | } else { | |
330 | /* workaround for deviation #4.88 (CRC errors) */ | |
331 | /* disable Automatic Crossover */ | |
332 | ||
333 | ctrl &= ~PHY_M_PC_MDIX_MSK; | |
334 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
335 | ||
336 | if (hw->chip_id == CHIP_ID_YUKON_XL) { | |
337 | /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ | |
338 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); | |
339 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
340 | ctrl &= ~PHY_M_MAC_MD_MSK; | |
341 | ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); | |
342 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
343 | ||
344 | /* select page 1 to access Fiber registers */ | |
345 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); | |
346 | } | |
cd28ab6a SH |
347 | } |
348 | ||
349 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); | |
350 | if (sky2->autoneg == AUTONEG_DISABLE) | |
351 | ctrl &= ~PHY_CT_ANE; | |
352 | else | |
353 | ctrl |= PHY_CT_ANE; | |
354 | ||
355 | ctrl |= PHY_CT_RESET; | |
356 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
357 | ||
358 | ctrl = 0; | |
359 | ct1000 = 0; | |
360 | adv = PHY_AN_CSMA; | |
361 | ||
362 | if (sky2->autoneg == AUTONEG_ENABLE) { | |
363 | if (hw->copper) { | |
364 | if (sky2->advertising & ADVERTISED_1000baseT_Full) | |
365 | ct1000 |= PHY_M_1000C_AFD; | |
366 | if (sky2->advertising & ADVERTISED_1000baseT_Half) | |
367 | ct1000 |= PHY_M_1000C_AHD; | |
368 | if (sky2->advertising & ADVERTISED_100baseT_Full) | |
369 | adv |= PHY_M_AN_100_FD; | |
370 | if (sky2->advertising & ADVERTISED_100baseT_Half) | |
371 | adv |= PHY_M_AN_100_HD; | |
372 | if (sky2->advertising & ADVERTISED_10baseT_Full) | |
373 | adv |= PHY_M_AN_10_FD; | |
374 | if (sky2->advertising & ADVERTISED_10baseT_Half) | |
375 | adv |= PHY_M_AN_10_HD; | |
793b883e | 376 | } else /* special defines for FIBER (88E1011S only) */ |
cd28ab6a SH |
377 | adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD; |
378 | ||
379 | /* Set Flow-control capabilities */ | |
380 | if (sky2->tx_pause && sky2->rx_pause) | |
793b883e | 381 | adv |= PHY_AN_PAUSE_CAP; /* symmetric */ |
cd28ab6a | 382 | else if (sky2->rx_pause && !sky2->tx_pause) |
793b883e | 383 | adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP; |
cd28ab6a SH |
384 | else if (!sky2->rx_pause && sky2->tx_pause) |
385 | adv |= PHY_AN_PAUSE_ASYM; /* local */ | |
386 | ||
387 | /* Restart Auto-negotiation */ | |
388 | ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; | |
389 | } else { | |
390 | /* forced speed/duplex settings */ | |
391 | ct1000 = PHY_M_1000C_MSE; | |
392 | ||
393 | if (sky2->duplex == DUPLEX_FULL) | |
394 | ctrl |= PHY_CT_DUP_MD; | |
395 | ||
396 | switch (sky2->speed) { | |
397 | case SPEED_1000: | |
398 | ctrl |= PHY_CT_SP1000; | |
399 | break; | |
400 | case SPEED_100: | |
401 | ctrl |= PHY_CT_SP100; | |
402 | break; | |
403 | } | |
404 | ||
405 | ctrl |= PHY_CT_RESET; | |
406 | } | |
407 | ||
408 | if (hw->chip_id != CHIP_ID_YUKON_FE) | |
409 | gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); | |
410 | ||
411 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); | |
412 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
413 | ||
414 | /* Setup Phy LED's */ | |
415 | ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); | |
416 | ledover = 0; | |
417 | ||
418 | switch (hw->chip_id) { | |
419 | case CHIP_ID_YUKON_FE: | |
420 | /* on 88E3082 these bits are at 11..9 (shifted left) */ | |
421 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; | |
422 | ||
423 | ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); | |
424 | ||
425 | /* delete ACT LED control bits */ | |
426 | ctrl &= ~PHY_M_FELP_LED1_MSK; | |
427 | /* change ACT LED control to blink mode */ | |
428 | ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); | |
429 | gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); | |
430 | break; | |
431 | ||
432 | case CHIP_ID_YUKON_XL: | |
793b883e | 433 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
cd28ab6a SH |
434 | |
435 | /* select page 3 to access LED control register */ | |
436 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
437 | ||
438 | /* set LED Function Control register */ | |
ed6d32c7 SH |
439 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, |
440 | (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ | |
441 | PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ | |
442 | PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ | |
443 | PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ | |
cd28ab6a SH |
444 | |
445 | /* set Polarity Control register */ | |
446 | gm_phy_write(hw, port, PHY_MARV_PHY_STAT, | |
793b883e SH |
447 | (PHY_M_POLC_LS1_P_MIX(4) | |
448 | PHY_M_POLC_IS0_P_MIX(4) | | |
449 | PHY_M_POLC_LOS_CTRL(2) | | |
450 | PHY_M_POLC_INIT_CTRL(2) | | |
451 | PHY_M_POLC_STA1_CTRL(2) | | |
452 | PHY_M_POLC_STA0_CTRL(2))); | |
cd28ab6a SH |
453 | |
454 | /* restore page register */ | |
793b883e | 455 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
cd28ab6a | 456 | break; |
ed6d32c7 SH |
457 | case CHIP_ID_YUKON_EC_U: |
458 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
459 | ||
460 | /* select page 3 to access LED control register */ | |
461 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
462 | ||
463 | /* set LED Function Control register */ | |
464 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
465 | (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ | |
466 | PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */ | |
467 | PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ | |
468 | PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */ | |
469 | ||
470 | /* set Blink Rate in LED Timer Control Register */ | |
471 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, | |
472 | ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS)); | |
473 | /* restore page register */ | |
474 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
475 | break; | |
cd28ab6a SH |
476 | |
477 | default: | |
478 | /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ | |
479 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; | |
480 | /* turn off the Rx LED (LED_RX) */ | |
481 | ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); | |
482 | } | |
483 | ||
ed6d32c7 | 484 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) { |
977bdf06 | 485 | /* apply fixes in PHY AFE */ |
ed6d32c7 SH |
486 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
487 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); | |
488 | ||
977bdf06 | 489 | /* increase differential signal amplitude in 10BASE-T */ |
ed6d32c7 SH |
490 | gm_phy_write(hw, port, 0x18, 0xaa99); |
491 | gm_phy_write(hw, port, 0x17, 0x2011); | |
cd28ab6a | 492 | |
977bdf06 | 493 | /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ |
ed6d32c7 SH |
494 | gm_phy_write(hw, port, 0x18, 0xa204); |
495 | gm_phy_write(hw, port, 0x17, 0x2002); | |
977bdf06 SH |
496 | |
497 | /* set page register to 0 */ | |
ed6d32c7 | 498 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
977bdf06 SH |
499 | } else { |
500 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); | |
cd28ab6a | 501 | |
977bdf06 SH |
502 | if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) { |
503 | /* turn on 100 Mbps LED (LED_LINK100) */ | |
504 | ledover |= PHY_M_LED_MO_100(MO_LED_ON); | |
505 | } | |
cd28ab6a | 506 | |
977bdf06 SH |
507 | if (ledover) |
508 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
509 | ||
510 | } | |
d571b694 | 511 | /* Enable phy interrupt on auto-negotiation complete (or link up) */ |
cd28ab6a SH |
512 | if (sky2->autoneg == AUTONEG_ENABLE) |
513 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); | |
514 | else | |
515 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
516 | } | |
517 | ||
d3bcfbeb | 518 | static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff) |
519 | { | |
520 | u32 reg1; | |
521 | static const u32 phy_power[] | |
522 | = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD }; | |
523 | ||
524 | /* looks like this XL is back asswards .. */ | |
525 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | |
526 | onoff = !onoff; | |
527 | ||
528 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); | |
529 | ||
530 | if (onoff) | |
531 | /* Turn off phy power saving */ | |
532 | reg1 &= ~phy_power[port]; | |
533 | else | |
534 | reg1 |= phy_power[port]; | |
535 | ||
536 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); | |
98232f85 | 537 | sky2_pci_read32(hw, PCI_DEV_REG1); |
d3bcfbeb | 538 | udelay(100); |
539 | } | |
540 | ||
1b537565 SH |
541 | /* Force a renegotiation */ |
542 | static void sky2_phy_reinit(struct sky2_port *sky2) | |
543 | { | |
e07b1aa8 | 544 | spin_lock_bh(&sky2->phy_lock); |
1b537565 | 545 | sky2_phy_init(sky2->hw, sky2->port); |
e07b1aa8 | 546 | spin_unlock_bh(&sky2->phy_lock); |
1b537565 SH |
547 | } |
548 | ||
cd28ab6a SH |
549 | static void sky2_mac_init(struct sky2_hw *hw, unsigned port) |
550 | { | |
551 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
552 | u16 reg; | |
553 | int i; | |
554 | const u8 *addr = hw->dev[port]->dev_addr; | |
555 | ||
42eeea01 | 556 | sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
557 | sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE); | |
cd28ab6a SH |
558 | |
559 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); | |
560 | ||
793b883e | 561 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) { |
cd28ab6a SH |
562 | /* WA DEV_472 -- looks like crossed wires on port 2 */ |
563 | /* clear GMAC 1 Control reset */ | |
564 | sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); | |
565 | do { | |
566 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); | |
567 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); | |
568 | } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || | |
569 | gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || | |
570 | gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); | |
571 | } | |
572 | ||
cd28ab6a SH |
573 | if (sky2->autoneg == AUTONEG_DISABLE) { |
574 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
575 | reg |= GM_GPCR_AU_ALL_DIS; | |
576 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
577 | gma_read16(hw, port, GM_GP_CTRL); | |
578 | ||
cd28ab6a SH |
579 | switch (sky2->speed) { |
580 | case SPEED_1000: | |
6f4c56b2 | 581 | reg &= ~GM_GPCR_SPEED_100; |
cd28ab6a | 582 | reg |= GM_GPCR_SPEED_1000; |
6f4c56b2 | 583 | break; |
cd28ab6a | 584 | case SPEED_100: |
6f4c56b2 | 585 | reg &= ~GM_GPCR_SPEED_1000; |
cd28ab6a | 586 | reg |= GM_GPCR_SPEED_100; |
6f4c56b2 SH |
587 | break; |
588 | case SPEED_10: | |
589 | reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); | |
590 | break; | |
cd28ab6a SH |
591 | } |
592 | ||
593 | if (sky2->duplex == DUPLEX_FULL) | |
594 | reg |= GM_GPCR_DUP_FULL; | |
ed6d32c7 SH |
595 | |
596 | /* turn off pause in 10/100mbps half duplex */ | |
597 | else if (sky2->speed != SPEED_1000 && | |
598 | hw->chip_id != CHIP_ID_YUKON_EC_U) | |
599 | sky2->tx_pause = sky2->rx_pause = 0; | |
cd28ab6a SH |
600 | } else |
601 | reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; | |
602 | ||
603 | if (!sky2->tx_pause && !sky2->rx_pause) { | |
604 | sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
793b883e SH |
605 | reg |= |
606 | GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
607 | } else if (sky2->tx_pause && !sky2->rx_pause) { | |
cd28ab6a SH |
608 | /* disable Rx flow-control */ |
609 | reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
610 | } | |
611 | ||
612 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
613 | ||
793b883e | 614 | sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); |
cd28ab6a | 615 | |
e07b1aa8 | 616 | spin_lock_bh(&sky2->phy_lock); |
cd28ab6a | 617 | sky2_phy_init(hw, port); |
e07b1aa8 | 618 | spin_unlock_bh(&sky2->phy_lock); |
cd28ab6a SH |
619 | |
620 | /* MIB clear */ | |
621 | reg = gma_read16(hw, port, GM_PHY_ADDR); | |
622 | gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); | |
623 | ||
43f2f104 SH |
624 | for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4) |
625 | gma_read16(hw, port, i); | |
cd28ab6a SH |
626 | gma_write16(hw, port, GM_PHY_ADDR, reg); |
627 | ||
628 | /* transmit control */ | |
629 | gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); | |
630 | ||
631 | /* receive control reg: unicast + multicast + no FCS */ | |
632 | gma_write16(hw, port, GM_RX_CTRL, | |
793b883e | 633 | GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); |
cd28ab6a SH |
634 | |
635 | /* transmit flow control */ | |
636 | gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); | |
637 | ||
638 | /* transmit parameter */ | |
639 | gma_write16(hw, port, GM_TX_PARAM, | |
640 | TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | | |
641 | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | | |
642 | TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | | |
643 | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); | |
644 | ||
645 | /* serial mode register */ | |
646 | reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | | |
6b1a3aef | 647 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); |
cd28ab6a | 648 | |
6b1a3aef | 649 | if (hw->dev[port]->mtu > ETH_DATA_LEN) |
cd28ab6a SH |
650 | reg |= GM_SMOD_JUMBO_ENA; |
651 | ||
652 | gma_write16(hw, port, GM_SERIAL_MODE, reg); | |
653 | ||
cd28ab6a SH |
654 | /* virtual address for data */ |
655 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); | |
656 | ||
793b883e SH |
657 | /* physical address: used for pause frames */ |
658 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); | |
659 | ||
660 | /* ignore counter overflows */ | |
cd28ab6a SH |
661 | gma_write16(hw, port, GM_TX_IRQ_MSK, 0); |
662 | gma_write16(hw, port, GM_RX_IRQ_MSK, 0); | |
663 | gma_write16(hw, port, GM_TR_IRQ_MSK, 0); | |
664 | ||
665 | /* Configure Rx MAC FIFO */ | |
666 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); | |
70f1be48 SH |
667 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), |
668 | GMF_OPER_ON | GMF_RX_F_FL_ON); | |
cd28ab6a | 669 | |
d571b694 | 670 | /* Flush Rx MAC FIFO on any flow control or error */ |
42eeea01 | 671 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); |
cd28ab6a | 672 | |
793b883e SH |
673 | /* Set threshold to 0xa (64 bytes) |
674 | * ASF disabled so no need to do WA dev #4.30 | |
cd28ab6a SH |
675 | */ |
676 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF); | |
677 | ||
678 | /* Configure Tx MAC FIFO */ | |
679 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); | |
680 | sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); | |
5a5b1ea0 | 681 | |
682 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { | |
683 | sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8); | |
684 | sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8); | |
685 | if (hw->dev[port]->mtu > ETH_DATA_LEN) { | |
686 | /* set Tx GMAC FIFO Almost Empty Threshold */ | |
687 | sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180); | |
688 | /* Disable Store & Forward mode for TX */ | |
689 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); | |
690 | } | |
691 | } | |
692 | ||
cd28ab6a SH |
693 | } |
694 | ||
1c28f6ba SH |
695 | /* Assign Ram Buffer allocation. |
696 | * start and end are in units of 4k bytes | |
697 | * ram registers are in units of 64bit words | |
698 | */ | |
699 | static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk) | |
cd28ab6a | 700 | { |
1c28f6ba | 701 | u32 start, end; |
cd28ab6a | 702 | |
1c28f6ba SH |
703 | start = startk * 4096/8; |
704 | end = (endk * 4096/8) - 1; | |
793b883e | 705 | |
cd28ab6a SH |
706 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); |
707 | sky2_write32(hw, RB_ADDR(q, RB_START), start); | |
708 | sky2_write32(hw, RB_ADDR(q, RB_END), end); | |
709 | sky2_write32(hw, RB_ADDR(q, RB_WP), start); | |
710 | sky2_write32(hw, RB_ADDR(q, RB_RP), start); | |
711 | ||
712 | if (q == Q_R1 || q == Q_R2) { | |
1c28f6ba SH |
713 | u32 space = (endk - startk) * 4096/8; |
714 | u32 tp = space - space/4; | |
793b883e | 715 | |
1c28f6ba SH |
716 | /* On receive queue's set the thresholds |
717 | * give receiver priority when > 3/4 full | |
718 | * send pause when down to 2K | |
719 | */ | |
720 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); | |
721 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); | |
793b883e | 722 | |
1c28f6ba SH |
723 | tp = space - 2048/8; |
724 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); | |
725 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); | |
cd28ab6a SH |
726 | } else { |
727 | /* Enable store & forward on Tx queue's because | |
728 | * Tx FIFO is only 1K on Yukon | |
729 | */ | |
730 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); | |
731 | } | |
732 | ||
733 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); | |
793b883e | 734 | sky2_read8(hw, RB_ADDR(q, RB_CTRL)); |
cd28ab6a SH |
735 | } |
736 | ||
cd28ab6a | 737 | /* Setup Bus Memory Interface */ |
af4ed7e6 | 738 | static void sky2_qset(struct sky2_hw *hw, u16 q) |
cd28ab6a SH |
739 | { |
740 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); | |
741 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); | |
742 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); | |
af4ed7e6 | 743 | sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); |
cd28ab6a SH |
744 | } |
745 | ||
cd28ab6a SH |
746 | /* Setup prefetch unit registers. This is the interface between |
747 | * hardware and driver list elements | |
748 | */ | |
8cc048e3 | 749 | static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, |
cd28ab6a SH |
750 | u64 addr, u32 last) |
751 | { | |
cd28ab6a SH |
752 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); |
753 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); | |
754 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32); | |
755 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr); | |
756 | sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); | |
757 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); | |
793b883e SH |
758 | |
759 | sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); | |
cd28ab6a SH |
760 | } |
761 | ||
793b883e SH |
762 | static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2) |
763 | { | |
764 | struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod; | |
765 | ||
cb5d9547 | 766 | sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE); |
793b883e SH |
767 | return le; |
768 | } | |
cd28ab6a | 769 | |
290d4de5 SH |
770 | /* Update chip's next pointer */ |
771 | static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) | |
cd28ab6a | 772 | { |
98232f85 | 773 | q = Y2_QADDR(q, PREF_UNIT_PUT_IDX); |
762c2de2 | 774 | wmb(); |
98232f85 | 775 | sky2_write16(hw, q, idx); |
776 | sky2_read16(hw, q); | |
cd28ab6a SH |
777 | } |
778 | ||
793b883e | 779 | |
cd28ab6a SH |
780 | static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) |
781 | { | |
782 | struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; | |
cb5d9547 | 783 | sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE); |
cd28ab6a SH |
784 | return le; |
785 | } | |
786 | ||
a018e330 | 787 | /* Return high part of DMA address (could be 32 or 64 bit) */ |
788 | static inline u32 high32(dma_addr_t a) | |
789 | { | |
a036119f | 790 | return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0; |
a018e330 | 791 | } |
792 | ||
793b883e | 793 | /* Build description to hardware about buffer */ |
28bd181a | 794 | static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map) |
cd28ab6a SH |
795 | { |
796 | struct sky2_rx_le *le; | |
734d1868 SH |
797 | u32 hi = high32(map); |
798 | u16 len = sky2->rx_bufsize; | |
cd28ab6a | 799 | |
793b883e | 800 | if (sky2->rx_addr64 != hi) { |
cd28ab6a | 801 | le = sky2_next_rx(sky2); |
793b883e | 802 | le->addr = cpu_to_le32(hi); |
cd28ab6a SH |
803 | le->ctrl = 0; |
804 | le->opcode = OP_ADDR64 | HW_OWNER; | |
734d1868 | 805 | sky2->rx_addr64 = high32(map + len); |
cd28ab6a | 806 | } |
793b883e | 807 | |
cd28ab6a | 808 | le = sky2_next_rx(sky2); |
734d1868 SH |
809 | le->addr = cpu_to_le32((u32) map); |
810 | le->length = cpu_to_le16(len); | |
cd28ab6a SH |
811 | le->ctrl = 0; |
812 | le->opcode = OP_PACKET | HW_OWNER; | |
813 | } | |
814 | ||
793b883e | 815 | |
cd28ab6a SH |
816 | /* Tell chip where to start receive checksum. |
817 | * Actually has two checksums, but set both same to avoid possible byte | |
818 | * order problems. | |
819 | */ | |
793b883e | 820 | static void rx_set_checksum(struct sky2_port *sky2) |
cd28ab6a SH |
821 | { |
822 | struct sky2_rx_le *le; | |
823 | ||
cd28ab6a | 824 | le = sky2_next_rx(sky2); |
793b883e | 825 | le->addr = (ETH_HLEN << 16) | ETH_HLEN; |
cd28ab6a SH |
826 | le->ctrl = 0; |
827 | le->opcode = OP_TCPSTART | HW_OWNER; | |
793b883e | 828 | |
793b883e SH |
829 | sky2_write32(sky2->hw, |
830 | Q_ADDR(rxqaddr[sky2->port], Q_CSR), | |
831 | sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); | |
cd28ab6a SH |
832 | |
833 | } | |
834 | ||
6b1a3aef | 835 | /* |
836 | * The RX Stop command will not work for Yukon-2 if the BMU does not | |
837 | * reach the end of packet and since we can't make sure that we have | |
838 | * incoming data, we must reset the BMU while it is not doing a DMA | |
839 | * transfer. Since it is possible that the RX path is still active, | |
840 | * the RX RAM buffer will be stopped first, so any possible incoming | |
841 | * data will not trigger a DMA. After the RAM buffer is stopped, the | |
842 | * BMU is polled until any DMA in progress is ended and only then it | |
843 | * will be reset. | |
844 | */ | |
845 | static void sky2_rx_stop(struct sky2_port *sky2) | |
846 | { | |
847 | struct sky2_hw *hw = sky2->hw; | |
848 | unsigned rxq = rxqaddr[sky2->port]; | |
849 | int i; | |
850 | ||
851 | /* disable the RAM Buffer receive queue */ | |
852 | sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); | |
853 | ||
854 | for (i = 0; i < 0xffff; i++) | |
855 | if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) | |
856 | == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) | |
857 | goto stopped; | |
858 | ||
859 | printk(KERN_WARNING PFX "%s: receiver stop failed\n", | |
860 | sky2->netdev->name); | |
861 | stopped: | |
862 | sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); | |
863 | ||
864 | /* reset the Rx prefetch unit */ | |
865 | sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); | |
866 | } | |
793b883e | 867 | |
d571b694 | 868 | /* Clean out receive buffer area, assumes receiver hardware stopped */ |
cd28ab6a SH |
869 | static void sky2_rx_clean(struct sky2_port *sky2) |
870 | { | |
871 | unsigned i; | |
872 | ||
873 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
793b883e | 874 | for (i = 0; i < sky2->rx_pending; i++) { |
cd28ab6a SH |
875 | struct ring_info *re = sky2->rx_ring + i; |
876 | ||
877 | if (re->skb) { | |
793b883e | 878 | pci_unmap_single(sky2->hw->pdev, |
734d1868 | 879 | re->mapaddr, sky2->rx_bufsize, |
cd28ab6a SH |
880 | PCI_DMA_FROMDEVICE); |
881 | kfree_skb(re->skb); | |
882 | re->skb = NULL; | |
883 | } | |
884 | } | |
885 | } | |
886 | ||
ef743d33 | 887 | /* Basic MII support */ |
888 | static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
889 | { | |
890 | struct mii_ioctl_data *data = if_mii(ifr); | |
891 | struct sky2_port *sky2 = netdev_priv(dev); | |
892 | struct sky2_hw *hw = sky2->hw; | |
893 | int err = -EOPNOTSUPP; | |
894 | ||
895 | if (!netif_running(dev)) | |
896 | return -ENODEV; /* Phy still in reset */ | |
897 | ||
d89e1343 | 898 | switch (cmd) { |
ef743d33 | 899 | case SIOCGMIIPHY: |
900 | data->phy_id = PHY_ADDR_MARV; | |
901 | ||
902 | /* fallthru */ | |
903 | case SIOCGMIIREG: { | |
904 | u16 val = 0; | |
91c86df5 | 905 | |
e07b1aa8 | 906 | spin_lock_bh(&sky2->phy_lock); |
ef743d33 | 907 | err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); |
e07b1aa8 | 908 | spin_unlock_bh(&sky2->phy_lock); |
91c86df5 | 909 | |
ef743d33 | 910 | data->val_out = val; |
911 | break; | |
912 | } | |
913 | ||
914 | case SIOCSMIIREG: | |
915 | if (!capable(CAP_NET_ADMIN)) | |
916 | return -EPERM; | |
917 | ||
e07b1aa8 | 918 | spin_lock_bh(&sky2->phy_lock); |
ef743d33 | 919 | err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, |
920 | data->val_in); | |
e07b1aa8 | 921 | spin_unlock_bh(&sky2->phy_lock); |
ef743d33 | 922 | break; |
923 | } | |
924 | return err; | |
925 | } | |
926 | ||
d1f13708 | 927 | #ifdef SKY2_VLAN_TAG_USED |
928 | static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) | |
929 | { | |
930 | struct sky2_port *sky2 = netdev_priv(dev); | |
931 | struct sky2_hw *hw = sky2->hw; | |
932 | u16 port = sky2->port; | |
d1f13708 | 933 | |
302d1252 | 934 | spin_lock_bh(&sky2->tx_lock); |
d1f13708 | 935 | |
936 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON); | |
937 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON); | |
938 | sky2->vlgrp = grp; | |
939 | ||
302d1252 | 940 | spin_unlock_bh(&sky2->tx_lock); |
d1f13708 | 941 | } |
942 | ||
943 | static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) | |
944 | { | |
945 | struct sky2_port *sky2 = netdev_priv(dev); | |
946 | struct sky2_hw *hw = sky2->hw; | |
947 | u16 port = sky2->port; | |
d1f13708 | 948 | |
302d1252 | 949 | spin_lock_bh(&sky2->tx_lock); |
d1f13708 | 950 | |
951 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF); | |
952 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF); | |
953 | if (sky2->vlgrp) | |
954 | sky2->vlgrp->vlan_devices[vid] = NULL; | |
955 | ||
302d1252 | 956 | spin_unlock_bh(&sky2->tx_lock); |
d1f13708 | 957 | } |
958 | #endif | |
959 | ||
82788c7a SH |
960 | /* |
961 | * It appears the hardware has a bug in the FIFO logic that | |
962 | * cause it to hang if the FIFO gets overrun and the receive buffer | |
497d7c86 | 963 | * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is |
964 | * aligned except if slab debugging is enabled. | |
82788c7a | 965 | */ |
497d7c86 | 966 | static inline struct sk_buff *sky2_alloc_skb(struct net_device *dev, |
967 | unsigned int length, | |
968 | gfp_t gfp_mask) | |
82788c7a SH |
969 | { |
970 | struct sk_buff *skb; | |
971 | ||
497d7c86 | 972 | skb = __netdev_alloc_skb(dev, length + RX_SKB_ALIGN, gfp_mask); |
82788c7a SH |
973 | if (likely(skb)) { |
974 | unsigned long p = (unsigned long) skb->data; | |
4a15d56f | 975 | skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p); |
82788c7a SH |
976 | } |
977 | ||
978 | return skb; | |
979 | } | |
980 | ||
cd28ab6a SH |
981 | /* |
982 | * Allocate and setup receiver buffer pool. | |
983 | * In case of 64 bit dma, there are 2X as many list elements | |
984 | * available as ring entries | |
985 | * and need to reserve one list element so we don't wrap around. | |
986 | */ | |
6b1a3aef | 987 | static int sky2_rx_start(struct sky2_port *sky2) |
cd28ab6a | 988 | { |
6b1a3aef | 989 | struct sky2_hw *hw = sky2->hw; |
6b1a3aef | 990 | unsigned rxq = rxqaddr[sky2->port]; |
991 | int i; | |
a1433ac4 | 992 | unsigned thresh; |
cd28ab6a | 993 | |
6b1a3aef | 994 | sky2->rx_put = sky2->rx_next = 0; |
af4ed7e6 | 995 | sky2_qset(hw, rxq); |
977bdf06 SH |
996 | |
997 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) { | |
998 | /* MAC Rx RAM Read is controlled by hardware */ | |
999 | sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS); | |
1000 | } | |
1001 | ||
6b1a3aef | 1002 | sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); |
1003 | ||
1004 | rx_set_checksum(sky2); | |
793b883e | 1005 | for (i = 0; i < sky2->rx_pending; i++) { |
cd28ab6a | 1006 | struct ring_info *re = sky2->rx_ring + i; |
cd28ab6a | 1007 | |
497d7c86 | 1008 | re->skb = sky2_alloc_skb(sky2->netdev, sky2->rx_bufsize, |
1009 | GFP_KERNEL); | |
cd28ab6a SH |
1010 | if (!re->skb) |
1011 | goto nomem; | |
1012 | ||
6b1a3aef | 1013 | re->mapaddr = pci_map_single(hw->pdev, re->skb->data, |
734d1868 SH |
1014 | sky2->rx_bufsize, PCI_DMA_FROMDEVICE); |
1015 | sky2_rx_add(sky2, re->mapaddr); | |
cd28ab6a SH |
1016 | } |
1017 | ||
a1433ac4 SH |
1018 | |
1019 | /* | |
1020 | * The receiver hangs if it receives frames larger than the | |
1021 | * packet buffer. As a workaround, truncate oversize frames, but | |
1022 | * the register is limited to 9 bits, so if you do frames > 2052 | |
1023 | * you better get the MTU right! | |
1024 | */ | |
1025 | thresh = (sky2->rx_bufsize - 8) / sizeof(u32); | |
1026 | if (thresh > 0x1ff) | |
1027 | sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF); | |
1028 | else { | |
1029 | sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh); | |
1030 | sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON); | |
1031 | } | |
1032 | ||
70f1be48 | 1033 | |
6b1a3aef | 1034 | /* Tell chip about available buffers */ |
1035 | sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put); | |
cd28ab6a SH |
1036 | return 0; |
1037 | nomem: | |
1038 | sky2_rx_clean(sky2); | |
1039 | return -ENOMEM; | |
1040 | } | |
1041 | ||
1042 | /* Bring up network interface. */ | |
1043 | static int sky2_up(struct net_device *dev) | |
1044 | { | |
1045 | struct sky2_port *sky2 = netdev_priv(dev); | |
1046 | struct sky2_hw *hw = sky2->hw; | |
1047 | unsigned port = sky2->port; | |
e07b1aa8 | 1048 | u32 ramsize, rxspace, imask; |
ee7abb04 | 1049 | int cap, err = -ENOMEM; |
843a46f4 | 1050 | struct net_device *otherdev = hw->dev[sky2->port^1]; |
cd28ab6a | 1051 | |
ee7abb04 SH |
1052 | /* |
1053 | * On dual port PCI-X card, there is an problem where status | |
1054 | * can be received out of order due to split transactions | |
843a46f4 | 1055 | */ |
ee7abb04 SH |
1056 | if (otherdev && netif_running(otherdev) && |
1057 | (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) { | |
1058 | struct sky2_port *osky2 = netdev_priv(otherdev); | |
1059 | u16 cmd; | |
1060 | ||
1061 | cmd = sky2_pci_read16(hw, cap + PCI_X_CMD); | |
1062 | cmd &= ~PCI_X_CMD_MAX_SPLIT; | |
1063 | sky2_pci_write16(hw, cap + PCI_X_CMD, cmd); | |
1064 | ||
1065 | sky2->rx_csum = 0; | |
1066 | osky2->rx_csum = 0; | |
1067 | } | |
843a46f4 | 1068 | |
cd28ab6a SH |
1069 | if (netif_msg_ifup(sky2)) |
1070 | printk(KERN_INFO PFX "%s: enabling interface\n", dev->name); | |
1071 | ||
1072 | /* must be power of 2 */ | |
1073 | sky2->tx_le = pci_alloc_consistent(hw->pdev, | |
793b883e SH |
1074 | TX_RING_SIZE * |
1075 | sizeof(struct sky2_tx_le), | |
cd28ab6a SH |
1076 | &sky2->tx_le_map); |
1077 | if (!sky2->tx_le) | |
1078 | goto err_out; | |
1079 | ||
6cdbbdf3 | 1080 | sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info), |
cd28ab6a SH |
1081 | GFP_KERNEL); |
1082 | if (!sky2->tx_ring) | |
1083 | goto err_out; | |
1084 | sky2->tx_prod = sky2->tx_cons = 0; | |
cd28ab6a SH |
1085 | |
1086 | sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES, | |
1087 | &sky2->rx_le_map); | |
1088 | if (!sky2->rx_le) | |
1089 | goto err_out; | |
1090 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
1091 | ||
6cdbbdf3 | 1092 | sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info), |
cd28ab6a SH |
1093 | GFP_KERNEL); |
1094 | if (!sky2->rx_ring) | |
1095 | goto err_out; | |
1096 | ||
d3bcfbeb | 1097 | sky2_phy_power(hw, port, 1); |
1098 | ||
cd28ab6a SH |
1099 | sky2_mac_init(hw, port); |
1100 | ||
1c28f6ba SH |
1101 | /* Determine available ram buffer space (in 4K blocks). |
1102 | * Note: not sure about the FE setting below yet | |
1103 | */ | |
1104 | if (hw->chip_id == CHIP_ID_YUKON_FE) | |
1105 | ramsize = 4; | |
1106 | else | |
1107 | ramsize = sky2_read8(hw, B2_E_0); | |
1108 | ||
1109 | /* Give transmitter one third (rounded up) */ | |
1110 | rxspace = ramsize - (ramsize + 2) / 3; | |
cd28ab6a | 1111 | |
cd28ab6a | 1112 | sky2_ramset(hw, rxqaddr[port], 0, rxspace); |
1c28f6ba | 1113 | sky2_ramset(hw, txqaddr[port], rxspace, ramsize); |
cd28ab6a | 1114 | |
793b883e SH |
1115 | /* Make sure SyncQ is disabled */ |
1116 | sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), | |
1117 | RB_RST_SET); | |
1118 | ||
af4ed7e6 | 1119 | sky2_qset(hw, txqaddr[port]); |
5a5b1ea0 | 1120 | |
977bdf06 SH |
1121 | /* Set almost empty threshold */ |
1122 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1) | |
1123 | sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0); | |
5a5b1ea0 | 1124 | |
6b1a3aef | 1125 | sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, |
1126 | TX_RING_SIZE - 1); | |
cd28ab6a | 1127 | |
6b1a3aef | 1128 | err = sky2_rx_start(sky2); |
cd28ab6a SH |
1129 | if (err) |
1130 | goto err_out; | |
1131 | ||
cd28ab6a | 1132 | /* Enable interrupts from phy/mac for port */ |
e07b1aa8 | 1133 | imask = sky2_read32(hw, B0_IMSK); |
f4ea431b | 1134 | imask |= portirq_msk[port]; |
e07b1aa8 SH |
1135 | sky2_write32(hw, B0_IMSK, imask); |
1136 | ||
cd28ab6a SH |
1137 | return 0; |
1138 | ||
1139 | err_out: | |
1b537565 | 1140 | if (sky2->rx_le) { |
cd28ab6a SH |
1141 | pci_free_consistent(hw->pdev, RX_LE_BYTES, |
1142 | sky2->rx_le, sky2->rx_le_map); | |
1b537565 SH |
1143 | sky2->rx_le = NULL; |
1144 | } | |
1145 | if (sky2->tx_le) { | |
cd28ab6a SH |
1146 | pci_free_consistent(hw->pdev, |
1147 | TX_RING_SIZE * sizeof(struct sky2_tx_le), | |
1148 | sky2->tx_le, sky2->tx_le_map); | |
1b537565 SH |
1149 | sky2->tx_le = NULL; |
1150 | } | |
1151 | kfree(sky2->tx_ring); | |
1152 | kfree(sky2->rx_ring); | |
cd28ab6a | 1153 | |
1b537565 SH |
1154 | sky2->tx_ring = NULL; |
1155 | sky2->rx_ring = NULL; | |
cd28ab6a SH |
1156 | return err; |
1157 | } | |
1158 | ||
793b883e SH |
1159 | /* Modular subtraction in ring */ |
1160 | static inline int tx_dist(unsigned tail, unsigned head) | |
1161 | { | |
cb5d9547 | 1162 | return (head - tail) & (TX_RING_SIZE - 1); |
793b883e | 1163 | } |
cd28ab6a | 1164 | |
793b883e SH |
1165 | /* Number of list elements available for next tx */ |
1166 | static inline int tx_avail(const struct sky2_port *sky2) | |
cd28ab6a | 1167 | { |
793b883e | 1168 | return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod); |
cd28ab6a SH |
1169 | } |
1170 | ||
793b883e | 1171 | /* Estimate of number of transmit list elements required */ |
28bd181a | 1172 | static unsigned tx_le_req(const struct sk_buff *skb) |
cd28ab6a | 1173 | { |
793b883e SH |
1174 | unsigned count; |
1175 | ||
1176 | count = sizeof(dma_addr_t) / sizeof(u32); | |
1177 | count += skb_shinfo(skb)->nr_frags * count; | |
1178 | ||
89114afd | 1179 | if (skb_is_gso(skb)) |
793b883e SH |
1180 | ++count; |
1181 | ||
0e3ff6aa | 1182 | if (skb->ip_summed == CHECKSUM_HW) |
793b883e SH |
1183 | ++count; |
1184 | ||
1185 | return count; | |
cd28ab6a SH |
1186 | } |
1187 | ||
793b883e SH |
1188 | /* |
1189 | * Put one packet in ring for transmit. | |
1190 | * A single packet can generate multiple list elements, and | |
1191 | * the number of ring elements will probably be less than the number | |
1192 | * of list elements used. | |
f2e46561 SH |
1193 | * |
1194 | * No BH disabling for tx_lock here (like tg3) | |
793b883e | 1195 | */ |
cd28ab6a SH |
1196 | static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev) |
1197 | { | |
1198 | struct sky2_port *sky2 = netdev_priv(dev); | |
1199 | struct sky2_hw *hw = sky2->hw; | |
d1f13708 | 1200 | struct sky2_tx_le *le = NULL; |
6cdbbdf3 | 1201 | struct tx_ring_info *re; |
cd28ab6a SH |
1202 | unsigned i, len; |
1203 | dma_addr_t mapping; | |
1204 | u32 addr64; | |
1205 | u16 mss; | |
1206 | u8 ctrl; | |
1207 | ||
302d1252 SH |
1208 | /* No BH disabling for tx_lock here. We are running in BH disabled |
1209 | * context and TX reclaim runs via poll inside of a software | |
1210 | * interrupt, and no related locks in IRQ processing. | |
1211 | */ | |
f2e46561 | 1212 | if (!spin_trylock(&sky2->tx_lock)) |
cd28ab6a SH |
1213 | return NETDEV_TX_LOCKED; |
1214 | ||
793b883e | 1215 | if (unlikely(tx_avail(sky2) < tx_le_req(skb))) { |
8c463ef7 SH |
1216 | /* There is a known but harmless race with lockless tx |
1217 | * and netif_stop_queue. | |
1218 | */ | |
1219 | if (!netif_queue_stopped(dev)) { | |
1220 | netif_stop_queue(dev); | |
3be92a70 SH |
1221 | if (net_ratelimit()) |
1222 | printk(KERN_WARNING PFX "%s: ring full when queue awake!\n", | |
1223 | dev->name); | |
8c463ef7 | 1224 | } |
f2e46561 | 1225 | spin_unlock(&sky2->tx_lock); |
cd28ab6a | 1226 | |
cd28ab6a SH |
1227 | return NETDEV_TX_BUSY; |
1228 | } | |
1229 | ||
793b883e | 1230 | if (unlikely(netif_msg_tx_queued(sky2))) |
cd28ab6a SH |
1231 | printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n", |
1232 | dev->name, sky2->tx_prod, skb->len); | |
1233 | ||
cd28ab6a SH |
1234 | len = skb_headlen(skb); |
1235 | mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
a018e330 | 1236 | addr64 = high32(mapping); |
793b883e SH |
1237 | |
1238 | re = sky2->tx_ring + sky2->tx_prod; | |
1239 | ||
a018e330 | 1240 | /* Send high bits if changed or crosses boundary */ |
1241 | if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) { | |
793b883e SH |
1242 | le = get_tx_le(sky2); |
1243 | le->tx.addr = cpu_to_le32(addr64); | |
1244 | le->ctrl = 0; | |
1245 | le->opcode = OP_ADDR64 | HW_OWNER; | |
a018e330 | 1246 | sky2->tx_addr64 = high32(mapping + len); |
793b883e | 1247 | } |
cd28ab6a SH |
1248 | |
1249 | /* Check for TCP Segmentation Offload */ | |
7967168c | 1250 | mss = skb_shinfo(skb)->gso_size; |
793b883e | 1251 | if (mss != 0) { |
cd28ab6a SH |
1252 | mss += ((skb->h.th->doff - 5) * 4); /* TCP options */ |
1253 | mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr); | |
1254 | mss += ETH_HLEN; | |
1255 | ||
e07560cd | 1256 | if (mss != sky2->tx_last_mss) { |
1257 | le = get_tx_le(sky2); | |
1258 | le->tx.tso.size = cpu_to_le16(mss); | |
1259 | le->tx.tso.rsvd = 0; | |
1260 | le->opcode = OP_LRGLEN | HW_OWNER; | |
1261 | le->ctrl = 0; | |
1262 | sky2->tx_last_mss = mss; | |
1263 | } | |
cd28ab6a SH |
1264 | } |
1265 | ||
cd28ab6a | 1266 | ctrl = 0; |
d1f13708 | 1267 | #ifdef SKY2_VLAN_TAG_USED |
1268 | /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */ | |
1269 | if (sky2->vlgrp && vlan_tx_tag_present(skb)) { | |
1270 | if (!le) { | |
1271 | le = get_tx_le(sky2); | |
1272 | le->tx.addr = 0; | |
1273 | le->opcode = OP_VLAN|HW_OWNER; | |
1274 | le->ctrl = 0; | |
1275 | } else | |
1276 | le->opcode |= OP_VLAN; | |
1277 | le->length = cpu_to_be16(vlan_tx_tag_get(skb)); | |
1278 | ctrl |= INS_VLAN; | |
1279 | } | |
1280 | #endif | |
1281 | ||
1282 | /* Handle TCP checksum offload */ | |
cd28ab6a | 1283 | if (skb->ip_summed == CHECKSUM_HW) { |
793b883e SH |
1284 | u16 hdr = skb->h.raw - skb->data; |
1285 | u16 offset = hdr + skb->csum; | |
cd28ab6a SH |
1286 | |
1287 | ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; | |
1288 | if (skb->nh.iph->protocol == IPPROTO_UDP) | |
1289 | ctrl |= UDPTCP; | |
1290 | ||
1d179332 | 1291 | if (hdr != sky2->tx_csum_start || offset != sky2->tx_csum_offset) { |
1292 | sky2->tx_csum_start = hdr; | |
1293 | sky2->tx_csum_offset = offset; | |
1294 | ||
1295 | le = get_tx_le(sky2); | |
1296 | le->tx.csum.start = cpu_to_le16(hdr); | |
1297 | le->tx.csum.offset = cpu_to_le16(offset); | |
1298 | le->length = 0; /* initial checksum value */ | |
1299 | le->ctrl = 1; /* one packet */ | |
1300 | le->opcode = OP_TCPLISW | HW_OWNER; | |
1301 | } | |
cd28ab6a SH |
1302 | } |
1303 | ||
1304 | le = get_tx_le(sky2); | |
1305 | le->tx.addr = cpu_to_le32((u32) mapping); | |
1306 | le->length = cpu_to_le16(len); | |
1307 | le->ctrl = ctrl; | |
793b883e | 1308 | le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); |
cd28ab6a | 1309 | |
793b883e | 1310 | /* Record the transmit mapping info */ |
cd28ab6a | 1311 | re->skb = skb; |
6cdbbdf3 | 1312 | pci_unmap_addr_set(re, mapaddr, mapping); |
cd28ab6a SH |
1313 | |
1314 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
1315 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6cdbbdf3 | 1316 | struct tx_ring_info *fre; |
cd28ab6a SH |
1317 | |
1318 | mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset, | |
1319 | frag->size, PCI_DMA_TODEVICE); | |
a036119f | 1320 | addr64 = high32(mapping); |
793b883e SH |
1321 | if (addr64 != sky2->tx_addr64) { |
1322 | le = get_tx_le(sky2); | |
1323 | le->tx.addr = cpu_to_le32(addr64); | |
1324 | le->ctrl = 0; | |
1325 | le->opcode = OP_ADDR64 | HW_OWNER; | |
1326 | sky2->tx_addr64 = addr64; | |
cd28ab6a SH |
1327 | } |
1328 | ||
1329 | le = get_tx_le(sky2); | |
1330 | le->tx.addr = cpu_to_le32((u32) mapping); | |
1331 | le->length = cpu_to_le16(frag->size); | |
1332 | le->ctrl = ctrl; | |
793b883e | 1333 | le->opcode = OP_BUFFER | HW_OWNER; |
cd28ab6a | 1334 | |
793b883e | 1335 | fre = sky2->tx_ring |
e07560cd | 1336 | + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE); |
6cdbbdf3 | 1337 | pci_unmap_addr_set(fre, mapaddr, mapping); |
cd28ab6a | 1338 | } |
6cdbbdf3 | 1339 | |
793b883e | 1340 | re->idx = sky2->tx_prod; |
cd28ab6a SH |
1341 | le->ctrl |= EOP; |
1342 | ||
97bda706 | 1343 | if (tx_avail(sky2) <= MAX_SKB_TX_LE) |
1344 | netif_stop_queue(dev); | |
b19666d9 | 1345 | |
290d4de5 | 1346 | sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); |
cd28ab6a | 1347 | |
f2e46561 | 1348 | spin_unlock(&sky2->tx_lock); |
cd28ab6a SH |
1349 | |
1350 | dev->trans_start = jiffies; | |
1351 | return NETDEV_TX_OK; | |
1352 | } | |
1353 | ||
cd28ab6a | 1354 | /* |
793b883e SH |
1355 | * Free ring elements from starting at tx_cons until "done" |
1356 | * | |
1357 | * NB: the hardware will tell us about partial completion of multi-part | |
d571b694 | 1358 | * buffers; these are deferred until completion. |
cd28ab6a | 1359 | */ |
d11c13e7 | 1360 | static void sky2_tx_complete(struct sky2_port *sky2, u16 done) |
cd28ab6a | 1361 | { |
d11c13e7 | 1362 | struct net_device *dev = sky2->netdev; |
af2a58ac SH |
1363 | struct pci_dev *pdev = sky2->hw->pdev; |
1364 | u16 nxt, put; | |
793b883e | 1365 | unsigned i; |
cd28ab6a | 1366 | |
0e3ff6aa | 1367 | BUG_ON(done >= TX_RING_SIZE); |
2224795d | 1368 | |
d11c13e7 | 1369 | if (unlikely(netif_msg_tx_done(sky2))) |
d571b694 | 1370 | printk(KERN_DEBUG "%s: tx done, up to %u\n", |
d11c13e7 | 1371 | dev->name, done); |
cd28ab6a | 1372 | |
af2a58ac SH |
1373 | for (put = sky2->tx_cons; put != done; put = nxt) { |
1374 | struct tx_ring_info *re = sky2->tx_ring + put; | |
1375 | struct sk_buff *skb = re->skb; | |
cd28ab6a | 1376 | |
d89e1343 | 1377 | nxt = re->idx; |
af2a58ac | 1378 | BUG_ON(nxt >= TX_RING_SIZE); |
d70cd51a | 1379 | prefetch(sky2->tx_ring + nxt); |
cd28ab6a | 1380 | |
793b883e | 1381 | /* Check for partial status */ |
af2a58ac SH |
1382 | if (tx_dist(put, done) < tx_dist(put, nxt)) |
1383 | break; | |
793b883e SH |
1384 | |
1385 | skb = re->skb; | |
af2a58ac | 1386 | pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr), |
734d1868 | 1387 | skb_headlen(skb), PCI_DMA_TODEVICE); |
793b883e SH |
1388 | |
1389 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
6cdbbdf3 | 1390 | struct tx_ring_info *fre; |
cb5d9547 | 1391 | fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE); |
af2a58ac | 1392 | pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr), |
d89e1343 | 1393 | skb_shinfo(skb)->frags[i].size, |
734d1868 | 1394 | PCI_DMA_TODEVICE); |
cd28ab6a SH |
1395 | } |
1396 | ||
15240072 | 1397 | dev_kfree_skb(skb); |
793b883e | 1398 | } |
793b883e | 1399 | |
af2a58ac | 1400 | sky2->tx_cons = put; |
22e11703 | 1401 | if (tx_avail(sky2) > MAX_SKB_TX_LE + 4) |
cd28ab6a | 1402 | netif_wake_queue(dev); |
cd28ab6a SH |
1403 | } |
1404 | ||
1405 | /* Cleanup all untransmitted buffers, assume transmitter not running */ | |
13b97b74 | 1406 | static void sky2_tx_clean(struct sky2_port *sky2) |
cd28ab6a | 1407 | { |
302d1252 | 1408 | spin_lock_bh(&sky2->tx_lock); |
d11c13e7 | 1409 | sky2_tx_complete(sky2, sky2->tx_prod); |
302d1252 | 1410 | spin_unlock_bh(&sky2->tx_lock); |
cd28ab6a SH |
1411 | } |
1412 | ||
1413 | /* Network shutdown */ | |
1414 | static int sky2_down(struct net_device *dev) | |
1415 | { | |
1416 | struct sky2_port *sky2 = netdev_priv(dev); | |
1417 | struct sky2_hw *hw = sky2->hw; | |
1418 | unsigned port = sky2->port; | |
1419 | u16 ctrl; | |
e07b1aa8 | 1420 | u32 imask; |
cd28ab6a | 1421 | |
1b537565 SH |
1422 | /* Never really got started! */ |
1423 | if (!sky2->tx_le) | |
1424 | return 0; | |
1425 | ||
cd28ab6a SH |
1426 | if (netif_msg_ifdown(sky2)) |
1427 | printk(KERN_INFO PFX "%s: disabling interface\n", dev->name); | |
1428 | ||
018d1c66 | 1429 | /* Stop more packets from being queued */ |
cd28ab6a SH |
1430 | netif_stop_queue(dev); |
1431 | ||
d3bcfbeb | 1432 | sky2_gmac_reset(hw, port); |
793b883e | 1433 | |
cd28ab6a SH |
1434 | /* Stop transmitter */ |
1435 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); | |
1436 | sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); | |
1437 | ||
1438 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), | |
793b883e | 1439 | RB_RST_SET | RB_DIS_OP_MD); |
cd28ab6a SH |
1440 | |
1441 | ctrl = gma_read16(hw, port, GM_GP_CTRL); | |
793b883e | 1442 | ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); |
cd28ab6a SH |
1443 | gma_write16(hw, port, GM_GP_CTRL, ctrl); |
1444 | ||
1445 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); | |
1446 | ||
1447 | /* Workaround shared GMAC reset */ | |
793b883e SH |
1448 | if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 |
1449 | && port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) | |
cd28ab6a SH |
1450 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); |
1451 | ||
1452 | /* Disable Force Sync bit and Enable Alloc bit */ | |
1453 | sky2_write8(hw, SK_REG(port, TXA_CTRL), | |
1454 | TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); | |
1455 | ||
1456 | /* Stop Interval Timer and Limit Counter of Tx Arbiter */ | |
1457 | sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); | |
1458 | sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); | |
1459 | ||
1460 | /* Reset the PCI FIFO of the async Tx queue */ | |
793b883e SH |
1461 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), |
1462 | BMU_RST_SET | BMU_FIFO_RST); | |
cd28ab6a SH |
1463 | |
1464 | /* Reset the Tx prefetch units */ | |
1465 | sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), | |
1466 | PREF_UNIT_RST_SET); | |
1467 | ||
1468 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); | |
1469 | ||
6b1a3aef | 1470 | sky2_rx_stop(sky2); |
cd28ab6a SH |
1471 | |
1472 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); | |
1473 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); | |
1474 | ||
e07b1aa8 SH |
1475 | /* Disable port IRQ */ |
1476 | imask = sky2_read32(hw, B0_IMSK); | |
f4ea431b | 1477 | imask &= ~portirq_msk[port]; |
e07b1aa8 SH |
1478 | sky2_write32(hw, B0_IMSK, imask); |
1479 | ||
d3bcfbeb | 1480 | sky2_phy_power(hw, port, 0); |
1481 | ||
d571b694 | 1482 | /* turn off LED's */ |
cd28ab6a SH |
1483 | sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); |
1484 | ||
018d1c66 | 1485 | synchronize_irq(hw->pdev->irq); |
1486 | ||
cd28ab6a SH |
1487 | sky2_tx_clean(sky2); |
1488 | sky2_rx_clean(sky2); | |
1489 | ||
1490 | pci_free_consistent(hw->pdev, RX_LE_BYTES, | |
1491 | sky2->rx_le, sky2->rx_le_map); | |
1492 | kfree(sky2->rx_ring); | |
1493 | ||
1494 | pci_free_consistent(hw->pdev, | |
1495 | TX_RING_SIZE * sizeof(struct sky2_tx_le), | |
1496 | sky2->tx_le, sky2->tx_le_map); | |
1497 | kfree(sky2->tx_ring); | |
1498 | ||
1b537565 SH |
1499 | sky2->tx_le = NULL; |
1500 | sky2->rx_le = NULL; | |
1501 | ||
1502 | sky2->rx_ring = NULL; | |
1503 | sky2->tx_ring = NULL; | |
1504 | ||
cd28ab6a SH |
1505 | return 0; |
1506 | } | |
1507 | ||
1508 | static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) | |
1509 | { | |
793b883e SH |
1510 | if (!hw->copper) |
1511 | return SPEED_1000; | |
1512 | ||
cd28ab6a SH |
1513 | if (hw->chip_id == CHIP_ID_YUKON_FE) |
1514 | return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10; | |
1515 | ||
1516 | switch (aux & PHY_M_PS_SPEED_MSK) { | |
1517 | case PHY_M_PS_SPEED_1000: | |
1518 | return SPEED_1000; | |
1519 | case PHY_M_PS_SPEED_100: | |
1520 | return SPEED_100; | |
1521 | default: | |
1522 | return SPEED_10; | |
1523 | } | |
1524 | } | |
1525 | ||
1526 | static void sky2_link_up(struct sky2_port *sky2) | |
1527 | { | |
1528 | struct sky2_hw *hw = sky2->hw; | |
1529 | unsigned port = sky2->port; | |
1530 | u16 reg; | |
1531 | ||
1532 | /* Enable Transmit FIFO Underrun */ | |
793b883e | 1533 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); |
cd28ab6a SH |
1534 | |
1535 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
6f4c56b2 SH |
1536 | if (sky2->autoneg == AUTONEG_DISABLE) { |
1537 | reg |= GM_GPCR_AU_ALL_DIS; | |
1538 | ||
1539 | /* Is write/read necessary? Copied from sky2_mac_init */ | |
1540 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
1541 | gma_read16(hw, port, GM_GP_CTRL); | |
1542 | ||
1543 | switch (sky2->speed) { | |
1544 | case SPEED_1000: | |
1545 | reg &= ~GM_GPCR_SPEED_100; | |
1546 | reg |= GM_GPCR_SPEED_1000; | |
1547 | break; | |
1548 | case SPEED_100: | |
1549 | reg &= ~GM_GPCR_SPEED_1000; | |
1550 | reg |= GM_GPCR_SPEED_100; | |
1551 | break; | |
1552 | case SPEED_10: | |
1553 | reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); | |
1554 | break; | |
1555 | } | |
1556 | } else | |
1557 | reg &= ~GM_GPCR_AU_ALL_DIS; | |
1558 | ||
cd28ab6a SH |
1559 | if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE) |
1560 | reg |= GM_GPCR_DUP_FULL; | |
1561 | ||
cd28ab6a SH |
1562 | /* enable Rx/Tx */ |
1563 | reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; | |
1564 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
1565 | gma_read16(hw, port, GM_GP_CTRL); | |
1566 | ||
1567 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
1568 | ||
1569 | netif_carrier_on(sky2->netdev); | |
1570 | netif_wake_queue(sky2->netdev); | |
1571 | ||
1572 | /* Turn on link LED */ | |
793b883e | 1573 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), |
cd28ab6a SH |
1574 | LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); |
1575 | ||
ed6d32c7 | 1576 | if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) { |
793b883e | 1577 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
ed6d32c7 SH |
1578 | u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */ |
1579 | ||
1580 | switch(sky2->speed) { | |
1581 | case SPEED_10: | |
1582 | led |= PHY_M_LEDC_INIT_CTRL(7); | |
1583 | break; | |
1584 | ||
1585 | case SPEED_100: | |
1586 | led |= PHY_M_LEDC_STA1_CTRL(7); | |
1587 | break; | |
1588 | ||
1589 | case SPEED_1000: | |
1590 | led |= PHY_M_LEDC_STA0_CTRL(7); | |
1591 | break; | |
1592 | } | |
793b883e SH |
1593 | |
1594 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
ed6d32c7 | 1595 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led); |
793b883e SH |
1596 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
1597 | } | |
1598 | ||
cd28ab6a SH |
1599 | if (netif_msg_link(sky2)) |
1600 | printk(KERN_INFO PFX | |
d571b694 | 1601 | "%s: Link is up at %d Mbps, %s duplex, flow control %s\n", |
cd28ab6a SH |
1602 | sky2->netdev->name, sky2->speed, |
1603 | sky2->duplex == DUPLEX_FULL ? "full" : "half", | |
1604 | (sky2->tx_pause && sky2->rx_pause) ? "both" : | |
793b883e | 1605 | sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none"); |
cd28ab6a SH |
1606 | } |
1607 | ||
1608 | static void sky2_link_down(struct sky2_port *sky2) | |
1609 | { | |
1610 | struct sky2_hw *hw = sky2->hw; | |
1611 | unsigned port = sky2->port; | |
1612 | u16 reg; | |
1613 | ||
1614 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
1615 | ||
1616 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
1617 | reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); | |
1618 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
1619 | gma_read16(hw, port, GM_GP_CTRL); /* PCI post */ | |
1620 | ||
1621 | if (sky2->rx_pause && !sky2->tx_pause) { | |
1622 | /* restore Asymmetric Pause bit */ | |
1623 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, | |
793b883e SH |
1624 | gm_phy_read(hw, port, PHY_MARV_AUNE_ADV) |
1625 | | PHY_M_AN_ASP); | |
cd28ab6a SH |
1626 | } |
1627 | ||
cd28ab6a SH |
1628 | netif_carrier_off(sky2->netdev); |
1629 | netif_stop_queue(sky2->netdev); | |
1630 | ||
1631 | /* Turn on link LED */ | |
1632 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); | |
1633 | ||
1634 | if (netif_msg_link(sky2)) | |
1635 | printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name); | |
1636 | sky2_phy_init(hw, port); | |
1637 | } | |
1638 | ||
793b883e SH |
1639 | static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) |
1640 | { | |
1641 | struct sky2_hw *hw = sky2->hw; | |
1642 | unsigned port = sky2->port; | |
1643 | u16 lpa; | |
1644 | ||
1645 | lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); | |
1646 | ||
1647 | if (lpa & PHY_M_AN_RF) { | |
1648 | printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name); | |
1649 | return -1; | |
1650 | } | |
1651 | ||
1652 | if (hw->chip_id != CHIP_ID_YUKON_FE && | |
1653 | gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { | |
1654 | printk(KERN_ERR PFX "%s: master/slave fault", | |
1655 | sky2->netdev->name); | |
1656 | return -1; | |
1657 | } | |
1658 | ||
1659 | if (!(aux & PHY_M_PS_SPDUP_RES)) { | |
1660 | printk(KERN_ERR PFX "%s: speed/duplex mismatch", | |
1661 | sky2->netdev->name); | |
1662 | return -1; | |
1663 | } | |
1664 | ||
1665 | sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
1666 | ||
1667 | sky2->speed = sky2_phy_speed(hw, aux); | |
1668 | ||
1669 | /* Pause bits are offset (9..8) */ | |
ed6d32c7 | 1670 | if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) |
793b883e SH |
1671 | aux >>= 6; |
1672 | ||
1673 | sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0; | |
1674 | sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0; | |
1675 | ||
1676 | if ((sky2->tx_pause || sky2->rx_pause) | |
1677 | && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF)) | |
1678 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); | |
1679 | else | |
1680 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
1681 | ||
1682 | return 0; | |
1683 | } | |
cd28ab6a | 1684 | |
e07b1aa8 SH |
1685 | /* Interrupt from PHY */ |
1686 | static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) | |
cd28ab6a | 1687 | { |
e07b1aa8 SH |
1688 | struct net_device *dev = hw->dev[port]; |
1689 | struct sky2_port *sky2 = netdev_priv(dev); | |
cd28ab6a SH |
1690 | u16 istatus, phystat; |
1691 | ||
e07b1aa8 SH |
1692 | spin_lock(&sky2->phy_lock); |
1693 | istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); | |
1694 | phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); | |
1695 | ||
1696 | if (!netif_running(dev)) | |
1697 | goto out; | |
cd28ab6a SH |
1698 | |
1699 | if (netif_msg_intr(sky2)) | |
1700 | printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n", | |
1701 | sky2->netdev->name, istatus, phystat); | |
1702 | ||
1703 | if (istatus & PHY_M_IS_AN_COMPL) { | |
793b883e SH |
1704 | if (sky2_autoneg_done(sky2, phystat) == 0) |
1705 | sky2_link_up(sky2); | |
1706 | goto out; | |
1707 | } | |
cd28ab6a | 1708 | |
793b883e SH |
1709 | if (istatus & PHY_M_IS_LSP_CHANGE) |
1710 | sky2->speed = sky2_phy_speed(hw, phystat); | |
cd28ab6a | 1711 | |
793b883e SH |
1712 | if (istatus & PHY_M_IS_DUP_CHANGE) |
1713 | sky2->duplex = | |
1714 | (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
cd28ab6a | 1715 | |
793b883e SH |
1716 | if (istatus & PHY_M_IS_LST_CHANGE) { |
1717 | if (phystat & PHY_M_PS_LINK_UP) | |
cd28ab6a | 1718 | sky2_link_up(sky2); |
793b883e SH |
1719 | else |
1720 | sky2_link_down(sky2); | |
cd28ab6a | 1721 | } |
793b883e | 1722 | out: |
e07b1aa8 | 1723 | spin_unlock(&sky2->phy_lock); |
cd28ab6a SH |
1724 | } |
1725 | ||
302d1252 SH |
1726 | |
1727 | /* Transmit timeout is only called if we are running, carries is up | |
1728 | * and tx queue is full (stopped). | |
1729 | */ | |
cd28ab6a SH |
1730 | static void sky2_tx_timeout(struct net_device *dev) |
1731 | { | |
1732 | struct sky2_port *sky2 = netdev_priv(dev); | |
8cc048e3 SH |
1733 | struct sky2_hw *hw = sky2->hw; |
1734 | unsigned txq = txqaddr[sky2->port]; | |
8f24664d | 1735 | u16 report, done; |
cd28ab6a SH |
1736 | |
1737 | if (netif_msg_timer(sky2)) | |
1738 | printk(KERN_ERR PFX "%s: tx timeout\n", dev->name); | |
1739 | ||
8f24664d SH |
1740 | report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX); |
1741 | done = sky2_read16(hw, Q_ADDR(txq, Q_DONE)); | |
cd28ab6a | 1742 | |
8f24664d SH |
1743 | printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n", |
1744 | dev->name, | |
1745 | sky2->tx_cons, sky2->tx_prod, report, done); | |
1746 | ||
1747 | if (report != done) { | |
1748 | printk(KERN_INFO PFX "status burst pending (irq moderation?)\n"); | |
1749 | ||
1750 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); | |
1751 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
1752 | } else if (report != sky2->tx_cons) { | |
1753 | printk(KERN_INFO PFX "status report lost?\n"); | |
1754 | ||
1755 | spin_lock_bh(&sky2->tx_lock); | |
1756 | sky2_tx_complete(sky2, report); | |
1757 | spin_unlock_bh(&sky2->tx_lock); | |
1758 | } else { | |
1759 | printk(KERN_INFO PFX "hardware hung? flushing\n"); | |
8cc048e3 | 1760 | |
8f24664d SH |
1761 | sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP); |
1762 | sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); | |
1763 | ||
1764 | sky2_tx_clean(sky2); | |
1765 | ||
1766 | sky2_qset(hw, txq); | |
1767 | sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1); | |
1768 | } | |
cd28ab6a SH |
1769 | } |
1770 | ||
734d1868 | 1771 | |
70f1be48 SH |
1772 | /* Want receive buffer size to be multiple of 64 bits |
1773 | * and incl room for vlan and truncation | |
1774 | */ | |
734d1868 SH |
1775 | static inline unsigned sky2_buf_size(int mtu) |
1776 | { | |
4a15d56f | 1777 | return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8; |
734d1868 SH |
1778 | } |
1779 | ||
cd28ab6a SH |
1780 | static int sky2_change_mtu(struct net_device *dev, int new_mtu) |
1781 | { | |
6b1a3aef | 1782 | struct sky2_port *sky2 = netdev_priv(dev); |
1783 | struct sky2_hw *hw = sky2->hw; | |
1784 | int err; | |
1785 | u16 ctl, mode; | |
e07b1aa8 | 1786 | u32 imask; |
cd28ab6a SH |
1787 | |
1788 | if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) | |
1789 | return -EINVAL; | |
1790 | ||
5a5b1ea0 | 1791 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN) |
1792 | return -EINVAL; | |
1793 | ||
6b1a3aef | 1794 | if (!netif_running(dev)) { |
1795 | dev->mtu = new_mtu; | |
1796 | return 0; | |
1797 | } | |
1798 | ||
e07b1aa8 | 1799 | imask = sky2_read32(hw, B0_IMSK); |
6b1a3aef | 1800 | sky2_write32(hw, B0_IMSK, 0); |
1801 | ||
018d1c66 | 1802 | dev->trans_start = jiffies; /* prevent tx timeout */ |
1803 | netif_stop_queue(dev); | |
1804 | netif_poll_disable(hw->dev[0]); | |
1805 | ||
e07b1aa8 SH |
1806 | synchronize_irq(hw->pdev->irq); |
1807 | ||
6b1a3aef | 1808 | ctl = gma_read16(hw, sky2->port, GM_GP_CTRL); |
1809 | gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); | |
1810 | sky2_rx_stop(sky2); | |
1811 | sky2_rx_clean(sky2); | |
cd28ab6a SH |
1812 | |
1813 | dev->mtu = new_mtu; | |
734d1868 | 1814 | sky2->rx_bufsize = sky2_buf_size(new_mtu); |
6b1a3aef | 1815 | mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | |
1816 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); | |
1817 | ||
1818 | if (dev->mtu > ETH_DATA_LEN) | |
1819 | mode |= GM_SMOD_JUMBO_ENA; | |
1820 | ||
1821 | gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode); | |
cd28ab6a | 1822 | |
6b1a3aef | 1823 | sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD); |
cd28ab6a | 1824 | |
6b1a3aef | 1825 | err = sky2_rx_start(sky2); |
e07b1aa8 | 1826 | sky2_write32(hw, B0_IMSK, imask); |
018d1c66 | 1827 | |
1b537565 SH |
1828 | if (err) |
1829 | dev_close(dev); | |
1830 | else { | |
1831 | gma_write16(hw, sky2->port, GM_GP_CTRL, ctl); | |
1832 | ||
1833 | netif_poll_enable(hw->dev[0]); | |
1834 | netif_wake_queue(dev); | |
1835 | } | |
1836 | ||
cd28ab6a SH |
1837 | return err; |
1838 | } | |
1839 | ||
1840 | /* | |
1841 | * Receive one packet. | |
1842 | * For small packets or errors, just reuse existing skb. | |
d571b694 | 1843 | * For larger packets, get new buffer. |
cd28ab6a | 1844 | */ |
497d7c86 | 1845 | static struct sk_buff *sky2_receive(struct net_device *dev, |
cd28ab6a SH |
1846 | u16 length, u32 status) |
1847 | { | |
497d7c86 | 1848 | struct sky2_port *sky2 = netdev_priv(dev); |
cd28ab6a | 1849 | struct ring_info *re = sky2->rx_ring + sky2->rx_next; |
79e57d32 | 1850 | struct sk_buff *skb = NULL; |
cd28ab6a SH |
1851 | |
1852 | if (unlikely(netif_msg_rx_status(sky2))) | |
1853 | printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n", | |
497d7c86 | 1854 | dev->name, sky2->rx_next, status, length); |
cd28ab6a | 1855 | |
793b883e | 1856 | sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; |
d70cd51a | 1857 | prefetch(sky2->rx_ring + sky2->rx_next); |
cd28ab6a | 1858 | |
42eeea01 | 1859 | if (status & GMR_FS_ANY_ERR) |
cd28ab6a SH |
1860 | goto error; |
1861 | ||
42eeea01 | 1862 | if (!(status & GMR_FS_RX_OK)) |
1863 | goto resubmit; | |
1864 | ||
497d7c86 | 1865 | if (length > dev->mtu + ETH_HLEN) |
6e15b712 SH |
1866 | goto oversize; |
1867 | ||
bdb5c58e | 1868 | if (length < copybreak) { |
497d7c86 | 1869 | skb = netdev_alloc_skb(dev, length + 2); |
79e57d32 | 1870 | if (!skb) |
793b883e SH |
1871 | goto resubmit; |
1872 | ||
79e57d32 | 1873 | skb_reserve(skb, 2); |
793b883e SH |
1874 | pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr, |
1875 | length, PCI_DMA_FROMDEVICE); | |
79e57d32 | 1876 | memcpy(skb->data, re->skb->data, length); |
d11c13e7 | 1877 | skb->ip_summed = re->skb->ip_summed; |
1878 | skb->csum = re->skb->csum; | |
793b883e SH |
1879 | pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr, |
1880 | length, PCI_DMA_FROMDEVICE); | |
793b883e | 1881 | } else { |
79e57d32 SH |
1882 | struct sk_buff *nskb; |
1883 | ||
497d7c86 | 1884 | nskb = sky2_alloc_skb(dev, sky2->rx_bufsize, GFP_ATOMIC); |
793b883e SH |
1885 | if (!nskb) |
1886 | goto resubmit; | |
cd28ab6a | 1887 | |
793b883e | 1888 | skb = re->skb; |
79e57d32 | 1889 | re->skb = nskb; |
793b883e | 1890 | pci_unmap_single(sky2->hw->pdev, re->mapaddr, |
734d1868 | 1891 | sky2->rx_bufsize, PCI_DMA_FROMDEVICE); |
793b883e | 1892 | prefetch(skb->data); |
cd28ab6a | 1893 | |
793b883e | 1894 | re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data, |
734d1868 | 1895 | sky2->rx_bufsize, PCI_DMA_FROMDEVICE); |
793b883e | 1896 | } |
cd28ab6a | 1897 | |
79e57d32 | 1898 | skb_put(skb, length); |
793b883e | 1899 | resubmit: |
d11c13e7 | 1900 | re->skb->ip_summed = CHECKSUM_NONE; |
734d1868 | 1901 | sky2_rx_add(sky2, re->mapaddr); |
79e57d32 | 1902 | |
cd28ab6a SH |
1903 | return skb; |
1904 | ||
6e15b712 SH |
1905 | oversize: |
1906 | ++sky2->net_stats.rx_over_errors; | |
1907 | goto resubmit; | |
1908 | ||
cd28ab6a | 1909 | error: |
6e15b712 SH |
1910 | ++sky2->net_stats.rx_errors; |
1911 | ||
3be92a70 | 1912 | if (netif_msg_rx_err(sky2) && net_ratelimit()) |
cd28ab6a | 1913 | printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n", |
497d7c86 | 1914 | dev->name, status, length); |
793b883e SH |
1915 | |
1916 | if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE)) | |
cd28ab6a SH |
1917 | sky2->net_stats.rx_length_errors++; |
1918 | if (status & GMR_FS_FRAGMENT) | |
1919 | sky2->net_stats.rx_frame_errors++; | |
1920 | if (status & GMR_FS_CRC_ERR) | |
1921 | sky2->net_stats.rx_crc_errors++; | |
793b883e SH |
1922 | if (status & GMR_FS_RX_FF_OV) |
1923 | sky2->net_stats.rx_fifo_errors++; | |
79e57d32 | 1924 | |
793b883e | 1925 | goto resubmit; |
cd28ab6a SH |
1926 | } |
1927 | ||
e07b1aa8 SH |
1928 | /* Transmit complete */ |
1929 | static inline void sky2_tx_done(struct net_device *dev, u16 last) | |
13b97b74 | 1930 | { |
e07b1aa8 | 1931 | struct sky2_port *sky2 = netdev_priv(dev); |
302d1252 | 1932 | |
e07b1aa8 SH |
1933 | if (netif_running(dev)) { |
1934 | spin_lock(&sky2->tx_lock); | |
1935 | sky2_tx_complete(sky2, last); | |
1936 | spin_unlock(&sky2->tx_lock); | |
2224795d | 1937 | } |
cd28ab6a SH |
1938 | } |
1939 | ||
e07b1aa8 SH |
1940 | /* Process status response ring */ |
1941 | static int sky2_status_intr(struct sky2_hw *hw, int to_do) | |
cd28ab6a | 1942 | { |
22e11703 | 1943 | struct sky2_port *sky2; |
e07b1aa8 | 1944 | int work_done = 0; |
22e11703 | 1945 | unsigned buf_write[2] = { 0, 0 }; |
e71ebd73 | 1946 | u16 hwidx = sky2_read16(hw, STAT_PUT_IDX); |
a8fd6266 | 1947 | |
af2a58ac | 1948 | rmb(); |
bea86103 | 1949 | |
e71ebd73 | 1950 | while (hw->st_idx != hwidx) { |
13210ce5 | 1951 | struct sky2_status_le *le = hw->st_le + hw->st_idx; |
1952 | struct net_device *dev; | |
cd28ab6a | 1953 | struct sk_buff *skb; |
cd28ab6a SH |
1954 | u32 status; |
1955 | u16 length; | |
1956 | ||
cb5d9547 | 1957 | hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE); |
bea86103 | 1958 | |
e71ebd73 SH |
1959 | BUG_ON(le->link >= 2); |
1960 | dev = hw->dev[le->link]; | |
13210ce5 | 1961 | |
1962 | sky2 = netdev_priv(dev); | |
e07b1aa8 SH |
1963 | length = le->length; |
1964 | status = le->status; | |
cd28ab6a | 1965 | |
e71ebd73 | 1966 | switch (le->opcode & ~HW_OWNER) { |
cd28ab6a | 1967 | case OP_RXSTAT: |
497d7c86 | 1968 | skb = sky2_receive(dev, length, status); |
d1f13708 | 1969 | if (!skb) |
1970 | break; | |
13210ce5 | 1971 | |
13210ce5 | 1972 | skb->protocol = eth_type_trans(skb, dev); |
1973 | dev->last_rx = jiffies; | |
1974 | ||
d1f13708 | 1975 | #ifdef SKY2_VLAN_TAG_USED |
1976 | if (sky2->vlgrp && (status & GMR_FS_VLAN)) { | |
1977 | vlan_hwaccel_receive_skb(skb, | |
1978 | sky2->vlgrp, | |
1979 | be16_to_cpu(sky2->rx_tag)); | |
1980 | } else | |
1981 | #endif | |
cd28ab6a | 1982 | netif_receive_skb(skb); |
13210ce5 | 1983 | |
22e11703 SH |
1984 | /* Update receiver after 16 frames */ |
1985 | if (++buf_write[le->link] == RX_BUF_WRITE) { | |
1986 | sky2_put_idx(hw, rxqaddr[le->link], | |
1987 | sky2->rx_put); | |
1988 | buf_write[le->link] = 0; | |
1989 | } | |
1990 | ||
1991 | /* Stop after net poll weight */ | |
13210ce5 | 1992 | if (++work_done >= to_do) |
1993 | goto exit_loop; | |
cd28ab6a SH |
1994 | break; |
1995 | ||
d1f13708 | 1996 | #ifdef SKY2_VLAN_TAG_USED |
1997 | case OP_RXVLAN: | |
1998 | sky2->rx_tag = length; | |
1999 | break; | |
2000 | ||
2001 | case OP_RXCHKSVLAN: | |
2002 | sky2->rx_tag = length; | |
2003 | /* fall through */ | |
2004 | #endif | |
cd28ab6a | 2005 | case OP_RXCHKS: |
d11c13e7 | 2006 | skb = sky2->rx_ring[sky2->rx_next].skb; |
2007 | skb->ip_summed = CHECKSUM_HW; | |
2008 | skb->csum = le16_to_cpu(status); | |
cd28ab6a SH |
2009 | break; |
2010 | ||
2011 | case OP_TXINDEXLE: | |
13b97b74 | 2012 | /* TX index reports status for both ports */ |
f55925d7 SH |
2013 | BUILD_BUG_ON(TX_RING_SIZE > 0x1000); |
2014 | sky2_tx_done(hw->dev[0], status & 0xfff); | |
e07b1aa8 SH |
2015 | if (hw->dev[1]) |
2016 | sky2_tx_done(hw->dev[1], | |
2017 | ((status >> 24) & 0xff) | |
2018 | | (u16)(length & 0xf) << 8); | |
cd28ab6a SH |
2019 | break; |
2020 | ||
cd28ab6a SH |
2021 | default: |
2022 | if (net_ratelimit()) | |
793b883e | 2023 | printk(KERN_WARNING PFX |
e71ebd73 SH |
2024 | "unknown status opcode 0x%x\n", le->opcode); |
2025 | goto exit_loop; | |
cd28ab6a | 2026 | } |
13210ce5 | 2027 | } |
cd28ab6a | 2028 | |
fe2a24df SH |
2029 | /* Fully processed status ring so clear irq */ |
2030 | sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); | |
2031 | ||
13210ce5 | 2032 | exit_loop: |
22e11703 SH |
2033 | if (buf_write[0]) { |
2034 | sky2 = netdev_priv(hw->dev[0]); | |
2035 | sky2_put_idx(hw, Q_R1, sky2->rx_put); | |
2036 | } | |
2037 | ||
2038 | if (buf_write[1]) { | |
2039 | sky2 = netdev_priv(hw->dev[1]); | |
2040 | sky2_put_idx(hw, Q_R2, sky2->rx_put); | |
2041 | } | |
2042 | ||
e07b1aa8 | 2043 | return work_done; |
cd28ab6a SH |
2044 | } |
2045 | ||
2046 | static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) | |
2047 | { | |
2048 | struct net_device *dev = hw->dev[port]; | |
2049 | ||
3be92a70 SH |
2050 | if (net_ratelimit()) |
2051 | printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n", | |
2052 | dev->name, status); | |
cd28ab6a SH |
2053 | |
2054 | if (status & Y2_IS_PAR_RD1) { | |
3be92a70 SH |
2055 | if (net_ratelimit()) |
2056 | printk(KERN_ERR PFX "%s: ram data read parity error\n", | |
2057 | dev->name); | |
cd28ab6a SH |
2058 | /* Clear IRQ */ |
2059 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); | |
2060 | } | |
2061 | ||
2062 | if (status & Y2_IS_PAR_WR1) { | |
3be92a70 SH |
2063 | if (net_ratelimit()) |
2064 | printk(KERN_ERR PFX "%s: ram data write parity error\n", | |
2065 | dev->name); | |
cd28ab6a SH |
2066 | |
2067 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); | |
2068 | } | |
2069 | ||
2070 | if (status & Y2_IS_PAR_MAC1) { | |
3be92a70 SH |
2071 | if (net_ratelimit()) |
2072 | printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name); | |
cd28ab6a SH |
2073 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); |
2074 | } | |
2075 | ||
2076 | if (status & Y2_IS_PAR_RX1) { | |
3be92a70 SH |
2077 | if (net_ratelimit()) |
2078 | printk(KERN_ERR PFX "%s: RX parity error\n", dev->name); | |
cd28ab6a SH |
2079 | sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); |
2080 | } | |
2081 | ||
2082 | if (status & Y2_IS_TCP_TXA1) { | |
3be92a70 SH |
2083 | if (net_ratelimit()) |
2084 | printk(KERN_ERR PFX "%s: TCP segmentation error\n", | |
2085 | dev->name); | |
cd28ab6a SH |
2086 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); |
2087 | } | |
2088 | } | |
2089 | ||
2090 | static void sky2_hw_intr(struct sky2_hw *hw) | |
2091 | { | |
2092 | u32 status = sky2_read32(hw, B0_HWE_ISRC); | |
2093 | ||
793b883e | 2094 | if (status & Y2_IS_TIST_OV) |
cd28ab6a | 2095 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
2096 | |
2097 | if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { | |
793b883e SH |
2098 | u16 pci_err; |
2099 | ||
56a645cc | 2100 | pci_err = sky2_pci_read16(hw, PCI_STATUS); |
3be92a70 SH |
2101 | if (net_ratelimit()) |
2102 | printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n", | |
2103 | pci_name(hw->pdev), pci_err); | |
cd28ab6a SH |
2104 | |
2105 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
56a645cc | 2106 | sky2_pci_write16(hw, PCI_STATUS, |
793b883e | 2107 | pci_err | PCI_STATUS_ERROR_BITS); |
cd28ab6a SH |
2108 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
2109 | } | |
2110 | ||
2111 | if (status & Y2_IS_PCI_EXP) { | |
d571b694 | 2112 | /* PCI-Express uncorrectable Error occurred */ |
793b883e SH |
2113 | u32 pex_err; |
2114 | ||
56a645cc | 2115 | pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT); |
cd28ab6a | 2116 | |
3be92a70 SH |
2117 | if (net_ratelimit()) |
2118 | printk(KERN_ERR PFX "%s: pci express error (0x%x)\n", | |
2119 | pci_name(hw->pdev), pex_err); | |
cd28ab6a SH |
2120 | |
2121 | /* clear the interrupt */ | |
2122 | sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
56a645cc | 2123 | sky2_pci_write32(hw, PEX_UNC_ERR_STAT, |
793b883e | 2124 | 0xffffffffUL); |
cd28ab6a SH |
2125 | sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
2126 | ||
2127 | if (pex_err & PEX_FATAL_ERRORS) { | |
2128 | u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); | |
2129 | hwmsk &= ~Y2_IS_PCI_EXP; | |
2130 | sky2_write32(hw, B0_HWE_IMSK, hwmsk); | |
2131 | } | |
2132 | } | |
2133 | ||
2134 | if (status & Y2_HWE_L1_MASK) | |
2135 | sky2_hw_error(hw, 0, status); | |
2136 | status >>= 8; | |
2137 | if (status & Y2_HWE_L1_MASK) | |
2138 | sky2_hw_error(hw, 1, status); | |
2139 | } | |
2140 | ||
2141 | static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) | |
2142 | { | |
2143 | struct net_device *dev = hw->dev[port]; | |
2144 | struct sky2_port *sky2 = netdev_priv(dev); | |
2145 | u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); | |
2146 | ||
2147 | if (netif_msg_intr(sky2)) | |
2148 | printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n", | |
2149 | dev->name, status); | |
2150 | ||
2151 | if (status & GM_IS_RX_FF_OR) { | |
2152 | ++sky2->net_stats.rx_fifo_errors; | |
2153 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); | |
2154 | } | |
2155 | ||
2156 | if (status & GM_IS_TX_FF_UR) { | |
2157 | ++sky2->net_stats.tx_fifo_errors; | |
2158 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); | |
2159 | } | |
cd28ab6a SH |
2160 | } |
2161 | ||
d257924e SH |
2162 | /* This should never happen it is a fatal situation */ |
2163 | static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port, | |
2164 | const char *rxtx, u32 mask) | |
2165 | { | |
2166 | struct net_device *dev = hw->dev[port]; | |
2167 | struct sky2_port *sky2 = netdev_priv(dev); | |
2168 | u32 imask; | |
2169 | ||
2170 | printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n", | |
2171 | dev ? dev->name : "<not registered>", rxtx); | |
2172 | ||
2173 | imask = sky2_read32(hw, B0_IMSK); | |
2174 | imask &= ~mask; | |
2175 | sky2_write32(hw, B0_IMSK, imask); | |
2176 | ||
2177 | if (dev) { | |
2178 | spin_lock(&sky2->phy_lock); | |
2179 | sky2_link_down(sky2); | |
2180 | spin_unlock(&sky2->phy_lock); | |
2181 | } | |
2182 | } | |
cd28ab6a | 2183 | |
d27ed387 SH |
2184 | /* If idle then force a fake soft NAPI poll once a second |
2185 | * to work around cases where sharing an edge triggered interrupt. | |
2186 | */ | |
eb35cf60 SH |
2187 | static inline void sky2_idle_start(struct sky2_hw *hw) |
2188 | { | |
2189 | if (idle_timeout > 0) | |
2190 | mod_timer(&hw->idle_timer, | |
2191 | jiffies + msecs_to_jiffies(idle_timeout)); | |
2192 | } | |
2193 | ||
d27ed387 SH |
2194 | static void sky2_idle(unsigned long arg) |
2195 | { | |
01bd7564 SH |
2196 | struct sky2_hw *hw = (struct sky2_hw *) arg; |
2197 | struct net_device *dev = hw->dev[0]; | |
d27ed387 | 2198 | |
d27ed387 SH |
2199 | if (__netif_rx_schedule_prep(dev)) |
2200 | __netif_rx_schedule(dev); | |
01bd7564 SH |
2201 | |
2202 | mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout)); | |
d27ed387 SH |
2203 | } |
2204 | ||
2205 | ||
e07b1aa8 | 2206 | static int sky2_poll(struct net_device *dev0, int *budget) |
cd28ab6a | 2207 | { |
e07b1aa8 SH |
2208 | struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw; |
2209 | int work_limit = min(dev0->quota, *budget); | |
2210 | int work_done = 0; | |
fb2690a9 | 2211 | u32 status = sky2_read32(hw, B0_Y2_SP_EISR); |
cd28ab6a | 2212 | |
1e5f1283 SH |
2213 | if (status & Y2_IS_HW_ERR) |
2214 | sky2_hw_intr(hw); | |
d257924e | 2215 | |
1e5f1283 SH |
2216 | if (status & Y2_IS_IRQ_PHY1) |
2217 | sky2_phy_intr(hw, 0); | |
cd28ab6a | 2218 | |
1e5f1283 SH |
2219 | if (status & Y2_IS_IRQ_PHY2) |
2220 | sky2_phy_intr(hw, 1); | |
cd28ab6a | 2221 | |
1e5f1283 SH |
2222 | if (status & Y2_IS_IRQ_MAC1) |
2223 | sky2_mac_intr(hw, 0); | |
cd28ab6a | 2224 | |
1e5f1283 SH |
2225 | if (status & Y2_IS_IRQ_MAC2) |
2226 | sky2_mac_intr(hw, 1); | |
cd28ab6a | 2227 | |
1e5f1283 SH |
2228 | if (status & Y2_IS_CHK_RX1) |
2229 | sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1); | |
d257924e | 2230 | |
1e5f1283 SH |
2231 | if (status & Y2_IS_CHK_RX2) |
2232 | sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2); | |
d257924e | 2233 | |
1e5f1283 SH |
2234 | if (status & Y2_IS_CHK_TXA1) |
2235 | sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1); | |
d257924e | 2236 | |
1e5f1283 SH |
2237 | if (status & Y2_IS_CHK_TXA2) |
2238 | sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2); | |
cd28ab6a | 2239 | |
1e5f1283 | 2240 | work_done = sky2_status_intr(hw, work_limit); |
fe2a24df SH |
2241 | if (work_done < work_limit) { |
2242 | netif_rx_complete(dev0); | |
86fba634 | 2243 | |
fe2a24df SH |
2244 | sky2_read32(hw, B0_Y2_SP_LISR); |
2245 | return 0; | |
2246 | } else { | |
2247 | *budget -= work_done; | |
2248 | dev0->quota -= work_done; | |
1e5f1283 | 2249 | return 1; |
fe2a24df | 2250 | } |
e07b1aa8 SH |
2251 | } |
2252 | ||
2253 | static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs) | |
2254 | { | |
2255 | struct sky2_hw *hw = dev_id; | |
2256 | struct net_device *dev0 = hw->dev[0]; | |
2257 | u32 status; | |
2258 | ||
2259 | /* Reading this mask interrupts as side effect */ | |
2260 | status = sky2_read32(hw, B0_Y2_SP_ISRC2); | |
2261 | if (status == 0 || status == ~0) | |
2262 | return IRQ_NONE; | |
793b883e | 2263 | |
e07b1aa8 SH |
2264 | prefetch(&hw->st_le[hw->st_idx]); |
2265 | if (likely(__netif_rx_schedule_prep(dev0))) | |
2266 | __netif_rx_schedule(dev0); | |
793b883e | 2267 | |
cd28ab6a SH |
2268 | return IRQ_HANDLED; |
2269 | } | |
2270 | ||
2271 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2272 | static void sky2_netpoll(struct net_device *dev) | |
2273 | { | |
2274 | struct sky2_port *sky2 = netdev_priv(dev); | |
88d11360 | 2275 | struct net_device *dev0 = sky2->hw->dev[0]; |
cd28ab6a | 2276 | |
88d11360 SH |
2277 | if (netif_running(dev) && __netif_rx_schedule_prep(dev0)) |
2278 | __netif_rx_schedule(dev0); | |
cd28ab6a SH |
2279 | } |
2280 | #endif | |
2281 | ||
2282 | /* Chip internal frequency for clock calculations */ | |
fb17358f | 2283 | static inline u32 sky2_mhz(const struct sky2_hw *hw) |
cd28ab6a | 2284 | { |
793b883e | 2285 | switch (hw->chip_id) { |
cd28ab6a | 2286 | case CHIP_ID_YUKON_EC: |
5a5b1ea0 | 2287 | case CHIP_ID_YUKON_EC_U: |
fb17358f | 2288 | return 125; /* 125 Mhz */ |
cd28ab6a | 2289 | case CHIP_ID_YUKON_FE: |
fb17358f | 2290 | return 100; /* 100 Mhz */ |
793b883e | 2291 | default: /* YUKON_XL */ |
fb17358f | 2292 | return 156; /* 156 Mhz */ |
cd28ab6a SH |
2293 | } |
2294 | } | |
2295 | ||
fb17358f | 2296 | static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) |
cd28ab6a | 2297 | { |
fb17358f | 2298 | return sky2_mhz(hw) * us; |
cd28ab6a SH |
2299 | } |
2300 | ||
fb17358f | 2301 | static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) |
cd28ab6a | 2302 | { |
fb17358f | 2303 | return clk / sky2_mhz(hw); |
cd28ab6a SH |
2304 | } |
2305 | ||
fb17358f | 2306 | |
59139528 | 2307 | static int sky2_reset(struct sky2_hw *hw) |
cd28ab6a | 2308 | { |
cd28ab6a SH |
2309 | u16 status; |
2310 | u8 t8, pmd_type; | |
56a645cc | 2311 | int i; |
cd28ab6a | 2312 | |
cd28ab6a | 2313 | sky2_write8(hw, B0_CTST, CS_RST_CLR); |
08c06d8a | 2314 | |
cd28ab6a SH |
2315 | hw->chip_id = sky2_read8(hw, B2_CHIP_ID); |
2316 | if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) { | |
2317 | printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n", | |
2318 | pci_name(hw->pdev), hw->chip_id); | |
2319 | return -EOPNOTSUPP; | |
2320 | } | |
2321 | ||
290d4de5 SH |
2322 | hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; |
2323 | ||
2324 | /* This rev is really old, and requires untested workarounds */ | |
2325 | if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) { | |
2326 | printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n", | |
2327 | pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL], | |
2328 | hw->chip_id, hw->chip_rev); | |
2329 | return -EOPNOTSUPP; | |
2330 | } | |
2331 | ||
cd28ab6a SH |
2332 | /* disable ASF */ |
2333 | if (hw->chip_id <= CHIP_ID_YUKON_EC) { | |
2334 | sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); | |
2335 | sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); | |
2336 | } | |
2337 | ||
2338 | /* do a SW reset */ | |
2339 | sky2_write8(hw, B0_CTST, CS_RST_SET); | |
2340 | sky2_write8(hw, B0_CTST, CS_RST_CLR); | |
2341 | ||
2342 | /* clear PCI errors, if any */ | |
56a645cc | 2343 | status = sky2_pci_read16(hw, PCI_STATUS); |
2d42d21f | 2344 | |
cd28ab6a | 2345 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
56a645cc SH |
2346 | sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS); |
2347 | ||
cd28ab6a SH |
2348 | |
2349 | sky2_write8(hw, B0_CTST, CS_MRST_CLR); | |
2350 | ||
2351 | /* clear any PEX errors */ | |
d89e1343 | 2352 | if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) |
56a645cc SH |
2353 | sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL); |
2354 | ||
cd28ab6a SH |
2355 | |
2356 | pmd_type = sky2_read8(hw, B2_PMD_TYP); | |
2357 | hw->copper = !(pmd_type == 'L' || pmd_type == 'S'); | |
2358 | ||
2359 | hw->ports = 1; | |
2360 | t8 = sky2_read8(hw, B2_Y2_HW_RES); | |
2361 | if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { | |
2362 | if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) | |
2363 | ++hw->ports; | |
2364 | } | |
cd28ab6a | 2365 | |
5afa0a9c | 2366 | sky2_set_power_state(hw, PCI_D0); |
cd28ab6a SH |
2367 | |
2368 | for (i = 0; i < hw->ports; i++) { | |
2369 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); | |
2370 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
2371 | } | |
2372 | ||
2373 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
2374 | ||
793b883e SH |
2375 | /* Clear I2C IRQ noise */ |
2376 | sky2_write32(hw, B2_I2C_IRQ, 1); | |
cd28ab6a SH |
2377 | |
2378 | /* turn off hardware timer (unused) */ | |
2379 | sky2_write8(hw, B2_TI_CTRL, TIM_STOP); | |
2380 | sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); | |
793b883e | 2381 | |
cd28ab6a SH |
2382 | sky2_write8(hw, B0_Y2LED, LED_STAT_ON); |
2383 | ||
69634ee7 SH |
2384 | /* Turn off descriptor polling */ |
2385 | sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); | |
cd28ab6a SH |
2386 | |
2387 | /* Turn off receive timestamp */ | |
2388 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); | |
793b883e | 2389 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
2390 | |
2391 | /* enable the Tx Arbiters */ | |
2392 | for (i = 0; i < hw->ports; i++) | |
2393 | sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); | |
2394 | ||
2395 | /* Initialize ram interface */ | |
2396 | for (i = 0; i < hw->ports; i++) { | |
793b883e | 2397 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); |
cd28ab6a SH |
2398 | |
2399 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); | |
2400 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); | |
2401 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); | |
2402 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); | |
2403 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); | |
2404 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); | |
2405 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); | |
2406 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); | |
2407 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); | |
2408 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); | |
2409 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); | |
2410 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); | |
2411 | } | |
2412 | ||
cd28ab6a SH |
2413 | sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK); |
2414 | ||
cd28ab6a | 2415 | for (i = 0; i < hw->ports; i++) |
d3bcfbeb | 2416 | sky2_gmac_reset(hw, i); |
cd28ab6a | 2417 | |
cd28ab6a SH |
2418 | memset(hw->st_le, 0, STATUS_LE_BYTES); |
2419 | hw->st_idx = 0; | |
2420 | ||
2421 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); | |
2422 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); | |
2423 | ||
2424 | sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); | |
793b883e | 2425 | sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); |
cd28ab6a SH |
2426 | |
2427 | /* Set the list last index */ | |
793b883e | 2428 | sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1); |
cd28ab6a | 2429 | |
290d4de5 SH |
2430 | sky2_write16(hw, STAT_TX_IDX_TH, 10); |
2431 | sky2_write8(hw, STAT_FIFO_WM, 16); | |
cd28ab6a | 2432 | |
290d4de5 SH |
2433 | /* set Status-FIFO ISR watermark */ |
2434 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) | |
2435 | sky2_write8(hw, STAT_FIFO_ISR_WM, 4); | |
2436 | else | |
2437 | sky2_write8(hw, STAT_FIFO_ISR_WM, 16); | |
cd28ab6a | 2438 | |
290d4de5 | 2439 | sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); |
77b3d6a2 SH |
2440 | sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); |
2441 | sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); | |
cd28ab6a | 2442 | |
793b883e | 2443 | /* enable status unit */ |
cd28ab6a SH |
2444 | sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); |
2445 | ||
2446 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
2447 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
2448 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
2449 | ||
2450 | return 0; | |
2451 | } | |
2452 | ||
28bd181a | 2453 | static u32 sky2_supported_modes(const struct sky2_hw *hw) |
cd28ab6a SH |
2454 | { |
2455 | u32 modes; | |
2456 | if (hw->copper) { | |
793b883e SH |
2457 | modes = SUPPORTED_10baseT_Half |
2458 | | SUPPORTED_10baseT_Full | |
2459 | | SUPPORTED_100baseT_Half | |
2460 | | SUPPORTED_100baseT_Full | |
2461 | | SUPPORTED_Autoneg | SUPPORTED_TP; | |
cd28ab6a SH |
2462 | |
2463 | if (hw->chip_id != CHIP_ID_YUKON_FE) | |
2464 | modes |= SUPPORTED_1000baseT_Half | |
793b883e | 2465 | | SUPPORTED_1000baseT_Full; |
cd28ab6a SH |
2466 | } else |
2467 | modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE | |
793b883e | 2468 | | SUPPORTED_Autoneg; |
cd28ab6a SH |
2469 | return modes; |
2470 | } | |
2471 | ||
793b883e | 2472 | static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
cd28ab6a SH |
2473 | { |
2474 | struct sky2_port *sky2 = netdev_priv(dev); | |
2475 | struct sky2_hw *hw = sky2->hw; | |
2476 | ||
2477 | ecmd->transceiver = XCVR_INTERNAL; | |
2478 | ecmd->supported = sky2_supported_modes(hw); | |
2479 | ecmd->phy_address = PHY_ADDR_MARV; | |
2480 | if (hw->copper) { | |
2481 | ecmd->supported = SUPPORTED_10baseT_Half | |
793b883e SH |
2482 | | SUPPORTED_10baseT_Full |
2483 | | SUPPORTED_100baseT_Half | |
2484 | | SUPPORTED_100baseT_Full | |
2485 | | SUPPORTED_1000baseT_Half | |
2486 | | SUPPORTED_1000baseT_Full | |
2487 | | SUPPORTED_Autoneg | SUPPORTED_TP; | |
cd28ab6a SH |
2488 | ecmd->port = PORT_TP; |
2489 | } else | |
2490 | ecmd->port = PORT_FIBRE; | |
2491 | ||
2492 | ecmd->advertising = sky2->advertising; | |
2493 | ecmd->autoneg = sky2->autoneg; | |
2494 | ecmd->speed = sky2->speed; | |
2495 | ecmd->duplex = sky2->duplex; | |
2496 | return 0; | |
2497 | } | |
2498 | ||
2499 | static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
2500 | { | |
2501 | struct sky2_port *sky2 = netdev_priv(dev); | |
2502 | const struct sky2_hw *hw = sky2->hw; | |
2503 | u32 supported = sky2_supported_modes(hw); | |
2504 | ||
2505 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
2506 | ecmd->advertising = supported; | |
2507 | sky2->duplex = -1; | |
2508 | sky2->speed = -1; | |
2509 | } else { | |
2510 | u32 setting; | |
2511 | ||
793b883e | 2512 | switch (ecmd->speed) { |
cd28ab6a SH |
2513 | case SPEED_1000: |
2514 | if (ecmd->duplex == DUPLEX_FULL) | |
2515 | setting = SUPPORTED_1000baseT_Full; | |
2516 | else if (ecmd->duplex == DUPLEX_HALF) | |
2517 | setting = SUPPORTED_1000baseT_Half; | |
2518 | else | |
2519 | return -EINVAL; | |
2520 | break; | |
2521 | case SPEED_100: | |
2522 | if (ecmd->duplex == DUPLEX_FULL) | |
2523 | setting = SUPPORTED_100baseT_Full; | |
2524 | else if (ecmd->duplex == DUPLEX_HALF) | |
2525 | setting = SUPPORTED_100baseT_Half; | |
2526 | else | |
2527 | return -EINVAL; | |
2528 | break; | |
2529 | ||
2530 | case SPEED_10: | |
2531 | if (ecmd->duplex == DUPLEX_FULL) | |
2532 | setting = SUPPORTED_10baseT_Full; | |
2533 | else if (ecmd->duplex == DUPLEX_HALF) | |
2534 | setting = SUPPORTED_10baseT_Half; | |
2535 | else | |
2536 | return -EINVAL; | |
2537 | break; | |
2538 | default: | |
2539 | return -EINVAL; | |
2540 | } | |
2541 | ||
2542 | if ((setting & supported) == 0) | |
2543 | return -EINVAL; | |
2544 | ||
2545 | sky2->speed = ecmd->speed; | |
2546 | sky2->duplex = ecmd->duplex; | |
2547 | } | |
2548 | ||
2549 | sky2->autoneg = ecmd->autoneg; | |
2550 | sky2->advertising = ecmd->advertising; | |
2551 | ||
1b537565 SH |
2552 | if (netif_running(dev)) |
2553 | sky2_phy_reinit(sky2); | |
cd28ab6a SH |
2554 | |
2555 | return 0; | |
2556 | } | |
2557 | ||
2558 | static void sky2_get_drvinfo(struct net_device *dev, | |
2559 | struct ethtool_drvinfo *info) | |
2560 | { | |
2561 | struct sky2_port *sky2 = netdev_priv(dev); | |
2562 | ||
2563 | strcpy(info->driver, DRV_NAME); | |
2564 | strcpy(info->version, DRV_VERSION); | |
2565 | strcpy(info->fw_version, "N/A"); | |
2566 | strcpy(info->bus_info, pci_name(sky2->hw->pdev)); | |
2567 | } | |
2568 | ||
2569 | static const struct sky2_stat { | |
793b883e SH |
2570 | char name[ETH_GSTRING_LEN]; |
2571 | u16 offset; | |
cd28ab6a SH |
2572 | } sky2_stats[] = { |
2573 | { "tx_bytes", GM_TXO_OK_HI }, | |
2574 | { "rx_bytes", GM_RXO_OK_HI }, | |
2575 | { "tx_broadcast", GM_TXF_BC_OK }, | |
2576 | { "rx_broadcast", GM_RXF_BC_OK }, | |
2577 | { "tx_multicast", GM_TXF_MC_OK }, | |
2578 | { "rx_multicast", GM_RXF_MC_OK }, | |
2579 | { "tx_unicast", GM_TXF_UC_OK }, | |
2580 | { "rx_unicast", GM_RXF_UC_OK }, | |
2581 | { "tx_mac_pause", GM_TXF_MPAUSE }, | |
2582 | { "rx_mac_pause", GM_RXF_MPAUSE }, | |
eadfa7dd | 2583 | { "collisions", GM_TXF_COL }, |
cd28ab6a SH |
2584 | { "late_collision",GM_TXF_LAT_COL }, |
2585 | { "aborted", GM_TXF_ABO_COL }, | |
eadfa7dd | 2586 | { "single_collisions", GM_TXF_SNG_COL }, |
cd28ab6a | 2587 | { "multi_collisions", GM_TXF_MUL_COL }, |
eadfa7dd | 2588 | |
d2604540 | 2589 | { "rx_short", GM_RXF_SHT }, |
cd28ab6a | 2590 | { "rx_runt", GM_RXE_FRAG }, |
eadfa7dd SH |
2591 | { "rx_64_byte_packets", GM_RXF_64B }, |
2592 | { "rx_65_to_127_byte_packets", GM_RXF_127B }, | |
2593 | { "rx_128_to_255_byte_packets", GM_RXF_255B }, | |
2594 | { "rx_256_to_511_byte_packets", GM_RXF_511B }, | |
2595 | { "rx_512_to_1023_byte_packets", GM_RXF_1023B }, | |
2596 | { "rx_1024_to_1518_byte_packets", GM_RXF_1518B }, | |
2597 | { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ }, | |
cd28ab6a | 2598 | { "rx_too_long", GM_RXF_LNG_ERR }, |
eadfa7dd SH |
2599 | { "rx_fifo_overflow", GM_RXE_FIFO_OV }, |
2600 | { "rx_jabber", GM_RXF_JAB_PKT }, | |
cd28ab6a | 2601 | { "rx_fcs_error", GM_RXF_FCS_ERR }, |
eadfa7dd SH |
2602 | |
2603 | { "tx_64_byte_packets", GM_TXF_64B }, | |
2604 | { "tx_65_to_127_byte_packets", GM_TXF_127B }, | |
2605 | { "tx_128_to_255_byte_packets", GM_TXF_255B }, | |
2606 | { "tx_256_to_511_byte_packets", GM_TXF_511B }, | |
2607 | { "tx_512_to_1023_byte_packets", GM_TXF_1023B }, | |
2608 | { "tx_1024_to_1518_byte_packets", GM_TXF_1518B }, | |
2609 | { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ }, | |
2610 | { "tx_fifo_underrun", GM_TXE_FIFO_UR }, | |
cd28ab6a SH |
2611 | }; |
2612 | ||
cd28ab6a SH |
2613 | static u32 sky2_get_rx_csum(struct net_device *dev) |
2614 | { | |
2615 | struct sky2_port *sky2 = netdev_priv(dev); | |
2616 | ||
2617 | return sky2->rx_csum; | |
2618 | } | |
2619 | ||
2620 | static int sky2_set_rx_csum(struct net_device *dev, u32 data) | |
2621 | { | |
2622 | struct sky2_port *sky2 = netdev_priv(dev); | |
2623 | ||
2624 | sky2->rx_csum = data; | |
793b883e | 2625 | |
cd28ab6a SH |
2626 | sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), |
2627 | data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); | |
2628 | ||
2629 | return 0; | |
2630 | } | |
2631 | ||
2632 | static u32 sky2_get_msglevel(struct net_device *netdev) | |
2633 | { | |
2634 | struct sky2_port *sky2 = netdev_priv(netdev); | |
2635 | return sky2->msg_enable; | |
2636 | } | |
2637 | ||
9a7ae0a9 SH |
2638 | static int sky2_nway_reset(struct net_device *dev) |
2639 | { | |
2640 | struct sky2_port *sky2 = netdev_priv(dev); | |
9a7ae0a9 SH |
2641 | |
2642 | if (sky2->autoneg != AUTONEG_ENABLE) | |
2643 | return -EINVAL; | |
2644 | ||
1b537565 | 2645 | sky2_phy_reinit(sky2); |
9a7ae0a9 SH |
2646 | |
2647 | return 0; | |
2648 | } | |
2649 | ||
793b883e | 2650 | static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) |
cd28ab6a SH |
2651 | { |
2652 | struct sky2_hw *hw = sky2->hw; | |
2653 | unsigned port = sky2->port; | |
2654 | int i; | |
2655 | ||
2656 | data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 | |
793b883e | 2657 | | (u64) gma_read32(hw, port, GM_TXO_OK_LO); |
cd28ab6a | 2658 | data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 |
793b883e | 2659 | | (u64) gma_read32(hw, port, GM_RXO_OK_LO); |
cd28ab6a | 2660 | |
793b883e | 2661 | for (i = 2; i < count; i++) |
cd28ab6a SH |
2662 | data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset); |
2663 | } | |
2664 | ||
cd28ab6a SH |
2665 | static void sky2_set_msglevel(struct net_device *netdev, u32 value) |
2666 | { | |
2667 | struct sky2_port *sky2 = netdev_priv(netdev); | |
2668 | sky2->msg_enable = value; | |
2669 | } | |
2670 | ||
2671 | static int sky2_get_stats_count(struct net_device *dev) | |
2672 | { | |
2673 | return ARRAY_SIZE(sky2_stats); | |
2674 | } | |
2675 | ||
2676 | static void sky2_get_ethtool_stats(struct net_device *dev, | |
793b883e | 2677 | struct ethtool_stats *stats, u64 * data) |
cd28ab6a SH |
2678 | { |
2679 | struct sky2_port *sky2 = netdev_priv(dev); | |
2680 | ||
793b883e | 2681 | sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); |
cd28ab6a SH |
2682 | } |
2683 | ||
793b883e | 2684 | static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) |
cd28ab6a SH |
2685 | { |
2686 | int i; | |
2687 | ||
2688 | switch (stringset) { | |
2689 | case ETH_SS_STATS: | |
2690 | for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) | |
2691 | memcpy(data + i * ETH_GSTRING_LEN, | |
2692 | sky2_stats[i].name, ETH_GSTRING_LEN); | |
2693 | break; | |
2694 | } | |
2695 | } | |
2696 | ||
2697 | /* Use hardware MIB variables for critical path statistics and | |
2698 | * transmit feedback not reported at interrupt. | |
2699 | * Other errors are accounted for in interrupt handler. | |
2700 | */ | |
2701 | static struct net_device_stats *sky2_get_stats(struct net_device *dev) | |
2702 | { | |
2703 | struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e | 2704 | u64 data[13]; |
cd28ab6a | 2705 | |
793b883e | 2706 | sky2_phy_stats(sky2, data, ARRAY_SIZE(data)); |
cd28ab6a SH |
2707 | |
2708 | sky2->net_stats.tx_bytes = data[0]; | |
2709 | sky2->net_stats.rx_bytes = data[1]; | |
2710 | sky2->net_stats.tx_packets = data[2] + data[4] + data[6]; | |
2711 | sky2->net_stats.rx_packets = data[3] + data[5] + data[7]; | |
050ff180 | 2712 | sky2->net_stats.multicast = data[3] + data[5]; |
cd28ab6a SH |
2713 | sky2->net_stats.collisions = data[10]; |
2714 | sky2->net_stats.tx_aborted_errors = data[12]; | |
2715 | ||
2716 | return &sky2->net_stats; | |
2717 | } | |
2718 | ||
2719 | static int sky2_set_mac_address(struct net_device *dev, void *p) | |
2720 | { | |
2721 | struct sky2_port *sky2 = netdev_priv(dev); | |
a8ab1ec0 SH |
2722 | struct sky2_hw *hw = sky2->hw; |
2723 | unsigned port = sky2->port; | |
2724 | const struct sockaddr *addr = p; | |
cd28ab6a SH |
2725 | |
2726 | if (!is_valid_ether_addr(addr->sa_data)) | |
2727 | return -EADDRNOTAVAIL; | |
2728 | ||
cd28ab6a | 2729 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); |
a8ab1ec0 | 2730 | memcpy_toio(hw->regs + B2_MAC_1 + port * 8, |
cd28ab6a | 2731 | dev->dev_addr, ETH_ALEN); |
a8ab1ec0 | 2732 | memcpy_toio(hw->regs + B2_MAC_2 + port * 8, |
cd28ab6a | 2733 | dev->dev_addr, ETH_ALEN); |
1b537565 | 2734 | |
a8ab1ec0 SH |
2735 | /* virtual address for data */ |
2736 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); | |
2737 | ||
2738 | /* physical address: used for pause frames */ | |
2739 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); | |
1b537565 SH |
2740 | |
2741 | return 0; | |
cd28ab6a SH |
2742 | } |
2743 | ||
2744 | static void sky2_set_multicast(struct net_device *dev) | |
2745 | { | |
2746 | struct sky2_port *sky2 = netdev_priv(dev); | |
2747 | struct sky2_hw *hw = sky2->hw; | |
2748 | unsigned port = sky2->port; | |
2749 | struct dev_mc_list *list = dev->mc_list; | |
2750 | u16 reg; | |
2751 | u8 filter[8]; | |
2752 | ||
2753 | memset(filter, 0, sizeof(filter)); | |
2754 | ||
2755 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
2756 | reg |= GM_RXCR_UCF_ENA; | |
2757 | ||
d571b694 | 2758 | if (dev->flags & IFF_PROMISC) /* promiscuous */ |
cd28ab6a | 2759 | reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); |
793b883e | 2760 | else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */ |
cd28ab6a | 2761 | memset(filter, 0xff, sizeof(filter)); |
793b883e | 2762 | else if (dev->mc_count == 0) /* no multicast */ |
cd28ab6a SH |
2763 | reg &= ~GM_RXCR_MCF_ENA; |
2764 | else { | |
2765 | int i; | |
2766 | reg |= GM_RXCR_MCF_ENA; | |
2767 | ||
2768 | for (i = 0; list && i < dev->mc_count; i++, list = list->next) { | |
2769 | u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f; | |
793b883e | 2770 | filter[bit / 8] |= 1 << (bit % 8); |
cd28ab6a SH |
2771 | } |
2772 | } | |
2773 | ||
cd28ab6a | 2774 | gma_write16(hw, port, GM_MC_ADDR_H1, |
793b883e | 2775 | (u16) filter[0] | ((u16) filter[1] << 8)); |
cd28ab6a | 2776 | gma_write16(hw, port, GM_MC_ADDR_H2, |
793b883e | 2777 | (u16) filter[2] | ((u16) filter[3] << 8)); |
cd28ab6a | 2778 | gma_write16(hw, port, GM_MC_ADDR_H3, |
793b883e | 2779 | (u16) filter[4] | ((u16) filter[5] << 8)); |
cd28ab6a | 2780 | gma_write16(hw, port, GM_MC_ADDR_H4, |
793b883e | 2781 | (u16) filter[6] | ((u16) filter[7] << 8)); |
cd28ab6a SH |
2782 | |
2783 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
2784 | } | |
2785 | ||
2786 | /* Can have one global because blinking is controlled by | |
2787 | * ethtool and that is always under RTNL mutex | |
2788 | */ | |
91c86df5 | 2789 | static void sky2_led(struct sky2_hw *hw, unsigned port, int on) |
cd28ab6a | 2790 | { |
793b883e SH |
2791 | u16 pg; |
2792 | ||
793b883e SH |
2793 | switch (hw->chip_id) { |
2794 | case CHIP_ID_YUKON_XL: | |
2795 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2796 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2797 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
2798 | on ? (PHY_M_LEDC_LOS_CTRL(1) | | |
2799 | PHY_M_LEDC_INIT_CTRL(7) | | |
2800 | PHY_M_LEDC_STA1_CTRL(7) | | |
2801 | PHY_M_LEDC_STA0_CTRL(7)) | |
2802 | : 0); | |
2803 | ||
2804 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2805 | break; | |
2806 | ||
2807 | default: | |
2808 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); | |
cd28ab6a | 2809 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, |
793b883e SH |
2810 | on ? PHY_M_LED_MO_DUP(MO_LED_ON) | |
2811 | PHY_M_LED_MO_10(MO_LED_ON) | | |
2812 | PHY_M_LED_MO_100(MO_LED_ON) | | |
cd28ab6a | 2813 | PHY_M_LED_MO_1000(MO_LED_ON) | |
793b883e SH |
2814 | PHY_M_LED_MO_RX(MO_LED_ON) |
2815 | : PHY_M_LED_MO_DUP(MO_LED_OFF) | | |
2816 | PHY_M_LED_MO_10(MO_LED_OFF) | | |
2817 | PHY_M_LED_MO_100(MO_LED_OFF) | | |
cd28ab6a SH |
2818 | PHY_M_LED_MO_1000(MO_LED_OFF) | |
2819 | PHY_M_LED_MO_RX(MO_LED_OFF)); | |
2820 | ||
793b883e | 2821 | } |
cd28ab6a SH |
2822 | } |
2823 | ||
2824 | /* blink LED's for finding board */ | |
2825 | static int sky2_phys_id(struct net_device *dev, u32 data) | |
2826 | { | |
2827 | struct sky2_port *sky2 = netdev_priv(dev); | |
2828 | struct sky2_hw *hw = sky2->hw; | |
2829 | unsigned port = sky2->port; | |
793b883e | 2830 | u16 ledctrl, ledover = 0; |
cd28ab6a | 2831 | long ms; |
91c86df5 | 2832 | int interrupted; |
cd28ab6a SH |
2833 | int onoff = 1; |
2834 | ||
793b883e | 2835 | if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)) |
cd28ab6a SH |
2836 | ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT); |
2837 | else | |
2838 | ms = data * 1000; | |
2839 | ||
2840 | /* save initial values */ | |
e07b1aa8 | 2841 | spin_lock_bh(&sky2->phy_lock); |
793b883e SH |
2842 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
2843 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2844 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2845 | ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
2846 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2847 | } else { | |
2848 | ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL); | |
2849 | ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER); | |
2850 | } | |
cd28ab6a | 2851 | |
91c86df5 SH |
2852 | interrupted = 0; |
2853 | while (!interrupted && ms > 0) { | |
cd28ab6a SH |
2854 | sky2_led(hw, port, onoff); |
2855 | onoff = !onoff; | |
2856 | ||
e07b1aa8 | 2857 | spin_unlock_bh(&sky2->phy_lock); |
91c86df5 | 2858 | interrupted = msleep_interruptible(250); |
e07b1aa8 | 2859 | spin_lock_bh(&sky2->phy_lock); |
91c86df5 | 2860 | |
cd28ab6a SH |
2861 | ms -= 250; |
2862 | } | |
2863 | ||
2864 | /* resume regularly scheduled programming */ | |
793b883e SH |
2865 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
2866 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2867 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2868 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl); | |
2869 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2870 | } else { | |
2871 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); | |
2872 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
2873 | } | |
e07b1aa8 | 2874 | spin_unlock_bh(&sky2->phy_lock); |
cd28ab6a SH |
2875 | |
2876 | return 0; | |
2877 | } | |
2878 | ||
2879 | static void sky2_get_pauseparam(struct net_device *dev, | |
2880 | struct ethtool_pauseparam *ecmd) | |
2881 | { | |
2882 | struct sky2_port *sky2 = netdev_priv(dev); | |
2883 | ||
2884 | ecmd->tx_pause = sky2->tx_pause; | |
2885 | ecmd->rx_pause = sky2->rx_pause; | |
2886 | ecmd->autoneg = sky2->autoneg; | |
2887 | } | |
2888 | ||
2889 | static int sky2_set_pauseparam(struct net_device *dev, | |
2890 | struct ethtool_pauseparam *ecmd) | |
2891 | { | |
2892 | struct sky2_port *sky2 = netdev_priv(dev); | |
2893 | int err = 0; | |
2894 | ||
2895 | sky2->autoneg = ecmd->autoneg; | |
2896 | sky2->tx_pause = ecmd->tx_pause != 0; | |
2897 | sky2->rx_pause = ecmd->rx_pause != 0; | |
2898 | ||
1b537565 | 2899 | sky2_phy_reinit(sky2); |
cd28ab6a SH |
2900 | |
2901 | return err; | |
2902 | } | |
2903 | ||
fb17358f SH |
2904 | static int sky2_get_coalesce(struct net_device *dev, |
2905 | struct ethtool_coalesce *ecmd) | |
2906 | { | |
2907 | struct sky2_port *sky2 = netdev_priv(dev); | |
2908 | struct sky2_hw *hw = sky2->hw; | |
2909 | ||
2910 | if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) | |
2911 | ecmd->tx_coalesce_usecs = 0; | |
2912 | else { | |
2913 | u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); | |
2914 | ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); | |
2915 | } | |
2916 | ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); | |
2917 | ||
2918 | if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) | |
2919 | ecmd->rx_coalesce_usecs = 0; | |
2920 | else { | |
2921 | u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); | |
2922 | ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); | |
2923 | } | |
2924 | ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); | |
2925 | ||
2926 | if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) | |
2927 | ecmd->rx_coalesce_usecs_irq = 0; | |
2928 | else { | |
2929 | u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); | |
2930 | ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); | |
2931 | } | |
2932 | ||
2933 | ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); | |
2934 | ||
2935 | return 0; | |
2936 | } | |
2937 | ||
2938 | /* Note: this affect both ports */ | |
2939 | static int sky2_set_coalesce(struct net_device *dev, | |
2940 | struct ethtool_coalesce *ecmd) | |
2941 | { | |
2942 | struct sky2_port *sky2 = netdev_priv(dev); | |
2943 | struct sky2_hw *hw = sky2->hw; | |
77b3d6a2 | 2944 | const u32 tmax = sky2_clk2us(hw, 0x0ffffff); |
fb17358f | 2945 | |
77b3d6a2 SH |
2946 | if (ecmd->tx_coalesce_usecs > tmax || |
2947 | ecmd->rx_coalesce_usecs > tmax || | |
2948 | ecmd->rx_coalesce_usecs_irq > tmax) | |
fb17358f SH |
2949 | return -EINVAL; |
2950 | ||
ff81fbbe | 2951 | if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1) |
fb17358f | 2952 | return -EINVAL; |
ff81fbbe | 2953 | if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING) |
fb17358f | 2954 | return -EINVAL; |
ff81fbbe | 2955 | if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING) |
fb17358f SH |
2956 | return -EINVAL; |
2957 | ||
2958 | if (ecmd->tx_coalesce_usecs == 0) | |
2959 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); | |
2960 | else { | |
2961 | sky2_write32(hw, STAT_TX_TIMER_INI, | |
2962 | sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); | |
2963 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
2964 | } | |
2965 | sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); | |
2966 | ||
2967 | if (ecmd->rx_coalesce_usecs == 0) | |
2968 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); | |
2969 | else { | |
2970 | sky2_write32(hw, STAT_LEV_TIMER_INI, | |
2971 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); | |
2972 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
2973 | } | |
2974 | sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); | |
2975 | ||
2976 | if (ecmd->rx_coalesce_usecs_irq == 0) | |
2977 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); | |
2978 | else { | |
d28d4870 | 2979 | sky2_write32(hw, STAT_ISR_TIMER_INI, |
fb17358f SH |
2980 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); |
2981 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
2982 | } | |
2983 | sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); | |
2984 | return 0; | |
2985 | } | |
2986 | ||
793b883e SH |
2987 | static void sky2_get_ringparam(struct net_device *dev, |
2988 | struct ethtool_ringparam *ering) | |
2989 | { | |
2990 | struct sky2_port *sky2 = netdev_priv(dev); | |
2991 | ||
2992 | ering->rx_max_pending = RX_MAX_PENDING; | |
2993 | ering->rx_mini_max_pending = 0; | |
2994 | ering->rx_jumbo_max_pending = 0; | |
2995 | ering->tx_max_pending = TX_RING_SIZE - 1; | |
2996 | ||
2997 | ering->rx_pending = sky2->rx_pending; | |
2998 | ering->rx_mini_pending = 0; | |
2999 | ering->rx_jumbo_pending = 0; | |
3000 | ering->tx_pending = sky2->tx_pending; | |
3001 | } | |
3002 | ||
3003 | static int sky2_set_ringparam(struct net_device *dev, | |
3004 | struct ethtool_ringparam *ering) | |
3005 | { | |
3006 | struct sky2_port *sky2 = netdev_priv(dev); | |
3007 | int err = 0; | |
3008 | ||
3009 | if (ering->rx_pending > RX_MAX_PENDING || | |
3010 | ering->rx_pending < 8 || | |
3011 | ering->tx_pending < MAX_SKB_TX_LE || | |
3012 | ering->tx_pending > TX_RING_SIZE - 1) | |
3013 | return -EINVAL; | |
3014 | ||
3015 | if (netif_running(dev)) | |
3016 | sky2_down(dev); | |
3017 | ||
3018 | sky2->rx_pending = ering->rx_pending; | |
3019 | sky2->tx_pending = ering->tx_pending; | |
3020 | ||
1b537565 | 3021 | if (netif_running(dev)) { |
793b883e | 3022 | err = sky2_up(dev); |
1b537565 SH |
3023 | if (err) |
3024 | dev_close(dev); | |
6ed995bb SH |
3025 | else |
3026 | sky2_set_multicast(dev); | |
1b537565 | 3027 | } |
793b883e SH |
3028 | |
3029 | return err; | |
3030 | } | |
3031 | ||
793b883e SH |
3032 | static int sky2_get_regs_len(struct net_device *dev) |
3033 | { | |
6e4cbb34 | 3034 | return 0x4000; |
793b883e SH |
3035 | } |
3036 | ||
3037 | /* | |
3038 | * Returns copy of control register region | |
6e4cbb34 | 3039 | * Note: access to the RAM address register set will cause timeouts. |
793b883e SH |
3040 | */ |
3041 | static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
3042 | void *p) | |
3043 | { | |
3044 | const struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e | 3045 | const void __iomem *io = sky2->hw->regs; |
793b883e | 3046 | |
6e4cbb34 | 3047 | BUG_ON(regs->len < B3_RI_WTO_R1); |
793b883e | 3048 | regs->version = 1; |
6e4cbb34 | 3049 | memset(p, 0, regs->len); |
793b883e | 3050 | |
6e4cbb34 SH |
3051 | memcpy_fromio(p, io, B3_RAM_ADDR); |
3052 | ||
3053 | memcpy_fromio(p + B3_RI_WTO_R1, | |
3054 | io + B3_RI_WTO_R1, | |
3055 | regs->len - B3_RI_WTO_R1); | |
793b883e | 3056 | } |
cd28ab6a SH |
3057 | |
3058 | static struct ethtool_ops sky2_ethtool_ops = { | |
793b883e SH |
3059 | .get_settings = sky2_get_settings, |
3060 | .set_settings = sky2_set_settings, | |
3061 | .get_drvinfo = sky2_get_drvinfo, | |
3062 | .get_msglevel = sky2_get_msglevel, | |
3063 | .set_msglevel = sky2_set_msglevel, | |
9a7ae0a9 | 3064 | .nway_reset = sky2_nway_reset, |
793b883e SH |
3065 | .get_regs_len = sky2_get_regs_len, |
3066 | .get_regs = sky2_get_regs, | |
3067 | .get_link = ethtool_op_get_link, | |
3068 | .get_sg = ethtool_op_get_sg, | |
3069 | .set_sg = ethtool_op_set_sg, | |
3070 | .get_tx_csum = ethtool_op_get_tx_csum, | |
3071 | .set_tx_csum = ethtool_op_set_tx_csum, | |
3072 | .get_tso = ethtool_op_get_tso, | |
3073 | .set_tso = ethtool_op_set_tso, | |
3074 | .get_rx_csum = sky2_get_rx_csum, | |
3075 | .set_rx_csum = sky2_set_rx_csum, | |
3076 | .get_strings = sky2_get_strings, | |
fb17358f SH |
3077 | .get_coalesce = sky2_get_coalesce, |
3078 | .set_coalesce = sky2_set_coalesce, | |
793b883e SH |
3079 | .get_ringparam = sky2_get_ringparam, |
3080 | .set_ringparam = sky2_set_ringparam, | |
cd28ab6a SH |
3081 | .get_pauseparam = sky2_get_pauseparam, |
3082 | .set_pauseparam = sky2_set_pauseparam, | |
793b883e | 3083 | .phys_id = sky2_phys_id, |
cd28ab6a SH |
3084 | .get_stats_count = sky2_get_stats_count, |
3085 | .get_ethtool_stats = sky2_get_ethtool_stats, | |
2995bfb7 | 3086 | .get_perm_addr = ethtool_op_get_perm_addr, |
cd28ab6a SH |
3087 | }; |
3088 | ||
3089 | /* Initialize network device */ | |
3090 | static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw, | |
3091 | unsigned port, int highmem) | |
3092 | { | |
3093 | struct sky2_port *sky2; | |
3094 | struct net_device *dev = alloc_etherdev(sizeof(*sky2)); | |
3095 | ||
3096 | if (!dev) { | |
3097 | printk(KERN_ERR "sky2 etherdev alloc failed"); | |
3098 | return NULL; | |
3099 | } | |
3100 | ||
3101 | SET_MODULE_OWNER(dev); | |
3102 | SET_NETDEV_DEV(dev, &hw->pdev->dev); | |
ef743d33 | 3103 | dev->irq = hw->pdev->irq; |
cd28ab6a SH |
3104 | dev->open = sky2_up; |
3105 | dev->stop = sky2_down; | |
ef743d33 | 3106 | dev->do_ioctl = sky2_ioctl; |
cd28ab6a SH |
3107 | dev->hard_start_xmit = sky2_xmit_frame; |
3108 | dev->get_stats = sky2_get_stats; | |
3109 | dev->set_multicast_list = sky2_set_multicast; | |
3110 | dev->set_mac_address = sky2_set_mac_address; | |
3111 | dev->change_mtu = sky2_change_mtu; | |
3112 | SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops); | |
3113 | dev->tx_timeout = sky2_tx_timeout; | |
3114 | dev->watchdog_timeo = TX_WATCHDOG; | |
3115 | if (port == 0) | |
3116 | dev->poll = sky2_poll; | |
3117 | dev->weight = NAPI_WEIGHT; | |
3118 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3119 | dev->poll_controller = sky2_netpoll; | |
3120 | #endif | |
cd28ab6a SH |
3121 | |
3122 | sky2 = netdev_priv(dev); | |
3123 | sky2->netdev = dev; | |
3124 | sky2->hw = hw; | |
3125 | sky2->msg_enable = netif_msg_init(debug, default_msg); | |
3126 | ||
3127 | spin_lock_init(&sky2->tx_lock); | |
3128 | /* Auto speed and flow control */ | |
3129 | sky2->autoneg = AUTONEG_ENABLE; | |
585b5601 | 3130 | sky2->tx_pause = 1; |
cd28ab6a SH |
3131 | sky2->rx_pause = 1; |
3132 | sky2->duplex = -1; | |
3133 | sky2->speed = -1; | |
3134 | sky2->advertising = sky2_supported_modes(hw); | |
ee7abb04 | 3135 | sky2->rx_csum = 1; |
75d070c5 | 3136 | |
e07b1aa8 | 3137 | spin_lock_init(&sky2->phy_lock); |
793b883e | 3138 | sky2->tx_pending = TX_DEF_PENDING; |
290d4de5 | 3139 | sky2->rx_pending = RX_DEF_PENDING; |
734d1868 | 3140 | sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN); |
cd28ab6a SH |
3141 | |
3142 | hw->dev[port] = dev; | |
3143 | ||
3144 | sky2->port = port; | |
3145 | ||
5a5b1ea0 | 3146 | dev->features |= NETIF_F_LLTX; |
3147 | if (hw->chip_id != CHIP_ID_YUKON_EC_U) | |
3148 | dev->features |= NETIF_F_TSO; | |
cd28ab6a SH |
3149 | if (highmem) |
3150 | dev->features |= NETIF_F_HIGHDMA; | |
793b883e | 3151 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; |
cd28ab6a | 3152 | |
d1f13708 | 3153 | #ifdef SKY2_VLAN_TAG_USED |
3154 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
3155 | dev->vlan_rx_register = sky2_vlan_rx_register; | |
3156 | dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid; | |
3157 | #endif | |
3158 | ||
cd28ab6a | 3159 | /* read the mac address */ |
793b883e | 3160 | memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); |
2995bfb7 | 3161 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
cd28ab6a SH |
3162 | |
3163 | /* device is off until link detection */ | |
3164 | netif_carrier_off(dev); | |
3165 | netif_stop_queue(dev); | |
3166 | ||
3167 | return dev; | |
3168 | } | |
3169 | ||
28bd181a | 3170 | static void __devinit sky2_show_addr(struct net_device *dev) |
cd28ab6a SH |
3171 | { |
3172 | const struct sky2_port *sky2 = netdev_priv(dev); | |
3173 | ||
3174 | if (netif_msg_probe(sky2)) | |
3175 | printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n", | |
3176 | dev->name, | |
3177 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], | |
3178 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); | |
3179 | } | |
3180 | ||
fb2690a9 SH |
3181 | /* Handle software interrupt used during MSI test */ |
3182 | static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id, | |
3183 | struct pt_regs *regs) | |
3184 | { | |
3185 | struct sky2_hw *hw = dev_id; | |
3186 | u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2); | |
3187 | ||
3188 | if (status == 0) | |
3189 | return IRQ_NONE; | |
3190 | ||
3191 | if (status & Y2_IS_IRQ_SW) { | |
3192 | hw->msi_detected = 1; | |
3193 | wake_up(&hw->msi_wait); | |
3194 | sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); | |
3195 | } | |
3196 | sky2_write32(hw, B0_Y2_SP_ICR, 2); | |
3197 | ||
3198 | return IRQ_HANDLED; | |
3199 | } | |
3200 | ||
3201 | /* Test interrupt path by forcing a a software IRQ */ | |
3202 | static int __devinit sky2_test_msi(struct sky2_hw *hw) | |
3203 | { | |
3204 | struct pci_dev *pdev = hw->pdev; | |
3205 | int err; | |
3206 | ||
bb507fe1 | 3207 | init_waitqueue_head (&hw->msi_wait); |
3208 | ||
fb2690a9 SH |
3209 | sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); |
3210 | ||
1fb9df5d | 3211 | err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw); |
fb2690a9 SH |
3212 | if (err) { |
3213 | printk(KERN_ERR PFX "%s: cannot assign irq %d\n", | |
3214 | pci_name(pdev), pdev->irq); | |
3215 | return err; | |
3216 | } | |
3217 | ||
fb2690a9 | 3218 | sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); |
bb507fe1 | 3219 | sky2_read8(hw, B0_CTST); |
fb2690a9 SH |
3220 | |
3221 | wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10); | |
3222 | ||
3223 | if (!hw->msi_detected) { | |
3224 | /* MSI test failed, go back to INTx mode */ | |
3225 | printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, " | |
3226 | "switching to INTx mode. Please report this failure to " | |
3227 | "the PCI maintainer and include system chipset information.\n", | |
3228 | pci_name(pdev)); | |
3229 | ||
3230 | err = -EOPNOTSUPP; | |
3231 | sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); | |
3232 | } | |
3233 | ||
3234 | sky2_write32(hw, B0_IMSK, 0); | |
3235 | ||
3236 | free_irq(pdev->irq, hw); | |
3237 | ||
3238 | return err; | |
3239 | } | |
3240 | ||
cd28ab6a SH |
3241 | static int __devinit sky2_probe(struct pci_dev *pdev, |
3242 | const struct pci_device_id *ent) | |
3243 | { | |
793b883e | 3244 | struct net_device *dev, *dev1 = NULL; |
cd28ab6a | 3245 | struct sky2_hw *hw; |
5afa0a9c | 3246 | int err, pm_cap, using_dac = 0; |
cd28ab6a | 3247 | |
793b883e SH |
3248 | err = pci_enable_device(pdev); |
3249 | if (err) { | |
cd28ab6a SH |
3250 | printk(KERN_ERR PFX "%s cannot enable PCI device\n", |
3251 | pci_name(pdev)); | |
3252 | goto err_out; | |
3253 | } | |
3254 | ||
793b883e SH |
3255 | err = pci_request_regions(pdev, DRV_NAME); |
3256 | if (err) { | |
cd28ab6a SH |
3257 | printk(KERN_ERR PFX "%s cannot obtain PCI resources\n", |
3258 | pci_name(pdev)); | |
793b883e | 3259 | goto err_out; |
cd28ab6a SH |
3260 | } |
3261 | ||
3262 | pci_set_master(pdev); | |
3263 | ||
5afa0a9c | 3264 | /* Find power-management capability. */ |
3265 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
3266 | if (pm_cap == 0) { | |
3267 | printk(KERN_ERR PFX "Cannot find PowerManagement capability, " | |
3268 | "aborting.\n"); | |
3269 | err = -EIO; | |
3270 | goto err_out_free_regions; | |
3271 | } | |
3272 | ||
d1f3d4dd SH |
3273 | if (sizeof(dma_addr_t) > sizeof(u32) && |
3274 | !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) { | |
3275 | using_dac = 1; | |
3276 | err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
3277 | if (err < 0) { | |
3278 | printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA " | |
3279 | "for consistent allocations\n", pci_name(pdev)); | |
3280 | goto err_out_free_regions; | |
3281 | } | |
cd28ab6a | 3282 | |
d1f3d4dd | 3283 | } else { |
cd28ab6a SH |
3284 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
3285 | if (err) { | |
3286 | printk(KERN_ERR PFX "%s no usable DMA configuration\n", | |
3287 | pci_name(pdev)); | |
3288 | goto err_out_free_regions; | |
3289 | } | |
3290 | } | |
d1f3d4dd | 3291 | |
cd28ab6a | 3292 | err = -ENOMEM; |
6aad85d6 | 3293 | hw = kzalloc(sizeof(*hw), GFP_KERNEL); |
cd28ab6a SH |
3294 | if (!hw) { |
3295 | printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n", | |
3296 | pci_name(pdev)); | |
3297 | goto err_out_free_regions; | |
3298 | } | |
3299 | ||
cd28ab6a | 3300 | hw->pdev = pdev; |
cd28ab6a SH |
3301 | |
3302 | hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); | |
3303 | if (!hw->regs) { | |
3304 | printk(KERN_ERR PFX "%s: cannot map device registers\n", | |
3305 | pci_name(pdev)); | |
3306 | goto err_out_free_hw; | |
3307 | } | |
5afa0a9c | 3308 | hw->pm_cap = pm_cap; |
cd28ab6a | 3309 | |
56a645cc SH |
3310 | #ifdef __BIG_ENDIAN |
3311 | /* byte swap descriptors in hardware */ | |
3312 | { | |
3313 | u32 reg; | |
3314 | ||
3315 | reg = sky2_pci_read32(hw, PCI_DEV_REG2); | |
3316 | reg |= PCI_REV_DESC; | |
3317 | sky2_pci_write32(hw, PCI_DEV_REG2, reg); | |
3318 | } | |
3319 | #endif | |
3320 | ||
08c06d8a SH |
3321 | /* ring for status responses */ |
3322 | hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES, | |
3323 | &hw->st_dma); | |
3324 | if (!hw->st_le) | |
3325 | goto err_out_iounmap; | |
3326 | ||
cd28ab6a SH |
3327 | err = sky2_reset(hw); |
3328 | if (err) | |
793b883e | 3329 | goto err_out_iounmap; |
cd28ab6a | 3330 | |
7c7459d1 GKH |
3331 | printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n", |
3332 | DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0), | |
3333 | pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL], | |
793b883e | 3334 | hw->chip_id, hw->chip_rev); |
cd28ab6a | 3335 | |
793b883e SH |
3336 | dev = sky2_init_netdev(hw, 0, using_dac); |
3337 | if (!dev) | |
cd28ab6a SH |
3338 | goto err_out_free_pci; |
3339 | ||
793b883e SH |
3340 | err = register_netdev(dev); |
3341 | if (err) { | |
cd28ab6a SH |
3342 | printk(KERN_ERR PFX "%s: cannot register net device\n", |
3343 | pci_name(pdev)); | |
3344 | goto err_out_free_netdev; | |
3345 | } | |
3346 | ||
3347 | sky2_show_addr(dev); | |
3348 | ||
3349 | if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) { | |
3350 | if (register_netdev(dev1) == 0) | |
3351 | sky2_show_addr(dev1); | |
3352 | else { | |
3353 | /* Failure to register second port need not be fatal */ | |
793b883e SH |
3354 | printk(KERN_WARNING PFX |
3355 | "register of second port failed\n"); | |
cd28ab6a SH |
3356 | hw->dev[1] = NULL; |
3357 | free_netdev(dev1); | |
3358 | } | |
3359 | } | |
3360 | ||
fb2690a9 SH |
3361 | if (!disable_msi && pci_enable_msi(pdev) == 0) { |
3362 | err = sky2_test_msi(hw); | |
3363 | if (err == -EOPNOTSUPP) | |
3364 | pci_disable_msi(pdev); | |
3365 | else if (err) | |
3366 | goto err_out_unregister; | |
3367 | } | |
3368 | ||
1fb9df5d | 3369 | err = request_irq(pdev->irq, sky2_intr, IRQF_SHARED, DRV_NAME, hw); |
793b883e SH |
3370 | if (err) { |
3371 | printk(KERN_ERR PFX "%s: cannot assign irq %d\n", | |
3372 | pci_name(pdev), pdev->irq); | |
3373 | goto err_out_unregister; | |
3374 | } | |
3375 | ||
e07b1aa8 | 3376 | sky2_write32(hw, B0_IMSK, Y2_IS_BASE); |
793b883e | 3377 | |
01bd7564 | 3378 | setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw); |
eb35cf60 | 3379 | sky2_idle_start(hw); |
d27ed387 | 3380 | |
793b883e SH |
3381 | pci_set_drvdata(pdev, hw); |
3382 | ||
cd28ab6a SH |
3383 | return 0; |
3384 | ||
793b883e | 3385 | err_out_unregister: |
fb2690a9 | 3386 | pci_disable_msi(pdev); |
793b883e SH |
3387 | if (dev1) { |
3388 | unregister_netdev(dev1); | |
3389 | free_netdev(dev1); | |
3390 | } | |
3391 | unregister_netdev(dev); | |
cd28ab6a SH |
3392 | err_out_free_netdev: |
3393 | free_netdev(dev); | |
cd28ab6a | 3394 | err_out_free_pci: |
793b883e | 3395 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
cd28ab6a SH |
3396 | pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); |
3397 | err_out_iounmap: | |
3398 | iounmap(hw->regs); | |
3399 | err_out_free_hw: | |
3400 | kfree(hw); | |
3401 | err_out_free_regions: | |
3402 | pci_release_regions(pdev); | |
cd28ab6a | 3403 | pci_disable_device(pdev); |
cd28ab6a SH |
3404 | err_out: |
3405 | return err; | |
3406 | } | |
3407 | ||
3408 | static void __devexit sky2_remove(struct pci_dev *pdev) | |
3409 | { | |
793b883e | 3410 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
cd28ab6a SH |
3411 | struct net_device *dev0, *dev1; |
3412 | ||
793b883e | 3413 | if (!hw) |
cd28ab6a SH |
3414 | return; |
3415 | ||
d27ed387 SH |
3416 | del_timer_sync(&hw->idle_timer); |
3417 | ||
3418 | sky2_write32(hw, B0_IMSK, 0); | |
72cb8529 SH |
3419 | synchronize_irq(hw->pdev->irq); |
3420 | ||
cd28ab6a | 3421 | dev0 = hw->dev[0]; |
793b883e SH |
3422 | dev1 = hw->dev[1]; |
3423 | if (dev1) | |
3424 | unregister_netdev(dev1); | |
cd28ab6a SH |
3425 | unregister_netdev(dev0); |
3426 | ||
5afa0a9c | 3427 | sky2_set_power_state(hw, PCI_D3hot); |
cd28ab6a | 3428 | sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); |
793b883e | 3429 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
5afa0a9c | 3430 | sky2_read8(hw, B0_CTST); |
cd28ab6a SH |
3431 | |
3432 | free_irq(pdev->irq, hw); | |
fb2690a9 | 3433 | pci_disable_msi(pdev); |
793b883e | 3434 | pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); |
cd28ab6a SH |
3435 | pci_release_regions(pdev); |
3436 | pci_disable_device(pdev); | |
793b883e | 3437 | |
cd28ab6a SH |
3438 | if (dev1) |
3439 | free_netdev(dev1); | |
3440 | free_netdev(dev0); | |
3441 | iounmap(hw->regs); | |
3442 | kfree(hw); | |
5afa0a9c | 3443 | |
cd28ab6a SH |
3444 | pci_set_drvdata(pdev, NULL); |
3445 | } | |
3446 | ||
3447 | #ifdef CONFIG_PM | |
3448 | static int sky2_suspend(struct pci_dev *pdev, pm_message_t state) | |
3449 | { | |
793b883e | 3450 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
5afa0a9c | 3451 | int i; |
2ccc99b7 SH |
3452 | pci_power_t pstate = pci_choose_state(pdev, state); |
3453 | ||
3454 | if (!(pstate == PCI_D3hot || pstate == PCI_D3cold)) | |
3455 | return -EINVAL; | |
cd28ab6a | 3456 | |
eb35cf60 | 3457 | del_timer_sync(&hw->idle_timer); |
6a5706b9 | 3458 | netif_poll_disable(hw->dev[0]); |
eb35cf60 | 3459 | |
f05267e7 | 3460 | for (i = 0; i < hw->ports; i++) { |
cd28ab6a SH |
3461 | struct net_device *dev = hw->dev[i]; |
3462 | ||
6a5706b9 | 3463 | if (netif_running(dev)) { |
5afa0a9c | 3464 | sky2_down(dev); |
cd28ab6a | 3465 | netif_device_detach(dev); |
cd28ab6a SH |
3466 | } |
3467 | } | |
3468 | ||
8ab8fca2 | 3469 | sky2_write32(hw, B0_IMSK, 0); |
d374c1c1 | 3470 | pci_save_state(pdev); |
2ccc99b7 SH |
3471 | sky2_set_power_state(hw, pstate); |
3472 | return 0; | |
cd28ab6a SH |
3473 | } |
3474 | ||
3475 | static int sky2_resume(struct pci_dev *pdev) | |
3476 | { | |
793b883e | 3477 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
08c06d8a | 3478 | int i, err; |
cd28ab6a | 3479 | |
cd28ab6a SH |
3480 | pci_restore_state(pdev); |
3481 | pci_enable_wake(pdev, PCI_D0, 0); | |
2ccc99b7 | 3482 | sky2_set_power_state(hw, PCI_D0); |
cd28ab6a | 3483 | |
08c06d8a SH |
3484 | err = sky2_reset(hw); |
3485 | if (err) | |
3486 | goto out; | |
cd28ab6a | 3487 | |
8ab8fca2 SH |
3488 | sky2_write32(hw, B0_IMSK, Y2_IS_BASE); |
3489 | ||
f05267e7 | 3490 | for (i = 0; i < hw->ports; i++) { |
cd28ab6a | 3491 | struct net_device *dev = hw->dev[i]; |
6a5706b9 | 3492 | if (netif_running(dev)) { |
08c06d8a | 3493 | netif_device_attach(dev); |
88d11360 | 3494 | |
08c06d8a SH |
3495 | err = sky2_up(dev); |
3496 | if (err) { | |
3497 | printk(KERN_ERR PFX "%s: could not up: %d\n", | |
3498 | dev->name, err); | |
3499 | dev_close(dev); | |
eb35cf60 | 3500 | goto out; |
5afa0a9c | 3501 | } |
cd28ab6a SH |
3502 | } |
3503 | } | |
eb35cf60 | 3504 | |
6a5706b9 | 3505 | netif_poll_enable(hw->dev[0]); |
eb35cf60 | 3506 | sky2_idle_start(hw); |
08c06d8a SH |
3507 | out: |
3508 | return err; | |
cd28ab6a SH |
3509 | } |
3510 | #endif | |
3511 | ||
3512 | static struct pci_driver sky2_driver = { | |
793b883e SH |
3513 | .name = DRV_NAME, |
3514 | .id_table = sky2_id_table, | |
3515 | .probe = sky2_probe, | |
3516 | .remove = __devexit_p(sky2_remove), | |
cd28ab6a | 3517 | #ifdef CONFIG_PM |
793b883e SH |
3518 | .suspend = sky2_suspend, |
3519 | .resume = sky2_resume, | |
cd28ab6a SH |
3520 | #endif |
3521 | }; | |
3522 | ||
3523 | static int __init sky2_init_module(void) | |
3524 | { | |
50241c4c | 3525 | return pci_register_driver(&sky2_driver); |
cd28ab6a SH |
3526 | } |
3527 | ||
3528 | static void __exit sky2_cleanup_module(void) | |
3529 | { | |
3530 | pci_unregister_driver(&sky2_driver); | |
3531 | } | |
3532 | ||
3533 | module_init(sky2_init_module); | |
3534 | module_exit(sky2_cleanup_module); | |
3535 | ||
3536 | MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); | |
3537 | MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>"); | |
3538 | MODULE_LICENSE("GPL"); | |
5f4f9dc1 | 3539 | MODULE_VERSION(DRV_VERSION); |