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signals: consolidate checks for whether or not to ignore a signal
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
3cf26753 42#include <linux/debugfs.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
bcc52894 54#define DRV_VERSION "1.21"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
793b883e
SH		 67
68#define TX_RING_SIZE 512
69#define TX_DEF_PENDING (TX_RING_SIZE - 1)
70#define TX_MIN_PENDING 64
b19666d9 71#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 72
793b883e 73#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 74#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 75#define TX_WATCHDOG (5 * HZ)
76#define NAPI_WEIGHT 64
77#define PHY_RETRIES 1000
78
f4331a6d
SH		 79#define SKY2_EEPROM_MAGIC 0x9955aabb
80
81
cb5d9547
SH		 82#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
cd28ab6a 84static const u32 default_msg =
793b883e
SH		 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 88
793b883e 89static int debug = -1; /* defaults above */
cd28ab6a
SH		 90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
14d0263f 93static int copybreak __read_mostly = 128;
bdb5c58e
SH		 94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
fb2690a9
SH		 97static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
cd28ab6a 101static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
e5b74c7d 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
cd28ab6a
SH		 139 { 0 }
140};
793b883e 141
cd28ab6a
SH		 142MODULE_DEVICE_TABLE(pci, sky2_id_table);
143
144/* Avoid conditionals by using array */
145static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
146static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 147static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 148
92f965e8
SH		 149/* This driver supports yukon2 chipset only */
150static const char *yukon2_name[] = {
151 "XL", /* 0xb3 */
152 "EC Ultra", /* 0xb4 */
93745494 153 "Extreme", /* 0xb5 */
92f965e8
SH		 154 "EC", /* 0xb6 */
155 "FE", /* 0xb7 */
05745c4a 156 "FE+", /* 0xb8 */
c63eddb2 157 "Supreme", /* 0xb9 */
793b883e
SH		 158};
159
d1b139c0
SH		 160static void sky2_set_multicast(struct net_device *dev);
161
af043aa5 162/* Access to PHY via serial interconnect */
ef743d33 163static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 164{
165 int i;
166
167 gma_write16(hw, port, GM_SMI_DATA, val);
168 gma_write16(hw, port, GM_SMI_CTRL,
169 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
170
171 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 172 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
173 if (ctrl == 0xffff)
174 goto io_error;
175
176 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 177 return 0;
af043aa5
SH		 178
179 udelay(10);
cd28ab6a 180 }
ef743d33 181
af043aa5 182 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 183 return -ETIMEDOUT;
af043aa5
SH		 184
185io_error:
186 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
187 return -EIO;
cd28ab6a
SH		 188}
189
ef743d33 190static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 191{
192 int i;
193
793b883e 194 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 195 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
196
197 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 198 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
199 if (ctrl == 0xffff)
200 goto io_error;
201
202 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33 203 *val = gma_read16(hw, port, GM_SMI_DATA);
204 return 0;
205 }
206
af043aa5 207 udelay(10);
cd28ab6a
SH		 208 }
209
af043aa5 210 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 211 return -ETIMEDOUT;
af043aa5
SH		 212io_error:
213 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
214 return -EIO;
ef743d33 215}
216
af043aa5 217static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33 218{
219 u16 v;
af043aa5 220 __gm_phy_read(hw, port, reg, &v);
ef743d33 221 return v;
cd28ab6a
SH		 222}
223
5afa0a9c 224
ae306cca
SH		 225static void sky2_power_on(struct sky2_hw *hw)
226{
227 /* switch power to VCC (WA for VAUX problem) */
228 sky2_write8(hw, B0_POWER_CTRL,
229 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 230
ae306cca
SH		 231 /* disable Core Clock Division, */
232 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 233
ae306cca
SH		 234 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
235 /* enable bits are inverted */
236 sky2_write8(hw, B2_Y2_CLK_GATE,
237 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
238 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
239 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
240 else
241 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 242
ea76e635 243 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 244 u32 reg;
5afa0a9c 245
b32f40c4 246 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 247
b32f40c4 248 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 249 /* set all bits to 0 except bits 15..12 and 8 */
250 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 251 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 252
b32f40c4 253 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 254 /* set all bits to 0 except bits 28 & 27 */
255 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 256 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 257
b32f40c4 258 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 259
260 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
261 reg = sky2_read32(hw, B2_GP_IO);
262 reg |= GLB_GPIO_STAT_RACE_DIS;
263 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 264
265 sky2_read32(hw, B2_GP_IO);
5afa0a9c 266 }
ae306cca 267}
5afa0a9c 268
ae306cca
SH		 269static void sky2_power_aux(struct sky2_hw *hw)
270{
271 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
272 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
273 else
274 /* enable bits are inverted */
275 sky2_write8(hw, B2_Y2_CLK_GATE,
276 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
277 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
278 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
279
280 /* switch power to VAUX */
281 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
282 sky2_write8(hw, B0_POWER_CTRL,
283 (PC_VAUX_ENA | PC_VCC_ENA |
284 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c 285}
286
d3bcfbeb 287static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 288{
289 u16 reg;
290
291 /* disable all GMAC IRQ's */
292 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 293
cd28ab6a
SH		 294 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
295 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
298
299 reg = gma_read16(hw, port, GM_RX_CTRL);
300 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
301 gma_write16(hw, port, GM_RX_CTRL, reg);
302}
303
16ad91e1
SH		 304/* flow control to advertise bits */
305static const u16 copper_fc_adv[] = {
306 [FC_NONE] = 0,
307 [FC_TX] = PHY_M_AN_ASP,
308 [FC_RX] = PHY_M_AN_PC,
309 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
310};
311
312/* flow control to advertise bits when using 1000BaseX */
313static const u16 fiber_fc_adv[] = {
df3fe1f3 314 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 315 [FC_TX] = PHY_M_P_ASYM_MD_X,
316 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 317 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 318};
319
320/* flow control to GMA disable bits */
321static const u16 gm_fc_disable[] = {
322 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
323 [FC_TX] = GM_GPCR_FC_RX_DIS,
324 [FC_RX] = GM_GPCR_FC_TX_DIS,
325 [FC_BOTH] = 0,
326};
327
328
cd28ab6a
SH		 329static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
330{
331 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 332 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 333
ea76e635
SH		 334 if (sky2->autoneg == AUTONEG_ENABLE &&
335 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 336 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
337
338 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 339 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 340 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
341
53419c68 342 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 343 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 344 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 345 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
346 else
53419c68
SH		 347 /* set master & slave downshift counter to 1x */
348 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 349
350 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
351 }
352
353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 354 if (sky2_is_copper(hw)) {
05745c4a 355 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 356 /* enable automatic crossover */
357 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 358
359 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
360 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
361 u16 spec;
362
363 /* Enable Class A driver for FE+ A0 */
364 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
365 spec |= PHY_M_FESC_SEL_CL_A;
366 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
367 }
cd28ab6a
SH		 368 } else {
369 /* disable energy detect */
370 ctrl &= ~PHY_M_PC_EN_DET_MSK;
371
372 /* enable automatic crossover */
373 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
374
53419c68 375 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 376 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 377 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 378 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 379 ctrl &= ~PHY_M_PC_DSC_MSK;
380 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
381 }
382 }
cd28ab6a
SH		 383 } else {
384 /* workaround for deviation #4.88 (CRC errors) */
385 /* disable Automatic Crossover */
386
387 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 388 }
cd28ab6a 389
b89165f2
SH		 390 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
391
392 /* special setup for PHY 88E1112 Fiber */
ea76e635 393 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 394 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 395
b89165f2
SH		 396 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
397 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl &= ~PHY_M_MAC_MD_MSK;
400 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
401 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
402
403 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 404 /* select page 1 to access Fiber registers */
405 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 406
407 /* for SFP-module set SIGDET polarity to low */
408 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
409 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 410 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 411 }
b89165f2
SH		 412
413 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 414 }
415
7800fddc 416 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 417 ct1000 = 0;
418 adv = PHY_AN_CSMA;
2eaba1a2 419 reg = 0;
cd28ab6a
SH		 420
421 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 422 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 423 if (sky2->advertising & ADVERTISED_1000baseT_Full)
424 ct1000 |= PHY_M_1000C_AFD;
425 if (sky2->advertising & ADVERTISED_1000baseT_Half)
426 ct1000 |= PHY_M_1000C_AHD;
427 if (sky2->advertising & ADVERTISED_100baseT_Full)
428 adv |= PHY_M_AN_100_FD;
429 if (sky2->advertising & ADVERTISED_100baseT_Half)
430 adv |= PHY_M_AN_100_HD;
431 if (sky2->advertising & ADVERTISED_10baseT_Full)
432 adv |= PHY_M_AN_10_FD;
433 if (sky2->advertising & ADVERTISED_10baseT_Half)
434 adv |= PHY_M_AN_10_HD;
709c6e7b 435
16ad91e1 436 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 437 } else { /* special defines for FIBER (88E1040S only) */
438 if (sky2->advertising & ADVERTISED_1000baseT_Full)
439 adv |= PHY_M_AN_1000X_AFD;
440 if (sky2->advertising & ADVERTISED_1000baseT_Half)
441 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 442
16ad91e1 443 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 444 }
cd28ab6a
SH		 445
446 /* Restart Auto-negotiation */
447 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
448 } else {
449 /* forced speed/duplex settings */
450 ct1000 = PHY_M_1000C_MSE;
451
2eaba1a2
SH		 452 /* Disable auto update for duplex flow control and speed */
453 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 454
455 switch (sky2->speed) {
456 case SPEED_1000:
457 ctrl |= PHY_CT_SP1000;
2eaba1a2 458 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 459 break;
460 case SPEED_100:
461 ctrl |= PHY_CT_SP100;
2eaba1a2 462 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 463 break;
464 }
465
2eaba1a2
SH		 466 if (sky2->duplex == DUPLEX_FULL) {
467 reg |= GM_GPCR_DUP_FULL;
468 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 469 } else if (sky2->speed < SPEED_1000)
470 sky2->flow_mode = FC_NONE;
2eaba1a2 471
2eaba1a2 472
16ad91e1 473 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 474
475 /* Forward pause packets to GMAC? */
16ad91e1 476 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 477 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
478 else
479 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 480 }
481
2eaba1a2
SH		 482 gma_write16(hw, port, GM_GP_CTRL, reg);
483
05745c4a 484 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 485 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
486
487 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
488 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
489
490 /* Setup Phy LED's */
491 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
492 ledover = 0;
493
494 switch (hw->chip_id) {
495 case CHIP_ID_YUKON_FE:
496 /* on 88E3082 these bits are at 11..9 (shifted left) */
497 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
498
499 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
500
501 /* delete ACT LED control bits */
502 ctrl &= ~PHY_M_FELP_LED1_MSK;
503 /* change ACT LED control to blink mode */
504 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
505 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
506 break;
507
05745c4a
SH		 508 case CHIP_ID_YUKON_FE_P:
509 /* Enable Link Partner Next Page */
510 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
511 ctrl |= PHY_M_PC_ENA_LIP_NP;
512
513 /* disable Energy Detect and enable scrambler */
514 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
515 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
516
517 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
518 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
519 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
520 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
521
522 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
523 break;
524
cd28ab6a 525 case CHIP_ID_YUKON_XL:
793b883e 526 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 527
528 /* select page 3 to access LED control register */
529 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
530
531 /* set LED Function Control register */
ed6d32c7
SH		 532 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
533 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
534 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
535 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
536 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 537
538 /* set Polarity Control register */
539 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 540 (PHY_M_POLC_LS1_P_MIX(4) |
541 PHY_M_POLC_IS0_P_MIX(4) |
542 PHY_M_POLC_LOS_CTRL(2) |
543 PHY_M_POLC_INIT_CTRL(2) |
544 PHY_M_POLC_STA1_CTRL(2) |
545 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 546
547 /* restore page register */
793b883e 548 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 549 break;
93745494 550
ed6d32c7 551 case CHIP_ID_YUKON_EC_U:
93745494 552 case CHIP_ID_YUKON_EX:
ed4d4161 553 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 554 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
555
556 /* select page 3 to access LED control register */
557 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
558
559 /* set LED Function Control register */
560 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
561 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
562 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
563 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
564 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
565
566 /* set Blink Rate in LED Timer Control Register */
567 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
568 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
569 /* restore page register */
570 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
571 break;
cd28ab6a
SH		 572
573 default:
574 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
575 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 576
cd28ab6a 577 /* turn off the Rx LED (LED_RX) */
a84d0a3d 578 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 579 }
580
9467a8fc
SH		 581 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
582 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 583 /* apply fixes in PHY AFE */
ed6d32c7
SH		 584 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
585
977bdf06 586 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 587 gm_phy_write(hw, port, 0x18, 0xaa99);
588 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 589
977bdf06 590 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 591 gm_phy_write(hw, port, 0x18, 0xa204);
592 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 593
594 /* set page register to 0 */
9467a8fc 595 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 596 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
597 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
598 /* apply workaround for integrated resistors calibration */
599 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
600 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
93745494 601 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
05745c4a 602 /* no effect on Yukon-XL */
977bdf06 603 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 604
977bdf06
SH		 605 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
606 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 607 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 608 }
cd28ab6a 609
977bdf06
SH		 610 if (ledover)
611 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
612
613 }
2eaba1a2 614
d571b694 615 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 616 if (sky2->autoneg == AUTONEG_ENABLE)
617 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
618 else
619 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
620}
621
d3bcfbeb 622static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
623{
624 u32 reg1;
ff35164e
SH		 625 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
626 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
d3bcfbeb 627
82637e80 628 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 629 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
ff35164e 630 /* Turn on/off phy power saving */
d3bcfbeb 631 if (onoff)
d3bcfbeb 632 reg1 &= ~phy_power[port];
633 else
634 reg1 |= phy_power[port];
635
ff35164e
SH		 636 if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
637 reg1 |= coma_mode[port];
638
b32f40c4 639 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80
SH		 640 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
641 sky2_pci_read32(hw, PCI_DEV_REG1);
167f53d0 642
d3bcfbeb 643 udelay(100);
644}
645
1b537565
SH		 646/* Force a renegotiation */
647static void sky2_phy_reinit(struct sky2_port *sky2)
648{
e07b1aa8 649 spin_lock_bh(&sky2->phy_lock);
1b537565 650 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 651 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 652}
653
e3173832
SH		 654/* Put device in state to listen for Wake On Lan */
655static void sky2_wol_init(struct sky2_port *sky2)
656{
657 struct sky2_hw *hw = sky2->hw;
658 unsigned port = sky2->port;
659 enum flow_control save_mode;
660 u16 ctrl;
661 u32 reg1;
662
663 /* Bring hardware out of reset */
664 sky2_write16(hw, B0_CTST, CS_RST_CLR);
665 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
666
667 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
668 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
669
670 /* Force to 10/100
671 * sky2_reset will re-enable on resume
672 */
673 save_mode = sky2->flow_mode;
674 ctrl = sky2->advertising;
675
676 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
677 sky2->flow_mode = FC_NONE;
678 sky2_phy_power(hw, port, 1);
679 sky2_phy_reinit(sky2);
680
681 sky2->flow_mode = save_mode;
682 sky2->advertising = ctrl;
683
684 /* Set GMAC to no flow control and auto update for speed/duplex */
685 gma_write16(hw, port, GM_GP_CTRL,
686 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
687 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
688
689 /* Set WOL address */
690 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
691 sky2->netdev->dev_addr, ETH_ALEN);
692
693 /* Turn on appropriate WOL control bits */
694 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
695 ctrl = 0;
696 if (sky2->wol & WAKE_PHY)
697 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
698 else
699 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
700
701 if (sky2->wol & WAKE_MAGIC)
702 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
703 else
704 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
705
706 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
707 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
708
709 /* Turn on legacy PCI-Express PME mode */
b32f40c4 710 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 711 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 712 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 713
714 /* block receiver */
715 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
716
717}
718
69161611
SH		 719static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
720{
05745c4a
SH		 721 struct net_device *dev = hw->dev[port];
722
ed4d4161
SH		 723 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
724 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
725 hw->chip_id == CHIP_ID_YUKON_FE_P ||
726 hw->chip_id == CHIP_ID_YUKON_SUPR) {
727 /* Yukon-Extreme B0 and further Extreme devices */
728 /* enable Store & Forward mode for TX */
05745c4a 729
ed4d4161
SH		 730 if (dev->mtu <= ETH_DATA_LEN)
731 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
732 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 733
ed4d4161
SH		 734 else
735 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
736 TX_JUMBO_ENA| TX_STFW_ENA);
737 } else {
738 if (dev->mtu <= ETH_DATA_LEN)
739 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
740 else {
741 /* set Tx GMAC FIFO Almost Empty Threshold */
742 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
743 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 744
ed4d4161
SH		 745 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
746
747 /* Can't do offload because of lack of store/forward */
748 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
749 }
69161611
SH		 750 }
751}
752
cd28ab6a
SH		 753static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
754{
755 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
756 u16 reg;
25cccecc 757 u32 rx_reg;
cd28ab6a
SH		 758 int i;
759 const u8 *addr = hw->dev[port]->dev_addr;
760
f350339c
SH		 761 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
762 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 763
764 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
765
793b883e 766 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 767 /* WA DEV_472 -- looks like crossed wires on port 2 */
768 /* clear GMAC 1 Control reset */
769 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
770 do {
771 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
772 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
773 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
774 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
775 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
776 }
777
793b883e 778 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 779
2eaba1a2
SH		 780 /* Enable Transmit FIFO Underrun */
781 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
782
e07b1aa8 783 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 784 sky2_phy_init(hw, port);
e07b1aa8 785 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 786
787 /* MIB clear */
788 reg = gma_read16(hw, port, GM_PHY_ADDR);
789 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
790
43f2f104
SH		 791 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
792 gma_read16(hw, port, i);
cd28ab6a
SH		 793 gma_write16(hw, port, GM_PHY_ADDR, reg);
794
795 /* transmit control */
796 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
797
798 /* receive control reg: unicast + multicast + no FCS */
799 gma_write16(hw, port, GM_RX_CTRL,
793b883e 800 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 801
802 /* transmit flow control */
803 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
804
805 /* transmit parameter */
806 gma_write16(hw, port, GM_TX_PARAM,
807 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
808 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
809 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
810 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
811
812 /* serial mode register */
813 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 814 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 815
6b1a3aef 816 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 817 reg |= GM_SMOD_JUMBO_ENA;
818
819 gma_write16(hw, port, GM_SERIAL_MODE, reg);
820
cd28ab6a
SH		 821 /* virtual address for data */
822 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
823
793b883e
SH		 824 /* physical address: used for pause frames */
825 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
826
827 /* ignore counter overflows */
cd28ab6a
SH		 828 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
829 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
830 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
831
832 /* Configure Rx MAC FIFO */
833 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 834 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 835 if (hw->chip_id == CHIP_ID_YUKON_EX ||
836 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 837 rx_reg |= GMF_RX_OVER_ON;
69161611 838
25cccecc 839 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 840
798fdd07
SH		 841 if (hw->chip_id == CHIP_ID_YUKON_XL) {
842 /* Hardware errata - clear flush mask */
843 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
844 } else {
845 /* Flush Rx MAC FIFO on any flow control or error */
846 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
847 }
cd28ab6a 848
8df9a876 849 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 850 reg = RX_GMF_FL_THR_DEF + 1;
851 /* Another magic mystery workaround from sk98lin */
852 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
853 hw->chip_rev == CHIP_REV_YU_FE2_A0)
854 reg = 0x178;
855 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 856
857 /* Configure Tx MAC FIFO */
858 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
859 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 860
e0c28116 861 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 862 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
8df9a876 863 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 864 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 865
69161611 866 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 867 }
868
e970d1f8
SH		 869 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
870 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
871 /* disable dynamic watermark */
872 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
873 reg &= ~TX_DYN_WM_ENA;
874 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
875 }
cd28ab6a
SH		 876}
877
67712901
SH		 878/* Assign Ram Buffer allocation to queue */
879static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 880{
67712901
SH		 881 u32 end;
882
883 /* convert from K bytes to qwords used for hw register */
884 start *= 1024/8;
885 space *= 1024/8;
886 end = start + space - 1;
793b883e 887
cd28ab6a
SH		 888 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
889 sky2_write32(hw, RB_ADDR(q, RB_START), start);
890 sky2_write32(hw, RB_ADDR(q, RB_END), end);
891 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
892 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
893
894 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 895 u32 tp = space - space/4;
793b883e 896
1c28f6ba
SH		 897 /* On receive queue's set the thresholds
898 * give receiver priority when > 3/4 full
899 * send pause when down to 2K
900 */
901 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
902 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 903
1c28f6ba
SH		 904 tp = space - 2048/8;
905 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
906 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 907 } else {
908 /* Enable store & forward on Tx queue's because
909 * Tx FIFO is only 1K on Yukon
910 */
911 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
912 }
913
914 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 915 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 916}
917
cd28ab6a 918/* Setup Bus Memory Interface */
af4ed7e6 919static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 920{
921 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
922 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
923 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 924 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 925}
926
cd28ab6a
SH		 927/* Setup prefetch unit registers. This is the interface between
928 * hardware and driver list elements
929 */
8cc048e3 930static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 931 u64 addr, u32 last)
932{
cd28ab6a
SH		 933 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
934 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
935 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
936 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
937 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
938 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 939
940 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 941}
942
793b883e
SH		 943static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
944{
945 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
946
cb5d9547 947 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 948 le->ctrl = 0;
793b883e
SH		 949 return le;
950}
cd28ab6a 951
88f5f0ca
SH		 952static void tx_init(struct sky2_port *sky2)
953{
954 struct sky2_tx_le *le;
955
956 sky2->tx_prod = sky2->tx_cons = 0;
957 sky2->tx_tcpsum = 0;
958 sky2->tx_last_mss = 0;
959
960 le = get_tx_le(sky2);
961 le->addr = 0;
962 le->opcode = OP_ADDR64 | HW_OWNER;
88f5f0ca
SH		 963}
964
291ea614
SH		 965static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
966 struct sky2_tx_le *le)
967{
968 return sky2->tx_ring + (le - sky2->tx_le);
969}
970
290d4de5
SH		 971/* Update chip's next pointer */
972static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 973{
50432cb5 974 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 975 wmb();
50432cb5
SH		 976 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
977
978 /* Synchronize I/O on since next processor may write to tail */
979 mmiowb();
cd28ab6a
SH		 980}
981
793b883e 982
cd28ab6a
SH		 983static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
984{
985 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 986 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 987 le->ctrl = 0;
cd28ab6a
SH		 988 return le;
989}
990
14d0263f
SH		 991/* Build description to hardware for one receive segment */
992static void sky2_rx_add(struct sky2_port *sky2, u8 op,
993 dma_addr_t map, unsigned len)
cd28ab6a
SH		 994{
995 struct sky2_rx_le *le;
996
86c6887e 997 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 998 le = sky2_next_rx(sky2);
86c6887e 999 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1000 le->opcode = OP_ADDR64 | HW_OWNER;
1001 }
793b883e 1002
cd28ab6a 1003 le = sky2_next_rx(sky2);
734d1868
SH		 1004 le->addr = cpu_to_le32((u32) map);
1005 le->length = cpu_to_le16(len);
14d0263f 1006 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1007}
1008
14d0263f
SH		 1009/* Build description to hardware for one possibly fragmented skb */
1010static void sky2_rx_submit(struct sky2_port *sky2,
1011 const struct rx_ring_info *re)
1012{
1013 int i;
1014
1015 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1016
1017 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1018 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1019}
1020
1021
1022static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1023 unsigned size)
1024{
1025 struct sk_buff *skb = re->skb;
1026 int i;
1027
1028 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1029 pci_unmap_len_set(re, data_size, size);
1030
1031 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1032 re->frag_addr[i] = pci_map_page(pdev,
1033 skb_shinfo(skb)->frags[i].page,
1034 skb_shinfo(skb)->frags[i].page_offset,
1035 skb_shinfo(skb)->frags[i].size,
1036 PCI_DMA_FROMDEVICE);
1037}
1038
1039static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1040{
1041 struct sk_buff *skb = re->skb;
1042 int i;
1043
1044 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1045 PCI_DMA_FROMDEVICE);
1046
1047 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1048 pci_unmap_page(pdev, re->frag_addr[i],
1049 skb_shinfo(skb)->frags[i].size,
1050 PCI_DMA_FROMDEVICE);
1051}
793b883e 1052
cd28ab6a
SH		 1053/* Tell chip where to start receive checksum.
1054 * Actually has two checksums, but set both same to avoid possible byte
1055 * order problems.
1056 */
793b883e 1057static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1058{
ea76e635 1059 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1060
ea76e635
SH		 1061 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1062 le->ctrl = 0;
1063 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1064
ea76e635
SH		 1065 sky2_write32(sky2->hw,
1066 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1067 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1068}
1069
6b1a3aef 1070/*
1071 * The RX Stop command will not work for Yukon-2 if the BMU does not
1072 * reach the end of packet and since we can't make sure that we have
1073 * incoming data, we must reset the BMU while it is not doing a DMA
1074 * transfer. Since it is possible that the RX path is still active,
1075 * the RX RAM buffer will be stopped first, so any possible incoming
1076 * data will not trigger a DMA. After the RAM buffer is stopped, the
1077 * BMU is polled until any DMA in progress is ended and only then it
1078 * will be reset.
1079 */
1080static void sky2_rx_stop(struct sky2_port *sky2)
1081{
1082 struct sky2_hw *hw = sky2->hw;
1083 unsigned rxq = rxqaddr[sky2->port];
1084 int i;
1085
1086 /* disable the RAM Buffer receive queue */
1087 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1088
1089 for (i = 0; i < 0xffff; i++)
1090 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1091 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1092 goto stopped;
1093
1094 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1095 sky2->netdev->name);
1096stopped:
1097 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1098
1099 /* reset the Rx prefetch unit */
1100 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1101 mmiowb();
6b1a3aef 1102}
793b883e 1103
d571b694 1104/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1105static void sky2_rx_clean(struct sky2_port *sky2)
1106{
1107 unsigned i;
1108
1109 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1110 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1111 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1112
1113 if (re->skb) {
14d0263f 1114 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1115 kfree_skb(re->skb);
1116 re->skb = NULL;
1117 }
1118 }
1119}
1120
ef743d33 1121/* Basic MII support */
1122static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1123{
1124 struct mii_ioctl_data *data = if_mii(ifr);
1125 struct sky2_port *sky2 = netdev_priv(dev);
1126 struct sky2_hw *hw = sky2->hw;
1127 int err = -EOPNOTSUPP;
1128
1129 if (!netif_running(dev))
1130 return -ENODEV; /* Phy still in reset */
1131
d89e1343 1132 switch (cmd) {
ef743d33 1133 case SIOCGMIIPHY:
1134 data->phy_id = PHY_ADDR_MARV;
1135
1136 /* fallthru */
1137 case SIOCGMIIREG: {
1138 u16 val = 0;
91c86df5 1139
e07b1aa8 1140 spin_lock_bh(&sky2->phy_lock);
ef743d33 1141 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1142 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1143
ef743d33 1144 data->val_out = val;
1145 break;
1146 }
1147
1148 case SIOCSMIIREG:
1149 if (!capable(CAP_NET_ADMIN))
1150 return -EPERM;
1151
e07b1aa8 1152 spin_lock_bh(&sky2->phy_lock);
ef743d33 1153 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1154 data->val_in);
e07b1aa8 1155 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1156 break;
1157 }
1158 return err;
1159}
1160
d1f13708 1161#ifdef SKY2_VLAN_TAG_USED
1162static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1163{
1164 struct sky2_port *sky2 = netdev_priv(dev);
1165 struct sky2_hw *hw = sky2->hw;
1166 u16 port = sky2->port;
d1f13708 1167
2bb8c262 1168 netif_tx_lock_bh(dev);
bea3348e 1169 napi_disable(&hw->napi);
d1f13708 1170
d1f13708 1171 sky2->vlgrp = grp;
3d4e66f5
SH		 1172 if (grp) {
1173 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1174 RX_VLAN_STRIP_ON);
1175 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1176 TX_VLAN_TAG_ON);
1177 } else {
1178 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1179 RX_VLAN_STRIP_OFF);
1180 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1181 TX_VLAN_TAG_OFF);
1182 }
d1f13708 1183
d1d08d12 1184 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1185 napi_enable(&hw->napi);
2bb8c262 1186 netif_tx_unlock_bh(dev);
d1f13708 1187}
1188#endif
1189
82788c7a 1190/*
14d0263f
SH		 1191 * Allocate an skb for receiving. If the MTU is large enough
1192 * make the skb non-linear with a fragment list of pages.
82788c7a 1193 */
14d0263f 1194static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1195{
1196 struct sk_buff *skb;
14d0263f 1197 int i;
82788c7a 1198
39dbd958 1199 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1200 unsigned char *start;
1201 /*
1202 * Workaround for a bug in FIFO that cause hang
1203 * if the FIFO if the receive buffer is not 64 byte aligned.
1204 * The buffer returned from netdev_alloc_skb is
1205 * aligned except if slab debugging is enabled.
1206 */
1207 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1208 if (!skb)
1209 goto nomem;
1210 start = PTR_ALIGN(skb->data, 8);
1211 skb_reserve(skb, start - skb->data);
1212 } else {
1213 skb = netdev_alloc_skb(sky2->netdev,
1214 sky2->rx_data_size + NET_IP_ALIGN);
1215 if (!skb)
1216 goto nomem;
1217 skb_reserve(skb, NET_IP_ALIGN);
1218 }
14d0263f
SH		 1219
1220 for (i = 0; i < sky2->rx_nfrags; i++) {
1221 struct page *page = alloc_page(GFP_ATOMIC);
1222
1223 if (!page)
1224 goto free_partial;
1225 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1226 }
1227
1228 return skb;
14d0263f
SH		 1229free_partial:
1230 kfree_skb(skb);
1231nomem:
1232 return NULL;
82788c7a
SH		 1233}
1234
55c9dd35
SH		 1235static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1236{
1237 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1238}
1239
cd28ab6a
SH		 1240/*
1241 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1242 * Normal case this ends up creating one list element for skb
1243 * in the receive ring. Worst case if using large MTU and each
1244 * allocation falls on a different 64 bit region, that results
1245 * in 6 list elements per ring entry.
1246 * One element is used for checksum enable/disable, and one
1247 * extra to avoid wrap.
cd28ab6a 1248 */
6b1a3aef 1249static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1250{
6b1a3aef 1251 struct sky2_hw *hw = sky2->hw;
14d0263f 1252 struct rx_ring_info *re;
6b1a3aef 1253 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1254 unsigned i, size, thresh;
cd28ab6a 1255
6b1a3aef 1256 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1257 sky2_qset(hw, rxq);
977bdf06 1258
c3905bc4
SH		 1259 /* On PCI express lowering the watermark gives better performance */
1260 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1261 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1262
1263 /* These chips have no ram buffer?
1264 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1265 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1266 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1267 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1268 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1269
6b1a3aef 1270 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1271
ea76e635
SH		 1272 if (!(hw->flags & SKY2_HW_NEW_LE))
1273 rx_set_checksum(sky2);
14d0263f
SH		 1274
1275 /* Space needed for frame data + headers rounded up */
f957da2a 1276 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1277
1278 /* Stopping point for hardware truncation */
1279 thresh = (size - 8) / sizeof(u32);
1280
5f06eba4 1281 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1282 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1283
5f06eba4
SH		 1284 /* Compute residue after pages */
1285 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1286
5f06eba4
SH		 1287 /* Optimize to handle small packets and headers */
1288 if (size < copybreak)
1289 size = copybreak;
1290 if (size < ETH_HLEN)
1291 size = ETH_HLEN;
14d0263f 1292
14d0263f
SH		 1293 sky2->rx_data_size = size;
1294
1295 /* Fill Rx ring */
793b883e 1296 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1297 re = sky2->rx_ring + i;
cd28ab6a 1298
14d0263f 1299 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1300 if (!re->skb)
1301 goto nomem;
1302
14d0263f
SH		 1303 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1304 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1305 }
1306
a1433ac4
SH		 1307 /*
1308 * The receiver hangs if it receives frames larger than the
1309 * packet buffer. As a workaround, truncate oversize frames, but
1310 * the register is limited to 9 bits, so if you do frames > 2052
1311 * you better get the MTU right!
1312 */
a1433ac4
SH		 1313 if (thresh > 0x1ff)
1314 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1315 else {
1316 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1317 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1318 }
1319
6b1a3aef 1320 /* Tell chip about available buffers */
55c9dd35 1321 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1322 return 0;
1323nomem:
1324 sky2_rx_clean(sky2);
1325 return -ENOMEM;
1326}
1327
1328/* Bring up network interface. */
1329static int sky2_up(struct net_device *dev)
1330{
1331 struct sky2_port *sky2 = netdev_priv(dev);
1332 struct sky2_hw *hw = sky2->hw;
1333 unsigned port = sky2->port;
e0c28116 1334 u32 imask, ramsize;
ee7abb04 1335 int cap, err = -ENOMEM;
843a46f4 1336 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1337
ee7abb04
SH		 1338 /*
1339 * On dual port PCI-X card, there is an problem where status
1340 * can be received out of order due to split transactions
843a46f4 1341 */
ee7abb04
SH		 1342 if (otherdev && netif_running(otherdev) &&
1343 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1344 u16 cmd;
1345
b32f40c4 1346 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1347 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1348 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1349
ee7abb04 1350 }
843a46f4 1351
cd28ab6a
SH		 1352 if (netif_msg_ifup(sky2))
1353 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1354
55d7b4e6
SH		 1355 netif_carrier_off(dev);
1356
cd28ab6a
SH		 1357 /* must be power of 2 */
1358 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1359 TX_RING_SIZE *
1360 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1361 &sky2->tx_le_map);
1362 if (!sky2->tx_le)
1363 goto err_out;
1364
6cdbbdf3 1365 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1366 GFP_KERNEL);
1367 if (!sky2->tx_ring)
1368 goto err_out;
88f5f0ca
SH		 1369
1370 tx_init(sky2);
cd28ab6a
SH		 1371
1372 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1373 &sky2->rx_le_map);
1374 if (!sky2->rx_le)
1375 goto err_out;
1376 memset(sky2->rx_le, 0, RX_LE_BYTES);
1377
291ea614 1378 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1379 GFP_KERNEL);
1380 if (!sky2->rx_ring)
1381 goto err_out;
1382
d3bcfbeb 1383 sky2_phy_power(hw, port, 1);
1384
cd28ab6a
SH		 1385 sky2_mac_init(hw, port);
1386
e0c28116
SH		 1387 /* Register is number of 4K blocks on internal RAM buffer. */
1388 ramsize = sky2_read8(hw, B2_E_0) * 4;
1389 if (ramsize > 0) {
67712901 1390 u32 rxspace;
cd28ab6a 1391
39dbd958 1392 hw->flags |= SKY2_HW_RAM_BUFFER;
e0c28116 1393 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1394 if (ramsize < 16)
1395 rxspace = ramsize / 2;
1396 else
1397 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1398
67712901
SH		 1399 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1400 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1401
1402 /* Make sure SyncQ is disabled */
1403 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1404 RB_RST_SET);
1405 }
793b883e 1406
af4ed7e6 1407 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1408
69161611
SH		 1409 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1410 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1411 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1412
977bdf06 1413 /* Set almost empty threshold */
c2716fb4
SH		 1414 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1415 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1416 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1417
6b1a3aef 1418 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1419 TX_RING_SIZE - 1);
cd28ab6a 1420
6b1a3aef 1421 err = sky2_rx_start(sky2);
6de16237 1422 if (err)
cd28ab6a
SH		 1423 goto err_out;
1424
cd28ab6a 1425 /* Enable interrupts from phy/mac for port */
e07b1aa8 1426 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1427 imask |= portirq_msk[port];
e07b1aa8
SH		 1428 sky2_write32(hw, B0_IMSK, imask);
1429
a7bffe72 1430 sky2_set_multicast(dev);
cd28ab6a
SH		 1431 return 0;
1432
1433err_out:
1b537565 1434 if (sky2->rx_le) {
cd28ab6a
SH		 1435 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1436 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1437 sky2->rx_le = NULL;
1438 }
1439 if (sky2->tx_le) {
cd28ab6a
SH		 1440 pci_free_consistent(hw->pdev,
1441 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1442 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1443 sky2->tx_le = NULL;
1444 }
1445 kfree(sky2->tx_ring);
1446 kfree(sky2->rx_ring);
cd28ab6a 1447
1b537565
SH		 1448 sky2->tx_ring = NULL;
1449 sky2->rx_ring = NULL;
cd28ab6a
SH		 1450 return err;
1451}
1452
793b883e
SH		 1453/* Modular subtraction in ring */
1454static inline int tx_dist(unsigned tail, unsigned head)
1455{
cb5d9547 1456 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1457}
cd28ab6a 1458
793b883e
SH		 1459/* Number of list elements available for next tx */
1460static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1461{
793b883e 1462 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1463}
1464
793b883e 1465/* Estimate of number of transmit list elements required */
28bd181a 1466static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1467{
793b883e
SH		 1468 unsigned count;
1469
1470 count = sizeof(dma_addr_t) / sizeof(u32);
1471 count += skb_shinfo(skb)->nr_frags * count;
1472
89114afd 1473 if (skb_is_gso(skb))
793b883e
SH		 1474 ++count;
1475
84fa7933 1476 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1477 ++count;
1478
1479 return count;
cd28ab6a
SH		 1480}
1481
793b883e
SH		 1482/*
1483 * Put one packet in ring for transmit.
1484 * A single packet can generate multiple list elements, and
1485 * the number of ring elements will probably be less than the number
1486 * of list elements used.
1487 */
cd28ab6a
SH		 1488static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1489{
1490 struct sky2_port *sky2 = netdev_priv(dev);
1491 struct sky2_hw *hw = sky2->hw;
d1f13708 1492 struct sky2_tx_le *le = NULL;
6cdbbdf3 1493 struct tx_ring_info *re;
cd28ab6a
SH		 1494 unsigned i, len;
1495 dma_addr_t mapping;
cd28ab6a
SH		 1496 u16 mss;
1497 u8 ctrl;
1498
2bb8c262
SH		 1499 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1500 return NETDEV_TX_BUSY;
cd28ab6a 1501
793b883e 1502 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1503 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1504 dev->name, sky2->tx_prod, skb->len);
1505
cd28ab6a
SH		 1506 len = skb_headlen(skb);
1507 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1508
86c6887e
SH		 1509 /* Send high bits if needed */
1510 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1511 le = get_tx_le(sky2);
86c6887e 1512 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e 1513 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1514 }
cd28ab6a
SH		 1515
1516 /* Check for TCP Segmentation Offload */
7967168c 1517 mss = skb_shinfo(skb)->gso_size;
793b883e 1518 if (mss != 0) {
ea76e635
SH		 1519
1520 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1521 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1522
1523 if (mss != sky2->tx_last_mss) {
1524 le = get_tx_le(sky2);
1525 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1526
1527 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1528 le->opcode = OP_MSS | HW_OWNER;
1529 else
1530 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1531 sky2->tx_last_mss = mss;
1532 }
cd28ab6a
SH		 1533 }
1534
cd28ab6a 1535 ctrl = 0;
d1f13708 1536#ifdef SKY2_VLAN_TAG_USED
1537 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1538 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1539 if (!le) {
1540 le = get_tx_le(sky2);
f65b138c 1541 le->addr = 0;
d1f13708 1542 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1543 } else
1544 le->opcode |= OP_VLAN;
1545 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1546 ctrl |= INS_VLAN;
1547 }
1548#endif
1549
1550 /* Handle TCP checksum offload */
84fa7933 1551 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1552 /* On Yukon EX (some versions) encoding change. */
ea76e635 1553 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1554 ctrl |= CALSUM; /* auto checksum */
1555 else {
1556 const unsigned offset = skb_transport_offset(skb);
1557 u32 tcpsum;
1558
1559 tcpsum = offset << 16; /* sum start */
1560 tcpsum |= offset + skb->csum_offset; /* sum write */
1561
1562 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1563 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1564 ctrl |= UDPTCP;
1565
1566 if (tcpsum != sky2->tx_tcpsum) {
1567 sky2->tx_tcpsum = tcpsum;
1568
1569 le = get_tx_le(sky2);
1570 le->addr = cpu_to_le32(tcpsum);
1571 le->length = 0; /* initial checksum value */
1572 le->ctrl = 1; /* one packet */
1573 le->opcode = OP_TCPLISW | HW_OWNER;
1574 }
1d179332 1575 }
cd28ab6a
SH		 1576 }
1577
1578 le = get_tx_le(sky2);
f65b138c 1579 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1580 le->length = cpu_to_le16(len);
1581 le->ctrl = ctrl;
793b883e 1582 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1583
291ea614 1584 re = tx_le_re(sky2, le);
cd28ab6a 1585 re->skb = skb;
6cdbbdf3 1586 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1587 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1588
1589 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1590 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1591
1592 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1593 frag->size, PCI_DMA_TODEVICE);
86c6887e
SH		 1594
1595 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1596 le = get_tx_le(sky2);
86c6887e 1597 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e
SH		 1598 le->ctrl = 0;
1599 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1600 }
1601
1602 le = get_tx_le(sky2);
f65b138c 1603 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1604 le->length = cpu_to_le16(frag->size);
1605 le->ctrl = ctrl;
793b883e 1606 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1607
291ea614
SH		 1608 re = tx_le_re(sky2, le);
1609 re->skb = skb;
1610 pci_unmap_addr_set(re, mapaddr, mapping);
1611 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1612 }
6cdbbdf3 1613
cd28ab6a
SH		 1614 le->ctrl |= EOP;
1615
97bda706 1616 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1617 netif_stop_queue(dev);
b19666d9 1618
290d4de5 1619 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1620
cd28ab6a
SH		 1621 dev->trans_start = jiffies;
1622 return NETDEV_TX_OK;
1623}
1624
cd28ab6a 1625/*
793b883e
SH		 1626 * Free ring elements from starting at tx_cons until "done"
1627 *
1628 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1629 * buffers so make sure not to free skb to early.
cd28ab6a 1630 */
d11c13e7 1631static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1632{
d11c13e7 1633 struct net_device *dev = sky2->netdev;
af2a58ac 1634 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1635 unsigned idx;
cd28ab6a 1636
0e3ff6aa 1637 BUG_ON(done >= TX_RING_SIZE);
2224795d 1638
291ea614
SH		 1639 for (idx = sky2->tx_cons; idx != done;
1640 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1641 struct sky2_tx_le *le = sky2->tx_le + idx;
1642 struct tx_ring_info *re = sky2->tx_ring + idx;
1643
1644 switch(le->opcode & ~HW_OWNER) {
1645 case OP_LARGESEND:
1646 case OP_PACKET:
1647 pci_unmap_single(pdev,
1648 pci_unmap_addr(re, mapaddr),
1649 pci_unmap_len(re, maplen),
1650 PCI_DMA_TODEVICE);
af2a58ac 1651 break;
291ea614
SH		 1652 case OP_BUFFER:
1653 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1654 pci_unmap_len(re, maplen),
734d1868 1655 PCI_DMA_TODEVICE);
291ea614
SH		 1656 break;
1657 }
1658
1659 if (le->ctrl & EOP) {
1660 if (unlikely(netif_msg_tx_done(sky2)))
1661 printk(KERN_DEBUG "%s: tx done %u\n",
1662 dev->name, idx);
3cf26753 1663
7138a0f5
SH		 1664 dev->stats.tx_packets++;
1665 dev->stats.tx_bytes += re->skb->len;
2bf56fe2 1666
794b2bd2 1667 dev_kfree_skb_any(re->skb);
3cf26753 1668 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1669 }
793b883e 1670 }
793b883e 1671
291ea614 1672 sky2->tx_cons = idx;
50432cb5
SH		 1673 smp_mb();
1674
22e11703 1675 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1676 netif_wake_queue(dev);
cd28ab6a
SH		 1677}
1678
1679/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1680static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1681{
2bb8c262
SH		 1682 struct sky2_port *sky2 = netdev_priv(dev);
1683
1684 netif_tx_lock_bh(dev);
d11c13e7 1685 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1686 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1687}
1688
1689/* Network shutdown */
1690static int sky2_down(struct net_device *dev)
1691{
1692 struct sky2_port *sky2 = netdev_priv(dev);
1693 struct sky2_hw *hw = sky2->hw;
1694 unsigned port = sky2->port;
1695 u16 ctrl;
e07b1aa8 1696 u32 imask;
cd28ab6a 1697
1b537565
SH		 1698 /* Never really got started! */
1699 if (!sky2->tx_le)
1700 return 0;
1701
cd28ab6a
SH		 1702 if (netif_msg_ifdown(sky2))
1703 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1704
018d1c66 1705 /* Stop more packets from being queued */
cd28ab6a
SH		 1706 netif_stop_queue(dev);
1707
ebc646f6
SH		 1708 /* Disable port IRQ */
1709 imask = sky2_read32(hw, B0_IMSK);
1710 imask &= ~portirq_msk[port];
1711 sky2_write32(hw, B0_IMSK, imask);
1712
6de16237
SH		 1713 synchronize_irq(hw->pdev->irq);
1714
d3bcfbeb 1715 sky2_gmac_reset(hw, port);
793b883e 1716
cd28ab6a
SH		 1717 /* Stop transmitter */
1718 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1719 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1720
1721 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1722 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1723
1724 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1725 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1726 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1727
6de16237
SH		 1728 /* Make sure no packets are pending */
1729 napi_synchronize(&hw->napi);
1730
cd28ab6a
SH		 1731 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1732
1733 /* Workaround shared GMAC reset */
793b883e
SH		 1734 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1735 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1736 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1737
1738 /* Disable Force Sync bit and Enable Alloc bit */
1739 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1740 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1741
1742 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1743 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1744 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1745
1746 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1747 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1748 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1749
1750 /* Reset the Tx prefetch units */
1751 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1752 PREF_UNIT_RST_SET);
1753
1754 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1755
6b1a3aef 1756 sky2_rx_stop(sky2);
cd28ab6a
SH		 1757
1758 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1759 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1760
d3bcfbeb 1761 sky2_phy_power(hw, port, 0);
1762
55d7b4e6
SH		 1763 netif_carrier_off(dev);
1764
d571b694 1765 /* turn off LED's */
cd28ab6a
SH		 1766 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1767
2bb8c262 1768 sky2_tx_clean(dev);
cd28ab6a
SH		 1769 sky2_rx_clean(sky2);
1770
1771 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1772 sky2->rx_le, sky2->rx_le_map);
1773 kfree(sky2->rx_ring);
1774
1775 pci_free_consistent(hw->pdev,
1776 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1777 sky2->tx_le, sky2->tx_le_map);
1778 kfree(sky2->tx_ring);
1779
1b537565
SH		 1780 sky2->tx_le = NULL;
1781 sky2->rx_le = NULL;
1782
1783 sky2->rx_ring = NULL;
1784 sky2->tx_ring = NULL;
1785
cd28ab6a
SH		 1786 return 0;
1787}
1788
1789static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1790{
ea76e635 1791 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1792 return SPEED_1000;
1793
05745c4a
SH		 1794 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1795 if (aux & PHY_M_PS_SPEED_100)
1796 return SPEED_100;
1797 else
1798 return SPEED_10;
1799 }
cd28ab6a
SH		 1800
1801 switch (aux & PHY_M_PS_SPEED_MSK) {
1802 case PHY_M_PS_SPEED_1000:
1803 return SPEED_1000;
1804 case PHY_M_PS_SPEED_100:
1805 return SPEED_100;
1806 default:
1807 return SPEED_10;
1808 }
1809}
1810
1811static void sky2_link_up(struct sky2_port *sky2)
1812{
1813 struct sky2_hw *hw = sky2->hw;
1814 unsigned port = sky2->port;
1815 u16 reg;
16ad91e1
SH		 1816 static const char *fc_name[] = {
1817 [FC_NONE] = "none",
1818 [FC_TX] = "tx",
1819 [FC_RX] = "rx",
1820 [FC_BOTH] = "both",
1821 };
cd28ab6a 1822
cd28ab6a 1823 /* enable Rx/Tx */
2eaba1a2 1824 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1825 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1826 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1827
1828 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1829
1830 netif_carrier_on(sky2->netdev);
cd28ab6a 1831
75e80683 1832 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1833
cd28ab6a 1834 /* Turn on link LED */
793b883e 1835 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1836 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1837
1838 if (netif_msg_link(sky2))
1839 printk(KERN_INFO PFX
d571b694 1840 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1841 sky2->netdev->name, sky2->speed,
1842 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1843 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1844}
1845
1846static void sky2_link_down(struct sky2_port *sky2)
1847{
1848 struct sky2_hw *hw = sky2->hw;
1849 unsigned port = sky2->port;
1850 u16 reg;
1851
1852 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1853
1854 reg = gma_read16(hw, port, GM_GP_CTRL);
1855 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1856 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1857
cd28ab6a 1858 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1859
1860 /* Turn on link LED */
1861 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1862
1863 if (netif_msg_link(sky2))
1864 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1865
cd28ab6a
SH		 1866 sky2_phy_init(hw, port);
1867}
1868
16ad91e1
SH		 1869static enum flow_control sky2_flow(int rx, int tx)
1870{
1871 if (rx)
1872 return tx ? FC_BOTH : FC_RX;
1873 else
1874 return tx ? FC_TX : FC_NONE;
1875}
1876
793b883e
SH		 1877static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1878{
1879 struct sky2_hw *hw = sky2->hw;
1880 unsigned port = sky2->port;
da4c1ff4 1881 u16 advert, lpa;
793b883e 1882
da4c1ff4 1883 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1884 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1885 if (lpa & PHY_M_AN_RF) {
1886 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1887 return -1;
1888 }
1889
793b883e
SH		 1890 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1891 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1892 sky2->netdev->name);
1893 return -1;
1894 }
1895
793b883e 1896 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1897 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1898
da4c1ff4
SH		 1899 /* Since the pause result bits seem to in different positions on
1900 * different chips. look at registers.
1901 */
ea76e635 1902 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 1903 /* Shift for bits in fiber PHY */
1904 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1905 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1906
1907 if (advert & ADVERTISE_1000XPAUSE)
1908 advert |= ADVERTISE_PAUSE_CAP;
1909 if (advert & ADVERTISE_1000XPSE_ASYM)
1910 advert |= ADVERTISE_PAUSE_ASYM;
1911 if (lpa & LPA_1000XPAUSE)
1912 lpa |= LPA_PAUSE_CAP;
1913 if (lpa & LPA_1000XPAUSE_ASYM)
1914 lpa |= LPA_PAUSE_ASYM;
1915 }
793b883e 1916
da4c1ff4
SH		 1917 sky2->flow_status = FC_NONE;
1918 if (advert & ADVERTISE_PAUSE_CAP) {
1919 if (lpa & LPA_PAUSE_CAP)
1920 sky2->flow_status = FC_BOTH;
1921 else if (advert & ADVERTISE_PAUSE_ASYM)
1922 sky2->flow_status = FC_RX;
1923 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1924 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1925 sky2->flow_status = FC_TX;
1926 }
793b883e 1927
16ad91e1 1928 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1929 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1930 sky2->flow_status = FC_NONE;
2eaba1a2 1931
da4c1ff4 1932 if (sky2->flow_status & FC_TX)
793b883e
SH		 1933 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1934 else
1935 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1936
1937 return 0;
1938}
cd28ab6a 1939
e07b1aa8
SH		 1940/* Interrupt from PHY */
1941static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1942{
e07b1aa8
SH		 1943 struct net_device *dev = hw->dev[port];
1944 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1945 u16 istatus, phystat;
1946
ebc646f6
SH		 1947 if (!netif_running(dev))
1948 return;
1949
e07b1aa8
SH		 1950 spin_lock(&sky2->phy_lock);
1951 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1952 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1953
cd28ab6a
SH		 1954 if (netif_msg_intr(sky2))
1955 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1956 sky2->netdev->name, istatus, phystat);
1957
2eaba1a2 1958 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1959 if (sky2_autoneg_done(sky2, phystat) == 0)
1960 sky2_link_up(sky2);
1961 goto out;
1962 }
cd28ab6a 1963
793b883e
SH		 1964 if (istatus & PHY_M_IS_LSP_CHANGE)
1965 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1966
793b883e
SH		 1967 if (istatus & PHY_M_IS_DUP_CHANGE)
1968 sky2->duplex =
1969 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1970
793b883e
SH		 1971 if (istatus & PHY_M_IS_LST_CHANGE) {
1972 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1973 sky2_link_up(sky2);
793b883e
SH		 1974 else
1975 sky2_link_down(sky2);
cd28ab6a 1976 }
793b883e 1977out:
e07b1aa8 1978 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1979}
1980
62335ab0 1981/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1982 * and tx queue is full (stopped).
1983 */
cd28ab6a
SH		 1984static void sky2_tx_timeout(struct net_device *dev)
1985{
1986 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1987 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1988
1989 if (netif_msg_timer(sky2))
1990 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1991
8f24664d 1992 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1993 dev->name, sky2->tx_cons, sky2->tx_prod,
1994 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1995 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1996
81906791
SH		 1997 /* can't restart safely under softirq */
1998 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1999}
2000
2001static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2002{
6b1a3aef 2003 struct sky2_port *sky2 = netdev_priv(dev);
2004 struct sky2_hw *hw = sky2->hw;
b628ed98 2005 unsigned port = sky2->port;
6b1a3aef 2006 int err;
2007 u16 ctl, mode;
e07b1aa8 2008 u32 imask;
cd28ab6a
SH		 2009
2010 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2011 return -EINVAL;
2012
05745c4a
SH		 2013 if (new_mtu > ETH_DATA_LEN &&
2014 (hw->chip_id == CHIP_ID_YUKON_FE ||
2015 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2016 return -EINVAL;
2017
6b1a3aef 2018 if (!netif_running(dev)) {
2019 dev->mtu = new_mtu;
2020 return 0;
2021 }
2022
e07b1aa8 2023 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 2024 sky2_write32(hw, B0_IMSK, 0);
2025
018d1c66 2026 dev->trans_start = jiffies; /* prevent tx timeout */
2027 netif_stop_queue(dev);
bea3348e 2028 napi_disable(&hw->napi);
018d1c66 2029
e07b1aa8
SH		 2030 synchronize_irq(hw->pdev->irq);
2031
39dbd958 2032 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2033 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2034
2035 ctl = gma_read16(hw, port, GM_GP_CTRL);
2036 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 2037 sky2_rx_stop(sky2);
2038 sky2_rx_clean(sky2);
cd28ab6a
SH		 2039
2040 dev->mtu = new_mtu;
14d0263f 2041
6b1a3aef 2042 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2043 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2044
2045 if (dev->mtu > ETH_DATA_LEN)
2046 mode |= GM_SMOD_JUMBO_ENA;
2047
b628ed98 2048 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2049
b628ed98 2050 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2051
6b1a3aef 2052 err = sky2_rx_start(sky2);
e07b1aa8 2053 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2054
d1d08d12 2055 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2056 napi_enable(&hw->napi);
2057
1b537565
SH		 2058 if (err)
2059 dev_close(dev);
2060 else {
b628ed98 2061 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2062
1b537565
SH		 2063 netif_wake_queue(dev);
2064 }
2065
cd28ab6a
SH		 2066 return err;
2067}
2068
14d0263f
SH		 2069/* For small just reuse existing skb for next receive */
2070static struct sk_buff *receive_copy(struct sky2_port *sky2,
2071 const struct rx_ring_info *re,
2072 unsigned length)
2073{
2074 struct sk_buff *skb;
2075
2076 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2077 if (likely(skb)) {
2078 skb_reserve(skb, 2);
2079 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2080 length, PCI_DMA_FROMDEVICE);
d626f62b 2081 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2082 skb->ip_summed = re->skb->ip_summed;
2083 skb->csum = re->skb->csum;
2084 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2085 length, PCI_DMA_FROMDEVICE);
2086 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2087 skb_put(skb, length);
14d0263f
SH		 2088 }
2089 return skb;
2090}
2091
2092/* Adjust length of skb with fragments to match received data */
2093static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2094 unsigned int length)
2095{
2096 int i, num_frags;
2097 unsigned int size;
2098
2099 /* put header into skb */
2100 size = min(length, hdr_space);
2101 skb->tail += size;
2102 skb->len += size;
2103 length -= size;
2104
2105 num_frags = skb_shinfo(skb)->nr_frags;
2106 for (i = 0; i < num_frags; i++) {
2107 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2108
2109 if (length == 0) {
2110 /* don't need this page */
2111 __free_page(frag->page);
2112 --skb_shinfo(skb)->nr_frags;
2113 } else {
2114 size = min(length, (unsigned) PAGE_SIZE);
2115
2116 frag->size = size;
2117 skb->data_len += size;
2118 skb->truesize += size;
2119 skb->len += size;
2120 length -= size;
2121 }
2122 }
2123}
2124
2125/* Normal packet - take skb from ring element and put in a new one */
2126static struct sk_buff *receive_new(struct sky2_port *sky2,
2127 struct rx_ring_info *re,
2128 unsigned int length)
2129{
2130 struct sk_buff *skb, *nskb;
2131 unsigned hdr_space = sky2->rx_data_size;
2132
14d0263f
SH		 2133 /* Don't be tricky about reusing pages (yet) */
2134 nskb = sky2_rx_alloc(sky2);
2135 if (unlikely(!nskb))
2136 return NULL;
2137
2138 skb = re->skb;
2139 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2140
2141 prefetch(skb->data);
2142 re->skb = nskb;
2143 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2144
2145 if (skb_shinfo(skb)->nr_frags)
2146 skb_put_frags(skb, hdr_space, length);
2147 else
489b10c1 2148 skb_put(skb, length);
14d0263f
SH		 2149 return skb;
2150}
2151
cd28ab6a
SH		 2152/*
2153 * Receive one packet.
d571b694 2154 * For larger packets, get new buffer.
cd28ab6a 2155 */
497d7c86 2156static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2157 u16 length, u32 status)
2158{
497d7c86 2159 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2160 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2161 struct sk_buff *skb = NULL;
d6532232
SH		 2162 u16 count = (status & GMR_FS_LEN) >> 16;
2163
2164#ifdef SKY2_VLAN_TAG_USED
2165 /* Account for vlan tag */
2166 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2167 count -= VLAN_HLEN;
2168#endif
cd28ab6a
SH		 2169
2170 if (unlikely(netif_msg_rx_status(sky2)))
2171 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2172 dev->name, sky2->rx_next, status, length);
cd28ab6a 2173
793b883e 2174 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2175 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2176
3b12e014
SH		 2177 /* This chip has hardware problems that generates bogus status.
2178 * So do only marginal checking and expect higher level protocols
2179 * to handle crap frames.
2180 */
2181 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2182 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2183 length != count)
2184 goto okay;
2185
42eeea01 2186 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2187 goto error;
2188
42eeea01 2189 if (!(status & GMR_FS_RX_OK))
2190 goto resubmit;
2191
d6532232
SH		 2192 /* if length reported by DMA does not match PHY, packet was truncated */
2193 if (length != count)
3b12e014 2194 goto len_error;
71749531 2195
3b12e014 2196okay:
14d0263f
SH		 2197 if (length < copybreak)
2198 skb = receive_copy(sky2, re, length);
2199 else
2200 skb = receive_new(sky2, re, length);
793b883e 2201resubmit:
14d0263f 2202 sky2_rx_submit(sky2, re);
79e57d32 2203
cd28ab6a
SH		 2204 return skb;
2205
3b12e014 2206len_error:
71749531
SH		 2207 /* Truncation of overlength packets
2208 causes PHY length to not match MAC length */
7138a0f5 2209 ++dev->stats.rx_length_errors;
d6532232 2210 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2211 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2212 dev->name, status, length);
d6532232 2213 goto resubmit;
71749531 2214
cd28ab6a 2215error:
7138a0f5 2216 ++dev->stats.rx_errors;
b6d77734 2217 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2218 dev->stats.rx_over_errors++;
b6d77734
SH		 2219 goto resubmit;
2220 }
6e15b712 2221
3be92a70 2222 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2223 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2224 dev->name, status, length);
793b883e
SH		 2225
2226 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2227 dev->stats.rx_length_errors++;
cd28ab6a 2228 if (status & GMR_FS_FRAGMENT)
7138a0f5 2229 dev->stats.rx_frame_errors++;
cd28ab6a 2230 if (status & GMR_FS_CRC_ERR)
7138a0f5 2231 dev->stats.rx_crc_errors++;
79e57d32 2232
793b883e 2233 goto resubmit;
cd28ab6a
SH		 2234}
2235
e07b1aa8
SH		 2236/* Transmit complete */
2237static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2238{
e07b1aa8 2239 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2240
e07b1aa8 2241 if (netif_running(dev)) {
2bb8c262 2242 netif_tx_lock(dev);
e07b1aa8 2243 sky2_tx_complete(sky2, last);
2bb8c262 2244 netif_tx_unlock(dev);
2224795d 2245 }
cd28ab6a
SH		 2246}
2247
e07b1aa8 2248/* Process status response ring */
26691830 2249static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2250{
e07b1aa8 2251 int work_done = 0;
55c9dd35 2252 unsigned rx[2] = { 0, 0 };
a8fd6266 2253
af2a58ac 2254 rmb();
26691830 2255 do {
55c9dd35 2256 struct sky2_port *sky2;
13210ce5 2257 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2258 unsigned port;
13210ce5 2259 struct net_device *dev;
cd28ab6a 2260 struct sk_buff *skb;
cd28ab6a
SH		 2261 u32 status;
2262 u16 length;
ab5adecb
SH		 2263 u8 opcode = le->opcode;
2264
2265 if (!(opcode & HW_OWNER))
2266 break;
cd28ab6a 2267
cb5d9547 2268 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2269
ab5adecb 2270 port = le->css & CSS_LINK_BIT;
69161611 2271 dev = hw->dev[port];
13210ce5 2272 sky2 = netdev_priv(dev);
f65b138c
SH		 2273 length = le16_to_cpu(le->length);
2274 status = le32_to_cpu(le->status);
cd28ab6a 2275
ab5adecb
SH		 2276 le->opcode = 0;
2277 switch (opcode & ~HW_OWNER) {
cd28ab6a 2278 case OP_RXSTAT:
55c9dd35 2279 ++rx[port];
497d7c86 2280 skb = sky2_receive(dev, length, status);
3225b919 2281 if (unlikely(!skb)) {
7138a0f5 2282 dev->stats.rx_dropped++;
55c9dd35 2283 break;
3225b919 2284 }
13210ce5 2285
69161611 2286 /* This chip reports checksum status differently */
05745c4a 2287 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2288 if (sky2->rx_csum &&
2289 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2290 (le->css & CSS_TCPUDPCSOK))
2291 skb->ip_summed = CHECKSUM_UNNECESSARY;
2292 else
2293 skb->ip_summed = CHECKSUM_NONE;
2294 }
2295
13210ce5 2296 skb->protocol = eth_type_trans(skb, dev);
7138a0f5
SH		 2297 dev->stats.rx_packets++;
2298 dev->stats.rx_bytes += skb->len;
13210ce5 2299 dev->last_rx = jiffies;
2300
d1f13708 2301#ifdef SKY2_VLAN_TAG_USED
2302 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2303 vlan_hwaccel_receive_skb(skb,
2304 sky2->vlgrp,
2305 be16_to_cpu(sky2->rx_tag));
2306 } else
2307#endif
cd28ab6a 2308 netif_receive_skb(skb);
13210ce5 2309
22e11703 2310 /* Stop after net poll weight */
13210ce5 2311 if (++work_done >= to_do)
2312 goto exit_loop;
cd28ab6a
SH		 2313 break;
2314
d1f13708 2315#ifdef SKY2_VLAN_TAG_USED
2316 case OP_RXVLAN:
2317 sky2->rx_tag = length;
2318 break;
2319
2320 case OP_RXCHKSVLAN:
2321 sky2->rx_tag = length;
2322 /* fall through */
2323#endif
cd28ab6a 2324 case OP_RXCHKS:
87418307
SH		 2325 if (!sky2->rx_csum)
2326 break;
2327
05745c4a
SH		 2328 /* If this happens then driver assuming wrong format */
2329 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2330 if (net_ratelimit())
2331 printk(KERN_NOTICE "%s: unexpected"
2332 " checksum status\n",
2333 dev->name);
69161611 2334 break;
05745c4a 2335 }
69161611 2336
87418307
SH		 2337 /* Both checksum counters are programmed to start at
2338 * the same offset, so unless there is a problem they
2339 * should match. This failure is an early indication that
2340 * hardware receive checksumming won't work.
2341 */
2342 if (likely(status >> 16 == (status & 0xffff))) {
2343 skb = sky2->rx_ring[sky2->rx_next].skb;
2344 skb->ip_summed = CHECKSUM_COMPLETE;
2345 skb->csum = status & 0xffff;
2346 } else {
2347 printk(KERN_NOTICE PFX "%s: hardware receive "
2348 "checksum problem (status = %#x)\n",
2349 dev->name, status);
2350 sky2->rx_csum = 0;
2351 sky2_write32(sky2->hw,
69161611 2352 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2353 BMU_DIS_RX_CHKSUM);
2354 }
cd28ab6a
SH		 2355 break;
2356
2357 case OP_TXINDEXLE:
13b97b74 2358 /* TX index reports status for both ports */
f55925d7
SH		 2359 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2360 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2361 if (hw->dev[1])
2362 sky2_tx_done(hw->dev[1],
2363 ((status >> 24) & 0xff)
2364 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2365 break;
2366
cd28ab6a
SH		 2367 default:
2368 if (net_ratelimit())
793b883e 2369 printk(KERN_WARNING PFX
ab5adecb 2370 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2371 }
26691830 2372 } while (hw->st_idx != idx);
cd28ab6a 2373
fe2a24df
SH		 2374 /* Fully processed status ring so clear irq */
2375 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2376
13210ce5 2377exit_loop:
55c9dd35
SH		 2378 if (rx[0])
2379 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2380
55c9dd35
SH		 2381 if (rx[1])
2382 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2383
e07b1aa8 2384 return work_done;
cd28ab6a
SH		 2385}
2386
2387static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2388{
2389 struct net_device *dev = hw->dev[port];
2390
3be92a70
SH		 2391 if (net_ratelimit())
2392 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2393 dev->name, status);
cd28ab6a
SH		 2394
2395 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2396 if (net_ratelimit())
2397 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2398 dev->name);
cd28ab6a
SH		 2399 /* Clear IRQ */
2400 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2401 }
2402
2403 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2404 if (net_ratelimit())
2405 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2406 dev->name);
cd28ab6a
SH		 2407
2408 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2409 }
2410
2411 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2412 if (net_ratelimit())
2413 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2414 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2415 }
2416
2417 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2418 if (net_ratelimit())
2419 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2420 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2421 }
2422
2423 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2424 if (net_ratelimit())
2425 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2426 dev->name);
cd28ab6a
SH		 2427 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2428 }
2429}
2430
2431static void sky2_hw_intr(struct sky2_hw *hw)
2432{
555382cb 2433 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2434 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2435 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2436
2437 status &= hwmsk;
cd28ab6a 2438
793b883e 2439 if (status & Y2_IS_TIST_OV)
cd28ab6a 2440 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2441
2442 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2443 u16 pci_err;
2444
82637e80 2445 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2446 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2447 if (net_ratelimit())
555382cb 2448 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2449 pci_err);
cd28ab6a 2450
b32f40c4 2451 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2452 pci_err | PCI_STATUS_ERROR_BITS);
82637e80 2453 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2454 }
2455
2456 if (status & Y2_IS_PCI_EXP) {
d571b694 2457 /* PCI-Express uncorrectable Error occurred */
555382cb 2458 u32 err;
cd28ab6a 2459
82637e80 2460 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2461 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2462 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2463 0xfffffffful);
3be92a70 2464 if (net_ratelimit())
555382cb 2465 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2466
7782c8c4 2467 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
82637e80 2468 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2469 }
2470
2471 if (status & Y2_HWE_L1_MASK)
2472 sky2_hw_error(hw, 0, status);
2473 status >>= 8;
2474 if (status & Y2_HWE_L1_MASK)
2475 sky2_hw_error(hw, 1, status);
2476}
2477
2478static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2479{
2480 struct net_device *dev = hw->dev[port];
2481 struct sky2_port *sky2 = netdev_priv(dev);
2482 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2483
2484 if (netif_msg_intr(sky2))
2485 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2486 dev->name, status);
2487
a3caeada
SH		 2488 if (status & GM_IS_RX_CO_OV)
2489 gma_read16(hw, port, GM_RX_IRQ_SRC);
2490
2491 if (status & GM_IS_TX_CO_OV)
2492 gma_read16(hw, port, GM_TX_IRQ_SRC);
2493
cd28ab6a 2494 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2495 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2496 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2497 }
2498
2499 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2500 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2501 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2502 }
cd28ab6a
SH		 2503}
2504
40b01727
SH		 2505/* This should never happen it is a bug. */
2506static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2507 u16 q, unsigned ring_size)
d257924e
SH		 2508{
2509 struct net_device *dev = hw->dev[port];
2510 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2511 unsigned idx;
2512 const u64 *le = (q == Q_R1 || q == Q_R2)
2513 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2514
40b01727
SH		 2515 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2516 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2517 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2518 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2519
40b01727 2520 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2521}
cd28ab6a 2522
75e80683
SH		 2523static int sky2_rx_hung(struct net_device *dev)
2524{
2525 struct sky2_port *sky2 = netdev_priv(dev);
2526 struct sky2_hw *hw = sky2->hw;
2527 unsigned port = sky2->port;
2528 unsigned rxq = rxqaddr[port];
2529 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2530 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2531 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2532 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2533
2534 /* If idle and MAC or PCI is stuck */
2535 if (sky2->check.last == dev->last_rx &&
2536 ((mac_rp == sky2->check.mac_rp &&
2537 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2538 /* Check if the PCI RX hang */
2539 (fifo_rp == sky2->check.fifo_rp &&
2540 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2541 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2542 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2543 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2544 return 1;
2545 } else {
2546 sky2->check.last = dev->last_rx;
2547 sky2->check.mac_rp = mac_rp;
2548 sky2->check.mac_lev = mac_lev;
2549 sky2->check.fifo_rp = fifo_rp;
2550 sky2->check.fifo_lev = fifo_lev;
2551 return 0;
2552 }
2553}
2554
32c2c300 2555static void sky2_watchdog(unsigned long arg)
d27ed387 2556{
01bd7564 2557 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2558
75e80683 2559 /* Check for lost IRQ once a second */
32c2c300 2560 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2561 napi_schedule(&hw->napi);
75e80683
SH		 2562 } else {
2563 int i, active = 0;
2564
2565 for (i = 0; i < hw->ports; i++) {
bea3348e 2566 struct net_device *dev = hw->dev[i];
75e80683
SH		 2567 if (!netif_running(dev))
2568 continue;
2569 ++active;
2570
2571 /* For chips with Rx FIFO, check if stuck */
39dbd958 2572 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2573 sky2_rx_hung(dev)) {
2574 pr_info(PFX "%s: receiver hang detected\n",
2575 dev->name);
2576 schedule_work(&hw->restart_work);
2577 return;
2578 }
2579 }
2580
2581 if (active == 0)
2582 return;
32c2c300 2583 }
01bd7564 2584
75e80683 2585 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2586}
2587
40b01727
SH		 2588/* Hardware/software error handling */
2589static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2590{
40b01727
SH		 2591 if (net_ratelimit())
2592 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2593
1e5f1283
SH		 2594 if (status & Y2_IS_HW_ERR)
2595 sky2_hw_intr(hw);
d257924e 2596
1e5f1283
SH		 2597 if (status & Y2_IS_IRQ_MAC1)
2598 sky2_mac_intr(hw, 0);
cd28ab6a 2599
1e5f1283
SH		 2600 if (status & Y2_IS_IRQ_MAC2)
2601 sky2_mac_intr(hw, 1);
cd28ab6a 2602
1e5f1283 2603 if (status & Y2_IS_CHK_RX1)
40b01727 2604 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2605
1e5f1283 2606 if (status & Y2_IS_CHK_RX2)
40b01727 2607 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2608
1e5f1283 2609 if (status & Y2_IS_CHK_TXA1)
40b01727 2610 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2611
1e5f1283 2612 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2613 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2614}
2615
bea3348e 2616static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2617{
bea3348e 2618 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2619 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2620 int work_done = 0;
26691830 2621 u16 idx;
40b01727
SH		 2622
2623 if (unlikely(status & Y2_IS_ERROR))
2624 sky2_err_intr(hw, status);
2625
2626 if (status & Y2_IS_IRQ_PHY1)
2627 sky2_phy_intr(hw, 0);
2628
2629 if (status & Y2_IS_IRQ_PHY2)
2630 sky2_phy_intr(hw, 1);
cd28ab6a 2631
26691830
SH		 2632 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2633 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2634
2635 if (work_done >= work_limit)
26691830
SH		 2636 goto done;
2637 }
6f535763 2638
26691830
SH		 2639 /* Bug/Errata workaround?
2640 * Need to kick the TX irq moderation timer.
2641 */
2642 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2643 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2644 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2645 }
26691830
SH		 2646 napi_complete(napi);
2647 sky2_read32(hw, B0_Y2_SP_LISR);
2648done:
6f535763 2649
bea3348e 2650 return work_done;
e07b1aa8
SH		 2651}
2652
7d12e780 2653static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2654{
2655 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2656 u32 status;
2657
2658 /* Reading this mask interrupts as side effect */
2659 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2660 if (status == 0 || status == ~0)
2661 return IRQ_NONE;
793b883e 2662
e07b1aa8 2663 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2664
2665 napi_schedule(&hw->napi);
793b883e 2666
cd28ab6a
SH		 2667 return IRQ_HANDLED;
2668}
2669
2670#ifdef CONFIG_NET_POLL_CONTROLLER
2671static void sky2_netpoll(struct net_device *dev)
2672{
2673 struct sky2_port *sky2 = netdev_priv(dev);
2674
bea3348e 2675 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2676}
2677#endif
2678
2679/* Chip internal frequency for clock calculations */
05745c4a 2680static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2681{
793b883e 2682 switch (hw->chip_id) {
cd28ab6a 2683 case CHIP_ID_YUKON_EC:
5a5b1ea0 2684 case CHIP_ID_YUKON_EC_U:
93745494 2685 case CHIP_ID_YUKON_EX:
ed4d4161 2686 case CHIP_ID_YUKON_SUPR:
05745c4a
SH		 2687 return 125;
2688
cd28ab6a 2689 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2690 return 100;
2691
2692 case CHIP_ID_YUKON_FE_P:
2693 return 50;
2694
2695 case CHIP_ID_YUKON_XL:
2696 return 156;
2697
2698 default:
2699 BUG();
cd28ab6a
SH		 2700 }
2701}
2702
fb17358f 2703static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2704{
fb17358f 2705 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2706}
2707
fb17358f 2708static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2709{
fb17358f 2710 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2711}
2712
fb17358f 2713
e3173832 2714static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2715{
b89165f2 2716 u8 t8;
cd28ab6a 2717
167f53d0 2718 /* Enable all clocks and check for bad PCI access */
b32f40c4 2719 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2720
cd28ab6a 2721 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2722
cd28ab6a 2723 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2724 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2725
2726 switch(hw->chip_id) {
2727 case CHIP_ID_YUKON_XL:
39dbd958 2728 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2729 break;
2730
2731 case CHIP_ID_YUKON_EC_U:
2732 hw->flags = SKY2_HW_GIGABIT
2733 | SKY2_HW_NEWER_PHY
2734 | SKY2_HW_ADV_POWER_CTL;
2735 break;
2736
2737 case CHIP_ID_YUKON_EX:
2738 hw->flags = SKY2_HW_GIGABIT
2739 | SKY2_HW_NEWER_PHY
2740 | SKY2_HW_NEW_LE
2741 | SKY2_HW_ADV_POWER_CTL;
2742
2743 /* New transmit checksum */
2744 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2745 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2746 break;
2747
2748 case CHIP_ID_YUKON_EC:
2749 /* This rev is really old, and requires untested workarounds */
2750 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2751 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2752 return -EOPNOTSUPP;
2753 }
39dbd958 2754 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2755 break;
2756
2757 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2758 break;
2759
05745c4a
SH		 2760 case CHIP_ID_YUKON_FE_P:
2761 hw->flags = SKY2_HW_NEWER_PHY
2762 | SKY2_HW_NEW_LE
2763 | SKY2_HW_AUTO_TX_SUM
2764 | SKY2_HW_ADV_POWER_CTL;
2765 break;
ed4d4161
SH		 2766
2767 case CHIP_ID_YUKON_SUPR:
2768 hw->flags = SKY2_HW_GIGABIT
2769 | SKY2_HW_NEWER_PHY
2770 | SKY2_HW_NEW_LE
2771 | SKY2_HW_AUTO_TX_SUM
2772 | SKY2_HW_ADV_POWER_CTL;
2773 break;
2774
ea76e635 2775 default:
b02a9258
SH		 2776 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2777 hw->chip_id);
cd28ab6a
SH		 2778 return -EOPNOTSUPP;
2779 }
2780
ea76e635
SH		 2781 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2782 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2783 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2784
290d4de5 2785
e3173832
SH		 2786 hw->ports = 1;
2787 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2788 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2789 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2790 ++hw->ports;
2791 }
2792
2793 return 0;
2794}
2795
2796static void sky2_reset(struct sky2_hw *hw)
2797{
555382cb 2798 struct pci_dev *pdev = hw->pdev;
e3173832 2799 u16 status;
555382cb
SH		 2800 int i, cap;
2801 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2802
cd28ab6a 2803 /* disable ASF */
4f44d8ba
SH		 2804 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2805 status = sky2_read16(hw, HCU_CCSR);
2806 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2807 HCU_CCSR_UC_STATE_MSK);
2808 sky2_write16(hw, HCU_CCSR, status);
2809 } else
2810 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2811 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2812
2813 /* do a SW reset */
2814 sky2_write8(hw, B0_CTST, CS_RST_SET);
2815 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2816
ac93a394
SH		 2817 /* allow writes to PCI config */
2818 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2819
cd28ab6a 2820 /* clear PCI errors, if any */
b32f40c4 2821 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2822 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2823 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2824
2825 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2826
555382cb
SH		 2827 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2828 if (cap) {
7782c8c4
SH		 2829 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2830 0xfffffffful);
555382cb
SH		 2831
2832 /* If error bit is stuck on ignore it */
2833 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2834 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2835 else
555382cb
SH		 2836 hwe_mask |= Y2_IS_PCI_EXP;
2837 }
cd28ab6a 2838
ae306cca 2839 sky2_power_on(hw);
82637e80 2840 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2841
2842 for (i = 0; i < hw->ports; i++) {
2843 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2844 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 2845
ed4d4161
SH		 2846 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2847 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 2848 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2849 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2850 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2851 }
2852
793b883e
SH		 2853 /* Clear I2C IRQ noise */
2854 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2855
2856 /* turn off hardware timer (unused) */
2857 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2858 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2859
cd28ab6a
SH		 2860 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2861
69634ee7
SH		 2862 /* Turn off descriptor polling */
2863 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2864
2865 /* Turn off receive timestamp */
2866 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2867 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2868
2869 /* enable the Tx Arbiters */
2870 for (i = 0; i < hw->ports; i++)
2871 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2872
2873 /* Initialize ram interface */
2874 for (i = 0; i < hw->ports; i++) {
793b883e 2875 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2876
2877 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2878 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2879 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2880 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2881 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2882 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2883 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2884 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2885 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2886 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2887 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2888 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2889 }
2890
555382cb 2891 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 2892
cd28ab6a 2893 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2894 sky2_gmac_reset(hw, i);
cd28ab6a 2895
cd28ab6a
SH		 2896 memset(hw->st_le, 0, STATUS_LE_BYTES);
2897 hw->st_idx = 0;
2898
2899 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2900 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2901
2902 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2903 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2904
2905 /* Set the list last index */
793b883e 2906 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2907
290d4de5
SH		 2908 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2909 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2910
290d4de5
SH		 2911 /* set Status-FIFO ISR watermark */
2912 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2913 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2914 else
2915 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2916
290d4de5 2917 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2918 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2919 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2920
793b883e 2921 /* enable status unit */
cd28ab6a
SH		 2922 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2923
2924 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2925 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2926 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2927}
2928
81906791
SH		 2929static void sky2_restart(struct work_struct *work)
2930{
2931 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2932 struct net_device *dev;
2933 int i, err;
2934
81906791 2935 rtnl_lock();
81906791
SH		 2936 for (i = 0; i < hw->ports; i++) {
2937 dev = hw->dev[i];
2938 if (netif_running(dev))
2939 sky2_down(dev);
2940 }
2941
8cfcbe99
SH		 2942 napi_disable(&hw->napi);
2943 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 2944 sky2_reset(hw);
2945 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 2946 napi_enable(&hw->napi);
81906791
SH		 2947
2948 for (i = 0; i < hw->ports; i++) {
2949 dev = hw->dev[i];
2950 if (netif_running(dev)) {
2951 err = sky2_up(dev);
2952 if (err) {
2953 printk(KERN_INFO PFX "%s: could not restart %d\n",
2954 dev->name, err);
2955 dev_close(dev);
2956 }
2957 }
2958 }
2959
81906791
SH		 2960 rtnl_unlock();
2961}
2962
e3173832
SH		 2963static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2964{
2965 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2966}
2967
2968static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2969{
2970 const struct sky2_port *sky2 = netdev_priv(dev);
2971
2972 wol->supported = sky2_wol_supported(sky2->hw);
2973 wol->wolopts = sky2->wol;
2974}
2975
2976static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2977{
2978 struct sky2_port *sky2 = netdev_priv(dev);
2979 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2980
e3173832
SH		 2981 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2982 return -EOPNOTSUPP;
2983
2984 sky2->wol = wol->wolopts;
2985
05745c4a
SH		 2986 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2987 hw->chip_id == CHIP_ID_YUKON_EX ||
2988 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 2989 sky2_write32(hw, B0_CTST, sky2->wol
2990 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2991
2992 if (!netif_running(dev))
2993 sky2_wol_init(sky2);
cd28ab6a
SH		 2994 return 0;
2995}
2996
28bd181a 2997static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2998{
b89165f2
SH		 2999 if (sky2_is_copper(hw)) {
3000 u32 modes = SUPPORTED_10baseT_Half
3001 | SUPPORTED_10baseT_Full
3002 | SUPPORTED_100baseT_Half
3003 | SUPPORTED_100baseT_Full
3004 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3005
ea76e635 3006 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3007 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3008 | SUPPORTED_1000baseT_Full;
3009 return modes;
cd28ab6a 3010 } else
b89165f2
SH		 3011 return SUPPORTED_1000baseT_Half
3012 | SUPPORTED_1000baseT_Full
3013 | SUPPORTED_Autoneg
3014 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3015}
3016
793b883e 3017static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3018{
3019 struct sky2_port *sky2 = netdev_priv(dev);
3020 struct sky2_hw *hw = sky2->hw;
3021
3022 ecmd->transceiver = XCVR_INTERNAL;
3023 ecmd->supported = sky2_supported_modes(hw);
3024 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3025 if (sky2_is_copper(hw)) {
cd28ab6a 3026 ecmd->port = PORT_TP;
b89165f2
SH		 3027 ecmd->speed = sky2->speed;
3028 } else {
3029 ecmd->speed = SPEED_1000;
cd28ab6a 3030 ecmd->port = PORT_FIBRE;
b89165f2 3031 }
cd28ab6a
SH		 3032
3033 ecmd->advertising = sky2->advertising;
3034 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3035 ecmd->duplex = sky2->duplex;
3036 return 0;
3037}
3038
3039static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3040{
3041 struct sky2_port *sky2 = netdev_priv(dev);
3042 const struct sky2_hw *hw = sky2->hw;
3043 u32 supported = sky2_supported_modes(hw);
3044
3045 if (ecmd->autoneg == AUTONEG_ENABLE) {
3046 ecmd->advertising = supported;
3047 sky2->duplex = -1;
3048 sky2->speed = -1;
3049 } else {
3050 u32 setting;
3051
793b883e 3052 switch (ecmd->speed) {
cd28ab6a
SH		 3053 case SPEED_1000:
3054 if (ecmd->duplex == DUPLEX_FULL)
3055 setting = SUPPORTED_1000baseT_Full;
3056 else if (ecmd->duplex == DUPLEX_HALF)
3057 setting = SUPPORTED_1000baseT_Half;
3058 else
3059 return -EINVAL;
3060 break;
3061 case SPEED_100:
3062 if (ecmd->duplex == DUPLEX_FULL)
3063 setting = SUPPORTED_100baseT_Full;
3064 else if (ecmd->duplex == DUPLEX_HALF)
3065 setting = SUPPORTED_100baseT_Half;
3066 else
3067 return -EINVAL;
3068 break;
3069
3070 case SPEED_10:
3071 if (ecmd->duplex == DUPLEX_FULL)
3072 setting = SUPPORTED_10baseT_Full;
3073 else if (ecmd->duplex == DUPLEX_HALF)
3074 setting = SUPPORTED_10baseT_Half;
3075 else
3076 return -EINVAL;
3077 break;
3078 default:
3079 return -EINVAL;
3080 }
3081
3082 if ((setting & supported) == 0)
3083 return -EINVAL;
3084
3085 sky2->speed = ecmd->speed;
3086 sky2->duplex = ecmd->duplex;
3087 }
3088
3089 sky2->autoneg = ecmd->autoneg;
3090 sky2->advertising = ecmd->advertising;
3091
d1b139c0 3092 if (netif_running(dev)) {
1b537565 3093 sky2_phy_reinit(sky2);
d1b139c0
SH		 3094 sky2_set_multicast(dev);
3095 }
cd28ab6a
SH		 3096
3097 return 0;
3098}
3099
3100static void sky2_get_drvinfo(struct net_device *dev,
3101 struct ethtool_drvinfo *info)
3102{
3103 struct sky2_port *sky2 = netdev_priv(dev);
3104
3105 strcpy(info->driver, DRV_NAME);
3106 strcpy(info->version, DRV_VERSION);
3107 strcpy(info->fw_version, "N/A");
3108 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3109}
3110
3111static const struct sky2_stat {
793b883e
SH		 3112 char name[ETH_GSTRING_LEN];
3113 u16 offset;
cd28ab6a
SH		 3114} sky2_stats[] = {
3115 { "tx_bytes", GM_TXO_OK_HI },
3116 { "rx_bytes", GM_RXO_OK_HI },
3117 { "tx_broadcast", GM_TXF_BC_OK },
3118 { "rx_broadcast", GM_RXF_BC_OK },
3119 { "tx_multicast", GM_TXF_MC_OK },
3120 { "rx_multicast", GM_RXF_MC_OK },
3121 { "tx_unicast", GM_TXF_UC_OK },
3122 { "rx_unicast", GM_RXF_UC_OK },
3123 { "tx_mac_pause", GM_TXF_MPAUSE },
3124 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3125 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3126 { "late_collision",GM_TXF_LAT_COL },
3127 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3128 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3129 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3130
d2604540 3131 { "rx_short", GM_RXF_SHT },
cd28ab6a 3132 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3133 { "rx_64_byte_packets", GM_RXF_64B },
3134 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3135 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3136 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3137 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3138 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3139 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3140 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3141 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3142 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3143 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3144
3145 { "tx_64_byte_packets", GM_TXF_64B },
3146 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3147 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3148 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3149 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3150 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3151 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3152 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3153};
3154
cd28ab6a
SH		 3155static u32 sky2_get_rx_csum(struct net_device *dev)
3156{
3157 struct sky2_port *sky2 = netdev_priv(dev);
3158
3159 return sky2->rx_csum;
3160}
3161
3162static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3163{
3164 struct sky2_port *sky2 = netdev_priv(dev);
3165
3166 sky2->rx_csum = data;
793b883e 3167
cd28ab6a
SH		 3168 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3169 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3170
3171 return 0;
3172}
3173
3174static u32 sky2_get_msglevel(struct net_device *netdev)
3175{
3176 struct sky2_port *sky2 = netdev_priv(netdev);
3177 return sky2->msg_enable;
3178}
3179
9a7ae0a9
SH		 3180static int sky2_nway_reset(struct net_device *dev)
3181{
3182 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3183
16ad91e1 3184 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3185 return -EINVAL;
3186
1b537565 3187 sky2_phy_reinit(sky2);
d1b139c0 3188 sky2_set_multicast(dev);
9a7ae0a9
SH		 3189
3190 return 0;
3191}
3192
793b883e 3193static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3194{
3195 struct sky2_hw *hw = sky2->hw;
3196 unsigned port = sky2->port;
3197 int i;
3198
3199 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3200 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3201 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3202 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3203
793b883e 3204 for (i = 2; i < count; i++)
cd28ab6a
SH		 3205 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3206}
3207
cd28ab6a
SH		 3208static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3209{
3210 struct sky2_port *sky2 = netdev_priv(netdev);
3211 sky2->msg_enable = value;
3212}
3213
b9f2c044 3214static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3215{
b9f2c044
JG		 3216 switch (sset) {
3217 case ETH_SS_STATS:
3218 return ARRAY_SIZE(sky2_stats);
3219 default:
3220 return -EOPNOTSUPP;
3221 }
cd28ab6a
SH		 3222}
3223
3224static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3225 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3226{
3227 struct sky2_port *sky2 = netdev_priv(dev);
3228
793b883e 3229 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3230}
3231
793b883e 3232static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3233{
3234 int i;
3235
3236 switch (stringset) {
3237 case ETH_SS_STATS:
3238 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3239 memcpy(data + i * ETH_GSTRING_LEN,
3240 sky2_stats[i].name, ETH_GSTRING_LEN);
3241 break;
3242 }
3243}
3244
cd28ab6a
SH		 3245static int sky2_set_mac_address(struct net_device *dev, void *p)
3246{
3247 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3248 struct sky2_hw *hw = sky2->hw;
3249 unsigned port = sky2->port;
3250 const struct sockaddr *addr = p;
cd28ab6a
SH		 3251
3252 if (!is_valid_ether_addr(addr->sa_data))
3253 return -EADDRNOTAVAIL;
3254
cd28ab6a 3255 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3256 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3257 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3258 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3259 dev->dev_addr, ETH_ALEN);
1b537565 3260
a8ab1ec0
SH		 3261 /* virtual address for data */
3262 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3263
3264 /* physical address: used for pause frames */
3265 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3266
3267 return 0;
cd28ab6a
SH		 3268}
3269
a052b52f
SH		 3270static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3271{
3272 u32 bit;
3273
3274 bit = ether_crc(ETH_ALEN, addr) & 63;
3275 filter[bit >> 3] |= 1 << (bit & 7);
3276}
3277
cd28ab6a
SH		 3278static void sky2_set_multicast(struct net_device *dev)
3279{
3280 struct sky2_port *sky2 = netdev_priv(dev);
3281 struct sky2_hw *hw = sky2->hw;
3282 unsigned port = sky2->port;
3283 struct dev_mc_list *list = dev->mc_list;
3284 u16 reg;
3285 u8 filter[8];
a052b52f
SH		 3286 int rx_pause;
3287 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3288
a052b52f 3289 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3290 memset(filter, 0, sizeof(filter));
3291
3292 reg = gma_read16(hw, port, GM_RX_CTRL);
3293 reg |= GM_RXCR_UCF_ENA;
3294
d571b694 3295 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3296 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3297 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3298 memset(filter, 0xff, sizeof(filter));
a052b52f 3299 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3300 reg &= ~GM_RXCR_MCF_ENA;
3301 else {
3302 int i;
3303 reg |= GM_RXCR_MCF_ENA;
3304
a052b52f
SH		 3305 if (rx_pause)
3306 sky2_add_filter(filter, pause_mc_addr);
3307
3308 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3309 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3310 }
3311
cd28ab6a 3312 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3313 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3314 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3315 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3316 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3317 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3318 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3319 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3320
3321 gma_write16(hw, port, GM_RX_CTRL, reg);
3322}
3323
3324/* Can have one global because blinking is controlled by
3325 * ethtool and that is always under RTNL mutex
3326 */
a84d0a3d 3327static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3328{
a84d0a3d
SH		 3329 struct sky2_hw *hw = sky2->hw;
3330 unsigned port = sky2->port;
793b883e 3331
a84d0a3d
SH		 3332 spin_lock_bh(&sky2->phy_lock);
3333 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3334 hw->chip_id == CHIP_ID_YUKON_EX ||
3335 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3336 u16 pg;
793b883e
SH		 3337 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3338 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3339
a84d0a3d
SH		 3340 switch (mode) {
3341 case MO_LED_OFF:
3342 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3343 PHY_M_LEDC_LOS_CTRL(8) |
3344 PHY_M_LEDC_INIT_CTRL(8) |
3345 PHY_M_LEDC_STA1_CTRL(8) |
3346 PHY_M_LEDC_STA0_CTRL(8));
3347 break;
3348 case MO_LED_ON:
3349 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3350 PHY_M_LEDC_LOS_CTRL(9) |
3351 PHY_M_LEDC_INIT_CTRL(9) |
3352 PHY_M_LEDC_STA1_CTRL(9) |
3353 PHY_M_LEDC_STA0_CTRL(9));
3354 break;
3355 case MO_LED_BLINK:
3356 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3357 PHY_M_LEDC_LOS_CTRL(0xa) |
3358 PHY_M_LEDC_INIT_CTRL(0xa) |
3359 PHY_M_LEDC_STA1_CTRL(0xa) |
3360 PHY_M_LEDC_STA0_CTRL(0xa));
3361 break;
3362 case MO_LED_NORM:
3363 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3364 PHY_M_LEDC_LOS_CTRL(1) |
3365 PHY_M_LEDC_INIT_CTRL(8) |
3366 PHY_M_LEDC_STA1_CTRL(7) |
3367 PHY_M_LEDC_STA0_CTRL(7));
3368 }
793b883e 3369
a84d0a3d
SH		 3370 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3371 } else
0efdf262 3372 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3373 PHY_M_LED_MO_DUP(mode) |
3374 PHY_M_LED_MO_10(mode) |
3375 PHY_M_LED_MO_100(mode) |
3376 PHY_M_LED_MO_1000(mode) |
3377 PHY_M_LED_MO_RX(mode) |
3378 PHY_M_LED_MO_TX(mode));
3379
3380 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3381}
3382
3383/* blink LED's for finding board */
3384static int sky2_phys_id(struct net_device *dev, u32 data)
3385{
3386 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3387 unsigned int i;
cd28ab6a 3388
a84d0a3d
SH		 3389 if (data == 0)
3390 data = UINT_MAX;
cd28ab6a 3391
a84d0a3d
SH		 3392 for (i = 0; i < data; i++) {
3393 sky2_led(sky2, MO_LED_ON);
3394 if (msleep_interruptible(500))
3395 break;
3396 sky2_led(sky2, MO_LED_OFF);
3397 if (msleep_interruptible(500))
3398 break;
793b883e 3399 }
a84d0a3d 3400 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3401
3402 return 0;
3403}
3404
3405static void sky2_get_pauseparam(struct net_device *dev,
3406 struct ethtool_pauseparam *ecmd)
3407{
3408 struct sky2_port *sky2 = netdev_priv(dev);
3409
16ad91e1
SH		 3410 switch (sky2->flow_mode) {
3411 case FC_NONE:
3412 ecmd->tx_pause = ecmd->rx_pause = 0;
3413 break;
3414 case FC_TX:
3415 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3416 break;
3417 case FC_RX:
3418 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3419 break;
3420 case FC_BOTH:
3421 ecmd->tx_pause = ecmd->rx_pause = 1;
3422 }
3423
cd28ab6a
SH		 3424 ecmd->autoneg = sky2->autoneg;
3425}
3426
3427static int sky2_set_pauseparam(struct net_device *dev,
3428 struct ethtool_pauseparam *ecmd)
3429{
3430 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3431
3432 sky2->autoneg = ecmd->autoneg;
16ad91e1 3433 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3434
16ad91e1
SH		 3435 if (netif_running(dev))
3436 sky2_phy_reinit(sky2);
cd28ab6a 3437
2eaba1a2 3438 return 0;
cd28ab6a
SH		 3439}
3440
fb17358f
SH		 3441static int sky2_get_coalesce(struct net_device *dev,
3442 struct ethtool_coalesce *ecmd)
3443{
3444 struct sky2_port *sky2 = netdev_priv(dev);
3445 struct sky2_hw *hw = sky2->hw;
3446
3447 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3448 ecmd->tx_coalesce_usecs = 0;
3449 else {
3450 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3451 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3452 }
3453 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3454
3455 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3456 ecmd->rx_coalesce_usecs = 0;
3457 else {
3458 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3459 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3460 }
3461 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3462
3463 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3464 ecmd->rx_coalesce_usecs_irq = 0;
3465 else {
3466 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3467 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3468 }
3469
3470 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3471
3472 return 0;
3473}
3474
3475/* Note: this affect both ports */
3476static int sky2_set_coalesce(struct net_device *dev,
3477 struct ethtool_coalesce *ecmd)
3478{
3479 struct sky2_port *sky2 = netdev_priv(dev);
3480 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3481 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3482
77b3d6a2
SH		 3483 if (ecmd->tx_coalesce_usecs > tmax ||
3484 ecmd->rx_coalesce_usecs > tmax ||
3485 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3486 return -EINVAL;
3487
ff81fbbe 3488 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3489 return -EINVAL;
ff81fbbe 3490 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3491 return -EINVAL;
ff81fbbe 3492 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3493 return -EINVAL;
3494
3495 if (ecmd->tx_coalesce_usecs == 0)
3496 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3497 else {
3498 sky2_write32(hw, STAT_TX_TIMER_INI,
3499 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3500 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3501 }
3502 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3503
3504 if (ecmd->rx_coalesce_usecs == 0)
3505 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3506 else {
3507 sky2_write32(hw, STAT_LEV_TIMER_INI,
3508 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3509 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3510 }
3511 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3512
3513 if (ecmd->rx_coalesce_usecs_irq == 0)
3514 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3515 else {
d28d4870 3516 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3517 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3518 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3519 }
3520 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3521 return 0;
3522}
3523
793b883e
SH		 3524static void sky2_get_ringparam(struct net_device *dev,
3525 struct ethtool_ringparam *ering)
3526{
3527 struct sky2_port *sky2 = netdev_priv(dev);
3528
3529 ering->rx_max_pending = RX_MAX_PENDING;
3530 ering->rx_mini_max_pending = 0;
3531 ering->rx_jumbo_max_pending = 0;
3532 ering->tx_max_pending = TX_RING_SIZE - 1;
3533
3534 ering->rx_pending = sky2->rx_pending;
3535 ering->rx_mini_pending = 0;
3536 ering->rx_jumbo_pending = 0;
3537 ering->tx_pending = sky2->tx_pending;
3538}
3539
3540static int sky2_set_ringparam(struct net_device *dev,
3541 struct ethtool_ringparam *ering)
3542{
3543 struct sky2_port *sky2 = netdev_priv(dev);
3544 int err = 0;
3545
3546 if (ering->rx_pending > RX_MAX_PENDING ||
3547 ering->rx_pending < 8 ||
3548 ering->tx_pending < MAX_SKB_TX_LE ||
3549 ering->tx_pending > TX_RING_SIZE - 1)
3550 return -EINVAL;
3551
3552 if (netif_running(dev))
3553 sky2_down(dev);
3554
3555 sky2->rx_pending = ering->rx_pending;
3556 sky2->tx_pending = ering->tx_pending;
3557
1b537565 3558 if (netif_running(dev)) {
793b883e 3559 err = sky2_up(dev);
1b537565
SH		 3560 if (err)
3561 dev_close(dev);
3562 }
793b883e
SH		 3563
3564 return err;
3565}
3566
793b883e
SH		 3567static int sky2_get_regs_len(struct net_device *dev)
3568{
6e4cbb34 3569 return 0x4000;
793b883e
SH		 3570}
3571
3572/*
3573 * Returns copy of control register region
3ead5db7 3574 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3575 */
3576static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3577 void *p)
3578{
3579 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3580 const void __iomem *io = sky2->hw->regs;
295b54c4 3581 unsigned int b;
793b883e
SH		 3582
3583 regs->version = 1;
793b883e 3584
295b54c4
SH		 3585 for (b = 0; b < 128; b++) {
3586 /* This complicated switch statement is to make sure and
3587 * only access regions that are unreserved.
3588 * Some blocks are only valid on dual port cards.
3589 * and block 3 has some special diagnostic registers that
3590 * are poison.
3591 */
3592 switch (b) {
3593 case 3:
3594 /* skip diagnostic ram region */
3595 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3596 break;
3ead5db7 3597
295b54c4
SH		 3598 /* dual port cards only */
3599 case 5: /* Tx Arbiter 2 */
3600 case 9: /* RX2 */
3601 case 14 ... 15: /* TX2 */
3602 case 17: case 19: /* Ram Buffer 2 */
3603 case 22 ... 23: /* Tx Ram Buffer 2 */
3604 case 25: /* Rx MAC Fifo 1 */
3605 case 27: /* Tx MAC Fifo 2 */
3606 case 31: /* GPHY 2 */
3607 case 40 ... 47: /* Pattern Ram 2 */
3608 case 52: case 54: /* TCP Segmentation 2 */
3609 case 112 ... 116: /* GMAC 2 */
3610 if (sky2->hw->ports == 1)
3611 goto reserved;
3612 /* fall through */
3613 case 0: /* Control */
3614 case 2: /* Mac address */
3615 case 4: /* Tx Arbiter 1 */
3616 case 7: /* PCI express reg */
3617 case 8: /* RX1 */
3618 case 12 ... 13: /* TX1 */
3619 case 16: case 18:/* Rx Ram Buffer 1 */
3620 case 20 ... 21: /* Tx Ram Buffer 1 */
3621 case 24: /* Rx MAC Fifo 1 */
3622 case 26: /* Tx MAC Fifo 1 */
3623 case 28 ... 29: /* Descriptor and status unit */
3624 case 30: /* GPHY 1*/
3625 case 32 ... 39: /* Pattern Ram 1 */
3626 case 48: case 50: /* TCP Segmentation 1 */
3627 case 56 ... 60: /* PCI space */
3628 case 80 ... 84: /* GMAC 1 */
3629 memcpy_fromio(p, io, 128);
3630 break;
3631 default:
3632reserved:
3633 memset(p, 0, 128);
3634 }
3ead5db7 3635
295b54c4
SH		 3636 p += 128;
3637 io += 128;
3638 }
793b883e 3639}
cd28ab6a 3640
b628ed98
SH		 3641/* In order to do Jumbo packets on these chips, need to turn off the
3642 * transmit store/forward. Therefore checksum offload won't work.
3643 */
3644static int no_tx_offload(struct net_device *dev)
3645{
3646 const struct sky2_port *sky2 = netdev_priv(dev);
3647 const struct sky2_hw *hw = sky2->hw;
3648
69161611 3649 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3650}
3651
3652static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3653{
3654 if (data && no_tx_offload(dev))
3655 return -EINVAL;
3656
3657 return ethtool_op_set_tx_csum(dev, data);
3658}
3659
3660
3661static int sky2_set_tso(struct net_device *dev, u32 data)
3662{
3663 if (data && no_tx_offload(dev))
3664 return -EINVAL;
3665
3666 return ethtool_op_set_tso(dev, data);
3667}
3668
f4331a6d
SH		 3669static int sky2_get_eeprom_len(struct net_device *dev)
3670{
3671 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3672 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3673 u16 reg2;
3674
b32f40c4 3675 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3676 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3677}
3678
b32f40c4 3679static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
f4331a6d 3680{
167f53d0 3681 u32 val;
f4331a6d 3682
b32f40c4 3683 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
167f53d0
SH		 3684
3685 do {
b32f40c4 3686 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0
SH		 3687 } while (!(offset & PCI_VPD_ADDR_F));
3688
b32f40c4 3689 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
167f53d0 3690 return val;
f4331a6d
SH		 3691}
3692
b32f40c4 3693static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
f4331a6d 3694{
b32f40c4
SH		 3695 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3696 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
f4331a6d 3697 do {
b32f40c4 3698 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0 3699 } while (offset & PCI_VPD_ADDR_F);
f4331a6d
SH		 3700}
3701
3702static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3703 u8 *data)
3704{
3705 struct sky2_port *sky2 = netdev_priv(dev);
3706 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3707 int length = eeprom->len;
3708 u16 offset = eeprom->offset;
3709
3710 if (!cap)
3711 return -EINVAL;
3712
3713 eeprom->magic = SKY2_EEPROM_MAGIC;
3714
3715 while (length > 0) {
b32f40c4 3716 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3717 int n = min_t(int, length, sizeof(val));
3718
3719 memcpy(data, &val, n);
3720 length -= n;
3721 data += n;
3722 offset += n;
3723 }
3724 return 0;
3725}
3726
3727static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3728 u8 *data)
3729{
3730 struct sky2_port *sky2 = netdev_priv(dev);
3731 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3732 int length = eeprom->len;
3733 u16 offset = eeprom->offset;
3734
3735 if (!cap)
3736 return -EINVAL;
3737
3738 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3739 return -EINVAL;
3740
3741 while (length > 0) {
3742 u32 val;
3743 int n = min_t(int, length, sizeof(val));
3744
3745 if (n < sizeof(val))
b32f40c4 3746 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3747 memcpy(&val, data, n);
3748
b32f40c4 3749 sky2_vpd_write(sky2->hw, cap, offset, val);
f4331a6d
SH		 3750
3751 length -= n;
3752 data += n;
3753 offset += n;
3754 }
3755 return 0;
3756}
3757
3758
7282d491 3759static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3760 .get_settings = sky2_get_settings,
3761 .set_settings = sky2_set_settings,
3762 .get_drvinfo = sky2_get_drvinfo,
3763 .get_wol = sky2_get_wol,
3764 .set_wol = sky2_set_wol,
3765 .get_msglevel = sky2_get_msglevel,
3766 .set_msglevel = sky2_set_msglevel,
3767 .nway_reset = sky2_nway_reset,
3768 .get_regs_len = sky2_get_regs_len,
3769 .get_regs = sky2_get_regs,
3770 .get_link = ethtool_op_get_link,
3771 .get_eeprom_len = sky2_get_eeprom_len,
3772 .get_eeprom = sky2_get_eeprom,
3773 .set_eeprom = sky2_set_eeprom,
f4331a6d 3774 .set_sg = ethtool_op_set_sg,
f4331a6d 3775 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3776 .set_tso = sky2_set_tso,
3777 .get_rx_csum = sky2_get_rx_csum,
3778 .set_rx_csum = sky2_set_rx_csum,
3779 .get_strings = sky2_get_strings,
3780 .get_coalesce = sky2_get_coalesce,
3781 .set_coalesce = sky2_set_coalesce,
3782 .get_ringparam = sky2_get_ringparam,
3783 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3784 .get_pauseparam = sky2_get_pauseparam,
3785 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3786 .phys_id = sky2_phys_id,
b9f2c044 3787 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3788 .get_ethtool_stats = sky2_get_ethtool_stats,
3789};
3790
3cf26753
SH		 3791#ifdef CONFIG_SKY2_DEBUG
3792
3793static struct dentry *sky2_debug;
3794
3795static int sky2_debug_show(struct seq_file *seq, void *v)
3796{
3797 struct net_device *dev = seq->private;
3798 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 3799 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 3800 unsigned port = sky2->port;
3801 unsigned idx, last;
3802 int sop;
3803
3804 if (!netif_running(dev))
3805 return -ENETDOWN;
3806
3807 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3808 sky2_read32(hw, B0_ISRC),
3809 sky2_read32(hw, B0_IMSK),
3810 sky2_read32(hw, B0_Y2_SP_ICR));
3811
bea3348e 3812 napi_disable(&hw->napi);
3cf26753
SH		 3813 last = sky2_read16(hw, STAT_PUT_IDX);
3814
3815 if (hw->st_idx == last)
3816 seq_puts(seq, "Status ring (empty)\n");
3817 else {
3818 seq_puts(seq, "Status ring\n");
3819 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3820 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3821 const struct sky2_status_le *le = hw->st_le + idx;
3822 seq_printf(seq, "[%d] %#x %d %#x\n",
3823 idx, le->opcode, le->length, le->status);
3824 }
3825 seq_puts(seq, "\n");
3826 }
3827
3828 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3829 sky2->tx_cons, sky2->tx_prod,
3830 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3831 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3832
3833 /* Dump contents of tx ring */
3834 sop = 1;
3835 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3836 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3837 const struct sky2_tx_le *le = sky2->tx_le + idx;
3838 u32 a = le32_to_cpu(le->addr);
3839
3840 if (sop)
3841 seq_printf(seq, "%u:", idx);
3842 sop = 0;
3843
3844 switch(le->opcode & ~HW_OWNER) {
3845 case OP_ADDR64:
3846 seq_printf(seq, " %#x:", a);
3847 break;
3848 case OP_LRGLEN:
3849 seq_printf(seq, " mtu=%d", a);
3850 break;
3851 case OP_VLAN:
3852 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3853 break;
3854 case OP_TCPLISW:
3855 seq_printf(seq, " csum=%#x", a);
3856 break;
3857 case OP_LARGESEND:
3858 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3859 break;
3860 case OP_PACKET:
3861 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3862 break;
3863 case OP_BUFFER:
3864 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3865 break;
3866 default:
3867 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3868 a, le16_to_cpu(le->length));
3869 }
3870
3871 if (le->ctrl & EOP) {
3872 seq_putc(seq, '\n');
3873 sop = 1;
3874 }
3875 }
3876
3877 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3878 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3879 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3880 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3881
d1d08d12 3882 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 3883 napi_enable(&hw->napi);
3cf26753
SH		 3884 return 0;
3885}
3886
3887static int sky2_debug_open(struct inode *inode, struct file *file)
3888{
3889 return single_open(file, sky2_debug_show, inode->i_private);
3890}
3891
3892static const struct file_operations sky2_debug_fops = {
3893 .owner = THIS_MODULE,
3894 .open = sky2_debug_open,
3895 .read = seq_read,
3896 .llseek = seq_lseek,
3897 .release = single_release,
3898};
3899
3900/*
3901 * Use network device events to create/remove/rename
3902 * debugfs file entries
3903 */
3904static int sky2_device_event(struct notifier_block *unused,
3905 unsigned long event, void *ptr)
3906{
3907 struct net_device *dev = ptr;
5b296bc9 3908 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 3909
5b296bc9
SH		 3910 if (dev->open != sky2_up || !sky2_debug)
3911 return NOTIFY_DONE;
3cf26753 3912
5b296bc9
SH		 3913 switch(event) {
3914 case NETDEV_CHANGENAME:
3915 if (sky2->debugfs) {
3916 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3917 sky2_debug, dev->name);
3918 }
3919 break;
3cf26753 3920
5b296bc9
SH		 3921 case NETDEV_GOING_DOWN:
3922 if (sky2->debugfs) {
3923 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3924 dev->name);
3925 debugfs_remove(sky2->debugfs);
3926 sky2->debugfs = NULL;
3cf26753 3927 }
5b296bc9
SH		 3928 break;
3929
3930 case NETDEV_UP:
3931 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3932 sky2_debug, dev,
3933 &sky2_debug_fops);
3934 if (IS_ERR(sky2->debugfs))
3935 sky2->debugfs = NULL;
3cf26753
SH		 3936 }
3937
3938 return NOTIFY_DONE;
3939}
3940
3941static struct notifier_block sky2_notifier = {
3942 .notifier_call = sky2_device_event,
3943};
3944
3945
3946static __init void sky2_debug_init(void)
3947{
3948 struct dentry *ent;
3949
3950 ent = debugfs_create_dir("sky2", NULL);
3951 if (!ent || IS_ERR(ent))
3952 return;
3953
3954 sky2_debug = ent;
3955 register_netdevice_notifier(&sky2_notifier);
3956}
3957
3958static __exit void sky2_debug_cleanup(void)
3959{
3960 if (sky2_debug) {
3961 unregister_netdevice_notifier(&sky2_notifier);
3962 debugfs_remove(sky2_debug);
3963 sky2_debug = NULL;
3964 }
3965}
3966
3967#else
3968#define sky2_debug_init()
3969#define sky2_debug_cleanup()
3970#endif
3971
3972
cd28ab6a
SH		 3973/* Initialize network device */
3974static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 3975 unsigned port,
be63a21c 3976 int highmem, int wol)
cd28ab6a
SH		 3977{
3978 struct sky2_port *sky2;
3979 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3980
3981 if (!dev) {
898eb71c 3982 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 3983 return NULL;
3984 }
3985
cd28ab6a 3986 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3987 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3988 dev->open = sky2_up;
3989 dev->stop = sky2_down;
ef743d33 3990 dev->do_ioctl = sky2_ioctl;
cd28ab6a 3991 dev->hard_start_xmit = sky2_xmit_frame;
cd28ab6a
SH		 3992 dev->set_multicast_list = sky2_set_multicast;
3993 dev->set_mac_address = sky2_set_mac_address;
3994 dev->change_mtu = sky2_change_mtu;
3995 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3996 dev->tx_timeout = sky2_tx_timeout;
3997 dev->watchdog_timeo = TX_WATCHDOG;
cd28ab6a 3998#ifdef CONFIG_NET_POLL_CONTROLLER
a5e68c02
SH		 3999 if (port == 0)
4000 dev->poll_controller = sky2_netpoll;
cd28ab6a 4001#endif
cd28ab6a
SH		 4002
4003 sky2 = netdev_priv(dev);
4004 sky2->netdev = dev;
4005 sky2->hw = hw;
4006 sky2->msg_enable = netif_msg_init(debug, default_msg);
4007
cd28ab6a
SH		 4008 /* Auto speed and flow control */
4009 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 4010 sky2->flow_mode = FC_BOTH;
4011
cd28ab6a
SH		 4012 sky2->duplex = -1;
4013 sky2->speed = -1;
4014 sky2->advertising = sky2_supported_modes(hw);
8b31cfbc 4015 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
be63a21c 4016 sky2->wol = wol;
75d070c5 4017
e07b1aa8 4018 spin_lock_init(&sky2->phy_lock);
793b883e 4019 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 4020 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4021
4022 hw->dev[port] = dev;
4023
4024 sky2->port = port;
4025
4a50a876 4026 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4027 if (highmem)
4028 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4029
d1f13708 4030#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4031 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4032 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4033 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4034 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4035 dev->vlan_rx_register = sky2_vlan_rx_register;
4036 }
d1f13708 4037#endif
4038
cd28ab6a 4039 /* read the mac address */
793b883e 4040 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4041 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4042
cd28ab6a
SH		 4043 return dev;
4044}
4045
28bd181a 4046static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4047{
4048 const struct sky2_port *sky2 = netdev_priv(dev);
0795af57 4049 DECLARE_MAC_BUF(mac);
cd28ab6a
SH		 4050
4051 if (netif_msg_probe(sky2))
0795af57
JP		 4052 printk(KERN_INFO PFX "%s: addr %s\n",
4053 dev->name, print_mac(mac, dev->dev_addr));
cd28ab6a
SH		 4054}
4055
fb2690a9 4056/* Handle software interrupt used during MSI test */
7d12e780 4057static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4058{
4059 struct sky2_hw *hw = dev_id;
4060 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4061
4062 if (status == 0)
4063 return IRQ_NONE;
4064
4065 if (status & Y2_IS_IRQ_SW) {
ea76e635 4066 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4067 wake_up(&hw->msi_wait);
4068 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4069 }
4070 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4071
4072 return IRQ_HANDLED;
4073}
4074
4075/* Test interrupt path by forcing a a software IRQ */
4076static int __devinit sky2_test_msi(struct sky2_hw *hw)
4077{
4078 struct pci_dev *pdev = hw->pdev;
4079 int err;
4080
bb507fe1 4081 init_waitqueue_head (&hw->msi_wait);
4082
fb2690a9
SH		 4083 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4084
b0a20ded 4085 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4086 if (err) {
b02a9258 4087 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4088 return err;
4089 }
4090
fb2690a9 4091 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4092 sky2_read8(hw, B0_CTST);
fb2690a9 4093
ea76e635 4094 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4095
ea76e635 4096 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4097 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4098 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4099 "switching to INTx mode.\n");
fb2690a9
SH		 4100
4101 err = -EOPNOTSUPP;
4102 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4103 }
4104
4105 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4106 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4107
4108 free_irq(pdev->irq, hw);
4109
4110 return err;
4111}
4112
be63a21c
SH		 4113static int __devinit pci_wake_enabled(struct pci_dev *dev)
4114{
4115 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4116 u16 value;
4117
4118 if (!pm)
4119 return 0;
4120 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4121 return 0;
4122 return value & PCI_PM_CTRL_PME_ENABLE;
4123}
4124
cd28ab6a
SH		 4125static int __devinit sky2_probe(struct pci_dev *pdev,
4126 const struct pci_device_id *ent)
4127{
7f60c64b 4128 struct net_device *dev;
cd28ab6a 4129 struct sky2_hw *hw;
be63a21c 4130 int err, using_dac = 0, wol_default;
cd28ab6a 4131
793b883e
SH		 4132 err = pci_enable_device(pdev);
4133 if (err) {
b02a9258 4134 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4135 goto err_out;
4136 }
4137
793b883e
SH		 4138 err = pci_request_regions(pdev, DRV_NAME);
4139 if (err) {
b02a9258 4140 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4141 goto err_out_disable;
cd28ab6a
SH		 4142 }
4143
4144 pci_set_master(pdev);
4145
d1f3d4dd
SH		 4146 if (sizeof(dma_addr_t) > sizeof(u32) &&
4147 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4148 using_dac = 1;
4149 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4150 if (err < 0) {
b02a9258
SH		 4151 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4152 "for consistent allocations\n");
d1f3d4dd
SH		 4153 goto err_out_free_regions;
4154 }
d1f3d4dd 4155 } else {
cd28ab6a
SH		 4156 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4157 if (err) {
b02a9258 4158 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4159 goto err_out_free_regions;
4160 }
4161 }
d1f3d4dd 4162
be63a21c
SH		 4163 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4164
cd28ab6a 4165 err = -ENOMEM;
6aad85d6 4166 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4167 if (!hw) {
b02a9258 4168 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4169 goto err_out_free_regions;
4170 }
4171
cd28ab6a 4172 hw->pdev = pdev;
cd28ab6a
SH		 4173
4174 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4175 if (!hw->regs) {
b02a9258 4176 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4177 goto err_out_free_hw;
4178 }
4179
56a645cc 4180#ifdef __BIG_ENDIAN
f65b138c
SH		 4181 /* The sk98lin vendor driver uses hardware byte swapping but
4182 * this driver uses software swapping.
4183 */
56a645cc
SH		 4184 {
4185 u32 reg;
b32f40c4 4186 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 4187 reg &= ~PCI_REV_DESC;
b32f40c4 4188 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
56a645cc
SH		 4189 }
4190#endif
4191
08c06d8a 4192 /* ring for status responses */
167f53d0 4193 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4194 if (!hw->st_le)
4195 goto err_out_iounmap;
4196
e3173832 4197 err = sky2_init(hw);
cd28ab6a 4198 if (err)
793b883e 4199 goto err_out_iounmap;
cd28ab6a 4200
b02a9258 4201 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 4202 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4203 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 4204 hw->chip_id, hw->chip_rev);
cd28ab6a 4205
e3173832
SH		 4206 sky2_reset(hw);
4207
be63a21c 4208 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4209 if (!dev) {
4210 err = -ENOMEM;
cd28ab6a 4211 goto err_out_free_pci;
7f60c64b 4212 }
cd28ab6a 4213
9fa1b1f3
SH		 4214 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4215 err = sky2_test_msi(hw);
4216 if (err == -EOPNOTSUPP)
4217 pci_disable_msi(pdev);
4218 else if (err)
4219 goto err_out_free_netdev;
4220 }
4221
793b883e
SH		 4222 err = register_netdev(dev);
4223 if (err) {
b02a9258 4224 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4225 goto err_out_free_netdev;
4226 }
4227
6de16237
SH		 4228 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4229
ea76e635
SH		 4230 err = request_irq(pdev->irq, sky2_intr,
4231 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4232 dev->name, hw);
9fa1b1f3 4233 if (err) {
b02a9258 4234 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4235 goto err_out_unregister;
4236 }
4237 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4238 napi_enable(&hw->napi);
9fa1b1f3 4239
cd28ab6a
SH		 4240 sky2_show_addr(dev);
4241
7f60c64b 4242 if (hw->ports > 1) {
4243 struct net_device *dev1;
4244
be63a21c 4245 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4246 if (!dev1)
4247 dev_warn(&pdev->dev, "allocation for second device failed\n");
4248 else if ((err = register_netdev(dev1))) {
4249 dev_warn(&pdev->dev,
4250 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4251 hw->dev[1] = NULL;
4252 free_netdev(dev1);
b02a9258
SH		 4253 } else
4254 sky2_show_addr(dev1);
cd28ab6a
SH		 4255 }
4256
32c2c300 4257 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4258 INIT_WORK(&hw->restart_work, sky2_restart);
4259
793b883e
SH		 4260 pci_set_drvdata(pdev, hw);
4261
cd28ab6a
SH		 4262 return 0;
4263
793b883e 4264err_out_unregister:
ea76e635 4265 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4266 pci_disable_msi(pdev);
793b883e 4267 unregister_netdev(dev);
cd28ab6a
SH		 4268err_out_free_netdev:
4269 free_netdev(dev);
cd28ab6a 4270err_out_free_pci:
793b883e 4271 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4272 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4273err_out_iounmap:
4274 iounmap(hw->regs);
4275err_out_free_hw:
4276 kfree(hw);
4277err_out_free_regions:
4278 pci_release_regions(pdev);
44a1d2e5 4279err_out_disable:
cd28ab6a 4280 pci_disable_device(pdev);
cd28ab6a 4281err_out:
549a68c3 4282 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4283 return err;
4284}
4285
4286static void __devexit sky2_remove(struct pci_dev *pdev)
4287{
793b883e 4288 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4289 int i;
cd28ab6a 4290
793b883e 4291 if (!hw)
cd28ab6a
SH		 4292 return;
4293
32c2c300 4294 del_timer_sync(&hw->watchdog_timer);
6de16237 4295 cancel_work_sync(&hw->restart_work);
d27ed387 4296
b877fe28 4297 for (i = hw->ports-1; i >= 0; --i)
6de16237 4298 unregister_netdev(hw->dev[i]);
81906791 4299
d27ed387 4300 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4301
ae306cca
SH		 4302 sky2_power_aux(hw);
4303
cd28ab6a 4304 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4305 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4306 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4307
4308 free_irq(pdev->irq, hw);
ea76e635 4309 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4310 pci_disable_msi(pdev);
793b883e 4311 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4312 pci_release_regions(pdev);
4313 pci_disable_device(pdev);
793b883e 4314
b877fe28 4315 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4316 free_netdev(hw->dev[i]);
4317
cd28ab6a
SH		 4318 iounmap(hw->regs);
4319 kfree(hw);
5afa0a9c 4320
cd28ab6a
SH		 4321 pci_set_drvdata(pdev, NULL);
4322}
4323
4324#ifdef CONFIG_PM
4325static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4326{
793b883e 4327 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4328 int i, wol = 0;
cd28ab6a 4329
549a68c3
SH		 4330 if (!hw)
4331 return 0;
4332
063a0b38
SH		 4333 del_timer_sync(&hw->watchdog_timer);
4334 cancel_work_sync(&hw->restart_work);
4335
f05267e7 4336 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4337 struct net_device *dev = hw->dev[i];
e3173832 4338 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4339
063a0b38 4340 netif_device_detach(dev);
e3173832 4341 if (netif_running(dev))
5afa0a9c 4342 sky2_down(dev);
e3173832
SH		 4343
4344 if (sky2->wol)
4345 sky2_wol_init(sky2);
4346
4347 wol |= sky2->wol;
cd28ab6a
SH		 4348 }
4349
8ab8fca2 4350 sky2_write32(hw, B0_IMSK, 0);
6de16237 4351 napi_disable(&hw->napi);
ae306cca 4352 sky2_power_aux(hw);
e3173832 4353
d374c1c1 4354 pci_save_state(pdev);
e3173832 4355 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 4356 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4357
2ccc99b7 4358 return 0;
cd28ab6a
SH		 4359}
4360
4361static int sky2_resume(struct pci_dev *pdev)
4362{
793b883e 4363 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4364 int i, err;
cd28ab6a 4365
549a68c3
SH		 4366 if (!hw)
4367 return 0;
4368
ae306cca
SH		 4369 err = pci_set_power_state(pdev, PCI_D0);
4370 if (err)
4371 goto out;
4372
4373 err = pci_restore_state(pdev);
4374 if (err)
4375 goto out;
4376
cd28ab6a 4377 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4378
4379 /* Re-enable all clocks */
05745c4a
SH		 4380 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4381 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4382 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4383 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4384
e3173832 4385 sky2_reset(hw);
8ab8fca2 4386 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4387 napi_enable(&hw->napi);
8ab8fca2 4388
f05267e7 4389 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4390 struct net_device *dev = hw->dev[i];
063a0b38
SH		 4391
4392 netif_device_attach(dev);
6a5706b9 4393 if (netif_running(dev)) {
08c06d8a
SH		 4394 err = sky2_up(dev);
4395 if (err) {
4396 printk(KERN_ERR PFX "%s: could not up: %d\n",
4397 dev->name, err);
4398 dev_close(dev);
eb35cf60 4399 goto out;
5afa0a9c 4400 }
cd28ab6a
SH		 4401 }
4402 }
eb35cf60 4403
ae306cca 4404 return 0;
08c06d8a 4405out:
b02a9258 4406 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4407 pci_disable_device(pdev);
08c06d8a 4408 return err;
cd28ab6a
SH		 4409}
4410#endif
4411
e3173832
SH		 4412static void sky2_shutdown(struct pci_dev *pdev)
4413{
4414 struct sky2_hw *hw = pci_get_drvdata(pdev);
4415 int i, wol = 0;
4416
549a68c3
SH		 4417 if (!hw)
4418 return;
4419
5c0d6b34 4420 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4421
4422 for (i = 0; i < hw->ports; i++) {
4423 struct net_device *dev = hw->dev[i];
4424 struct sky2_port *sky2 = netdev_priv(dev);
4425
4426 if (sky2->wol) {
4427 wol = 1;
4428 sky2_wol_init(sky2);
4429 }
4430 }
4431
4432 if (wol)
4433 sky2_power_aux(hw);
4434
4435 pci_enable_wake(pdev, PCI_D3hot, wol);
4436 pci_enable_wake(pdev, PCI_D3cold, wol);
4437
4438 pci_disable_device(pdev);
4439 pci_set_power_state(pdev, PCI_D3hot);
4440
4441}
4442
cd28ab6a 4443static struct pci_driver sky2_driver = {
793b883e
SH		 4444 .name = DRV_NAME,
4445 .id_table = sky2_id_table,
4446 .probe = sky2_probe,
4447 .remove = __devexit_p(sky2_remove),
cd28ab6a 4448#ifdef CONFIG_PM
793b883e
SH		 4449 .suspend = sky2_suspend,
4450 .resume = sky2_resume,
cd28ab6a 4451#endif
e3173832 4452 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4453};
4454
4455static int __init sky2_init_module(void)
4456{
3cf26753 4457 sky2_debug_init();
50241c4c 4458 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4459}
4460
4461static void __exit sky2_cleanup_module(void)
4462{
4463 pci_unregister_driver(&sky2_driver);
3cf26753 4464 sky2_debug_cleanup();
cd28ab6a
SH		 4465}
4466
4467module_init(sky2_init_module);
4468module_exit(sky2_cleanup_module);
4469
4470MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4471MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4472MODULE_LICENSE("GPL");
5f4f9dc1 4473MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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