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Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
cd28ab6a 26#include <linux/config.h>
793b883e 27#include <linux/crc32.h>
cd28ab6a
SH		 28#include <linux/kernel.h>
29#include <linux/version.h>
30#include <linux/module.h>
31#include <linux/netdevice.h>
d0bbccfa 32#include <linux/dma-mapping.h>
cd28ab6a
SH		 33#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/pci.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/in.h>
39#include <linux/delay.h>
91c86df5 40#include <linux/workqueue.h>
d1f13708 41#include <linux/if_vlan.h>
d70cd51a 42#include <linux/prefetch.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
6d4b0f61 54#define DRV_VERSION "1.3"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
62 */
63
13210ce5 64#define RX_LE_SIZE 512
cd28ab6a 65#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
bea86103 66#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
13210ce5 67#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 68#define RX_SKB_ALIGN 8
793b883e
SH		 69
70#define TX_RING_SIZE 512
71#define TX_DEF_PENDING (TX_RING_SIZE - 1)
72#define TX_MIN_PENDING 64
b19666d9 73#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 74
793b883e 75#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 76#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77#define ETH_JUMBO_MTU 9000
78#define TX_WATCHDOG (5 * HZ)
79#define NAPI_WEIGHT 64
80#define PHY_RETRIES 1000
81
cb5d9547
SH		 82#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
cd28ab6a 84static const u32 default_msg =
793b883e
SH		 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 88
793b883e 89static int debug = -1; /* defaults above */
cd28ab6a
SH		 90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
bdb5c58e
SH		 93static int copybreak __read_mostly = 256;
94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
fb2690a9
SH		 97static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
01bd7564
SH		 101static int idle_timeout = 100;
102module_param(idle_timeout, int, 0);
103MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
104
cd28ab6a 105static const struct pci_device_id sky2_id_table[] = {
793b883e 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a 107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
cd28ab6a
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
cd28ab6a
SH		 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
cd28ab6a
SH		 123 { 0 }
124};
793b883e 125
cd28ab6a
SH		 126MODULE_DEVICE_TABLE(pci, sky2_id_table);
127
128/* Avoid conditionals by using array */
129static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
130static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 131static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 132
92f965e8
SH		 133/* This driver supports yukon2 chipset only */
134static const char *yukon2_name[] = {
135 "XL", /* 0xb3 */
136 "EC Ultra", /* 0xb4 */
137 "UNKNOWN", /* 0xb5 */
138 "EC", /* 0xb6 */
139 "FE", /* 0xb7 */
793b883e
SH		 140};
141
793b883e 142/* Access to external PHY */
ef743d33 143static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 144{
145 int i;
146
147 gma_write16(hw, port, GM_SMI_DATA, val);
148 gma_write16(hw, port, GM_SMI_CTRL,
149 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
150
151 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 152 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 153 return 0;
793b883e 154 udelay(1);
cd28ab6a 155 }
ef743d33 156
793b883e 157 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 158 return -ETIMEDOUT;
cd28ab6a
SH		 159}
160
ef743d33 161static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 162{
163 int i;
164
793b883e 165 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 166 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
167
168 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33 169 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
170 *val = gma_read16(hw, port, GM_SMI_DATA);
171 return 0;
172 }
173
793b883e 174 udelay(1);
cd28ab6a
SH		 175 }
176
ef743d33 177 return -ETIMEDOUT;
178}
179
180static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
181{
182 u16 v;
183
184 if (__gm_phy_read(hw, port, reg, &v) != 0)
185 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
186 return v;
cd28ab6a
SH		 187}
188
5afa0a9c 189static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
190{
191 u16 power_control;
192 u32 reg1;
193 int vaux;
194 int ret = 0;
195
196 pr_debug("sky2_set_power_state %d\n", state);
197 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
198
56a645cc 199 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 200 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c 201 (power_control & PCI_PM_CAP_PME_D3cold);
202
56a645cc 203 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c 204
205 power_control |= PCI_PM_CTRL_PME_STATUS;
206 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
207
208 switch (state) {
209 case PCI_D0:
210 /* switch power to VCC (WA for VAUX problem) */
211 sky2_write8(hw, B0_POWER_CTRL,
212 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
213
214 /* disable Core Clock Division, */
215 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
216
217 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
218 /* enable bits are inverted */
219 sky2_write8(hw, B2_Y2_CLK_GATE,
220 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
221 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
222 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
223 else
224 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
225
226 /* Turn off phy power saving */
56a645cc 227 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
5afa0a9c 228 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
229
d571b694 230 /* looks like this XL is back asswards .. */
5afa0a9c 231 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
232 reg1 |= PCI_Y2_PHY1_COMA;
233 if (hw->ports > 1)
234 reg1 |= PCI_Y2_PHY2_COMA;
235 }
977bdf06
SH		 236
237 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
56a645cc
SH		 238 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
239 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 240 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 241 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
242 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 243 }
244
56a645cc 245 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
977bdf06 246
5afa0a9c 247 break;
248
249 case PCI_D3hot:
250 case PCI_D3cold:
251 /* Turn on phy power saving */
56a645cc 252 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
5afa0a9c 253 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
254 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
255 else
256 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
56a645cc 257 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
5afa0a9c 258
259 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
260 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
261 else
262 /* enable bits are inverted */
263 sky2_write8(hw, B2_Y2_CLK_GATE,
264 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
265 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
266 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
267
268 /* switch power to VAUX */
269 if (vaux && state != PCI_D3cold)
270 sky2_write8(hw, B0_POWER_CTRL,
271 (PC_VAUX_ENA | PC_VCC_ENA |
272 PC_VAUX_ON | PC_VCC_OFF));
273 break;
274 default:
275 printk(KERN_ERR PFX "Unknown power state %d\n", state);
276 ret = -1;
277 }
278
56a645cc 279 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c 280 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
281 return ret;
282}
283
cd28ab6a
SH		 284static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
285{
286 u16 reg;
287
288 /* disable all GMAC IRQ's */
289 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
290 /* disable PHY IRQs */
291 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 292
cd28ab6a
SH		 293 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
294 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
297
298 reg = gma_read16(hw, port, GM_RX_CTRL);
299 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
300 gma_write16(hw, port, GM_RX_CTRL, reg);
301}
302
303static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
304{
305 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
793b883e 306 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
cd28ab6a 307
ed6d32c7
SH		 308 if (sky2->autoneg == AUTONEG_ENABLE &&
309 (hw->chip_id != CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 310 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
311
312 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 313 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 314 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
315
316 if (hw->chip_id == CHIP_ID_YUKON_EC)
317 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
318 else
319 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
320
321 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
322 }
323
324 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
325 if (hw->copper) {
326 if (hw->chip_id == CHIP_ID_YUKON_FE) {
327 /* enable automatic crossover */
328 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
329 } else {
330 /* disable energy detect */
331 ctrl &= ~PHY_M_PC_EN_DET_MSK;
332
333 /* enable automatic crossover */
334 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
335
336 if (sky2->autoneg == AUTONEG_ENABLE &&
ed6d32c7 337 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 338 ctrl &= ~PHY_M_PC_DSC_MSK;
339 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
340 }
341 }
342 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
343 } else {
344 /* workaround for deviation #4.88 (CRC errors) */
345 /* disable Automatic Crossover */
346
347 ctrl &= ~PHY_M_PC_MDIX_MSK;
348 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
349
350 if (hw->chip_id == CHIP_ID_YUKON_XL) {
351 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
352 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
354 ctrl &= ~PHY_M_MAC_MD_MSK;
355 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
356 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
357
358 /* select page 1 to access Fiber registers */
359 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
360 }
cd28ab6a
SH		 361 }
362
363 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
364 if (sky2->autoneg == AUTONEG_DISABLE)
365 ctrl &= ~PHY_CT_ANE;
366 else
367 ctrl |= PHY_CT_ANE;
368
369 ctrl |= PHY_CT_RESET;
370 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
371
372 ctrl = 0;
373 ct1000 = 0;
374 adv = PHY_AN_CSMA;
375
376 if (sky2->autoneg == AUTONEG_ENABLE) {
377 if (hw->copper) {
378 if (sky2->advertising & ADVERTISED_1000baseT_Full)
379 ct1000 |= PHY_M_1000C_AFD;
380 if (sky2->advertising & ADVERTISED_1000baseT_Half)
381 ct1000 |= PHY_M_1000C_AHD;
382 if (sky2->advertising & ADVERTISED_100baseT_Full)
383 adv |= PHY_M_AN_100_FD;
384 if (sky2->advertising & ADVERTISED_100baseT_Half)
385 adv |= PHY_M_AN_100_HD;
386 if (sky2->advertising & ADVERTISED_10baseT_Full)
387 adv |= PHY_M_AN_10_FD;
388 if (sky2->advertising & ADVERTISED_10baseT_Half)
389 adv |= PHY_M_AN_10_HD;
793b883e 390 } else /* special defines for FIBER (88E1011S only) */
cd28ab6a
SH		 391 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
392
393 /* Set Flow-control capabilities */
394 if (sky2->tx_pause && sky2->rx_pause)
793b883e 395 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 396 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 397 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 398 else if (!sky2->rx_pause && sky2->tx_pause)
399 adv |= PHY_AN_PAUSE_ASYM; /* local */
400
401 /* Restart Auto-negotiation */
402 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
403 } else {
404 /* forced speed/duplex settings */
405 ct1000 = PHY_M_1000C_MSE;
406
407 if (sky2->duplex == DUPLEX_FULL)
408 ctrl |= PHY_CT_DUP_MD;
409
410 switch (sky2->speed) {
411 case SPEED_1000:
412 ctrl |= PHY_CT_SP1000;
413 break;
414 case SPEED_100:
415 ctrl |= PHY_CT_SP100;
416 break;
417 }
418
419 ctrl |= PHY_CT_RESET;
420 }
421
422 if (hw->chip_id != CHIP_ID_YUKON_FE)
423 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
424
425 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
426 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
427
428 /* Setup Phy LED's */
429 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
430 ledover = 0;
431
432 switch (hw->chip_id) {
433 case CHIP_ID_YUKON_FE:
434 /* on 88E3082 these bits are at 11..9 (shifted left) */
435 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
436
437 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
438
439 /* delete ACT LED control bits */
440 ctrl &= ~PHY_M_FELP_LED1_MSK;
441 /* change ACT LED control to blink mode */
442 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
443 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
444 break;
445
446 case CHIP_ID_YUKON_XL:
793b883e 447 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 448
449 /* select page 3 to access LED control register */
450 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
451
452 /* set LED Function Control register */
ed6d32c7
SH		 453 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
454 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
455 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
456 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
457 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 458
459 /* set Polarity Control register */
460 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 461 (PHY_M_POLC_LS1_P_MIX(4) |
462 PHY_M_POLC_IS0_P_MIX(4) |
463 PHY_M_POLC_LOS_CTRL(2) |
464 PHY_M_POLC_INIT_CTRL(2) |
465 PHY_M_POLC_STA1_CTRL(2) |
466 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 467
468 /* restore page register */
793b883e 469 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 470 break;
ed6d32c7
SH		 471 case CHIP_ID_YUKON_EC_U:
472 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
473
474 /* select page 3 to access LED control register */
475 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
476
477 /* set LED Function Control register */
478 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
479 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
480 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
481 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
482 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
483
484 /* set Blink Rate in LED Timer Control Register */
485 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
486 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
487 /* restore page register */
488 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
489 break;
cd28ab6a
SH		 490
491 default:
492 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
493 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
494 /* turn off the Rx LED (LED_RX) */
495 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
496 }
497
ed6d32c7 498 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 499 /* apply fixes in PHY AFE */
ed6d32c7
SH		 500 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
501 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
502
977bdf06 503 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 504 gm_phy_write(hw, port, 0x18, 0xaa99);
505 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 506
977bdf06 507 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 508 gm_phy_write(hw, port, 0x18, 0xa204);
509 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 510
511 /* set page register to 0 */
ed6d32c7 512 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
977bdf06
SH		 513 } else {
514 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 515
977bdf06
SH		 516 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
517 /* turn on 100 Mbps LED (LED_LINK100) */
518 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
519 }
cd28ab6a 520
977bdf06
SH		 521 if (ledover)
522 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
523
524 }
d571b694 525 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 526 if (sky2->autoneg == AUTONEG_ENABLE)
527 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
528 else
529 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
530}
531
1b537565
SH		 532/* Force a renegotiation */
533static void sky2_phy_reinit(struct sky2_port *sky2)
534{
e07b1aa8 535 spin_lock_bh(&sky2->phy_lock);
1b537565 536 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 537 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 538}
539
cd28ab6a
SH		 540static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
541{
542 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
543 u16 reg;
544 int i;
545 const u8 *addr = hw->dev[port]->dev_addr;
546
42eeea01 547 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
548 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 549
550 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
551
793b883e 552 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 553 /* WA DEV_472 -- looks like crossed wires on port 2 */
554 /* clear GMAC 1 Control reset */
555 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
556 do {
557 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
558 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
559 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
560 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
561 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
562 }
563
cd28ab6a
SH		 564 if (sky2->autoneg == AUTONEG_DISABLE) {
565 reg = gma_read16(hw, port, GM_GP_CTRL);
566 reg |= GM_GPCR_AU_ALL_DIS;
567 gma_write16(hw, port, GM_GP_CTRL, reg);
568 gma_read16(hw, port, GM_GP_CTRL);
569
cd28ab6a
SH		 570 switch (sky2->speed) {
571 case SPEED_1000:
6f4c56b2 572 reg &= ~GM_GPCR_SPEED_100;
cd28ab6a 573 reg |= GM_GPCR_SPEED_1000;
6f4c56b2 574 break;
cd28ab6a 575 case SPEED_100:
6f4c56b2 576 reg &= ~GM_GPCR_SPEED_1000;
cd28ab6a 577 reg |= GM_GPCR_SPEED_100;
6f4c56b2
SH		 578 break;
579 case SPEED_10:
580 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
581 break;
cd28ab6a
SH		 582 }
583
584 if (sky2->duplex == DUPLEX_FULL)
585 reg |= GM_GPCR_DUP_FULL;
ed6d32c7
SH		 586
587 /* turn off pause in 10/100mbps half duplex */
588 else if (sky2->speed != SPEED_1000 &&
589 hw->chip_id != CHIP_ID_YUKON_EC_U)
590 sky2->tx_pause = sky2->rx_pause = 0;
cd28ab6a
SH		 591 } else
592 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
593
594 if (!sky2->tx_pause && !sky2->rx_pause) {
595 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e
SH		 596 reg |=
597 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
598 } else if (sky2->tx_pause && !sky2->rx_pause) {
cd28ab6a
SH		 599 /* disable Rx flow-control */
600 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
601 }
602
603 gma_write16(hw, port, GM_GP_CTRL, reg);
604
793b883e 605 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 606
e07b1aa8 607 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 608 sky2_phy_init(hw, port);
e07b1aa8 609 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 610
611 /* MIB clear */
612 reg = gma_read16(hw, port, GM_PHY_ADDR);
613 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
614
43f2f104
SH		 615 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
616 gma_read16(hw, port, i);
cd28ab6a
SH		 617 gma_write16(hw, port, GM_PHY_ADDR, reg);
618
619 /* transmit control */
620 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
621
622 /* receive control reg: unicast + multicast + no FCS */
623 gma_write16(hw, port, GM_RX_CTRL,
793b883e 624 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 625
626 /* transmit flow control */
627 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
628
629 /* transmit parameter */
630 gma_write16(hw, port, GM_TX_PARAM,
631 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
632 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
633 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
634 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
635
636 /* serial mode register */
637 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 638 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 639
6b1a3aef 640 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 641 reg |= GM_SMOD_JUMBO_ENA;
642
643 gma_write16(hw, port, GM_SERIAL_MODE, reg);
644
cd28ab6a
SH		 645 /* virtual address for data */
646 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
647
793b883e
SH		 648 /* physical address: used for pause frames */
649 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
650
651 /* ignore counter overflows */
cd28ab6a
SH		 652 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
653 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
654 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
655
656 /* Configure Rx MAC FIFO */
657 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 658 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
659 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 660
d571b694 661 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 662 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 663
793b883e
SH		 664 /* Set threshold to 0xa (64 bytes)
665 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 666 */
667 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
668
669 /* Configure Tx MAC FIFO */
670 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
671 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 672
673 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
674 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
675 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
676 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
677 /* set Tx GMAC FIFO Almost Empty Threshold */
678 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
679 /* Disable Store & Forward mode for TX */
680 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
681 }
682 }
683
cd28ab6a
SH		 684}
685
1c28f6ba
SH		 686/* Assign Ram Buffer allocation.
687 * start and end are in units of 4k bytes
688 * ram registers are in units of 64bit words
689 */
690static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
cd28ab6a 691{
1c28f6ba 692 u32 start, end;
cd28ab6a 693
1c28f6ba
SH		 694 start = startk * 4096/8;
695 end = (endk * 4096/8) - 1;
793b883e 696
cd28ab6a
SH		 697 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
698 sky2_write32(hw, RB_ADDR(q, RB_START), start);
699 sky2_write32(hw, RB_ADDR(q, RB_END), end);
700 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
701 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
702
703 if (q == Q_R1 || q == Q_R2) {
1c28f6ba
SH		 704 u32 space = (endk - startk) * 4096/8;
705 u32 tp = space - space/4;
793b883e 706
1c28f6ba
SH		 707 /* On receive queue's set the thresholds
708 * give receiver priority when > 3/4 full
709 * send pause when down to 2K
710 */
711 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
712 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 713
1c28f6ba
SH		 714 tp = space - 2048/8;
715 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
716 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 717 } else {
718 /* Enable store & forward on Tx queue's because
719 * Tx FIFO is only 1K on Yukon
720 */
721 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
722 }
723
724 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 725 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 726}
727
cd28ab6a 728/* Setup Bus Memory Interface */
af4ed7e6 729static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 730{
731 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
732 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
733 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 734 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 735}
736
cd28ab6a
SH		 737/* Setup prefetch unit registers. This is the interface between
738 * hardware and driver list elements
739 */
8cc048e3 740static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 741 u64 addr, u32 last)
742{
cd28ab6a
SH		 743 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
744 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
745 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
746 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
747 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
748 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 749
750 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 751}
752
793b883e
SH		 753static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
754{
755 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
756
cb5d9547 757 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
793b883e
SH		 758 return le;
759}
cd28ab6a 760
290d4de5
SH		 761/* Update chip's next pointer */
762static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 763{
762c2de2 764 wmb();
290d4de5 765 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
762c2de2 766 mmiowb();
cd28ab6a
SH		 767}
768
793b883e 769
cd28ab6a
SH		 770static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
771{
772 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 773 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
cd28ab6a
SH		 774 return le;
775}
776
a018e330 777/* Return high part of DMA address (could be 32 or 64 bit) */
778static inline u32 high32(dma_addr_t a)
779{
a036119f 780 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330 781}
782
793b883e 783/* Build description to hardware about buffer */
28bd181a 784static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
cd28ab6a
SH		 785{
786 struct sky2_rx_le *le;
734d1868
SH		 787 u32 hi = high32(map);
788 u16 len = sky2->rx_bufsize;
cd28ab6a 789
793b883e 790 if (sky2->rx_addr64 != hi) {
cd28ab6a 791 le = sky2_next_rx(sky2);
793b883e 792 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 793 le->ctrl = 0;
794 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 795 sky2->rx_addr64 = high32(map + len);
cd28ab6a 796 }
793b883e 797
cd28ab6a 798 le = sky2_next_rx(sky2);
734d1868
SH		 799 le->addr = cpu_to_le32((u32) map);
800 le->length = cpu_to_le16(len);
cd28ab6a
SH		 801 le->ctrl = 0;
802 le->opcode = OP_PACKET | HW_OWNER;
803}
804
793b883e 805
cd28ab6a
SH		 806/* Tell chip where to start receive checksum.
807 * Actually has two checksums, but set both same to avoid possible byte
808 * order problems.
809 */
793b883e 810static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 811{
812 struct sky2_rx_le *le;
813
cd28ab6a 814 le = sky2_next_rx(sky2);
793b883e 815 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
cd28ab6a
SH		 816 le->ctrl = 0;
817 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 818
793b883e
SH		 819 sky2_write32(sky2->hw,
820 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
821 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 822
823}
824
6b1a3aef 825/*
826 * The RX Stop command will not work for Yukon-2 if the BMU does not
827 * reach the end of packet and since we can't make sure that we have
828 * incoming data, we must reset the BMU while it is not doing a DMA
829 * transfer. Since it is possible that the RX path is still active,
830 * the RX RAM buffer will be stopped first, so any possible incoming
831 * data will not trigger a DMA. After the RAM buffer is stopped, the
832 * BMU is polled until any DMA in progress is ended and only then it
833 * will be reset.
834 */
835static void sky2_rx_stop(struct sky2_port *sky2)
836{
837 struct sky2_hw *hw = sky2->hw;
838 unsigned rxq = rxqaddr[sky2->port];
839 int i;
840
841 /* disable the RAM Buffer receive queue */
842 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
843
844 for (i = 0; i < 0xffff; i++)
845 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
846 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
847 goto stopped;
848
849 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
850 sky2->netdev->name);
851stopped:
852 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
853
854 /* reset the Rx prefetch unit */
855 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
856}
793b883e 857
d571b694 858/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 859static void sky2_rx_clean(struct sky2_port *sky2)
860{
861 unsigned i;
862
863 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 864 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 865 struct ring_info *re = sky2->rx_ring + i;
866
867 if (re->skb) {
793b883e 868 pci_unmap_single(sky2->hw->pdev,
734d1868 869 re->mapaddr, sky2->rx_bufsize,
cd28ab6a
SH		 870 PCI_DMA_FROMDEVICE);
871 kfree_skb(re->skb);
872 re->skb = NULL;
873 }
874 }
875}
876
ef743d33 877/* Basic MII support */
878static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
879{
880 struct mii_ioctl_data *data = if_mii(ifr);
881 struct sky2_port *sky2 = netdev_priv(dev);
882 struct sky2_hw *hw = sky2->hw;
883 int err = -EOPNOTSUPP;
884
885 if (!netif_running(dev))
886 return -ENODEV; /* Phy still in reset */
887
d89e1343 888 switch (cmd) {
ef743d33 889 case SIOCGMIIPHY:
890 data->phy_id = PHY_ADDR_MARV;
891
892 /* fallthru */
893 case SIOCGMIIREG: {
894 u16 val = 0;
91c86df5 895
e07b1aa8 896 spin_lock_bh(&sky2->phy_lock);
ef743d33 897 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 898 spin_unlock_bh(&sky2->phy_lock);
91c86df5 899
ef743d33 900 data->val_out = val;
901 break;
902 }
903
904 case SIOCSMIIREG:
905 if (!capable(CAP_NET_ADMIN))
906 return -EPERM;
907
e07b1aa8 908 spin_lock_bh(&sky2->phy_lock);
ef743d33 909 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
910 data->val_in);
e07b1aa8 911 spin_unlock_bh(&sky2->phy_lock);
ef743d33 912 break;
913 }
914 return err;
915}
916
d1f13708 917#ifdef SKY2_VLAN_TAG_USED
918static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
919{
920 struct sky2_port *sky2 = netdev_priv(dev);
921 struct sky2_hw *hw = sky2->hw;
922 u16 port = sky2->port;
d1f13708 923
302d1252 924 spin_lock_bh(&sky2->tx_lock);
d1f13708 925
926 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
927 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
928 sky2->vlgrp = grp;
929
302d1252 930 spin_unlock_bh(&sky2->tx_lock);
d1f13708 931}
932
933static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
934{
935 struct sky2_port *sky2 = netdev_priv(dev);
936 struct sky2_hw *hw = sky2->hw;
937 u16 port = sky2->port;
d1f13708 938
302d1252 939 spin_lock_bh(&sky2->tx_lock);
d1f13708 940
941 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
942 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
943 if (sky2->vlgrp)
944 sky2->vlgrp->vlan_devices[vid] = NULL;
945
302d1252 946 spin_unlock_bh(&sky2->tx_lock);
d1f13708 947}
948#endif
949
82788c7a
SH		 950/*
951 * It appears the hardware has a bug in the FIFO logic that
952 * cause it to hang if the FIFO gets overrun and the receive buffer
953 * is not aligned. ALso alloc_skb() won't align properly if slab
954 * debugging is enabled.
955 */
956static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
957{
958 struct sk_buff *skb;
959
960 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
961 if (likely(skb)) {
962 unsigned long p = (unsigned long) skb->data;
4a15d56f 963 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
82788c7a
SH		 964 }
965
966 return skb;
967}
968
cd28ab6a
SH		 969/*
970 * Allocate and setup receiver buffer pool.
971 * In case of 64 bit dma, there are 2X as many list elements
972 * available as ring entries
973 * and need to reserve one list element so we don't wrap around.
974 */
6b1a3aef 975static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 976{
6b1a3aef 977 struct sky2_hw *hw = sky2->hw;
6b1a3aef 978 unsigned rxq = rxqaddr[sky2->port];
979 int i;
cd28ab6a 980
6b1a3aef 981 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 982 sky2_qset(hw, rxq);
977bdf06
SH		 983
984 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
985 /* MAC Rx RAM Read is controlled by hardware */
986 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
987 }
988
6b1a3aef 989 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
990
991 rx_set_checksum(sky2);
793b883e 992 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 993 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 994
82788c7a 995 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
cd28ab6a
SH		 996 if (!re->skb)
997 goto nomem;
998
6b1a3aef 999 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
734d1868
SH		 1000 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1001 sky2_rx_add(sky2, re->mapaddr);
cd28ab6a
SH		 1002 }
1003
70f1be48
SH		 1004 /* Truncate oversize frames */
1005 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8);
1006 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1007
6b1a3aef 1008 /* Tell chip about available buffers */
1009 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1010 return 0;
1011nomem:
1012 sky2_rx_clean(sky2);
1013 return -ENOMEM;
1014}
1015
1016/* Bring up network interface. */
1017static int sky2_up(struct net_device *dev)
1018{
1019 struct sky2_port *sky2 = netdev_priv(dev);
1020 struct sky2_hw *hw = sky2->hw;
1021 unsigned port = sky2->port;
e07b1aa8 1022 u32 ramsize, rxspace, imask;
cd28ab6a
SH		 1023 int err = -ENOMEM;
1024
1025 if (netif_msg_ifup(sky2))
1026 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1027
1028 /* must be power of 2 */
1029 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1030 TX_RING_SIZE *
1031 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1032 &sky2->tx_le_map);
1033 if (!sky2->tx_le)
1034 goto err_out;
1035
6cdbbdf3 1036 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1037 GFP_KERNEL);
1038 if (!sky2->tx_ring)
1039 goto err_out;
1040 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1041
1042 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1043 &sky2->rx_le_map);
1044 if (!sky2->rx_le)
1045 goto err_out;
1046 memset(sky2->rx_le, 0, RX_LE_BYTES);
1047
6cdbbdf3 1048 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
cd28ab6a
SH		 1049 GFP_KERNEL);
1050 if (!sky2->rx_ring)
1051 goto err_out;
1052
1053 sky2_mac_init(hw, port);
1054
1c28f6ba
SH		 1055 /* Determine available ram buffer space (in 4K blocks).
1056 * Note: not sure about the FE setting below yet
1057 */
1058 if (hw->chip_id == CHIP_ID_YUKON_FE)
1059 ramsize = 4;
1060 else
1061 ramsize = sky2_read8(hw, B2_E_0);
1062
1063 /* Give transmitter one third (rounded up) */
1064 rxspace = ramsize - (ramsize + 2) / 3;
cd28ab6a 1065
cd28ab6a 1066 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1c28f6ba 1067 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
cd28ab6a 1068
793b883e
SH		 1069 /* Make sure SyncQ is disabled */
1070 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1071 RB_RST_SET);
1072
af4ed7e6 1073 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1074
977bdf06
SH		 1075 /* Set almost empty threshold */
1076 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1077 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1078
6b1a3aef 1079 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1080 TX_RING_SIZE - 1);
cd28ab6a 1081
6b1a3aef 1082 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1083 if (err)
1084 goto err_out;
1085
cd28ab6a 1086 /* Enable interrupts from phy/mac for port */
e07b1aa8 1087 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1088 imask |= portirq_msk[port];
e07b1aa8
SH		 1089 sky2_write32(hw, B0_IMSK, imask);
1090
cd28ab6a
SH		 1091 return 0;
1092
1093err_out:
1b537565 1094 if (sky2->rx_le) {
cd28ab6a
SH		 1095 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1096 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1097 sky2->rx_le = NULL;
1098 }
1099 if (sky2->tx_le) {
cd28ab6a
SH		 1100 pci_free_consistent(hw->pdev,
1101 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1102 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1103 sky2->tx_le = NULL;
1104 }
1105 kfree(sky2->tx_ring);
1106 kfree(sky2->rx_ring);
cd28ab6a 1107
1b537565
SH		 1108 sky2->tx_ring = NULL;
1109 sky2->rx_ring = NULL;
cd28ab6a
SH		 1110 return err;
1111}
1112
793b883e
SH		 1113/* Modular subtraction in ring */
1114static inline int tx_dist(unsigned tail, unsigned head)
1115{
cb5d9547 1116 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1117}
cd28ab6a 1118
793b883e
SH		 1119/* Number of list elements available for next tx */
1120static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1121{
793b883e 1122 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1123}
1124
793b883e 1125/* Estimate of number of transmit list elements required */
28bd181a 1126static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1127{
793b883e
SH		 1128 unsigned count;
1129
1130 count = sizeof(dma_addr_t) / sizeof(u32);
1131 count += skb_shinfo(skb)->nr_frags * count;
1132
1133 if (skb_shinfo(skb)->tso_size)
1134 ++count;
1135
0e3ff6aa 1136 if (skb->ip_summed == CHECKSUM_HW)
793b883e
SH		 1137 ++count;
1138
1139 return count;
cd28ab6a
SH		 1140}
1141
793b883e
SH		 1142/*
1143 * Put one packet in ring for transmit.
1144 * A single packet can generate multiple list elements, and
1145 * the number of ring elements will probably be less than the number
1146 * of list elements used.
f2e46561
SH		 1147 *
1148 * No BH disabling for tx_lock here (like tg3)
793b883e 1149 */
cd28ab6a
SH		 1150static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1151{
1152 struct sky2_port *sky2 = netdev_priv(dev);
1153 struct sky2_hw *hw = sky2->hw;
d1f13708 1154 struct sky2_tx_le *le = NULL;
6cdbbdf3 1155 struct tx_ring_info *re;
cd28ab6a 1156 unsigned i, len;
b19666d9 1157 int avail;
cd28ab6a
SH		 1158 dma_addr_t mapping;
1159 u32 addr64;
1160 u16 mss;
1161 u8 ctrl;
1162
302d1252
SH		 1163 /* No BH disabling for tx_lock here. We are running in BH disabled
1164 * context and TX reclaim runs via poll inside of a software
1165 * interrupt, and no related locks in IRQ processing.
1166 */
f2e46561 1167 if (!spin_trylock(&sky2->tx_lock))
cd28ab6a
SH		 1168 return NETDEV_TX_LOCKED;
1169
793b883e 1170 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
8c463ef7
SH		 1171 /* There is a known but harmless race with lockless tx
1172 * and netif_stop_queue.
1173 */
1174 if (!netif_queue_stopped(dev)) {
1175 netif_stop_queue(dev);
3be92a70
SH		 1176 if (net_ratelimit())
1177 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1178 dev->name);
8c463ef7 1179 }
f2e46561 1180 spin_unlock(&sky2->tx_lock);
cd28ab6a 1181
cd28ab6a
SH		 1182 return NETDEV_TX_BUSY;
1183 }
1184
793b883e 1185 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1186 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1187 dev->name, sky2->tx_prod, skb->len);
1188
cd28ab6a
SH		 1189 len = skb_headlen(skb);
1190 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1191 addr64 = high32(mapping);
793b883e
SH		 1192
1193 re = sky2->tx_ring + sky2->tx_prod;
1194
a018e330 1195 /* Send high bits if changed or crosses boundary */
1196 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e
SH		 1197 le = get_tx_le(sky2);
1198 le->tx.addr = cpu_to_le32(addr64);
1199 le->ctrl = 0;
1200 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1201 sky2->tx_addr64 = high32(mapping + len);
793b883e 1202 }
cd28ab6a
SH		 1203
1204 /* Check for TCP Segmentation Offload */
1205 mss = skb_shinfo(skb)->tso_size;
793b883e 1206 if (mss != 0) {
cd28ab6a
SH		 1207 /* just drop the packet if non-linear expansion fails */
1208 if (skb_header_cloned(skb) &&
1209 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
15240072 1210 dev_kfree_skb(skb);
793b883e 1211 goto out_unlock;
cd28ab6a
SH		 1212 }
1213
1214 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1215 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1216 mss += ETH_HLEN;
793b883e 1217 }
cd28ab6a 1218
793b883e 1219 if (mss != sky2->tx_last_mss) {
cd28ab6a
SH		 1220 le = get_tx_le(sky2);
1221 le->tx.tso.size = cpu_to_le16(mss);
793b883e 1222 le->tx.tso.rsvd = 0;
cd28ab6a 1223 le->opcode = OP_LRGLEN | HW_OWNER;
cd28ab6a 1224 le->ctrl = 0;
793b883e 1225 sky2->tx_last_mss = mss;
cd28ab6a
SH		 1226 }
1227
cd28ab6a 1228 ctrl = 0;
d1f13708 1229#ifdef SKY2_VLAN_TAG_USED
1230 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1231 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1232 if (!le) {
1233 le = get_tx_le(sky2);
1234 le->tx.addr = 0;
1235 le->opcode = OP_VLAN|HW_OWNER;
1236 le->ctrl = 0;
1237 } else
1238 le->opcode |= OP_VLAN;
1239 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1240 ctrl |= INS_VLAN;
1241 }
1242#endif
1243
1244 /* Handle TCP checksum offload */
cd28ab6a 1245 if (skb->ip_summed == CHECKSUM_HW) {
793b883e
SH		 1246 u16 hdr = skb->h.raw - skb->data;
1247 u16 offset = hdr + skb->csum;
cd28ab6a
SH		 1248
1249 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1250 if (skb->nh.iph->protocol == IPPROTO_UDP)
1251 ctrl |= UDPTCP;
1252
1253 le = get_tx_le(sky2);
1254 le->tx.csum.start = cpu_to_le16(hdr);
793b883e
SH		 1255 le->tx.csum.offset = cpu_to_le16(offset);
1256 le->length = 0; /* initial checksum value */
cd28ab6a 1257 le->ctrl = 1; /* one packet */
793b883e 1258 le->opcode = OP_TCPLISW | HW_OWNER;
cd28ab6a
SH		 1259 }
1260
1261 le = get_tx_le(sky2);
1262 le->tx.addr = cpu_to_le32((u32) mapping);
1263 le->length = cpu_to_le16(len);
1264 le->ctrl = ctrl;
793b883e 1265 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1266
793b883e 1267 /* Record the transmit mapping info */
cd28ab6a 1268 re->skb = skb;
6cdbbdf3 1269 pci_unmap_addr_set(re, mapaddr, mapping);
cd28ab6a
SH		 1270
1271 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1272 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6cdbbdf3 1273 struct tx_ring_info *fre;
cd28ab6a
SH		 1274
1275 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1276 frag->size, PCI_DMA_TODEVICE);
a036119f 1277 addr64 = high32(mapping);
793b883e
SH		 1278 if (addr64 != sky2->tx_addr64) {
1279 le = get_tx_le(sky2);
1280 le->tx.addr = cpu_to_le32(addr64);
1281 le->ctrl = 0;
1282 le->opcode = OP_ADDR64 | HW_OWNER;
1283 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1284 }
1285
1286 le = get_tx_le(sky2);
1287 le->tx.addr = cpu_to_le32((u32) mapping);
1288 le->length = cpu_to_le16(frag->size);
1289 le->ctrl = ctrl;
793b883e 1290 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1291
793b883e 1292 fre = sky2->tx_ring
cb5d9547 1293 + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
6cdbbdf3 1294 pci_unmap_addr_set(fre, mapaddr, mapping);
cd28ab6a 1295 }
6cdbbdf3 1296
793b883e 1297 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1298 le->ctrl |= EOP;
1299
b19666d9
SH		 1300 avail = tx_avail(sky2);
1301 if (mss != 0 || avail < TX_MIN_PENDING) {
1302 le->ctrl |= FRC_STAT;
1303 if (avail <= MAX_SKB_TX_LE)
1304 netif_stop_queue(dev);
1305 }
1306
290d4de5 1307 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1308
793b883e 1309out_unlock:
f2e46561 1310 spin_unlock(&sky2->tx_lock);
cd28ab6a
SH		 1311
1312 dev->trans_start = jiffies;
1313 return NETDEV_TX_OK;
1314}
1315
cd28ab6a 1316/*
793b883e
SH		 1317 * Free ring elements from starting at tx_cons until "done"
1318 *
1319 * NB: the hardware will tell us about partial completion of multi-part
d571b694 1320 * buffers; these are deferred until completion.
cd28ab6a 1321 */
d11c13e7 1322static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1323{
d11c13e7 1324 struct net_device *dev = sky2->netdev;
af2a58ac
SH		 1325 struct pci_dev *pdev = sky2->hw->pdev;
1326 u16 nxt, put;
793b883e 1327 unsigned i;
cd28ab6a 1328
0e3ff6aa 1329 BUG_ON(done >= TX_RING_SIZE);
2224795d 1330
d11c13e7 1331 if (unlikely(netif_msg_tx_done(sky2)))
d571b694 1332 printk(KERN_DEBUG "%s: tx done, up to %u\n",
d11c13e7 1333 dev->name, done);
cd28ab6a 1334
af2a58ac
SH		 1335 for (put = sky2->tx_cons; put != done; put = nxt) {
1336 struct tx_ring_info *re = sky2->tx_ring + put;
1337 struct sk_buff *skb = re->skb;
cd28ab6a 1338
d89e1343 1339 nxt = re->idx;
af2a58ac 1340 BUG_ON(nxt >= TX_RING_SIZE);
d70cd51a 1341 prefetch(sky2->tx_ring + nxt);
cd28ab6a 1342
793b883e 1343 /* Check for partial status */
af2a58ac
SH		 1344 if (tx_dist(put, done) < tx_dist(put, nxt))
1345 break;
793b883e
SH		 1346
1347 skb = re->skb;
af2a58ac 1348 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
734d1868 1349 skb_headlen(skb), PCI_DMA_TODEVICE);
793b883e
SH		 1350
1351 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6cdbbdf3 1352 struct tx_ring_info *fre;
cb5d9547 1353 fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
af2a58ac 1354 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
d89e1343 1355 skb_shinfo(skb)->frags[i].size,
734d1868 1356 PCI_DMA_TODEVICE);
cd28ab6a
SH		 1357 }
1358
15240072 1359 dev_kfree_skb(skb);
793b883e 1360 }
793b883e 1361
af2a58ac 1362 sky2->tx_cons = put;
8f24664d 1363 if (tx_avail(sky2) > MAX_SKB_TX_LE)
cd28ab6a 1364 netif_wake_queue(dev);
cd28ab6a
SH		 1365}
1366
1367/* Cleanup all untransmitted buffers, assume transmitter not running */
13b97b74 1368static void sky2_tx_clean(struct sky2_port *sky2)
cd28ab6a 1369{
302d1252 1370 spin_lock_bh(&sky2->tx_lock);
d11c13e7 1371 sky2_tx_complete(sky2, sky2->tx_prod);
302d1252 1372 spin_unlock_bh(&sky2->tx_lock);
cd28ab6a
SH		 1373}
1374
1375/* Network shutdown */
1376static int sky2_down(struct net_device *dev)
1377{
1378 struct sky2_port *sky2 = netdev_priv(dev);
1379 struct sky2_hw *hw = sky2->hw;
1380 unsigned port = sky2->port;
1381 u16 ctrl;
e07b1aa8 1382 u32 imask;
cd28ab6a 1383
1b537565
SH		 1384 /* Never really got started! */
1385 if (!sky2->tx_le)
1386 return 0;
1387
cd28ab6a
SH		 1388 if (netif_msg_ifdown(sky2))
1389 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1390
018d1c66 1391 /* Stop more packets from being queued */
cd28ab6a
SH		 1392 netif_stop_queue(dev);
1393
793b883e
SH		 1394 sky2_phy_reset(hw, port);
1395
cd28ab6a
SH		 1396 /* Stop transmitter */
1397 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1398 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1399
1400 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1401 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1402
1403 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1404 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1405 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1406
1407 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1408
1409 /* Workaround shared GMAC reset */
793b883e
SH		 1410 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1411 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1412 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1413
1414 /* Disable Force Sync bit and Enable Alloc bit */
1415 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1416 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1417
1418 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1419 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1420 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1421
1422 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1423 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1424 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1425
1426 /* Reset the Tx prefetch units */
1427 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1428 PREF_UNIT_RST_SET);
1429
1430 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1431
6b1a3aef 1432 sky2_rx_stop(sky2);
cd28ab6a
SH		 1433
1434 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1435 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1436
e07b1aa8
SH		 1437 /* Disable port IRQ */
1438 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1439 imask &= ~portirq_msk[port];
e07b1aa8
SH		 1440 sky2_write32(hw, B0_IMSK, imask);
1441
d571b694 1442 /* turn off LED's */
cd28ab6a
SH		 1443 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1444
018d1c66 1445 synchronize_irq(hw->pdev->irq);
1446
cd28ab6a
SH		 1447 sky2_tx_clean(sky2);
1448 sky2_rx_clean(sky2);
1449
1450 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1451 sky2->rx_le, sky2->rx_le_map);
1452 kfree(sky2->rx_ring);
1453
1454 pci_free_consistent(hw->pdev,
1455 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1456 sky2->tx_le, sky2->tx_le_map);
1457 kfree(sky2->tx_ring);
1458
1b537565
SH		 1459 sky2->tx_le = NULL;
1460 sky2->rx_le = NULL;
1461
1462 sky2->rx_ring = NULL;
1463 sky2->tx_ring = NULL;
1464
cd28ab6a
SH		 1465 return 0;
1466}
1467
1468static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1469{
793b883e
SH		 1470 if (!hw->copper)
1471 return SPEED_1000;
1472
cd28ab6a
SH		 1473 if (hw->chip_id == CHIP_ID_YUKON_FE)
1474 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1475
1476 switch (aux & PHY_M_PS_SPEED_MSK) {
1477 case PHY_M_PS_SPEED_1000:
1478 return SPEED_1000;
1479 case PHY_M_PS_SPEED_100:
1480 return SPEED_100;
1481 default:
1482 return SPEED_10;
1483 }
1484}
1485
1486static void sky2_link_up(struct sky2_port *sky2)
1487{
1488 struct sky2_hw *hw = sky2->hw;
1489 unsigned port = sky2->port;
1490 u16 reg;
1491
1492 /* Enable Transmit FIFO Underrun */
793b883e 1493 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
cd28ab6a
SH		 1494
1495 reg = gma_read16(hw, port, GM_GP_CTRL);
6f4c56b2
SH		 1496 if (sky2->autoneg == AUTONEG_DISABLE) {
1497 reg |= GM_GPCR_AU_ALL_DIS;
1498
1499 /* Is write/read necessary? Copied from sky2_mac_init */
1500 gma_write16(hw, port, GM_GP_CTRL, reg);
1501 gma_read16(hw, port, GM_GP_CTRL);
1502
1503 switch (sky2->speed) {
1504 case SPEED_1000:
1505 reg &= ~GM_GPCR_SPEED_100;
1506 reg |= GM_GPCR_SPEED_1000;
1507 break;
1508 case SPEED_100:
1509 reg &= ~GM_GPCR_SPEED_1000;
1510 reg |= GM_GPCR_SPEED_100;
1511 break;
1512 case SPEED_10:
1513 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1514 break;
1515 }
1516 } else
1517 reg &= ~GM_GPCR_AU_ALL_DIS;
1518
cd28ab6a
SH		 1519 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1520 reg |= GM_GPCR_DUP_FULL;
1521
cd28ab6a
SH		 1522 /* enable Rx/Tx */
1523 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1524 gma_write16(hw, port, GM_GP_CTRL, reg);
1525 gma_read16(hw, port, GM_GP_CTRL);
1526
1527 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1528
1529 netif_carrier_on(sky2->netdev);
1530 netif_wake_queue(sky2->netdev);
1531
1532 /* Turn on link LED */
793b883e 1533 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1534 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1535
ed6d32c7 1536 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
793b883e 1537 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1538 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1539
1540 switch(sky2->speed) {
1541 case SPEED_10:
1542 led |= PHY_M_LEDC_INIT_CTRL(7);
1543 break;
1544
1545 case SPEED_100:
1546 led |= PHY_M_LEDC_STA1_CTRL(7);
1547 break;
1548
1549 case SPEED_1000:
1550 led |= PHY_M_LEDC_STA0_CTRL(7);
1551 break;
1552 }
793b883e
SH		 1553
1554 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1555 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1556 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1557 }
1558
cd28ab6a
SH		 1559 if (netif_msg_link(sky2))
1560 printk(KERN_INFO PFX
d571b694 1561 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1562 sky2->netdev->name, sky2->speed,
1563 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1564 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1565 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1566}
1567
1568static void sky2_link_down(struct sky2_port *sky2)
1569{
1570 struct sky2_hw *hw = sky2->hw;
1571 unsigned port = sky2->port;
1572 u16 reg;
1573
1574 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1575
1576 reg = gma_read16(hw, port, GM_GP_CTRL);
1577 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1578 gma_write16(hw, port, GM_GP_CTRL, reg);
1579 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1580
1581 if (sky2->rx_pause && !sky2->tx_pause) {
1582 /* restore Asymmetric Pause bit */
1583 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1584 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1585 | PHY_M_AN_ASP);
cd28ab6a
SH		 1586 }
1587
cd28ab6a
SH		 1588 netif_carrier_off(sky2->netdev);
1589 netif_stop_queue(sky2->netdev);
1590
1591 /* Turn on link LED */
1592 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1593
1594 if (netif_msg_link(sky2))
1595 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1596 sky2_phy_init(hw, port);
1597}
1598
793b883e
SH		 1599static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1600{
1601 struct sky2_hw *hw = sky2->hw;
1602 unsigned port = sky2->port;
1603 u16 lpa;
1604
1605 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1606
1607 if (lpa & PHY_M_AN_RF) {
1608 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1609 return -1;
1610 }
1611
1612 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1613 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1614 printk(KERN_ERR PFX "%s: master/slave fault",
1615 sky2->netdev->name);
1616 return -1;
1617 }
1618
1619 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1620 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1621 sky2->netdev->name);
1622 return -1;
1623 }
1624
1625 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1626
1627 sky2->speed = sky2_phy_speed(hw, aux);
1628
1629 /* Pause bits are offset (9..8) */
ed6d32c7 1630 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
793b883e
SH		 1631 aux >>= 6;
1632
1633 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1634 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1635
1636 if ((sky2->tx_pause || sky2->rx_pause)
1637 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1638 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1639 else
1640 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1641
1642 return 0;
1643}
cd28ab6a 1644
e07b1aa8
SH		 1645/* Interrupt from PHY */
1646static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1647{
e07b1aa8
SH		 1648 struct net_device *dev = hw->dev[port];
1649 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1650 u16 istatus, phystat;
1651
e07b1aa8
SH		 1652 spin_lock(&sky2->phy_lock);
1653 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1654 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1655
1656 if (!netif_running(dev))
1657 goto out;
cd28ab6a
SH		 1658
1659 if (netif_msg_intr(sky2))
1660 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1661 sky2->netdev->name, istatus, phystat);
1662
1663 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 1664 if (sky2_autoneg_done(sky2, phystat) == 0)
1665 sky2_link_up(sky2);
1666 goto out;
1667 }
cd28ab6a 1668
793b883e
SH		 1669 if (istatus & PHY_M_IS_LSP_CHANGE)
1670 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1671
793b883e
SH		 1672 if (istatus & PHY_M_IS_DUP_CHANGE)
1673 sky2->duplex =
1674 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1675
793b883e
SH		 1676 if (istatus & PHY_M_IS_LST_CHANGE) {
1677 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1678 sky2_link_up(sky2);
793b883e
SH		 1679 else
1680 sky2_link_down(sky2);
cd28ab6a 1681 }
793b883e 1682out:
e07b1aa8 1683 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1684}
1685
302d1252
SH		 1686
1687/* Transmit timeout is only called if we are running, carries is up
1688 * and tx queue is full (stopped).
1689 */
cd28ab6a
SH		 1690static void sky2_tx_timeout(struct net_device *dev)
1691{
1692 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1693 struct sky2_hw *hw = sky2->hw;
1694 unsigned txq = txqaddr[sky2->port];
8f24664d 1695 u16 report, done;
cd28ab6a
SH		 1696
1697 if (netif_msg_timer(sky2))
1698 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1699
8f24664d
SH		 1700 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1701 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1702
8f24664d
SH		 1703 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1704 dev->name,
1705 sky2->tx_cons, sky2->tx_prod, report, done);
1706
1707 if (report != done) {
1708 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1709
1710 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1711 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1712 } else if (report != sky2->tx_cons) {
1713 printk(KERN_INFO PFX "status report lost?\n");
1714
1715 spin_lock_bh(&sky2->tx_lock);
1716 sky2_tx_complete(sky2, report);
1717 spin_unlock_bh(&sky2->tx_lock);
1718 } else {
1719 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1720
8f24664d
SH		 1721 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1722 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1723
1724 sky2_tx_clean(sky2);
1725
1726 sky2_qset(hw, txq);
1727 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1728 }
cd28ab6a
SH		 1729}
1730
734d1868 1731
70f1be48
SH		 1732/* Want receive buffer size to be multiple of 64 bits
1733 * and incl room for vlan and truncation
1734 */
734d1868
SH		 1735static inline unsigned sky2_buf_size(int mtu)
1736{
4a15d56f 1737 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
734d1868
SH		 1738}
1739
cd28ab6a
SH		 1740static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1741{
6b1a3aef 1742 struct sky2_port *sky2 = netdev_priv(dev);
1743 struct sky2_hw *hw = sky2->hw;
1744 int err;
1745 u16 ctl, mode;
e07b1aa8 1746 u32 imask;
cd28ab6a
SH		 1747
1748 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1749 return -EINVAL;
1750
5a5b1ea0 1751 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1752 return -EINVAL;
1753
6b1a3aef 1754 if (!netif_running(dev)) {
1755 dev->mtu = new_mtu;
1756 return 0;
1757 }
1758
e07b1aa8 1759 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 1760 sky2_write32(hw, B0_IMSK, 0);
1761
018d1c66 1762 dev->trans_start = jiffies; /* prevent tx timeout */
1763 netif_stop_queue(dev);
1764 netif_poll_disable(hw->dev[0]);
1765
e07b1aa8
SH		 1766 synchronize_irq(hw->pdev->irq);
1767
6b1a3aef 1768 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1769 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1770 sky2_rx_stop(sky2);
1771 sky2_rx_clean(sky2);
cd28ab6a
SH		 1772
1773 dev->mtu = new_mtu;
734d1868 1774 sky2->rx_bufsize = sky2_buf_size(new_mtu);
6b1a3aef 1775 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1776 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1777
1778 if (dev->mtu > ETH_DATA_LEN)
1779 mode |= GM_SMOD_JUMBO_ENA;
1780
1781 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1782
6b1a3aef 1783 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1784
6b1a3aef 1785 err = sky2_rx_start(sky2);
e07b1aa8 1786 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1787
1b537565
SH		 1788 if (err)
1789 dev_close(dev);
1790 else {
1791 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1792
1793 netif_poll_enable(hw->dev[0]);
1794 netif_wake_queue(dev);
1795 }
1796
cd28ab6a
SH		 1797 return err;
1798}
1799
1800/*
1801 * Receive one packet.
1802 * For small packets or errors, just reuse existing skb.
d571b694 1803 * For larger packets, get new buffer.
cd28ab6a 1804 */
d11c13e7 1805static struct sk_buff *sky2_receive(struct sky2_port *sky2,
cd28ab6a
SH		 1806 u16 length, u32 status)
1807{
cd28ab6a 1808 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1809 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1810
1811 if (unlikely(netif_msg_rx_status(sky2)))
1812 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
d11c13e7 1813 sky2->netdev->name, sky2->rx_next, status, length);
cd28ab6a 1814
793b883e 1815 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1816 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1817
42eeea01 1818 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1819 goto error;
1820
42eeea01 1821 if (!(status & GMR_FS_RX_OK))
1822 goto resubmit;
1823
70f1be48 1824 if (length > sky2->netdev->mtu + ETH_HLEN)
6e15b712
SH		 1825 goto oversize;
1826
bdb5c58e 1827 if (length < copybreak) {
79e57d32
SH		 1828 skb = alloc_skb(length + 2, GFP_ATOMIC);
1829 if (!skb)
793b883e
SH		 1830 goto resubmit;
1831
79e57d32 1832 skb_reserve(skb, 2);
793b883e
SH		 1833 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1834 length, PCI_DMA_FROMDEVICE);
79e57d32 1835 memcpy(skb->data, re->skb->data, length);
d11c13e7 1836 skb->ip_summed = re->skb->ip_summed;
1837 skb->csum = re->skb->csum;
793b883e
SH		 1838 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1839 length, PCI_DMA_FROMDEVICE);
793b883e 1840 } else {
79e57d32
SH		 1841 struct sk_buff *nskb;
1842
82788c7a 1843 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
793b883e
SH		 1844 if (!nskb)
1845 goto resubmit;
cd28ab6a 1846
793b883e 1847 skb = re->skb;
79e57d32 1848 re->skb = nskb;
793b883e 1849 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
734d1868 1850 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1851 prefetch(skb->data);
cd28ab6a 1852
793b883e 1853 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
734d1868 1854 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1855 }
cd28ab6a 1856
79e57d32 1857 skb_put(skb, length);
793b883e 1858resubmit:
d11c13e7 1859 re->skb->ip_summed = CHECKSUM_NONE;
734d1868 1860 sky2_rx_add(sky2, re->mapaddr);
79e57d32 1861
bea86103 1862 /* Tell receiver about new buffers. */
290d4de5 1863 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put);
bea86103 1864
cd28ab6a
SH		 1865 return skb;
1866
6e15b712
SH		 1867oversize:
1868 ++sky2->net_stats.rx_over_errors;
1869 goto resubmit;
1870
cd28ab6a 1871error:
6e15b712
SH		 1872 ++sky2->net_stats.rx_errors;
1873
3be92a70 1874 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a
SH		 1875 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1876 sky2->netdev->name, status, length);
793b883e
SH		 1877
1878 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1879 sky2->net_stats.rx_length_errors++;
1880 if (status & GMR_FS_FRAGMENT)
1881 sky2->net_stats.rx_frame_errors++;
1882 if (status & GMR_FS_CRC_ERR)
1883 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1884 if (status & GMR_FS_RX_FF_OV)
1885 sky2->net_stats.rx_fifo_errors++;
79e57d32 1886
793b883e 1887 goto resubmit;
cd28ab6a
SH		 1888}
1889
e07b1aa8
SH		 1890/* Transmit complete */
1891static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 1892{
e07b1aa8 1893 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 1894
e07b1aa8
SH		 1895 if (netif_running(dev)) {
1896 spin_lock(&sky2->tx_lock);
1897 sky2_tx_complete(sky2, last);
1898 spin_unlock(&sky2->tx_lock);
2224795d 1899 }
cd28ab6a
SH		 1900}
1901
e07b1aa8
SH		 1902/* Process status response ring */
1903static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 1904{
e07b1aa8 1905 int work_done = 0;
e71ebd73 1906 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 1907
af2a58ac 1908 rmb();
bea86103 1909
e71ebd73 1910 while (hw->st_idx != hwidx) {
13210ce5 1911 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1912 struct net_device *dev;
d11c13e7 1913 struct sky2_port *sky2;
cd28ab6a 1914 struct sk_buff *skb;
cd28ab6a
SH		 1915 u32 status;
1916 u16 length;
1917
cb5d9547 1918 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 1919
e71ebd73
SH		 1920 BUG_ON(le->link >= 2);
1921 dev = hw->dev[le->link];
13210ce5 1922
1923 sky2 = netdev_priv(dev);
e07b1aa8
SH		 1924 length = le->length;
1925 status = le->status;
cd28ab6a 1926
e71ebd73 1927 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 1928 case OP_RXSTAT:
d11c13e7 1929 skb = sky2_receive(sky2, length, status);
d1f13708 1930 if (!skb)
1931 break;
13210ce5 1932
1933 skb->dev = dev;
1934 skb->protocol = eth_type_trans(skb, dev);
1935 dev->last_rx = jiffies;
1936
d1f13708 1937#ifdef SKY2_VLAN_TAG_USED
1938 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1939 vlan_hwaccel_receive_skb(skb,
1940 sky2->vlgrp,
1941 be16_to_cpu(sky2->rx_tag));
1942 } else
1943#endif
cd28ab6a 1944 netif_receive_skb(skb);
13210ce5 1945
1946 if (++work_done >= to_do)
1947 goto exit_loop;
cd28ab6a
SH		 1948 break;
1949
d1f13708 1950#ifdef SKY2_VLAN_TAG_USED
1951 case OP_RXVLAN:
1952 sky2->rx_tag = length;
1953 break;
1954
1955 case OP_RXCHKSVLAN:
1956 sky2->rx_tag = length;
1957 /* fall through */
1958#endif
cd28ab6a 1959 case OP_RXCHKS:
d11c13e7 1960 skb = sky2->rx_ring[sky2->rx_next].skb;
1961 skb->ip_summed = CHECKSUM_HW;
1962 skb->csum = le16_to_cpu(status);
cd28ab6a
SH		 1963 break;
1964
1965 case OP_TXINDEXLE:
13b97b74 1966 /* TX index reports status for both ports */
f55925d7
SH		 1967 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
1968 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 1969 if (hw->dev[1])
1970 sky2_tx_done(hw->dev[1],
1971 ((status >> 24) & 0xff)
1972 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 1973 break;
1974
cd28ab6a
SH		 1975 default:
1976 if (net_ratelimit())
793b883e 1977 printk(KERN_WARNING PFX
e71ebd73
SH		 1978 "unknown status opcode 0x%x\n", le->opcode);
1979 goto exit_loop;
cd28ab6a 1980 }
13210ce5 1981 }
cd28ab6a 1982
13210ce5 1983exit_loop:
e07b1aa8 1984 return work_done;
cd28ab6a
SH		 1985}
1986
1987static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1988{
1989 struct net_device *dev = hw->dev[port];
1990
3be92a70
SH		 1991 if (net_ratelimit())
1992 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1993 dev->name, status);
cd28ab6a
SH		 1994
1995 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 1996 if (net_ratelimit())
1997 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1998 dev->name);
cd28ab6a
SH		 1999 /* Clear IRQ */
2000 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2001 }
2002
2003 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2004 if (net_ratelimit())
2005 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2006 dev->name);
cd28ab6a
SH		 2007
2008 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2009 }
2010
2011 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2012 if (net_ratelimit())
2013 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2014 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2015 }
2016
2017 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2018 if (net_ratelimit())
2019 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2020 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2021 }
2022
2023 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2024 if (net_ratelimit())
2025 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2026 dev->name);
cd28ab6a
SH		 2027 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2028 }
2029}
2030
2031static void sky2_hw_intr(struct sky2_hw *hw)
2032{
2033 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2034
793b883e 2035 if (status & Y2_IS_TIST_OV)
cd28ab6a 2036 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2037
2038 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2039 u16 pci_err;
2040
56a645cc 2041 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2042 if (net_ratelimit())
2043 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2044 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2045
2046 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2047 sky2_pci_write16(hw, PCI_STATUS,
793b883e 2048 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2049 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2050 }
2051
2052 if (status & Y2_IS_PCI_EXP) {
d571b694 2053 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2054 u32 pex_err;
2055
56a645cc 2056 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2057
3be92a70
SH		 2058 if (net_ratelimit())
2059 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2060 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2061
2062 /* clear the interrupt */
2063 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2064 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
793b883e 2065 0xffffffffUL);
cd28ab6a
SH		 2066 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2067
2068 if (pex_err & PEX_FATAL_ERRORS) {
2069 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2070 hwmsk &= ~Y2_IS_PCI_EXP;
2071 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2072 }
2073 }
2074
2075 if (status & Y2_HWE_L1_MASK)
2076 sky2_hw_error(hw, 0, status);
2077 status >>= 8;
2078 if (status & Y2_HWE_L1_MASK)
2079 sky2_hw_error(hw, 1, status);
2080}
2081
2082static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2083{
2084 struct net_device *dev = hw->dev[port];
2085 struct sky2_port *sky2 = netdev_priv(dev);
2086 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2087
2088 if (netif_msg_intr(sky2))
2089 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2090 dev->name, status);
2091
2092 if (status & GM_IS_RX_FF_OR) {
2093 ++sky2->net_stats.rx_fifo_errors;
2094 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2095 }
2096
2097 if (status & GM_IS_TX_FF_UR) {
2098 ++sky2->net_stats.tx_fifo_errors;
2099 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2100 }
cd28ab6a
SH		 2101}
2102
d257924e
SH		 2103/* This should never happen it is a fatal situation */
2104static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2105 const char *rxtx, u32 mask)
2106{
2107 struct net_device *dev = hw->dev[port];
2108 struct sky2_port *sky2 = netdev_priv(dev);
2109 u32 imask;
2110
2111 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2112 dev ? dev->name : "<not registered>", rxtx);
2113
2114 imask = sky2_read32(hw, B0_IMSK);
2115 imask &= ~mask;
2116 sky2_write32(hw, B0_IMSK, imask);
2117
2118 if (dev) {
2119 spin_lock(&sky2->phy_lock);
2120 sky2_link_down(sky2);
2121 spin_unlock(&sky2->phy_lock);
2122 }
2123}
cd28ab6a 2124
d27ed387
SH		 2125/* If idle then force a fake soft NAPI poll once a second
2126 * to work around cases where sharing an edge triggered interrupt.
2127 */
2128static void sky2_idle(unsigned long arg)
2129{
01bd7564
SH		 2130 struct sky2_hw *hw = (struct sky2_hw *) arg;
2131 struct net_device *dev = hw->dev[0];
d27ed387 2132
d27ed387
SH		 2133 if (__netif_rx_schedule_prep(dev))
2134 __netif_rx_schedule(dev);
01bd7564
SH		 2135
2136 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2137}
2138
2139
e07b1aa8 2140static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2141{
e07b1aa8
SH		 2142 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2143 int work_limit = min(dev0->quota, *budget);
2144 int work_done = 0;
fb2690a9 2145 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2146
1e5f1283
SH		 2147 if (status & Y2_IS_HW_ERR)
2148 sky2_hw_intr(hw);
d257924e 2149
1e5f1283
SH		 2150 if (status & Y2_IS_IRQ_PHY1)
2151 sky2_phy_intr(hw, 0);
cd28ab6a 2152
1e5f1283
SH		 2153 if (status & Y2_IS_IRQ_PHY2)
2154 sky2_phy_intr(hw, 1);
cd28ab6a 2155
1e5f1283
SH		 2156 if (status & Y2_IS_IRQ_MAC1)
2157 sky2_mac_intr(hw, 0);
cd28ab6a 2158
1e5f1283
SH		 2159 if (status & Y2_IS_IRQ_MAC2)
2160 sky2_mac_intr(hw, 1);
cd28ab6a 2161
1e5f1283
SH		 2162 if (status & Y2_IS_CHK_RX1)
2163 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2164
1e5f1283
SH		 2165 if (status & Y2_IS_CHK_RX2)
2166 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2167
1e5f1283
SH		 2168 if (status & Y2_IS_CHK_TXA1)
2169 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2170
1e5f1283
SH		 2171 if (status & Y2_IS_CHK_TXA2)
2172 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2173
1e5f1283
SH		 2174 if (status & Y2_IS_STAT_BMU)
2175 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
e07b1aa8 2176
1e5f1283
SH		 2177 work_done = sky2_status_intr(hw, work_limit);
2178 *budget -= work_done;
2179 dev0->quota -= work_done;
e07b1aa8 2180
1e5f1283
SH		 2181 if (work_done >= work_limit)
2182 return 1;
e07b1aa8 2183
d3240312 2184 netif_rx_complete(dev0);
e07b1aa8 2185
fb2690a9 2186 status = sky2_read32(hw, B0_Y2_SP_LISR);
e07b1aa8
SH		 2187 return 0;
2188}
2189
2190static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2191{
2192 struct sky2_hw *hw = dev_id;
2193 struct net_device *dev0 = hw->dev[0];
2194 u32 status;
2195
2196 /* Reading this mask interrupts as side effect */
2197 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2198 if (status == 0 || status == ~0)
2199 return IRQ_NONE;
793b883e 2200
e07b1aa8
SH		 2201 prefetch(&hw->st_le[hw->st_idx]);
2202 if (likely(__netif_rx_schedule_prep(dev0)))
2203 __netif_rx_schedule(dev0);
793b883e 2204
cd28ab6a
SH		 2205 return IRQ_HANDLED;
2206}
2207
2208#ifdef CONFIG_NET_POLL_CONTROLLER
2209static void sky2_netpoll(struct net_device *dev)
2210{
2211 struct sky2_port *sky2 = netdev_priv(dev);
2212
793b883e 2213 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
cd28ab6a
SH		 2214}
2215#endif
2216
2217/* Chip internal frequency for clock calculations */
fb17358f 2218static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2219{
793b883e 2220 switch (hw->chip_id) {
cd28ab6a 2221 case CHIP_ID_YUKON_EC:
5a5b1ea0 2222 case CHIP_ID_YUKON_EC_U:
fb17358f 2223 return 125; /* 125 Mhz */
cd28ab6a 2224 case CHIP_ID_YUKON_FE:
fb17358f 2225 return 100; /* 100 Mhz */
793b883e 2226 default: /* YUKON_XL */
fb17358f 2227 return 156; /* 156 Mhz */
cd28ab6a
SH		 2228 }
2229}
2230
fb17358f 2231static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2232{
fb17358f 2233 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2234}
2235
fb17358f 2236static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2237{
fb17358f 2238 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2239}
2240
fb17358f 2241
98712e5e 2242static int __devinit sky2_reset(struct sky2_hw *hw)
cd28ab6a 2243{
cd28ab6a
SH		 2244 u16 status;
2245 u8 t8, pmd_type;
56a645cc 2246 int i;
cd28ab6a 2247
cd28ab6a 2248 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2249
cd28ab6a
SH		 2250 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2251 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2252 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2253 pci_name(hw->pdev), hw->chip_id);
2254 return -EOPNOTSUPP;
2255 }
2256
290d4de5
SH		 2257 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2258
2259 /* This rev is really old, and requires untested workarounds */
2260 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2261 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2262 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2263 hw->chip_id, hw->chip_rev);
2264 return -EOPNOTSUPP;
2265 }
2266
cd28ab6a
SH		 2267 /* disable ASF */
2268 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2269 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2270 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2271 }
2272
2273 /* do a SW reset */
2274 sky2_write8(hw, B0_CTST, CS_RST_SET);
2275 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2276
2277 /* clear PCI errors, if any */
56a645cc 2278 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2279
cd28ab6a 2280 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2281 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2282
cd28ab6a
SH		 2283
2284 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2285
2286 /* clear any PEX errors */
d89e1343 2287 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
56a645cc
SH		 2288 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2289
cd28ab6a
SH		 2290
2291 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2292 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2293
2294 hw->ports = 1;
2295 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2296 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2297 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2298 ++hw->ports;
2299 }
cd28ab6a 2300
5afa0a9c 2301 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2302
2303 for (i = 0; i < hw->ports; i++) {
2304 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2305 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2306 }
2307
2308 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2309
793b883e
SH		 2310 /* Clear I2C IRQ noise */
2311 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2312
2313 /* turn off hardware timer (unused) */
2314 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2315 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2316
cd28ab6a
SH		 2317 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2318
69634ee7
SH		 2319 /* Turn off descriptor polling */
2320 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2321
2322 /* Turn off receive timestamp */
2323 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2324 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2325
2326 /* enable the Tx Arbiters */
2327 for (i = 0; i < hw->ports; i++)
2328 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2329
2330 /* Initialize ram interface */
2331 for (i = 0; i < hw->ports; i++) {
793b883e 2332 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2333
2334 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2335 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2336 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2337 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2338 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2339 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2340 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2341 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2342 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2343 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2344 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2345 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2346 }
2347
cd28ab6a
SH		 2348 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2349
cd28ab6a
SH		 2350 for (i = 0; i < hw->ports; i++)
2351 sky2_phy_reset(hw, i);
cd28ab6a 2352
cd28ab6a
SH		 2353 memset(hw->st_le, 0, STATUS_LE_BYTES);
2354 hw->st_idx = 0;
2355
2356 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2357 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2358
2359 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2360 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2361
2362 /* Set the list last index */
793b883e 2363 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2364
290d4de5
SH		 2365 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2366 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2367
290d4de5
SH		 2368 /* set Status-FIFO ISR watermark */
2369 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2370 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2371 else
2372 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2373
290d4de5 2374 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2375 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2376 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2377
793b883e 2378 /* enable status unit */
cd28ab6a
SH		 2379 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2380
2381 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2382 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2383 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2384
2385 return 0;
2386}
2387
28bd181a 2388static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a
SH		 2389{
2390 u32 modes;
2391 if (hw->copper) {
793b883e
SH		 2392 modes = SUPPORTED_10baseT_Half
2393 | SUPPORTED_10baseT_Full
2394 | SUPPORTED_100baseT_Half
2395 | SUPPORTED_100baseT_Full
2396 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2397
2398 if (hw->chip_id != CHIP_ID_YUKON_FE)
2399 modes |= SUPPORTED_1000baseT_Half
793b883e 2400 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 2401 } else
2402 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
793b883e 2403 | SUPPORTED_Autoneg;
cd28ab6a
SH		 2404 return modes;
2405}
2406
793b883e 2407static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2408{
2409 struct sky2_port *sky2 = netdev_priv(dev);
2410 struct sky2_hw *hw = sky2->hw;
2411
2412 ecmd->transceiver = XCVR_INTERNAL;
2413 ecmd->supported = sky2_supported_modes(hw);
2414 ecmd->phy_address = PHY_ADDR_MARV;
2415 if (hw->copper) {
2416 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2417 | SUPPORTED_10baseT_Full
2418 | SUPPORTED_100baseT_Half
2419 | SUPPORTED_100baseT_Full
2420 | SUPPORTED_1000baseT_Half
2421 | SUPPORTED_1000baseT_Full
2422 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2423 ecmd->port = PORT_TP;
2424 } else
2425 ecmd->port = PORT_FIBRE;
2426
2427 ecmd->advertising = sky2->advertising;
2428 ecmd->autoneg = sky2->autoneg;
2429 ecmd->speed = sky2->speed;
2430 ecmd->duplex = sky2->duplex;
2431 return 0;
2432}
2433
2434static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2435{
2436 struct sky2_port *sky2 = netdev_priv(dev);
2437 const struct sky2_hw *hw = sky2->hw;
2438 u32 supported = sky2_supported_modes(hw);
2439
2440 if (ecmd->autoneg == AUTONEG_ENABLE) {
2441 ecmd->advertising = supported;
2442 sky2->duplex = -1;
2443 sky2->speed = -1;
2444 } else {
2445 u32 setting;
2446
793b883e 2447 switch (ecmd->speed) {
cd28ab6a
SH		 2448 case SPEED_1000:
2449 if (ecmd->duplex == DUPLEX_FULL)
2450 setting = SUPPORTED_1000baseT_Full;
2451 else if (ecmd->duplex == DUPLEX_HALF)
2452 setting = SUPPORTED_1000baseT_Half;
2453 else
2454 return -EINVAL;
2455 break;
2456 case SPEED_100:
2457 if (ecmd->duplex == DUPLEX_FULL)
2458 setting = SUPPORTED_100baseT_Full;
2459 else if (ecmd->duplex == DUPLEX_HALF)
2460 setting = SUPPORTED_100baseT_Half;
2461 else
2462 return -EINVAL;
2463 break;
2464
2465 case SPEED_10:
2466 if (ecmd->duplex == DUPLEX_FULL)
2467 setting = SUPPORTED_10baseT_Full;
2468 else if (ecmd->duplex == DUPLEX_HALF)
2469 setting = SUPPORTED_10baseT_Half;
2470 else
2471 return -EINVAL;
2472 break;
2473 default:
2474 return -EINVAL;
2475 }
2476
2477 if ((setting & supported) == 0)
2478 return -EINVAL;
2479
2480 sky2->speed = ecmd->speed;
2481 sky2->duplex = ecmd->duplex;
2482 }
2483
2484 sky2->autoneg = ecmd->autoneg;
2485 sky2->advertising = ecmd->advertising;
2486
1b537565
SH		 2487 if (netif_running(dev))
2488 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2489
2490 return 0;
2491}
2492
2493static void sky2_get_drvinfo(struct net_device *dev,
2494 struct ethtool_drvinfo *info)
2495{
2496 struct sky2_port *sky2 = netdev_priv(dev);
2497
2498 strcpy(info->driver, DRV_NAME);
2499 strcpy(info->version, DRV_VERSION);
2500 strcpy(info->fw_version, "N/A");
2501 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2502}
2503
2504static const struct sky2_stat {
793b883e
SH		 2505 char name[ETH_GSTRING_LEN];
2506 u16 offset;
cd28ab6a
SH		 2507} sky2_stats[] = {
2508 { "tx_bytes", GM_TXO_OK_HI },
2509 { "rx_bytes", GM_RXO_OK_HI },
2510 { "tx_broadcast", GM_TXF_BC_OK },
2511 { "rx_broadcast", GM_RXF_BC_OK },
2512 { "tx_multicast", GM_TXF_MC_OK },
2513 { "rx_multicast", GM_RXF_MC_OK },
2514 { "tx_unicast", GM_TXF_UC_OK },
2515 { "rx_unicast", GM_RXF_UC_OK },
2516 { "tx_mac_pause", GM_TXF_MPAUSE },
2517 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2518 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2519 { "late_collision",GM_TXF_LAT_COL },
2520 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2521 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2522 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2523
d2604540 2524 { "rx_short", GM_RXF_SHT },
cd28ab6a 2525 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2526 { "rx_64_byte_packets", GM_RXF_64B },
2527 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2528 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2529 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2530 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2531 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2532 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2533 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2534 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2535 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2536 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2537
2538 { "tx_64_byte_packets", GM_TXF_64B },
2539 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2540 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2541 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2542 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2543 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2544 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2545 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2546};
2547
cd28ab6a
SH		 2548static u32 sky2_get_rx_csum(struct net_device *dev)
2549{
2550 struct sky2_port *sky2 = netdev_priv(dev);
2551
2552 return sky2->rx_csum;
2553}
2554
2555static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2556{
2557 struct sky2_port *sky2 = netdev_priv(dev);
2558
2559 sky2->rx_csum = data;
793b883e 2560
cd28ab6a
SH		 2561 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2562 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2563
2564 return 0;
2565}
2566
2567static u32 sky2_get_msglevel(struct net_device *netdev)
2568{
2569 struct sky2_port *sky2 = netdev_priv(netdev);
2570 return sky2->msg_enable;
2571}
2572
9a7ae0a9
SH		 2573static int sky2_nway_reset(struct net_device *dev)
2574{
2575 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9
SH		 2576
2577 if (sky2->autoneg != AUTONEG_ENABLE)
2578 return -EINVAL;
2579
1b537565 2580 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2581
2582 return 0;
2583}
2584
793b883e 2585static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2586{
2587 struct sky2_hw *hw = sky2->hw;
2588 unsigned port = sky2->port;
2589 int i;
2590
2591 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2592 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2593 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2594 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2595
793b883e 2596 for (i = 2; i < count; i++)
cd28ab6a
SH		 2597 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2598}
2599
cd28ab6a
SH		 2600static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2601{
2602 struct sky2_port *sky2 = netdev_priv(netdev);
2603 sky2->msg_enable = value;
2604}
2605
2606static int sky2_get_stats_count(struct net_device *dev)
2607{
2608 return ARRAY_SIZE(sky2_stats);
2609}
2610
2611static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2612 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2613{
2614 struct sky2_port *sky2 = netdev_priv(dev);
2615
793b883e 2616 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2617}
2618
793b883e 2619static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2620{
2621 int i;
2622
2623 switch (stringset) {
2624 case ETH_SS_STATS:
2625 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2626 memcpy(data + i * ETH_GSTRING_LEN,
2627 sky2_stats[i].name, ETH_GSTRING_LEN);
2628 break;
2629 }
2630}
2631
2632/* Use hardware MIB variables for critical path statistics and
2633 * transmit feedback not reported at interrupt.
2634 * Other errors are accounted for in interrupt handler.
2635 */
2636static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2637{
2638 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2639 u64 data[13];
cd28ab6a 2640
793b883e 2641 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2642
2643 sky2->net_stats.tx_bytes = data[0];
2644 sky2->net_stats.rx_bytes = data[1];
2645 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2646 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
050ff180 2647 sky2->net_stats.multicast = data[3] + data[5];
cd28ab6a
SH		 2648 sky2->net_stats.collisions = data[10];
2649 sky2->net_stats.tx_aborted_errors = data[12];
2650
2651 return &sky2->net_stats;
2652}
2653
2654static int sky2_set_mac_address(struct net_device *dev, void *p)
2655{
2656 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2657 struct sky2_hw *hw = sky2->hw;
2658 unsigned port = sky2->port;
2659 const struct sockaddr *addr = p;
cd28ab6a
SH		 2660
2661 if (!is_valid_ether_addr(addr->sa_data))
2662 return -EADDRNOTAVAIL;
2663
cd28ab6a 2664 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2665 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2666 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2667 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2668 dev->dev_addr, ETH_ALEN);
1b537565 2669
a8ab1ec0
SH		 2670 /* virtual address for data */
2671 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2672
2673 /* physical address: used for pause frames */
2674 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2675
2676 return 0;
cd28ab6a
SH		 2677}
2678
2679static void sky2_set_multicast(struct net_device *dev)
2680{
2681 struct sky2_port *sky2 = netdev_priv(dev);
2682 struct sky2_hw *hw = sky2->hw;
2683 unsigned port = sky2->port;
2684 struct dev_mc_list *list = dev->mc_list;
2685 u16 reg;
2686 u8 filter[8];
2687
2688 memset(filter, 0, sizeof(filter));
2689
2690 reg = gma_read16(hw, port, GM_RX_CTRL);
2691 reg |= GM_RXCR_UCF_ENA;
2692
d571b694 2693 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2694 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2695 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2696 memset(filter, 0xff, sizeof(filter));
793b883e 2697 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2698 reg &= ~GM_RXCR_MCF_ENA;
2699 else {
2700 int i;
2701 reg |= GM_RXCR_MCF_ENA;
2702
2703 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2704 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2705 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2706 }
2707 }
2708
cd28ab6a 2709 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2710 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2711 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2712 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2713 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2714 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2715 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2716 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2717
2718 gma_write16(hw, port, GM_RX_CTRL, reg);
2719}
2720
2721/* Can have one global because blinking is controlled by
2722 * ethtool and that is always under RTNL mutex
2723 */
91c86df5 2724static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2725{
793b883e
SH		 2726 u16 pg;
2727
793b883e
SH		 2728 switch (hw->chip_id) {
2729 case CHIP_ID_YUKON_XL:
2730 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2731 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2732 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2733 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2734 PHY_M_LEDC_INIT_CTRL(7) |
2735 PHY_M_LEDC_STA1_CTRL(7) |
2736 PHY_M_LEDC_STA0_CTRL(7))
2737 : 0);
2738
2739 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2740 break;
2741
2742 default:
2743 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2744 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2745 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2746 PHY_M_LED_MO_10(MO_LED_ON) |
2747 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2748 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2749 PHY_M_LED_MO_RX(MO_LED_ON)
2750 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2751 PHY_M_LED_MO_10(MO_LED_OFF) |
2752 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2753 PHY_M_LED_MO_1000(MO_LED_OFF) |
2754 PHY_M_LED_MO_RX(MO_LED_OFF));
2755
793b883e 2756 }
cd28ab6a
SH		 2757}
2758
2759/* blink LED's for finding board */
2760static int sky2_phys_id(struct net_device *dev, u32 data)
2761{
2762 struct sky2_port *sky2 = netdev_priv(dev);
2763 struct sky2_hw *hw = sky2->hw;
2764 unsigned port = sky2->port;
793b883e 2765 u16 ledctrl, ledover = 0;
cd28ab6a 2766 long ms;
91c86df5 2767 int interrupted;
cd28ab6a
SH		 2768 int onoff = 1;
2769
793b883e 2770 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2771 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2772 else
2773 ms = data * 1000;
2774
2775 /* save initial values */
e07b1aa8 2776 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2777 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2778 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2779 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2780 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2781 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2782 } else {
2783 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2784 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2785 }
cd28ab6a 2786
91c86df5
SH		 2787 interrupted = 0;
2788 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2789 sky2_led(hw, port, onoff);
2790 onoff = !onoff;
2791
e07b1aa8 2792 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2793 interrupted = msleep_interruptible(250);
e07b1aa8 2794 spin_lock_bh(&sky2->phy_lock);
91c86df5 2795
cd28ab6a
SH		 2796 ms -= 250;
2797 }
2798
2799 /* resume regularly scheduled programming */
793b883e
SH		 2800 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2801 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2802 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2803 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2804 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2805 } else {
2806 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2807 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2808 }
e07b1aa8 2809 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2810
2811 return 0;
2812}
2813
2814static void sky2_get_pauseparam(struct net_device *dev,
2815 struct ethtool_pauseparam *ecmd)
2816{
2817 struct sky2_port *sky2 = netdev_priv(dev);
2818
2819 ecmd->tx_pause = sky2->tx_pause;
2820 ecmd->rx_pause = sky2->rx_pause;
2821 ecmd->autoneg = sky2->autoneg;
2822}
2823
2824static int sky2_set_pauseparam(struct net_device *dev,
2825 struct ethtool_pauseparam *ecmd)
2826{
2827 struct sky2_port *sky2 = netdev_priv(dev);
2828 int err = 0;
2829
2830 sky2->autoneg = ecmd->autoneg;
2831 sky2->tx_pause = ecmd->tx_pause != 0;
2832 sky2->rx_pause = ecmd->rx_pause != 0;
2833
1b537565 2834 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2835
2836 return err;
2837}
2838
fb17358f
SH		 2839static int sky2_get_coalesce(struct net_device *dev,
2840 struct ethtool_coalesce *ecmd)
2841{
2842 struct sky2_port *sky2 = netdev_priv(dev);
2843 struct sky2_hw *hw = sky2->hw;
2844
2845 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2846 ecmd->tx_coalesce_usecs = 0;
2847 else {
2848 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2849 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2850 }
2851 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2852
2853 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2854 ecmd->rx_coalesce_usecs = 0;
2855 else {
2856 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2857 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2858 }
2859 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2860
2861 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2862 ecmd->rx_coalesce_usecs_irq = 0;
2863 else {
2864 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2865 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2866 }
2867
2868 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2869
2870 return 0;
2871}
2872
2873/* Note: this affect both ports */
2874static int sky2_set_coalesce(struct net_device *dev,
2875 struct ethtool_coalesce *ecmd)
2876{
2877 struct sky2_port *sky2 = netdev_priv(dev);
2878 struct sky2_hw *hw = sky2->hw;
77b3d6a2 2879 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 2880
77b3d6a2
SH		 2881 if (ecmd->tx_coalesce_usecs > tmax ||
2882 ecmd->rx_coalesce_usecs > tmax ||
2883 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 2884 return -EINVAL;
2885
ff81fbbe 2886 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 2887 return -EINVAL;
ff81fbbe 2888 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 2889 return -EINVAL;
ff81fbbe 2890 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 2891 return -EINVAL;
2892
2893 if (ecmd->tx_coalesce_usecs == 0)
2894 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2895 else {
2896 sky2_write32(hw, STAT_TX_TIMER_INI,
2897 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2898 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2899 }
2900 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2901
2902 if (ecmd->rx_coalesce_usecs == 0)
2903 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2904 else {
2905 sky2_write32(hw, STAT_LEV_TIMER_INI,
2906 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2907 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2908 }
2909 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2910
2911 if (ecmd->rx_coalesce_usecs_irq == 0)
2912 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2913 else {
d28d4870 2914 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 2915 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2916 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2917 }
2918 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2919 return 0;
2920}
2921
793b883e
SH		 2922static void sky2_get_ringparam(struct net_device *dev,
2923 struct ethtool_ringparam *ering)
2924{
2925 struct sky2_port *sky2 = netdev_priv(dev);
2926
2927 ering->rx_max_pending = RX_MAX_PENDING;
2928 ering->rx_mini_max_pending = 0;
2929 ering->rx_jumbo_max_pending = 0;
2930 ering->tx_max_pending = TX_RING_SIZE - 1;
2931
2932 ering->rx_pending = sky2->rx_pending;
2933 ering->rx_mini_pending = 0;
2934 ering->rx_jumbo_pending = 0;
2935 ering->tx_pending = sky2->tx_pending;
2936}
2937
2938static int sky2_set_ringparam(struct net_device *dev,
2939 struct ethtool_ringparam *ering)
2940{
2941 struct sky2_port *sky2 = netdev_priv(dev);
2942 int err = 0;
2943
2944 if (ering->rx_pending > RX_MAX_PENDING ||
2945 ering->rx_pending < 8 ||
2946 ering->tx_pending < MAX_SKB_TX_LE ||
2947 ering->tx_pending > TX_RING_SIZE - 1)
2948 return -EINVAL;
2949
2950 if (netif_running(dev))
2951 sky2_down(dev);
2952
2953 sky2->rx_pending = ering->rx_pending;
2954 sky2->tx_pending = ering->tx_pending;
2955
1b537565 2956 if (netif_running(dev)) {
793b883e 2957 err = sky2_up(dev);
1b537565
SH		 2958 if (err)
2959 dev_close(dev);
6ed995bb
SH		 2960 else
2961 sky2_set_multicast(dev);
1b537565 2962 }
793b883e
SH		 2963
2964 return err;
2965}
2966
793b883e
SH		 2967static int sky2_get_regs_len(struct net_device *dev)
2968{
6e4cbb34 2969 return 0x4000;
793b883e
SH		 2970}
2971
2972/*
2973 * Returns copy of control register region
6e4cbb34 2974 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 2975 */
2976static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2977 void *p)
2978{
2979 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2980 const void __iomem *io = sky2->hw->regs;
793b883e 2981
6e4cbb34 2982 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 2983 regs->version = 1;
6e4cbb34 2984 memset(p, 0, regs->len);
793b883e 2985
6e4cbb34
SH		 2986 memcpy_fromio(p, io, B3_RAM_ADDR);
2987
2988 memcpy_fromio(p + B3_RI_WTO_R1,
2989 io + B3_RI_WTO_R1,
2990 regs->len - B3_RI_WTO_R1);
793b883e 2991}
cd28ab6a
SH		 2992
2993static struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 2994 .get_settings = sky2_get_settings,
2995 .set_settings = sky2_set_settings,
2996 .get_drvinfo = sky2_get_drvinfo,
2997 .get_msglevel = sky2_get_msglevel,
2998 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 2999 .nway_reset = sky2_nway_reset,
793b883e
SH		 3000 .get_regs_len = sky2_get_regs_len,
3001 .get_regs = sky2_get_regs,
3002 .get_link = ethtool_op_get_link,
3003 .get_sg = ethtool_op_get_sg,
3004 .set_sg = ethtool_op_set_sg,
3005 .get_tx_csum = ethtool_op_get_tx_csum,
3006 .set_tx_csum = ethtool_op_set_tx_csum,
3007 .get_tso = ethtool_op_get_tso,
3008 .set_tso = ethtool_op_set_tso,
3009 .get_rx_csum = sky2_get_rx_csum,
3010 .set_rx_csum = sky2_set_rx_csum,
3011 .get_strings = sky2_get_strings,
fb17358f
SH		 3012 .get_coalesce = sky2_get_coalesce,
3013 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3014 .get_ringparam = sky2_get_ringparam,
3015 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3016 .get_pauseparam = sky2_get_pauseparam,
3017 .set_pauseparam = sky2_set_pauseparam,
793b883e 3018 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3019 .get_stats_count = sky2_get_stats_count,
3020 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3021 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3022};
3023
3024/* Initialize network device */
3025static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3026 unsigned port, int highmem)
3027{
3028 struct sky2_port *sky2;
3029 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3030
3031 if (!dev) {
3032 printk(KERN_ERR "sky2 etherdev alloc failed");
3033 return NULL;
3034 }
3035
3036 SET_MODULE_OWNER(dev);
3037 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3038 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3039 dev->open = sky2_up;
3040 dev->stop = sky2_down;
ef743d33 3041 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3042 dev->hard_start_xmit = sky2_xmit_frame;
3043 dev->get_stats = sky2_get_stats;
3044 dev->set_multicast_list = sky2_set_multicast;
3045 dev->set_mac_address = sky2_set_mac_address;
3046 dev->change_mtu = sky2_change_mtu;
3047 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3048 dev->tx_timeout = sky2_tx_timeout;
3049 dev->watchdog_timeo = TX_WATCHDOG;
3050 if (port == 0)
3051 dev->poll = sky2_poll;
3052 dev->weight = NAPI_WEIGHT;
3053#ifdef CONFIG_NET_POLL_CONTROLLER
3054 dev->poll_controller = sky2_netpoll;
3055#endif
cd28ab6a
SH		 3056
3057 sky2 = netdev_priv(dev);
3058 sky2->netdev = dev;
3059 sky2->hw = hw;
3060 sky2->msg_enable = netif_msg_init(debug, default_msg);
3061
3062 spin_lock_init(&sky2->tx_lock);
3063 /* Auto speed and flow control */
3064 sky2->autoneg = AUTONEG_ENABLE;
585b5601 3065 sky2->tx_pause = 1;
cd28ab6a
SH		 3066 sky2->rx_pause = 1;
3067 sky2->duplex = -1;
3068 sky2->speed = -1;
3069 sky2->advertising = sky2_supported_modes(hw);
75d070c5 3070
d89e1343 3071 /* Receive checksum disabled for Yukon XL
75d070c5
SH		 3072 * because of observed problems with incorrect
3073 * values when multiple packets are received in one interrupt
3074 */
3075 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
3076
e07b1aa8 3077 spin_lock_init(&sky2->phy_lock);
793b883e 3078 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3079 sky2->rx_pending = RX_DEF_PENDING;
734d1868 3080 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
cd28ab6a
SH		 3081
3082 hw->dev[port] = dev;
3083
3084 sky2->port = port;
3085
5a5b1ea0 3086 dev->features |= NETIF_F_LLTX;
3087 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3088 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3089 if (highmem)
3090 dev->features |= NETIF_F_HIGHDMA;
793b883e 3091 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3092
d1f13708 3093#ifdef SKY2_VLAN_TAG_USED
3094 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3095 dev->vlan_rx_register = sky2_vlan_rx_register;
3096 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3097#endif
3098
cd28ab6a 3099 /* read the mac address */
793b883e 3100 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3101 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3102
3103 /* device is off until link detection */
3104 netif_carrier_off(dev);
3105 netif_stop_queue(dev);
3106
3107 return dev;
3108}
3109
28bd181a 3110static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3111{
3112 const struct sky2_port *sky2 = netdev_priv(dev);
3113
3114 if (netif_msg_probe(sky2))
3115 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3116 dev->name,
3117 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3118 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3119}
3120
fb2690a9
SH		 3121/* Handle software interrupt used during MSI test */
3122static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3123 struct pt_regs *regs)
3124{
3125 struct sky2_hw *hw = dev_id;
3126 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3127
3128 if (status == 0)
3129 return IRQ_NONE;
3130
3131 if (status & Y2_IS_IRQ_SW) {
3132 hw->msi_detected = 1;
3133 wake_up(&hw->msi_wait);
3134 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3135 }
3136 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3137
3138 return IRQ_HANDLED;
3139}
3140
3141/* Test interrupt path by forcing a a software IRQ */
3142static int __devinit sky2_test_msi(struct sky2_hw *hw)
3143{
3144 struct pci_dev *pdev = hw->pdev;
3145 int err;
3146
3147 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3148
3149 err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw);
3150 if (err) {
3151 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3152 pci_name(pdev), pdev->irq);
3153 return err;
3154 }
3155
3156 init_waitqueue_head (&hw->msi_wait);
3157
3158 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3159 wmb();
3160
3161 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3162
3163 if (!hw->msi_detected) {
3164 /* MSI test failed, go back to INTx mode */
3165 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3166 "switching to INTx mode. Please report this failure to "
3167 "the PCI maintainer and include system chipset information.\n",
3168 pci_name(pdev));
3169
3170 err = -EOPNOTSUPP;
3171 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3172 }
3173
3174 sky2_write32(hw, B0_IMSK, 0);
3175
3176 free_irq(pdev->irq, hw);
3177
3178 return err;
3179}
3180
cd28ab6a
SH		 3181static int __devinit sky2_probe(struct pci_dev *pdev,
3182 const struct pci_device_id *ent)
3183{
793b883e 3184 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3185 struct sky2_hw *hw;
5afa0a9c 3186 int err, pm_cap, using_dac = 0;
cd28ab6a 3187
793b883e
SH		 3188 err = pci_enable_device(pdev);
3189 if (err) {
cd28ab6a
SH		 3190 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3191 pci_name(pdev));
3192 goto err_out;
3193 }
3194
793b883e
SH		 3195 err = pci_request_regions(pdev, DRV_NAME);
3196 if (err) {
cd28ab6a
SH		 3197 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3198 pci_name(pdev));
793b883e 3199 goto err_out;
cd28ab6a
SH		 3200 }
3201
3202 pci_set_master(pdev);
3203
5afa0a9c 3204 /* Find power-management capability. */
3205 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3206 if (pm_cap == 0) {
3207 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3208 "aborting.\n");
3209 err = -EIO;
3210 goto err_out_free_regions;
3211 }
3212
d1f3d4dd
SH		 3213 if (sizeof(dma_addr_t) > sizeof(u32) &&
3214 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3215 using_dac = 1;
3216 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3217 if (err < 0) {
3218 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3219 "for consistent allocations\n", pci_name(pdev));
3220 goto err_out_free_regions;
3221 }
cd28ab6a 3222
d1f3d4dd 3223 } else {
cd28ab6a
SH		 3224 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3225 if (err) {
3226 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3227 pci_name(pdev));
3228 goto err_out_free_regions;
3229 }
3230 }
d1f3d4dd 3231
cd28ab6a 3232 err = -ENOMEM;
6aad85d6 3233 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3234 if (!hw) {
3235 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3236 pci_name(pdev));
3237 goto err_out_free_regions;
3238 }
3239
cd28ab6a 3240 hw->pdev = pdev;
cd28ab6a
SH		 3241
3242 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3243 if (!hw->regs) {
3244 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3245 pci_name(pdev));
3246 goto err_out_free_hw;
3247 }
5afa0a9c 3248 hw->pm_cap = pm_cap;
cd28ab6a 3249
56a645cc
SH		 3250#ifdef __BIG_ENDIAN
3251 /* byte swap descriptors in hardware */
3252 {
3253 u32 reg;
3254
3255 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3256 reg |= PCI_REV_DESC;
3257 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3258 }
3259#endif
3260
08c06d8a
SH		 3261 /* ring for status responses */
3262 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3263 &hw->st_dma);
3264 if (!hw->st_le)
3265 goto err_out_iounmap;
3266
cd28ab6a
SH		 3267 err = sky2_reset(hw);
3268 if (err)
793b883e 3269 goto err_out_iounmap;
cd28ab6a 3270
5f4f9dc1 3271 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3272 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
92f965e8 3273 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3274 hw->chip_id, hw->chip_rev);
cd28ab6a 3275
793b883e
SH		 3276 dev = sky2_init_netdev(hw, 0, using_dac);
3277 if (!dev)
cd28ab6a
SH		 3278 goto err_out_free_pci;
3279
793b883e
SH		 3280 err = register_netdev(dev);
3281 if (err) {
cd28ab6a
SH		 3282 printk(KERN_ERR PFX "%s: cannot register net device\n",
3283 pci_name(pdev));
3284 goto err_out_free_netdev;
3285 }
3286
3287 sky2_show_addr(dev);
3288
3289 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3290 if (register_netdev(dev1) == 0)
3291 sky2_show_addr(dev1);
3292 else {
3293 /* Failure to register second port need not be fatal */
793b883e
SH		 3294 printk(KERN_WARNING PFX
3295 "register of second port failed\n");
cd28ab6a
SH		 3296 hw->dev[1] = NULL;
3297 free_netdev(dev1);
3298 }
3299 }
3300
fb2690a9
SH		 3301 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3302 err = sky2_test_msi(hw);
3303 if (err == -EOPNOTSUPP)
3304 pci_disable_msi(pdev);
3305 else if (err)
3306 goto err_out_unregister;
3307 }
3308
3309 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
793b883e
SH		 3310 if (err) {
3311 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3312 pci_name(pdev), pdev->irq);
3313 goto err_out_unregister;
3314 }
3315
e07b1aa8 3316 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
793b883e 3317
01bd7564
SH		 3318 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3319 if (idle_timeout > 0)
3320 mod_timer(&hw->idle_timer,
3321 jiffies + msecs_to_jiffies(idle_timeout));
d27ed387 3322
793b883e
SH		 3323 pci_set_drvdata(pdev, hw);
3324
cd28ab6a
SH		 3325 return 0;
3326
793b883e 3327err_out_unregister:
fb2690a9 3328 pci_disable_msi(pdev);
793b883e
SH		 3329 if (dev1) {
3330 unregister_netdev(dev1);
3331 free_netdev(dev1);
3332 }
3333 unregister_netdev(dev);
cd28ab6a
SH		 3334err_out_free_netdev:
3335 free_netdev(dev);
cd28ab6a 3336err_out_free_pci:
793b883e 3337 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3338 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3339err_out_iounmap:
3340 iounmap(hw->regs);
3341err_out_free_hw:
3342 kfree(hw);
3343err_out_free_regions:
3344 pci_release_regions(pdev);
cd28ab6a 3345 pci_disable_device(pdev);
cd28ab6a
SH		 3346err_out:
3347 return err;
3348}
3349
3350static void __devexit sky2_remove(struct pci_dev *pdev)
3351{
793b883e 3352 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3353 struct net_device *dev0, *dev1;
3354
793b883e 3355 if (!hw)
cd28ab6a
SH		 3356 return;
3357
d27ed387
SH		 3358 del_timer_sync(&hw->idle_timer);
3359
3360 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3361 synchronize_irq(hw->pdev->irq);
3362
cd28ab6a 3363 dev0 = hw->dev[0];
793b883e
SH		 3364 dev1 = hw->dev[1];
3365 if (dev1)
3366 unregister_netdev(dev1);
cd28ab6a
SH		 3367 unregister_netdev(dev0);
3368
5afa0a9c 3369 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3370 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3371 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3372 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3373
3374 free_irq(pdev->irq, hw);
fb2690a9 3375 pci_disable_msi(pdev);
793b883e 3376 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3377 pci_release_regions(pdev);
3378 pci_disable_device(pdev);
793b883e 3379
cd28ab6a
SH		 3380 if (dev1)
3381 free_netdev(dev1);
3382 free_netdev(dev0);
3383 iounmap(hw->regs);
3384 kfree(hw);
5afa0a9c 3385
cd28ab6a
SH		 3386 pci_set_drvdata(pdev, NULL);
3387}
3388
3389#ifdef CONFIG_PM
3390static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3391{
793b883e 3392 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3393 int i;
cd28ab6a
SH		 3394
3395 for (i = 0; i < 2; i++) {
3396 struct net_device *dev = hw->dev[i];
3397
3398 if (dev) {
5afa0a9c 3399 if (!netif_running(dev))
3400 continue;
3401
3402 sky2_down(dev);
cd28ab6a 3403 netif_device_detach(dev);
cd28ab6a
SH		 3404 }
3405 }
3406
5afa0a9c 3407 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
cd28ab6a
SH		 3408}
3409
3410static int sky2_resume(struct pci_dev *pdev)
3411{
793b883e 3412 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3413 int i, err;
cd28ab6a 3414
cd28ab6a
SH		 3415 pci_restore_state(pdev);
3416 pci_enable_wake(pdev, PCI_D0, 0);
08c06d8a
SH		 3417 err = sky2_set_power_state(hw, PCI_D0);
3418 if (err)
3419 goto out;
cd28ab6a 3420
08c06d8a
SH		 3421 err = sky2_reset(hw);
3422 if (err)
3423 goto out;
cd28ab6a
SH		 3424
3425 for (i = 0; i < 2; i++) {
3426 struct net_device *dev = hw->dev[i];
08c06d8a
SH		 3427 if (dev && netif_running(dev)) {
3428 netif_device_attach(dev);
3429 err = sky2_up(dev);
3430 if (err) {
3431 printk(KERN_ERR PFX "%s: could not up: %d\n",
3432 dev->name, err);
3433 dev_close(dev);
3434 break;
5afa0a9c 3435 }
cd28ab6a
SH		 3436 }
3437 }
08c06d8a
SH		 3438out:
3439 return err;
cd28ab6a
SH		 3440}
3441#endif
3442
3443static struct pci_driver sky2_driver = {
793b883e
SH		 3444 .name = DRV_NAME,
3445 .id_table = sky2_id_table,
3446 .probe = sky2_probe,
3447 .remove = __devexit_p(sky2_remove),
cd28ab6a 3448#ifdef CONFIG_PM
793b883e
SH		 3449 .suspend = sky2_suspend,
3450 .resume = sky2_resume,
cd28ab6a
SH		 3451#endif
3452};
3453
3454static int __init sky2_init_module(void)
3455{
50241c4c 3456 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3457}
3458
3459static void __exit sky2_cleanup_module(void)
3460{
3461 pci_unregister_driver(&sky2_driver);
3462}
3463
3464module_init(sky2_init_module);
3465module_exit(sky2_cleanup_module);
3466
3467MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3468MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3469MODULE_LICENSE("GPL");
5f4f9dc1 3470MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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