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net: CONFIG_COMPAT redux
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a 26#include <linux/kernel.h>
cd28ab6a
SH		 27#include <linux/module.h>
28#include <linux/netdevice.h>
d0bbccfa 29#include <linux/dma-mapping.h>
cd28ab6a
SH		 30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/pci.h>
33#include <linux/ip.h>
c9bdd4b5 34#include <net/ip.h>
cd28ab6a
SH		 35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
3cf26753 41#include <linux/debugfs.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
ac958154 53#define DRV_VERSION "1.26"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
793b883e 66
ee5f68fe 67/* This is the worst case number of transmit list elements for a single skb:
07e31637
SH		 68 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
69#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
e9c1be80 70#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
ee5f68fe
SH		 71#define TX_MAX_PENDING 4096
72#define TX_DEF_PENDING 127
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
e6cac9ba 102static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
e30a4ac2 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
2d2a3871 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
0f5aac70 143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
cd28ab6a
SH		 144 { 0 }
145};
793b883e 146
cd28ab6a
SH		 147MODULE_DEVICE_TABLE(pci, sky2_id_table);
148
149/* Avoid conditionals by using array */
150static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
151static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 152static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 153
d1b139c0
SH		 154static void sky2_set_multicast(struct net_device *dev);
155
af043aa5 156/* Access to PHY via serial interconnect */
ef743d33 157static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 158{
159 int i;
160
161 gma_write16(hw, port, GM_SMI_DATA, val);
162 gma_write16(hw, port, GM_SMI_CTRL,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
164
165 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 166 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
167 if (ctrl == 0xffff)
168 goto io_error;
169
170 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 171 return 0;
af043aa5
SH		 172
173 udelay(10);
cd28ab6a 174 }
ef743d33 175
af043aa5 176 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 177 return -ETIMEDOUT;
af043aa5
SH		 178
179io_error:
180 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
181 return -EIO;
cd28ab6a
SH		 182}
183
ef743d33 184static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 185{
186 int i;
187
793b883e 188 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 189 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
190
191 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 192 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
193 if (ctrl == 0xffff)
194 goto io_error;
195
196 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33 197 *val = gma_read16(hw, port, GM_SMI_DATA);
198 return 0;
199 }
200
af043aa5 201 udelay(10);
cd28ab6a
SH		 202 }
203
af043aa5 204 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 205 return -ETIMEDOUT;
af043aa5
SH		 206io_error:
207 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
208 return -EIO;
ef743d33 209}
210
af043aa5 211static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33 212{
213 u16 v;
af043aa5 214 __gm_phy_read(hw, port, reg, &v);
ef743d33 215 return v;
cd28ab6a
SH		 216}
217
5afa0a9c 218
ae306cca
SH		 219static void sky2_power_on(struct sky2_hw *hw)
220{
221 /* switch power to VCC (WA for VAUX problem) */
222 sky2_write8(hw, B0_POWER_CTRL,
223 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 224
ae306cca
SH		 225 /* disable Core Clock Division, */
226 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 227
ae306cca
SH		 228 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
229 /* enable bits are inverted */
230 sky2_write8(hw, B2_Y2_CLK_GATE,
231 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
232 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
233 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
234 else
235 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 236
ea76e635 237 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 238 u32 reg;
5afa0a9c 239
b32f40c4 240 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 241
b32f40c4 242 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 243 /* set all bits to 0 except bits 15..12 and 8 */
244 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 245 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 246
b32f40c4 247 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 248 /* set all bits to 0 except bits 28 & 27 */
249 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 250 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 251
b32f40c4 252 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 253
254 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
255 reg = sky2_read32(hw, B2_GP_IO);
256 reg |= GLB_GPIO_STAT_RACE_DIS;
257 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 258
259 sky2_read32(hw, B2_GP_IO);
5afa0a9c 260 }
10547ae2
SH		 261
262 /* Turn on "driver loaded" LED */
263 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
ae306cca 264}
5afa0a9c 265
ae306cca
SH		 266static void sky2_power_aux(struct sky2_hw *hw)
267{
268 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
269 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
270 else
271 /* enable bits are inverted */
272 sky2_write8(hw, B2_Y2_CLK_GATE,
273 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
274 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
275 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
276
c23ddf8f
SH		 277 /* switch power to VAUX if supported and PME from D3cold */
278 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
279 pci_pme_capable(hw->pdev, PCI_D3cold))
ae306cca
SH		 280 sky2_write8(hw, B0_POWER_CTRL,
281 (PC_VAUX_ENA | PC_VCC_ENA |
282 PC_VAUX_ON | PC_VCC_OFF));
10547ae2
SH		 283
284 /* turn off "driver loaded LED" */
285 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
5afa0a9c 286}
287
d3bcfbeb 288static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 289{
290 u16 reg;
291
292 /* disable all GMAC IRQ's */
293 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 294
cd28ab6a
SH		 295 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
296 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
298 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
299
300 reg = gma_read16(hw, port, GM_RX_CTRL);
301 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
302 gma_write16(hw, port, GM_RX_CTRL, reg);
303}
304
16ad91e1
SH		 305/* flow control to advertise bits */
306static const u16 copper_fc_adv[] = {
307 [FC_NONE] = 0,
308 [FC_TX] = PHY_M_AN_ASP,
309 [FC_RX] = PHY_M_AN_PC,
310 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
311};
312
313/* flow control to advertise bits when using 1000BaseX */
314static const u16 fiber_fc_adv[] = {
df3fe1f3 315 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 316 [FC_TX] = PHY_M_P_ASYM_MD_X,
317 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 318 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 319};
320
321/* flow control to GMA disable bits */
322static const u16 gm_fc_disable[] = {
323 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
324 [FC_TX] = GM_GPCR_FC_RX_DIS,
325 [FC_RX] = GM_GPCR_FC_TX_DIS,
326 [FC_BOTH] = 0,
327};
328
329
cd28ab6a
SH		 330static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
331{
332 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 333 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 334
0ea065e5 335 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 336 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 337 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
338
339 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 340 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 341 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
342
53419c68 343 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 344 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 345 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 346 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
347 else
53419c68
SH		 348 /* set master & slave downshift counter to 1x */
349 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 350
351 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
352 }
353
354 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 355 if (sky2_is_copper(hw)) {
05745c4a 356 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 357 /* enable automatic crossover */
358 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 359
360 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
361 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
362 u16 spec;
363
364 /* Enable Class A driver for FE+ A0 */
365 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
366 spec |= PHY_M_FESC_SEL_CL_A;
367 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
368 }
cd28ab6a
SH		 369 } else {
370 /* disable energy detect */
371 ctrl &= ~PHY_M_PC_EN_DET_MSK;
372
373 /* enable automatic crossover */
374 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
375
53419c68 376 /* downshift on PHY 88E1112 and 88E1149 is changed */
8e95a202
JP		 377 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
378 (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 379 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 380 ctrl &= ~PHY_M_PC_DSC_MSK;
381 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
382 }
383 }
cd28ab6a
SH		 384 } else {
385 /* workaround for deviation #4.88 (CRC errors) */
386 /* disable Automatic Crossover */
387
388 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 389 }
cd28ab6a 390
b89165f2
SH		 391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392
393 /* special setup for PHY 88E1112 Fiber */
ea76e635 394 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 395 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 396
b89165f2
SH		 397 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
398 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
399 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
400 ctrl &= ~PHY_M_MAC_MD_MSK;
401 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
402 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
403
404 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 405 /* select page 1 to access Fiber registers */
406 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 407
408 /* for SFP-module set SIGDET polarity to low */
409 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
410 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 411 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 412 }
b89165f2
SH		 413
414 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 415 }
416
7800fddc 417 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 418 ct1000 = 0;
419 adv = PHY_AN_CSMA;
2eaba1a2 420 reg = 0;
cd28ab6a 421
0ea065e5 422 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 423 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 424 if (sky2->advertising & ADVERTISED_1000baseT_Full)
425 ct1000 |= PHY_M_1000C_AFD;
426 if (sky2->advertising & ADVERTISED_1000baseT_Half)
427 ct1000 |= PHY_M_1000C_AHD;
428 if (sky2->advertising & ADVERTISED_100baseT_Full)
429 adv |= PHY_M_AN_100_FD;
430 if (sky2->advertising & ADVERTISED_100baseT_Half)
431 adv |= PHY_M_AN_100_HD;
432 if (sky2->advertising & ADVERTISED_10baseT_Full)
433 adv |= PHY_M_AN_10_FD;
434 if (sky2->advertising & ADVERTISED_10baseT_Half)
435 adv |= PHY_M_AN_10_HD;
709c6e7b 436
b89165f2
SH		 437 } else { /* special defines for FIBER (88E1040S only) */
438 if (sky2->advertising & ADVERTISED_1000baseT_Full)
439 adv |= PHY_M_AN_1000X_AFD;
440 if (sky2->advertising & ADVERTISED_1000baseT_Half)
441 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 442 }
cd28ab6a
SH		 443
444 /* Restart Auto-negotiation */
445 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
446 } else {
447 /* forced speed/duplex settings */
448 ct1000 = PHY_M_1000C_MSE;
449
0ea065e5
SH		 450 /* Disable auto update for duplex flow control and duplex */
451 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 452
453 switch (sky2->speed) {
454 case SPEED_1000:
455 ctrl |= PHY_CT_SP1000;
2eaba1a2 456 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 457 break;
458 case SPEED_100:
459 ctrl |= PHY_CT_SP100;
2eaba1a2 460 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 461 break;
462 }
463
2eaba1a2
SH		 464 if (sky2->duplex == DUPLEX_FULL) {
465 reg |= GM_GPCR_DUP_FULL;
466 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 467 } else if (sky2->speed < SPEED_1000)
468 sky2->flow_mode = FC_NONE;
0ea065e5 469 }
2eaba1a2 470
0ea065e5
SH		 471 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
472 if (sky2_is_copper(hw))
473 adv |= copper_fc_adv[sky2->flow_mode];
474 else
475 adv |= fiber_fc_adv[sky2->flow_mode];
476 } else {
477 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 478 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 479
480 /* Forward pause packets to GMAC? */
16ad91e1 481 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 482 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
483 else
484 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 485 }
486
2eaba1a2
SH		 487 gma_write16(hw, port, GM_GP_CTRL, reg);
488
05745c4a 489 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 490 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
491
492 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
493 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
494
495 /* Setup Phy LED's */
496 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
497 ledover = 0;
498
499 switch (hw->chip_id) {
500 case CHIP_ID_YUKON_FE:
501 /* on 88E3082 these bits are at 11..9 (shifted left) */
502 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
503
504 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
505
506 /* delete ACT LED control bits */
507 ctrl &= ~PHY_M_FELP_LED1_MSK;
508 /* change ACT LED control to blink mode */
509 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
510 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
511 break;
512
05745c4a
SH		 513 case CHIP_ID_YUKON_FE_P:
514 /* Enable Link Partner Next Page */
515 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
516 ctrl |= PHY_M_PC_ENA_LIP_NP;
517
518 /* disable Energy Detect and enable scrambler */
519 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
520 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
521
522 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
523 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
524 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
525 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
526
527 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
528 break;
529
cd28ab6a 530 case CHIP_ID_YUKON_XL:
793b883e 531 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 532
533 /* select page 3 to access LED control register */
534 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
535
536 /* set LED Function Control register */
ed6d32c7
SH		 537 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
538 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
539 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
540 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
541 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 542
543 /* set Polarity Control register */
544 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 545 (PHY_M_POLC_LS1_P_MIX(4) |
546 PHY_M_POLC_IS0_P_MIX(4) |
547 PHY_M_POLC_LOS_CTRL(2) |
548 PHY_M_POLC_INIT_CTRL(2) |
549 PHY_M_POLC_STA1_CTRL(2) |
550 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 551
552 /* restore page register */
793b883e 553 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 554 break;
93745494 555
ed6d32c7 556 case CHIP_ID_YUKON_EC_U:
93745494 557 case CHIP_ID_YUKON_EX:
ed4d4161 558 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 559 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
560
561 /* select page 3 to access LED control register */
562 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
563
564 /* set LED Function Control register */
565 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
566 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
567 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
568 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
569 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
570
571 /* set Blink Rate in LED Timer Control Register */
572 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
573 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
574 /* restore page register */
575 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
576 break;
cd28ab6a
SH		 577
578 default:
579 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
580 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 581
cd28ab6a 582 /* turn off the Rx LED (LED_RX) */
a84d0a3d 583 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 584 }
585
0ce8b98d 586 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 587 /* apply fixes in PHY AFE */
ed6d32c7
SH		 588 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
589
977bdf06 590 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 591 gm_phy_write(hw, port, 0x18, 0xaa99);
592 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 593
0ce8b98d
SH		 594 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
595 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
596 gm_phy_write(hw, port, 0x18, 0xa204);
597 gm_phy_write(hw, port, 0x17, 0x2002);
598 }
977bdf06
SH		 599
600 /* set page register to 0 */
9467a8fc 601 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 602 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
603 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
604 /* apply workaround for integrated resistors calibration */
605 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
606 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
0f5aac70
SH		 607 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
608 /* apply fixes in PHY AFE */
609 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
610
611 /* apply RDAC termination workaround */
612 gm_phy_write(hw, port, 24, 0x2800);
613 gm_phy_write(hw, port, 23, 0x2001);
614
615 /* set page register back to 0 */
616 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
e1a74b37
SH		 617 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
618 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 619 /* no effect on Yukon-XL */
977bdf06 620 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 621
8e95a202
JP		 622 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
623 sky2->speed == SPEED_100) {
977bdf06 624 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 625 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 626 }
cd28ab6a 627
977bdf06
SH		 628 if (ledover)
629 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
630
631 }
2eaba1a2 632
d571b694 633 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 634 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 635 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
636 else
637 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
638}
639
b96936da
SH		 640static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
641static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
642
643static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb 644{
645 u32 reg1;
d3bcfbeb 646
a40ccc68 647 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 648 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 649 reg1 &= ~phy_power[port];
d3bcfbeb 650
b96936da 651 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 652 reg1 |= coma_mode[port];
653
b32f40c4 654 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 655 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
82637e80 656 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 657
658 if (hw->chip_id == CHIP_ID_YUKON_FE)
659 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
660 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
661 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 662}
167f53d0 663
b96936da
SH		 664static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
665{
666 u32 reg1;
db99b988
SH		 667 u16 ctrl;
668
669 /* release GPHY Control reset */
670 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
671
672 /* release GMAC reset */
673 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
674
675 if (hw->flags & SKY2_HW_NEWER_PHY) {
676 /* select page 2 to access MAC control register */
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
678
679 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
680 /* allow GMII Power Down */
681 ctrl &= ~PHY_M_MAC_GMIF_PUP;
682 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
683
684 /* set page register back to 0 */
685 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
686 }
687
688 /* setup General Purpose Control Register */
689 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 690 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
691 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
692 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 693
694 if (hw->chip_id != CHIP_ID_YUKON_EC) {
695 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 696 /* select page 2 to access MAC control register */
697 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 698
e484d5f5 699 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 700 /* enable Power Down */
701 ctrl |= PHY_M_PC_POW_D_ENA;
702 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 703
704 /* set page register back to 0 */
705 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 706 }
707
708 /* set IEEE compatible Power Down Mode (dev. #4.99) */
709 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
710 }
b96936da 711
a40ccc68 712 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b96936da 713 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 714 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da 715 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 716 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb 717}
718
1b537565
SH		 719/* Force a renegotiation */
720static void sky2_phy_reinit(struct sky2_port *sky2)
721{
e07b1aa8 722 spin_lock_bh(&sky2->phy_lock);
1b537565 723 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 724 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 725}
726
e3173832
SH		 727/* Put device in state to listen for Wake On Lan */
728static void sky2_wol_init(struct sky2_port *sky2)
729{
730 struct sky2_hw *hw = sky2->hw;
731 unsigned port = sky2->port;
732 enum flow_control save_mode;
733 u16 ctrl;
734 u32 reg1;
735
736 /* Bring hardware out of reset */
737 sky2_write16(hw, B0_CTST, CS_RST_CLR);
738 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
739
740 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
741 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
742
743 /* Force to 10/100
744 * sky2_reset will re-enable on resume
745 */
746 save_mode = sky2->flow_mode;
747 ctrl = sky2->advertising;
748
749 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
750 sky2->flow_mode = FC_NONE;
b96936da
SH		 751
752 spin_lock_bh(&sky2->phy_lock);
753 sky2_phy_power_up(hw, port);
754 sky2_phy_init(hw, port);
755 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 756
757 sky2->flow_mode = save_mode;
758 sky2->advertising = ctrl;
759
760 /* Set GMAC to no flow control and auto update for speed/duplex */
761 gma_write16(hw, port, GM_GP_CTRL,
762 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
763 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
764
765 /* Set WOL address */
766 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
767 sky2->netdev->dev_addr, ETH_ALEN);
768
769 /* Turn on appropriate WOL control bits */
770 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
771 ctrl = 0;
772 if (sky2->wol & WAKE_PHY)
773 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
774 else
775 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
776
777 if (sky2->wol & WAKE_MAGIC)
778 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
779 else
a419aef8 780 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
e3173832
SH		 781
782 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
783 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
784
785 /* Turn on legacy PCI-Express PME mode */
b32f40c4 786 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 787 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 788 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 789
790 /* block receiver */
791 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
792
793}
794
69161611
SH		 795static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
796{
05745c4a
SH		 797 struct net_device *dev = hw->dev[port];
798
ed4d4161
SH		 799 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
800 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
877c8570 801 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
ed4d4161
SH		 802 /* Yukon-Extreme B0 and further Extreme devices */
803 /* enable Store & Forward mode for TX */
05745c4a 804
ed4d4161
SH		 805 if (dev->mtu <= ETH_DATA_LEN)
806 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
807 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 808
ed4d4161
SH		 809 else
810 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
811 TX_JUMBO_ENA| TX_STFW_ENA);
812 } else {
813 if (dev->mtu <= ETH_DATA_LEN)
814 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
815 else {
816 /* set Tx GMAC FIFO Almost Empty Threshold */
817 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
818 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 819
ed4d4161
SH		 820 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
821
822 /* Can't do offload because of lack of store/forward */
823 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
824 }
69161611
SH		 825 }
826}
827
cd28ab6a
SH		 828static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
829{
830 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
831 u16 reg;
25cccecc 832 u32 rx_reg;
cd28ab6a
SH		 833 int i;
834 const u8 *addr = hw->dev[port]->dev_addr;
835
f350339c
SH		 836 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
837 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 838
839 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
840
793b883e 841 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 842 /* WA DEV_472 -- looks like crossed wires on port 2 */
843 /* clear GMAC 1 Control reset */
844 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
845 do {
846 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
847 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
848 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
849 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
850 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
851 }
852
793b883e 853 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 854
2eaba1a2
SH		 855 /* Enable Transmit FIFO Underrun */
856 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
857
e07b1aa8 858 spin_lock_bh(&sky2->phy_lock);
b96936da 859 sky2_phy_power_up(hw, port);
cd28ab6a 860 sky2_phy_init(hw, port);
e07b1aa8 861 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 862
863 /* MIB clear */
864 reg = gma_read16(hw, port, GM_PHY_ADDR);
865 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
866
43f2f104
SH		 867 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
868 gma_read16(hw, port, i);
cd28ab6a
SH		 869 gma_write16(hw, port, GM_PHY_ADDR, reg);
870
871 /* transmit control */
872 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
873
874 /* receive control reg: unicast + multicast + no FCS */
875 gma_write16(hw, port, GM_RX_CTRL,
793b883e 876 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 877
878 /* transmit flow control */
879 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
880
881 /* transmit parameter */
882 gma_write16(hw, port, GM_TX_PARAM,
883 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
884 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
885 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
886 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
887
888 /* serial mode register */
889 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 890 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 891
6b1a3aef 892 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 893 reg |= GM_SMOD_JUMBO_ENA;
894
895 gma_write16(hw, port, GM_SERIAL_MODE, reg);
896
cd28ab6a
SH		 897 /* virtual address for data */
898 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
899
793b883e
SH		 900 /* physical address: used for pause frames */
901 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
902
903 /* ignore counter overflows */
cd28ab6a
SH		 904 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
905 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
906 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
907
908 /* Configure Rx MAC FIFO */
909 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 910 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 911 if (hw->chip_id == CHIP_ID_YUKON_EX ||
912 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 913 rx_reg |= GMF_RX_OVER_ON;
69161611 914
25cccecc 915 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 916
798fdd07
SH		 917 if (hw->chip_id == CHIP_ID_YUKON_XL) {
918 /* Hardware errata - clear flush mask */
919 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
920 } else {
921 /* Flush Rx MAC FIFO on any flow control or error */
922 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
923 }
cd28ab6a 924
8df9a876 925 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 926 reg = RX_GMF_FL_THR_DEF + 1;
927 /* Another magic mystery workaround from sk98lin */
928 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
929 hw->chip_rev == CHIP_REV_YU_FE2_A0)
930 reg = 0x178;
931 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 932
933 /* Configure Tx MAC FIFO */
934 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
935 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 936
e0c28116 937 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 938 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
d6b54d24 939 /* Pause threshold is scaled by 8 in bytes */
8e95a202
JP		 940 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
941 hw->chip_rev == CHIP_REV_YU_FE2_A0)
d6b54d24
SH		 942 reg = 1568 / 8;
943 else
944 reg = 1024 / 8;
945 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
946 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
b628ed98 947
69161611 948 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 949 }
950
e970d1f8
SH		 951 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
952 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
953 /* disable dynamic watermark */
954 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
955 reg &= ~TX_DYN_WM_ENA;
956 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
957 }
cd28ab6a
SH		 958}
959
67712901
SH		 960/* Assign Ram Buffer allocation to queue */
961static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 962{
67712901
SH		 963 u32 end;
964
965 /* convert from K bytes to qwords used for hw register */
966 start *= 1024/8;
967 space *= 1024/8;
968 end = start + space - 1;
793b883e 969
cd28ab6a
SH		 970 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
971 sky2_write32(hw, RB_ADDR(q, RB_START), start);
972 sky2_write32(hw, RB_ADDR(q, RB_END), end);
973 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
974 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
975
976 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 977 u32 tp = space - space/4;
793b883e 978
1c28f6ba
SH		 979 /* On receive queue's set the thresholds
980 * give receiver priority when > 3/4 full
981 * send pause when down to 2K
982 */
983 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
984 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 985
1c28f6ba
SH		 986 tp = space - 2048/8;
987 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
988 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 989 } else {
990 /* Enable store & forward on Tx queue's because
991 * Tx FIFO is only 1K on Yukon
992 */
993 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
994 }
995
996 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 997 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 998}
999
cd28ab6a 1000/* Setup Bus Memory Interface */
af4ed7e6 1001static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 1002{
1003 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1004 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1005 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 1006 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 1007}
1008
cd28ab6a
SH		 1009/* Setup prefetch unit registers. This is the interface between
1010 * hardware and driver list elements
1011 */
8cc048e3 1012static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 1013 dma_addr_t addr, u32 last)
cd28ab6a 1014{
cd28ab6a
SH		 1015 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1016 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 1017 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1018 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 1019 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1020 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1021
1022 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1023}
1024
9b289c33 1025static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1026{
9b289c33 1027 struct sky2_tx_le *le = sky2->tx_le + *slot;
793b883e 1028
ee5f68fe 1029 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
291ea614 1030 le->ctrl = 0;
793b883e
SH		 1031 return le;
1032}
cd28ab6a 1033
88f5f0ca
SH		 1034static void tx_init(struct sky2_port *sky2)
1035{
1036 struct sky2_tx_le *le;
1037
1038 sky2->tx_prod = sky2->tx_cons = 0;
1039 sky2->tx_tcpsum = 0;
1040 sky2->tx_last_mss = 0;
1041
9b289c33 1042 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1043 le->addr = 0;
1044 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1045 sky2->tx_last_upper = 0;
88f5f0ca
SH		 1046}
1047
290d4de5
SH		 1048/* Update chip's next pointer */
1049static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1050{
50432cb5 1051 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1052 wmb();
50432cb5
SH		 1053 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1054
1055 /* Synchronize I/O on since next processor may write to tail */
1056 mmiowb();
cd28ab6a
SH		 1057}
1058
793b883e 1059
cd28ab6a
SH		 1060static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1061{
1062 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1063 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1064 le->ctrl = 0;
cd28ab6a
SH		 1065 return le;
1066}
1067
14d0263f
SH		 1068/* Build description to hardware for one receive segment */
1069static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1070 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1071{
1072 struct sky2_rx_le *le;
1073
86c6887e 1074 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1075 le = sky2_next_rx(sky2);
86c6887e 1076 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1077 le->opcode = OP_ADDR64 | HW_OWNER;
1078 }
793b883e 1079
cd28ab6a 1080 le = sky2_next_rx(sky2);
d6e74b6b 1081 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1082 le->length = cpu_to_le16(len);
14d0263f 1083 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1084}
1085
14d0263f
SH		 1086/* Build description to hardware for one possibly fragmented skb */
1087static void sky2_rx_submit(struct sky2_port *sky2,
1088 const struct rx_ring_info *re)
1089{
1090 int i;
1091
1092 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1093
1094 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1095 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1096}
1097
1098
454e6cb6 1099static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1100 unsigned size)
1101{
1102 struct sk_buff *skb = re->skb;
1103 int i;
1104
1105 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
454e6cb6
SH		 1106 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1107 return -EIO;
1108
14d0263f
SH		 1109 pci_unmap_len_set(re, data_size, size);
1110
1111 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1112 re->frag_addr[i] = pci_map_page(pdev,
1113 skb_shinfo(skb)->frags[i].page,
1114 skb_shinfo(skb)->frags[i].page_offset,
1115 skb_shinfo(skb)->frags[i].size,
1116 PCI_DMA_FROMDEVICE);
454e6cb6 1117 return 0;
14d0263f
SH		 1118}
1119
1120static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1121{
1122 struct sk_buff *skb = re->skb;
1123 int i;
1124
1125 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1126 PCI_DMA_FROMDEVICE);
1127
1128 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1129 pci_unmap_page(pdev, re->frag_addr[i],
1130 skb_shinfo(skb)->frags[i].size,
1131 PCI_DMA_FROMDEVICE);
1132}
793b883e 1133
cd28ab6a
SH		 1134/* Tell chip where to start receive checksum.
1135 * Actually has two checksums, but set both same to avoid possible byte
1136 * order problems.
1137 */
793b883e 1138static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1139{
ea76e635 1140 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1141
ea76e635
SH		 1142 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1143 le->ctrl = 0;
1144 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1145
ea76e635
SH		 1146 sky2_write32(sky2->hw,
1147 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
0ea065e5
SH		 1148 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1149 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1150}
1151
6b1a3aef 1152/*
1153 * The RX Stop command will not work for Yukon-2 if the BMU does not
1154 * reach the end of packet and since we can't make sure that we have
1155 * incoming data, we must reset the BMU while it is not doing a DMA
1156 * transfer. Since it is possible that the RX path is still active,
1157 * the RX RAM buffer will be stopped first, so any possible incoming
1158 * data will not trigger a DMA. After the RAM buffer is stopped, the
1159 * BMU is polled until any DMA in progress is ended and only then it
1160 * will be reset.
1161 */
1162static void sky2_rx_stop(struct sky2_port *sky2)
1163{
1164 struct sky2_hw *hw = sky2->hw;
1165 unsigned rxq = rxqaddr[sky2->port];
1166 int i;
1167
1168 /* disable the RAM Buffer receive queue */
1169 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1170
1171 for (i = 0; i < 0xffff; i++)
1172 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1173 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1174 goto stopped;
1175
1176 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1177 sky2->netdev->name);
1178stopped:
1179 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1180
1181 /* reset the Rx prefetch unit */
1182 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1183 mmiowb();
6b1a3aef 1184}
793b883e 1185
d571b694 1186/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1187static void sky2_rx_clean(struct sky2_port *sky2)
1188{
1189 unsigned i;
1190
1191 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1192 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1193 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1194
1195 if (re->skb) {
14d0263f 1196 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1197 kfree_skb(re->skb);
1198 re->skb = NULL;
1199 }
1200 }
1201}
1202
ef743d33 1203/* Basic MII support */
1204static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1205{
1206 struct mii_ioctl_data *data = if_mii(ifr);
1207 struct sky2_port *sky2 = netdev_priv(dev);
1208 struct sky2_hw *hw = sky2->hw;
1209 int err = -EOPNOTSUPP;
1210
1211 if (!netif_running(dev))
1212 return -ENODEV; /* Phy still in reset */
1213
d89e1343 1214 switch (cmd) {
ef743d33 1215 case SIOCGMIIPHY:
1216 data->phy_id = PHY_ADDR_MARV;
1217
1218 /* fallthru */
1219 case SIOCGMIIREG: {
1220 u16 val = 0;
91c86df5 1221
e07b1aa8 1222 spin_lock_bh(&sky2->phy_lock);
ef743d33 1223 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1224 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1225
ef743d33 1226 data->val_out = val;
1227 break;
1228 }
1229
1230 case SIOCSMIIREG:
e07b1aa8 1231 spin_lock_bh(&sky2->phy_lock);
ef743d33 1232 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1233 data->val_in);
e07b1aa8 1234 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1235 break;
1236 }
1237 return err;
1238}
1239
d1f13708 1240#ifdef SKY2_VLAN_TAG_USED
d494eacd 1241static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1242{
d494eacd 1243 if (onoff) {
3d4e66f5
SH		 1244 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1245 RX_VLAN_STRIP_ON);
1246 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1247 TX_VLAN_TAG_ON);
1248 } else {
1249 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1250 RX_VLAN_STRIP_OFF);
1251 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1252 TX_VLAN_TAG_OFF);
1253 }
d494eacd
SH		 1254}
1255
1256static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1257{
1258 struct sky2_port *sky2 = netdev_priv(dev);
1259 struct sky2_hw *hw = sky2->hw;
1260 u16 port = sky2->port;
1261
1262 netif_tx_lock_bh(dev);
1263 napi_disable(&hw->napi);
1264
1265 sky2->vlgrp = grp;
1266 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1267
d1d08d12 1268 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1269 napi_enable(&hw->napi);
2bb8c262 1270 netif_tx_unlock_bh(dev);
d1f13708 1271}
1272#endif
1273
bd1c6869
SH		 1274/* Amount of required worst case padding in rx buffer */
1275static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1276{
1277 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1278}
1279
82788c7a 1280/*
14d0263f
SH		 1281 * Allocate an skb for receiving. If the MTU is large enough
1282 * make the skb non-linear with a fragment list of pages.
82788c7a 1283 */
14d0263f 1284static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1285{
1286 struct sk_buff *skb;
14d0263f 1287 int i;
82788c7a 1288
724b6942
SH		 1289 skb = netdev_alloc_skb(sky2->netdev,
1290 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
bd1c6869
SH		 1291 if (!skb)
1292 goto nomem;
1293
39dbd958 1294 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1295 unsigned char *start;
1296 /*
1297 * Workaround for a bug in FIFO that cause hang
1298 * if the FIFO if the receive buffer is not 64 byte aligned.
1299 * The buffer returned from netdev_alloc_skb is
1300 * aligned except if slab debugging is enabled.
1301 */
f03b8654
SH		 1302 start = PTR_ALIGN(skb->data, 8);
1303 skb_reserve(skb, start - skb->data);
bd1c6869 1304 } else
f03b8654 1305 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1306
1307 for (i = 0; i < sky2->rx_nfrags; i++) {
1308 struct page *page = alloc_page(GFP_ATOMIC);
1309
1310 if (!page)
1311 goto free_partial;
1312 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1313 }
1314
1315 return skb;
14d0263f
SH		 1316free_partial:
1317 kfree_skb(skb);
1318nomem:
1319 return NULL;
82788c7a
SH		 1320}
1321
55c9dd35
SH		 1322static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1323{
1324 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1325}
1326
cd28ab6a
SH		 1327/*
1328 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1329 * Normal case this ends up creating one list element for skb
1330 * in the receive ring. Worst case if using large MTU and each
1331 * allocation falls on a different 64 bit region, that results
1332 * in 6 list elements per ring entry.
1333 * One element is used for checksum enable/disable, and one
1334 * extra to avoid wrap.
cd28ab6a 1335 */
6b1a3aef 1336static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1337{
6b1a3aef 1338 struct sky2_hw *hw = sky2->hw;
14d0263f 1339 struct rx_ring_info *re;
6b1a3aef 1340 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1341 unsigned i, size, thresh;
cd28ab6a 1342
6b1a3aef 1343 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1344 sky2_qset(hw, rxq);
977bdf06 1345
c3905bc4
SH		 1346 /* On PCI express lowering the watermark gives better performance */
1347 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1348 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1349
1350 /* These chips have no ram buffer?
1351 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1352 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
8e95a202
JP		 1353 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 ||
1354 hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1355 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1356
6b1a3aef 1357 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1358
ea76e635
SH		 1359 if (!(hw->flags & SKY2_HW_NEW_LE))
1360 rx_set_checksum(sky2);
14d0263f
SH		 1361
1362 /* Space needed for frame data + headers rounded up */
f957da2a 1363 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1364
1365 /* Stopping point for hardware truncation */
1366 thresh = (size - 8) / sizeof(u32);
1367
5f06eba4 1368 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1369 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1370
5f06eba4
SH		 1371 /* Compute residue after pages */
1372 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1373
5f06eba4
SH		 1374 /* Optimize to handle small packets and headers */
1375 if (size < copybreak)
1376 size = copybreak;
1377 if (size < ETH_HLEN)
1378 size = ETH_HLEN;
14d0263f 1379
14d0263f
SH		 1380 sky2->rx_data_size = size;
1381
1382 /* Fill Rx ring */
793b883e 1383 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1384 re = sky2->rx_ring + i;
cd28ab6a 1385
14d0263f 1386 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1387 if (!re->skb)
1388 goto nomem;
1389
454e6cb6
SH		 1390 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1391 dev_kfree_skb(re->skb);
1392 re->skb = NULL;
1393 goto nomem;
1394 }
1395
14d0263f 1396 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1397 }
1398
a1433ac4
SH		 1399 /*
1400 * The receiver hangs if it receives frames larger than the
1401 * packet buffer. As a workaround, truncate oversize frames, but
1402 * the register is limited to 9 bits, so if you do frames > 2052
1403 * you better get the MTU right!
1404 */
a1433ac4
SH		 1405 if (thresh > 0x1ff)
1406 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1407 else {
1408 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1409 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1410 }
1411
6b1a3aef 1412 /* Tell chip about available buffers */
55c9dd35 1413 sky2_rx_update(sky2, rxq);
877c8570
SH		 1414
1415 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1416 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1417 /*
1418 * Disable flushing of non ASF packets;
1419 * must be done after initializing the BMUs;
1420 * drivers without ASF support should do this too, otherwise
1421 * it may happen that they cannot run on ASF devices;
1422 * remember that the MAC FIFO isn't reset during initialization.
1423 */
1424 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1425 }
1426
1427 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1428 /* Enable RX Home Address & Routing Header checksum fix */
1429 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1430 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1431
1432 /* Enable TX Home Address & Routing Header checksum fix */
1433 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1434 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1435 }
1436
1437
1438
cd28ab6a
SH		 1439 return 0;
1440nomem:
1441 sky2_rx_clean(sky2);
1442 return -ENOMEM;
1443}
1444
90bbebb4
MM		 1445static int sky2_alloc_buffers(struct sky2_port *sky2)
1446{
1447 struct sky2_hw *hw = sky2->hw;
1448
1449 /* must be power of 2 */
1450 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1451 sky2->tx_ring_size *
1452 sizeof(struct sky2_tx_le),
1453 &sky2->tx_le_map);
1454 if (!sky2->tx_le)
1455 goto nomem;
1456
1457 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1458 GFP_KERNEL);
1459 if (!sky2->tx_ring)
1460 goto nomem;
1461
1462 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1463 &sky2->rx_le_map);
1464 if (!sky2->rx_le)
1465 goto nomem;
1466 memset(sky2->rx_le, 0, RX_LE_BYTES);
1467
1468 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1469 GFP_KERNEL);
1470 if (!sky2->rx_ring)
1471 goto nomem;
1472
1473 return 0;
1474nomem:
1475 return -ENOMEM;
1476}
1477
1478static void sky2_free_buffers(struct sky2_port *sky2)
1479{
1480 struct sky2_hw *hw = sky2->hw;
1481
1482 if (sky2->rx_le) {
1483 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1484 sky2->rx_le, sky2->rx_le_map);
1485 sky2->rx_le = NULL;
1486 }
1487 if (sky2->tx_le) {
1488 pci_free_consistent(hw->pdev,
1489 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1490 sky2->tx_le, sky2->tx_le_map);
1491 sky2->tx_le = NULL;
1492 }
1493 kfree(sky2->tx_ring);
1494 kfree(sky2->rx_ring);
1495
1496 sky2->tx_ring = NULL;
1497 sky2->rx_ring = NULL;
1498}
1499
cd28ab6a
SH		 1500/* Bring up network interface. */
1501static int sky2_up(struct net_device *dev)
1502{
1503 struct sky2_port *sky2 = netdev_priv(dev);
1504 struct sky2_hw *hw = sky2->hw;
1505 unsigned port = sky2->port;
e0c28116 1506 u32 imask, ramsize;
90bbebb4 1507 int cap, err;
843a46f4 1508 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1509
ee7abb04
SH		 1510 /*
1511 * On dual port PCI-X card, there is an problem where status
1512 * can be received out of order due to split transactions
843a46f4 1513 */
ee7abb04
SH		 1514 if (otherdev && netif_running(otherdev) &&
1515 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1516 u16 cmd;
1517
b32f40c4 1518 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1519 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1520 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1521
ee7abb04 1522 }
843a46f4 1523
55d7b4e6
SH		 1524 netif_carrier_off(dev);
1525
90bbebb4
MM		 1526 err = sky2_alloc_buffers(sky2);
1527 if (err)
cd28ab6a 1528 goto err_out;
88f5f0ca
SH		 1529
1530 tx_init(sky2);
cd28ab6a 1531
cd28ab6a
SH		 1532 sky2_mac_init(hw, port);
1533
e0c28116
SH		 1534 /* Register is number of 4K blocks on internal RAM buffer. */
1535 ramsize = sky2_read8(hw, B2_E_0) * 4;
1536 if (ramsize > 0) {
67712901 1537 u32 rxspace;
cd28ab6a 1538
e0c28116 1539 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1540 if (ramsize < 16)
1541 rxspace = ramsize / 2;
1542 else
1543 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1544
67712901
SH		 1545 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1546 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1547
1548 /* Make sure SyncQ is disabled */
1549 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1550 RB_RST_SET);
1551 }
793b883e 1552
af4ed7e6 1553 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1554
69161611
SH		 1555 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1556 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1557 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1558
977bdf06 1559 /* Set almost empty threshold */
8e95a202
JP		 1560 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1561 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1562 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1563
6b1a3aef 1564 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
ee5f68fe 1565 sky2->tx_ring_size - 1);
cd28ab6a 1566
d494eacd
SH		 1567#ifdef SKY2_VLAN_TAG_USED
1568 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1569#endif
1570
6b1a3aef 1571 err = sky2_rx_start(sky2);
6de16237 1572 if (err)
cd28ab6a
SH		 1573 goto err_out;
1574
cd28ab6a 1575 /* Enable interrupts from phy/mac for port */
e07b1aa8 1576 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1577 imask |= portirq_msk[port];
e07b1aa8 1578 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1579 sky2_read32(hw, B0_IMSK);
e07b1aa8 1580
a11da890
AD		 1581 if (netif_msg_ifup(sky2))
1582 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
af18d8b8 1583
cd28ab6a
SH		 1584 return 0;
1585
1586err_out:
90bbebb4 1587 sky2_free_buffers(sky2);
cd28ab6a
SH		 1588 return err;
1589}
1590
793b883e 1591/* Modular subtraction in ring */
ee5f68fe 1592static inline int tx_inuse(const struct sky2_port *sky2)
793b883e 1593{
ee5f68fe 1594 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
793b883e 1595}
cd28ab6a 1596
793b883e
SH		 1597/* Number of list elements available for next tx */
1598static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1599{
ee5f68fe 1600 return sky2->tx_pending - tx_inuse(sky2);
cd28ab6a
SH		 1601}
1602
793b883e 1603/* Estimate of number of transmit list elements required */
28bd181a 1604static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1605{
793b883e
SH		 1606 unsigned count;
1607
07e31637
SH		 1608 count = (skb_shinfo(skb)->nr_frags + 1)
1609 * (sizeof(dma_addr_t) / sizeof(u32));
793b883e 1610
89114afd 1611 if (skb_is_gso(skb))
793b883e 1612 ++count;
07e31637
SH		 1613 else if (sizeof(dma_addr_t) == sizeof(u32))
1614 ++count; /* possible vlan */
793b883e 1615
84fa7933 1616 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1617 ++count;
1618
1619 return count;
cd28ab6a
SH		 1620}
1621
f6815077 1622static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
6b84daca
SH		 1623{
1624 if (re->flags & TX_MAP_SINGLE)
1625 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1626 pci_unmap_len(re, maplen),
1627 PCI_DMA_TODEVICE);
1628 else if (re->flags & TX_MAP_PAGE)
1629 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1630 pci_unmap_len(re, maplen),
1631 PCI_DMA_TODEVICE);
f6815077 1632 re->flags = 0;
6b84daca
SH		 1633}
1634
793b883e
SH		 1635/*
1636 * Put one packet in ring for transmit.
1637 * A single packet can generate multiple list elements, and
1638 * the number of ring elements will probably be less than the number
1639 * of list elements used.
1640 */
61357325
SH		 1641static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1642 struct net_device *dev)
cd28ab6a
SH		 1643{
1644 struct sky2_port *sky2 = netdev_priv(dev);
1645 struct sky2_hw *hw = sky2->hw;
d1f13708 1646 struct sky2_tx_le *le = NULL;
6cdbbdf3 1647 struct tx_ring_info *re;
9b289c33 1648 unsigned i, len;
cd28ab6a 1649 dma_addr_t mapping;
5dce95e5
SH		 1650 u32 upper;
1651 u16 slot;
cd28ab6a
SH		 1652 u16 mss;
1653 u8 ctrl;
1654
2bb8c262
SH		 1655 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1656 return NETDEV_TX_BUSY;
cd28ab6a 1657
cd28ab6a
SH		 1658 len = skb_headlen(skb);
1659 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1660
454e6cb6
SH		 1661 if (pci_dma_mapping_error(hw->pdev, mapping))
1662 goto mapping_error;
1663
9b289c33 1664 slot = sky2->tx_prod;
454e6cb6
SH		 1665 if (unlikely(netif_msg_tx_queued(sky2)))
1666 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
9b289c33 1667 dev->name, slot, skb->len);
454e6cb6 1668
86c6887e 1669 /* Send high bits if needed */
5dce95e5
SH		 1670 upper = upper_32_bits(mapping);
1671 if (upper != sky2->tx_last_upper) {
9b289c33 1672 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1673 le->addr = cpu_to_le32(upper);
1674 sky2->tx_last_upper = upper;
793b883e 1675 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1676 }
cd28ab6a
SH		 1677
1678 /* Check for TCP Segmentation Offload */
7967168c 1679 mss = skb_shinfo(skb)->gso_size;
793b883e 1680 if (mss != 0) {
ea76e635
SH		 1681
1682 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1683 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1684
1685 if (mss != sky2->tx_last_mss) {
9b289c33 1686 le = get_tx_le(sky2, &slot);
69161611 1687 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1688
1689 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1690 le->opcode = OP_MSS | HW_OWNER;
1691 else
1692 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1693 sky2->tx_last_mss = mss;
1694 }
cd28ab6a
SH		 1695 }
1696
cd28ab6a 1697 ctrl = 0;
d1f13708 1698#ifdef SKY2_VLAN_TAG_USED
1699 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1700 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1701 if (!le) {
9b289c33 1702 le = get_tx_le(sky2, &slot);
f65b138c 1703 le->addr = 0;
d1f13708 1704 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1705 } else
1706 le->opcode |= OP_VLAN;
1707 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1708 ctrl |= INS_VLAN;
1709 }
1710#endif
1711
1712 /* Handle TCP checksum offload */
84fa7933 1713 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1714 /* On Yukon EX (some versions) encoding change. */
ea76e635 1715 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1716 ctrl |= CALSUM; /* auto checksum */
1717 else {
1718 const unsigned offset = skb_transport_offset(skb);
1719 u32 tcpsum;
1720
1721 tcpsum = offset << 16; /* sum start */
1722 tcpsum |= offset + skb->csum_offset; /* sum write */
1723
1724 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1725 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1726 ctrl |= UDPTCP;
1727
1728 if (tcpsum != sky2->tx_tcpsum) {
1729 sky2->tx_tcpsum = tcpsum;
1730
9b289c33 1731 le = get_tx_le(sky2, &slot);
69161611
SH		 1732 le->addr = cpu_to_le32(tcpsum);
1733 le->length = 0; /* initial checksum value */
1734 le->ctrl = 1; /* one packet */
1735 le->opcode = OP_TCPLISW | HW_OWNER;
1736 }
1d179332 1737 }
cd28ab6a
SH		 1738 }
1739
6b84daca
SH		 1740 re = sky2->tx_ring + slot;
1741 re->flags = TX_MAP_SINGLE;
1742 pci_unmap_addr_set(re, mapaddr, mapping);
1743 pci_unmap_len_set(re, maplen, len);
1744
9b289c33 1745 le = get_tx_le(sky2, &slot);
d6e74b6b 1746 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1747 le->length = cpu_to_le16(len);
1748 le->ctrl = ctrl;
793b883e 1749 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1750
cd28ab6a
SH		 1751
1752 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1753 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1754
1755 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1756 frag->size, PCI_DMA_TODEVICE);
86c6887e 1757
454e6cb6
SH		 1758 if (pci_dma_mapping_error(hw->pdev, mapping))
1759 goto mapping_unwind;
1760
5dce95e5
SH		 1761 upper = upper_32_bits(mapping);
1762 if (upper != sky2->tx_last_upper) {
9b289c33 1763 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1764 le->addr = cpu_to_le32(upper);
1765 sky2->tx_last_upper = upper;
793b883e 1766 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1767 }
1768
6b84daca
SH		 1769 re = sky2->tx_ring + slot;
1770 re->flags = TX_MAP_PAGE;
1771 pci_unmap_addr_set(re, mapaddr, mapping);
1772 pci_unmap_len_set(re, maplen, frag->size);
1773
9b289c33 1774 le = get_tx_le(sky2, &slot);
d6e74b6b 1775 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1776 le->length = cpu_to_le16(frag->size);
1777 le->ctrl = ctrl;
793b883e 1778 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1779 }
6cdbbdf3 1780
6b84daca 1781 re->skb = skb;
cd28ab6a
SH		 1782 le->ctrl |= EOP;
1783
9b289c33
MM		 1784 sky2->tx_prod = slot;
1785
97bda706 1786 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1787 netif_stop_queue(dev);
b19666d9 1788
290d4de5 1789 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1790
cd28ab6a 1791 return NETDEV_TX_OK;
454e6cb6
SH		 1792
1793mapping_unwind:
ee5f68fe 1794 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
454e6cb6
SH		 1795 re = sky2->tx_ring + i;
1796
6b84daca 1797 sky2_tx_unmap(hw->pdev, re);
454e6cb6
SH		 1798 }
1799
454e6cb6
SH		 1800mapping_error:
1801 if (net_ratelimit())
1802 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1803 dev_kfree_skb(skb);
1804 return NETDEV_TX_OK;
cd28ab6a
SH		 1805}
1806
cd28ab6a 1807/*
793b883e
SH		 1808 * Free ring elements from starting at tx_cons until "done"
1809 *
481cea4a
SH		 1810 * NB:
1811 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1812 * buffers so make sure not to free skb to early.
481cea4a
SH		 1813 * 2. This may run in parallel start_xmit because the it only
1814 * looks at the tail of the queue of FIFO (tx_cons), not
1815 * the head (tx_prod)
cd28ab6a 1816 */
d11c13e7 1817static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1818{
d11c13e7 1819 struct net_device *dev = sky2->netdev;
291ea614 1820 unsigned idx;
cd28ab6a 1821
ee5f68fe 1822 BUG_ON(done >= sky2->tx_ring_size);
2224795d 1823
291ea614 1824 for (idx = sky2->tx_cons; idx != done;
ee5f68fe 1825 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
291ea614 1826 struct tx_ring_info *re = sky2->tx_ring + idx;
6b84daca 1827 struct sk_buff *skb = re->skb;
291ea614 1828
6b84daca 1829 sky2_tx_unmap(sky2->hw->pdev, re);
bd1c6869 1830
6b84daca 1831 if (skb) {
291ea614
SH		 1832 if (unlikely(netif_msg_tx_done(sky2)))
1833 printk(KERN_DEBUG "%s: tx done %u\n",
1834 dev->name, idx);
3cf26753 1835
7138a0f5 1836 dev->stats.tx_packets++;
bd1c6869
SH		 1837 dev->stats.tx_bytes += skb->len;
1838
f6815077 1839 re->skb = NULL;
724b6942 1840 dev_kfree_skb_any(skb);
2bf56fe2 1841
ee5f68fe 1842 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
cd28ab6a 1843 }
793b883e 1844 }
793b883e 1845
291ea614 1846 sky2->tx_cons = idx;
50432cb5
SH		 1847 smp_mb();
1848
9db2f1be
JP		 1849 /* Wake unless it's detached, and called e.g. from sky2_down() */
1850 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4 && netif_device_present(dev))
cd28ab6a 1851 netif_wake_queue(dev);
cd28ab6a
SH		 1852}
1853
264bb4fa 1854static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 1855{
a510996b
MM		 1856 /* Disable Force Sync bit and Enable Alloc bit */
1857 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1858 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1859
1860 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1861 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1862 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1863
1864 /* Reset the PCI FIFO of the async Tx queue */
1865 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1866 BMU_RST_SET | BMU_FIFO_RST);
1867
1868 /* Reset the Tx prefetch units */
1869 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1870 PREF_UNIT_RST_SET);
1871
1872 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1873 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1874}
1875
cd28ab6a
SH		 1876/* Network shutdown */
1877static int sky2_down(struct net_device *dev)
1878{
1879 struct sky2_port *sky2 = netdev_priv(dev);
1880 struct sky2_hw *hw = sky2->hw;
1881 unsigned port = sky2->port;
1882 u16 ctrl;
e07b1aa8 1883 u32 imask;
cd28ab6a 1884
1b537565
SH		 1885 /* Never really got started! */
1886 if (!sky2->tx_le)
1887 return 0;
1888
cd28ab6a
SH		 1889 if (netif_msg_ifdown(sky2))
1890 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1891
d104acaf
SH		 1892 /* Force flow control off */
1893 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1894
cd28ab6a
SH		 1895 /* Stop transmitter */
1896 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1897 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1898
1899 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1900 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1901
1902 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1903 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1904 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1905
1906 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1907
1908 /* Workaround shared GMAC reset */
8e95a202
JP		 1909 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1910 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1911 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1912
cd28ab6a 1913 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 1914
6c83504f
SH		 1915 /* Force any delayed status interrrupt and NAPI */
1916 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1917 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1918 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1919 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1920
a947a39d
MM		 1921 sky2_rx_stop(sky2);
1922
1923 /* Disable port IRQ */
1924 imask = sky2_read32(hw, B0_IMSK);
1925 imask &= ~portirq_msk[port];
1926 sky2_write32(hw, B0_IMSK, imask);
1927 sky2_read32(hw, B0_IMSK);
1928
6c83504f
SH		 1929 synchronize_irq(hw->pdev->irq);
1930 napi_synchronize(&hw->napi);
1931
0da6d7b3 1932 spin_lock_bh(&sky2->phy_lock);
b96936da 1933 sky2_phy_power_down(hw, port);
0da6d7b3 1934 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 1935
264bb4fa
MM		 1936 sky2_tx_reset(hw, port);
1937
481cea4a
SH		 1938 /* Free any pending frames stuck in HW queue */
1939 sky2_tx_complete(sky2, sky2->tx_prod);
1940
cd28ab6a
SH		 1941 sky2_rx_clean(sky2);
1942
90bbebb4 1943 sky2_free_buffers(sky2);
1b537565 1944
cd28ab6a
SH		 1945 return 0;
1946}
1947
1948static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1949{
ea76e635 1950 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1951 return SPEED_1000;
1952
05745c4a
SH		 1953 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1954 if (aux & PHY_M_PS_SPEED_100)
1955 return SPEED_100;
1956 else
1957 return SPEED_10;
1958 }
cd28ab6a
SH		 1959
1960 switch (aux & PHY_M_PS_SPEED_MSK) {
1961 case PHY_M_PS_SPEED_1000:
1962 return SPEED_1000;
1963 case PHY_M_PS_SPEED_100:
1964 return SPEED_100;
1965 default:
1966 return SPEED_10;
1967 }
1968}
1969
1970static void sky2_link_up(struct sky2_port *sky2)
1971{
1972 struct sky2_hw *hw = sky2->hw;
1973 unsigned port = sky2->port;
1974 u16 reg;
16ad91e1
SH		 1975 static const char *fc_name[] = {
1976 [FC_NONE] = "none",
1977 [FC_TX] = "tx",
1978 [FC_RX] = "rx",
1979 [FC_BOTH] = "both",
1980 };
cd28ab6a 1981
cd28ab6a 1982 /* enable Rx/Tx */
2eaba1a2 1983 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1984 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1985 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1986
1987 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1988
1989 netif_carrier_on(sky2->netdev);
cd28ab6a 1990
75e80683 1991 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1992
cd28ab6a 1993 /* Turn on link LED */
793b883e 1994 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1995 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1996
1997 if (netif_msg_link(sky2))
1998 printk(KERN_INFO PFX
d571b694 1999 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 2000 sky2->netdev->name, sky2->speed,
2001 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 2002 fc_name[sky2->flow_status]);
cd28ab6a
SH		 2003}
2004
2005static void sky2_link_down(struct sky2_port *sky2)
2006{
2007 struct sky2_hw *hw = sky2->hw;
2008 unsigned port = sky2->port;
2009 u16 reg;
2010
2011 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2012
2013 reg = gma_read16(hw, port, GM_GP_CTRL);
2014 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2015 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 2016
cd28ab6a 2017 netif_carrier_off(sky2->netdev);
cd28ab6a 2018
809aaaae 2019 /* Turn off link LED */
cd28ab6a
SH		 2020 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2021
2022 if (netif_msg_link(sky2))
2023 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 2024
cd28ab6a
SH		 2025 sky2_phy_init(hw, port);
2026}
2027
16ad91e1
SH		 2028static enum flow_control sky2_flow(int rx, int tx)
2029{
2030 if (rx)
2031 return tx ? FC_BOTH : FC_RX;
2032 else
2033 return tx ? FC_TX : FC_NONE;
2034}
2035
793b883e
SH		 2036static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2037{
2038 struct sky2_hw *hw = sky2->hw;
2039 unsigned port = sky2->port;
da4c1ff4 2040 u16 advert, lpa;
793b883e 2041
da4c1ff4 2042 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2043 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 2044 if (lpa & PHY_M_AN_RF) {
2045 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2046 return -1;
2047 }
2048
793b883e
SH		 2049 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2050 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2051 sky2->netdev->name);
2052 return -1;
2053 }
2054
793b883e 2055 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2056 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2057
da4c1ff4
SH		 2058 /* Since the pause result bits seem to in different positions on
2059 * different chips. look at registers.
2060 */
ea76e635 2061 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2062 /* Shift for bits in fiber PHY */
2063 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2064 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2065
2066 if (advert & ADVERTISE_1000XPAUSE)
2067 advert |= ADVERTISE_PAUSE_CAP;
2068 if (advert & ADVERTISE_1000XPSE_ASYM)
2069 advert |= ADVERTISE_PAUSE_ASYM;
2070 if (lpa & LPA_1000XPAUSE)
2071 lpa |= LPA_PAUSE_CAP;
2072 if (lpa & LPA_1000XPAUSE_ASYM)
2073 lpa |= LPA_PAUSE_ASYM;
2074 }
793b883e 2075
da4c1ff4
SH		 2076 sky2->flow_status = FC_NONE;
2077 if (advert & ADVERTISE_PAUSE_CAP) {
2078 if (lpa & LPA_PAUSE_CAP)
2079 sky2->flow_status = FC_BOTH;
2080 else if (advert & ADVERTISE_PAUSE_ASYM)
2081 sky2->flow_status = FC_RX;
2082 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2083 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2084 sky2->flow_status = FC_TX;
2085 }
793b883e 2086
8e95a202
JP		 2087 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2088 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2089 sky2->flow_status = FC_NONE;
2eaba1a2 2090
da4c1ff4 2091 if (sky2->flow_status & FC_TX)
793b883e
SH		 2092 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2093 else
2094 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2095
2096 return 0;
2097}
cd28ab6a 2098
e07b1aa8
SH		 2099/* Interrupt from PHY */
2100static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2101{
e07b1aa8
SH		 2102 struct net_device *dev = hw->dev[port];
2103 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2104 u16 istatus, phystat;
2105
ebc646f6
SH		 2106 if (!netif_running(dev))
2107 return;
2108
e07b1aa8
SH		 2109 spin_lock(&sky2->phy_lock);
2110 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2111 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2112
cd28ab6a
SH		 2113 if (netif_msg_intr(sky2))
2114 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2115 sky2->netdev->name, istatus, phystat);
2116
0ea065e5 2117 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 2118 if (sky2_autoneg_done(sky2, phystat) == 0)
2119 sky2_link_up(sky2);
2120 goto out;
2121 }
cd28ab6a 2122
793b883e
SH		 2123 if (istatus & PHY_M_IS_LSP_CHANGE)
2124 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2125
793b883e
SH		 2126 if (istatus & PHY_M_IS_DUP_CHANGE)
2127 sky2->duplex =
2128 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2129
793b883e
SH		 2130 if (istatus & PHY_M_IS_LST_CHANGE) {
2131 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2132 sky2_link_up(sky2);
793b883e
SH		 2133 else
2134 sky2_link_down(sky2);
cd28ab6a 2135 }
793b883e 2136out:
e07b1aa8 2137 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2138}
2139
0f5aac70
SH		 2140/* Special quick link interrupt (Yukon-2 Optima only) */
2141static void sky2_qlink_intr(struct sky2_hw *hw)
2142{
2143 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2144 u32 imask;
2145 u16 phy;
2146
2147 /* disable irq */
2148 imask = sky2_read32(hw, B0_IMSK);
2149 imask &= ~Y2_IS_PHY_QLNK;
2150 sky2_write32(hw, B0_IMSK, imask);
2151
2152 /* reset PHY Link Detect */
2153 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
a40ccc68 2154 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70 2155 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
a40ccc68 2156 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 2157
2158 sky2_link_up(sky2);
2159}
2160
62335ab0 2161/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2162 * and tx queue is full (stopped).
2163 */
cd28ab6a
SH		 2164static void sky2_tx_timeout(struct net_device *dev)
2165{
2166 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2167 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2168
2169 if (netif_msg_timer(sky2))
2170 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2171
8f24664d 2172 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2173 dev->name, sky2->tx_cons, sky2->tx_prod,
2174 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2175 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2176
81906791
SH		 2177 /* can't restart safely under softirq */
2178 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2179}
2180
2181static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2182{
6b1a3aef 2183 struct sky2_port *sky2 = netdev_priv(dev);
2184 struct sky2_hw *hw = sky2->hw;
b628ed98 2185 unsigned port = sky2->port;
6b1a3aef 2186 int err;
2187 u16 ctl, mode;
e07b1aa8 2188 u32 imask;
cd28ab6a
SH		 2189
2190 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2191 return -EINVAL;
2192
05745c4a
SH		 2193 if (new_mtu > ETH_DATA_LEN &&
2194 (hw->chip_id == CHIP_ID_YUKON_FE ||
2195 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2196 return -EINVAL;
2197
6b1a3aef 2198 if (!netif_running(dev)) {
2199 dev->mtu = new_mtu;
2200 return 0;
2201 }
2202
e07b1aa8 2203 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 2204 sky2_write32(hw, B0_IMSK, 0);
2205
018d1c66 2206 dev->trans_start = jiffies; /* prevent tx timeout */
2207 netif_stop_queue(dev);
bea3348e 2208 napi_disable(&hw->napi);
018d1c66 2209
e07b1aa8
SH		 2210 synchronize_irq(hw->pdev->irq);
2211
39dbd958 2212 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2213 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2214
2215 ctl = gma_read16(hw, port, GM_GP_CTRL);
2216 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 2217 sky2_rx_stop(sky2);
2218 sky2_rx_clean(sky2);
cd28ab6a
SH		 2219
2220 dev->mtu = new_mtu;
14d0263f 2221
6b1a3aef 2222 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2223 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2224
2225 if (dev->mtu > ETH_DATA_LEN)
2226 mode |= GM_SMOD_JUMBO_ENA;
2227
b628ed98 2228 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2229
b628ed98 2230 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2231
6b1a3aef 2232 err = sky2_rx_start(sky2);
e07b1aa8 2233 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2234
d1d08d12 2235 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2236 napi_enable(&hw->napi);
2237
1b537565
SH		 2238 if (err)
2239 dev_close(dev);
2240 else {
b628ed98 2241 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2242
1b537565
SH		 2243 netif_wake_queue(dev);
2244 }
2245
cd28ab6a
SH		 2246 return err;
2247}
2248
14d0263f
SH		 2249/* For small just reuse existing skb for next receive */
2250static struct sk_buff *receive_copy(struct sky2_port *sky2,
2251 const struct rx_ring_info *re,
2252 unsigned length)
2253{
2254 struct sk_buff *skb;
2255
89d71a66 2256 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
14d0263f 2257 if (likely(skb)) {
14d0263f
SH		 2258 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2259 length, PCI_DMA_FROMDEVICE);
d626f62b 2260 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2261 skb->ip_summed = re->skb->ip_summed;
2262 skb->csum = re->skb->csum;
2263 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2264 length, PCI_DMA_FROMDEVICE);
2265 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2266 skb_put(skb, length);
14d0263f
SH		 2267 }
2268 return skb;
2269}
2270
2271/* Adjust length of skb with fragments to match received data */
2272static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2273 unsigned int length)
2274{
2275 int i, num_frags;
2276 unsigned int size;
2277
2278 /* put header into skb */
2279 size = min(length, hdr_space);
2280 skb->tail += size;
2281 skb->len += size;
2282 length -= size;
2283
2284 num_frags = skb_shinfo(skb)->nr_frags;
2285 for (i = 0; i < num_frags; i++) {
2286 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2287
2288 if (length == 0) {
2289 /* don't need this page */
2290 __free_page(frag->page);
2291 --skb_shinfo(skb)->nr_frags;
2292 } else {
2293 size = min(length, (unsigned) PAGE_SIZE);
2294
2295 frag->size = size;
2296 skb->data_len += size;
2297 skb->truesize += size;
2298 skb->len += size;
2299 length -= size;
2300 }
2301 }
2302}
2303
2304/* Normal packet - take skb from ring element and put in a new one */
2305static struct sk_buff *receive_new(struct sky2_port *sky2,
2306 struct rx_ring_info *re,
2307 unsigned int length)
2308{
2309 struct sk_buff *skb, *nskb;
2310 unsigned hdr_space = sky2->rx_data_size;
2311
14d0263f
SH		 2312 /* Don't be tricky about reusing pages (yet) */
2313 nskb = sky2_rx_alloc(sky2);
2314 if (unlikely(!nskb))
2315 return NULL;
2316
2317 skb = re->skb;
2318 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2319
2320 prefetch(skb->data);
2321 re->skb = nskb;
454e6cb6
SH		 2322 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2323 dev_kfree_skb(nskb);
2324 re->skb = skb;
2325 return NULL;
2326 }
14d0263f
SH		 2327
2328 if (skb_shinfo(skb)->nr_frags)
2329 skb_put_frags(skb, hdr_space, length);
2330 else
489b10c1 2331 skb_put(skb, length);
14d0263f
SH		 2332 return skb;
2333}
2334
cd28ab6a
SH		 2335/*
2336 * Receive one packet.
d571b694 2337 * For larger packets, get new buffer.
cd28ab6a 2338 */
497d7c86 2339static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2340 u16 length, u32 status)
2341{
497d7c86 2342 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2343 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2344 struct sk_buff *skb = NULL;
d6532232
SH		 2345 u16 count = (status & GMR_FS_LEN) >> 16;
2346
2347#ifdef SKY2_VLAN_TAG_USED
2348 /* Account for vlan tag */
2349 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2350 count -= VLAN_HLEN;
2351#endif
cd28ab6a
SH		 2352
2353 if (unlikely(netif_msg_rx_status(sky2)))
2354 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2355 dev->name, sky2->rx_next, status, length);
cd28ab6a 2356
793b883e 2357 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2358 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2359
3b12e014
SH		 2360 /* This chip has hardware problems that generates bogus status.
2361 * So do only marginal checking and expect higher level protocols
2362 * to handle crap frames.
2363 */
2364 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2365 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2366 length != count)
2367 goto okay;
2368
42eeea01 2369 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2370 goto error;
2371
42eeea01 2372 if (!(status & GMR_FS_RX_OK))
2373 goto resubmit;
2374
d6532232
SH		 2375 /* if length reported by DMA does not match PHY, packet was truncated */
2376 if (length != count)
3b12e014 2377 goto len_error;
71749531 2378
3b12e014 2379okay:
14d0263f
SH		 2380 if (length < copybreak)
2381 skb = receive_copy(sky2, re, length);
2382 else
2383 skb = receive_new(sky2, re, length);
793b883e 2384resubmit:
14d0263f 2385 sky2_rx_submit(sky2, re);
79e57d32 2386
cd28ab6a
SH		 2387 return skb;
2388
3b12e014 2389len_error:
71749531
SH		 2390 /* Truncation of overlength packets
2391 causes PHY length to not match MAC length */
7138a0f5 2392 ++dev->stats.rx_length_errors;
d6532232 2393 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2394 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2395 dev->name, status, length);
d6532232 2396 goto resubmit;
71749531 2397
cd28ab6a 2398error:
7138a0f5 2399 ++dev->stats.rx_errors;
b6d77734 2400 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2401 dev->stats.rx_over_errors++;
b6d77734
SH		 2402 goto resubmit;
2403 }
6e15b712 2404
3be92a70 2405 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2406 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2407 dev->name, status, length);
793b883e
SH		 2408
2409 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2410 dev->stats.rx_length_errors++;
cd28ab6a 2411 if (status & GMR_FS_FRAGMENT)
7138a0f5 2412 dev->stats.rx_frame_errors++;
cd28ab6a 2413 if (status & GMR_FS_CRC_ERR)
7138a0f5 2414 dev->stats.rx_crc_errors++;
79e57d32 2415
793b883e 2416 goto resubmit;
cd28ab6a
SH		 2417}
2418
e07b1aa8
SH		 2419/* Transmit complete */
2420static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2421{
e07b1aa8 2422 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2423
49d4b8ba 2424 if (netif_running(dev))
e07b1aa8 2425 sky2_tx_complete(sky2, last);
cd28ab6a
SH		 2426}
2427
37e5a243
SH		 2428static inline void sky2_skb_rx(const struct sky2_port *sky2,
2429 u32 status, struct sk_buff *skb)
2430{
2431#ifdef SKY2_VLAN_TAG_USED
2432 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2433 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2434 if (skb->ip_summed == CHECKSUM_NONE)
2435 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2436 else
2437 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2438 vlan_tag, skb);
2439 return;
2440 }
2441#endif
2442 if (skb->ip_summed == CHECKSUM_NONE)
2443 netif_receive_skb(skb);
2444 else
2445 napi_gro_receive(&sky2->hw->napi, skb);
2446}
2447
bf15fe99
SH		 2448static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2449 unsigned packets, unsigned bytes)
2450{
2451 if (packets) {
2452 struct net_device *dev = hw->dev[port];
2453
2454 dev->stats.rx_packets += packets;
2455 dev->stats.rx_bytes += bytes;
2456 dev->last_rx = jiffies;
2457 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2458 }
2459}
2460
e07b1aa8 2461/* Process status response ring */
26691830 2462static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2463{
e07b1aa8 2464 int work_done = 0;
bf15fe99
SH		 2465 unsigned int total_bytes[2] = { 0 };
2466 unsigned int total_packets[2] = { 0 };
a8fd6266 2467
af2a58ac 2468 rmb();
26691830 2469 do {
55c9dd35 2470 struct sky2_port *sky2;
13210ce5 2471 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2472 unsigned port;
13210ce5 2473 struct net_device *dev;
cd28ab6a 2474 struct sk_buff *skb;
cd28ab6a
SH		 2475 u32 status;
2476 u16 length;
ab5adecb
SH		 2477 u8 opcode = le->opcode;
2478
2479 if (!(opcode & HW_OWNER))
2480 break;
cd28ab6a 2481
cb5d9547 2482 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2483
ab5adecb 2484 port = le->css & CSS_LINK_BIT;
69161611 2485 dev = hw->dev[port];
13210ce5 2486 sky2 = netdev_priv(dev);
f65b138c
SH		 2487 length = le16_to_cpu(le->length);
2488 status = le32_to_cpu(le->status);
cd28ab6a 2489
ab5adecb
SH		 2490 le->opcode = 0;
2491 switch (opcode & ~HW_OWNER) {
cd28ab6a 2492 case OP_RXSTAT:
bf15fe99
SH		 2493 total_packets[port]++;
2494 total_bytes[port] += length;
497d7c86 2495 skb = sky2_receive(dev, length, status);
3225b919 2496 if (unlikely(!skb)) {
7138a0f5 2497 dev->stats.rx_dropped++;
55c9dd35 2498 break;
3225b919 2499 }
13210ce5 2500
69161611 2501 /* This chip reports checksum status differently */
05745c4a 2502 if (hw->flags & SKY2_HW_NEW_LE) {
0ea065e5 2503 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
69161611
SH		 2504 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2505 (le->css & CSS_TCPUDPCSOK))
2506 skb->ip_summed = CHECKSUM_UNNECESSARY;
2507 else
2508 skb->ip_summed = CHECKSUM_NONE;
2509 }
2510
13210ce5 2511 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2512
37e5a243 2513 sky2_skb_rx(sky2, status, skb);
13210ce5 2514
22e11703 2515 /* Stop after net poll weight */
13210ce5 2516 if (++work_done >= to_do)
2517 goto exit_loop;
cd28ab6a
SH		 2518 break;
2519
d1f13708 2520#ifdef SKY2_VLAN_TAG_USED
2521 case OP_RXVLAN:
2522 sky2->rx_tag = length;
2523 break;
2524
2525 case OP_RXCHKSVLAN:
2526 sky2->rx_tag = length;
2527 /* fall through */
2528#endif
cd28ab6a 2529 case OP_RXCHKS:
0ea065e5 2530 if (!(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
87418307
SH		 2531 break;
2532
05745c4a
SH		 2533 /* If this happens then driver assuming wrong format */
2534 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2535 if (net_ratelimit())
2536 printk(KERN_NOTICE "%s: unexpected"
2537 " checksum status\n",
2538 dev->name);
69161611 2539 break;
05745c4a 2540 }
69161611 2541
87418307
SH		 2542 /* Both checksum counters are programmed to start at
2543 * the same offset, so unless there is a problem they
2544 * should match. This failure is an early indication that
2545 * hardware receive checksumming won't work.
2546 */
2547 if (likely(status >> 16 == (status & 0xffff))) {
2548 skb = sky2->rx_ring[sky2->rx_next].skb;
2549 skb->ip_summed = CHECKSUM_COMPLETE;
b9389796 2550 skb->csum = le16_to_cpu(status);
87418307
SH		 2551 } else {
2552 printk(KERN_NOTICE PFX "%s: hardware receive "
2553 "checksum problem (status = %#x)\n",
2554 dev->name, status);
0ea065e5
SH		 2555 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2556
87418307 2557 sky2_write32(sky2->hw,
69161611 2558 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2559 BMU_DIS_RX_CHKSUM);
2560 }
cd28ab6a
SH		 2561 break;
2562
2563 case OP_TXINDEXLE:
13b97b74 2564 /* TX index reports status for both ports */
f55925d7 2565 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2566 if (hw->dev[1])
2567 sky2_tx_done(hw->dev[1],
2568 ((status >> 24) & 0xff)
2569 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2570 break;
2571
cd28ab6a
SH		 2572 default:
2573 if (net_ratelimit())
793b883e 2574 printk(KERN_WARNING PFX
ab5adecb 2575 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2576 }
26691830 2577 } while (hw->st_idx != idx);
cd28ab6a 2578
fe2a24df
SH		 2579 /* Fully processed status ring so clear irq */
2580 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2581
13210ce5 2582exit_loop:
bf15fe99
SH		 2583 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2584 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2585
e07b1aa8 2586 return work_done;
cd28ab6a
SH		 2587}
2588
2589static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2590{
2591 struct net_device *dev = hw->dev[port];
2592
3be92a70
SH		 2593 if (net_ratelimit())
2594 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2595 dev->name, status);
cd28ab6a
SH		 2596
2597 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2598 if (net_ratelimit())
2599 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2600 dev->name);
cd28ab6a
SH		 2601 /* Clear IRQ */
2602 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2603 }
2604
2605 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2606 if (net_ratelimit())
2607 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2608 dev->name);
cd28ab6a
SH		 2609
2610 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2611 }
2612
2613 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2614 if (net_ratelimit())
2615 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2616 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2617 }
2618
2619 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2620 if (net_ratelimit())
2621 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2622 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2623 }
2624
2625 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2626 if (net_ratelimit())
2627 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2628 dev->name);
cd28ab6a
SH		 2629 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2630 }
2631}
2632
2633static void sky2_hw_intr(struct sky2_hw *hw)
2634{
555382cb 2635 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2636 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2637 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2638
2639 status &= hwmsk;
cd28ab6a 2640
793b883e 2641 if (status & Y2_IS_TIST_OV)
cd28ab6a 2642 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2643
2644 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2645 u16 pci_err;
2646
a40ccc68 2647 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2648 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2649 if (net_ratelimit())
555382cb 2650 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2651 pci_err);
cd28ab6a 2652
b32f40c4 2653 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2654 pci_err | PCI_STATUS_ERROR_BITS);
a40ccc68 2655 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2656 }
2657
2658 if (status & Y2_IS_PCI_EXP) {
d571b694 2659 /* PCI-Express uncorrectable Error occurred */
555382cb 2660 u32 err;
cd28ab6a 2661
a40ccc68 2662 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2663 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2664 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2665 0xfffffffful);
3be92a70 2666 if (net_ratelimit())
555382cb 2667 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2668
7782c8c4 2669 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
a40ccc68 2670 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2671 }
2672
2673 if (status & Y2_HWE_L1_MASK)
2674 sky2_hw_error(hw, 0, status);
2675 status >>= 8;
2676 if (status & Y2_HWE_L1_MASK)
2677 sky2_hw_error(hw, 1, status);
2678}
2679
2680static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2681{
2682 struct net_device *dev = hw->dev[port];
2683 struct sky2_port *sky2 = netdev_priv(dev);
2684 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2685
2686 if (netif_msg_intr(sky2))
2687 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2688 dev->name, status);
2689
a3caeada
SH		 2690 if (status & GM_IS_RX_CO_OV)
2691 gma_read16(hw, port, GM_RX_IRQ_SRC);
2692
2693 if (status & GM_IS_TX_CO_OV)
2694 gma_read16(hw, port, GM_TX_IRQ_SRC);
2695
cd28ab6a 2696 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2697 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2698 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2699 }
2700
2701 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2702 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2703 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2704 }
cd28ab6a
SH		 2705}
2706
40b01727 2707/* This should never happen it is a bug. */
c119731d 2708static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH		 2709{
2710 struct net_device *dev = hw->dev[port];
c119731d 2711 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2712
c119731d
SH		 2713 dev_err(&hw->pdev->dev, PFX
2714 "%s: descriptor error q=%#x get=%u put=%u\n",
2715 dev->name, (unsigned) q, (unsigned) idx,
2716 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2717
40b01727 2718 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2719}
cd28ab6a 2720
75e80683
SH		 2721static int sky2_rx_hung(struct net_device *dev)
2722{
2723 struct sky2_port *sky2 = netdev_priv(dev);
2724 struct sky2_hw *hw = sky2->hw;
2725 unsigned port = sky2->port;
2726 unsigned rxq = rxqaddr[port];
2727 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2728 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2729 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2730 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2731
2732 /* If idle and MAC or PCI is stuck */
2733 if (sky2->check.last == dev->last_rx &&
2734 ((mac_rp == sky2->check.mac_rp &&
2735 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2736 /* Check if the PCI RX hang */
2737 (fifo_rp == sky2->check.fifo_rp &&
2738 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2739 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2740 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2741 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2742 return 1;
2743 } else {
2744 sky2->check.last = dev->last_rx;
2745 sky2->check.mac_rp = mac_rp;
2746 sky2->check.mac_lev = mac_lev;
2747 sky2->check.fifo_rp = fifo_rp;
2748 sky2->check.fifo_lev = fifo_lev;
2749 return 0;
2750 }
2751}
2752
32c2c300 2753static void sky2_watchdog(unsigned long arg)
d27ed387 2754{
01bd7564 2755 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2756
75e80683 2757 /* Check for lost IRQ once a second */
32c2c300 2758 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2759 napi_schedule(&hw->napi);
75e80683
SH		 2760 } else {
2761 int i, active = 0;
2762
2763 for (i = 0; i < hw->ports; i++) {
bea3348e 2764 struct net_device *dev = hw->dev[i];
75e80683
SH		 2765 if (!netif_running(dev))
2766 continue;
2767 ++active;
2768
2769 /* For chips with Rx FIFO, check if stuck */
39dbd958 2770 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2771 sky2_rx_hung(dev)) {
2772 pr_info(PFX "%s: receiver hang detected\n",
2773 dev->name);
2774 schedule_work(&hw->restart_work);
2775 return;
2776 }
2777 }
2778
2779 if (active == 0)
2780 return;
32c2c300 2781 }
01bd7564 2782
75e80683 2783 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2784}
2785
40b01727
SH		 2786/* Hardware/software error handling */
2787static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2788{
40b01727
SH		 2789 if (net_ratelimit())
2790 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2791
1e5f1283
SH		 2792 if (status & Y2_IS_HW_ERR)
2793 sky2_hw_intr(hw);
d257924e 2794
1e5f1283
SH		 2795 if (status & Y2_IS_IRQ_MAC1)
2796 sky2_mac_intr(hw, 0);
cd28ab6a 2797
1e5f1283
SH		 2798 if (status & Y2_IS_IRQ_MAC2)
2799 sky2_mac_intr(hw, 1);
cd28ab6a 2800
1e5f1283 2801 if (status & Y2_IS_CHK_RX1)
c119731d 2802 sky2_le_error(hw, 0, Q_R1);
d257924e 2803
1e5f1283 2804 if (status & Y2_IS_CHK_RX2)
c119731d 2805 sky2_le_error(hw, 1, Q_R2);
d257924e 2806
1e5f1283 2807 if (status & Y2_IS_CHK_TXA1)
c119731d 2808 sky2_le_error(hw, 0, Q_XA1);
d257924e 2809
1e5f1283 2810 if (status & Y2_IS_CHK_TXA2)
c119731d 2811 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH		 2812}
2813
bea3348e 2814static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2815{
bea3348e 2816 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2817 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2818 int work_done = 0;
26691830 2819 u16 idx;
40b01727
SH		 2820
2821 if (unlikely(status & Y2_IS_ERROR))
2822 sky2_err_intr(hw, status);
2823
2824 if (status & Y2_IS_IRQ_PHY1)
2825 sky2_phy_intr(hw, 0);
2826
2827 if (status & Y2_IS_IRQ_PHY2)
2828 sky2_phy_intr(hw, 1);
cd28ab6a 2829
0f5aac70
SH		 2830 if (status & Y2_IS_PHY_QLNK)
2831 sky2_qlink_intr(hw);
2832
26691830
SH		 2833 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2834 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2835
2836 if (work_done >= work_limit)
26691830
SH		 2837 goto done;
2838 }
6f535763 2839
26691830
SH		 2840 napi_complete(napi);
2841 sky2_read32(hw, B0_Y2_SP_LISR);
2842done:
6f535763 2843
bea3348e 2844 return work_done;
e07b1aa8
SH		 2845}
2846
7d12e780 2847static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2848{
2849 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2850 u32 status;
2851
2852 /* Reading this mask interrupts as side effect */
2853 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2854 if (status == 0 || status == ~0)
2855 return IRQ_NONE;
793b883e 2856
e07b1aa8 2857 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2858
2859 napi_schedule(&hw->napi);
793b883e 2860
cd28ab6a
SH		 2861 return IRQ_HANDLED;
2862}
2863
2864#ifdef CONFIG_NET_POLL_CONTROLLER
2865static void sky2_netpoll(struct net_device *dev)
2866{
2867 struct sky2_port *sky2 = netdev_priv(dev);
2868
bea3348e 2869 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2870}
2871#endif
2872
2873/* Chip internal frequency for clock calculations */
05745c4a 2874static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2875{
793b883e 2876 switch (hw->chip_id) {
cd28ab6a 2877 case CHIP_ID_YUKON_EC:
5a5b1ea0 2878 case CHIP_ID_YUKON_EC_U:
93745494 2879 case CHIP_ID_YUKON_EX:
ed4d4161 2880 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2881 case CHIP_ID_YUKON_UL_2:
0f5aac70 2882 case CHIP_ID_YUKON_OPT:
05745c4a
SH		 2883 return 125;
2884
cd28ab6a 2885 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2886 return 100;
2887
2888 case CHIP_ID_YUKON_FE_P:
2889 return 50;
2890
2891 case CHIP_ID_YUKON_XL:
2892 return 156;
2893
2894 default:
2895 BUG();
cd28ab6a
SH		 2896 }
2897}
2898
fb17358f 2899static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2900{
fb17358f 2901 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2902}
2903
fb17358f 2904static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2905{
fb17358f 2906 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2907}
2908
fb17358f 2909
e3173832 2910static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2911{
b89165f2 2912 u8 t8;
cd28ab6a 2913
167f53d0 2914 /* Enable all clocks and check for bad PCI access */
b32f40c4 2915 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2916
cd28ab6a 2917 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2918
cd28ab6a 2919 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2920 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2921
2922 switch(hw->chip_id) {
2923 case CHIP_ID_YUKON_XL:
39dbd958 2924 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2925 break;
2926
2927 case CHIP_ID_YUKON_EC_U:
2928 hw->flags = SKY2_HW_GIGABIT
2929 | SKY2_HW_NEWER_PHY
2930 | SKY2_HW_ADV_POWER_CTL;
2931 break;
2932
2933 case CHIP_ID_YUKON_EX:
2934 hw->flags = SKY2_HW_GIGABIT
2935 | SKY2_HW_NEWER_PHY
2936 | SKY2_HW_NEW_LE
2937 | SKY2_HW_ADV_POWER_CTL;
2938
2939 /* New transmit checksum */
2940 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2941 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2942 break;
2943
2944 case CHIP_ID_YUKON_EC:
2945 /* This rev is really old, and requires untested workarounds */
2946 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2947 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2948 return -EOPNOTSUPP;
2949 }
39dbd958 2950 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2951 break;
2952
2953 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2954 break;
2955
05745c4a
SH		 2956 case CHIP_ID_YUKON_FE_P:
2957 hw->flags = SKY2_HW_NEWER_PHY
2958 | SKY2_HW_NEW_LE
2959 | SKY2_HW_AUTO_TX_SUM
2960 | SKY2_HW_ADV_POWER_CTL;
2961 break;
ed4d4161
SH		 2962
2963 case CHIP_ID_YUKON_SUPR:
2964 hw->flags = SKY2_HW_GIGABIT
2965 | SKY2_HW_NEWER_PHY
2966 | SKY2_HW_NEW_LE
2967 | SKY2_HW_AUTO_TX_SUM
2968 | SKY2_HW_ADV_POWER_CTL;
2969 break;
2970
0ce8b98d 2971 case CHIP_ID_YUKON_UL_2:
b338682d
TI		 2972 hw->flags = SKY2_HW_GIGABIT
2973 | SKY2_HW_ADV_POWER_CTL;
2974 break;
2975
0f5aac70 2976 case CHIP_ID_YUKON_OPT:
0ce8b98d 2977 hw->flags = SKY2_HW_GIGABIT
b338682d 2978 | SKY2_HW_NEW_LE
0ce8b98d
SH		 2979 | SKY2_HW_ADV_POWER_CTL;
2980 break;
2981
ea76e635 2982 default:
b02a9258
SH		 2983 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2984 hw->chip_id);
cd28ab6a
SH		 2985 return -EOPNOTSUPP;
2986 }
2987
ea76e635
SH		 2988 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2989 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2990 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2991
e3173832
SH		 2992 hw->ports = 1;
2993 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2994 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2995 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2996 ++hw->ports;
2997 }
2998
74a61ebf
MM		 2999 if (sky2_read8(hw, B2_E_0))
3000 hw->flags |= SKY2_HW_RAM_BUFFER;
3001
e3173832
SH		 3002 return 0;
3003}
3004
3005static void sky2_reset(struct sky2_hw *hw)
3006{
555382cb 3007 struct pci_dev *pdev = hw->pdev;
e3173832 3008 u16 status;
555382cb
SH		 3009 int i, cap;
3010 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 3011
cd28ab6a 3012 /* disable ASF */
4f44d8ba
SH		 3013 if (hw->chip_id == CHIP_ID_YUKON_EX) {
3014 status = sky2_read16(hw, HCU_CCSR);
3015 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3016 HCU_CCSR_UC_STATE_MSK);
3017 sky2_write16(hw, HCU_CCSR, status);
3018 } else
3019 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3020 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 3021
3022 /* do a SW reset */
3023 sky2_write8(hw, B0_CTST, CS_RST_SET);
3024 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3025
ac93a394
SH		 3026 /* allow writes to PCI config */
3027 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3028
cd28ab6a 3029 /* clear PCI errors, if any */
b32f40c4 3030 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 3031 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 3032 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 3033
3034 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3035
555382cb
SH		 3036 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3037 if (cap) {
7782c8c4
SH		 3038 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3039 0xfffffffful);
555382cb
SH		 3040
3041 /* If error bit is stuck on ignore it */
3042 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3043 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 3044 else
555382cb
SH		 3045 hwe_mask |= Y2_IS_PCI_EXP;
3046 }
cd28ab6a 3047
ae306cca 3048 sky2_power_on(hw);
a40ccc68 3049 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 3050
3051 for (i = 0; i < hw->ports; i++) {
3052 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3053 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 3054
ed4d4161
SH		 3055 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3056 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 3057 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3058 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3059 | GMC_BYP_RETR_ON);
877c8570
SH		 3060
3061 }
3062
3063 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3064 /* enable MACSec clock gating */
3065 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
cd28ab6a
SH		 3066 }
3067
0f5aac70
SH		 3068 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3069 u16 reg;
3070 u32 msk;
3071
3072 if (hw->chip_rev == 0) {
3073 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3074 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3075
3076 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3077 reg = 10;
3078 } else {
3079 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3080 reg = 3;
3081 }
3082
3083 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3084
3085 /* reset PHY Link Detect */
a40ccc68 3086 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70
SH		 3087 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3088 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3089 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3090
3091
3092 /* enable PHY Quick Link */
3093 msk = sky2_read32(hw, B0_IMSK);
3094 msk |= Y2_IS_PHY_QLNK;
3095 sky2_write32(hw, B0_IMSK, msk);
3096
3097 /* check if PSMv2 was running before */
3098 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3099 if (reg & PCI_EXP_LNKCTL_ASPMC) {
3100 int cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3101 /* restore the PCIe Link Control register */
3102 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3103 }
a40ccc68 3104 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 3105
3106 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3107 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3108 }
3109
793b883e
SH		 3110 /* Clear I2C IRQ noise */
3111 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 3112
3113 /* turn off hardware timer (unused) */
3114 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3115 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3116
69634ee7
SH		 3117 /* Turn off descriptor polling */
3118 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3119
3120 /* Turn off receive timestamp */
3121 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3122 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3123
3124 /* enable the Tx Arbiters */
3125 for (i = 0; i < hw->ports; i++)
3126 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3127
3128 /* Initialize ram interface */
3129 for (i = 0; i < hw->ports; i++) {
793b883e 3130 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3131
3132 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3133 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3134 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3135 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3136 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3137 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3138 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3139 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3140 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3141 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3142 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3143 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3144 }
3145
555382cb 3146 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3147
cd28ab6a 3148 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3149 sky2_gmac_reset(hw, i);
cd28ab6a 3150
cd28ab6a
SH		 3151 memset(hw->st_le, 0, STATUS_LE_BYTES);
3152 hw->st_idx = 0;
3153
3154 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3155 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3156
3157 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3158 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3159
3160 /* Set the list last index */
793b883e 3161 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3162
290d4de5
SH		 3163 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3164 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3165
290d4de5
SH		 3166 /* set Status-FIFO ISR watermark */
3167 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3168 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3169 else
3170 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3171
290d4de5 3172 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3173 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3174 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3175
793b883e 3176 /* enable status unit */
cd28ab6a
SH		 3177 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3178
3179 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3180 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3181 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3182}
3183
af18d8b8
SH		 3184/* Take device down (offline).
3185 * Equivalent to doing dev_stop() but this does not
3186 * inform upper layers of the transistion.
3187 */
3188static void sky2_detach(struct net_device *dev)
3189{
3190 if (netif_running(dev)) {
c36531b9 3191 netif_tx_lock(dev);
af18d8b8 3192 netif_device_detach(dev); /* stop txq */
c36531b9 3193 netif_tx_unlock(dev);
af18d8b8
SH		 3194 sky2_down(dev);
3195 }
3196}
3197
3198/* Bring device back after doing sky2_detach */
3199static int sky2_reattach(struct net_device *dev)
3200{
3201 int err = 0;
3202
3203 if (netif_running(dev)) {
3204 err = sky2_up(dev);
3205 if (err) {
3206 printk(KERN_INFO PFX "%s: could not restart %d\n",
3207 dev->name, err);
3208 dev_close(dev);
3209 } else {
3210 netif_device_attach(dev);
3211 sky2_set_multicast(dev);
3212 }
3213 }
3214
3215 return err;
3216}
3217
81906791
SH		 3218static void sky2_restart(struct work_struct *work)
3219{
3220 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
af18d8b8 3221 int i;
81906791 3222
81906791 3223 rtnl_lock();
af18d8b8
SH		 3224 for (i = 0; i < hw->ports; i++)
3225 sky2_detach(hw->dev[i]);
81906791 3226
8cfcbe99
SH		 3227 napi_disable(&hw->napi);
3228 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 3229 sky2_reset(hw);
3230 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 3231 napi_enable(&hw->napi);
81906791 3232
af18d8b8
SH		 3233 for (i = 0; i < hw->ports; i++)
3234 sky2_reattach(hw->dev[i]);
81906791 3235
81906791
SH		 3236 rtnl_unlock();
3237}
3238
e3173832
SH		 3239static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3240{
3241 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3242}
3243
2ca4231d
MM		 3244static void sky2_hw_set_wol(struct sky2_hw *hw)
3245{
3246 int wol = 0;
3247 int i;
3248
3249 for (i = 0; i < hw->ports; i++) {
3250 struct net_device *dev = hw->dev[i];
3251 struct sky2_port *sky2 = netdev_priv(dev);
3252
3253 if (sky2->wol)
3254 wol = 1;
3255 }
3256
3257 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3258 hw->chip_id == CHIP_ID_YUKON_EX ||
3259 hw->chip_id == CHIP_ID_YUKON_FE_P)
3260 sky2_write32(hw, B0_CTST, wol ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3261
3262 device_set_wakeup_enable(&hw->pdev->dev, wol);
3263}
3264
e3173832
SH		 3265static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3266{
3267 const struct sky2_port *sky2 = netdev_priv(dev);
3268
3269 wol->supported = sky2_wol_supported(sky2->hw);
3270 wol->wolopts = sky2->wol;
3271}
3272
3273static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3274{
3275 struct sky2_port *sky2 = netdev_priv(dev);
3276 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3277
8e95a202
JP		 3278 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3279 !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3280 return -EOPNOTSUPP;
3281
3282 sky2->wol = wol->wolopts;
3283
2ca4231d 3284 sky2_hw_set_wol(hw);
9d731d77 3285
e3173832
SH		 3286 if (!netif_running(dev))
3287 sky2_wol_init(sky2);
cd28ab6a
SH		 3288 return 0;
3289}
3290
28bd181a 3291static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3292{
b89165f2
SH		 3293 if (sky2_is_copper(hw)) {
3294 u32 modes = SUPPORTED_10baseT_Half
3295 | SUPPORTED_10baseT_Full
3296 | SUPPORTED_100baseT_Half
3297 | SUPPORTED_100baseT_Full
3298 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3299
ea76e635 3300 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3301 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3302 | SUPPORTED_1000baseT_Full;
3303 return modes;
cd28ab6a 3304 } else
b89165f2
SH		 3305 return SUPPORTED_1000baseT_Half
3306 | SUPPORTED_1000baseT_Full
3307 | SUPPORTED_Autoneg
3308 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3309}
3310
793b883e 3311static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3312{
3313 struct sky2_port *sky2 = netdev_priv(dev);
3314 struct sky2_hw *hw = sky2->hw;
3315
3316 ecmd->transceiver = XCVR_INTERNAL;
3317 ecmd->supported = sky2_supported_modes(hw);
3318 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3319 if (sky2_is_copper(hw)) {
cd28ab6a 3320 ecmd->port = PORT_TP;
b89165f2
SH		 3321 ecmd->speed = sky2->speed;
3322 } else {
3323 ecmd->speed = SPEED_1000;
cd28ab6a 3324 ecmd->port = PORT_FIBRE;
b89165f2 3325 }
cd28ab6a
SH		 3326
3327 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3328 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3329 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3330 ecmd->duplex = sky2->duplex;
3331 return 0;
3332}
3333
3334static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3335{
3336 struct sky2_port *sky2 = netdev_priv(dev);
3337 const struct sky2_hw *hw = sky2->hw;
3338 u32 supported = sky2_supported_modes(hw);
3339
3340 if (ecmd->autoneg == AUTONEG_ENABLE) {
0ea065e5 3341 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3342 ecmd->advertising = supported;
3343 sky2->duplex = -1;
3344 sky2->speed = -1;
3345 } else {
3346 u32 setting;
3347
793b883e 3348 switch (ecmd->speed) {
cd28ab6a
SH		 3349 case SPEED_1000:
3350 if (ecmd->duplex == DUPLEX_FULL)
3351 setting = SUPPORTED_1000baseT_Full;
3352 else if (ecmd->duplex == DUPLEX_HALF)
3353 setting = SUPPORTED_1000baseT_Half;
3354 else
3355 return -EINVAL;
3356 break;
3357 case SPEED_100:
3358 if (ecmd->duplex == DUPLEX_FULL)
3359 setting = SUPPORTED_100baseT_Full;
3360 else if (ecmd->duplex == DUPLEX_HALF)
3361 setting = SUPPORTED_100baseT_Half;
3362 else
3363 return -EINVAL;
3364 break;
3365
3366 case SPEED_10:
3367 if (ecmd->duplex == DUPLEX_FULL)
3368 setting = SUPPORTED_10baseT_Full;
3369 else if (ecmd->duplex == DUPLEX_HALF)
3370 setting = SUPPORTED_10baseT_Half;
3371 else
3372 return -EINVAL;
3373 break;
3374 default:
3375 return -EINVAL;
3376 }
3377
3378 if ((setting & supported) == 0)
3379 return -EINVAL;
3380
3381 sky2->speed = ecmd->speed;
3382 sky2->duplex = ecmd->duplex;
0ea065e5 3383 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3384 }
3385
cd28ab6a
SH		 3386 sky2->advertising = ecmd->advertising;
3387
d1b139c0 3388 if (netif_running(dev)) {
1b537565 3389 sky2_phy_reinit(sky2);
d1b139c0
SH		 3390 sky2_set_multicast(dev);
3391 }
cd28ab6a
SH		 3392
3393 return 0;
3394}
3395
3396static void sky2_get_drvinfo(struct net_device *dev,
3397 struct ethtool_drvinfo *info)
3398{
3399 struct sky2_port *sky2 = netdev_priv(dev);
3400
3401 strcpy(info->driver, DRV_NAME);
3402 strcpy(info->version, DRV_VERSION);
3403 strcpy(info->fw_version, "N/A");
3404 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3405}
3406
3407static const struct sky2_stat {
793b883e
SH		 3408 char name[ETH_GSTRING_LEN];
3409 u16 offset;
cd28ab6a
SH		 3410} sky2_stats[] = {
3411 { "tx_bytes", GM_TXO_OK_HI },
3412 { "rx_bytes", GM_RXO_OK_HI },
3413 { "tx_broadcast", GM_TXF_BC_OK },
3414 { "rx_broadcast", GM_RXF_BC_OK },
3415 { "tx_multicast", GM_TXF_MC_OK },
3416 { "rx_multicast", GM_RXF_MC_OK },
3417 { "tx_unicast", GM_TXF_UC_OK },
3418 { "rx_unicast", GM_RXF_UC_OK },
3419 { "tx_mac_pause", GM_TXF_MPAUSE },
3420 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3421 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3422 { "late_collision",GM_TXF_LAT_COL },
3423 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3424 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3425 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3426
d2604540 3427 { "rx_short", GM_RXF_SHT },
cd28ab6a 3428 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3429 { "rx_64_byte_packets", GM_RXF_64B },
3430 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3431 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3432 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3433 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3434 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3435 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3436 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3437 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3438 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3439 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3440
3441 { "tx_64_byte_packets", GM_TXF_64B },
3442 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3443 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3444 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3445 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3446 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3447 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3448 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3449};
3450
cd28ab6a
SH		 3451static u32 sky2_get_rx_csum(struct net_device *dev)
3452{
3453 struct sky2_port *sky2 = netdev_priv(dev);
3454
0ea065e5 3455 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
cd28ab6a
SH		 3456}
3457
3458static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3459{
3460 struct sky2_port *sky2 = netdev_priv(dev);
3461
0ea065e5
SH		 3462 if (data)
3463 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3464 else
3465 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
793b883e 3466
cd28ab6a
SH		 3467 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3468 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3469
3470 return 0;
3471}
3472
3473static u32 sky2_get_msglevel(struct net_device *netdev)
3474{
3475 struct sky2_port *sky2 = netdev_priv(netdev);
3476 return sky2->msg_enable;
3477}
3478
9a7ae0a9
SH		 3479static int sky2_nway_reset(struct net_device *dev)
3480{
3481 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3482
0ea065e5 3483 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3484 return -EINVAL;
3485
1b537565 3486 sky2_phy_reinit(sky2);
d1b139c0 3487 sky2_set_multicast(dev);
9a7ae0a9
SH		 3488
3489 return 0;
3490}
3491
793b883e 3492static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3493{
3494 struct sky2_hw *hw = sky2->hw;
3495 unsigned port = sky2->port;
3496 int i;
3497
3498 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3499 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3500 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3501 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3502
793b883e 3503 for (i = 2; i < count; i++)
cd28ab6a
SH		 3504 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3505}
3506
cd28ab6a
SH		 3507static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3508{
3509 struct sky2_port *sky2 = netdev_priv(netdev);
3510 sky2->msg_enable = value;
3511}
3512
b9f2c044 3513static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3514{
b9f2c044
JG		 3515 switch (sset) {
3516 case ETH_SS_STATS:
3517 return ARRAY_SIZE(sky2_stats);
3518 default:
3519 return -EOPNOTSUPP;
3520 }
cd28ab6a
SH		 3521}
3522
3523static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3524 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3525{
3526 struct sky2_port *sky2 = netdev_priv(dev);
3527
793b883e 3528 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3529}
3530
793b883e 3531static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3532{
3533 int i;
3534
3535 switch (stringset) {
3536 case ETH_SS_STATS:
3537 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3538 memcpy(data + i * ETH_GSTRING_LEN,
3539 sky2_stats[i].name, ETH_GSTRING_LEN);
3540 break;
3541 }
3542}
3543
cd28ab6a
SH		 3544static int sky2_set_mac_address(struct net_device *dev, void *p)
3545{
3546 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3547 struct sky2_hw *hw = sky2->hw;
3548 unsigned port = sky2->port;
3549 const struct sockaddr *addr = p;
cd28ab6a
SH		 3550
3551 if (!is_valid_ether_addr(addr->sa_data))
3552 return -EADDRNOTAVAIL;
3553
cd28ab6a 3554 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3555 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3556 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3557 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3558 dev->dev_addr, ETH_ALEN);
1b537565 3559
a8ab1ec0
SH		 3560 /* virtual address for data */
3561 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3562
3563 /* physical address: used for pause frames */
3564 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3565
3566 return 0;
cd28ab6a
SH		 3567}
3568
a052b52f
SH		 3569static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3570{
3571 u32 bit;
3572
3573 bit = ether_crc(ETH_ALEN, addr) & 63;
3574 filter[bit >> 3] |= 1 << (bit & 7);
3575}
3576
cd28ab6a
SH		 3577static void sky2_set_multicast(struct net_device *dev)
3578{
3579 struct sky2_port *sky2 = netdev_priv(dev);
3580 struct sky2_hw *hw = sky2->hw;
3581 unsigned port = sky2->port;
3582 struct dev_mc_list *list = dev->mc_list;
3583 u16 reg;
3584 u8 filter[8];
a052b52f
SH		 3585 int rx_pause;
3586 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3587
a052b52f 3588 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3589 memset(filter, 0, sizeof(filter));
3590
3591 reg = gma_read16(hw, port, GM_RX_CTRL);
3592 reg |= GM_RXCR_UCF_ENA;
3593
d571b694 3594 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3595 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3596 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3597 memset(filter, 0xff, sizeof(filter));
a052b52f 3598 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3599 reg &= ~GM_RXCR_MCF_ENA;
3600 else {
3601 int i;
3602 reg |= GM_RXCR_MCF_ENA;
3603
a052b52f
SH		 3604 if (rx_pause)
3605 sky2_add_filter(filter, pause_mc_addr);
3606
3607 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3608 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3609 }
3610
cd28ab6a 3611 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3612 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3613 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3614 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3615 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3616 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3617 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3618 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3619
3620 gma_write16(hw, port, GM_RX_CTRL, reg);
3621}
3622
3623/* Can have one global because blinking is controlled by
3624 * ethtool and that is always under RTNL mutex
3625 */
a84d0a3d 3626static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3627{
a84d0a3d
SH		 3628 struct sky2_hw *hw = sky2->hw;
3629 unsigned port = sky2->port;
793b883e 3630
a84d0a3d
SH		 3631 spin_lock_bh(&sky2->phy_lock);
3632 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3633 hw->chip_id == CHIP_ID_YUKON_EX ||
3634 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3635 u16 pg;
793b883e
SH		 3636 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3637 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3638
a84d0a3d
SH		 3639 switch (mode) {
3640 case MO_LED_OFF:
3641 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3642 PHY_M_LEDC_LOS_CTRL(8) |
3643 PHY_M_LEDC_INIT_CTRL(8) |
3644 PHY_M_LEDC_STA1_CTRL(8) |
3645 PHY_M_LEDC_STA0_CTRL(8));
3646 break;
3647 case MO_LED_ON:
3648 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3649 PHY_M_LEDC_LOS_CTRL(9) |
3650 PHY_M_LEDC_INIT_CTRL(9) |
3651 PHY_M_LEDC_STA1_CTRL(9) |
3652 PHY_M_LEDC_STA0_CTRL(9));
3653 break;
3654 case MO_LED_BLINK:
3655 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3656 PHY_M_LEDC_LOS_CTRL(0xa) |
3657 PHY_M_LEDC_INIT_CTRL(0xa) |
3658 PHY_M_LEDC_STA1_CTRL(0xa) |
3659 PHY_M_LEDC_STA0_CTRL(0xa));
3660 break;
3661 case MO_LED_NORM:
3662 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3663 PHY_M_LEDC_LOS_CTRL(1) |
3664 PHY_M_LEDC_INIT_CTRL(8) |
3665 PHY_M_LEDC_STA1_CTRL(7) |
3666 PHY_M_LEDC_STA0_CTRL(7));
3667 }
793b883e 3668
a84d0a3d
SH		 3669 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3670 } else
7d2e3cb7 3671 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3672 PHY_M_LED_MO_DUP(mode) |
3673 PHY_M_LED_MO_10(mode) |
3674 PHY_M_LED_MO_100(mode) |
3675 PHY_M_LED_MO_1000(mode) |
3676 PHY_M_LED_MO_RX(mode) |
3677 PHY_M_LED_MO_TX(mode));
3678
3679 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3680}
3681
3682/* blink LED's for finding board */
3683static int sky2_phys_id(struct net_device *dev, u32 data)
3684{
3685 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3686 unsigned int i;
cd28ab6a 3687
a84d0a3d
SH		 3688 if (data == 0)
3689 data = UINT_MAX;
cd28ab6a 3690
a84d0a3d
SH		 3691 for (i = 0; i < data; i++) {
3692 sky2_led(sky2, MO_LED_ON);
3693 if (msleep_interruptible(500))
3694 break;
3695 sky2_led(sky2, MO_LED_OFF);
3696 if (msleep_interruptible(500))
3697 break;
793b883e 3698 }
a84d0a3d 3699 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3700
3701 return 0;
3702}
3703
3704static void sky2_get_pauseparam(struct net_device *dev,
3705 struct ethtool_pauseparam *ecmd)
3706{
3707 struct sky2_port *sky2 = netdev_priv(dev);
3708
16ad91e1
SH		 3709 switch (sky2->flow_mode) {
3710 case FC_NONE:
3711 ecmd->tx_pause = ecmd->rx_pause = 0;
3712 break;
3713 case FC_TX:
3714 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3715 break;
3716 case FC_RX:
3717 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3718 break;
3719 case FC_BOTH:
3720 ecmd->tx_pause = ecmd->rx_pause = 1;
3721 }
3722
0ea065e5
SH		 3723 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3724 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3725}
3726
3727static int sky2_set_pauseparam(struct net_device *dev,
3728 struct ethtool_pauseparam *ecmd)
3729{
3730 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3731
0ea065e5
SH		 3732 if (ecmd->autoneg == AUTONEG_ENABLE)
3733 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3734 else
3735 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3736
16ad91e1 3737 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3738
16ad91e1
SH		 3739 if (netif_running(dev))
3740 sky2_phy_reinit(sky2);
cd28ab6a 3741
2eaba1a2 3742 return 0;
cd28ab6a
SH		 3743}
3744
fb17358f
SH		 3745static int sky2_get_coalesce(struct net_device *dev,
3746 struct ethtool_coalesce *ecmd)
3747{
3748 struct sky2_port *sky2 = netdev_priv(dev);
3749 struct sky2_hw *hw = sky2->hw;
3750
3751 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3752 ecmd->tx_coalesce_usecs = 0;
3753 else {
3754 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3755 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3756 }
3757 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3758
3759 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3760 ecmd->rx_coalesce_usecs = 0;
3761 else {
3762 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3763 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3764 }
3765 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3766
3767 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3768 ecmd->rx_coalesce_usecs_irq = 0;
3769 else {
3770 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3771 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3772 }
3773
3774 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3775
3776 return 0;
3777}
3778
3779/* Note: this affect both ports */
3780static int sky2_set_coalesce(struct net_device *dev,
3781 struct ethtool_coalesce *ecmd)
3782{
3783 struct sky2_port *sky2 = netdev_priv(dev);
3784 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3785 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3786
77b3d6a2
SH		 3787 if (ecmd->tx_coalesce_usecs > tmax ||
3788 ecmd->rx_coalesce_usecs > tmax ||
3789 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3790 return -EINVAL;
3791
ee5f68fe 3792 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
fb17358f 3793 return -EINVAL;
ff81fbbe 3794 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3795 return -EINVAL;
ff81fbbe 3796 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3797 return -EINVAL;
3798
3799 if (ecmd->tx_coalesce_usecs == 0)
3800 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3801 else {
3802 sky2_write32(hw, STAT_TX_TIMER_INI,
3803 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3804 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3805 }
3806 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3807
3808 if (ecmd->rx_coalesce_usecs == 0)
3809 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3810 else {
3811 sky2_write32(hw, STAT_LEV_TIMER_INI,
3812 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3813 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3814 }
3815 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3816
3817 if (ecmd->rx_coalesce_usecs_irq == 0)
3818 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3819 else {
d28d4870 3820 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3821 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3822 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3823 }
3824 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3825 return 0;
3826}
3827
793b883e
SH		 3828static void sky2_get_ringparam(struct net_device *dev,
3829 struct ethtool_ringparam *ering)
3830{
3831 struct sky2_port *sky2 = netdev_priv(dev);
3832
3833 ering->rx_max_pending = RX_MAX_PENDING;
3834 ering->rx_mini_max_pending = 0;
3835 ering->rx_jumbo_max_pending = 0;
ee5f68fe 3836 ering->tx_max_pending = TX_MAX_PENDING;
793b883e
SH		 3837
3838 ering->rx_pending = sky2->rx_pending;
3839 ering->rx_mini_pending = 0;
3840 ering->rx_jumbo_pending = 0;
3841 ering->tx_pending = sky2->tx_pending;
3842}
3843
3844static int sky2_set_ringparam(struct net_device *dev,
3845 struct ethtool_ringparam *ering)
3846{
3847 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 3848
3849 if (ering->rx_pending > RX_MAX_PENDING ||
3850 ering->rx_pending < 8 ||
ee5f68fe
SH		 3851 ering->tx_pending < TX_MIN_PENDING ||
3852 ering->tx_pending > TX_MAX_PENDING)
793b883e
SH		 3853 return -EINVAL;
3854
af18d8b8 3855 sky2_detach(dev);
793b883e
SH		 3856
3857 sky2->rx_pending = ering->rx_pending;
3858 sky2->tx_pending = ering->tx_pending;
ee5f68fe 3859 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
793b883e 3860
af18d8b8 3861 return sky2_reattach(dev);
793b883e
SH		 3862}
3863
793b883e
SH		 3864static int sky2_get_regs_len(struct net_device *dev)
3865{
6e4cbb34 3866 return 0x4000;
793b883e
SH		 3867}
3868
c32bbff8
MM		 3869static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
3870{
3871 /* This complicated switch statement is to make sure and
3872 * only access regions that are unreserved.
3873 * Some blocks are only valid on dual port cards.
3874 */
3875 switch (b) {
3876 /* second port */
3877 case 5: /* Tx Arbiter 2 */
3878 case 9: /* RX2 */
3879 case 14 ... 15: /* TX2 */
3880 case 17: case 19: /* Ram Buffer 2 */
3881 case 22 ... 23: /* Tx Ram Buffer 2 */
3882 case 25: /* Rx MAC Fifo 1 */
3883 case 27: /* Tx MAC Fifo 2 */
3884 case 31: /* GPHY 2 */
3885 case 40 ... 47: /* Pattern Ram 2 */
3886 case 52: case 54: /* TCP Segmentation 2 */
3887 case 112 ... 116: /* GMAC 2 */
3888 return hw->ports > 1;
3889
3890 case 0: /* Control */
3891 case 2: /* Mac address */
3892 case 4: /* Tx Arbiter 1 */
3893 case 7: /* PCI express reg */
3894 case 8: /* RX1 */
3895 case 12 ... 13: /* TX1 */
3896 case 16: case 18:/* Rx Ram Buffer 1 */
3897 case 20 ... 21: /* Tx Ram Buffer 1 */
3898 case 24: /* Rx MAC Fifo 1 */
3899 case 26: /* Tx MAC Fifo 1 */
3900 case 28 ... 29: /* Descriptor and status unit */
3901 case 30: /* GPHY 1*/
3902 case 32 ... 39: /* Pattern Ram 1 */
3903 case 48: case 50: /* TCP Segmentation 1 */
3904 case 56 ... 60: /* PCI space */
3905 case 80 ... 84: /* GMAC 1 */
3906 return 1;
3907
3908 default:
3909 return 0;
3910 }
3911}
3912
793b883e
SH		 3913/*
3914 * Returns copy of control register region
3ead5db7 3915 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3916 */
3917static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3918 void *p)
3919{
3920 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3921 const void __iomem *io = sky2->hw->regs;
295b54c4 3922 unsigned int b;
793b883e
SH		 3923
3924 regs->version = 1;
793b883e 3925
295b54c4 3926 for (b = 0; b < 128; b++) {
c32bbff8
MM		 3927 /* skip poisonous diagnostic ram region in block 3 */
3928 if (b == 3)
295b54c4 3929 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
c32bbff8 3930 else if (sky2_reg_access_ok(sky2->hw, b))
295b54c4 3931 memcpy_fromio(p, io, 128);
c32bbff8 3932 else
295b54c4 3933 memset(p, 0, 128);
3ead5db7 3934
295b54c4
SH		 3935 p += 128;
3936 io += 128;
3937 }
793b883e 3938}
cd28ab6a 3939
b628ed98
SH		 3940/* In order to do Jumbo packets on these chips, need to turn off the
3941 * transmit store/forward. Therefore checksum offload won't work.
3942 */
3943static int no_tx_offload(struct net_device *dev)
3944{
3945 const struct sky2_port *sky2 = netdev_priv(dev);
3946 const struct sky2_hw *hw = sky2->hw;
3947
69161611 3948 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3949}
3950
3951static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3952{
3953 if (data && no_tx_offload(dev))
3954 return -EINVAL;
3955
3956 return ethtool_op_set_tx_csum(dev, data);
3957}
3958
3959
3960static int sky2_set_tso(struct net_device *dev, u32 data)
3961{
3962 if (data && no_tx_offload(dev))
3963 return -EINVAL;
3964
3965 return ethtool_op_set_tso(dev, data);
3966}
3967
f4331a6d
SH		 3968static int sky2_get_eeprom_len(struct net_device *dev)
3969{
3970 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3971 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3972 u16 reg2;
3973
b32f40c4 3974 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3975 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3976}
3977
1413235c 3978static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 3979{
1413235c 3980 unsigned long start = jiffies;
f4331a6d 3981
1413235c
SH		 3982 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3983 /* Can take up to 10.6 ms for write */
3984 if (time_after(jiffies, start + HZ/4)) {
3985 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3986 return -ETIMEDOUT;
3987 }
3988 mdelay(1);
3989 }
167f53d0 3990
1413235c
SH		 3991 return 0;
3992}
167f53d0 3993
1413235c
SH		 3994static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3995 u16 offset, size_t length)
3996{
3997 int rc = 0;
3998
3999 while (length > 0) {
4000 u32 val;
4001
4002 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4003 rc = sky2_vpd_wait(hw, cap, 0);
4004 if (rc)
4005 break;
4006
4007 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4008
4009 memcpy(data, &val, min(sizeof(val), length));
4010 offset += sizeof(u32);
4011 data += sizeof(u32);
4012 length -= sizeof(u32);
4013 }
4014
4015 return rc;
f4331a6d
SH		 4016}
4017
1413235c
SH		 4018static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4019 u16 offset, unsigned int length)
f4331a6d 4020{
1413235c
SH		 4021 unsigned int i;
4022 int rc = 0;
4023
4024 for (i = 0; i < length; i += sizeof(u32)) {
4025 u32 val = *(u32 *)(data + i);
4026
4027 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4028 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4029
4030 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4031 if (rc)
4032 break;
4033 }
4034 return rc;
f4331a6d
SH		 4035}
4036
4037static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4038 u8 *data)
4039{
4040 struct sky2_port *sky2 = netdev_priv(dev);
4041 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4042
4043 if (!cap)
4044 return -EINVAL;
4045
4046 eeprom->magic = SKY2_EEPROM_MAGIC;
4047
1413235c 4048 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4049}
4050
4051static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4052 u8 *data)
4053{
4054 struct sky2_port *sky2 = netdev_priv(dev);
4055 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4056
4057 if (!cap)
4058 return -EINVAL;
4059
4060 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4061 return -EINVAL;
4062
1413235c
SH		 4063 /* Partial writes not supported */
4064 if ((eeprom->offset & 3) || (eeprom->len & 3))
4065 return -EINVAL;
f4331a6d 4066
1413235c 4067 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4068}
4069
4070
7282d491 4071static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 4072 .get_settings = sky2_get_settings,
4073 .set_settings = sky2_set_settings,
4074 .get_drvinfo = sky2_get_drvinfo,
4075 .get_wol = sky2_get_wol,
4076 .set_wol = sky2_set_wol,
4077 .get_msglevel = sky2_get_msglevel,
4078 .set_msglevel = sky2_set_msglevel,
4079 .nway_reset = sky2_nway_reset,
4080 .get_regs_len = sky2_get_regs_len,
4081 .get_regs = sky2_get_regs,
4082 .get_link = ethtool_op_get_link,
4083 .get_eeprom_len = sky2_get_eeprom_len,
4084 .get_eeprom = sky2_get_eeprom,
4085 .set_eeprom = sky2_set_eeprom,
f4331a6d 4086 .set_sg = ethtool_op_set_sg,
f4331a6d 4087 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 4088 .set_tso = sky2_set_tso,
4089 .get_rx_csum = sky2_get_rx_csum,
4090 .set_rx_csum = sky2_set_rx_csum,
4091 .get_strings = sky2_get_strings,
4092 .get_coalesce = sky2_get_coalesce,
4093 .set_coalesce = sky2_set_coalesce,
4094 .get_ringparam = sky2_get_ringparam,
4095 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 4096 .get_pauseparam = sky2_get_pauseparam,
4097 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 4098 .phys_id = sky2_phys_id,
b9f2c044 4099 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 4100 .get_ethtool_stats = sky2_get_ethtool_stats,
4101};
4102
3cf26753
SH		 4103#ifdef CONFIG_SKY2_DEBUG
4104
4105static struct dentry *sky2_debug;
4106
e4c2abe2
SH		 4107
4108/*
4109 * Read and parse the first part of Vital Product Data
4110 */
4111#define VPD_SIZE 128
4112#define VPD_MAGIC 0x82
4113
4114static const struct vpd_tag {
4115 char tag[2];
4116 char *label;
4117} vpd_tags[] = {
4118 { "PN", "Part Number" },
4119 { "EC", "Engineering Level" },
4120 { "MN", "Manufacturer" },
4121 { "SN", "Serial Number" },
4122 { "YA", "Asset Tag" },
4123 { "VL", "First Error Log Message" },
4124 { "VF", "Second Error Log Message" },
4125 { "VB", "Boot Agent ROM Configuration" },
4126 { "VE", "EFI UNDI Configuration" },
4127};
4128
4129static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4130{
4131 size_t vpd_size;
4132 loff_t offs;
4133 u8 len;
4134 unsigned char *buf;
4135 u16 reg2;
4136
4137 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4138 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4139
4140 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4141 buf = kmalloc(vpd_size, GFP_KERNEL);
4142 if (!buf) {
4143 seq_puts(seq, "no memory!\n");
4144 return;
4145 }
4146
4147 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4148 seq_puts(seq, "VPD read failed\n");
4149 goto out;
4150 }
4151
4152 if (buf[0] != VPD_MAGIC) {
4153 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4154 goto out;
4155 }
4156 len = buf[1];
4157 if (len == 0 || len > vpd_size - 4) {
4158 seq_printf(seq, "Invalid id length: %d\n", len);
4159 goto out;
4160 }
4161
4162 seq_printf(seq, "%.*s\n", len, buf + 3);
4163 offs = len + 3;
4164
4165 while (offs < vpd_size - 4) {
4166 int i;
4167
4168 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4169 break;
4170 len = buf[offs + 2];
4171 if (offs + len + 3 >= vpd_size)
4172 break;
4173
4174 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4175 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4176 seq_printf(seq, " %s: %.*s\n",
4177 vpd_tags[i].label, len, buf + offs + 3);
4178 break;
4179 }
4180 }
4181 offs += len + 3;
4182 }
4183out:
4184 kfree(buf);
4185}
4186
3cf26753
SH		 4187static int sky2_debug_show(struct seq_file *seq, void *v)
4188{
4189 struct net_device *dev = seq->private;
4190 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4191 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4192 unsigned port = sky2->port;
4193 unsigned idx, last;
4194 int sop;
4195
e4c2abe2 4196 sky2_show_vpd(seq, hw);
3cf26753 4197
e4c2abe2 4198 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4199 sky2_read32(hw, B0_ISRC),
4200 sky2_read32(hw, B0_IMSK),
4201 sky2_read32(hw, B0_Y2_SP_ICR));
4202
e4c2abe2
SH		 4203 if (!netif_running(dev)) {
4204 seq_printf(seq, "network not running\n");
4205 return 0;
4206 }
4207
bea3348e 4208 napi_disable(&hw->napi);
3cf26753
SH		 4209 last = sky2_read16(hw, STAT_PUT_IDX);
4210
4211 if (hw->st_idx == last)
4212 seq_puts(seq, "Status ring (empty)\n");
4213 else {
4214 seq_puts(seq, "Status ring\n");
4215 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4216 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4217 const struct sky2_status_le *le = hw->st_le + idx;
4218 seq_printf(seq, "[%d] %#x %d %#x\n",
4219 idx, le->opcode, le->length, le->status);
4220 }
4221 seq_puts(seq, "\n");
4222 }
4223
4224 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4225 sky2->tx_cons, sky2->tx_prod,
4226 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4227 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4228
4229 /* Dump contents of tx ring */
4230 sop = 1;
ee5f68fe
SH		 4231 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4232 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
3cf26753
SH		 4233 const struct sky2_tx_le *le = sky2->tx_le + idx;
4234 u32 a = le32_to_cpu(le->addr);
4235
4236 if (sop)
4237 seq_printf(seq, "%u:", idx);
4238 sop = 0;
4239
4240 switch(le->opcode & ~HW_OWNER) {
4241 case OP_ADDR64:
4242 seq_printf(seq, " %#x:", a);
4243 break;
4244 case OP_LRGLEN:
4245 seq_printf(seq, " mtu=%d", a);
4246 break;
4247 case OP_VLAN:
4248 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4249 break;
4250 case OP_TCPLISW:
4251 seq_printf(seq, " csum=%#x", a);
4252 break;
4253 case OP_LARGESEND:
4254 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4255 break;
4256 case OP_PACKET:
4257 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4258 break;
4259 case OP_BUFFER:
4260 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4261 break;
4262 default:
4263 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4264 a, le16_to_cpu(le->length));
4265 }
4266
4267 if (le->ctrl & EOP) {
4268 seq_putc(seq, '\n');
4269 sop = 1;
4270 }
4271 }
4272
4273 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4274 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4275 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4276 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4277
d1d08d12 4278 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4279 napi_enable(&hw->napi);
3cf26753
SH		 4280 return 0;
4281}
4282
4283static int sky2_debug_open(struct inode *inode, struct file *file)
4284{
4285 return single_open(file, sky2_debug_show, inode->i_private);
4286}
4287
4288static const struct file_operations sky2_debug_fops = {
4289 .owner = THIS_MODULE,
4290 .open = sky2_debug_open,
4291 .read = seq_read,
4292 .llseek = seq_lseek,
4293 .release = single_release,
4294};
4295
4296/*
4297 * Use network device events to create/remove/rename
4298 * debugfs file entries
4299 */
4300static int sky2_device_event(struct notifier_block *unused,
4301 unsigned long event, void *ptr)
4302{
4303 struct net_device *dev = ptr;
5b296bc9 4304 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4305
1436b301 4306 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4307 return NOTIFY_DONE;
3cf26753 4308
5b296bc9
SH		 4309 switch(event) {
4310 case NETDEV_CHANGENAME:
4311 if (sky2->debugfs) {
4312 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4313 sky2_debug, dev->name);
4314 }
4315 break;
3cf26753 4316
5b296bc9
SH		 4317 case NETDEV_GOING_DOWN:
4318 if (sky2->debugfs) {
4319 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4320 dev->name);
4321 debugfs_remove(sky2->debugfs);
4322 sky2->debugfs = NULL;
3cf26753 4323 }
5b296bc9
SH		 4324 break;
4325
4326 case NETDEV_UP:
4327 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4328 sky2_debug, dev,
4329 &sky2_debug_fops);
4330 if (IS_ERR(sky2->debugfs))
4331 sky2->debugfs = NULL;
3cf26753
SH		 4332 }
4333
4334 return NOTIFY_DONE;
4335}
4336
4337static struct notifier_block sky2_notifier = {
4338 .notifier_call = sky2_device_event,
4339};
4340
4341
4342static __init void sky2_debug_init(void)
4343{
4344 struct dentry *ent;
4345
4346 ent = debugfs_create_dir("sky2", NULL);
4347 if (!ent || IS_ERR(ent))
4348 return;
4349
4350 sky2_debug = ent;
4351 register_netdevice_notifier(&sky2_notifier);
4352}
4353
4354static __exit void sky2_debug_cleanup(void)
4355{
4356 if (sky2_debug) {
4357 unregister_netdevice_notifier(&sky2_notifier);
4358 debugfs_remove(sky2_debug);
4359 sky2_debug = NULL;
4360 }
4361}
4362
4363#else
4364#define sky2_debug_init()
4365#define sky2_debug_cleanup()
4366#endif
4367
1436b301
SH		 4368/* Two copies of network device operations to handle special case of
4369 not allowing netpoll on second port */
4370static const struct net_device_ops sky2_netdev_ops[2] = {
4371 {
4372 .ndo_open = sky2_up,
4373 .ndo_stop = sky2_down,
00829823 4374 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4375 .ndo_do_ioctl = sky2_ioctl,
4376 .ndo_validate_addr = eth_validate_addr,
4377 .ndo_set_mac_address = sky2_set_mac_address,
4378 .ndo_set_multicast_list = sky2_set_multicast,
4379 .ndo_change_mtu = sky2_change_mtu,
4380 .ndo_tx_timeout = sky2_tx_timeout,
4381#ifdef SKY2_VLAN_TAG_USED
4382 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4383#endif
4384#ifdef CONFIG_NET_POLL_CONTROLLER
4385 .ndo_poll_controller = sky2_netpoll,
4386#endif
4387 },
4388 {
4389 .ndo_open = sky2_up,
4390 .ndo_stop = sky2_down,
00829823 4391 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4392 .ndo_do_ioctl = sky2_ioctl,
4393 .ndo_validate_addr = eth_validate_addr,
4394 .ndo_set_mac_address = sky2_set_mac_address,
4395 .ndo_set_multicast_list = sky2_set_multicast,
4396 .ndo_change_mtu = sky2_change_mtu,
4397 .ndo_tx_timeout = sky2_tx_timeout,
4398#ifdef SKY2_VLAN_TAG_USED
4399 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4400#endif
4401 },
4402};
3cf26753 4403
cd28ab6a
SH		 4404/* Initialize network device */
4405static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4406 unsigned port,
be63a21c 4407 int highmem, int wol)
cd28ab6a
SH		 4408{
4409 struct sky2_port *sky2;
4410 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4411
4412 if (!dev) {
898eb71c 4413 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4414 return NULL;
4415 }
4416
cd28ab6a 4417 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4418 dev->irq = hw->pdev->irq;
cd28ab6a 4419 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4420 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4421 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4422
4423 sky2 = netdev_priv(dev);
4424 sky2->netdev = dev;
4425 sky2->hw = hw;
4426 sky2->msg_enable = netif_msg_init(debug, default_msg);
4427
cd28ab6a 4428 /* Auto speed and flow control */
0ea065e5
SH		 4429 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4430 if (hw->chip_id != CHIP_ID_YUKON_XL)
4431 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4432
16ad91e1
SH		 4433 sky2->flow_mode = FC_BOTH;
4434
cd28ab6a
SH		 4435 sky2->duplex = -1;
4436 sky2->speed = -1;
4437 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4438 sky2->wol = wol;
75d070c5 4439
e07b1aa8 4440 spin_lock_init(&sky2->phy_lock);
ee5f68fe 4441
793b883e 4442 sky2->tx_pending = TX_DEF_PENDING;
ee5f68fe 4443 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
290d4de5 4444 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4445
4446 hw->dev[port] = dev;
4447
4448 sky2->port = port;
4449
4a50a876 4450 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4451 if (highmem)
4452 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4453
d1f13708 4454#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4455 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4456 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4457 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4458 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4459 }
d1f13708 4460#endif
4461
cd28ab6a 4462 /* read the mac address */
793b883e 4463 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4464 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4465
cd28ab6a
SH		 4466 return dev;
4467}
4468
28bd181a 4469static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4470{
4471 const struct sky2_port *sky2 = netdev_priv(dev);
4472
4473 if (netif_msg_probe(sky2))
e174961c
JB		 4474 printk(KERN_INFO PFX "%s: addr %pM\n",
4475 dev->name, dev->dev_addr);
cd28ab6a
SH		 4476}
4477
fb2690a9 4478/* Handle software interrupt used during MSI test */
7d12e780 4479static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4480{
4481 struct sky2_hw *hw = dev_id;
4482 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4483
4484 if (status == 0)
4485 return IRQ_NONE;
4486
4487 if (status & Y2_IS_IRQ_SW) {
ea76e635 4488 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4489 wake_up(&hw->msi_wait);
4490 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4491 }
4492 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4493
4494 return IRQ_HANDLED;
4495}
4496
4497/* Test interrupt path by forcing a a software IRQ */
4498static int __devinit sky2_test_msi(struct sky2_hw *hw)
4499{
4500 struct pci_dev *pdev = hw->pdev;
4501 int err;
4502
bb507fe1 4503 init_waitqueue_head (&hw->msi_wait);
4504
fb2690a9
SH		 4505 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4506
b0a20ded 4507 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4508 if (err) {
b02a9258 4509 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4510 return err;
4511 }
4512
fb2690a9 4513 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4514 sky2_read8(hw, B0_CTST);
fb2690a9 4515
ea76e635 4516 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4517
ea76e635 4518 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4519 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4520 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4521 "switching to INTx mode.\n");
fb2690a9
SH		 4522
4523 err = -EOPNOTSUPP;
4524 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4525 }
4526
4527 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4528 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4529
4530 free_irq(pdev->irq, hw);
4531
4532 return err;
4533}
4534
c7127a34
SH		 4535/* This driver supports yukon2 chipset only */
4536static const char *sky2_name(u8 chipid, char *buf, int sz)
4537{
4538 const char *name[] = {
4539 "XL", /* 0xb3 */
4540 "EC Ultra", /* 0xb4 */
4541 "Extreme", /* 0xb5 */
4542 "EC", /* 0xb6 */
4543 "FE", /* 0xb7 */
4544 "FE+", /* 0xb8 */
4545 "Supreme", /* 0xb9 */
0ce8b98d 4546 "UL 2", /* 0xba */
0f5aac70
SH		 4547 "Unknown", /* 0xbb */
4548 "Optima", /* 0xbc */
c7127a34
SH		 4549 };
4550
dae3a511 4551 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
c7127a34
SH		 4552 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4553 else
4554 snprintf(buf, sz, "(chip %#x)", chipid);
4555 return buf;
4556}
4557
cd28ab6a
SH		 4558static int __devinit sky2_probe(struct pci_dev *pdev,
4559 const struct pci_device_id *ent)
4560{
7f60c64b 4561 struct net_device *dev;
cd28ab6a 4562 struct sky2_hw *hw;
be63a21c 4563 int err, using_dac = 0, wol_default;
3834507d 4564 u32 reg;
c7127a34 4565 char buf1[16];
cd28ab6a 4566
793b883e
SH		 4567 err = pci_enable_device(pdev);
4568 if (err) {
b02a9258 4569 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4570 goto err_out;
4571 }
4572
6cc90a5a
SH		 4573 /* Get configuration information
4574 * Note: only regular PCI config access once to test for HW issues
4575 * other PCI access through shared memory for speed and to
4576 * avoid MMCONFIG problems.
4577 */
4578 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4579 if (err) {
4580 dev_err(&pdev->dev, "PCI read config failed\n");
4581 goto err_out;
4582 }
4583
4584 if (~reg == 0) {
4585 dev_err(&pdev->dev, "PCI configuration read error\n");
4586 goto err_out;
4587 }
4588
793b883e
SH		 4589 err = pci_request_regions(pdev, DRV_NAME);
4590 if (err) {
b02a9258 4591 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4592 goto err_out_disable;
cd28ab6a
SH		 4593 }
4594
4595 pci_set_master(pdev);
4596
d1f3d4dd 4597 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4598 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4599 using_dac = 1;
6a35528a 4600 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4601 if (err < 0) {
b02a9258
SH		 4602 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4603 "for consistent allocations\n");
d1f3d4dd
SH		 4604 goto err_out_free_regions;
4605 }
d1f3d4dd 4606 } else {
284901a9 4607 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4608 if (err) {
b02a9258 4609 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4610 goto err_out_free_regions;
4611 }
4612 }
d1f3d4dd 4613
3834507d
SH		 4614
4615#ifdef __BIG_ENDIAN
4616 /* The sk98lin vendor driver uses hardware byte swapping but
4617 * this driver uses software swapping.
4618 */
4619 reg &= ~PCI_REV_DESC;
4620 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4621 if (err) {
4622 dev_err(&pdev->dev, "PCI write config failed\n");
4623 goto err_out_free_regions;
4624 }
4625#endif
4626
9d731d77 4627 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4628
cd28ab6a 4629 err = -ENOMEM;
66466797
SH		 4630
4631 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4632 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
cd28ab6a 4633 if (!hw) {
b02a9258 4634 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4635 goto err_out_free_regions;
4636 }
4637
cd28ab6a 4638 hw->pdev = pdev;
66466797 4639 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
cd28ab6a
SH		 4640
4641 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4642 if (!hw->regs) {
b02a9258 4643 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4644 goto err_out_free_hw;
4645 }
4646
08c06d8a 4647 /* ring for status responses */
167f53d0 4648 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4649 if (!hw->st_le)
4650 goto err_out_iounmap;
4651
e3173832 4652 err = sky2_init(hw);
cd28ab6a 4653 if (err)
793b883e 4654 goto err_out_iounmap;
cd28ab6a 4655
c844d483
SH		 4656 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4657 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4658
e3173832
SH		 4659 sky2_reset(hw);
4660
be63a21c 4661 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4662 if (!dev) {
4663 err = -ENOMEM;
cd28ab6a 4664 goto err_out_free_pci;
7f60c64b 4665 }
cd28ab6a 4666
9fa1b1f3
SH		 4667 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4668 err = sky2_test_msi(hw);
4669 if (err == -EOPNOTSUPP)
4670 pci_disable_msi(pdev);
4671 else if (err)
4672 goto err_out_free_netdev;
4673 }
4674
793b883e
SH		 4675 err = register_netdev(dev);
4676 if (err) {
b02a9258 4677 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4678 goto err_out_free_netdev;
4679 }
4680
33cb7d33
BP		 4681 netif_carrier_off(dev);
4682
6de16237
SH		 4683 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4684
ea76e635
SH		 4685 err = request_irq(pdev->irq, sky2_intr,
4686 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
66466797 4687 hw->irq_name, hw);
9fa1b1f3 4688 if (err) {
b02a9258 4689 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4690 goto err_out_unregister;
4691 }
4692 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4693 napi_enable(&hw->napi);
9fa1b1f3 4694
cd28ab6a
SH		 4695 sky2_show_addr(dev);
4696
7f60c64b 4697 if (hw->ports > 1) {
4698 struct net_device *dev1;
4699
ca519274 4700 err = -ENOMEM;
be63a21c 4701 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
ca519274
SH		 4702 if (dev1 && (err = register_netdev(dev1)) == 0)
4703 sky2_show_addr(dev1);
4704 else {
b02a9258
SH		 4705 dev_warn(&pdev->dev,
4706 "register of second port failed (%d)\n", err);
cd28ab6a 4707 hw->dev[1] = NULL;
ca519274
SH		 4708 hw->ports = 1;
4709 if (dev1)
4710 free_netdev(dev1);
4711 }
cd28ab6a
SH		 4712 }
4713
32c2c300 4714 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4715 INIT_WORK(&hw->restart_work, sky2_restart);
4716
793b883e 4717 pci_set_drvdata(pdev, hw);
1ae861e6 4718 pdev->d3_delay = 150;
793b883e 4719
cd28ab6a
SH		 4720 return 0;
4721
793b883e 4722err_out_unregister:
ea76e635 4723 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4724 pci_disable_msi(pdev);
793b883e 4725 unregister_netdev(dev);
cd28ab6a
SH		 4726err_out_free_netdev:
4727 free_netdev(dev);
cd28ab6a 4728err_out_free_pci:
793b883e 4729 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4730 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4731err_out_iounmap:
4732 iounmap(hw->regs);
4733err_out_free_hw:
4734 kfree(hw);
4735err_out_free_regions:
4736 pci_release_regions(pdev);
44a1d2e5 4737err_out_disable:
cd28ab6a 4738 pci_disable_device(pdev);
cd28ab6a 4739err_out:
549a68c3 4740 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4741 return err;
4742}
4743
4744static void __devexit sky2_remove(struct pci_dev *pdev)
4745{
793b883e 4746 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4747 int i;
cd28ab6a 4748
793b883e 4749 if (!hw)
cd28ab6a
SH		 4750 return;
4751
32c2c300 4752 del_timer_sync(&hw->watchdog_timer);
6de16237 4753 cancel_work_sync(&hw->restart_work);
d27ed387 4754
b877fe28 4755 for (i = hw->ports-1; i >= 0; --i)
6de16237 4756 unregister_netdev(hw->dev[i]);
81906791 4757
d27ed387 4758 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4759
ae306cca
SH		 4760 sky2_power_aux(hw);
4761
793b883e 4762 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4763 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4764
4765 free_irq(pdev->irq, hw);
ea76e635 4766 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4767 pci_disable_msi(pdev);
793b883e 4768 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4769 pci_release_regions(pdev);
4770 pci_disable_device(pdev);
793b883e 4771
b877fe28 4772 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4773 free_netdev(hw->dev[i]);
4774
cd28ab6a
SH		 4775 iounmap(hw->regs);
4776 kfree(hw);
5afa0a9c 4777
cd28ab6a
SH		 4778 pci_set_drvdata(pdev, NULL);
4779}
4780
4781#ifdef CONFIG_PM
4782static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4783{
793b883e 4784 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4785 int i, wol = 0;
cd28ab6a 4786
549a68c3
SH		 4787 if (!hw)
4788 return 0;
4789
063a0b38
SH		 4790 del_timer_sync(&hw->watchdog_timer);
4791 cancel_work_sync(&hw->restart_work);
4792
19720737 4793 rtnl_lock();
f05267e7 4794 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4795 struct net_device *dev = hw->dev[i];
e3173832 4796 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4797
af18d8b8 4798 sky2_detach(dev);
e3173832
SH		 4799
4800 if (sky2->wol)
4801 sky2_wol_init(sky2);
4802
4803 wol |= sky2->wol;
cd28ab6a
SH		 4804 }
4805
8ab8fca2 4806 sky2_write32(hw, B0_IMSK, 0);
6de16237 4807 napi_disable(&hw->napi);
ae306cca 4808 sky2_power_aux(hw);
19720737 4809 rtnl_unlock();
e3173832 4810
d374c1c1 4811 pci_save_state(pdev);
e3173832 4812 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4813 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4814
2ccc99b7 4815 return 0;
cd28ab6a
SH		 4816}
4817
4818static int sky2_resume(struct pci_dev *pdev)
4819{
793b883e 4820 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4821 int i, err;
cd28ab6a 4822
549a68c3
SH		 4823 if (!hw)
4824 return 0;
4825
f71eb1a2
SH		 4826 err = pci_set_power_state(pdev, PCI_D0);
4827 if (err)
4828 goto out;
ae306cca
SH		 4829
4830 err = pci_restore_state(pdev);
4831 if (err)
4832 goto out;
4833
cd28ab6a 4834 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4835
4836 /* Re-enable all clocks */
05745c4a
SH		 4837 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4838 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4839 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4840 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4841
e3173832 4842 sky2_reset(hw);
8ab8fca2 4843 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4844 napi_enable(&hw->napi);
8ab8fca2 4845
af18d8b8 4846 rtnl_lock();
f05267e7 4847 for (i = 0; i < hw->ports; i++) {
af18d8b8
SH		 4848 err = sky2_reattach(hw->dev[i]);
4849 if (err)
4850 goto out;
cd28ab6a 4851 }
af18d8b8 4852 rtnl_unlock();
eb35cf60 4853
ae306cca 4854 return 0;
08c06d8a 4855out:
af18d8b8
SH		 4856 rtnl_unlock();
4857
b02a9258 4858 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4859 pci_disable_device(pdev);
08c06d8a 4860 return err;
cd28ab6a
SH		 4861}
4862#endif
4863
e3173832
SH		 4864static void sky2_shutdown(struct pci_dev *pdev)
4865{
4866 struct sky2_hw *hw = pci_get_drvdata(pdev);
4867 int i, wol = 0;
4868
549a68c3
SH		 4869 if (!hw)
4870 return;
4871
19720737 4872 rtnl_lock();
5c0d6b34 4873 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4874
4875 for (i = 0; i < hw->ports; i++) {
4876 struct net_device *dev = hw->dev[i];
4877 struct sky2_port *sky2 = netdev_priv(dev);
4878
4879 if (sky2->wol) {
4880 wol = 1;
4881 sky2_wol_init(sky2);
4882 }
4883 }
4884
4885 if (wol)
4886 sky2_power_aux(hw);
19720737 4887 rtnl_unlock();
e3173832
SH		 4888
4889 pci_enable_wake(pdev, PCI_D3hot, wol);
4890 pci_enable_wake(pdev, PCI_D3cold, wol);
4891
4892 pci_disable_device(pdev);
f71eb1a2 4893 pci_set_power_state(pdev, PCI_D3hot);
e3173832
SH		 4894}
4895
cd28ab6a 4896static struct pci_driver sky2_driver = {
793b883e
SH		 4897 .name = DRV_NAME,
4898 .id_table = sky2_id_table,
4899 .probe = sky2_probe,
4900 .remove = __devexit_p(sky2_remove),
cd28ab6a 4901#ifdef CONFIG_PM
793b883e
SH		 4902 .suspend = sky2_suspend,
4903 .resume = sky2_resume,
cd28ab6a 4904#endif
e3173832 4905 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4906};
4907
4908static int __init sky2_init_module(void)
4909{
c844d483
SH		 4910 pr_info(PFX "driver version " DRV_VERSION "\n");
4911
3cf26753 4912 sky2_debug_init();
50241c4c 4913 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4914}
4915
4916static void __exit sky2_cleanup_module(void)
4917{
4918 pci_unregister_driver(&sky2_driver);
3cf26753 4919 sky2_debug_cleanup();
cd28ab6a
SH		 4920}
4921
4922module_init(sky2_init_module);
4923module_exit(sky2_cleanup_module);
4924
4925MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4926MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4927MODULE_LICENSE("GPL");
5f4f9dc1 4928MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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