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sky2: dual port NAPI problem
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
ef743d33 41#include <linux/mii.h>
cd28ab6a
SH		 42
43#include <asm/irq.h>
44
d1f13708 45#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
46#define SKY2_VLAN_TAG_USED 1
47#endif
48
cd28ab6a
SH		 49#include "sky2.h"
50
51#define DRV_NAME "sky2"
52c89cac 52#define DRV_VERSION "1.10"
cd28ab6a
SH		 53#define PFX DRV_NAME " "
54
55/*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
14d0263f 58 * similar to Tigon3.
cd28ab6a
SH		 59 */
60
14d0263f 61#define RX_LE_SIZE 1024
cd28ab6a 62#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 63#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 64#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 65#define RX_SKB_ALIGN 8
22e11703 66#define RX_BUF_WRITE 16
793b883e
SH		 67
68#define TX_RING_SIZE 512
69#define TX_DEF_PENDING (TX_RING_SIZE - 1)
70#define TX_MIN_PENDING 64
b19666d9 71#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 72
793b883e 73#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 74#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 75#define TX_WATCHDOG (5 * HZ)
76#define NAPI_WEIGHT 64
77#define PHY_RETRIES 1000
78
cb5d9547
SH		 79#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
80
cd28ab6a 81static const u32 default_msg =
793b883e
SH		 82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 85
793b883e 86static int debug = -1; /* defaults above */
cd28ab6a
SH		 87module_param(debug, int, 0);
88MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
14d0263f 90static int copybreak __read_mostly = 128;
bdb5c58e
SH		 91module_param(copybreak, int, 0);
92MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
fb2690a9
SH		 94static int disable_msi = 0;
95module_param(disable_msi, int, 0);
96MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
e561a83b 98static int idle_timeout = 0;
01bd7564 99module_param(idle_timeout, int, 0);
e561a83b 100MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 101
cd28ab6a 102static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
e5b74c7d
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
cd28ab6a
SH		 129 { 0 }
130};
793b883e 131
cd28ab6a
SH		 132MODULE_DEVICE_TABLE(pci, sky2_id_table);
133
134/* Avoid conditionals by using array */
135static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
136static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 137static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 138
92f965e8
SH		 139/* This driver supports yukon2 chipset only */
140static const char *yukon2_name[] = {
141 "XL", /* 0xb3 */
142 "EC Ultra", /* 0xb4 */
143 "UNKNOWN", /* 0xb5 */
144 "EC", /* 0xb6 */
145 "FE", /* 0xb7 */
793b883e
SH		 146};
147
793b883e 148/* Access to external PHY */
ef743d33 149static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 150{
151 int i;
152
153 gma_write16(hw, port, GM_SMI_DATA, val);
154 gma_write16(hw, port, GM_SMI_CTRL,
155 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
156
157 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 158 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 159 return 0;
793b883e 160 udelay(1);
cd28ab6a 161 }
ef743d33 162
793b883e 163 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 164 return -ETIMEDOUT;
cd28ab6a
SH		 165}
166
ef743d33 167static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 168{
169 int i;
170
793b883e 171 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 172 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
173
174 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33 175 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
176 *val = gma_read16(hw, port, GM_SMI_DATA);
177 return 0;
178 }
179
793b883e 180 udelay(1);
cd28ab6a
SH		 181 }
182
ef743d33 183 return -ETIMEDOUT;
184}
185
186static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
187{
188 u16 v;
189
190 if (__gm_phy_read(hw, port, reg, &v) != 0)
191 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
192 return v;
cd28ab6a
SH		 193}
194
2ccc99b7 195static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
5afa0a9c 196{
197 u16 power_control;
5afa0a9c 198 int vaux;
5afa0a9c 199
200 pr_debug("sky2_set_power_state %d\n", state);
201 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
202
56a645cc 203 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 204 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c 205 (power_control & PCI_PM_CAP_PME_D3cold);
206
56a645cc 207 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c 208
209 power_control |= PCI_PM_CTRL_PME_STATUS;
210 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
211
212 switch (state) {
213 case PCI_D0:
214 /* switch power to VCC (WA for VAUX problem) */
215 sky2_write8(hw, B0_POWER_CTRL,
216 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
217
218 /* disable Core Clock Division, */
219 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
220
221 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
222 /* enable bits are inverted */
223 sky2_write8(hw, B2_Y2_CLK_GATE,
224 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
225 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
226 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
227 else
228 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
229
977bdf06 230 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
d3bcfbeb 231 u32 reg1;
232
56a645cc
SH		 233 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
234 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 235 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 236 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
237 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 238 }
239
5afa0a9c 240 break;
241
242 case PCI_D3hot:
243 case PCI_D3cold:
5afa0a9c 244 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
245 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
246 else
247 /* enable bits are inverted */
248 sky2_write8(hw, B2_Y2_CLK_GATE,
249 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
250 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
251 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
252
253 /* switch power to VAUX */
254 if (vaux && state != PCI_D3cold)
255 sky2_write8(hw, B0_POWER_CTRL,
256 (PC_VAUX_ENA | PC_VCC_ENA |
257 PC_VAUX_ON | PC_VCC_OFF));
258 break;
259 default:
260 printk(KERN_ERR PFX "Unknown power state %d\n", state);
5afa0a9c 261 }
262
56a645cc 263 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c 264 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
5afa0a9c 265}
266
d3bcfbeb 267static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 268{
269 u16 reg;
270
271 /* disable all GMAC IRQ's */
272 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
273 /* disable PHY IRQs */
274 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 275
cd28ab6a
SH		 276 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
277 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
278 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
279 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
280
281 reg = gma_read16(hw, port, GM_RX_CTRL);
282 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
283 gma_write16(hw, port, GM_RX_CTRL, reg);
284}
285
16ad91e1
SH		 286/* flow control to advertise bits */
287static const u16 copper_fc_adv[] = {
288 [FC_NONE] = 0,
289 [FC_TX] = PHY_M_AN_ASP,
290 [FC_RX] = PHY_M_AN_PC,
291 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
292};
293
294/* flow control to advertise bits when using 1000BaseX */
295static const u16 fiber_fc_adv[] = {
296 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
297 [FC_TX] = PHY_M_P_ASYM_MD_X,
298 [FC_RX] = PHY_M_P_SYM_MD_X,
299 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
300};
301
302/* flow control to GMA disable bits */
303static const u16 gm_fc_disable[] = {
304 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
305 [FC_TX] = GM_GPCR_FC_RX_DIS,
306 [FC_RX] = GM_GPCR_FC_TX_DIS,
307 [FC_BOTH] = 0,
308};
309
310
cd28ab6a
SH		 311static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
312{
313 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 314 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 315
ed6d32c7 316 if (sky2->autoneg == AUTONEG_ENABLE &&
86a31a75 317 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 318 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
319
320 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 321 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 322 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
323
324 if (hw->chip_id == CHIP_ID_YUKON_EC)
325 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
326 else
327 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
328
329 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
330 }
331
332 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 333 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 334 if (hw->chip_id == CHIP_ID_YUKON_FE) {
335 /* enable automatic crossover */
336 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
337 } else {
338 /* disable energy detect */
339 ctrl &= ~PHY_M_PC_EN_DET_MSK;
340
341 /* enable automatic crossover */
342 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
343
344 if (sky2->autoneg == AUTONEG_ENABLE &&
ed6d32c7 345 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 346 ctrl &= ~PHY_M_PC_DSC_MSK;
347 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
348 }
349 }
cd28ab6a
SH		 350 } else {
351 /* workaround for deviation #4.88 (CRC errors) */
352 /* disable Automatic Crossover */
353
354 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 355 }
cd28ab6a 356
b89165f2
SH		 357 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
358
359 /* special setup for PHY 88E1112 Fiber */
360 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
361 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 362
b89165f2
SH		 363 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
364 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
365 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
366 ctrl &= ~PHY_M_MAC_MD_MSK;
367 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
368 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
369
370 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 371 /* select page 1 to access Fiber registers */
372 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 373
374 /* for SFP-module set SIGDET polarity to low */
375 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
376 ctrl |= PHY_M_FIB_SIGD_POL;
377 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
cd28ab6a 378 }
b89165f2
SH		 379
380 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 381 }
382
7800fddc 383 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 384 ct1000 = 0;
385 adv = PHY_AN_CSMA;
2eaba1a2 386 reg = 0;
cd28ab6a
SH		 387
388 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 389 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 390 if (sky2->advertising & ADVERTISED_1000baseT_Full)
391 ct1000 |= PHY_M_1000C_AFD;
392 if (sky2->advertising & ADVERTISED_1000baseT_Half)
393 ct1000 |= PHY_M_1000C_AHD;
394 if (sky2->advertising & ADVERTISED_100baseT_Full)
395 adv |= PHY_M_AN_100_FD;
396 if (sky2->advertising & ADVERTISED_100baseT_Half)
397 adv |= PHY_M_AN_100_HD;
398 if (sky2->advertising & ADVERTISED_10baseT_Full)
399 adv |= PHY_M_AN_10_FD;
400 if (sky2->advertising & ADVERTISED_10baseT_Half)
401 adv |= PHY_M_AN_10_HD;
709c6e7b 402
16ad91e1 403 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 404 } else { /* special defines for FIBER (88E1040S only) */
405 if (sky2->advertising & ADVERTISED_1000baseT_Full)
406 adv |= PHY_M_AN_1000X_AFD;
407 if (sky2->advertising & ADVERTISED_1000baseT_Half)
408 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 409
16ad91e1 410 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 411 }
cd28ab6a
SH		 412
413 /* Restart Auto-negotiation */
414 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
415 } else {
416 /* forced speed/duplex settings */
417 ct1000 = PHY_M_1000C_MSE;
418
2eaba1a2
SH		 419 /* Disable auto update for duplex flow control and speed */
420 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 421
422 switch (sky2->speed) {
423 case SPEED_1000:
424 ctrl |= PHY_CT_SP1000;
2eaba1a2 425 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 426 break;
427 case SPEED_100:
428 ctrl |= PHY_CT_SP100;
2eaba1a2 429 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 430 break;
431 }
432
2eaba1a2
SH		 433 if (sky2->duplex == DUPLEX_FULL) {
434 reg |= GM_GPCR_DUP_FULL;
435 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 436 } else if (sky2->speed < SPEED_1000)
437 sky2->flow_mode = FC_NONE;
2eaba1a2 438
2eaba1a2 439
16ad91e1 440 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 441
442 /* Forward pause packets to GMAC? */
16ad91e1 443 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 444 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
445 else
446 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 447 }
448
2eaba1a2
SH		 449 gma_write16(hw, port, GM_GP_CTRL, reg);
450
cd28ab6a
SH		 451 if (hw->chip_id != CHIP_ID_YUKON_FE)
452 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
453
454 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
455 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
456
457 /* Setup Phy LED's */
458 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
459 ledover = 0;
460
461 switch (hw->chip_id) {
462 case CHIP_ID_YUKON_FE:
463 /* on 88E3082 these bits are at 11..9 (shifted left) */
464 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
465
466 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
467
468 /* delete ACT LED control bits */
469 ctrl &= ~PHY_M_FELP_LED1_MSK;
470 /* change ACT LED control to blink mode */
471 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
472 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
473 break;
474
475 case CHIP_ID_YUKON_XL:
793b883e 476 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 477
478 /* select page 3 to access LED control register */
479 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
480
481 /* set LED Function Control register */
ed6d32c7
SH		 482 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
483 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
484 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
485 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
486 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 487
488 /* set Polarity Control register */
489 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 490 (PHY_M_POLC_LS1_P_MIX(4) |
491 PHY_M_POLC_IS0_P_MIX(4) |
492 PHY_M_POLC_LOS_CTRL(2) |
493 PHY_M_POLC_INIT_CTRL(2) |
494 PHY_M_POLC_STA1_CTRL(2) |
495 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 496
497 /* restore page register */
793b883e 498 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 499 break;
ed6d32c7
SH		 500 case CHIP_ID_YUKON_EC_U:
501 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
502
503 /* select page 3 to access LED control register */
504 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
505
506 /* set LED Function Control register */
507 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
508 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
509 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
510 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
511 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
512
513 /* set Blink Rate in LED Timer Control Register */
514 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
515 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
516 /* restore page register */
517 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
518 break;
cd28ab6a
SH		 519
520 default:
521 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
522 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
523 /* turn off the Rx LED (LED_RX) */
0efdf262 524 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 525 }
526
ed6d32c7 527 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 528 /* apply fixes in PHY AFE */
ed6d32c7
SH		 529 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
530 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
531
977bdf06 532 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 533 gm_phy_write(hw, port, 0x18, 0xaa99);
534 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 535
977bdf06 536 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 537 gm_phy_write(hw, port, 0x18, 0xa204);
538 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 539
540 /* set page register to 0 */
ed6d32c7 541 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
977bdf06
SH		 542 } else {
543 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 544
977bdf06
SH		 545 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
546 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 547 ledover |= PHY_M_LED_MO_100;
977bdf06 548 }
cd28ab6a 549
977bdf06
SH		 550 if (ledover)
551 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
552
553 }
2eaba1a2 554
d571b694 555 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 556 if (sky2->autoneg == AUTONEG_ENABLE)
557 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
558 else
559 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
560}
561
d3bcfbeb 562static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
563{
564 u32 reg1;
565 static const u32 phy_power[]
566 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
567
568 /* looks like this XL is back asswards .. */
569 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
570 onoff = !onoff;
571
572 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
573
574 if (onoff)
575 /* Turn off phy power saving */
576 reg1 &= ~phy_power[port];
577 else
578 reg1 |= phy_power[port];
579
580 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 581 sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb 582 udelay(100);
583}
584
1b537565
SH		 585/* Force a renegotiation */
586static void sky2_phy_reinit(struct sky2_port *sky2)
587{
e07b1aa8 588 spin_lock_bh(&sky2->phy_lock);
1b537565 589 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 590 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 591}
592
cd28ab6a
SH		 593static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
594{
595 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
596 u16 reg;
597 int i;
598 const u8 *addr = hw->dev[port]->dev_addr;
599
42eeea01 600 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
601 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 602
603 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
604
793b883e 605 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 606 /* WA DEV_472 -- looks like crossed wires on port 2 */
607 /* clear GMAC 1 Control reset */
608 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
609 do {
610 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
611 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
612 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
613 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
614 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
615 }
616
793b883e 617 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 618
2eaba1a2
SH		 619 /* Enable Transmit FIFO Underrun */
620 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
621
e07b1aa8 622 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 623 sky2_phy_init(hw, port);
e07b1aa8 624 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 625
626 /* MIB clear */
627 reg = gma_read16(hw, port, GM_PHY_ADDR);
628 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
629
43f2f104
SH		 630 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
631 gma_read16(hw, port, i);
cd28ab6a
SH		 632 gma_write16(hw, port, GM_PHY_ADDR, reg);
633
634 /* transmit control */
635 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
636
637 /* receive control reg: unicast + multicast + no FCS */
638 gma_write16(hw, port, GM_RX_CTRL,
793b883e 639 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 640
641 /* transmit flow control */
642 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
643
644 /* transmit parameter */
645 gma_write16(hw, port, GM_TX_PARAM,
646 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
647 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
648 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
649 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
650
651 /* serial mode register */
652 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 653 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 654
6b1a3aef 655 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 656 reg |= GM_SMOD_JUMBO_ENA;
657
658 gma_write16(hw, port, GM_SERIAL_MODE, reg);
659
cd28ab6a
SH		 660 /* virtual address for data */
661 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
662
793b883e
SH		 663 /* physical address: used for pause frames */
664 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
665
666 /* ignore counter overflows */
cd28ab6a
SH		 667 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
668 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
669 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
670
671 /* Configure Rx MAC FIFO */
672 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 673 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
674 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 675
d571b694 676 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 677 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 678
8df9a876
SH		 679 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
680 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 681
682 /* Configure Tx MAC FIFO */
683 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
684 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 685
686 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
8df9a876 687 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 688 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
689 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
690 /* set Tx GMAC FIFO Almost Empty Threshold */
691 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
692 /* Disable Store & Forward mode for TX */
693 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
694 }
695 }
696
cd28ab6a
SH		 697}
698
67712901
SH		 699/* Assign Ram Buffer allocation to queue */
700static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 701{
67712901
SH		 702 u32 end;
703
704 /* convert from K bytes to qwords used for hw register */
705 start *= 1024/8;
706 space *= 1024/8;
707 end = start + space - 1;
793b883e 708
cd28ab6a
SH		 709 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
710 sky2_write32(hw, RB_ADDR(q, RB_START), start);
711 sky2_write32(hw, RB_ADDR(q, RB_END), end);
712 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
713 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
714
715 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 716 u32 tp = space - space/4;
793b883e 717
1c28f6ba
SH		 718 /* On receive queue's set the thresholds
719 * give receiver priority when > 3/4 full
720 * send pause when down to 2K
721 */
722 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
723 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 724
1c28f6ba
SH		 725 tp = space - 2048/8;
726 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
727 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 728 } else {
729 /* Enable store & forward on Tx queue's because
730 * Tx FIFO is only 1K on Yukon
731 */
732 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
733 }
734
735 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 736 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 737}
738
cd28ab6a 739/* Setup Bus Memory Interface */
af4ed7e6 740static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 741{
742 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
743 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
744 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 745 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 746}
747
cd28ab6a
SH		 748/* Setup prefetch unit registers. This is the interface between
749 * hardware and driver list elements
750 */
8cc048e3 751static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 752 u64 addr, u32 last)
753{
cd28ab6a
SH		 754 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
755 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
756 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
757 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
758 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
759 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 760
761 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 762}
763
793b883e
SH		 764static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
765{
766 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
767
cb5d9547 768 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 769 le->ctrl = 0;
793b883e
SH		 770 return le;
771}
cd28ab6a 772
291ea614
SH		 773static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
774 struct sky2_tx_le *le)
775{
776 return sky2->tx_ring + (le - sky2->tx_le);
777}
778
290d4de5
SH		 779/* Update chip's next pointer */
780static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 781{
98232f85 782 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
762c2de2 783 wmb();
98232f85 784 sky2_write16(hw, q, idx);
785 sky2_read16(hw, q);
cd28ab6a
SH		 786}
787
793b883e 788
cd28ab6a
SH		 789static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
790{
791 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 792 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 793 le->ctrl = 0;
cd28ab6a
SH		 794 return le;
795}
796
a018e330 797/* Return high part of DMA address (could be 32 or 64 bit) */
798static inline u32 high32(dma_addr_t a)
799{
a036119f 800 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330 801}
802
14d0263f
SH		 803/* Build description to hardware for one receive segment */
804static void sky2_rx_add(struct sky2_port *sky2, u8 op,
805 dma_addr_t map, unsigned len)
cd28ab6a
SH		 806{
807 struct sky2_rx_le *le;
734d1868 808 u32 hi = high32(map);
cd28ab6a 809
793b883e 810 if (sky2->rx_addr64 != hi) {
cd28ab6a 811 le = sky2_next_rx(sky2);
793b883e 812 le->addr = cpu_to_le32(hi);
cd28ab6a 813 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 814 sky2->rx_addr64 = high32(map + len);
cd28ab6a 815 }
793b883e 816
cd28ab6a 817 le = sky2_next_rx(sky2);
734d1868
SH		 818 le->addr = cpu_to_le32((u32) map);
819 le->length = cpu_to_le16(len);
14d0263f 820 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 821}
822
14d0263f
SH		 823/* Build description to hardware for one possibly fragmented skb */
824static void sky2_rx_submit(struct sky2_port *sky2,
825 const struct rx_ring_info *re)
826{
827 int i;
828
829 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
830
831 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
832 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
833}
834
835
836static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
837 unsigned size)
838{
839 struct sk_buff *skb = re->skb;
840 int i;
841
842 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
843 pci_unmap_len_set(re, data_size, size);
844
845 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
846 re->frag_addr[i] = pci_map_page(pdev,
847 skb_shinfo(skb)->frags[i].page,
848 skb_shinfo(skb)->frags[i].page_offset,
849 skb_shinfo(skb)->frags[i].size,
850 PCI_DMA_FROMDEVICE);
851}
852
853static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
854{
855 struct sk_buff *skb = re->skb;
856 int i;
857
858 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
859 PCI_DMA_FROMDEVICE);
860
861 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
862 pci_unmap_page(pdev, re->frag_addr[i],
863 skb_shinfo(skb)->frags[i].size,
864 PCI_DMA_FROMDEVICE);
865}
793b883e 866
cd28ab6a
SH		 867/* Tell chip where to start receive checksum.
868 * Actually has two checksums, but set both same to avoid possible byte
869 * order problems.
870 */
793b883e 871static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 872{
873 struct sky2_rx_le *le;
874
cd28ab6a 875 le = sky2_next_rx(sky2);
f65b138c 876 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
cd28ab6a
SH		 877 le->ctrl = 0;
878 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 879
793b883e
SH		 880 sky2_write32(sky2->hw,
881 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
882 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 883
884}
885
6b1a3aef 886/*
887 * The RX Stop command will not work for Yukon-2 if the BMU does not
888 * reach the end of packet and since we can't make sure that we have
889 * incoming data, we must reset the BMU while it is not doing a DMA
890 * transfer. Since it is possible that the RX path is still active,
891 * the RX RAM buffer will be stopped first, so any possible incoming
892 * data will not trigger a DMA. After the RAM buffer is stopped, the
893 * BMU is polled until any DMA in progress is ended and only then it
894 * will be reset.
895 */
896static void sky2_rx_stop(struct sky2_port *sky2)
897{
898 struct sky2_hw *hw = sky2->hw;
899 unsigned rxq = rxqaddr[sky2->port];
900 int i;
901
902 /* disable the RAM Buffer receive queue */
903 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
904
905 for (i = 0; i < 0xffff; i++)
906 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
907 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
908 goto stopped;
909
910 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
911 sky2->netdev->name);
912stopped:
913 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
914
915 /* reset the Rx prefetch unit */
916 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
917}
793b883e 918
d571b694 919/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 920static void sky2_rx_clean(struct sky2_port *sky2)
921{
922 unsigned i;
923
924 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 925 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 926 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 927
928 if (re->skb) {
14d0263f 929 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 930 kfree_skb(re->skb);
931 re->skb = NULL;
932 }
933 }
934}
935
ef743d33 936/* Basic MII support */
937static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
938{
939 struct mii_ioctl_data *data = if_mii(ifr);
940 struct sky2_port *sky2 = netdev_priv(dev);
941 struct sky2_hw *hw = sky2->hw;
942 int err = -EOPNOTSUPP;
943
944 if (!netif_running(dev))
945 return -ENODEV; /* Phy still in reset */
946
d89e1343 947 switch (cmd) {
ef743d33 948 case SIOCGMIIPHY:
949 data->phy_id = PHY_ADDR_MARV;
950
951 /* fallthru */
952 case SIOCGMIIREG: {
953 u16 val = 0;
91c86df5 954
e07b1aa8 955 spin_lock_bh(&sky2->phy_lock);
ef743d33 956 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 957 spin_unlock_bh(&sky2->phy_lock);
91c86df5 958
ef743d33 959 data->val_out = val;
960 break;
961 }
962
963 case SIOCSMIIREG:
964 if (!capable(CAP_NET_ADMIN))
965 return -EPERM;
966
e07b1aa8 967 spin_lock_bh(&sky2->phy_lock);
ef743d33 968 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
969 data->val_in);
e07b1aa8 970 spin_unlock_bh(&sky2->phy_lock);
ef743d33 971 break;
972 }
973 return err;
974}
975
d1f13708 976#ifdef SKY2_VLAN_TAG_USED
977static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
978{
979 struct sky2_port *sky2 = netdev_priv(dev);
980 struct sky2_hw *hw = sky2->hw;
981 u16 port = sky2->port;
d1f13708 982
2bb8c262 983 netif_tx_lock_bh(dev);
d1f13708 984
985 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
986 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
987 sky2->vlgrp = grp;
988
2bb8c262 989 netif_tx_unlock_bh(dev);
d1f13708 990}
991
992static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
993{
994 struct sky2_port *sky2 = netdev_priv(dev);
995 struct sky2_hw *hw = sky2->hw;
996 u16 port = sky2->port;
d1f13708 997
2bb8c262 998 netif_tx_lock_bh(dev);
d1f13708 999
1000 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1001 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
1002 if (sky2->vlgrp)
1003 sky2->vlgrp->vlan_devices[vid] = NULL;
1004
2bb8c262 1005 netif_tx_unlock_bh(dev);
d1f13708 1006}
1007#endif
1008
82788c7a 1009/*
14d0263f
SH		 1010 * Allocate an skb for receiving. If the MTU is large enough
1011 * make the skb non-linear with a fragment list of pages.
1012 *
82788c7a
SH		 1013 * It appears the hardware has a bug in the FIFO logic that
1014 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86 1015 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1016 * aligned except if slab debugging is enabled.
82788c7a 1017 */
14d0263f 1018static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1019{
1020 struct sk_buff *skb;
14d0263f
SH		 1021 unsigned long p;
1022 int i;
82788c7a 1023
14d0263f
SH		 1024 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1025 if (!skb)
1026 goto nomem;
1027
1028 p = (unsigned long) skb->data;
1029 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1030
1031 for (i = 0; i < sky2->rx_nfrags; i++) {
1032 struct page *page = alloc_page(GFP_ATOMIC);
1033
1034 if (!page)
1035 goto free_partial;
1036 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1037 }
1038
1039 return skb;
14d0263f
SH		 1040free_partial:
1041 kfree_skb(skb);
1042nomem:
1043 return NULL;
82788c7a
SH		 1044}
1045
cd28ab6a
SH		 1046/*
1047 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1048 * Normal case this ends up creating one list element for skb
1049 * in the receive ring. Worst case if using large MTU and each
1050 * allocation falls on a different 64 bit region, that results
1051 * in 6 list elements per ring entry.
1052 * One element is used for checksum enable/disable, and one
1053 * extra to avoid wrap.
cd28ab6a 1054 */
6b1a3aef 1055static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1056{
6b1a3aef 1057 struct sky2_hw *hw = sky2->hw;
14d0263f 1058 struct rx_ring_info *re;
6b1a3aef 1059 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1060 unsigned i, size, space, thresh;
cd28ab6a 1061
6b1a3aef 1062 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1063 sky2_qset(hw, rxq);
977bdf06 1064
c3905bc4
SH		 1065 /* On PCI express lowering the watermark gives better performance */
1066 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1067 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1068
1069 /* These chips have no ram buffer?
1070 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1071 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1072 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1073 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
977bdf06 1074 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
977bdf06 1075
6b1a3aef 1076 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1077
1078 rx_set_checksum(sky2);
14d0263f
SH		 1079
1080 /* Space needed for frame data + headers rounded up */
1081 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1082 + 8;
1083
1084 /* Stopping point for hardware truncation */
1085 thresh = (size - 8) / sizeof(u32);
1086
1087 /* Account for overhead of skb - to avoid order > 0 allocation */
1088 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1089 + sizeof(struct skb_shared_info);
1090
1091 sky2->rx_nfrags = space >> PAGE_SHIFT;
1092 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1093
1094 if (sky2->rx_nfrags != 0) {
1095 /* Compute residue after pages */
1096 space = sky2->rx_nfrags << PAGE_SHIFT;
1097
1098 if (space < size)
1099 size -= space;
1100 else
1101 size = 0;
1102
1103 /* Optimize to handle small packets and headers */
1104 if (size < copybreak)
1105 size = copybreak;
1106 if (size < ETH_HLEN)
1107 size = ETH_HLEN;
1108 }
1109 sky2->rx_data_size = size;
1110
1111 /* Fill Rx ring */
793b883e 1112 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1113 re = sky2->rx_ring + i;
cd28ab6a 1114
14d0263f 1115 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1116 if (!re->skb)
1117 goto nomem;
1118
14d0263f
SH		 1119 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1120 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1121 }
1122
a1433ac4
SH		 1123 /*
1124 * The receiver hangs if it receives frames larger than the
1125 * packet buffer. As a workaround, truncate oversize frames, but
1126 * the register is limited to 9 bits, so if you do frames > 2052
1127 * you better get the MTU right!
1128 */
a1433ac4
SH		 1129 if (thresh > 0x1ff)
1130 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1131 else {
1132 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1133 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1134 }
1135
6b1a3aef 1136 /* Tell chip about available buffers */
1137 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1138 return 0;
1139nomem:
1140 sky2_rx_clean(sky2);
1141 return -ENOMEM;
1142}
1143
1144/* Bring up network interface. */
1145static int sky2_up(struct net_device *dev)
1146{
1147 struct sky2_port *sky2 = netdev_priv(dev);
1148 struct sky2_hw *hw = sky2->hw;
1149 unsigned port = sky2->port;
67712901 1150 u32 ramsize, imask;
ee7abb04 1151 int cap, err = -ENOMEM;
843a46f4 1152 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1153
ee7abb04
SH		 1154 /*
1155 * On dual port PCI-X card, there is an problem where status
1156 * can be received out of order due to split transactions
843a46f4 1157 */
ee7abb04
SH		 1158 if (otherdev && netif_running(otherdev) &&
1159 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1160 struct sky2_port *osky2 = netdev_priv(otherdev);
1161 u16 cmd;
1162
1163 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1164 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1165 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1166
1167 sky2->rx_csum = 0;
1168 osky2->rx_csum = 0;
1169 }
843a46f4 1170
cd28ab6a
SH		 1171 if (netif_msg_ifup(sky2))
1172 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1173
1174 /* must be power of 2 */
1175 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1176 TX_RING_SIZE *
1177 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1178 &sky2->tx_le_map);
1179 if (!sky2->tx_le)
1180 goto err_out;
1181
6cdbbdf3 1182 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1183 GFP_KERNEL);
1184 if (!sky2->tx_ring)
1185 goto err_out;
1186 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1187
1188 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1189 &sky2->rx_le_map);
1190 if (!sky2->rx_le)
1191 goto err_out;
1192 memset(sky2->rx_le, 0, RX_LE_BYTES);
1193
291ea614 1194 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1195 GFP_KERNEL);
1196 if (!sky2->rx_ring)
1197 goto err_out;
1198
d3bcfbeb 1199 sky2_phy_power(hw, port, 1);
1200
cd28ab6a
SH		 1201 sky2_mac_init(hw, port);
1202
67712901
SH		 1203 /* Register is number of 4K blocks on internal RAM buffer. */
1204 ramsize = sky2_read8(hw, B2_E_0) * 4;
1205 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1c28f6ba 1206
67712901
SH		 1207 if (ramsize > 0) {
1208 u32 rxspace;
cd28ab6a 1209
67712901
SH		 1210 if (ramsize < 16)
1211 rxspace = ramsize / 2;
1212 else
1213 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1214
67712901
SH		 1215 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1216 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1217
1218 /* Make sure SyncQ is disabled */
1219 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1220 RB_RST_SET);
1221 }
793b883e 1222
af4ed7e6 1223 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1224
977bdf06 1225 /* Set almost empty threshold */
c2716fb4
SH		 1226 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1227 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
977bdf06 1228 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1229
6b1a3aef 1230 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1231 TX_RING_SIZE - 1);
cd28ab6a 1232
6b1a3aef 1233 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1234 if (err)
1235 goto err_out;
1236
cd28ab6a 1237 /* Enable interrupts from phy/mac for port */
e07b1aa8 1238 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1239 imask |= portirq_msk[port];
e07b1aa8
SH		 1240 sky2_write32(hw, B0_IMSK, imask);
1241
cd28ab6a
SH		 1242 return 0;
1243
1244err_out:
1b537565 1245 if (sky2->rx_le) {
cd28ab6a
SH		 1246 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1247 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1248 sky2->rx_le = NULL;
1249 }
1250 if (sky2->tx_le) {
cd28ab6a
SH		 1251 pci_free_consistent(hw->pdev,
1252 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1253 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1254 sky2->tx_le = NULL;
1255 }
1256 kfree(sky2->tx_ring);
1257 kfree(sky2->rx_ring);
cd28ab6a 1258
1b537565
SH		 1259 sky2->tx_ring = NULL;
1260 sky2->rx_ring = NULL;
cd28ab6a
SH		 1261 return err;
1262}
1263
793b883e
SH		 1264/* Modular subtraction in ring */
1265static inline int tx_dist(unsigned tail, unsigned head)
1266{
cb5d9547 1267 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1268}
cd28ab6a 1269
793b883e
SH		 1270/* Number of list elements available for next tx */
1271static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1272{
793b883e 1273 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1274}
1275
793b883e 1276/* Estimate of number of transmit list elements required */
28bd181a 1277static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1278{
793b883e
SH		 1279 unsigned count;
1280
1281 count = sizeof(dma_addr_t) / sizeof(u32);
1282 count += skb_shinfo(skb)->nr_frags * count;
1283
89114afd 1284 if (skb_is_gso(skb))
793b883e
SH		 1285 ++count;
1286
84fa7933 1287 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1288 ++count;
1289
1290 return count;
cd28ab6a
SH		 1291}
1292
793b883e
SH		 1293/*
1294 * Put one packet in ring for transmit.
1295 * A single packet can generate multiple list elements, and
1296 * the number of ring elements will probably be less than the number
1297 * of list elements used.
1298 */
cd28ab6a
SH		 1299static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1300{
1301 struct sky2_port *sky2 = netdev_priv(dev);
1302 struct sky2_hw *hw = sky2->hw;
d1f13708 1303 struct sky2_tx_le *le = NULL;
6cdbbdf3 1304 struct tx_ring_info *re;
cd28ab6a
SH		 1305 unsigned i, len;
1306 dma_addr_t mapping;
1307 u32 addr64;
1308 u16 mss;
1309 u8 ctrl;
1310
2bb8c262
SH		 1311 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1312 return NETDEV_TX_BUSY;
cd28ab6a 1313
793b883e 1314 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1315 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1316 dev->name, sky2->tx_prod, skb->len);
1317
cd28ab6a
SH		 1318 len = skb_headlen(skb);
1319 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1320 addr64 = high32(mapping);
793b883e 1321
a018e330 1322 /* Send high bits if changed or crosses boundary */
1323 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1324 le = get_tx_le(sky2);
f65b138c 1325 le->addr = cpu_to_le32(addr64);
793b883e 1326 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1327 sky2->tx_addr64 = high32(mapping + len);
793b883e 1328 }
cd28ab6a
SH		 1329
1330 /* Check for TCP Segmentation Offload */
7967168c 1331 mss = skb_shinfo(skb)->gso_size;
793b883e 1332 if (mss != 0) {
cd28ab6a
SH		 1333 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1334 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1335 mss += ETH_HLEN;
1336
e07560cd 1337 if (mss != sky2->tx_last_mss) {
1338 le = get_tx_le(sky2);
f65b138c 1339 le->addr = cpu_to_le32(mss);
e07560cd 1340 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1341 sky2->tx_last_mss = mss;
1342 }
cd28ab6a
SH		 1343 }
1344
cd28ab6a 1345 ctrl = 0;
d1f13708 1346#ifdef SKY2_VLAN_TAG_USED
1347 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1348 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1349 if (!le) {
1350 le = get_tx_le(sky2);
f65b138c 1351 le->addr = 0;
d1f13708 1352 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1353 } else
1354 le->opcode |= OP_VLAN;
1355 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1356 ctrl |= INS_VLAN;
1357 }
1358#endif
1359
1360 /* Handle TCP checksum offload */
84fa7933 1361 if (skb->ip_summed == CHECKSUM_PARTIAL) {
f65b138c
SH		 1362 unsigned offset = skb->h.raw - skb->data;
1363 u32 tcpsum;
1364
1365 tcpsum = offset << 16; /* sum start */
ff1dcadb 1366 tcpsum |= offset + skb->csum_offset; /* sum write */
cd28ab6a
SH		 1367
1368 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1369 if (skb->nh.iph->protocol == IPPROTO_UDP)
1370 ctrl |= UDPTCP;
1371
f65b138c
SH		 1372 if (tcpsum != sky2->tx_tcpsum) {
1373 sky2->tx_tcpsum = tcpsum;
1d179332 1374
1375 le = get_tx_le(sky2);
f65b138c 1376 le->addr = cpu_to_le32(tcpsum);
1d179332 1377 le->length = 0; /* initial checksum value */
1378 le->ctrl = 1; /* one packet */
1379 le->opcode = OP_TCPLISW | HW_OWNER;
1380 }
cd28ab6a
SH		 1381 }
1382
1383 le = get_tx_le(sky2);
f65b138c 1384 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1385 le->length = cpu_to_le16(len);
1386 le->ctrl = ctrl;
793b883e 1387 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1388
291ea614 1389 re = tx_le_re(sky2, le);
cd28ab6a 1390 re->skb = skb;
6cdbbdf3 1391 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1392 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1393
1394 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1395 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1396
1397 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1398 frag->size, PCI_DMA_TODEVICE);
a036119f 1399 addr64 = high32(mapping);
793b883e
SH		 1400 if (addr64 != sky2->tx_addr64) {
1401 le = get_tx_le(sky2);
f65b138c 1402 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1403 le->ctrl = 0;
1404 le->opcode = OP_ADDR64 | HW_OWNER;
1405 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1406 }
1407
1408 le = get_tx_le(sky2);
f65b138c 1409 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1410 le->length = cpu_to_le16(frag->size);
1411 le->ctrl = ctrl;
793b883e 1412 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1413
291ea614
SH		 1414 re = tx_le_re(sky2, le);
1415 re->skb = skb;
1416 pci_unmap_addr_set(re, mapaddr, mapping);
1417 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1418 }
6cdbbdf3 1419
cd28ab6a
SH		 1420 le->ctrl |= EOP;
1421
97bda706 1422 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1423 netif_stop_queue(dev);
b19666d9 1424
290d4de5 1425 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1426
cd28ab6a
SH		 1427 dev->trans_start = jiffies;
1428 return NETDEV_TX_OK;
1429}
1430
cd28ab6a 1431/*
793b883e
SH		 1432 * Free ring elements from starting at tx_cons until "done"
1433 *
1434 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1435 * buffers so make sure not to free skb to early.
cd28ab6a 1436 */
d11c13e7 1437static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1438{
d11c13e7 1439 struct net_device *dev = sky2->netdev;
af2a58ac 1440 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1441 unsigned idx;
cd28ab6a 1442
0e3ff6aa 1443 BUG_ON(done >= TX_RING_SIZE);
2224795d 1444
291ea614
SH		 1445 for (idx = sky2->tx_cons; idx != done;
1446 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1447 struct sky2_tx_le *le = sky2->tx_le + idx;
1448 struct tx_ring_info *re = sky2->tx_ring + idx;
1449
1450 switch(le->opcode & ~HW_OWNER) {
1451 case OP_LARGESEND:
1452 case OP_PACKET:
1453 pci_unmap_single(pdev,
1454 pci_unmap_addr(re, mapaddr),
1455 pci_unmap_len(re, maplen),
1456 PCI_DMA_TODEVICE);
af2a58ac 1457 break;
291ea614
SH		 1458 case OP_BUFFER:
1459 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1460 pci_unmap_len(re, maplen),
734d1868 1461 PCI_DMA_TODEVICE);
291ea614
SH		 1462 break;
1463 }
1464
1465 if (le->ctrl & EOP) {
1466 if (unlikely(netif_msg_tx_done(sky2)))
1467 printk(KERN_DEBUG "%s: tx done %u\n",
1468 dev->name, idx);
794b2bd2 1469 dev_kfree_skb_any(re->skb);
cd28ab6a
SH		 1470 }
1471
291ea614 1472 le->opcode = 0; /* paranoia */
793b883e 1473 }
793b883e 1474
291ea614 1475 sky2->tx_cons = idx;
22e11703 1476 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1477 netif_wake_queue(dev);
cd28ab6a
SH		 1478}
1479
1480/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1481static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1482{
2bb8c262
SH		 1483 struct sky2_port *sky2 = netdev_priv(dev);
1484
1485 netif_tx_lock_bh(dev);
d11c13e7 1486 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1487 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1488}
1489
1490/* Network shutdown */
1491static int sky2_down(struct net_device *dev)
1492{
1493 struct sky2_port *sky2 = netdev_priv(dev);
1494 struct sky2_hw *hw = sky2->hw;
1495 unsigned port = sky2->port;
1496 u16 ctrl;
e07b1aa8 1497 u32 imask;
cd28ab6a 1498
1b537565
SH		 1499 /* Never really got started! */
1500 if (!sky2->tx_le)
1501 return 0;
1502
cd28ab6a
SH		 1503 if (netif_msg_ifdown(sky2))
1504 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1505
018d1c66 1506 /* Stop more packets from being queued */
cd28ab6a
SH		 1507 netif_stop_queue(dev);
1508
ebc646f6
SH		 1509 /* Disable port IRQ */
1510 imask = sky2_read32(hw, B0_IMSK);
1511 imask &= ~portirq_msk[port];
1512 sky2_write32(hw, B0_IMSK, imask);
1513
25d82d7a
SH		 1514 /*
1515 * Both ports share the NAPI poll on port 0, so if necessary undo the
1516 * the disable that is done in dev_close.
1517 */
1518 if (sky2->port == 0 && hw->ports > 1)
1519 netif_poll_enable(dev);
1520
d3bcfbeb 1521 sky2_gmac_reset(hw, port);
793b883e 1522
cd28ab6a
SH		 1523 /* Stop transmitter */
1524 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1525 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1526
1527 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1528 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a 1529
c2716fb4
SH		 1530 /* WA for dev. #4.209 */
1531 if (hw->chip_id == CHIP_ID_YUKON_EC_U
8df9a876 1532 && (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
c2716fb4
SH		 1533 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1534 sky2->speed != SPEED_1000 ?
1535 TX_STFW_ENA : TX_STFW_DIS);
1536
cd28ab6a 1537 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1538 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1539 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1540
1541 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1542
1543 /* Workaround shared GMAC reset */
793b883e
SH		 1544 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1545 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1546 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1547
1548 /* Disable Force Sync bit and Enable Alloc bit */
1549 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1550 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1551
1552 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1553 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1554 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1555
1556 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1557 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1558 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1559
1560 /* Reset the Tx prefetch units */
1561 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1562 PREF_UNIT_RST_SET);
1563
1564 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1565
6b1a3aef 1566 sky2_rx_stop(sky2);
cd28ab6a
SH		 1567
1568 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1569 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1570
d3bcfbeb 1571 sky2_phy_power(hw, port, 0);
1572
d571b694 1573 /* turn off LED's */
cd28ab6a
SH		 1574 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1575
018d1c66 1576 synchronize_irq(hw->pdev->irq);
1577
2bb8c262 1578 sky2_tx_clean(dev);
cd28ab6a
SH		 1579 sky2_rx_clean(sky2);
1580
1581 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1582 sky2->rx_le, sky2->rx_le_map);
1583 kfree(sky2->rx_ring);
1584
1585 pci_free_consistent(hw->pdev,
1586 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1587 sky2->tx_le, sky2->tx_le_map);
1588 kfree(sky2->tx_ring);
1589
1b537565
SH		 1590 sky2->tx_le = NULL;
1591 sky2->rx_le = NULL;
1592
1593 sky2->rx_ring = NULL;
1594 sky2->tx_ring = NULL;
1595
cd28ab6a
SH		 1596 return 0;
1597}
1598
1599static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1600{
b89165f2 1601 if (!sky2_is_copper(hw))
793b883e
SH		 1602 return SPEED_1000;
1603
cd28ab6a
SH		 1604 if (hw->chip_id == CHIP_ID_YUKON_FE)
1605 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1606
1607 switch (aux & PHY_M_PS_SPEED_MSK) {
1608 case PHY_M_PS_SPEED_1000:
1609 return SPEED_1000;
1610 case PHY_M_PS_SPEED_100:
1611 return SPEED_100;
1612 default:
1613 return SPEED_10;
1614 }
1615}
1616
1617static void sky2_link_up(struct sky2_port *sky2)
1618{
1619 struct sky2_hw *hw = sky2->hw;
1620 unsigned port = sky2->port;
1621 u16 reg;
16ad91e1
SH		 1622 static const char *fc_name[] = {
1623 [FC_NONE] = "none",
1624 [FC_TX] = "tx",
1625 [FC_RX] = "rx",
1626 [FC_BOTH] = "both",
1627 };
cd28ab6a 1628
cd28ab6a 1629 /* enable Rx/Tx */
2eaba1a2 1630 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1631 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1632 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1633
1634 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1635
1636 netif_carrier_on(sky2->netdev);
1637 netif_wake_queue(sky2->netdev);
1638
1639 /* Turn on link LED */
793b883e 1640 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1641 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1642
ed6d32c7 1643 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
793b883e 1644 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1645 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1646
1647 switch(sky2->speed) {
1648 case SPEED_10:
1649 led |= PHY_M_LEDC_INIT_CTRL(7);
1650 break;
1651
1652 case SPEED_100:
1653 led |= PHY_M_LEDC_STA1_CTRL(7);
1654 break;
1655
1656 case SPEED_1000:
1657 led |= PHY_M_LEDC_STA0_CTRL(7);
1658 break;
1659 }
793b883e
SH		 1660
1661 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1662 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1663 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1664 }
1665
cd28ab6a
SH		 1666 if (netif_msg_link(sky2))
1667 printk(KERN_INFO PFX
d571b694 1668 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1669 sky2->netdev->name, sky2->speed,
1670 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1671 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1672}
1673
1674static void sky2_link_down(struct sky2_port *sky2)
1675{
1676 struct sky2_hw *hw = sky2->hw;
1677 unsigned port = sky2->port;
1678 u16 reg;
1679
1680 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1681
1682 reg = gma_read16(hw, port, GM_GP_CTRL);
1683 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1684 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1685
16ad91e1 1686 if (sky2->flow_status == FC_RX) {
cd28ab6a
SH		 1687 /* restore Asymmetric Pause bit */
1688 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1689 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1690 | PHY_M_AN_ASP);
cd28ab6a
SH		 1691 }
1692
cd28ab6a
SH		 1693 netif_carrier_off(sky2->netdev);
1694 netif_stop_queue(sky2->netdev);
1695
1696 /* Turn on link LED */
1697 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1698
1699 if (netif_msg_link(sky2))
1700 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1701
cd28ab6a
SH		 1702 sky2_phy_init(hw, port);
1703}
1704
16ad91e1
SH		 1705static enum flow_control sky2_flow(int rx, int tx)
1706{
1707 if (rx)
1708 return tx ? FC_BOTH : FC_RX;
1709 else
1710 return tx ? FC_TX : FC_NONE;
1711}
1712
793b883e
SH		 1713static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1714{
1715 struct sky2_hw *hw = sky2->hw;
1716 unsigned port = sky2->port;
1717 u16 lpa;
1718
1719 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1720
1721 if (lpa & PHY_M_AN_RF) {
1722 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1723 return -1;
1724 }
1725
793b883e
SH		 1726 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1727 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1728 sky2->netdev->name);
1729 return -1;
1730 }
1731
793b883e 1732 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1733 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e
SH		 1734
1735 /* Pause bits are offset (9..8) */
ed6d32c7 1736 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
793b883e
SH		 1737 aux >>= 6;
1738
16ad91e1
SH		 1739 sky2->flow_status = sky2_flow(aux & PHY_M_PS_RX_P_EN,
1740 aux & PHY_M_PS_TX_P_EN);
793b883e 1741
16ad91e1 1742 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
2eaba1a2 1743 && hw->chip_id != CHIP_ID_YUKON_EC_U)
16ad91e1 1744 sky2->flow_status = FC_NONE;
2eaba1a2 1745
16ad91e1 1746 if (aux & PHY_M_PS_RX_P_EN)
793b883e
SH		 1747 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1748 else
1749 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1750
1751 return 0;
1752}
cd28ab6a 1753
e07b1aa8
SH		 1754/* Interrupt from PHY */
1755static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1756{
e07b1aa8
SH		 1757 struct net_device *dev = hw->dev[port];
1758 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1759 u16 istatus, phystat;
1760
ebc646f6
SH		 1761 if (!netif_running(dev))
1762 return;
1763
e07b1aa8
SH		 1764 spin_lock(&sky2->phy_lock);
1765 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1766 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1767
cd28ab6a
SH		 1768 if (netif_msg_intr(sky2))
1769 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1770 sky2->netdev->name, istatus, phystat);
1771
2eaba1a2 1772 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1773 if (sky2_autoneg_done(sky2, phystat) == 0)
1774 sky2_link_up(sky2);
1775 goto out;
1776 }
cd28ab6a 1777
793b883e
SH		 1778 if (istatus & PHY_M_IS_LSP_CHANGE)
1779 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1780
793b883e
SH		 1781 if (istatus & PHY_M_IS_DUP_CHANGE)
1782 sky2->duplex =
1783 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1784
793b883e
SH		 1785 if (istatus & PHY_M_IS_LST_CHANGE) {
1786 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1787 sky2_link_up(sky2);
793b883e
SH		 1788 else
1789 sky2_link_down(sky2);
cd28ab6a 1790 }
793b883e 1791out:
e07b1aa8 1792 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1793}
1794
302d1252
SH		 1795
1796/* Transmit timeout is only called if we are running, carries is up
1797 * and tx queue is full (stopped).
1798 */
cd28ab6a
SH		 1799static void sky2_tx_timeout(struct net_device *dev)
1800{
1801 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1802 struct sky2_hw *hw = sky2->hw;
1803 unsigned txq = txqaddr[sky2->port];
8f24664d 1804 u16 report, done;
cd28ab6a
SH		 1805
1806 if (netif_msg_timer(sky2))
1807 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1808
8f24664d
SH		 1809 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1810 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1811
8f24664d
SH		 1812 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1813 dev->name,
1814 sky2->tx_cons, sky2->tx_prod, report, done);
1815
1816 if (report != done) {
1817 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1818
1819 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1820 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1821 } else if (report != sky2->tx_cons) {
1822 printk(KERN_INFO PFX "status report lost?\n");
1823
2bb8c262 1824 netif_tx_lock_bh(dev);
8f24664d 1825 sky2_tx_complete(sky2, report);
2bb8c262 1826 netif_tx_unlock_bh(dev);
8f24664d
SH		 1827 } else {
1828 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1829
8f24664d
SH		 1830 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1831 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1832
2bb8c262 1833 sky2_tx_clean(dev);
8f24664d
SH		 1834
1835 sky2_qset(hw, txq);
1836 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1837 }
cd28ab6a
SH		 1838}
1839
1840static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1841{
6b1a3aef 1842 struct sky2_port *sky2 = netdev_priv(dev);
1843 struct sky2_hw *hw = sky2->hw;
1844 int err;
1845 u16 ctl, mode;
e07b1aa8 1846 u32 imask;
cd28ab6a
SH		 1847
1848 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1849 return -EINVAL;
1850
5a5b1ea0 1851 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1852 return -EINVAL;
1853
6b1a3aef 1854 if (!netif_running(dev)) {
1855 dev->mtu = new_mtu;
1856 return 0;
1857 }
1858
e07b1aa8 1859 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 1860 sky2_write32(hw, B0_IMSK, 0);
1861
018d1c66 1862 dev->trans_start = jiffies; /* prevent tx timeout */
1863 netif_stop_queue(dev);
1864 netif_poll_disable(hw->dev[0]);
1865
e07b1aa8
SH		 1866 synchronize_irq(hw->pdev->irq);
1867
6b1a3aef 1868 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1869 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1870 sky2_rx_stop(sky2);
1871 sky2_rx_clean(sky2);
cd28ab6a
SH		 1872
1873 dev->mtu = new_mtu;
14d0263f 1874
6b1a3aef 1875 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1876 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1877
1878 if (dev->mtu > ETH_DATA_LEN)
1879 mode |= GM_SMOD_JUMBO_ENA;
1880
1881 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1882
6b1a3aef 1883 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1884
6b1a3aef 1885 err = sky2_rx_start(sky2);
e07b1aa8 1886 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1887
1b537565
SH		 1888 if (err)
1889 dev_close(dev);
1890 else {
1891 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1892
1893 netif_poll_enable(hw->dev[0]);
1894 netif_wake_queue(dev);
1895 }
1896
cd28ab6a
SH		 1897 return err;
1898}
1899
14d0263f
SH		 1900/* For small just reuse existing skb for next receive */
1901static struct sk_buff *receive_copy(struct sky2_port *sky2,
1902 const struct rx_ring_info *re,
1903 unsigned length)
1904{
1905 struct sk_buff *skb;
1906
1907 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1908 if (likely(skb)) {
1909 skb_reserve(skb, 2);
1910 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1911 length, PCI_DMA_FROMDEVICE);
1912 memcpy(skb->data, re->skb->data, length);
1913 skb->ip_summed = re->skb->ip_summed;
1914 skb->csum = re->skb->csum;
1915 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1916 length, PCI_DMA_FROMDEVICE);
1917 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 1918 skb_put(skb, length);
14d0263f
SH		 1919 }
1920 return skb;
1921}
1922
1923/* Adjust length of skb with fragments to match received data */
1924static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1925 unsigned int length)
1926{
1927 int i, num_frags;
1928 unsigned int size;
1929
1930 /* put header into skb */
1931 size = min(length, hdr_space);
1932 skb->tail += size;
1933 skb->len += size;
1934 length -= size;
1935
1936 num_frags = skb_shinfo(skb)->nr_frags;
1937 for (i = 0; i < num_frags; i++) {
1938 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1939
1940 if (length == 0) {
1941 /* don't need this page */
1942 __free_page(frag->page);
1943 --skb_shinfo(skb)->nr_frags;
1944 } else {
1945 size = min(length, (unsigned) PAGE_SIZE);
1946
1947 frag->size = size;
1948 skb->data_len += size;
1949 skb->truesize += size;
1950 skb->len += size;
1951 length -= size;
1952 }
1953 }
1954}
1955
1956/* Normal packet - take skb from ring element and put in a new one */
1957static struct sk_buff *receive_new(struct sky2_port *sky2,
1958 struct rx_ring_info *re,
1959 unsigned int length)
1960{
1961 struct sk_buff *skb, *nskb;
1962 unsigned hdr_space = sky2->rx_data_size;
1963
1964 pr_debug(PFX "receive new length=%d\n", length);
1965
1966 /* Don't be tricky about reusing pages (yet) */
1967 nskb = sky2_rx_alloc(sky2);
1968 if (unlikely(!nskb))
1969 return NULL;
1970
1971 skb = re->skb;
1972 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1973
1974 prefetch(skb->data);
1975 re->skb = nskb;
1976 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
1977
1978 if (skb_shinfo(skb)->nr_frags)
1979 skb_put_frags(skb, hdr_space, length);
1980 else
489b10c1 1981 skb_put(skb, length);
14d0263f
SH		 1982 return skb;
1983}
1984
cd28ab6a
SH		 1985/*
1986 * Receive one packet.
d571b694 1987 * For larger packets, get new buffer.
cd28ab6a 1988 */
497d7c86 1989static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 1990 u16 length, u32 status)
1991{
497d7c86 1992 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 1993 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1994 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1995
1996 if (unlikely(netif_msg_rx_status(sky2)))
1997 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 1998 dev->name, sky2->rx_next, status, length);
cd28ab6a 1999
793b883e 2000 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2001 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2002
42eeea01 2003 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2004 goto error;
2005
42eeea01 2006 if (!(status & GMR_FS_RX_OK))
2007 goto resubmit;
2008
497d7c86 2009 if (length > dev->mtu + ETH_HLEN)
6e15b712
SH		 2010 goto oversize;
2011
14d0263f
SH		 2012 if (length < copybreak)
2013 skb = receive_copy(sky2, re, length);
2014 else
2015 skb = receive_new(sky2, re, length);
793b883e 2016resubmit:
14d0263f 2017 sky2_rx_submit(sky2, re);
79e57d32 2018
cd28ab6a
SH		 2019 return skb;
2020
6e15b712
SH		 2021oversize:
2022 ++sky2->net_stats.rx_over_errors;
2023 goto resubmit;
2024
cd28ab6a 2025error:
6e15b712 2026 ++sky2->net_stats.rx_errors;
b6d77734
SH		 2027 if (status & GMR_FS_RX_FF_OV) {
2028 sky2->net_stats.rx_fifo_errors++;
2029 goto resubmit;
2030 }
6e15b712 2031
3be92a70 2032 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2033 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2034 dev->name, status, length);
793b883e
SH		 2035
2036 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2037 sky2->net_stats.rx_length_errors++;
2038 if (status & GMR_FS_FRAGMENT)
2039 sky2->net_stats.rx_frame_errors++;
2040 if (status & GMR_FS_CRC_ERR)
2041 sky2->net_stats.rx_crc_errors++;
79e57d32 2042
793b883e 2043 goto resubmit;
cd28ab6a
SH		 2044}
2045
e07b1aa8
SH		 2046/* Transmit complete */
2047static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2048{
e07b1aa8 2049 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2050
e07b1aa8 2051 if (netif_running(dev)) {
2bb8c262 2052 netif_tx_lock(dev);
e07b1aa8 2053 sky2_tx_complete(sky2, last);
2bb8c262 2054 netif_tx_unlock(dev);
2224795d 2055 }
cd28ab6a
SH		 2056}
2057
e07b1aa8
SH		 2058/* Process status response ring */
2059static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2060{
22e11703 2061 struct sky2_port *sky2;
e07b1aa8 2062 int work_done = 0;
22e11703 2063 unsigned buf_write[2] = { 0, 0 };
e71ebd73 2064 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2065
af2a58ac 2066 rmb();
bea86103 2067
e71ebd73 2068 while (hw->st_idx != hwidx) {
13210ce5 2069 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2070 struct net_device *dev;
cd28ab6a 2071 struct sk_buff *skb;
cd28ab6a
SH		 2072 u32 status;
2073 u16 length;
2074
cb5d9547 2075 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2076
e71ebd73
SH		 2077 BUG_ON(le->link >= 2);
2078 dev = hw->dev[le->link];
13210ce5 2079
2080 sky2 = netdev_priv(dev);
f65b138c
SH		 2081 length = le16_to_cpu(le->length);
2082 status = le32_to_cpu(le->status);
cd28ab6a 2083
e71ebd73 2084 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2085 case OP_RXSTAT:
497d7c86 2086 skb = sky2_receive(dev, length, status);
d1f13708 2087 if (!skb)
5df79111 2088 goto force_update;
13210ce5 2089
13210ce5 2090 skb->protocol = eth_type_trans(skb, dev);
2091 dev->last_rx = jiffies;
2092
d1f13708 2093#ifdef SKY2_VLAN_TAG_USED
2094 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2095 vlan_hwaccel_receive_skb(skb,
2096 sky2->vlgrp,
2097 be16_to_cpu(sky2->rx_tag));
2098 } else
2099#endif
cd28ab6a 2100 netif_receive_skb(skb);
13210ce5 2101
22e11703
SH		 2102 /* Update receiver after 16 frames */
2103 if (++buf_write[le->link] == RX_BUF_WRITE) {
5df79111
SH		 2104force_update:
2105 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
22e11703
SH		 2106 buf_write[le->link] = 0;
2107 }
2108
2109 /* Stop after net poll weight */
13210ce5 2110 if (++work_done >= to_do)
2111 goto exit_loop;
cd28ab6a
SH		 2112 break;
2113
d1f13708 2114#ifdef SKY2_VLAN_TAG_USED
2115 case OP_RXVLAN:
2116 sky2->rx_tag = length;
2117 break;
2118
2119 case OP_RXCHKSVLAN:
2120 sky2->rx_tag = length;
2121 /* fall through */
2122#endif
cd28ab6a 2123 case OP_RXCHKS:
d11c13e7 2124 skb = sky2->rx_ring[sky2->rx_next].skb;
84fa7933 2125 skb->ip_summed = CHECKSUM_COMPLETE;
f65b138c 2126 skb->csum = status & 0xffff;
cd28ab6a
SH		 2127 break;
2128
2129 case OP_TXINDEXLE:
13b97b74 2130 /* TX index reports status for both ports */
f55925d7
SH		 2131 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2132 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2133 if (hw->dev[1])
2134 sky2_tx_done(hw->dev[1],
2135 ((status >> 24) & 0xff)
2136 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2137 break;
2138
cd28ab6a
SH		 2139 default:
2140 if (net_ratelimit())
793b883e 2141 printk(KERN_WARNING PFX
e71ebd73
SH		 2142 "unknown status opcode 0x%x\n", le->opcode);
2143 goto exit_loop;
cd28ab6a 2144 }
13210ce5 2145 }
cd28ab6a 2146
fe2a24df
SH		 2147 /* Fully processed status ring so clear irq */
2148 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2149
13210ce5 2150exit_loop:
22e11703
SH		 2151 if (buf_write[0]) {
2152 sky2 = netdev_priv(hw->dev[0]);
2153 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2154 }
2155
2156 if (buf_write[1]) {
2157 sky2 = netdev_priv(hw->dev[1]);
2158 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2159 }
2160
e07b1aa8 2161 return work_done;
cd28ab6a
SH		 2162}
2163
2164static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2165{
2166 struct net_device *dev = hw->dev[port];
2167
3be92a70
SH		 2168 if (net_ratelimit())
2169 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2170 dev->name, status);
cd28ab6a
SH		 2171
2172 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2173 if (net_ratelimit())
2174 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2175 dev->name);
cd28ab6a
SH		 2176 /* Clear IRQ */
2177 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2178 }
2179
2180 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2181 if (net_ratelimit())
2182 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2183 dev->name);
cd28ab6a
SH		 2184
2185 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2186 }
2187
2188 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2189 if (net_ratelimit())
2190 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2191 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2192 }
2193
2194 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2195 if (net_ratelimit())
2196 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2197 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2198 }
2199
2200 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2201 if (net_ratelimit())
2202 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2203 dev->name);
cd28ab6a
SH		 2204 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2205 }
2206}
2207
2208static void sky2_hw_intr(struct sky2_hw *hw)
2209{
2210 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2211
793b883e 2212 if (status & Y2_IS_TIST_OV)
cd28ab6a 2213 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2214
2215 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2216 u16 pci_err;
2217
56a645cc 2218 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2219 if (net_ratelimit())
2220 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2221 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2222
2223 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2224 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2225 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2226 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2227 }
2228
2229 if (status & Y2_IS_PCI_EXP) {
d571b694 2230 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2231 u32 pex_err;
2232
7bd656d1 2233 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2234
3be92a70
SH		 2235 if (net_ratelimit())
2236 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2237 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2238
2239 /* clear the interrupt */
2240 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2241 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2242 0xffffffffUL);
cd28ab6a
SH		 2243 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2244
7bd656d1 2245 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2246 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2247 hwmsk &= ~Y2_IS_PCI_EXP;
2248 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2249 }
2250 }
2251
2252 if (status & Y2_HWE_L1_MASK)
2253 sky2_hw_error(hw, 0, status);
2254 status >>= 8;
2255 if (status & Y2_HWE_L1_MASK)
2256 sky2_hw_error(hw, 1, status);
2257}
2258
2259static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2260{
2261 struct net_device *dev = hw->dev[port];
2262 struct sky2_port *sky2 = netdev_priv(dev);
2263 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2264
2265 if (netif_msg_intr(sky2))
2266 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2267 dev->name, status);
2268
2269 if (status & GM_IS_RX_FF_OR) {
2270 ++sky2->net_stats.rx_fifo_errors;
2271 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2272 }
2273
2274 if (status & GM_IS_TX_FF_UR) {
2275 ++sky2->net_stats.tx_fifo_errors;
2276 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2277 }
cd28ab6a
SH		 2278}
2279
d257924e
SH		 2280/* This should never happen it is a fatal situation */
2281static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2282 const char *rxtx, u32 mask)
2283{
2284 struct net_device *dev = hw->dev[port];
2285 struct sky2_port *sky2 = netdev_priv(dev);
2286 u32 imask;
2287
2288 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2289 dev ? dev->name : "<not registered>", rxtx);
2290
2291 imask = sky2_read32(hw, B0_IMSK);
2292 imask &= ~mask;
2293 sky2_write32(hw, B0_IMSK, imask);
2294
2295 if (dev) {
2296 spin_lock(&sky2->phy_lock);
2297 sky2_link_down(sky2);
2298 spin_unlock(&sky2->phy_lock);
2299 }
2300}
cd28ab6a 2301
d27ed387
SH		 2302/* If idle then force a fake soft NAPI poll once a second
2303 * to work around cases where sharing an edge triggered interrupt.
2304 */
eb35cf60
SH		 2305static inline void sky2_idle_start(struct sky2_hw *hw)
2306{
2307 if (idle_timeout > 0)
2308 mod_timer(&hw->idle_timer,
2309 jiffies + msecs_to_jiffies(idle_timeout));
2310}
2311
d27ed387
SH		 2312static void sky2_idle(unsigned long arg)
2313{
01bd7564
SH		 2314 struct sky2_hw *hw = (struct sky2_hw *) arg;
2315 struct net_device *dev = hw->dev[0];
d27ed387 2316
d27ed387
SH		 2317 if (__netif_rx_schedule_prep(dev))
2318 __netif_rx_schedule(dev);
01bd7564
SH		 2319
2320 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2321}
2322
2323
e07b1aa8 2324static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2325{
e07b1aa8
SH		 2326 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2327 int work_limit = min(dev0->quota, *budget);
2328 int work_done = 0;
fb2690a9 2329 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2330
1e5f1283
SH		 2331 if (status & Y2_IS_HW_ERR)
2332 sky2_hw_intr(hw);
d257924e 2333
1e5f1283
SH		 2334 if (status & Y2_IS_IRQ_PHY1)
2335 sky2_phy_intr(hw, 0);
cd28ab6a 2336
1e5f1283
SH		 2337 if (status & Y2_IS_IRQ_PHY2)
2338 sky2_phy_intr(hw, 1);
cd28ab6a 2339
1e5f1283
SH		 2340 if (status & Y2_IS_IRQ_MAC1)
2341 sky2_mac_intr(hw, 0);
cd28ab6a 2342
1e5f1283
SH		 2343 if (status & Y2_IS_IRQ_MAC2)
2344 sky2_mac_intr(hw, 1);
cd28ab6a 2345
1e5f1283
SH		 2346 if (status & Y2_IS_CHK_RX1)
2347 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2348
1e5f1283
SH		 2349 if (status & Y2_IS_CHK_RX2)
2350 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2351
1e5f1283
SH		 2352 if (status & Y2_IS_CHK_TXA1)
2353 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2354
1e5f1283
SH		 2355 if (status & Y2_IS_CHK_TXA2)
2356 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2357
1e5f1283 2358 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2359 if (work_done < work_limit) {
2360 netif_rx_complete(dev0);
86fba634 2361
fe2a24df
SH		 2362 sky2_read32(hw, B0_Y2_SP_LISR);
2363 return 0;
2364 } else {
2365 *budget -= work_done;
2366 dev0->quota -= work_done;
1e5f1283 2367 return 1;
fe2a24df 2368 }
e07b1aa8
SH		 2369}
2370
7d12e780 2371static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2372{
2373 struct sky2_hw *hw = dev_id;
2374 struct net_device *dev0 = hw->dev[0];
2375 u32 status;
2376
2377 /* Reading this mask interrupts as side effect */
2378 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2379 if (status == 0 || status == ~0)
2380 return IRQ_NONE;
793b883e 2381
e07b1aa8
SH		 2382 prefetch(&hw->st_le[hw->st_idx]);
2383 if (likely(__netif_rx_schedule_prep(dev0)))
2384 __netif_rx_schedule(dev0);
793b883e 2385
cd28ab6a
SH		 2386 return IRQ_HANDLED;
2387}
2388
2389#ifdef CONFIG_NET_POLL_CONTROLLER
2390static void sky2_netpoll(struct net_device *dev)
2391{
2392 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2393 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2394
88d11360
SH		 2395 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2396 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2397}
2398#endif
2399
2400/* Chip internal frequency for clock calculations */
fb17358f 2401static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2402{
793b883e 2403 switch (hw->chip_id) {
cd28ab6a 2404 case CHIP_ID_YUKON_EC:
5a5b1ea0 2405 case CHIP_ID_YUKON_EC_U:
fb17358f 2406 return 125; /* 125 Mhz */
cd28ab6a 2407 case CHIP_ID_YUKON_FE:
fb17358f 2408 return 100; /* 100 Mhz */
793b883e 2409 default: /* YUKON_XL */
fb17358f 2410 return 156; /* 156 Mhz */
cd28ab6a
SH		 2411 }
2412}
2413
fb17358f 2414static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2415{
fb17358f 2416 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2417}
2418
fb17358f 2419static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2420{
fb17358f 2421 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2422}
2423
fb17358f 2424
59139528 2425static int sky2_reset(struct sky2_hw *hw)
cd28ab6a 2426{
cd28ab6a 2427 u16 status;
b89165f2 2428 u8 t8;
56a645cc 2429 int i;
cd28ab6a 2430
cd28ab6a 2431 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2432
cd28ab6a
SH		 2433 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2434 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2435 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2436 pci_name(hw->pdev), hw->chip_id);
2437 return -EOPNOTSUPP;
2438 }
2439
290d4de5
SH		 2440 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2441
2442 /* This rev is really old, and requires untested workarounds */
2443 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2444 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2445 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2446 hw->chip_id, hw->chip_rev);
2447 return -EOPNOTSUPP;
2448 }
2449
cd28ab6a
SH		 2450 /* disable ASF */
2451 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2452 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2453 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2454 }
2455
2456 /* do a SW reset */
2457 sky2_write8(hw, B0_CTST, CS_RST_SET);
2458 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2459
2460 /* clear PCI errors, if any */
56a645cc 2461 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2462
cd28ab6a 2463 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2464 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2465
cd28ab6a
SH		 2466
2467 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2468
2469 /* clear any PEX errors */
7bd656d1
SH		 2470 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2471 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2472
cd28ab6a 2473
b89165f2 2474 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
cd28ab6a
SH		 2475 hw->ports = 1;
2476 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2477 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2478 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2479 ++hw->ports;
2480 }
cd28ab6a 2481
5afa0a9c 2482 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2483
2484 for (i = 0; i < hw->ports; i++) {
2485 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2486 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2487 }
2488
2489 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2490
793b883e
SH		 2491 /* Clear I2C IRQ noise */
2492 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2493
2494 /* turn off hardware timer (unused) */
2495 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2496 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2497
cd28ab6a
SH		 2498 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2499
69634ee7
SH		 2500 /* Turn off descriptor polling */
2501 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2502
2503 /* Turn off receive timestamp */
2504 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2505 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2506
2507 /* enable the Tx Arbiters */
2508 for (i = 0; i < hw->ports; i++)
2509 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2510
2511 /* Initialize ram interface */
2512 for (i = 0; i < hw->ports; i++) {
793b883e 2513 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2514
2515 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2516 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2517 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2518 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2519 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2520 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2521 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2522 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2523 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2524 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2525 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2526 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2527 }
2528
7bd656d1 2529 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2530
cd28ab6a 2531 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2532 sky2_gmac_reset(hw, i);
cd28ab6a 2533
cd28ab6a
SH		 2534 memset(hw->st_le, 0, STATUS_LE_BYTES);
2535 hw->st_idx = 0;
2536
2537 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2538 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2539
2540 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2541 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2542
2543 /* Set the list last index */
793b883e 2544 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2545
290d4de5
SH		 2546 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2547 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2548
290d4de5
SH		 2549 /* set Status-FIFO ISR watermark */
2550 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2551 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2552 else
2553 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2554
290d4de5 2555 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2556 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2557 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2558
793b883e 2559 /* enable status unit */
cd28ab6a
SH		 2560 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2561
2562 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2563 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2564 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2565
2566 return 0;
2567}
2568
28bd181a 2569static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2570{
b89165f2
SH		 2571 if (sky2_is_copper(hw)) {
2572 u32 modes = SUPPORTED_10baseT_Half
2573 | SUPPORTED_10baseT_Full
2574 | SUPPORTED_100baseT_Half
2575 | SUPPORTED_100baseT_Full
2576 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2577
2578 if (hw->chip_id != CHIP_ID_YUKON_FE)
2579 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2580 | SUPPORTED_1000baseT_Full;
2581 return modes;
cd28ab6a 2582 } else
b89165f2
SH		 2583 return SUPPORTED_1000baseT_Half
2584 | SUPPORTED_1000baseT_Full
2585 | SUPPORTED_Autoneg
2586 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2587}
2588
793b883e 2589static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2590{
2591 struct sky2_port *sky2 = netdev_priv(dev);
2592 struct sky2_hw *hw = sky2->hw;
2593
2594 ecmd->transceiver = XCVR_INTERNAL;
2595 ecmd->supported = sky2_supported_modes(hw);
2596 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2597 if (sky2_is_copper(hw)) {
cd28ab6a 2598 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2599 | SUPPORTED_10baseT_Full
2600 | SUPPORTED_100baseT_Half
2601 | SUPPORTED_100baseT_Full
2602 | SUPPORTED_1000baseT_Half
2603 | SUPPORTED_1000baseT_Full
2604 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2605 ecmd->port = PORT_TP;
b89165f2
SH		 2606 ecmd->speed = sky2->speed;
2607 } else {
2608 ecmd->speed = SPEED_1000;
cd28ab6a 2609 ecmd->port = PORT_FIBRE;
b89165f2 2610 }
cd28ab6a
SH		 2611
2612 ecmd->advertising = sky2->advertising;
2613 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2614 ecmd->duplex = sky2->duplex;
2615 return 0;
2616}
2617
2618static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2619{
2620 struct sky2_port *sky2 = netdev_priv(dev);
2621 const struct sky2_hw *hw = sky2->hw;
2622 u32 supported = sky2_supported_modes(hw);
2623
2624 if (ecmd->autoneg == AUTONEG_ENABLE) {
2625 ecmd->advertising = supported;
2626 sky2->duplex = -1;
2627 sky2->speed = -1;
2628 } else {
2629 u32 setting;
2630
793b883e 2631 switch (ecmd->speed) {
cd28ab6a
SH		 2632 case SPEED_1000:
2633 if (ecmd->duplex == DUPLEX_FULL)
2634 setting = SUPPORTED_1000baseT_Full;
2635 else if (ecmd->duplex == DUPLEX_HALF)
2636 setting = SUPPORTED_1000baseT_Half;
2637 else
2638 return -EINVAL;
2639 break;
2640 case SPEED_100:
2641 if (ecmd->duplex == DUPLEX_FULL)
2642 setting = SUPPORTED_100baseT_Full;
2643 else if (ecmd->duplex == DUPLEX_HALF)
2644 setting = SUPPORTED_100baseT_Half;
2645 else
2646 return -EINVAL;
2647 break;
2648
2649 case SPEED_10:
2650 if (ecmd->duplex == DUPLEX_FULL)
2651 setting = SUPPORTED_10baseT_Full;
2652 else if (ecmd->duplex == DUPLEX_HALF)
2653 setting = SUPPORTED_10baseT_Half;
2654 else
2655 return -EINVAL;
2656 break;
2657 default:
2658 return -EINVAL;
2659 }
2660
2661 if ((setting & supported) == 0)
2662 return -EINVAL;
2663
2664 sky2->speed = ecmd->speed;
2665 sky2->duplex = ecmd->duplex;
2666 }
2667
2668 sky2->autoneg = ecmd->autoneg;
2669 sky2->advertising = ecmd->advertising;
2670
1b537565
SH		 2671 if (netif_running(dev))
2672 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2673
2674 return 0;
2675}
2676
2677static void sky2_get_drvinfo(struct net_device *dev,
2678 struct ethtool_drvinfo *info)
2679{
2680 struct sky2_port *sky2 = netdev_priv(dev);
2681
2682 strcpy(info->driver, DRV_NAME);
2683 strcpy(info->version, DRV_VERSION);
2684 strcpy(info->fw_version, "N/A");
2685 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2686}
2687
2688static const struct sky2_stat {
793b883e
SH		 2689 char name[ETH_GSTRING_LEN];
2690 u16 offset;
cd28ab6a
SH		 2691} sky2_stats[] = {
2692 { "tx_bytes", GM_TXO_OK_HI },
2693 { "rx_bytes", GM_RXO_OK_HI },
2694 { "tx_broadcast", GM_TXF_BC_OK },
2695 { "rx_broadcast", GM_RXF_BC_OK },
2696 { "tx_multicast", GM_TXF_MC_OK },
2697 { "rx_multicast", GM_RXF_MC_OK },
2698 { "tx_unicast", GM_TXF_UC_OK },
2699 { "rx_unicast", GM_RXF_UC_OK },
2700 { "tx_mac_pause", GM_TXF_MPAUSE },
2701 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2702 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2703 { "late_collision",GM_TXF_LAT_COL },
2704 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2705 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2706 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2707
d2604540 2708 { "rx_short", GM_RXF_SHT },
cd28ab6a 2709 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2710 { "rx_64_byte_packets", GM_RXF_64B },
2711 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2712 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2713 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2714 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2715 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2716 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2717 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2718 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2719 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2720 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2721
2722 { "tx_64_byte_packets", GM_TXF_64B },
2723 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2724 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2725 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2726 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2727 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2728 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2729 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2730};
2731
cd28ab6a
SH		 2732static u32 sky2_get_rx_csum(struct net_device *dev)
2733{
2734 struct sky2_port *sky2 = netdev_priv(dev);
2735
2736 return sky2->rx_csum;
2737}
2738
2739static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2740{
2741 struct sky2_port *sky2 = netdev_priv(dev);
2742
2743 sky2->rx_csum = data;
793b883e 2744
cd28ab6a
SH		 2745 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2746 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2747
2748 return 0;
2749}
2750
2751static u32 sky2_get_msglevel(struct net_device *netdev)
2752{
2753 struct sky2_port *sky2 = netdev_priv(netdev);
2754 return sky2->msg_enable;
2755}
2756
9a7ae0a9
SH		 2757static int sky2_nway_reset(struct net_device *dev)
2758{
2759 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2760
16ad91e1 2761 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2762 return -EINVAL;
2763
1b537565 2764 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2765
2766 return 0;
2767}
2768
793b883e 2769static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2770{
2771 struct sky2_hw *hw = sky2->hw;
2772 unsigned port = sky2->port;
2773 int i;
2774
2775 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2776 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2777 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2778 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2779
793b883e 2780 for (i = 2; i < count; i++)
cd28ab6a
SH		 2781 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2782}
2783
cd28ab6a
SH		 2784static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2785{
2786 struct sky2_port *sky2 = netdev_priv(netdev);
2787 sky2->msg_enable = value;
2788}
2789
2790static int sky2_get_stats_count(struct net_device *dev)
2791{
2792 return ARRAY_SIZE(sky2_stats);
2793}
2794
2795static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2796 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2797{
2798 struct sky2_port *sky2 = netdev_priv(dev);
2799
793b883e 2800 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2801}
2802
793b883e 2803static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2804{
2805 int i;
2806
2807 switch (stringset) {
2808 case ETH_SS_STATS:
2809 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2810 memcpy(data + i * ETH_GSTRING_LEN,
2811 sky2_stats[i].name, ETH_GSTRING_LEN);
2812 break;
2813 }
2814}
2815
2816/* Use hardware MIB variables for critical path statistics and
2817 * transmit feedback not reported at interrupt.
2818 * Other errors are accounted for in interrupt handler.
2819 */
2820static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2821{
2822 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2823 u64 data[13];
cd28ab6a 2824
793b883e 2825 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2826
2827 sky2->net_stats.tx_bytes = data[0];
2828 sky2->net_stats.rx_bytes = data[1];
2829 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2830 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
050ff180 2831 sky2->net_stats.multicast = data[3] + data[5];
cd28ab6a
SH		 2832 sky2->net_stats.collisions = data[10];
2833 sky2->net_stats.tx_aborted_errors = data[12];
2834
2835 return &sky2->net_stats;
2836}
2837
2838static int sky2_set_mac_address(struct net_device *dev, void *p)
2839{
2840 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2841 struct sky2_hw *hw = sky2->hw;
2842 unsigned port = sky2->port;
2843 const struct sockaddr *addr = p;
cd28ab6a
SH		 2844
2845 if (!is_valid_ether_addr(addr->sa_data))
2846 return -EADDRNOTAVAIL;
2847
cd28ab6a 2848 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2849 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2850 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2851 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2852 dev->dev_addr, ETH_ALEN);
1b537565 2853
a8ab1ec0
SH		 2854 /* virtual address for data */
2855 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2856
2857 /* physical address: used for pause frames */
2858 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2859
2860 return 0;
cd28ab6a
SH		 2861}
2862
a052b52f
SH		 2863static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
2864{
2865 u32 bit;
2866
2867 bit = ether_crc(ETH_ALEN, addr) & 63;
2868 filter[bit >> 3] |= 1 << (bit & 7);
2869}
2870
cd28ab6a
SH		 2871static void sky2_set_multicast(struct net_device *dev)
2872{
2873 struct sky2_port *sky2 = netdev_priv(dev);
2874 struct sky2_hw *hw = sky2->hw;
2875 unsigned port = sky2->port;
2876 struct dev_mc_list *list = dev->mc_list;
2877 u16 reg;
2878 u8 filter[8];
a052b52f
SH		 2879 int rx_pause;
2880 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 2881
a052b52f 2882 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 2883 memset(filter, 0, sizeof(filter));
2884
2885 reg = gma_read16(hw, port, GM_RX_CTRL);
2886 reg |= GM_RXCR_UCF_ENA;
2887
d571b694 2888 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2889 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 2890 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 2891 memset(filter, 0xff, sizeof(filter));
a052b52f 2892 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 2893 reg &= ~GM_RXCR_MCF_ENA;
2894 else {
2895 int i;
2896 reg |= GM_RXCR_MCF_ENA;
2897
a052b52f
SH		 2898 if (rx_pause)
2899 sky2_add_filter(filter, pause_mc_addr);
2900
2901 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2902 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 2903 }
2904
cd28ab6a 2905 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2906 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2907 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2908 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2909 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2910 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2911 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2912 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2913
2914 gma_write16(hw, port, GM_RX_CTRL, reg);
2915}
2916
2917/* Can have one global because blinking is controlled by
2918 * ethtool and that is always under RTNL mutex
2919 */
91c86df5 2920static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2921{
793b883e
SH		 2922 u16 pg;
2923
793b883e
SH		 2924 switch (hw->chip_id) {
2925 case CHIP_ID_YUKON_XL:
2926 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2927 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2928 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2929 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2930 PHY_M_LEDC_INIT_CTRL(7) |
2931 PHY_M_LEDC_STA1_CTRL(7) |
2932 PHY_M_LEDC_STA0_CTRL(7))
2933 : 0);
2934
2935 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2936 break;
2937
2938 default:
2939 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 2940 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2941 on ? PHY_M_LED_ALL : 0);
793b883e 2942 }
cd28ab6a
SH		 2943}
2944
2945/* blink LED's for finding board */
2946static int sky2_phys_id(struct net_device *dev, u32 data)
2947{
2948 struct sky2_port *sky2 = netdev_priv(dev);
2949 struct sky2_hw *hw = sky2->hw;
2950 unsigned port = sky2->port;
793b883e 2951 u16 ledctrl, ledover = 0;
cd28ab6a 2952 long ms;
91c86df5 2953 int interrupted;
cd28ab6a
SH		 2954 int onoff = 1;
2955
793b883e 2956 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2957 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2958 else
2959 ms = data * 1000;
2960
2961 /* save initial values */
e07b1aa8 2962 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2963 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2964 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2965 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2966 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2967 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2968 } else {
2969 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2970 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2971 }
cd28ab6a 2972
91c86df5
SH		 2973 interrupted = 0;
2974 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2975 sky2_led(hw, port, onoff);
2976 onoff = !onoff;
2977
e07b1aa8 2978 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2979 interrupted = msleep_interruptible(250);
e07b1aa8 2980 spin_lock_bh(&sky2->phy_lock);
91c86df5 2981
cd28ab6a
SH		 2982 ms -= 250;
2983 }
2984
2985 /* resume regularly scheduled programming */
793b883e
SH		 2986 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2987 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2988 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2989 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2990 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2991 } else {
2992 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2993 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2994 }
e07b1aa8 2995 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2996
2997 return 0;
2998}
2999
3000static void sky2_get_pauseparam(struct net_device *dev,
3001 struct ethtool_pauseparam *ecmd)
3002{
3003 struct sky2_port *sky2 = netdev_priv(dev);
3004
16ad91e1
SH		 3005 switch (sky2->flow_mode) {
3006 case FC_NONE:
3007 ecmd->tx_pause = ecmd->rx_pause = 0;
3008 break;
3009 case FC_TX:
3010 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3011 break;
3012 case FC_RX:
3013 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3014 break;
3015 case FC_BOTH:
3016 ecmd->tx_pause = ecmd->rx_pause = 1;
3017 }
3018
cd28ab6a
SH		 3019 ecmd->autoneg = sky2->autoneg;
3020}
3021
3022static int sky2_set_pauseparam(struct net_device *dev,
3023 struct ethtool_pauseparam *ecmd)
3024{
3025 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3026
3027 sky2->autoneg = ecmd->autoneg;
16ad91e1 3028 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3029
16ad91e1
SH		 3030 if (netif_running(dev))
3031 sky2_phy_reinit(sky2);
cd28ab6a 3032
2eaba1a2 3033 return 0;
cd28ab6a
SH		 3034}
3035
fb17358f
SH		 3036static int sky2_get_coalesce(struct net_device *dev,
3037 struct ethtool_coalesce *ecmd)
3038{
3039 struct sky2_port *sky2 = netdev_priv(dev);
3040 struct sky2_hw *hw = sky2->hw;
3041
3042 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3043 ecmd->tx_coalesce_usecs = 0;
3044 else {
3045 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3046 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3047 }
3048 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3049
3050 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3051 ecmd->rx_coalesce_usecs = 0;
3052 else {
3053 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3054 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3055 }
3056 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3057
3058 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3059 ecmd->rx_coalesce_usecs_irq = 0;
3060 else {
3061 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3062 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3063 }
3064
3065 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3066
3067 return 0;
3068}
3069
3070/* Note: this affect both ports */
3071static int sky2_set_coalesce(struct net_device *dev,
3072 struct ethtool_coalesce *ecmd)
3073{
3074 struct sky2_port *sky2 = netdev_priv(dev);
3075 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3076 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3077
77b3d6a2
SH		 3078 if (ecmd->tx_coalesce_usecs > tmax ||
3079 ecmd->rx_coalesce_usecs > tmax ||
3080 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3081 return -EINVAL;
3082
ff81fbbe 3083 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3084 return -EINVAL;
ff81fbbe 3085 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3086 return -EINVAL;
ff81fbbe 3087 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3088 return -EINVAL;
3089
3090 if (ecmd->tx_coalesce_usecs == 0)
3091 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3092 else {
3093 sky2_write32(hw, STAT_TX_TIMER_INI,
3094 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3095 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3096 }
3097 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3098
3099 if (ecmd->rx_coalesce_usecs == 0)
3100 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3101 else {
3102 sky2_write32(hw, STAT_LEV_TIMER_INI,
3103 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3104 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3105 }
3106 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3107
3108 if (ecmd->rx_coalesce_usecs_irq == 0)
3109 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3110 else {
d28d4870 3111 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3112 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3113 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3114 }
3115 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3116 return 0;
3117}
3118
793b883e
SH		 3119static void sky2_get_ringparam(struct net_device *dev,
3120 struct ethtool_ringparam *ering)
3121{
3122 struct sky2_port *sky2 = netdev_priv(dev);
3123
3124 ering->rx_max_pending = RX_MAX_PENDING;
3125 ering->rx_mini_max_pending = 0;
3126 ering->rx_jumbo_max_pending = 0;
3127 ering->tx_max_pending = TX_RING_SIZE - 1;
3128
3129 ering->rx_pending = sky2->rx_pending;
3130 ering->rx_mini_pending = 0;
3131 ering->rx_jumbo_pending = 0;
3132 ering->tx_pending = sky2->tx_pending;
3133}
3134
3135static int sky2_set_ringparam(struct net_device *dev,
3136 struct ethtool_ringparam *ering)
3137{
3138 struct sky2_port *sky2 = netdev_priv(dev);
3139 int err = 0;
3140
3141 if (ering->rx_pending > RX_MAX_PENDING ||
3142 ering->rx_pending < 8 ||
3143 ering->tx_pending < MAX_SKB_TX_LE ||
3144 ering->tx_pending > TX_RING_SIZE - 1)
3145 return -EINVAL;
3146
3147 if (netif_running(dev))
3148 sky2_down(dev);
3149
3150 sky2->rx_pending = ering->rx_pending;
3151 sky2->tx_pending = ering->tx_pending;
3152
1b537565 3153 if (netif_running(dev)) {
793b883e 3154 err = sky2_up(dev);
1b537565
SH		 3155 if (err)
3156 dev_close(dev);
6ed995bb
SH		 3157 else
3158 sky2_set_multicast(dev);
1b537565 3159 }
793b883e
SH		 3160
3161 return err;
3162}
3163
793b883e
SH		 3164static int sky2_get_regs_len(struct net_device *dev)
3165{
6e4cbb34 3166 return 0x4000;
793b883e
SH		 3167}
3168
3169/*
3170 * Returns copy of control register region
6e4cbb34 3171 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3172 */
3173static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3174 void *p)
3175{
3176 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3177 const void __iomem *io = sky2->hw->regs;
793b883e 3178
6e4cbb34 3179 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3180 regs->version = 1;
6e4cbb34 3181 memset(p, 0, regs->len);
793b883e 3182
6e4cbb34
SH		 3183 memcpy_fromio(p, io, B3_RAM_ADDR);
3184
3185 memcpy_fromio(p + B3_RI_WTO_R1,
3186 io + B3_RI_WTO_R1,
3187 regs->len - B3_RI_WTO_R1);
793b883e 3188}
cd28ab6a 3189
7282d491 3190static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3191 .get_settings = sky2_get_settings,
3192 .set_settings = sky2_set_settings,
3193 .get_drvinfo = sky2_get_drvinfo,
3194 .get_msglevel = sky2_get_msglevel,
3195 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3196 .nway_reset = sky2_nway_reset,
793b883e
SH		 3197 .get_regs_len = sky2_get_regs_len,
3198 .get_regs = sky2_get_regs,
3199 .get_link = ethtool_op_get_link,
3200 .get_sg = ethtool_op_get_sg,
3201 .set_sg = ethtool_op_set_sg,
3202 .get_tx_csum = ethtool_op_get_tx_csum,
3203 .set_tx_csum = ethtool_op_set_tx_csum,
3204 .get_tso = ethtool_op_get_tso,
3205 .set_tso = ethtool_op_set_tso,
3206 .get_rx_csum = sky2_get_rx_csum,
3207 .set_rx_csum = sky2_set_rx_csum,
3208 .get_strings = sky2_get_strings,
fb17358f
SH		 3209 .get_coalesce = sky2_get_coalesce,
3210 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3211 .get_ringparam = sky2_get_ringparam,
3212 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3213 .get_pauseparam = sky2_get_pauseparam,
3214 .set_pauseparam = sky2_set_pauseparam,
793b883e 3215 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3216 .get_stats_count = sky2_get_stats_count,
3217 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3218 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3219};
3220
3221/* Initialize network device */
3222static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3223 unsigned port, int highmem)
3224{
3225 struct sky2_port *sky2;
3226 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3227
3228 if (!dev) {
3229 printk(KERN_ERR "sky2 etherdev alloc failed");
3230 return NULL;
3231 }
3232
3233 SET_MODULE_OWNER(dev);
3234 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3235 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3236 dev->open = sky2_up;
3237 dev->stop = sky2_down;
ef743d33 3238 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3239 dev->hard_start_xmit = sky2_xmit_frame;
3240 dev->get_stats = sky2_get_stats;
3241 dev->set_multicast_list = sky2_set_multicast;
3242 dev->set_mac_address = sky2_set_mac_address;
3243 dev->change_mtu = sky2_change_mtu;
3244 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3245 dev->tx_timeout = sky2_tx_timeout;
3246 dev->watchdog_timeo = TX_WATCHDOG;
3247 if (port == 0)
3248 dev->poll = sky2_poll;
3249 dev->weight = NAPI_WEIGHT;
3250#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3251 /* Network console (only works on port 0)
3252 * because netpoll makes assumptions about NAPI
3253 */
3254 if (port == 0)
3255 dev->poll_controller = sky2_netpoll;
cd28ab6a 3256#endif
cd28ab6a
SH		 3257
3258 sky2 = netdev_priv(dev);
3259 sky2->netdev = dev;
3260 sky2->hw = hw;
3261 sky2->msg_enable = netif_msg_init(debug, default_msg);
3262
cd28ab6a
SH		 3263 /* Auto speed and flow control */
3264 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3265 sky2->flow_mode = FC_BOTH;
3266
cd28ab6a
SH		 3267 sky2->duplex = -1;
3268 sky2->speed = -1;
3269 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3270 sky2->rx_csum = 1;
75d070c5 3271
e07b1aa8 3272 spin_lock_init(&sky2->phy_lock);
793b883e 3273 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3274 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3275
3276 hw->dev[port] = dev;
3277
3278 sky2->port = port;
3279
5a5b1ea0 3280 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3281 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3282 if (highmem)
3283 dev->features |= NETIF_F_HIGHDMA;
793b883e 3284 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3285
d1f13708 3286#ifdef SKY2_VLAN_TAG_USED
3287 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3288 dev->vlan_rx_register = sky2_vlan_rx_register;
3289 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3290#endif
3291
cd28ab6a 3292 /* read the mac address */
793b883e 3293 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3294 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3295
3296 /* device is off until link detection */
3297 netif_carrier_off(dev);
3298 netif_stop_queue(dev);
3299
3300 return dev;
3301}
3302
28bd181a 3303static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3304{
3305 const struct sky2_port *sky2 = netdev_priv(dev);
3306
3307 if (netif_msg_probe(sky2))
3308 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3309 dev->name,
3310 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3311 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3312}
3313
fb2690a9 3314/* Handle software interrupt used during MSI test */
7d12e780 3315static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3316{
3317 struct sky2_hw *hw = dev_id;
3318 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3319
3320 if (status == 0)
3321 return IRQ_NONE;
3322
3323 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3324 hw->msi = 1;
fb2690a9
SH		 3325 wake_up(&hw->msi_wait);
3326 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3327 }
3328 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3329
3330 return IRQ_HANDLED;
3331}
3332
3333/* Test interrupt path by forcing a a software IRQ */
3334static int __devinit sky2_test_msi(struct sky2_hw *hw)
3335{
3336 struct pci_dev *pdev = hw->pdev;
3337 int err;
3338
bb507fe1 3339 init_waitqueue_head (&hw->msi_wait);
3340
fb2690a9
SH		 3341 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3342
b0a20ded 3343 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9
SH		 3344 if (err) {
3345 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3346 pci_name(pdev), pdev->irq);
3347 return err;
3348 }
3349
fb2690a9 3350 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3351 sky2_read8(hw, B0_CTST);
fb2690a9 3352
b0a20ded 3353 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3354
b0a20ded 3355 if (!hw->msi) {
fb2690a9 3356 /* MSI test failed, go back to INTx mode */
2bffc23a
SH		 3357 printk(KERN_INFO PFX "%s: No interrupt generated using MSI, "
3358 "switching to INTx mode.\n",
fb2690a9
SH		 3359 pci_name(pdev));
3360
3361 err = -EOPNOTSUPP;
3362 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3363 }
3364
3365 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3366 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3367
3368 free_irq(pdev->irq, hw);
3369
3370 return err;
3371}
3372
cd28ab6a
SH		 3373static int __devinit sky2_probe(struct pci_dev *pdev,
3374 const struct pci_device_id *ent)
3375{
793b883e 3376 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3377 struct sky2_hw *hw;
5afa0a9c 3378 int err, pm_cap, using_dac = 0;
cd28ab6a 3379
793b883e
SH		 3380 err = pci_enable_device(pdev);
3381 if (err) {
cd28ab6a
SH		 3382 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3383 pci_name(pdev));
3384 goto err_out;
3385 }
3386
793b883e
SH		 3387 err = pci_request_regions(pdev, DRV_NAME);
3388 if (err) {
cd28ab6a
SH		 3389 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3390 pci_name(pdev));
793b883e 3391 goto err_out;
cd28ab6a
SH		 3392 }
3393
3394 pci_set_master(pdev);
3395
5afa0a9c 3396 /* Find power-management capability. */
3397 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3398 if (pm_cap == 0) {
3399 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3400 "aborting.\n");
3401 err = -EIO;
3402 goto err_out_free_regions;
3403 }
3404
d1f3d4dd
SH		 3405 if (sizeof(dma_addr_t) > sizeof(u32) &&
3406 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3407 using_dac = 1;
3408 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3409 if (err < 0) {
3410 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3411 "for consistent allocations\n", pci_name(pdev));
3412 goto err_out_free_regions;
3413 }
cd28ab6a 3414
d1f3d4dd 3415 } else {
cd28ab6a
SH		 3416 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3417 if (err) {
3418 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3419 pci_name(pdev));
3420 goto err_out_free_regions;
3421 }
3422 }
d1f3d4dd 3423
cd28ab6a 3424 err = -ENOMEM;
6aad85d6 3425 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3426 if (!hw) {
3427 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3428 pci_name(pdev));
3429 goto err_out_free_regions;
3430 }
3431
cd28ab6a 3432 hw->pdev = pdev;
cd28ab6a
SH		 3433
3434 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3435 if (!hw->regs) {
3436 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3437 pci_name(pdev));
3438 goto err_out_free_hw;
3439 }
5afa0a9c 3440 hw->pm_cap = pm_cap;
cd28ab6a 3441
56a645cc 3442#ifdef __BIG_ENDIAN
f65b138c
SH		 3443 /* The sk98lin vendor driver uses hardware byte swapping but
3444 * this driver uses software swapping.
3445 */
56a645cc
SH		 3446 {
3447 u32 reg;
56a645cc 3448 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3449 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3450 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3451 }
3452#endif
3453
08c06d8a
SH		 3454 /* ring for status responses */
3455 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3456 &hw->st_dma);
3457 if (!hw->st_le)
3458 goto err_out_iounmap;
3459
cd28ab6a
SH		 3460 err = sky2_reset(hw);
3461 if (err)
793b883e 3462 goto err_out_iounmap;
cd28ab6a 3463
7c7459d1
GKH		 3464 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3465 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3466 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3467 hw->chip_id, hw->chip_rev);
cd28ab6a 3468
793b883e
SH		 3469 dev = sky2_init_netdev(hw, 0, using_dac);
3470 if (!dev)
cd28ab6a
SH		 3471 goto err_out_free_pci;
3472
9fa1b1f3
SH		 3473 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3474 err = sky2_test_msi(hw);
3475 if (err == -EOPNOTSUPP)
3476 pci_disable_msi(pdev);
3477 else if (err)
3478 goto err_out_free_netdev;
3479 }
3480
793b883e
SH		 3481 err = register_netdev(dev);
3482 if (err) {
cd28ab6a
SH		 3483 printk(KERN_ERR PFX "%s: cannot register net device\n",
3484 pci_name(pdev));
3485 goto err_out_free_netdev;
3486 }
3487
b0a20ded
SH		 3488 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3489 dev->name, hw);
9fa1b1f3
SH		 3490 if (err) {
3491 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3492 pci_name(pdev), pdev->irq);
3493 goto err_out_unregister;
3494 }
3495 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3496
cd28ab6a
SH		 3497 sky2_show_addr(dev);
3498
3499 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3500 if (register_netdev(dev1) == 0)
3501 sky2_show_addr(dev1);
3502 else {
3503 /* Failure to register second port need not be fatal */
793b883e
SH		 3504 printk(KERN_WARNING PFX
3505 "register of second port failed\n");
cd28ab6a
SH		 3506 hw->dev[1] = NULL;
3507 free_netdev(dev1);
3508 }
3509 }
3510
01bd7564 3511 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
eb35cf60 3512 sky2_idle_start(hw);
d27ed387 3513
793b883e
SH		 3514 pci_set_drvdata(pdev, hw);
3515
cd28ab6a
SH		 3516 return 0;
3517
793b883e 3518err_out_unregister:
b0a20ded
SH		 3519 if (hw->msi)
3520 pci_disable_msi(pdev);
793b883e 3521 unregister_netdev(dev);
cd28ab6a
SH		 3522err_out_free_netdev:
3523 free_netdev(dev);
cd28ab6a 3524err_out_free_pci:
793b883e 3525 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3526 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3527err_out_iounmap:
3528 iounmap(hw->regs);
3529err_out_free_hw:
3530 kfree(hw);
3531err_out_free_regions:
3532 pci_release_regions(pdev);
cd28ab6a 3533 pci_disable_device(pdev);
cd28ab6a
SH		 3534err_out:
3535 return err;
3536}
3537
3538static void __devexit sky2_remove(struct pci_dev *pdev)
3539{
793b883e 3540 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3541 struct net_device *dev0, *dev1;
3542
793b883e 3543 if (!hw)
cd28ab6a
SH		 3544 return;
3545
d27ed387
SH		 3546 del_timer_sync(&hw->idle_timer);
3547
3548 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3549 synchronize_irq(hw->pdev->irq);
3550
cd28ab6a 3551 dev0 = hw->dev[0];
793b883e
SH		 3552 dev1 = hw->dev[1];
3553 if (dev1)
3554 unregister_netdev(dev1);
cd28ab6a
SH		 3555 unregister_netdev(dev0);
3556
5afa0a9c 3557 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3558 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3559 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3560 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3561
3562 free_irq(pdev->irq, hw);
b0a20ded
SH		 3563 if (hw->msi)
3564 pci_disable_msi(pdev);
793b883e 3565 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3566 pci_release_regions(pdev);
3567 pci_disable_device(pdev);
793b883e 3568
cd28ab6a
SH		 3569 if (dev1)
3570 free_netdev(dev1);
3571 free_netdev(dev0);
3572 iounmap(hw->regs);
3573 kfree(hw);
5afa0a9c 3574
cd28ab6a
SH		 3575 pci_set_drvdata(pdev, NULL);
3576}
3577
3578#ifdef CONFIG_PM
3579static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3580{
793b883e 3581 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3582 int i;
2ccc99b7
SH		 3583 pci_power_t pstate = pci_choose_state(pdev, state);
3584
3585 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3586 return -EINVAL;
cd28ab6a 3587
eb35cf60 3588 del_timer_sync(&hw->idle_timer);
6a5706b9 3589 netif_poll_disable(hw->dev[0]);
eb35cf60 3590
f05267e7 3591 for (i = 0; i < hw->ports; i++) {
cd28ab6a
SH		 3592 struct net_device *dev = hw->dev[i];
3593
6a5706b9 3594 if (netif_running(dev)) {
5afa0a9c 3595 sky2_down(dev);
cd28ab6a 3596 netif_device_detach(dev);
cd28ab6a
SH		 3597 }
3598 }
3599
8ab8fca2 3600 sky2_write32(hw, B0_IMSK, 0);
d374c1c1 3601 pci_save_state(pdev);
2ccc99b7
SH		 3602 sky2_set_power_state(hw, pstate);
3603 return 0;
cd28ab6a
SH		 3604}
3605
3606static int sky2_resume(struct pci_dev *pdev)
3607{
793b883e 3608 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3609 int i, err;
cd28ab6a 3610
cd28ab6a
SH		 3611 pci_restore_state(pdev);
3612 pci_enable_wake(pdev, PCI_D0, 0);
2ccc99b7 3613 sky2_set_power_state(hw, PCI_D0);
cd28ab6a 3614
08c06d8a
SH		 3615 err = sky2_reset(hw);
3616 if (err)
3617 goto out;
cd28ab6a 3618
8ab8fca2
SH		 3619 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3620
f05267e7 3621 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3622 struct net_device *dev = hw->dev[i];
6a5706b9 3623 if (netif_running(dev)) {
08c06d8a 3624 netif_device_attach(dev);
88d11360 3625
08c06d8a
SH		 3626 err = sky2_up(dev);
3627 if (err) {
3628 printk(KERN_ERR PFX "%s: could not up: %d\n",
3629 dev->name, err);
3630 dev_close(dev);
eb35cf60 3631 goto out;
5afa0a9c 3632 }
cd28ab6a
SH		 3633 }
3634 }
eb35cf60 3635
6a5706b9 3636 netif_poll_enable(hw->dev[0]);
eb35cf60 3637 sky2_idle_start(hw);
08c06d8a
SH		 3638out:
3639 return err;
cd28ab6a
SH		 3640}
3641#endif
3642
3643static struct pci_driver sky2_driver = {
793b883e
SH		 3644 .name = DRV_NAME,
3645 .id_table = sky2_id_table,
3646 .probe = sky2_probe,
3647 .remove = __devexit_p(sky2_remove),
cd28ab6a 3648#ifdef CONFIG_PM
793b883e
SH		 3649 .suspend = sky2_suspend,
3650 .resume = sky2_resume,
cd28ab6a
SH		 3651#endif
3652};
3653
3654static int __init sky2_init_module(void)
3655{
50241c4c 3656 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3657}
3658
3659static void __exit sky2_cleanup_module(void)
3660{
3661 pci_unregister_driver(&sky2_driver);
3662}
3663
3664module_init(sky2_init_module);
3665module_exit(sky2_cleanup_module);
3666
3667MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3668MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3669MODULE_LICENSE("GPL");
5f4f9dc1 3670MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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