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au1000_eth: use 'unsigned long' for irqflags
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a 26#include <linux/kernel.h>
cd28ab6a
SH		 27#include <linux/module.h>
28#include <linux/netdevice.h>
d0bbccfa 29#include <linux/dma-mapping.h>
cd28ab6a
SH		 30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/pci.h>
33#include <linux/ip.h>
c9bdd4b5 34#include <net/ip.h>
cd28ab6a
SH		 35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
3cf26753 41#include <linux/debugfs.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
743d32ad 53#define DRV_VERSION "1.22"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
793b883e
SH		 66
67#define TX_RING_SIZE 512
68#define TX_DEF_PENDING (TX_RING_SIZE - 1)
69#define TX_MIN_PENDING 64
b19666d9 70#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 71
793b883e 72#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 73#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 74#define TX_WATCHDOG (5 * HZ)
75#define NAPI_WEIGHT 64
76#define PHY_RETRIES 1000
77
f4331a6d
SH		 78#define SKY2_EEPROM_MAGIC 0x9955aabb
79
80
cb5d9547
SH		 81#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82
cd28ab6a 83static const u32 default_msg =
793b883e
SH		 84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 87
793b883e 88static int debug = -1; /* defaults above */
cd28ab6a
SH		 89module_param(debug, int, 0);
90MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91
14d0263f 92static int copybreak __read_mostly = 128;
bdb5c58e
SH		 93module_param(copybreak, int, 0);
94MODULE_PARM_DESC(copybreak, "Receive copy threshold");
95
fb2690a9
SH		 96static int disable_msi = 0;
97module_param(disable_msi, int, 0);
98MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
99
e6cac9ba 100static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
cd28ab6a
SH		 140 { 0 }
141};
793b883e 142
cd28ab6a
SH		 143MODULE_DEVICE_TABLE(pci, sky2_id_table);
144
145/* Avoid conditionals by using array */
146static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 148static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 149
d1b139c0
SH		 150static void sky2_set_multicast(struct net_device *dev);
151
af043aa5 152/* Access to PHY via serial interconnect */
ef743d33 153static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 154{
155 int i;
156
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160
161 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 162 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
163 if (ctrl == 0xffff)
164 goto io_error;
165
166 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 167 return 0;
af043aa5
SH		 168
169 udelay(10);
cd28ab6a 170 }
ef743d33 171
af043aa5 172 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 173 return -ETIMEDOUT;
af043aa5
SH		 174
175io_error:
176 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
177 return -EIO;
cd28ab6a
SH		 178}
179
ef743d33 180static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 181{
182 int i;
183
793b883e 184 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 185 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
186
187 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 188 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
189 if (ctrl == 0xffff)
190 goto io_error;
191
192 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33 193 *val = gma_read16(hw, port, GM_SMI_DATA);
194 return 0;
195 }
196
af043aa5 197 udelay(10);
cd28ab6a
SH		 198 }
199
af043aa5 200 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 201 return -ETIMEDOUT;
af043aa5
SH		 202io_error:
203 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
204 return -EIO;
ef743d33 205}
206
af043aa5 207static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33 208{
209 u16 v;
af043aa5 210 __gm_phy_read(hw, port, reg, &v);
ef743d33 211 return v;
cd28ab6a
SH		 212}
213
5afa0a9c 214
ae306cca
SH		 215static void sky2_power_on(struct sky2_hw *hw)
216{
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 220
ae306cca
SH		 221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 223
ae306cca
SH		 224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 else
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 232
ea76e635 233 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 234 u32 reg;
5afa0a9c 235
b32f40c4 236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 237
b32f40c4 238 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 239 /* set all bits to 0 except bits 15..12 and 8 */
240 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 241 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 242
b32f40c4 243 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 244 /* set all bits to 0 except bits 28 & 27 */
245 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 246 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 247
b32f40c4 248 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 249
250 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
251 reg = sky2_read32(hw, B2_GP_IO);
252 reg |= GLB_GPIO_STAT_RACE_DIS;
253 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 254
255 sky2_read32(hw, B2_GP_IO);
5afa0a9c 256 }
ae306cca 257}
5afa0a9c 258
ae306cca
SH		 259static void sky2_power_aux(struct sky2_hw *hw)
260{
261 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
262 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
263 else
264 /* enable bits are inverted */
265 sky2_write8(hw, B2_Y2_CLK_GATE,
266 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
267 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
268 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
269
270 /* switch power to VAUX */
271 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
272 sky2_write8(hw, B0_POWER_CTRL,
273 (PC_VAUX_ENA | PC_VCC_ENA |
274 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c 275}
276
d3bcfbeb 277static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 278{
279 u16 reg;
280
281 /* disable all GMAC IRQ's */
282 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 283
cd28ab6a
SH		 284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
285 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
288
289 reg = gma_read16(hw, port, GM_RX_CTRL);
290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
291 gma_write16(hw, port, GM_RX_CTRL, reg);
292}
293
16ad91e1
SH		 294/* flow control to advertise bits */
295static const u16 copper_fc_adv[] = {
296 [FC_NONE] = 0,
297 [FC_TX] = PHY_M_AN_ASP,
298 [FC_RX] = PHY_M_AN_PC,
299 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
300};
301
302/* flow control to advertise bits when using 1000BaseX */
303static const u16 fiber_fc_adv[] = {
df3fe1f3 304 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 305 [FC_TX] = PHY_M_P_ASYM_MD_X,
306 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 307 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 308};
309
310/* flow control to GMA disable bits */
311static const u16 gm_fc_disable[] = {
312 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
313 [FC_TX] = GM_GPCR_FC_RX_DIS,
314 [FC_RX] = GM_GPCR_FC_TX_DIS,
315 [FC_BOTH] = 0,
316};
317
318
cd28ab6a
SH		 319static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
320{
321 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 322 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 323
ea76e635
SH		 324 if (sky2->autoneg == AUTONEG_ENABLE &&
325 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 326 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
327
328 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 329 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 330 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
331
53419c68 332 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 333 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 334 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 335 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
336 else
53419c68
SH		 337 /* set master & slave downshift counter to 1x */
338 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 339
340 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
341 }
342
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 344 if (sky2_is_copper(hw)) {
05745c4a 345 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 346 /* enable automatic crossover */
347 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 348
349 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
350 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
351 u16 spec;
352
353 /* Enable Class A driver for FE+ A0 */
354 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
355 spec |= PHY_M_FESC_SEL_CL_A;
356 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
357 }
cd28ab6a
SH		 358 } else {
359 /* disable energy detect */
360 ctrl &= ~PHY_M_PC_EN_DET_MSK;
361
362 /* enable automatic crossover */
363 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
364
53419c68 365 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 366 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 367 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 368 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 369 ctrl &= ~PHY_M_PC_DSC_MSK;
370 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
371 }
372 }
cd28ab6a
SH		 373 } else {
374 /* workaround for deviation #4.88 (CRC errors) */
375 /* disable Automatic Crossover */
376
377 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 378 }
cd28ab6a 379
b89165f2
SH		 380 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
381
382 /* special setup for PHY 88E1112 Fiber */
ea76e635 383 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 384 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 385
b89165f2
SH		 386 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
387 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
388 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
389 ctrl &= ~PHY_M_MAC_MD_MSK;
390 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392
393 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 394 /* select page 1 to access Fiber registers */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 396
397 /* for SFP-module set SIGDET polarity to low */
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 401 }
b89165f2
SH		 402
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 404 }
405
7800fddc 406 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 407 ct1000 = 0;
408 adv = PHY_AN_CSMA;
2eaba1a2 409 reg = 0;
cd28ab6a
SH		 410
411 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 412 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 413 if (sky2->advertising & ADVERTISED_1000baseT_Full)
414 ct1000 |= PHY_M_1000C_AFD;
415 if (sky2->advertising & ADVERTISED_1000baseT_Half)
416 ct1000 |= PHY_M_1000C_AHD;
417 if (sky2->advertising & ADVERTISED_100baseT_Full)
418 adv |= PHY_M_AN_100_FD;
419 if (sky2->advertising & ADVERTISED_100baseT_Half)
420 adv |= PHY_M_AN_100_HD;
421 if (sky2->advertising & ADVERTISED_10baseT_Full)
422 adv |= PHY_M_AN_10_FD;
423 if (sky2->advertising & ADVERTISED_10baseT_Half)
424 adv |= PHY_M_AN_10_HD;
709c6e7b 425
16ad91e1 426 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 427 } else { /* special defines for FIBER (88E1040S only) */
428 if (sky2->advertising & ADVERTISED_1000baseT_Full)
429 adv |= PHY_M_AN_1000X_AFD;
430 if (sky2->advertising & ADVERTISED_1000baseT_Half)
431 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 432
16ad91e1 433 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 434 }
cd28ab6a
SH		 435
436 /* Restart Auto-negotiation */
437 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
438 } else {
439 /* forced speed/duplex settings */
440 ct1000 = PHY_M_1000C_MSE;
441
2eaba1a2
SH		 442 /* Disable auto update for duplex flow control and speed */
443 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 444
445 switch (sky2->speed) {
446 case SPEED_1000:
447 ctrl |= PHY_CT_SP1000;
2eaba1a2 448 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 449 break;
450 case SPEED_100:
451 ctrl |= PHY_CT_SP100;
2eaba1a2 452 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 453 break;
454 }
455
2eaba1a2
SH		 456 if (sky2->duplex == DUPLEX_FULL) {
457 reg |= GM_GPCR_DUP_FULL;
458 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 459 } else if (sky2->speed < SPEED_1000)
460 sky2->flow_mode = FC_NONE;
2eaba1a2 461
2eaba1a2 462
16ad91e1 463 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 464
465 /* Forward pause packets to GMAC? */
16ad91e1 466 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 467 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
468 else
469 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 470 }
471
2eaba1a2
SH		 472 gma_write16(hw, port, GM_GP_CTRL, reg);
473
05745c4a 474 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 475 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
476
477 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
478 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
479
480 /* Setup Phy LED's */
481 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
482 ledover = 0;
483
484 switch (hw->chip_id) {
485 case CHIP_ID_YUKON_FE:
486 /* on 88E3082 these bits are at 11..9 (shifted left) */
487 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
488
489 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
490
491 /* delete ACT LED control bits */
492 ctrl &= ~PHY_M_FELP_LED1_MSK;
493 /* change ACT LED control to blink mode */
494 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
495 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
496 break;
497
05745c4a
SH		 498 case CHIP_ID_YUKON_FE_P:
499 /* Enable Link Partner Next Page */
500 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
501 ctrl |= PHY_M_PC_ENA_LIP_NP;
502
503 /* disable Energy Detect and enable scrambler */
504 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
505 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
506
507 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
508 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
509 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
510 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
511
512 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
513 break;
514
cd28ab6a 515 case CHIP_ID_YUKON_XL:
793b883e 516 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 517
518 /* select page 3 to access LED control register */
519 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
520
521 /* set LED Function Control register */
ed6d32c7
SH		 522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
523 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
524 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
525 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
526 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 527
528 /* set Polarity Control register */
529 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 530 (PHY_M_POLC_LS1_P_MIX(4) |
531 PHY_M_POLC_IS0_P_MIX(4) |
532 PHY_M_POLC_LOS_CTRL(2) |
533 PHY_M_POLC_INIT_CTRL(2) |
534 PHY_M_POLC_STA1_CTRL(2) |
535 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 536
537 /* restore page register */
793b883e 538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 539 break;
93745494 540
ed6d32c7 541 case CHIP_ID_YUKON_EC_U:
93745494 542 case CHIP_ID_YUKON_EX:
ed4d4161 543 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 544 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
545
546 /* select page 3 to access LED control register */
547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
548
549 /* set LED Function Control register */
550 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
551 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
552 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
553 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
554 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
555
556 /* set Blink Rate in LED Timer Control Register */
557 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
558 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
559 /* restore page register */
560 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
561 break;
cd28ab6a
SH		 562
563 default:
564 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
565 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 566
cd28ab6a 567 /* turn off the Rx LED (LED_RX) */
a84d0a3d 568 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 569 }
570
0ce8b98d 571 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 572 /* apply fixes in PHY AFE */
ed6d32c7
SH		 573 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
574
977bdf06 575 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 576 gm_phy_write(hw, port, 0x18, 0xaa99);
577 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 578
0ce8b98d
SH		 579 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
580 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
581 gm_phy_write(hw, port, 0x18, 0xa204);
582 gm_phy_write(hw, port, 0x17, 0x2002);
583 }
977bdf06
SH		 584
585 /* set page register to 0 */
9467a8fc 586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 587 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
588 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
589 /* apply workaround for integrated resistors calibration */
590 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
591 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
e1a74b37
SH		 592 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
593 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 594 /* no effect on Yukon-XL */
977bdf06 595 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 596
977bdf06
SH		 597 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
598 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 599 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 600 }
cd28ab6a 601
977bdf06
SH		 602 if (ledover)
603 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
604
605 }
2eaba1a2 606
d571b694 607 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 608 if (sky2->autoneg == AUTONEG_ENABLE)
609 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
610 else
611 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
612}
613
b96936da
SH		 614static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
615static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
616
617static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb 618{
619 u32 reg1;
d3bcfbeb 620
82637e80 621 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 622 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 623 reg1 &= ~phy_power[port];
d3bcfbeb 624
b96936da 625 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 626 reg1 |= coma_mode[port];
627
b32f40c4 628 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80
SH		 629 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
630 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 631
632 if (hw->chip_id == CHIP_ID_YUKON_FE)
633 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
634 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
635 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 636}
167f53d0 637
b96936da
SH		 638static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
639{
640 u32 reg1;
db99b988
SH		 641 u16 ctrl;
642
643 /* release GPHY Control reset */
644 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
645
646 /* release GMAC reset */
647 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
648
649 if (hw->flags & SKY2_HW_NEWER_PHY) {
650 /* select page 2 to access MAC control register */
651 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
652
653 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
654 /* allow GMII Power Down */
655 ctrl &= ~PHY_M_MAC_GMIF_PUP;
656 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
657
658 /* set page register back to 0 */
659 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
660 }
661
662 /* setup General Purpose Control Register */
663 gma_write16(hw, port, GM_GP_CTRL,
664 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
665
666 if (hw->chip_id != CHIP_ID_YUKON_EC) {
667 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
668 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
669
670 /* enable Power Down */
671 ctrl |= PHY_M_PC_POW_D_ENA;
672 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
673 }
674
675 /* set IEEE compatible Power Down Mode (dev. #4.99) */
676 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
677 }
b96936da
SH		 678
679 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
680 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 681 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da
SH		 682 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
683 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb 684}
685
1b537565
SH		 686/* Force a renegotiation */
687static void sky2_phy_reinit(struct sky2_port *sky2)
688{
e07b1aa8 689 spin_lock_bh(&sky2->phy_lock);
1b537565 690 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 691 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 692}
693
e3173832
SH		 694/* Put device in state to listen for Wake On Lan */
695static void sky2_wol_init(struct sky2_port *sky2)
696{
697 struct sky2_hw *hw = sky2->hw;
698 unsigned port = sky2->port;
699 enum flow_control save_mode;
700 u16 ctrl;
701 u32 reg1;
702
703 /* Bring hardware out of reset */
704 sky2_write16(hw, B0_CTST, CS_RST_CLR);
705 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
706
707 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
708 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
709
710 /* Force to 10/100
711 * sky2_reset will re-enable on resume
712 */
713 save_mode = sky2->flow_mode;
714 ctrl = sky2->advertising;
715
716 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
717 sky2->flow_mode = FC_NONE;
b96936da
SH		 718
719 spin_lock_bh(&sky2->phy_lock);
720 sky2_phy_power_up(hw, port);
721 sky2_phy_init(hw, port);
722 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 723
724 sky2->flow_mode = save_mode;
725 sky2->advertising = ctrl;
726
727 /* Set GMAC to no flow control and auto update for speed/duplex */
728 gma_write16(hw, port, GM_GP_CTRL,
729 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
730 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
731
732 /* Set WOL address */
733 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
734 sky2->netdev->dev_addr, ETH_ALEN);
735
736 /* Turn on appropriate WOL control bits */
737 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
738 ctrl = 0;
739 if (sky2->wol & WAKE_PHY)
740 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
741 else
742 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
743
744 if (sky2->wol & WAKE_MAGIC)
745 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
746 else
747 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
748
749 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
750 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
751
752 /* Turn on legacy PCI-Express PME mode */
b32f40c4 753 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 754 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 755 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 756
757 /* block receiver */
758 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
759
760}
761
69161611
SH		 762static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
763{
05745c4a
SH		 764 struct net_device *dev = hw->dev[port];
765
ed4d4161
SH		 766 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
767 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
768 hw->chip_id == CHIP_ID_YUKON_FE_P ||
769 hw->chip_id == CHIP_ID_YUKON_SUPR) {
770 /* Yukon-Extreme B0 and further Extreme devices */
771 /* enable Store & Forward mode for TX */
05745c4a 772
ed4d4161
SH		 773 if (dev->mtu <= ETH_DATA_LEN)
774 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
775 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 776
ed4d4161
SH		 777 else
778 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
779 TX_JUMBO_ENA| TX_STFW_ENA);
780 } else {
781 if (dev->mtu <= ETH_DATA_LEN)
782 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
783 else {
784 /* set Tx GMAC FIFO Almost Empty Threshold */
785 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
786 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 787
ed4d4161
SH		 788 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
789
790 /* Can't do offload because of lack of store/forward */
791 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
792 }
69161611
SH		 793 }
794}
795
cd28ab6a
SH		 796static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
797{
798 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
799 u16 reg;
25cccecc 800 u32 rx_reg;
cd28ab6a
SH		 801 int i;
802 const u8 *addr = hw->dev[port]->dev_addr;
803
f350339c
SH		 804 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
805 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 806
807 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
808
793b883e 809 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 810 /* WA DEV_472 -- looks like crossed wires on port 2 */
811 /* clear GMAC 1 Control reset */
812 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
813 do {
814 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
815 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
816 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
817 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
818 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
819 }
820
793b883e 821 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 822
2eaba1a2
SH		 823 /* Enable Transmit FIFO Underrun */
824 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
825
e07b1aa8 826 spin_lock_bh(&sky2->phy_lock);
b96936da 827 sky2_phy_power_up(hw, port);
cd28ab6a 828 sky2_phy_init(hw, port);
e07b1aa8 829 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 830
831 /* MIB clear */
832 reg = gma_read16(hw, port, GM_PHY_ADDR);
833 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
834
43f2f104
SH		 835 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
836 gma_read16(hw, port, i);
cd28ab6a
SH		 837 gma_write16(hw, port, GM_PHY_ADDR, reg);
838
839 /* transmit control */
840 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
841
842 /* receive control reg: unicast + multicast + no FCS */
843 gma_write16(hw, port, GM_RX_CTRL,
793b883e 844 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 845
846 /* transmit flow control */
847 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
848
849 /* transmit parameter */
850 gma_write16(hw, port, GM_TX_PARAM,
851 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
852 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
853 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
854 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
855
856 /* serial mode register */
857 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 858 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 859
6b1a3aef 860 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 861 reg |= GM_SMOD_JUMBO_ENA;
862
863 gma_write16(hw, port, GM_SERIAL_MODE, reg);
864
cd28ab6a
SH		 865 /* virtual address for data */
866 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
867
793b883e
SH		 868 /* physical address: used for pause frames */
869 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
870
871 /* ignore counter overflows */
cd28ab6a
SH		 872 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
873 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
874 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
875
876 /* Configure Rx MAC FIFO */
877 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 878 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 879 if (hw->chip_id == CHIP_ID_YUKON_EX ||
880 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 881 rx_reg |= GMF_RX_OVER_ON;
69161611 882
25cccecc 883 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 884
798fdd07
SH		 885 if (hw->chip_id == CHIP_ID_YUKON_XL) {
886 /* Hardware errata - clear flush mask */
887 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
888 } else {
889 /* Flush Rx MAC FIFO on any flow control or error */
890 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
891 }
cd28ab6a 892
8df9a876 893 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 894 reg = RX_GMF_FL_THR_DEF + 1;
895 /* Another magic mystery workaround from sk98lin */
896 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
897 hw->chip_rev == CHIP_REV_YU_FE2_A0)
898 reg = 0x178;
899 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 900
901 /* Configure Tx MAC FIFO */
902 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
903 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 904
e0c28116 905 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 906 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
8df9a876 907 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 908 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 909
69161611 910 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 911 }
912
e970d1f8
SH		 913 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
914 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
915 /* disable dynamic watermark */
916 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
917 reg &= ~TX_DYN_WM_ENA;
918 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
919 }
cd28ab6a
SH		 920}
921
67712901
SH		 922/* Assign Ram Buffer allocation to queue */
923static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 924{
67712901
SH		 925 u32 end;
926
927 /* convert from K bytes to qwords used for hw register */
928 start *= 1024/8;
929 space *= 1024/8;
930 end = start + space - 1;
793b883e 931
cd28ab6a
SH		 932 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
933 sky2_write32(hw, RB_ADDR(q, RB_START), start);
934 sky2_write32(hw, RB_ADDR(q, RB_END), end);
935 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
936 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
937
938 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 939 u32 tp = space - space/4;
793b883e 940
1c28f6ba
SH		 941 /* On receive queue's set the thresholds
942 * give receiver priority when > 3/4 full
943 * send pause when down to 2K
944 */
945 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
946 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 947
1c28f6ba
SH		 948 tp = space - 2048/8;
949 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
950 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 951 } else {
952 /* Enable store & forward on Tx queue's because
953 * Tx FIFO is only 1K on Yukon
954 */
955 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
956 }
957
958 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 959 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 960}
961
cd28ab6a 962/* Setup Bus Memory Interface */
af4ed7e6 963static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 964{
965 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
966 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
967 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 968 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 969}
970
cd28ab6a
SH		 971/* Setup prefetch unit registers. This is the interface between
972 * hardware and driver list elements
973 */
8cc048e3 974static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 975 u64 addr, u32 last)
976{
cd28ab6a
SH		 977 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
978 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
979 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
980 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
981 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
982 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 983
984 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 985}
986
793b883e
SH		 987static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
988{
989 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
990
cb5d9547 991 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 992 le->ctrl = 0;
793b883e
SH		 993 return le;
994}
cd28ab6a 995
88f5f0ca
SH		 996static void tx_init(struct sky2_port *sky2)
997{
998 struct sky2_tx_le *le;
999
1000 sky2->tx_prod = sky2->tx_cons = 0;
1001 sky2->tx_tcpsum = 0;
1002 sky2->tx_last_mss = 0;
1003
1004 le = get_tx_le(sky2);
1005 le->addr = 0;
1006 le->opcode = OP_ADDR64 | HW_OWNER;
88f5f0ca
SH		 1007}
1008
291ea614
SH		 1009static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1010 struct sky2_tx_le *le)
1011{
1012 return sky2->tx_ring + (le - sky2->tx_le);
1013}
1014
290d4de5
SH		 1015/* Update chip's next pointer */
1016static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1017{
50432cb5 1018 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1019 wmb();
50432cb5
SH		 1020 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1021
1022 /* Synchronize I/O on since next processor may write to tail */
1023 mmiowb();
cd28ab6a
SH		 1024}
1025
793b883e 1026
cd28ab6a
SH		 1027static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1028{
1029 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1030 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1031 le->ctrl = 0;
cd28ab6a
SH		 1032 return le;
1033}
1034
14d0263f
SH		 1035/* Build description to hardware for one receive segment */
1036static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1037 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1038{
1039 struct sky2_rx_le *le;
1040
86c6887e 1041 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1042 le = sky2_next_rx(sky2);
86c6887e 1043 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1044 le->opcode = OP_ADDR64 | HW_OWNER;
1045 }
793b883e 1046
cd28ab6a 1047 le = sky2_next_rx(sky2);
734d1868
SH		 1048 le->addr = cpu_to_le32((u32) map);
1049 le->length = cpu_to_le16(len);
14d0263f 1050 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1051}
1052
14d0263f
SH		 1053/* Build description to hardware for one possibly fragmented skb */
1054static void sky2_rx_submit(struct sky2_port *sky2,
1055 const struct rx_ring_info *re)
1056{
1057 int i;
1058
1059 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1060
1061 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1062 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1063}
1064
1065
1066static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1067 unsigned size)
1068{
1069 struct sk_buff *skb = re->skb;
1070 int i;
1071
1072 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1073 pci_unmap_len_set(re, data_size, size);
1074
1075 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1076 re->frag_addr[i] = pci_map_page(pdev,
1077 skb_shinfo(skb)->frags[i].page,
1078 skb_shinfo(skb)->frags[i].page_offset,
1079 skb_shinfo(skb)->frags[i].size,
1080 PCI_DMA_FROMDEVICE);
1081}
1082
1083static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1084{
1085 struct sk_buff *skb = re->skb;
1086 int i;
1087
1088 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1089 PCI_DMA_FROMDEVICE);
1090
1091 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1092 pci_unmap_page(pdev, re->frag_addr[i],
1093 skb_shinfo(skb)->frags[i].size,
1094 PCI_DMA_FROMDEVICE);
1095}
793b883e 1096
cd28ab6a
SH		 1097/* Tell chip where to start receive checksum.
1098 * Actually has two checksums, but set both same to avoid possible byte
1099 * order problems.
1100 */
793b883e 1101static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1102{
ea76e635 1103 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1104
ea76e635
SH		 1105 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1106 le->ctrl = 0;
1107 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1108
ea76e635
SH		 1109 sky2_write32(sky2->hw,
1110 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1111 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1112}
1113
6b1a3aef 1114/*
1115 * The RX Stop command will not work for Yukon-2 if the BMU does not
1116 * reach the end of packet and since we can't make sure that we have
1117 * incoming data, we must reset the BMU while it is not doing a DMA
1118 * transfer. Since it is possible that the RX path is still active,
1119 * the RX RAM buffer will be stopped first, so any possible incoming
1120 * data will not trigger a DMA. After the RAM buffer is stopped, the
1121 * BMU is polled until any DMA in progress is ended and only then it
1122 * will be reset.
1123 */
1124static void sky2_rx_stop(struct sky2_port *sky2)
1125{
1126 struct sky2_hw *hw = sky2->hw;
1127 unsigned rxq = rxqaddr[sky2->port];
1128 int i;
1129
1130 /* disable the RAM Buffer receive queue */
1131 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1132
1133 for (i = 0; i < 0xffff; i++)
1134 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1135 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1136 goto stopped;
1137
1138 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1139 sky2->netdev->name);
1140stopped:
1141 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1142
1143 /* reset the Rx prefetch unit */
1144 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1145 mmiowb();
6b1a3aef 1146}
793b883e 1147
d571b694 1148/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1149static void sky2_rx_clean(struct sky2_port *sky2)
1150{
1151 unsigned i;
1152
1153 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1154 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1155 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1156
1157 if (re->skb) {
14d0263f 1158 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1159 kfree_skb(re->skb);
1160 re->skb = NULL;
1161 }
1162 }
1163}
1164
ef743d33 1165/* Basic MII support */
1166static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1167{
1168 struct mii_ioctl_data *data = if_mii(ifr);
1169 struct sky2_port *sky2 = netdev_priv(dev);
1170 struct sky2_hw *hw = sky2->hw;
1171 int err = -EOPNOTSUPP;
1172
1173 if (!netif_running(dev))
1174 return -ENODEV; /* Phy still in reset */
1175
d89e1343 1176 switch (cmd) {
ef743d33 1177 case SIOCGMIIPHY:
1178 data->phy_id = PHY_ADDR_MARV;
1179
1180 /* fallthru */
1181 case SIOCGMIIREG: {
1182 u16 val = 0;
91c86df5 1183
e07b1aa8 1184 spin_lock_bh(&sky2->phy_lock);
ef743d33 1185 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1186 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1187
ef743d33 1188 data->val_out = val;
1189 break;
1190 }
1191
1192 case SIOCSMIIREG:
1193 if (!capable(CAP_NET_ADMIN))
1194 return -EPERM;
1195
e07b1aa8 1196 spin_lock_bh(&sky2->phy_lock);
ef743d33 1197 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1198 data->val_in);
e07b1aa8 1199 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1200 break;
1201 }
1202 return err;
1203}
1204
d1f13708 1205#ifdef SKY2_VLAN_TAG_USED
d494eacd 1206static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1207{
d494eacd 1208 if (onoff) {
3d4e66f5
SH		 1209 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1210 RX_VLAN_STRIP_ON);
1211 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1212 TX_VLAN_TAG_ON);
1213 } else {
1214 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1215 RX_VLAN_STRIP_OFF);
1216 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1217 TX_VLAN_TAG_OFF);
1218 }
d494eacd
SH		 1219}
1220
1221static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1222{
1223 struct sky2_port *sky2 = netdev_priv(dev);
1224 struct sky2_hw *hw = sky2->hw;
1225 u16 port = sky2->port;
1226
1227 netif_tx_lock_bh(dev);
1228 napi_disable(&hw->napi);
1229
1230 sky2->vlgrp = grp;
1231 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1232
d1d08d12 1233 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1234 napi_enable(&hw->napi);
2bb8c262 1235 netif_tx_unlock_bh(dev);
d1f13708 1236}
1237#endif
1238
82788c7a 1239/*
14d0263f
SH		 1240 * Allocate an skb for receiving. If the MTU is large enough
1241 * make the skb non-linear with a fragment list of pages.
82788c7a 1242 */
14d0263f 1243static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1244{
1245 struct sk_buff *skb;
14d0263f 1246 int i;
82788c7a 1247
39dbd958 1248 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1249 unsigned char *start;
1250 /*
1251 * Workaround for a bug in FIFO that cause hang
1252 * if the FIFO if the receive buffer is not 64 byte aligned.
1253 * The buffer returned from netdev_alloc_skb is
1254 * aligned except if slab debugging is enabled.
1255 */
1256 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1257 if (!skb)
1258 goto nomem;
1259 start = PTR_ALIGN(skb->data, 8);
1260 skb_reserve(skb, start - skb->data);
1261 } else {
1262 skb = netdev_alloc_skb(sky2->netdev,
1263 sky2->rx_data_size + NET_IP_ALIGN);
1264 if (!skb)
1265 goto nomem;
1266 skb_reserve(skb, NET_IP_ALIGN);
1267 }
14d0263f
SH		 1268
1269 for (i = 0; i < sky2->rx_nfrags; i++) {
1270 struct page *page = alloc_page(GFP_ATOMIC);
1271
1272 if (!page)
1273 goto free_partial;
1274 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1275 }
1276
1277 return skb;
14d0263f
SH		 1278free_partial:
1279 kfree_skb(skb);
1280nomem:
1281 return NULL;
82788c7a
SH		 1282}
1283
55c9dd35
SH		 1284static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1285{
1286 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1287}
1288
cd28ab6a
SH		 1289/*
1290 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1291 * Normal case this ends up creating one list element for skb
1292 * in the receive ring. Worst case if using large MTU and each
1293 * allocation falls on a different 64 bit region, that results
1294 * in 6 list elements per ring entry.
1295 * One element is used for checksum enable/disable, and one
1296 * extra to avoid wrap.
cd28ab6a 1297 */
6b1a3aef 1298static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1299{
6b1a3aef 1300 struct sky2_hw *hw = sky2->hw;
14d0263f 1301 struct rx_ring_info *re;
6b1a3aef 1302 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1303 unsigned i, size, thresh;
cd28ab6a 1304
6b1a3aef 1305 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1306 sky2_qset(hw, rxq);
977bdf06 1307
c3905bc4
SH		 1308 /* On PCI express lowering the watermark gives better performance */
1309 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1310 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1311
1312 /* These chips have no ram buffer?
1313 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1314 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1315 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1316 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1317 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1318
6b1a3aef 1319 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1320
ea76e635
SH		 1321 if (!(hw->flags & SKY2_HW_NEW_LE))
1322 rx_set_checksum(sky2);
14d0263f
SH		 1323
1324 /* Space needed for frame data + headers rounded up */
f957da2a 1325 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1326
1327 /* Stopping point for hardware truncation */
1328 thresh = (size - 8) / sizeof(u32);
1329
5f06eba4 1330 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1331 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1332
5f06eba4
SH		 1333 /* Compute residue after pages */
1334 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1335
5f06eba4
SH		 1336 /* Optimize to handle small packets and headers */
1337 if (size < copybreak)
1338 size = copybreak;
1339 if (size < ETH_HLEN)
1340 size = ETH_HLEN;
14d0263f 1341
14d0263f
SH		 1342 sky2->rx_data_size = size;
1343
1344 /* Fill Rx ring */
793b883e 1345 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1346 re = sky2->rx_ring + i;
cd28ab6a 1347
14d0263f 1348 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1349 if (!re->skb)
1350 goto nomem;
1351
14d0263f
SH		 1352 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1353 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1354 }
1355
a1433ac4
SH		 1356 /*
1357 * The receiver hangs if it receives frames larger than the
1358 * packet buffer. As a workaround, truncate oversize frames, but
1359 * the register is limited to 9 bits, so if you do frames > 2052
1360 * you better get the MTU right!
1361 */
a1433ac4
SH		 1362 if (thresh > 0x1ff)
1363 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1364 else {
1365 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1366 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1367 }
1368
6b1a3aef 1369 /* Tell chip about available buffers */
55c9dd35 1370 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1371 return 0;
1372nomem:
1373 sky2_rx_clean(sky2);
1374 return -ENOMEM;
1375}
1376
1377/* Bring up network interface. */
1378static int sky2_up(struct net_device *dev)
1379{
1380 struct sky2_port *sky2 = netdev_priv(dev);
1381 struct sky2_hw *hw = sky2->hw;
1382 unsigned port = sky2->port;
e0c28116 1383 u32 imask, ramsize;
ee7abb04 1384 int cap, err = -ENOMEM;
843a46f4 1385 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1386
ee7abb04
SH		 1387 /*
1388 * On dual port PCI-X card, there is an problem where status
1389 * can be received out of order due to split transactions
843a46f4 1390 */
ee7abb04
SH		 1391 if (otherdev && netif_running(otherdev) &&
1392 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1393 u16 cmd;
1394
b32f40c4 1395 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1396 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1397 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1398
ee7abb04 1399 }
843a46f4 1400
cd28ab6a
SH		 1401 if (netif_msg_ifup(sky2))
1402 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1403
55d7b4e6
SH		 1404 netif_carrier_off(dev);
1405
cd28ab6a
SH		 1406 /* must be power of 2 */
1407 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1408 TX_RING_SIZE *
1409 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1410 &sky2->tx_le_map);
1411 if (!sky2->tx_le)
1412 goto err_out;
1413
6cdbbdf3 1414 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1415 GFP_KERNEL);
1416 if (!sky2->tx_ring)
1417 goto err_out;
88f5f0ca
SH		 1418
1419 tx_init(sky2);
cd28ab6a
SH		 1420
1421 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1422 &sky2->rx_le_map);
1423 if (!sky2->rx_le)
1424 goto err_out;
1425 memset(sky2->rx_le, 0, RX_LE_BYTES);
1426
291ea614 1427 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1428 GFP_KERNEL);
1429 if (!sky2->rx_ring)
1430 goto err_out;
1431
1432 sky2_mac_init(hw, port);
1433
e0c28116
SH		 1434 /* Register is number of 4K blocks on internal RAM buffer. */
1435 ramsize = sky2_read8(hw, B2_E_0) * 4;
1436 if (ramsize > 0) {
67712901 1437 u32 rxspace;
cd28ab6a 1438
39dbd958 1439 hw->flags |= SKY2_HW_RAM_BUFFER;
e0c28116 1440 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1441 if (ramsize < 16)
1442 rxspace = ramsize / 2;
1443 else
1444 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1445
67712901
SH		 1446 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1447 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1448
1449 /* Make sure SyncQ is disabled */
1450 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1451 RB_RST_SET);
1452 }
793b883e 1453
af4ed7e6 1454 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1455
69161611
SH		 1456 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1457 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1458 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1459
977bdf06 1460 /* Set almost empty threshold */
c2716fb4
SH		 1461 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1462 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1463 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1464
6b1a3aef 1465 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1466 TX_RING_SIZE - 1);
cd28ab6a 1467
d494eacd
SH		 1468#ifdef SKY2_VLAN_TAG_USED
1469 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1470#endif
1471
6b1a3aef 1472 err = sky2_rx_start(sky2);
6de16237 1473 if (err)
cd28ab6a
SH		 1474 goto err_out;
1475
cd28ab6a 1476 /* Enable interrupts from phy/mac for port */
e07b1aa8 1477 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1478 imask |= portirq_msk[port];
e07b1aa8
SH		 1479 sky2_write32(hw, B0_IMSK, imask);
1480
a7bffe72 1481 sky2_set_multicast(dev);
cd28ab6a
SH		 1482 return 0;
1483
1484err_out:
1b537565 1485 if (sky2->rx_le) {
cd28ab6a
SH		 1486 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1487 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1488 sky2->rx_le = NULL;
1489 }
1490 if (sky2->tx_le) {
cd28ab6a
SH		 1491 pci_free_consistent(hw->pdev,
1492 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1493 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1494 sky2->tx_le = NULL;
1495 }
1496 kfree(sky2->tx_ring);
1497 kfree(sky2->rx_ring);
cd28ab6a 1498
1b537565
SH		 1499 sky2->tx_ring = NULL;
1500 sky2->rx_ring = NULL;
cd28ab6a
SH		 1501 return err;
1502}
1503
793b883e
SH		 1504/* Modular subtraction in ring */
1505static inline int tx_dist(unsigned tail, unsigned head)
1506{
cb5d9547 1507 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1508}
cd28ab6a 1509
793b883e
SH		 1510/* Number of list elements available for next tx */
1511static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1512{
793b883e 1513 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1514}
1515
793b883e 1516/* Estimate of number of transmit list elements required */
28bd181a 1517static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1518{
793b883e
SH		 1519 unsigned count;
1520
1521 count = sizeof(dma_addr_t) / sizeof(u32);
1522 count += skb_shinfo(skb)->nr_frags * count;
1523
89114afd 1524 if (skb_is_gso(skb))
793b883e
SH		 1525 ++count;
1526
84fa7933 1527 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1528 ++count;
1529
1530 return count;
cd28ab6a
SH		 1531}
1532
793b883e
SH		 1533/*
1534 * Put one packet in ring for transmit.
1535 * A single packet can generate multiple list elements, and
1536 * the number of ring elements will probably be less than the number
1537 * of list elements used.
1538 */
cd28ab6a
SH		 1539static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1540{
1541 struct sky2_port *sky2 = netdev_priv(dev);
1542 struct sky2_hw *hw = sky2->hw;
d1f13708 1543 struct sky2_tx_le *le = NULL;
6cdbbdf3 1544 struct tx_ring_info *re;
cd28ab6a
SH		 1545 unsigned i, len;
1546 dma_addr_t mapping;
cd28ab6a
SH		 1547 u16 mss;
1548 u8 ctrl;
1549
2bb8c262
SH		 1550 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1551 return NETDEV_TX_BUSY;
cd28ab6a 1552
793b883e 1553 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1554 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1555 dev->name, sky2->tx_prod, skb->len);
1556
cd28ab6a
SH		 1557 len = skb_headlen(skb);
1558 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1559
86c6887e
SH		 1560 /* Send high bits if needed */
1561 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1562 le = get_tx_le(sky2);
86c6887e 1563 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e 1564 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1565 }
cd28ab6a
SH		 1566
1567 /* Check for TCP Segmentation Offload */
7967168c 1568 mss = skb_shinfo(skb)->gso_size;
793b883e 1569 if (mss != 0) {
ea76e635
SH		 1570
1571 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1572 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1573
1574 if (mss != sky2->tx_last_mss) {
1575 le = get_tx_le(sky2);
1576 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1577
1578 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1579 le->opcode = OP_MSS | HW_OWNER;
1580 else
1581 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1582 sky2->tx_last_mss = mss;
1583 }
cd28ab6a
SH		 1584 }
1585
cd28ab6a 1586 ctrl = 0;
d1f13708 1587#ifdef SKY2_VLAN_TAG_USED
1588 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1589 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1590 if (!le) {
1591 le = get_tx_le(sky2);
f65b138c 1592 le->addr = 0;
d1f13708 1593 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1594 } else
1595 le->opcode |= OP_VLAN;
1596 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1597 ctrl |= INS_VLAN;
1598 }
1599#endif
1600
1601 /* Handle TCP checksum offload */
84fa7933 1602 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1603 /* On Yukon EX (some versions) encoding change. */
ea76e635 1604 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1605 ctrl |= CALSUM; /* auto checksum */
1606 else {
1607 const unsigned offset = skb_transport_offset(skb);
1608 u32 tcpsum;
1609
1610 tcpsum = offset << 16; /* sum start */
1611 tcpsum |= offset + skb->csum_offset; /* sum write */
1612
1613 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1614 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1615 ctrl |= UDPTCP;
1616
1617 if (tcpsum != sky2->tx_tcpsum) {
1618 sky2->tx_tcpsum = tcpsum;
1619
1620 le = get_tx_le(sky2);
1621 le->addr = cpu_to_le32(tcpsum);
1622 le->length = 0; /* initial checksum value */
1623 le->ctrl = 1; /* one packet */
1624 le->opcode = OP_TCPLISW | HW_OWNER;
1625 }
1d179332 1626 }
cd28ab6a
SH		 1627 }
1628
1629 le = get_tx_le(sky2);
f65b138c 1630 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1631 le->length = cpu_to_le16(len);
1632 le->ctrl = ctrl;
793b883e 1633 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1634
291ea614 1635 re = tx_le_re(sky2, le);
cd28ab6a 1636 re->skb = skb;
6cdbbdf3 1637 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1638 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1639
1640 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1641 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1642
1643 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1644 frag->size, PCI_DMA_TODEVICE);
86c6887e
SH		 1645
1646 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1647 le = get_tx_le(sky2);
86c6887e 1648 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e
SH		 1649 le->ctrl = 0;
1650 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1651 }
1652
1653 le = get_tx_le(sky2);
f65b138c 1654 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1655 le->length = cpu_to_le16(frag->size);
1656 le->ctrl = ctrl;
793b883e 1657 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1658
291ea614
SH		 1659 re = tx_le_re(sky2, le);
1660 re->skb = skb;
1661 pci_unmap_addr_set(re, mapaddr, mapping);
1662 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1663 }
6cdbbdf3 1664
cd28ab6a
SH		 1665 le->ctrl |= EOP;
1666
97bda706 1667 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1668 netif_stop_queue(dev);
b19666d9 1669
290d4de5 1670 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1671
cd28ab6a
SH		 1672 dev->trans_start = jiffies;
1673 return NETDEV_TX_OK;
1674}
1675
cd28ab6a 1676/*
793b883e
SH		 1677 * Free ring elements from starting at tx_cons until "done"
1678 *
1679 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1680 * buffers so make sure not to free skb to early.
cd28ab6a 1681 */
d11c13e7 1682static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1683{
d11c13e7 1684 struct net_device *dev = sky2->netdev;
af2a58ac 1685 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1686 unsigned idx;
cd28ab6a 1687
0e3ff6aa 1688 BUG_ON(done >= TX_RING_SIZE);
2224795d 1689
291ea614
SH		 1690 for (idx = sky2->tx_cons; idx != done;
1691 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1692 struct sky2_tx_le *le = sky2->tx_le + idx;
1693 struct tx_ring_info *re = sky2->tx_ring + idx;
1694
1695 switch(le->opcode & ~HW_OWNER) {
1696 case OP_LARGESEND:
1697 case OP_PACKET:
1698 pci_unmap_single(pdev,
1699 pci_unmap_addr(re, mapaddr),
1700 pci_unmap_len(re, maplen),
1701 PCI_DMA_TODEVICE);
af2a58ac 1702 break;
291ea614
SH		 1703 case OP_BUFFER:
1704 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1705 pci_unmap_len(re, maplen),
734d1868 1706 PCI_DMA_TODEVICE);
291ea614
SH		 1707 break;
1708 }
1709
1710 if (le->ctrl & EOP) {
1711 if (unlikely(netif_msg_tx_done(sky2)))
1712 printk(KERN_DEBUG "%s: tx done %u\n",
1713 dev->name, idx);
3cf26753 1714
7138a0f5
SH		 1715 dev->stats.tx_packets++;
1716 dev->stats.tx_bytes += re->skb->len;
2bf56fe2 1717
794b2bd2 1718 dev_kfree_skb_any(re->skb);
3cf26753 1719 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1720 }
793b883e 1721 }
793b883e 1722
291ea614 1723 sky2->tx_cons = idx;
50432cb5
SH		 1724 smp_mb();
1725
22e11703 1726 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1727 netif_wake_queue(dev);
cd28ab6a
SH		 1728}
1729
1730/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1731static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1732{
2bb8c262
SH		 1733 struct sky2_port *sky2 = netdev_priv(dev);
1734
1735 netif_tx_lock_bh(dev);
d11c13e7 1736 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1737 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1738}
1739
1740/* Network shutdown */
1741static int sky2_down(struct net_device *dev)
1742{
1743 struct sky2_port *sky2 = netdev_priv(dev);
1744 struct sky2_hw *hw = sky2->hw;
1745 unsigned port = sky2->port;
1746 u16 ctrl;
e07b1aa8 1747 u32 imask;
cd28ab6a 1748
1b537565
SH		 1749 /* Never really got started! */
1750 if (!sky2->tx_le)
1751 return 0;
1752
cd28ab6a
SH		 1753 if (netif_msg_ifdown(sky2))
1754 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1755
ebc646f6
SH		 1756 /* Disable port IRQ */
1757 imask = sky2_read32(hw, B0_IMSK);
1758 imask &= ~portirq_msk[port];
1759 sky2_write32(hw, B0_IMSK, imask);
1760
6de16237
SH		 1761 synchronize_irq(hw->pdev->irq);
1762
d3bcfbeb 1763 sky2_gmac_reset(hw, port);
793b883e 1764
cd28ab6a
SH		 1765 /* Stop transmitter */
1766 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1767 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1768
1769 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1770 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1771
1772 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1773 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1774 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1775
6de16237
SH		 1776 /* Make sure no packets are pending */
1777 napi_synchronize(&hw->napi);
1778
cd28ab6a
SH		 1779 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1780
1781 /* Workaround shared GMAC reset */
793b883e
SH		 1782 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1783 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1784 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1785
1786 /* Disable Force Sync bit and Enable Alloc bit */
1787 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1788 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1789
1790 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1791 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1792 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1793
1794 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1795 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1796 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1797
1798 /* Reset the Tx prefetch units */
1799 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1800 PREF_UNIT_RST_SET);
1801
1802 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1803
6b1a3aef 1804 sky2_rx_stop(sky2);
cd28ab6a
SH		 1805
1806 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1807 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1808
b96936da 1809 sky2_phy_power_down(hw, port);
d3bcfbeb 1810
d571b694 1811 /* turn off LED's */
cd28ab6a
SH		 1812 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1813
2bb8c262 1814 sky2_tx_clean(dev);
cd28ab6a
SH		 1815 sky2_rx_clean(sky2);
1816
1817 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1818 sky2->rx_le, sky2->rx_le_map);
1819 kfree(sky2->rx_ring);
1820
1821 pci_free_consistent(hw->pdev,
1822 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1823 sky2->tx_le, sky2->tx_le_map);
1824 kfree(sky2->tx_ring);
1825
1b537565
SH		 1826 sky2->tx_le = NULL;
1827 sky2->rx_le = NULL;
1828
1829 sky2->rx_ring = NULL;
1830 sky2->tx_ring = NULL;
1831
cd28ab6a
SH		 1832 return 0;
1833}
1834
1835static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1836{
ea76e635 1837 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1838 return SPEED_1000;
1839
05745c4a
SH		 1840 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1841 if (aux & PHY_M_PS_SPEED_100)
1842 return SPEED_100;
1843 else
1844 return SPEED_10;
1845 }
cd28ab6a
SH		 1846
1847 switch (aux & PHY_M_PS_SPEED_MSK) {
1848 case PHY_M_PS_SPEED_1000:
1849 return SPEED_1000;
1850 case PHY_M_PS_SPEED_100:
1851 return SPEED_100;
1852 default:
1853 return SPEED_10;
1854 }
1855}
1856
1857static void sky2_link_up(struct sky2_port *sky2)
1858{
1859 struct sky2_hw *hw = sky2->hw;
1860 unsigned port = sky2->port;
1861 u16 reg;
16ad91e1
SH		 1862 static const char *fc_name[] = {
1863 [FC_NONE] = "none",
1864 [FC_TX] = "tx",
1865 [FC_RX] = "rx",
1866 [FC_BOTH] = "both",
1867 };
cd28ab6a 1868
cd28ab6a 1869 /* enable Rx/Tx */
2eaba1a2 1870 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1871 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1872 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1873
1874 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1875
1876 netif_carrier_on(sky2->netdev);
cd28ab6a 1877
75e80683 1878 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1879
cd28ab6a 1880 /* Turn on link LED */
793b883e 1881 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1882 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1883
1884 if (netif_msg_link(sky2))
1885 printk(KERN_INFO PFX
d571b694 1886 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1887 sky2->netdev->name, sky2->speed,
1888 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1889 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1890}
1891
1892static void sky2_link_down(struct sky2_port *sky2)
1893{
1894 struct sky2_hw *hw = sky2->hw;
1895 unsigned port = sky2->port;
1896 u16 reg;
1897
1898 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1899
1900 reg = gma_read16(hw, port, GM_GP_CTRL);
1901 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1902 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1903
cd28ab6a 1904 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1905
1906 /* Turn on link LED */
1907 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1908
1909 if (netif_msg_link(sky2))
1910 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1911
cd28ab6a
SH		 1912 sky2_phy_init(hw, port);
1913}
1914
16ad91e1
SH		 1915static enum flow_control sky2_flow(int rx, int tx)
1916{
1917 if (rx)
1918 return tx ? FC_BOTH : FC_RX;
1919 else
1920 return tx ? FC_TX : FC_NONE;
1921}
1922
793b883e
SH		 1923static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1924{
1925 struct sky2_hw *hw = sky2->hw;
1926 unsigned port = sky2->port;
da4c1ff4 1927 u16 advert, lpa;
793b883e 1928
da4c1ff4 1929 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1930 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1931 if (lpa & PHY_M_AN_RF) {
1932 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1933 return -1;
1934 }
1935
793b883e
SH		 1936 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1937 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1938 sky2->netdev->name);
1939 return -1;
1940 }
1941
793b883e 1942 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1943 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1944
da4c1ff4
SH		 1945 /* Since the pause result bits seem to in different positions on
1946 * different chips. look at registers.
1947 */
ea76e635 1948 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 1949 /* Shift for bits in fiber PHY */
1950 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1951 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1952
1953 if (advert & ADVERTISE_1000XPAUSE)
1954 advert |= ADVERTISE_PAUSE_CAP;
1955 if (advert & ADVERTISE_1000XPSE_ASYM)
1956 advert |= ADVERTISE_PAUSE_ASYM;
1957 if (lpa & LPA_1000XPAUSE)
1958 lpa |= LPA_PAUSE_CAP;
1959 if (lpa & LPA_1000XPAUSE_ASYM)
1960 lpa |= LPA_PAUSE_ASYM;
1961 }
793b883e 1962
da4c1ff4
SH		 1963 sky2->flow_status = FC_NONE;
1964 if (advert & ADVERTISE_PAUSE_CAP) {
1965 if (lpa & LPA_PAUSE_CAP)
1966 sky2->flow_status = FC_BOTH;
1967 else if (advert & ADVERTISE_PAUSE_ASYM)
1968 sky2->flow_status = FC_RX;
1969 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1970 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1971 sky2->flow_status = FC_TX;
1972 }
793b883e 1973
16ad91e1 1974 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1975 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1976 sky2->flow_status = FC_NONE;
2eaba1a2 1977
da4c1ff4 1978 if (sky2->flow_status & FC_TX)
793b883e
SH		 1979 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1980 else
1981 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1982
1983 return 0;
1984}
cd28ab6a 1985
e07b1aa8
SH		 1986/* Interrupt from PHY */
1987static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1988{
e07b1aa8
SH		 1989 struct net_device *dev = hw->dev[port];
1990 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1991 u16 istatus, phystat;
1992
ebc646f6
SH		 1993 if (!netif_running(dev))
1994 return;
1995
e07b1aa8
SH		 1996 spin_lock(&sky2->phy_lock);
1997 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1998 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1999
cd28ab6a
SH		 2000 if (netif_msg_intr(sky2))
2001 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2002 sky2->netdev->name, istatus, phystat);
2003
2eaba1a2 2004 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 2005 if (sky2_autoneg_done(sky2, phystat) == 0)
2006 sky2_link_up(sky2);
2007 goto out;
2008 }
cd28ab6a 2009
793b883e
SH		 2010 if (istatus & PHY_M_IS_LSP_CHANGE)
2011 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2012
793b883e
SH		 2013 if (istatus & PHY_M_IS_DUP_CHANGE)
2014 sky2->duplex =
2015 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2016
793b883e
SH		 2017 if (istatus & PHY_M_IS_LST_CHANGE) {
2018 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2019 sky2_link_up(sky2);
793b883e
SH		 2020 else
2021 sky2_link_down(sky2);
cd28ab6a 2022 }
793b883e 2023out:
e07b1aa8 2024 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2025}
2026
62335ab0 2027/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2028 * and tx queue is full (stopped).
2029 */
cd28ab6a
SH		 2030static void sky2_tx_timeout(struct net_device *dev)
2031{
2032 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2033 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2034
2035 if (netif_msg_timer(sky2))
2036 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2037
8f24664d 2038 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2039 dev->name, sky2->tx_cons, sky2->tx_prod,
2040 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2041 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2042
81906791
SH		 2043 /* can't restart safely under softirq */
2044 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2045}
2046
2047static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2048{
6b1a3aef 2049 struct sky2_port *sky2 = netdev_priv(dev);
2050 struct sky2_hw *hw = sky2->hw;
b628ed98 2051 unsigned port = sky2->port;
6b1a3aef 2052 int err;
2053 u16 ctl, mode;
e07b1aa8 2054 u32 imask;
cd28ab6a
SH		 2055
2056 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2057 return -EINVAL;
2058
05745c4a
SH		 2059 if (new_mtu > ETH_DATA_LEN &&
2060 (hw->chip_id == CHIP_ID_YUKON_FE ||
2061 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2062 return -EINVAL;
2063
6b1a3aef 2064 if (!netif_running(dev)) {
2065 dev->mtu = new_mtu;
2066 return 0;
2067 }
2068
e07b1aa8 2069 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 2070 sky2_write32(hw, B0_IMSK, 0);
2071
018d1c66 2072 dev->trans_start = jiffies; /* prevent tx timeout */
2073 netif_stop_queue(dev);
bea3348e 2074 napi_disable(&hw->napi);
018d1c66 2075
e07b1aa8
SH		 2076 synchronize_irq(hw->pdev->irq);
2077
39dbd958 2078 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2079 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2080
2081 ctl = gma_read16(hw, port, GM_GP_CTRL);
2082 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 2083 sky2_rx_stop(sky2);
2084 sky2_rx_clean(sky2);
cd28ab6a
SH		 2085
2086 dev->mtu = new_mtu;
14d0263f 2087
6b1a3aef 2088 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2089 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2090
2091 if (dev->mtu > ETH_DATA_LEN)
2092 mode |= GM_SMOD_JUMBO_ENA;
2093
b628ed98 2094 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2095
b628ed98 2096 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2097
6b1a3aef 2098 err = sky2_rx_start(sky2);
e07b1aa8 2099 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2100
d1d08d12 2101 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2102 napi_enable(&hw->napi);
2103
1b537565
SH		 2104 if (err)
2105 dev_close(dev);
2106 else {
b628ed98 2107 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2108
1b537565
SH		 2109 netif_wake_queue(dev);
2110 }
2111
cd28ab6a
SH		 2112 return err;
2113}
2114
14d0263f
SH		 2115/* For small just reuse existing skb for next receive */
2116static struct sk_buff *receive_copy(struct sky2_port *sky2,
2117 const struct rx_ring_info *re,
2118 unsigned length)
2119{
2120 struct sk_buff *skb;
2121
2122 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2123 if (likely(skb)) {
2124 skb_reserve(skb, 2);
2125 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2126 length, PCI_DMA_FROMDEVICE);
d626f62b 2127 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2128 skb->ip_summed = re->skb->ip_summed;
2129 skb->csum = re->skb->csum;
2130 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2131 length, PCI_DMA_FROMDEVICE);
2132 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2133 skb_put(skb, length);
14d0263f
SH		 2134 }
2135 return skb;
2136}
2137
2138/* Adjust length of skb with fragments to match received data */
2139static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2140 unsigned int length)
2141{
2142 int i, num_frags;
2143 unsigned int size;
2144
2145 /* put header into skb */
2146 size = min(length, hdr_space);
2147 skb->tail += size;
2148 skb->len += size;
2149 length -= size;
2150
2151 num_frags = skb_shinfo(skb)->nr_frags;
2152 for (i = 0; i < num_frags; i++) {
2153 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2154
2155 if (length == 0) {
2156 /* don't need this page */
2157 __free_page(frag->page);
2158 --skb_shinfo(skb)->nr_frags;
2159 } else {
2160 size = min(length, (unsigned) PAGE_SIZE);
2161
2162 frag->size = size;
2163 skb->data_len += size;
2164 skb->truesize += size;
2165 skb->len += size;
2166 length -= size;
2167 }
2168 }
2169}
2170
2171/* Normal packet - take skb from ring element and put in a new one */
2172static struct sk_buff *receive_new(struct sky2_port *sky2,
2173 struct rx_ring_info *re,
2174 unsigned int length)
2175{
2176 struct sk_buff *skb, *nskb;
2177 unsigned hdr_space = sky2->rx_data_size;
2178
14d0263f
SH		 2179 /* Don't be tricky about reusing pages (yet) */
2180 nskb = sky2_rx_alloc(sky2);
2181 if (unlikely(!nskb))
2182 return NULL;
2183
2184 skb = re->skb;
2185 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2186
2187 prefetch(skb->data);
2188 re->skb = nskb;
2189 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2190
2191 if (skb_shinfo(skb)->nr_frags)
2192 skb_put_frags(skb, hdr_space, length);
2193 else
489b10c1 2194 skb_put(skb, length);
14d0263f
SH		 2195 return skb;
2196}
2197
cd28ab6a
SH		 2198/*
2199 * Receive one packet.
d571b694 2200 * For larger packets, get new buffer.
cd28ab6a 2201 */
497d7c86 2202static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2203 u16 length, u32 status)
2204{
497d7c86 2205 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2206 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2207 struct sk_buff *skb = NULL;
d6532232
SH		 2208 u16 count = (status & GMR_FS_LEN) >> 16;
2209
2210#ifdef SKY2_VLAN_TAG_USED
2211 /* Account for vlan tag */
2212 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2213 count -= VLAN_HLEN;
2214#endif
cd28ab6a
SH		 2215
2216 if (unlikely(netif_msg_rx_status(sky2)))
2217 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2218 dev->name, sky2->rx_next, status, length);
cd28ab6a 2219
793b883e 2220 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2221 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2222
3b12e014
SH		 2223 /* This chip has hardware problems that generates bogus status.
2224 * So do only marginal checking and expect higher level protocols
2225 * to handle crap frames.
2226 */
2227 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2228 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2229 length != count)
2230 goto okay;
2231
42eeea01 2232 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2233 goto error;
2234
42eeea01 2235 if (!(status & GMR_FS_RX_OK))
2236 goto resubmit;
2237
d6532232
SH		 2238 /* if length reported by DMA does not match PHY, packet was truncated */
2239 if (length != count)
3b12e014 2240 goto len_error;
71749531 2241
3b12e014 2242okay:
14d0263f
SH		 2243 if (length < copybreak)
2244 skb = receive_copy(sky2, re, length);
2245 else
2246 skb = receive_new(sky2, re, length);
793b883e 2247resubmit:
14d0263f 2248 sky2_rx_submit(sky2, re);
79e57d32 2249
cd28ab6a
SH		 2250 return skb;
2251
3b12e014 2252len_error:
71749531
SH		 2253 /* Truncation of overlength packets
2254 causes PHY length to not match MAC length */
7138a0f5 2255 ++dev->stats.rx_length_errors;
d6532232 2256 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2257 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2258 dev->name, status, length);
d6532232 2259 goto resubmit;
71749531 2260
cd28ab6a 2261error:
7138a0f5 2262 ++dev->stats.rx_errors;
b6d77734 2263 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2264 dev->stats.rx_over_errors++;
b6d77734
SH		 2265 goto resubmit;
2266 }
6e15b712 2267
3be92a70 2268 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2269 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2270 dev->name, status, length);
793b883e
SH		 2271
2272 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2273 dev->stats.rx_length_errors++;
cd28ab6a 2274 if (status & GMR_FS_FRAGMENT)
7138a0f5 2275 dev->stats.rx_frame_errors++;
cd28ab6a 2276 if (status & GMR_FS_CRC_ERR)
7138a0f5 2277 dev->stats.rx_crc_errors++;
79e57d32 2278
793b883e 2279 goto resubmit;
cd28ab6a
SH		 2280}
2281
e07b1aa8
SH		 2282/* Transmit complete */
2283static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2284{
e07b1aa8 2285 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2286
e07b1aa8 2287 if (netif_running(dev)) {
2bb8c262 2288 netif_tx_lock(dev);
e07b1aa8 2289 sky2_tx_complete(sky2, last);
2bb8c262 2290 netif_tx_unlock(dev);
2224795d 2291 }
cd28ab6a
SH		 2292}
2293
e07b1aa8 2294/* Process status response ring */
26691830 2295static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2296{
e07b1aa8 2297 int work_done = 0;
55c9dd35 2298 unsigned rx[2] = { 0, 0 };
a8fd6266 2299
af2a58ac 2300 rmb();
26691830 2301 do {
55c9dd35 2302 struct sky2_port *sky2;
13210ce5 2303 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2304 unsigned port;
13210ce5 2305 struct net_device *dev;
cd28ab6a 2306 struct sk_buff *skb;
cd28ab6a
SH		 2307 u32 status;
2308 u16 length;
ab5adecb
SH		 2309 u8 opcode = le->opcode;
2310
2311 if (!(opcode & HW_OWNER))
2312 break;
cd28ab6a 2313
cb5d9547 2314 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2315
ab5adecb 2316 port = le->css & CSS_LINK_BIT;
69161611 2317 dev = hw->dev[port];
13210ce5 2318 sky2 = netdev_priv(dev);
f65b138c
SH		 2319 length = le16_to_cpu(le->length);
2320 status = le32_to_cpu(le->status);
cd28ab6a 2321
ab5adecb
SH		 2322 le->opcode = 0;
2323 switch (opcode & ~HW_OWNER) {
cd28ab6a 2324 case OP_RXSTAT:
55c9dd35 2325 ++rx[port];
497d7c86 2326 skb = sky2_receive(dev, length, status);
3225b919 2327 if (unlikely(!skb)) {
7138a0f5 2328 dev->stats.rx_dropped++;
55c9dd35 2329 break;
3225b919 2330 }
13210ce5 2331
69161611 2332 /* This chip reports checksum status differently */
05745c4a 2333 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2334 if (sky2->rx_csum &&
2335 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2336 (le->css & CSS_TCPUDPCSOK))
2337 skb->ip_summed = CHECKSUM_UNNECESSARY;
2338 else
2339 skb->ip_summed = CHECKSUM_NONE;
2340 }
2341
13210ce5 2342 skb->protocol = eth_type_trans(skb, dev);
7138a0f5
SH		 2343 dev->stats.rx_packets++;
2344 dev->stats.rx_bytes += skb->len;
13210ce5 2345 dev->last_rx = jiffies;
2346
d1f13708 2347#ifdef SKY2_VLAN_TAG_USED
2348 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2349 vlan_hwaccel_receive_skb(skb,
2350 sky2->vlgrp,
2351 be16_to_cpu(sky2->rx_tag));
2352 } else
2353#endif
cd28ab6a 2354 netif_receive_skb(skb);
13210ce5 2355
22e11703 2356 /* Stop after net poll weight */
13210ce5 2357 if (++work_done >= to_do)
2358 goto exit_loop;
cd28ab6a
SH		 2359 break;
2360
d1f13708 2361#ifdef SKY2_VLAN_TAG_USED
2362 case OP_RXVLAN:
2363 sky2->rx_tag = length;
2364 break;
2365
2366 case OP_RXCHKSVLAN:
2367 sky2->rx_tag = length;
2368 /* fall through */
2369#endif
cd28ab6a 2370 case OP_RXCHKS:
87418307
SH		 2371 if (!sky2->rx_csum)
2372 break;
2373
05745c4a
SH		 2374 /* If this happens then driver assuming wrong format */
2375 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2376 if (net_ratelimit())
2377 printk(KERN_NOTICE "%s: unexpected"
2378 " checksum status\n",
2379 dev->name);
69161611 2380 break;
05745c4a 2381 }
69161611 2382
87418307
SH		 2383 /* Both checksum counters are programmed to start at
2384 * the same offset, so unless there is a problem they
2385 * should match. This failure is an early indication that
2386 * hardware receive checksumming won't work.
2387 */
2388 if (likely(status >> 16 == (status & 0xffff))) {
2389 skb = sky2->rx_ring[sky2->rx_next].skb;
2390 skb->ip_summed = CHECKSUM_COMPLETE;
2391 skb->csum = status & 0xffff;
2392 } else {
2393 printk(KERN_NOTICE PFX "%s: hardware receive "
2394 "checksum problem (status = %#x)\n",
2395 dev->name, status);
2396 sky2->rx_csum = 0;
2397 sky2_write32(sky2->hw,
69161611 2398 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2399 BMU_DIS_RX_CHKSUM);
2400 }
cd28ab6a
SH		 2401 break;
2402
2403 case OP_TXINDEXLE:
13b97b74 2404 /* TX index reports status for both ports */
f55925d7
SH		 2405 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2406 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2407 if (hw->dev[1])
2408 sky2_tx_done(hw->dev[1],
2409 ((status >> 24) & 0xff)
2410 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2411 break;
2412
cd28ab6a
SH		 2413 default:
2414 if (net_ratelimit())
793b883e 2415 printk(KERN_WARNING PFX
ab5adecb 2416 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2417 }
26691830 2418 } while (hw->st_idx != idx);
cd28ab6a 2419
fe2a24df
SH		 2420 /* Fully processed status ring so clear irq */
2421 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2422
13210ce5 2423exit_loop:
55c9dd35
SH		 2424 if (rx[0])
2425 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2426
55c9dd35
SH		 2427 if (rx[1])
2428 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2429
e07b1aa8 2430 return work_done;
cd28ab6a
SH		 2431}
2432
2433static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2434{
2435 struct net_device *dev = hw->dev[port];
2436
3be92a70
SH		 2437 if (net_ratelimit())
2438 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2439 dev->name, status);
cd28ab6a
SH		 2440
2441 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2442 if (net_ratelimit())
2443 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2444 dev->name);
cd28ab6a
SH		 2445 /* Clear IRQ */
2446 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2447 }
2448
2449 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2450 if (net_ratelimit())
2451 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2452 dev->name);
cd28ab6a
SH		 2453
2454 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2455 }
2456
2457 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2458 if (net_ratelimit())
2459 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2460 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2461 }
2462
2463 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2464 if (net_ratelimit())
2465 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2466 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2467 }
2468
2469 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2470 if (net_ratelimit())
2471 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2472 dev->name);
cd28ab6a
SH		 2473 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2474 }
2475}
2476
2477static void sky2_hw_intr(struct sky2_hw *hw)
2478{
555382cb 2479 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2480 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2481 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2482
2483 status &= hwmsk;
cd28ab6a 2484
793b883e 2485 if (status & Y2_IS_TIST_OV)
cd28ab6a 2486 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2487
2488 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2489 u16 pci_err;
2490
82637e80 2491 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2492 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2493 if (net_ratelimit())
555382cb 2494 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2495 pci_err);
cd28ab6a 2496
b32f40c4 2497 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2498 pci_err | PCI_STATUS_ERROR_BITS);
82637e80 2499 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2500 }
2501
2502 if (status & Y2_IS_PCI_EXP) {
d571b694 2503 /* PCI-Express uncorrectable Error occurred */
555382cb 2504 u32 err;
cd28ab6a 2505
82637e80 2506 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2507 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2508 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2509 0xfffffffful);
3be92a70 2510 if (net_ratelimit())
555382cb 2511 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2512
7782c8c4 2513 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
82637e80 2514 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2515 }
2516
2517 if (status & Y2_HWE_L1_MASK)
2518 sky2_hw_error(hw, 0, status);
2519 status >>= 8;
2520 if (status & Y2_HWE_L1_MASK)
2521 sky2_hw_error(hw, 1, status);
2522}
2523
2524static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2525{
2526 struct net_device *dev = hw->dev[port];
2527 struct sky2_port *sky2 = netdev_priv(dev);
2528 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2529
2530 if (netif_msg_intr(sky2))
2531 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2532 dev->name, status);
2533
a3caeada
SH		 2534 if (status & GM_IS_RX_CO_OV)
2535 gma_read16(hw, port, GM_RX_IRQ_SRC);
2536
2537 if (status & GM_IS_TX_CO_OV)
2538 gma_read16(hw, port, GM_TX_IRQ_SRC);
2539
cd28ab6a 2540 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2541 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2542 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2543 }
2544
2545 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2546 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2547 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2548 }
cd28ab6a
SH		 2549}
2550
40b01727
SH		 2551/* This should never happen it is a bug. */
2552static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2553 u16 q, unsigned ring_size)
d257924e
SH		 2554{
2555 struct net_device *dev = hw->dev[port];
2556 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2557 unsigned idx;
2558 const u64 *le = (q == Q_R1 || q == Q_R2)
2559 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2560
40b01727
SH		 2561 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2562 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2563 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2564 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2565
40b01727 2566 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2567}
cd28ab6a 2568
75e80683
SH		 2569static int sky2_rx_hung(struct net_device *dev)
2570{
2571 struct sky2_port *sky2 = netdev_priv(dev);
2572 struct sky2_hw *hw = sky2->hw;
2573 unsigned port = sky2->port;
2574 unsigned rxq = rxqaddr[port];
2575 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2576 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2577 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2578 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2579
2580 /* If idle and MAC or PCI is stuck */
2581 if (sky2->check.last == dev->last_rx &&
2582 ((mac_rp == sky2->check.mac_rp &&
2583 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2584 /* Check if the PCI RX hang */
2585 (fifo_rp == sky2->check.fifo_rp &&
2586 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2587 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2588 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2589 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2590 return 1;
2591 } else {
2592 sky2->check.last = dev->last_rx;
2593 sky2->check.mac_rp = mac_rp;
2594 sky2->check.mac_lev = mac_lev;
2595 sky2->check.fifo_rp = fifo_rp;
2596 sky2->check.fifo_lev = fifo_lev;
2597 return 0;
2598 }
2599}
2600
32c2c300 2601static void sky2_watchdog(unsigned long arg)
d27ed387 2602{
01bd7564 2603 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2604
75e80683 2605 /* Check for lost IRQ once a second */
32c2c300 2606 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2607 napi_schedule(&hw->napi);
75e80683
SH		 2608 } else {
2609 int i, active = 0;
2610
2611 for (i = 0; i < hw->ports; i++) {
bea3348e 2612 struct net_device *dev = hw->dev[i];
75e80683
SH		 2613 if (!netif_running(dev))
2614 continue;
2615 ++active;
2616
2617 /* For chips with Rx FIFO, check if stuck */
39dbd958 2618 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2619 sky2_rx_hung(dev)) {
2620 pr_info(PFX "%s: receiver hang detected\n",
2621 dev->name);
2622 schedule_work(&hw->restart_work);
2623 return;
2624 }
2625 }
2626
2627 if (active == 0)
2628 return;
32c2c300 2629 }
01bd7564 2630
75e80683 2631 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2632}
2633
40b01727
SH		 2634/* Hardware/software error handling */
2635static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2636{
40b01727
SH		 2637 if (net_ratelimit())
2638 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2639
1e5f1283
SH		 2640 if (status & Y2_IS_HW_ERR)
2641 sky2_hw_intr(hw);
d257924e 2642
1e5f1283
SH		 2643 if (status & Y2_IS_IRQ_MAC1)
2644 sky2_mac_intr(hw, 0);
cd28ab6a 2645
1e5f1283
SH		 2646 if (status & Y2_IS_IRQ_MAC2)
2647 sky2_mac_intr(hw, 1);
cd28ab6a 2648
1e5f1283 2649 if (status & Y2_IS_CHK_RX1)
40b01727 2650 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2651
1e5f1283 2652 if (status & Y2_IS_CHK_RX2)
40b01727 2653 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2654
1e5f1283 2655 if (status & Y2_IS_CHK_TXA1)
40b01727 2656 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2657
1e5f1283 2658 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2659 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2660}
2661
bea3348e 2662static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2663{
bea3348e 2664 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2665 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2666 int work_done = 0;
26691830 2667 u16 idx;
40b01727
SH		 2668
2669 if (unlikely(status & Y2_IS_ERROR))
2670 sky2_err_intr(hw, status);
2671
2672 if (status & Y2_IS_IRQ_PHY1)
2673 sky2_phy_intr(hw, 0);
2674
2675 if (status & Y2_IS_IRQ_PHY2)
2676 sky2_phy_intr(hw, 1);
cd28ab6a 2677
26691830
SH		 2678 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2679 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2680
2681 if (work_done >= work_limit)
26691830
SH		 2682 goto done;
2683 }
6f535763 2684
26691830
SH		 2685 /* Bug/Errata workaround?
2686 * Need to kick the TX irq moderation timer.
2687 */
2688 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2689 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2690 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2691 }
26691830
SH		 2692 napi_complete(napi);
2693 sky2_read32(hw, B0_Y2_SP_LISR);
2694done:
6f535763 2695
bea3348e 2696 return work_done;
e07b1aa8
SH		 2697}
2698
7d12e780 2699static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2700{
2701 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2702 u32 status;
2703
2704 /* Reading this mask interrupts as side effect */
2705 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2706 if (status == 0 || status == ~0)
2707 return IRQ_NONE;
793b883e 2708
e07b1aa8 2709 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2710
2711 napi_schedule(&hw->napi);
793b883e 2712
cd28ab6a
SH		 2713 return IRQ_HANDLED;
2714}
2715
2716#ifdef CONFIG_NET_POLL_CONTROLLER
2717static void sky2_netpoll(struct net_device *dev)
2718{
2719 struct sky2_port *sky2 = netdev_priv(dev);
2720
bea3348e 2721 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2722}
2723#endif
2724
2725/* Chip internal frequency for clock calculations */
05745c4a 2726static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2727{
793b883e 2728 switch (hw->chip_id) {
cd28ab6a 2729 case CHIP_ID_YUKON_EC:
5a5b1ea0 2730 case CHIP_ID_YUKON_EC_U:
93745494 2731 case CHIP_ID_YUKON_EX:
ed4d4161 2732 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2733 case CHIP_ID_YUKON_UL_2:
05745c4a
SH		 2734 return 125;
2735
cd28ab6a 2736 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2737 return 100;
2738
2739 case CHIP_ID_YUKON_FE_P:
2740 return 50;
2741
2742 case CHIP_ID_YUKON_XL:
2743 return 156;
2744
2745 default:
2746 BUG();
cd28ab6a
SH		 2747 }
2748}
2749
fb17358f 2750static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2751{
fb17358f 2752 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2753}
2754
fb17358f 2755static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2756{
fb17358f 2757 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2758}
2759
fb17358f 2760
e3173832 2761static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2762{
b89165f2 2763 u8 t8;
cd28ab6a 2764
167f53d0 2765 /* Enable all clocks and check for bad PCI access */
b32f40c4 2766 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2767
cd28ab6a 2768 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2769
cd28ab6a 2770 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2771 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2772
2773 switch(hw->chip_id) {
2774 case CHIP_ID_YUKON_XL:
39dbd958 2775 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2776 break;
2777
2778 case CHIP_ID_YUKON_EC_U:
2779 hw->flags = SKY2_HW_GIGABIT
2780 | SKY2_HW_NEWER_PHY
2781 | SKY2_HW_ADV_POWER_CTL;
2782 break;
2783
2784 case CHIP_ID_YUKON_EX:
2785 hw->flags = SKY2_HW_GIGABIT
2786 | SKY2_HW_NEWER_PHY
2787 | SKY2_HW_NEW_LE
2788 | SKY2_HW_ADV_POWER_CTL;
2789
2790 /* New transmit checksum */
2791 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2792 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2793 break;
2794
2795 case CHIP_ID_YUKON_EC:
2796 /* This rev is really old, and requires untested workarounds */
2797 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2798 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2799 return -EOPNOTSUPP;
2800 }
39dbd958 2801 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2802 break;
2803
2804 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2805 break;
2806
05745c4a
SH		 2807 case CHIP_ID_YUKON_FE_P:
2808 hw->flags = SKY2_HW_NEWER_PHY
2809 | SKY2_HW_NEW_LE
2810 | SKY2_HW_AUTO_TX_SUM
2811 | SKY2_HW_ADV_POWER_CTL;
2812 break;
ed4d4161
SH		 2813
2814 case CHIP_ID_YUKON_SUPR:
2815 hw->flags = SKY2_HW_GIGABIT
2816 | SKY2_HW_NEWER_PHY
2817 | SKY2_HW_NEW_LE
2818 | SKY2_HW_AUTO_TX_SUM
2819 | SKY2_HW_ADV_POWER_CTL;
2820 break;
2821
0ce8b98d
SH		 2822 case CHIP_ID_YUKON_UL_2:
2823 hw->flags = SKY2_HW_GIGABIT
2824 | SKY2_HW_ADV_POWER_CTL;
2825 break;
2826
ea76e635 2827 default:
b02a9258
SH		 2828 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2829 hw->chip_id);
cd28ab6a
SH		 2830 return -EOPNOTSUPP;
2831 }
2832
ea76e635
SH		 2833 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2834 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2835 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2836
e3173832
SH		 2837 hw->ports = 1;
2838 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2839 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2840 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2841 ++hw->ports;
2842 }
2843
2844 return 0;
2845}
2846
2847static void sky2_reset(struct sky2_hw *hw)
2848{
555382cb 2849 struct pci_dev *pdev = hw->pdev;
e3173832 2850 u16 status;
555382cb
SH		 2851 int i, cap;
2852 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2853
cd28ab6a 2854 /* disable ASF */
4f44d8ba
SH		 2855 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2856 status = sky2_read16(hw, HCU_CCSR);
2857 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2858 HCU_CCSR_UC_STATE_MSK);
2859 sky2_write16(hw, HCU_CCSR, status);
2860 } else
2861 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2862 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2863
2864 /* do a SW reset */
2865 sky2_write8(hw, B0_CTST, CS_RST_SET);
2866 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2867
ac93a394
SH		 2868 /* allow writes to PCI config */
2869 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2870
cd28ab6a 2871 /* clear PCI errors, if any */
b32f40c4 2872 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2873 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2874 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2875
2876 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2877
555382cb
SH		 2878 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2879 if (cap) {
7782c8c4
SH		 2880 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2881 0xfffffffful);
555382cb
SH		 2882
2883 /* If error bit is stuck on ignore it */
2884 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2885 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2886 else
555382cb
SH		 2887 hwe_mask |= Y2_IS_PCI_EXP;
2888 }
cd28ab6a 2889
ae306cca 2890 sky2_power_on(hw);
82637e80 2891 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2892
2893 for (i = 0; i < hw->ports; i++) {
2894 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2895 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 2896
ed4d4161
SH		 2897 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2898 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 2899 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2900 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2901 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2902 }
2903
793b883e
SH		 2904 /* Clear I2C IRQ noise */
2905 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2906
2907 /* turn off hardware timer (unused) */
2908 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2909 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2910
cd28ab6a
SH		 2911 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2912
69634ee7
SH		 2913 /* Turn off descriptor polling */
2914 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2915
2916 /* Turn off receive timestamp */
2917 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2918 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2919
2920 /* enable the Tx Arbiters */
2921 for (i = 0; i < hw->ports; i++)
2922 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2923
2924 /* Initialize ram interface */
2925 for (i = 0; i < hw->ports; i++) {
793b883e 2926 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2927
2928 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2929 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2930 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2931 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2932 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2933 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2934 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2935 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2936 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2937 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2938 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2939 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2940 }
2941
555382cb 2942 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 2943
cd28ab6a 2944 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2945 sky2_gmac_reset(hw, i);
cd28ab6a 2946
cd28ab6a
SH		 2947 memset(hw->st_le, 0, STATUS_LE_BYTES);
2948 hw->st_idx = 0;
2949
2950 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2951 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2952
2953 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2954 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2955
2956 /* Set the list last index */
793b883e 2957 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2958
290d4de5
SH		 2959 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2960 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2961
290d4de5
SH		 2962 /* set Status-FIFO ISR watermark */
2963 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2964 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2965 else
2966 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2967
290d4de5 2968 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2969 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2970 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2971
793b883e 2972 /* enable status unit */
cd28ab6a
SH		 2973 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2974
2975 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2976 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2977 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2978}
2979
81906791
SH		 2980static void sky2_restart(struct work_struct *work)
2981{
2982 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2983 struct net_device *dev;
2984 int i, err;
2985
81906791 2986 rtnl_lock();
81906791
SH		 2987 for (i = 0; i < hw->ports; i++) {
2988 dev = hw->dev[i];
2989 if (netif_running(dev))
2990 sky2_down(dev);
2991 }
2992
8cfcbe99
SH		 2993 napi_disable(&hw->napi);
2994 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 2995 sky2_reset(hw);
2996 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 2997 napi_enable(&hw->napi);
81906791
SH		 2998
2999 for (i = 0; i < hw->ports; i++) {
3000 dev = hw->dev[i];
3001 if (netif_running(dev)) {
3002 err = sky2_up(dev);
3003 if (err) {
3004 printk(KERN_INFO PFX "%s: could not restart %d\n",
3005 dev->name, err);
3006 dev_close(dev);
3007 }
3008 }
3009 }
3010
81906791
SH		 3011 rtnl_unlock();
3012}
3013
e3173832
SH		 3014static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3015{
3016 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3017}
3018
3019static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3020{
3021 const struct sky2_port *sky2 = netdev_priv(dev);
3022
3023 wol->supported = sky2_wol_supported(sky2->hw);
3024 wol->wolopts = sky2->wol;
3025}
3026
3027static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3028{
3029 struct sky2_port *sky2 = netdev_priv(dev);
3030 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3031
e3173832
SH		 3032 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
3033 return -EOPNOTSUPP;
3034
3035 sky2->wol = wol->wolopts;
3036
05745c4a
SH		 3037 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3038 hw->chip_id == CHIP_ID_YUKON_EX ||
3039 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 3040 sky2_write32(hw, B0_CTST, sky2->wol
3041 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3042
3043 if (!netif_running(dev))
3044 sky2_wol_init(sky2);
cd28ab6a
SH		 3045 return 0;
3046}
3047
28bd181a 3048static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3049{
b89165f2
SH		 3050 if (sky2_is_copper(hw)) {
3051 u32 modes = SUPPORTED_10baseT_Half
3052 | SUPPORTED_10baseT_Full
3053 | SUPPORTED_100baseT_Half
3054 | SUPPORTED_100baseT_Full
3055 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3056
ea76e635 3057 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3058 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3059 | SUPPORTED_1000baseT_Full;
3060 return modes;
cd28ab6a 3061 } else
b89165f2
SH		 3062 return SUPPORTED_1000baseT_Half
3063 | SUPPORTED_1000baseT_Full
3064 | SUPPORTED_Autoneg
3065 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3066}
3067
793b883e 3068static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3069{
3070 struct sky2_port *sky2 = netdev_priv(dev);
3071 struct sky2_hw *hw = sky2->hw;
3072
3073 ecmd->transceiver = XCVR_INTERNAL;
3074 ecmd->supported = sky2_supported_modes(hw);
3075 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3076 if (sky2_is_copper(hw)) {
cd28ab6a 3077 ecmd->port = PORT_TP;
b89165f2
SH		 3078 ecmd->speed = sky2->speed;
3079 } else {
3080 ecmd->speed = SPEED_1000;
cd28ab6a 3081 ecmd->port = PORT_FIBRE;
b89165f2 3082 }
cd28ab6a
SH		 3083
3084 ecmd->advertising = sky2->advertising;
3085 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3086 ecmd->duplex = sky2->duplex;
3087 return 0;
3088}
3089
3090static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3091{
3092 struct sky2_port *sky2 = netdev_priv(dev);
3093 const struct sky2_hw *hw = sky2->hw;
3094 u32 supported = sky2_supported_modes(hw);
3095
3096 if (ecmd->autoneg == AUTONEG_ENABLE) {
3097 ecmd->advertising = supported;
3098 sky2->duplex = -1;
3099 sky2->speed = -1;
3100 } else {
3101 u32 setting;
3102
793b883e 3103 switch (ecmd->speed) {
cd28ab6a
SH		 3104 case SPEED_1000:
3105 if (ecmd->duplex == DUPLEX_FULL)
3106 setting = SUPPORTED_1000baseT_Full;
3107 else if (ecmd->duplex == DUPLEX_HALF)
3108 setting = SUPPORTED_1000baseT_Half;
3109 else
3110 return -EINVAL;
3111 break;
3112 case SPEED_100:
3113 if (ecmd->duplex == DUPLEX_FULL)
3114 setting = SUPPORTED_100baseT_Full;
3115 else if (ecmd->duplex == DUPLEX_HALF)
3116 setting = SUPPORTED_100baseT_Half;
3117 else
3118 return -EINVAL;
3119 break;
3120
3121 case SPEED_10:
3122 if (ecmd->duplex == DUPLEX_FULL)
3123 setting = SUPPORTED_10baseT_Full;
3124 else if (ecmd->duplex == DUPLEX_HALF)
3125 setting = SUPPORTED_10baseT_Half;
3126 else
3127 return -EINVAL;
3128 break;
3129 default:
3130 return -EINVAL;
3131 }
3132
3133 if ((setting & supported) == 0)
3134 return -EINVAL;
3135
3136 sky2->speed = ecmd->speed;
3137 sky2->duplex = ecmd->duplex;
3138 }
3139
3140 sky2->autoneg = ecmd->autoneg;
3141 sky2->advertising = ecmd->advertising;
3142
d1b139c0 3143 if (netif_running(dev)) {
1b537565 3144 sky2_phy_reinit(sky2);
d1b139c0
SH		 3145 sky2_set_multicast(dev);
3146 }
cd28ab6a
SH		 3147
3148 return 0;
3149}
3150
3151static void sky2_get_drvinfo(struct net_device *dev,
3152 struct ethtool_drvinfo *info)
3153{
3154 struct sky2_port *sky2 = netdev_priv(dev);
3155
3156 strcpy(info->driver, DRV_NAME);
3157 strcpy(info->version, DRV_VERSION);
3158 strcpy(info->fw_version, "N/A");
3159 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3160}
3161
3162static const struct sky2_stat {
793b883e
SH		 3163 char name[ETH_GSTRING_LEN];
3164 u16 offset;
cd28ab6a
SH		 3165} sky2_stats[] = {
3166 { "tx_bytes", GM_TXO_OK_HI },
3167 { "rx_bytes", GM_RXO_OK_HI },
3168 { "tx_broadcast", GM_TXF_BC_OK },
3169 { "rx_broadcast", GM_RXF_BC_OK },
3170 { "tx_multicast", GM_TXF_MC_OK },
3171 { "rx_multicast", GM_RXF_MC_OK },
3172 { "tx_unicast", GM_TXF_UC_OK },
3173 { "rx_unicast", GM_RXF_UC_OK },
3174 { "tx_mac_pause", GM_TXF_MPAUSE },
3175 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3176 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3177 { "late_collision",GM_TXF_LAT_COL },
3178 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3179 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3180 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3181
d2604540 3182 { "rx_short", GM_RXF_SHT },
cd28ab6a 3183 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3184 { "rx_64_byte_packets", GM_RXF_64B },
3185 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3186 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3187 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3188 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3189 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3190 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3191 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3192 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3193 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3194 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3195
3196 { "tx_64_byte_packets", GM_TXF_64B },
3197 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3198 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3199 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3200 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3201 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3202 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3203 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3204};
3205
cd28ab6a
SH		 3206static u32 sky2_get_rx_csum(struct net_device *dev)
3207{
3208 struct sky2_port *sky2 = netdev_priv(dev);
3209
3210 return sky2->rx_csum;
3211}
3212
3213static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3214{
3215 struct sky2_port *sky2 = netdev_priv(dev);
3216
3217 sky2->rx_csum = data;
793b883e 3218
cd28ab6a
SH		 3219 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3220 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3221
3222 return 0;
3223}
3224
3225static u32 sky2_get_msglevel(struct net_device *netdev)
3226{
3227 struct sky2_port *sky2 = netdev_priv(netdev);
3228 return sky2->msg_enable;
3229}
3230
9a7ae0a9
SH		 3231static int sky2_nway_reset(struct net_device *dev)
3232{
3233 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3234
16ad91e1 3235 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3236 return -EINVAL;
3237
1b537565 3238 sky2_phy_reinit(sky2);
d1b139c0 3239 sky2_set_multicast(dev);
9a7ae0a9
SH		 3240
3241 return 0;
3242}
3243
793b883e 3244static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3245{
3246 struct sky2_hw *hw = sky2->hw;
3247 unsigned port = sky2->port;
3248 int i;
3249
3250 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3251 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3252 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3253 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3254
793b883e 3255 for (i = 2; i < count; i++)
cd28ab6a
SH		 3256 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3257}
3258
cd28ab6a
SH		 3259static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3260{
3261 struct sky2_port *sky2 = netdev_priv(netdev);
3262 sky2->msg_enable = value;
3263}
3264
b9f2c044 3265static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3266{
b9f2c044
JG		 3267 switch (sset) {
3268 case ETH_SS_STATS:
3269 return ARRAY_SIZE(sky2_stats);
3270 default:
3271 return -EOPNOTSUPP;
3272 }
cd28ab6a
SH		 3273}
3274
3275static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3276 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3277{
3278 struct sky2_port *sky2 = netdev_priv(dev);
3279
793b883e 3280 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3281}
3282
793b883e 3283static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3284{
3285 int i;
3286
3287 switch (stringset) {
3288 case ETH_SS_STATS:
3289 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3290 memcpy(data + i * ETH_GSTRING_LEN,
3291 sky2_stats[i].name, ETH_GSTRING_LEN);
3292 break;
3293 }
3294}
3295
cd28ab6a
SH		 3296static int sky2_set_mac_address(struct net_device *dev, void *p)
3297{
3298 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3299 struct sky2_hw *hw = sky2->hw;
3300 unsigned port = sky2->port;
3301 const struct sockaddr *addr = p;
cd28ab6a
SH		 3302
3303 if (!is_valid_ether_addr(addr->sa_data))
3304 return -EADDRNOTAVAIL;
3305
cd28ab6a 3306 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3307 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3308 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3309 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3310 dev->dev_addr, ETH_ALEN);
1b537565 3311
a8ab1ec0
SH		 3312 /* virtual address for data */
3313 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3314
3315 /* physical address: used for pause frames */
3316 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3317
3318 return 0;
cd28ab6a
SH		 3319}
3320
a052b52f
SH		 3321static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3322{
3323 u32 bit;
3324
3325 bit = ether_crc(ETH_ALEN, addr) & 63;
3326 filter[bit >> 3] |= 1 << (bit & 7);
3327}
3328
cd28ab6a
SH		 3329static void sky2_set_multicast(struct net_device *dev)
3330{
3331 struct sky2_port *sky2 = netdev_priv(dev);
3332 struct sky2_hw *hw = sky2->hw;
3333 unsigned port = sky2->port;
3334 struct dev_mc_list *list = dev->mc_list;
3335 u16 reg;
3336 u8 filter[8];
a052b52f
SH		 3337 int rx_pause;
3338 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3339
a052b52f 3340 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3341 memset(filter, 0, sizeof(filter));
3342
3343 reg = gma_read16(hw, port, GM_RX_CTRL);
3344 reg |= GM_RXCR_UCF_ENA;
3345
d571b694 3346 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3347 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3348 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3349 memset(filter, 0xff, sizeof(filter));
a052b52f 3350 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3351 reg &= ~GM_RXCR_MCF_ENA;
3352 else {
3353 int i;
3354 reg |= GM_RXCR_MCF_ENA;
3355
a052b52f
SH		 3356 if (rx_pause)
3357 sky2_add_filter(filter, pause_mc_addr);
3358
3359 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3360 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3361 }
3362
cd28ab6a 3363 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3364 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3365 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3366 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3367 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3368 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3369 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3370 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3371
3372 gma_write16(hw, port, GM_RX_CTRL, reg);
3373}
3374
3375/* Can have one global because blinking is controlled by
3376 * ethtool and that is always under RTNL mutex
3377 */
a84d0a3d 3378static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3379{
a84d0a3d
SH		 3380 struct sky2_hw *hw = sky2->hw;
3381 unsigned port = sky2->port;
793b883e 3382
a84d0a3d
SH		 3383 spin_lock_bh(&sky2->phy_lock);
3384 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3385 hw->chip_id == CHIP_ID_YUKON_EX ||
3386 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3387 u16 pg;
793b883e
SH		 3388 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3389 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3390
a84d0a3d
SH		 3391 switch (mode) {
3392 case MO_LED_OFF:
3393 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3394 PHY_M_LEDC_LOS_CTRL(8) |
3395 PHY_M_LEDC_INIT_CTRL(8) |
3396 PHY_M_LEDC_STA1_CTRL(8) |
3397 PHY_M_LEDC_STA0_CTRL(8));
3398 break;
3399 case MO_LED_ON:
3400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3401 PHY_M_LEDC_LOS_CTRL(9) |
3402 PHY_M_LEDC_INIT_CTRL(9) |
3403 PHY_M_LEDC_STA1_CTRL(9) |
3404 PHY_M_LEDC_STA0_CTRL(9));
3405 break;
3406 case MO_LED_BLINK:
3407 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3408 PHY_M_LEDC_LOS_CTRL(0xa) |
3409 PHY_M_LEDC_INIT_CTRL(0xa) |
3410 PHY_M_LEDC_STA1_CTRL(0xa) |
3411 PHY_M_LEDC_STA0_CTRL(0xa));
3412 break;
3413 case MO_LED_NORM:
3414 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3415 PHY_M_LEDC_LOS_CTRL(1) |
3416 PHY_M_LEDC_INIT_CTRL(8) |
3417 PHY_M_LEDC_STA1_CTRL(7) |
3418 PHY_M_LEDC_STA0_CTRL(7));
3419 }
793b883e 3420
a84d0a3d
SH		 3421 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3422 } else
7d2e3cb7 3423 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3424 PHY_M_LED_MO_DUP(mode) |
3425 PHY_M_LED_MO_10(mode) |
3426 PHY_M_LED_MO_100(mode) |
3427 PHY_M_LED_MO_1000(mode) |
3428 PHY_M_LED_MO_RX(mode) |
3429 PHY_M_LED_MO_TX(mode));
3430
3431 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3432}
3433
3434/* blink LED's for finding board */
3435static int sky2_phys_id(struct net_device *dev, u32 data)
3436{
3437 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3438 unsigned int i;
cd28ab6a 3439
a84d0a3d
SH		 3440 if (data == 0)
3441 data = UINT_MAX;
cd28ab6a 3442
a84d0a3d
SH		 3443 for (i = 0; i < data; i++) {
3444 sky2_led(sky2, MO_LED_ON);
3445 if (msleep_interruptible(500))
3446 break;
3447 sky2_led(sky2, MO_LED_OFF);
3448 if (msleep_interruptible(500))
3449 break;
793b883e 3450 }
a84d0a3d 3451 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3452
3453 return 0;
3454}
3455
3456static void sky2_get_pauseparam(struct net_device *dev,
3457 struct ethtool_pauseparam *ecmd)
3458{
3459 struct sky2_port *sky2 = netdev_priv(dev);
3460
16ad91e1
SH		 3461 switch (sky2->flow_mode) {
3462 case FC_NONE:
3463 ecmd->tx_pause = ecmd->rx_pause = 0;
3464 break;
3465 case FC_TX:
3466 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3467 break;
3468 case FC_RX:
3469 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3470 break;
3471 case FC_BOTH:
3472 ecmd->tx_pause = ecmd->rx_pause = 1;
3473 }
3474
cd28ab6a
SH		 3475 ecmd->autoneg = sky2->autoneg;
3476}
3477
3478static int sky2_set_pauseparam(struct net_device *dev,
3479 struct ethtool_pauseparam *ecmd)
3480{
3481 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3482
3483 sky2->autoneg = ecmd->autoneg;
16ad91e1 3484 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3485
16ad91e1
SH		 3486 if (netif_running(dev))
3487 sky2_phy_reinit(sky2);
cd28ab6a 3488
2eaba1a2 3489 return 0;
cd28ab6a
SH		 3490}
3491
fb17358f
SH		 3492static int sky2_get_coalesce(struct net_device *dev,
3493 struct ethtool_coalesce *ecmd)
3494{
3495 struct sky2_port *sky2 = netdev_priv(dev);
3496 struct sky2_hw *hw = sky2->hw;
3497
3498 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3499 ecmd->tx_coalesce_usecs = 0;
3500 else {
3501 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3502 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3503 }
3504 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3505
3506 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3507 ecmd->rx_coalesce_usecs = 0;
3508 else {
3509 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3510 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3511 }
3512 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3513
3514 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3515 ecmd->rx_coalesce_usecs_irq = 0;
3516 else {
3517 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3518 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3519 }
3520
3521 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3522
3523 return 0;
3524}
3525
3526/* Note: this affect both ports */
3527static int sky2_set_coalesce(struct net_device *dev,
3528 struct ethtool_coalesce *ecmd)
3529{
3530 struct sky2_port *sky2 = netdev_priv(dev);
3531 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3532 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3533
77b3d6a2
SH		 3534 if (ecmd->tx_coalesce_usecs > tmax ||
3535 ecmd->rx_coalesce_usecs > tmax ||
3536 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3537 return -EINVAL;
3538
ff81fbbe 3539 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3540 return -EINVAL;
ff81fbbe 3541 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3542 return -EINVAL;
ff81fbbe 3543 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3544 return -EINVAL;
3545
3546 if (ecmd->tx_coalesce_usecs == 0)
3547 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3548 else {
3549 sky2_write32(hw, STAT_TX_TIMER_INI,
3550 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3551 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3552 }
3553 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3554
3555 if (ecmd->rx_coalesce_usecs == 0)
3556 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3557 else {
3558 sky2_write32(hw, STAT_LEV_TIMER_INI,
3559 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3560 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3561 }
3562 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3563
3564 if (ecmd->rx_coalesce_usecs_irq == 0)
3565 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3566 else {
d28d4870 3567 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3568 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3569 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3570 }
3571 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3572 return 0;
3573}
3574
793b883e
SH		 3575static void sky2_get_ringparam(struct net_device *dev,
3576 struct ethtool_ringparam *ering)
3577{
3578 struct sky2_port *sky2 = netdev_priv(dev);
3579
3580 ering->rx_max_pending = RX_MAX_PENDING;
3581 ering->rx_mini_max_pending = 0;
3582 ering->rx_jumbo_max_pending = 0;
3583 ering->tx_max_pending = TX_RING_SIZE - 1;
3584
3585 ering->rx_pending = sky2->rx_pending;
3586 ering->rx_mini_pending = 0;
3587 ering->rx_jumbo_pending = 0;
3588 ering->tx_pending = sky2->tx_pending;
3589}
3590
3591static int sky2_set_ringparam(struct net_device *dev,
3592 struct ethtool_ringparam *ering)
3593{
3594 struct sky2_port *sky2 = netdev_priv(dev);
3595 int err = 0;
3596
3597 if (ering->rx_pending > RX_MAX_PENDING ||
3598 ering->rx_pending < 8 ||
3599 ering->tx_pending < MAX_SKB_TX_LE ||
3600 ering->tx_pending > TX_RING_SIZE - 1)
3601 return -EINVAL;
3602
3603 if (netif_running(dev))
3604 sky2_down(dev);
3605
3606 sky2->rx_pending = ering->rx_pending;
3607 sky2->tx_pending = ering->tx_pending;
3608
1b537565 3609 if (netif_running(dev)) {
793b883e 3610 err = sky2_up(dev);
1b537565
SH		 3611 if (err)
3612 dev_close(dev);
3613 }
793b883e
SH		 3614
3615 return err;
3616}
3617
793b883e
SH		 3618static int sky2_get_regs_len(struct net_device *dev)
3619{
6e4cbb34 3620 return 0x4000;
793b883e
SH		 3621}
3622
3623/*
3624 * Returns copy of control register region
3ead5db7 3625 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3626 */
3627static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3628 void *p)
3629{
3630 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3631 const void __iomem *io = sky2->hw->regs;
295b54c4 3632 unsigned int b;
793b883e
SH		 3633
3634 regs->version = 1;
793b883e 3635
295b54c4
SH		 3636 for (b = 0; b < 128; b++) {
3637 /* This complicated switch statement is to make sure and
3638 * only access regions that are unreserved.
3639 * Some blocks are only valid on dual port cards.
3640 * and block 3 has some special diagnostic registers that
3641 * are poison.
3642 */
3643 switch (b) {
3644 case 3:
3645 /* skip diagnostic ram region */
3646 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3647 break;
3ead5db7 3648
295b54c4
SH		 3649 /* dual port cards only */
3650 case 5: /* Tx Arbiter 2 */
3651 case 9: /* RX2 */
3652 case 14 ... 15: /* TX2 */
3653 case 17: case 19: /* Ram Buffer 2 */
3654 case 22 ... 23: /* Tx Ram Buffer 2 */
3655 case 25: /* Rx MAC Fifo 1 */
3656 case 27: /* Tx MAC Fifo 2 */
3657 case 31: /* GPHY 2 */
3658 case 40 ... 47: /* Pattern Ram 2 */
3659 case 52: case 54: /* TCP Segmentation 2 */
3660 case 112 ... 116: /* GMAC 2 */
3661 if (sky2->hw->ports == 1)
3662 goto reserved;
3663 /* fall through */
3664 case 0: /* Control */
3665 case 2: /* Mac address */
3666 case 4: /* Tx Arbiter 1 */
3667 case 7: /* PCI express reg */
3668 case 8: /* RX1 */
3669 case 12 ... 13: /* TX1 */
3670 case 16: case 18:/* Rx Ram Buffer 1 */
3671 case 20 ... 21: /* Tx Ram Buffer 1 */
3672 case 24: /* Rx MAC Fifo 1 */
3673 case 26: /* Tx MAC Fifo 1 */
3674 case 28 ... 29: /* Descriptor and status unit */
3675 case 30: /* GPHY 1*/
3676 case 32 ... 39: /* Pattern Ram 1 */
3677 case 48: case 50: /* TCP Segmentation 1 */
3678 case 56 ... 60: /* PCI space */
3679 case 80 ... 84: /* GMAC 1 */
3680 memcpy_fromio(p, io, 128);
3681 break;
3682 default:
3683reserved:
3684 memset(p, 0, 128);
3685 }
3ead5db7 3686
295b54c4
SH		 3687 p += 128;
3688 io += 128;
3689 }
793b883e 3690}
cd28ab6a 3691
b628ed98
SH		 3692/* In order to do Jumbo packets on these chips, need to turn off the
3693 * transmit store/forward. Therefore checksum offload won't work.
3694 */
3695static int no_tx_offload(struct net_device *dev)
3696{
3697 const struct sky2_port *sky2 = netdev_priv(dev);
3698 const struct sky2_hw *hw = sky2->hw;
3699
69161611 3700 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3701}
3702
3703static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3704{
3705 if (data && no_tx_offload(dev))
3706 return -EINVAL;
3707
3708 return ethtool_op_set_tx_csum(dev, data);
3709}
3710
3711
3712static int sky2_set_tso(struct net_device *dev, u32 data)
3713{
3714 if (data && no_tx_offload(dev))
3715 return -EINVAL;
3716
3717 return ethtool_op_set_tso(dev, data);
3718}
3719
f4331a6d
SH		 3720static int sky2_get_eeprom_len(struct net_device *dev)
3721{
3722 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3723 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3724 u16 reg2;
3725
b32f40c4 3726 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3727 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3728}
3729
b32f40c4 3730static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
f4331a6d 3731{
167f53d0 3732 u32 val;
f4331a6d 3733
b32f40c4 3734 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
167f53d0
SH		 3735
3736 do {
b32f40c4 3737 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0
SH		 3738 } while (!(offset & PCI_VPD_ADDR_F));
3739
b32f40c4 3740 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
167f53d0 3741 return val;
f4331a6d
SH		 3742}
3743
b32f40c4 3744static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
f4331a6d 3745{
b32f40c4
SH		 3746 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3747 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
f4331a6d 3748 do {
b32f40c4 3749 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0 3750 } while (offset & PCI_VPD_ADDR_F);
f4331a6d
SH		 3751}
3752
3753static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3754 u8 *data)
3755{
3756 struct sky2_port *sky2 = netdev_priv(dev);
3757 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3758 int length = eeprom->len;
3759 u16 offset = eeprom->offset;
3760
3761 if (!cap)
3762 return -EINVAL;
3763
3764 eeprom->magic = SKY2_EEPROM_MAGIC;
3765
3766 while (length > 0) {
b32f40c4 3767 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3768 int n = min_t(int, length, sizeof(val));
3769
3770 memcpy(data, &val, n);
3771 length -= n;
3772 data += n;
3773 offset += n;
3774 }
3775 return 0;
3776}
3777
3778static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3779 u8 *data)
3780{
3781 struct sky2_port *sky2 = netdev_priv(dev);
3782 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3783 int length = eeprom->len;
3784 u16 offset = eeprom->offset;
3785
3786 if (!cap)
3787 return -EINVAL;
3788
3789 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3790 return -EINVAL;
3791
3792 while (length > 0) {
3793 u32 val;
3794 int n = min_t(int, length, sizeof(val));
3795
3796 if (n < sizeof(val))
b32f40c4 3797 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3798 memcpy(&val, data, n);
3799
b32f40c4 3800 sky2_vpd_write(sky2->hw, cap, offset, val);
f4331a6d
SH		 3801
3802 length -= n;
3803 data += n;
3804 offset += n;
3805 }
3806 return 0;
3807}
3808
3809
7282d491 3810static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3811 .get_settings = sky2_get_settings,
3812 .set_settings = sky2_set_settings,
3813 .get_drvinfo = sky2_get_drvinfo,
3814 .get_wol = sky2_get_wol,
3815 .set_wol = sky2_set_wol,
3816 .get_msglevel = sky2_get_msglevel,
3817 .set_msglevel = sky2_set_msglevel,
3818 .nway_reset = sky2_nway_reset,
3819 .get_regs_len = sky2_get_regs_len,
3820 .get_regs = sky2_get_regs,
3821 .get_link = ethtool_op_get_link,
3822 .get_eeprom_len = sky2_get_eeprom_len,
3823 .get_eeprom = sky2_get_eeprom,
3824 .set_eeprom = sky2_set_eeprom,
f4331a6d 3825 .set_sg = ethtool_op_set_sg,
f4331a6d 3826 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3827 .set_tso = sky2_set_tso,
3828 .get_rx_csum = sky2_get_rx_csum,
3829 .set_rx_csum = sky2_set_rx_csum,
3830 .get_strings = sky2_get_strings,
3831 .get_coalesce = sky2_get_coalesce,
3832 .set_coalesce = sky2_set_coalesce,
3833 .get_ringparam = sky2_get_ringparam,
3834 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3835 .get_pauseparam = sky2_get_pauseparam,
3836 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3837 .phys_id = sky2_phys_id,
b9f2c044 3838 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3839 .get_ethtool_stats = sky2_get_ethtool_stats,
3840};
3841
3cf26753
SH		 3842#ifdef CONFIG_SKY2_DEBUG
3843
3844static struct dentry *sky2_debug;
3845
3846static int sky2_debug_show(struct seq_file *seq, void *v)
3847{
3848 struct net_device *dev = seq->private;
3849 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 3850 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 3851 unsigned port = sky2->port;
3852 unsigned idx, last;
3853 int sop;
3854
3855 if (!netif_running(dev))
3856 return -ENETDOWN;
3857
3858 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3859 sky2_read32(hw, B0_ISRC),
3860 sky2_read32(hw, B0_IMSK),
3861 sky2_read32(hw, B0_Y2_SP_ICR));
3862
bea3348e 3863 napi_disable(&hw->napi);
3cf26753
SH		 3864 last = sky2_read16(hw, STAT_PUT_IDX);
3865
3866 if (hw->st_idx == last)
3867 seq_puts(seq, "Status ring (empty)\n");
3868 else {
3869 seq_puts(seq, "Status ring\n");
3870 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3871 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3872 const struct sky2_status_le *le = hw->st_le + idx;
3873 seq_printf(seq, "[%d] %#x %d %#x\n",
3874 idx, le->opcode, le->length, le->status);
3875 }
3876 seq_puts(seq, "\n");
3877 }
3878
3879 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3880 sky2->tx_cons, sky2->tx_prod,
3881 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3882 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3883
3884 /* Dump contents of tx ring */
3885 sop = 1;
3886 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3887 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3888 const struct sky2_tx_le *le = sky2->tx_le + idx;
3889 u32 a = le32_to_cpu(le->addr);
3890
3891 if (sop)
3892 seq_printf(seq, "%u:", idx);
3893 sop = 0;
3894
3895 switch(le->opcode & ~HW_OWNER) {
3896 case OP_ADDR64:
3897 seq_printf(seq, " %#x:", a);
3898 break;
3899 case OP_LRGLEN:
3900 seq_printf(seq, " mtu=%d", a);
3901 break;
3902 case OP_VLAN:
3903 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3904 break;
3905 case OP_TCPLISW:
3906 seq_printf(seq, " csum=%#x", a);
3907 break;
3908 case OP_LARGESEND:
3909 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3910 break;
3911 case OP_PACKET:
3912 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3913 break;
3914 case OP_BUFFER:
3915 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3916 break;
3917 default:
3918 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3919 a, le16_to_cpu(le->length));
3920 }
3921
3922 if (le->ctrl & EOP) {
3923 seq_putc(seq, '\n');
3924 sop = 1;
3925 }
3926 }
3927
3928 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3929 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3930 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3931 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3932
d1d08d12 3933 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 3934 napi_enable(&hw->napi);
3cf26753
SH		 3935 return 0;
3936}
3937
3938static int sky2_debug_open(struct inode *inode, struct file *file)
3939{
3940 return single_open(file, sky2_debug_show, inode->i_private);
3941}
3942
3943static const struct file_operations sky2_debug_fops = {
3944 .owner = THIS_MODULE,
3945 .open = sky2_debug_open,
3946 .read = seq_read,
3947 .llseek = seq_lseek,
3948 .release = single_release,
3949};
3950
3951/*
3952 * Use network device events to create/remove/rename
3953 * debugfs file entries
3954 */
3955static int sky2_device_event(struct notifier_block *unused,
3956 unsigned long event, void *ptr)
3957{
3958 struct net_device *dev = ptr;
5b296bc9 3959 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 3960
5b296bc9
SH		 3961 if (dev->open != sky2_up || !sky2_debug)
3962 return NOTIFY_DONE;
3cf26753 3963
5b296bc9
SH		 3964 switch(event) {
3965 case NETDEV_CHANGENAME:
3966 if (sky2->debugfs) {
3967 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3968 sky2_debug, dev->name);
3969 }
3970 break;
3cf26753 3971
5b296bc9
SH		 3972 case NETDEV_GOING_DOWN:
3973 if (sky2->debugfs) {
3974 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3975 dev->name);
3976 debugfs_remove(sky2->debugfs);
3977 sky2->debugfs = NULL;
3cf26753 3978 }
5b296bc9
SH		 3979 break;
3980
3981 case NETDEV_UP:
3982 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3983 sky2_debug, dev,
3984 &sky2_debug_fops);
3985 if (IS_ERR(sky2->debugfs))
3986 sky2->debugfs = NULL;
3cf26753
SH		 3987 }
3988
3989 return NOTIFY_DONE;
3990}
3991
3992static struct notifier_block sky2_notifier = {
3993 .notifier_call = sky2_device_event,
3994};
3995
3996
3997static __init void sky2_debug_init(void)
3998{
3999 struct dentry *ent;
4000
4001 ent = debugfs_create_dir("sky2", NULL);
4002 if (!ent || IS_ERR(ent))
4003 return;
4004
4005 sky2_debug = ent;
4006 register_netdevice_notifier(&sky2_notifier);
4007}
4008
4009static __exit void sky2_debug_cleanup(void)
4010{
4011 if (sky2_debug) {
4012 unregister_netdevice_notifier(&sky2_notifier);
4013 debugfs_remove(sky2_debug);
4014 sky2_debug = NULL;
4015 }
4016}
4017
4018#else
4019#define sky2_debug_init()
4020#define sky2_debug_cleanup()
4021#endif
4022
4023
cd28ab6a
SH		 4024/* Initialize network device */
4025static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4026 unsigned port,
be63a21c 4027 int highmem, int wol)
cd28ab6a
SH		 4028{
4029 struct sky2_port *sky2;
4030 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4031
4032 if (!dev) {
898eb71c 4033 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4034 return NULL;
4035 }
4036
cd28ab6a 4037 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4038 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 4039 dev->open = sky2_up;
4040 dev->stop = sky2_down;
ef743d33 4041 dev->do_ioctl = sky2_ioctl;
cd28ab6a 4042 dev->hard_start_xmit = sky2_xmit_frame;
cd28ab6a
SH		 4043 dev->set_multicast_list = sky2_set_multicast;
4044 dev->set_mac_address = sky2_set_mac_address;
4045 dev->change_mtu = sky2_change_mtu;
4046 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4047 dev->tx_timeout = sky2_tx_timeout;
4048 dev->watchdog_timeo = TX_WATCHDOG;
cd28ab6a 4049#ifdef CONFIG_NET_POLL_CONTROLLER
a5e68c02
SH		 4050 if (port == 0)
4051 dev->poll_controller = sky2_netpoll;
cd28ab6a 4052#endif
cd28ab6a
SH		 4053
4054 sky2 = netdev_priv(dev);
4055 sky2->netdev = dev;
4056 sky2->hw = hw;
4057 sky2->msg_enable = netif_msg_init(debug, default_msg);
4058
cd28ab6a
SH		 4059 /* Auto speed and flow control */
4060 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 4061 sky2->flow_mode = FC_BOTH;
4062
cd28ab6a
SH		 4063 sky2->duplex = -1;
4064 sky2->speed = -1;
4065 sky2->advertising = sky2_supported_modes(hw);
8b31cfbc 4066 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
be63a21c 4067 sky2->wol = wol;
75d070c5 4068
e07b1aa8 4069 spin_lock_init(&sky2->phy_lock);
793b883e 4070 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 4071 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4072
4073 hw->dev[port] = dev;
4074
4075 sky2->port = port;
4076
4a50a876 4077 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4078 if (highmem)
4079 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4080
d1f13708 4081#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4082 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4083 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4084 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4085 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4086 dev->vlan_rx_register = sky2_vlan_rx_register;
4087 }
d1f13708 4088#endif
4089
cd28ab6a 4090 /* read the mac address */
793b883e 4091 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4092 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4093
cd28ab6a
SH		 4094 return dev;
4095}
4096
28bd181a 4097static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4098{
4099 const struct sky2_port *sky2 = netdev_priv(dev);
0795af57 4100 DECLARE_MAC_BUF(mac);
cd28ab6a
SH		 4101
4102 if (netif_msg_probe(sky2))
0795af57
JP		 4103 printk(KERN_INFO PFX "%s: addr %s\n",
4104 dev->name, print_mac(mac, dev->dev_addr));
cd28ab6a
SH		 4105}
4106
fb2690a9 4107/* Handle software interrupt used during MSI test */
7d12e780 4108static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4109{
4110 struct sky2_hw *hw = dev_id;
4111 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4112
4113 if (status == 0)
4114 return IRQ_NONE;
4115
4116 if (status & Y2_IS_IRQ_SW) {
ea76e635 4117 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4118 wake_up(&hw->msi_wait);
4119 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4120 }
4121 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4122
4123 return IRQ_HANDLED;
4124}
4125
4126/* Test interrupt path by forcing a a software IRQ */
4127static int __devinit sky2_test_msi(struct sky2_hw *hw)
4128{
4129 struct pci_dev *pdev = hw->pdev;
4130 int err;
4131
bb507fe1 4132 init_waitqueue_head (&hw->msi_wait);
4133
fb2690a9
SH		 4134 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4135
b0a20ded 4136 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4137 if (err) {
b02a9258 4138 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4139 return err;
4140 }
4141
fb2690a9 4142 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4143 sky2_read8(hw, B0_CTST);
fb2690a9 4144
ea76e635 4145 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4146
ea76e635 4147 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4148 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4149 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4150 "switching to INTx mode.\n");
fb2690a9
SH		 4151
4152 err = -EOPNOTSUPP;
4153 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4154 }
4155
4156 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4157 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4158
4159 free_irq(pdev->irq, hw);
4160
4161 return err;
4162}
4163
be63a21c
SH		 4164static int __devinit pci_wake_enabled(struct pci_dev *dev)
4165{
4166 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4167 u16 value;
4168
4169 if (!pm)
4170 return 0;
4171 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4172 return 0;
4173 return value & PCI_PM_CTRL_PME_ENABLE;
4174}
4175
c7127a34
SH		 4176/* This driver supports yukon2 chipset only */
4177static const char *sky2_name(u8 chipid, char *buf, int sz)
4178{
4179 const char *name[] = {
4180 "XL", /* 0xb3 */
4181 "EC Ultra", /* 0xb4 */
4182 "Extreme", /* 0xb5 */
4183 "EC", /* 0xb6 */
4184 "FE", /* 0xb7 */
4185 "FE+", /* 0xb8 */
4186 "Supreme", /* 0xb9 */
0ce8b98d 4187 "UL 2", /* 0xba */
c7127a34
SH		 4188 };
4189
0ce8b98d 4190 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
c7127a34
SH		 4191 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4192 else
4193 snprintf(buf, sz, "(chip %#x)", chipid);
4194 return buf;
4195}
4196
cd28ab6a
SH		 4197static int __devinit sky2_probe(struct pci_dev *pdev,
4198 const struct pci_device_id *ent)
4199{
7f60c64b 4200 struct net_device *dev;
cd28ab6a 4201 struct sky2_hw *hw;
be63a21c 4202 int err, using_dac = 0, wol_default;
c7127a34 4203 char buf1[16];
cd28ab6a 4204
793b883e
SH		 4205 err = pci_enable_device(pdev);
4206 if (err) {
b02a9258 4207 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4208 goto err_out;
4209 }
4210
793b883e
SH		 4211 err = pci_request_regions(pdev, DRV_NAME);
4212 if (err) {
b02a9258 4213 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4214 goto err_out_disable;
cd28ab6a
SH		 4215 }
4216
4217 pci_set_master(pdev);
4218
d1f3d4dd
SH		 4219 if (sizeof(dma_addr_t) > sizeof(u32) &&
4220 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4221 using_dac = 1;
4222 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4223 if (err < 0) {
b02a9258
SH		 4224 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4225 "for consistent allocations\n");
d1f3d4dd
SH		 4226 goto err_out_free_regions;
4227 }
d1f3d4dd 4228 } else {
cd28ab6a
SH		 4229 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4230 if (err) {
b02a9258 4231 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4232 goto err_out_free_regions;
4233 }
4234 }
d1f3d4dd 4235
be63a21c
SH		 4236 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4237
cd28ab6a 4238 err = -ENOMEM;
6aad85d6 4239 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4240 if (!hw) {
b02a9258 4241 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4242 goto err_out_free_regions;
4243 }
4244
cd28ab6a 4245 hw->pdev = pdev;
cd28ab6a
SH		 4246
4247 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4248 if (!hw->regs) {
b02a9258 4249 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4250 goto err_out_free_hw;
4251 }
4252
56a645cc 4253#ifdef __BIG_ENDIAN
f65b138c
SH		 4254 /* The sk98lin vendor driver uses hardware byte swapping but
4255 * this driver uses software swapping.
4256 */
56a645cc
SH		 4257 {
4258 u32 reg;
b32f40c4 4259 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 4260 reg &= ~PCI_REV_DESC;
b32f40c4 4261 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
56a645cc
SH		 4262 }
4263#endif
4264
08c06d8a 4265 /* ring for status responses */
167f53d0 4266 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4267 if (!hw->st_le)
4268 goto err_out_iounmap;
4269
e3173832 4270 err = sky2_init(hw);
cd28ab6a 4271 if (err)
793b883e 4272 goto err_out_iounmap;
cd28ab6a 4273
c7127a34
SH		 4274 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-2 %s rev %d\n",
4275 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4276 pdev->irq, sky2_name(hw->chip_id, buf1, sizeof(buf1)),
4277 hw->chip_rev);
cd28ab6a 4278
e3173832
SH		 4279 sky2_reset(hw);
4280
be63a21c 4281 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4282 if (!dev) {
4283 err = -ENOMEM;
cd28ab6a 4284 goto err_out_free_pci;
7f60c64b 4285 }
cd28ab6a 4286
9fa1b1f3
SH		 4287 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4288 err = sky2_test_msi(hw);
4289 if (err == -EOPNOTSUPP)
4290 pci_disable_msi(pdev);
4291 else if (err)
4292 goto err_out_free_netdev;
4293 }
4294
793b883e
SH		 4295 err = register_netdev(dev);
4296 if (err) {
b02a9258 4297 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4298 goto err_out_free_netdev;
4299 }
4300
6de16237
SH		 4301 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4302
ea76e635
SH		 4303 err = request_irq(pdev->irq, sky2_intr,
4304 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4305 dev->name, hw);
9fa1b1f3 4306 if (err) {
b02a9258 4307 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4308 goto err_out_unregister;
4309 }
4310 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4311 napi_enable(&hw->napi);
9fa1b1f3 4312
cd28ab6a
SH		 4313 sky2_show_addr(dev);
4314
7f60c64b 4315 if (hw->ports > 1) {
4316 struct net_device *dev1;
4317
be63a21c 4318 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4319 if (!dev1)
4320 dev_warn(&pdev->dev, "allocation for second device failed\n");
4321 else if ((err = register_netdev(dev1))) {
4322 dev_warn(&pdev->dev,
4323 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4324 hw->dev[1] = NULL;
4325 free_netdev(dev1);
b02a9258
SH		 4326 } else
4327 sky2_show_addr(dev1);
cd28ab6a
SH		 4328 }
4329
32c2c300 4330 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4331 INIT_WORK(&hw->restart_work, sky2_restart);
4332
793b883e
SH		 4333 pci_set_drvdata(pdev, hw);
4334
cd28ab6a
SH		 4335 return 0;
4336
793b883e 4337err_out_unregister:
ea76e635 4338 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4339 pci_disable_msi(pdev);
793b883e 4340 unregister_netdev(dev);
cd28ab6a
SH		 4341err_out_free_netdev:
4342 free_netdev(dev);
cd28ab6a 4343err_out_free_pci:
793b883e 4344 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4345 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4346err_out_iounmap:
4347 iounmap(hw->regs);
4348err_out_free_hw:
4349 kfree(hw);
4350err_out_free_regions:
4351 pci_release_regions(pdev);
44a1d2e5 4352err_out_disable:
cd28ab6a 4353 pci_disable_device(pdev);
cd28ab6a 4354err_out:
549a68c3 4355 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4356 return err;
4357}
4358
4359static void __devexit sky2_remove(struct pci_dev *pdev)
4360{
793b883e 4361 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4362 int i;
cd28ab6a 4363
793b883e 4364 if (!hw)
cd28ab6a
SH		 4365 return;
4366
32c2c300 4367 del_timer_sync(&hw->watchdog_timer);
6de16237 4368 cancel_work_sync(&hw->restart_work);
d27ed387 4369
b877fe28 4370 for (i = hw->ports-1; i >= 0; --i)
6de16237 4371 unregister_netdev(hw->dev[i]);
81906791 4372
d27ed387 4373 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4374
ae306cca
SH		 4375 sky2_power_aux(hw);
4376
cd28ab6a 4377 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4378 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4379 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4380
4381 free_irq(pdev->irq, hw);
ea76e635 4382 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4383 pci_disable_msi(pdev);
793b883e 4384 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4385 pci_release_regions(pdev);
4386 pci_disable_device(pdev);
793b883e 4387
b877fe28 4388 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4389 free_netdev(hw->dev[i]);
4390
cd28ab6a
SH		 4391 iounmap(hw->regs);
4392 kfree(hw);
5afa0a9c 4393
cd28ab6a
SH		 4394 pci_set_drvdata(pdev, NULL);
4395}
4396
4397#ifdef CONFIG_PM
4398static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4399{
793b883e 4400 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4401 int i, wol = 0;
cd28ab6a 4402
549a68c3
SH		 4403 if (!hw)
4404 return 0;
4405
063a0b38
SH		 4406 del_timer_sync(&hw->watchdog_timer);
4407 cancel_work_sync(&hw->restart_work);
4408
f05267e7 4409 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4410 struct net_device *dev = hw->dev[i];
e3173832 4411 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4412
063a0b38 4413 netif_device_detach(dev);
e3173832 4414 if (netif_running(dev))
5afa0a9c 4415 sky2_down(dev);
e3173832
SH		 4416
4417 if (sky2->wol)
4418 sky2_wol_init(sky2);
4419
4420 wol |= sky2->wol;
cd28ab6a
SH		 4421 }
4422
8ab8fca2 4423 sky2_write32(hw, B0_IMSK, 0);
6de16237 4424 napi_disable(&hw->napi);
ae306cca 4425 sky2_power_aux(hw);
e3173832 4426
d374c1c1 4427 pci_save_state(pdev);
e3173832 4428 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4429 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4430
2ccc99b7 4431 return 0;
cd28ab6a
SH		 4432}
4433
4434static int sky2_resume(struct pci_dev *pdev)
4435{
793b883e 4436 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4437 int i, err;
cd28ab6a 4438
549a68c3
SH		 4439 if (!hw)
4440 return 0;
4441
f71eb1a2
SH		 4442 err = pci_set_power_state(pdev, PCI_D0);
4443 if (err)
4444 goto out;
ae306cca
SH		 4445
4446 err = pci_restore_state(pdev);
4447 if (err)
4448 goto out;
4449
cd28ab6a 4450 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4451
4452 /* Re-enable all clocks */
05745c4a
SH		 4453 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4454 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4455 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4456 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4457
e3173832 4458 sky2_reset(hw);
8ab8fca2 4459 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4460 napi_enable(&hw->napi);
8ab8fca2 4461
f05267e7 4462 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4463 struct net_device *dev = hw->dev[i];
063a0b38
SH		 4464
4465 netif_device_attach(dev);
6a5706b9 4466 if (netif_running(dev)) {
08c06d8a
SH		 4467 err = sky2_up(dev);
4468 if (err) {
4469 printk(KERN_ERR PFX "%s: could not up: %d\n",
4470 dev->name, err);
68c28898 4471 rtnl_lock();
08c06d8a 4472 dev_close(dev);
68c28898 4473 rtnl_unlock();
eb35cf60 4474 goto out;
5afa0a9c 4475 }
cd28ab6a
SH		 4476 }
4477 }
eb35cf60 4478
ae306cca 4479 return 0;
08c06d8a 4480out:
b02a9258 4481 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4482 pci_disable_device(pdev);
08c06d8a 4483 return err;
cd28ab6a
SH		 4484}
4485#endif
4486
e3173832
SH		 4487static void sky2_shutdown(struct pci_dev *pdev)
4488{
4489 struct sky2_hw *hw = pci_get_drvdata(pdev);
4490 int i, wol = 0;
4491
549a68c3
SH		 4492 if (!hw)
4493 return;
4494
5c0d6b34 4495 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4496
4497 for (i = 0; i < hw->ports; i++) {
4498 struct net_device *dev = hw->dev[i];
4499 struct sky2_port *sky2 = netdev_priv(dev);
4500
4501 if (sky2->wol) {
4502 wol = 1;
4503 sky2_wol_init(sky2);
4504 }
4505 }
4506
4507 if (wol)
4508 sky2_power_aux(hw);
4509
4510 pci_enable_wake(pdev, PCI_D3hot, wol);
4511 pci_enable_wake(pdev, PCI_D3cold, wol);
4512
4513 pci_disable_device(pdev);
f71eb1a2 4514 pci_set_power_state(pdev, PCI_D3hot);
e3173832
SH		 4515}
4516
cd28ab6a 4517static struct pci_driver sky2_driver = {
793b883e
SH		 4518 .name = DRV_NAME,
4519 .id_table = sky2_id_table,
4520 .probe = sky2_probe,
4521 .remove = __devexit_p(sky2_remove),
cd28ab6a 4522#ifdef CONFIG_PM
793b883e
SH		 4523 .suspend = sky2_suspend,
4524 .resume = sky2_resume,
cd28ab6a 4525#endif
e3173832 4526 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4527};
4528
4529static int __init sky2_init_module(void)
4530{
3cf26753 4531 sky2_debug_init();
50241c4c 4532 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4533}
4534
4535static void __exit sky2_cleanup_module(void)
4536{
4537 pci_unregister_driver(&sky2_driver);
3cf26753 4538 sky2_debug_cleanup();
cd28ab6a
SH		 4539}
4540
4541module_init(sky2_init_module);
4542module_exit(sky2_cleanup_module);
4543
4544MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4545MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4546MODULE_LICENSE("GPL");
5f4f9dc1 4547MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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