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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
ef743d33 41#include <linux/mii.h>
cd28ab6a
SH		 42
43#include <asm/irq.h>
44
d1f13708 45#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
46#define SKY2_VLAN_TAG_USED 1
47#endif
48
cd28ab6a
SH		 49#include "sky2.h"
50
51#define DRV_NAME "sky2"
52c89cac 52#define DRV_VERSION "1.10"
cd28ab6a
SH		 53#define PFX DRV_NAME " "
54
55/*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
14d0263f 58 * similar to Tigon3.
cd28ab6a
SH		 59 */
60
14d0263f 61#define RX_LE_SIZE 1024
cd28ab6a 62#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 63#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 64#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 65#define RX_SKB_ALIGN 8
22e11703 66#define RX_BUF_WRITE 16
793b883e
SH		 67
68#define TX_RING_SIZE 512
69#define TX_DEF_PENDING (TX_RING_SIZE - 1)
70#define TX_MIN_PENDING 64
b19666d9 71#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 72
793b883e 73#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 74#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 75#define TX_WATCHDOG (5 * HZ)
76#define NAPI_WEIGHT 64
77#define PHY_RETRIES 1000
78
cb5d9547
SH		 79#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
80
cd28ab6a 81static const u32 default_msg =
793b883e
SH		 82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 85
793b883e 86static int debug = -1; /* defaults above */
cd28ab6a
SH		 87module_param(debug, int, 0);
88MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
14d0263f 90static int copybreak __read_mostly = 128;
bdb5c58e
SH		 91module_param(copybreak, int, 0);
92MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
fb2690a9
SH		 94static int disable_msi = 0;
95module_param(disable_msi, int, 0);
96MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
e561a83b 98static int idle_timeout = 0;
01bd7564 99module_param(idle_timeout, int, 0);
e561a83b 100MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 101
cd28ab6a 102static const struct pci_device_id sky2_id_table[] = {
793b883e 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
cd28ab6a
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
2f4a66ad 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) },
cd28ab6a
SH		 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
5f5d83fd 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) },
57fa442c
SH		 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) },
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) },
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) },
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) },
2f4a66ad 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) },
cd28ab6a
SH		 130 { 0 }
131};
793b883e 132
cd28ab6a
SH		 133MODULE_DEVICE_TABLE(pci, sky2_id_table);
134
135/* Avoid conditionals by using array */
136static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
137static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 138static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 139
92f965e8
SH		 140/* This driver supports yukon2 chipset only */
141static const char *yukon2_name[] = {
142 "XL", /* 0xb3 */
143 "EC Ultra", /* 0xb4 */
144 "UNKNOWN", /* 0xb5 */
145 "EC", /* 0xb6 */
146 "FE", /* 0xb7 */
793b883e
SH		 147};
148
793b883e 149/* Access to external PHY */
ef743d33 150static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 151{
152 int i;
153
154 gma_write16(hw, port, GM_SMI_DATA, val);
155 gma_write16(hw, port, GM_SMI_CTRL,
156 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
157
158 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 159 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 160 return 0;
793b883e 161 udelay(1);
cd28ab6a 162 }
ef743d33 163
793b883e 164 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 165 return -ETIMEDOUT;
cd28ab6a
SH		 166}
167
ef743d33 168static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 169{
170 int i;
171
793b883e 172 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 173 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
174
175 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33 176 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
177 *val = gma_read16(hw, port, GM_SMI_DATA);
178 return 0;
179 }
180
793b883e 181 udelay(1);
cd28ab6a
SH		 182 }
183
ef743d33 184 return -ETIMEDOUT;
185}
186
187static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
188{
189 u16 v;
190
191 if (__gm_phy_read(hw, port, reg, &v) != 0)
192 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
193 return v;
cd28ab6a
SH		 194}
195
2ccc99b7 196static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
5afa0a9c 197{
198 u16 power_control;
5afa0a9c 199 int vaux;
5afa0a9c 200
201 pr_debug("sky2_set_power_state %d\n", state);
202 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
203
56a645cc 204 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 205 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c 206 (power_control & PCI_PM_CAP_PME_D3cold);
207
56a645cc 208 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c 209
210 power_control |= PCI_PM_CTRL_PME_STATUS;
211 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
212
213 switch (state) {
214 case PCI_D0:
215 /* switch power to VCC (WA for VAUX problem) */
216 sky2_write8(hw, B0_POWER_CTRL,
217 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
218
219 /* disable Core Clock Division, */
220 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
221
222 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
223 /* enable bits are inverted */
224 sky2_write8(hw, B2_Y2_CLK_GATE,
225 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
226 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
227 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
228 else
229 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
230
977bdf06 231 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
d3bcfbeb 232 u32 reg1;
233
56a645cc
SH		 234 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
235 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 236 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 237 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
238 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 239 }
240
5afa0a9c 241 break;
242
243 case PCI_D3hot:
244 case PCI_D3cold:
5afa0a9c 245 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
246 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
247 else
248 /* enable bits are inverted */
249 sky2_write8(hw, B2_Y2_CLK_GATE,
250 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
251 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
252 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
253
254 /* switch power to VAUX */
255 if (vaux && state != PCI_D3cold)
256 sky2_write8(hw, B0_POWER_CTRL,
257 (PC_VAUX_ENA | PC_VCC_ENA |
258 PC_VAUX_ON | PC_VCC_OFF));
259 break;
260 default:
261 printk(KERN_ERR PFX "Unknown power state %d\n", state);
5afa0a9c 262 }
263
56a645cc 264 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c 265 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
5afa0a9c 266}
267
d3bcfbeb 268static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 269{
270 u16 reg;
271
272 /* disable all GMAC IRQ's */
273 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
274 /* disable PHY IRQs */
275 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 276
cd28ab6a
SH		 277 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
278 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
279 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
280 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
281
282 reg = gma_read16(hw, port, GM_RX_CTRL);
283 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
284 gma_write16(hw, port, GM_RX_CTRL, reg);
285}
286
16ad91e1
SH		 287/* flow control to advertise bits */
288static const u16 copper_fc_adv[] = {
289 [FC_NONE] = 0,
290 [FC_TX] = PHY_M_AN_ASP,
291 [FC_RX] = PHY_M_AN_PC,
292 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
293};
294
295/* flow control to advertise bits when using 1000BaseX */
296static const u16 fiber_fc_adv[] = {
297 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
298 [FC_TX] = PHY_M_P_ASYM_MD_X,
299 [FC_RX] = PHY_M_P_SYM_MD_X,
300 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
301};
302
303/* flow control to GMA disable bits */
304static const u16 gm_fc_disable[] = {
305 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
306 [FC_TX] = GM_GPCR_FC_RX_DIS,
307 [FC_RX] = GM_GPCR_FC_TX_DIS,
308 [FC_BOTH] = 0,
309};
310
311
cd28ab6a
SH		 312static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
313{
314 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 315 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 316
ed6d32c7 317 if (sky2->autoneg == AUTONEG_ENABLE &&
86a31a75 318 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 319 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
320
321 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 322 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 323 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
324
325 if (hw->chip_id == CHIP_ID_YUKON_EC)
326 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
327 else
328 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
329
330 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
331 }
332
333 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 334 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 335 if (hw->chip_id == CHIP_ID_YUKON_FE) {
336 /* enable automatic crossover */
337 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
338 } else {
339 /* disable energy detect */
340 ctrl &= ~PHY_M_PC_EN_DET_MSK;
341
342 /* enable automatic crossover */
343 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
344
345 if (sky2->autoneg == AUTONEG_ENABLE &&
ed6d32c7 346 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 347 ctrl &= ~PHY_M_PC_DSC_MSK;
348 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
349 }
350 }
cd28ab6a
SH		 351 } else {
352 /* workaround for deviation #4.88 (CRC errors) */
353 /* disable Automatic Crossover */
354
355 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 356 }
cd28ab6a 357
b89165f2
SH		 358 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
359
360 /* special setup for PHY 88E1112 Fiber */
361 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
362 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 363
b89165f2
SH		 364 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
365 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
366 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
367 ctrl &= ~PHY_M_MAC_MD_MSK;
368 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
369 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
370
371 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 372 /* select page 1 to access Fiber registers */
373 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 374
375 /* for SFP-module set SIGDET polarity to low */
376 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
377 ctrl |= PHY_M_FIB_SIGD_POL;
378 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
cd28ab6a 379 }
b89165f2
SH		 380
381 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 382 }
383
7800fddc 384 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 385 ct1000 = 0;
386 adv = PHY_AN_CSMA;
2eaba1a2 387 reg = 0;
cd28ab6a
SH		 388
389 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 390 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 391 if (sky2->advertising & ADVERTISED_1000baseT_Full)
392 ct1000 |= PHY_M_1000C_AFD;
393 if (sky2->advertising & ADVERTISED_1000baseT_Half)
394 ct1000 |= PHY_M_1000C_AHD;
395 if (sky2->advertising & ADVERTISED_100baseT_Full)
396 adv |= PHY_M_AN_100_FD;
397 if (sky2->advertising & ADVERTISED_100baseT_Half)
398 adv |= PHY_M_AN_100_HD;
399 if (sky2->advertising & ADVERTISED_10baseT_Full)
400 adv |= PHY_M_AN_10_FD;
401 if (sky2->advertising & ADVERTISED_10baseT_Half)
402 adv |= PHY_M_AN_10_HD;
709c6e7b 403
16ad91e1 404 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 405 } else { /* special defines for FIBER (88E1040S only) */
406 if (sky2->advertising & ADVERTISED_1000baseT_Full)
407 adv |= PHY_M_AN_1000X_AFD;
408 if (sky2->advertising & ADVERTISED_1000baseT_Half)
409 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 410
16ad91e1 411 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 412 }
cd28ab6a
SH		 413
414 /* Restart Auto-negotiation */
415 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
416 } else {
417 /* forced speed/duplex settings */
418 ct1000 = PHY_M_1000C_MSE;
419
2eaba1a2
SH		 420 /* Disable auto update for duplex flow control and speed */
421 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 422
423 switch (sky2->speed) {
424 case SPEED_1000:
425 ctrl |= PHY_CT_SP1000;
2eaba1a2 426 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 427 break;
428 case SPEED_100:
429 ctrl |= PHY_CT_SP100;
2eaba1a2 430 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 431 break;
432 }
433
2eaba1a2
SH		 434 if (sky2->duplex == DUPLEX_FULL) {
435 reg |= GM_GPCR_DUP_FULL;
436 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 437 } else if (sky2->speed < SPEED_1000)
438 sky2->flow_mode = FC_NONE;
2eaba1a2 439
2eaba1a2 440
16ad91e1 441 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 442
443 /* Forward pause packets to GMAC? */
16ad91e1 444 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 445 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
446 else
447 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 448 }
449
2eaba1a2
SH		 450 gma_write16(hw, port, GM_GP_CTRL, reg);
451
cd28ab6a
SH		 452 if (hw->chip_id != CHIP_ID_YUKON_FE)
453 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
454
455 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
456 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
457
458 /* Setup Phy LED's */
459 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
460 ledover = 0;
461
462 switch (hw->chip_id) {
463 case CHIP_ID_YUKON_FE:
464 /* on 88E3082 these bits are at 11..9 (shifted left) */
465 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
466
467 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
468
469 /* delete ACT LED control bits */
470 ctrl &= ~PHY_M_FELP_LED1_MSK;
471 /* change ACT LED control to blink mode */
472 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
473 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
474 break;
475
476 case CHIP_ID_YUKON_XL:
793b883e 477 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 478
479 /* select page 3 to access LED control register */
480 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
481
482 /* set LED Function Control register */
ed6d32c7
SH		 483 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
484 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
485 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
486 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
487 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 488
489 /* set Polarity Control register */
490 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 491 (PHY_M_POLC_LS1_P_MIX(4) |
492 PHY_M_POLC_IS0_P_MIX(4) |
493 PHY_M_POLC_LOS_CTRL(2) |
494 PHY_M_POLC_INIT_CTRL(2) |
495 PHY_M_POLC_STA1_CTRL(2) |
496 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 497
498 /* restore page register */
793b883e 499 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 500 break;
ed6d32c7
SH		 501 case CHIP_ID_YUKON_EC_U:
502 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
503
504 /* select page 3 to access LED control register */
505 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
506
507 /* set LED Function Control register */
508 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
509 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
510 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
511 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
512 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
513
514 /* set Blink Rate in LED Timer Control Register */
515 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
516 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
517 /* restore page register */
518 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
519 break;
cd28ab6a
SH		 520
521 default:
522 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
523 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
524 /* turn off the Rx LED (LED_RX) */
525 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
526 }
527
ed6d32c7 528 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 529 /* apply fixes in PHY AFE */
ed6d32c7
SH		 530 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
531 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
532
977bdf06 533 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 534 gm_phy_write(hw, port, 0x18, 0xaa99);
535 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 536
977bdf06 537 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 538 gm_phy_write(hw, port, 0x18, 0xa204);
539 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 540
541 /* set page register to 0 */
ed6d32c7 542 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
977bdf06
SH		 543 } else {
544 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 545
977bdf06
SH		 546 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
547 /* turn on 100 Mbps LED (LED_LINK100) */
548 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
549 }
cd28ab6a 550
977bdf06
SH		 551 if (ledover)
552 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
553
554 }
2eaba1a2 555
d571b694 556 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 557 if (sky2->autoneg == AUTONEG_ENABLE)
558 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
559 else
560 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
561}
562
d3bcfbeb 563static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
564{
565 u32 reg1;
566 static const u32 phy_power[]
567 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
568
569 /* looks like this XL is back asswards .. */
570 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
571 onoff = !onoff;
572
573 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
574
575 if (onoff)
576 /* Turn off phy power saving */
577 reg1 &= ~phy_power[port];
578 else
579 reg1 |= phy_power[port];
580
581 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 582 sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb 583 udelay(100);
584}
585
1b537565
SH		 586/* Force a renegotiation */
587static void sky2_phy_reinit(struct sky2_port *sky2)
588{
e07b1aa8 589 spin_lock_bh(&sky2->phy_lock);
1b537565 590 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 591 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 592}
593
cd28ab6a
SH		 594static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
595{
596 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
597 u16 reg;
598 int i;
599 const u8 *addr = hw->dev[port]->dev_addr;
600
42eeea01 601 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
602 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 603
604 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
605
793b883e 606 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 607 /* WA DEV_472 -- looks like crossed wires on port 2 */
608 /* clear GMAC 1 Control reset */
609 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
610 do {
611 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
612 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
613 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
614 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
615 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
616 }
617
793b883e 618 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 619
2eaba1a2
SH		 620 /* Enable Transmit FIFO Underrun */
621 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
622
e07b1aa8 623 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 624 sky2_phy_init(hw, port);
e07b1aa8 625 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 626
627 /* MIB clear */
628 reg = gma_read16(hw, port, GM_PHY_ADDR);
629 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
630
43f2f104
SH		 631 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
632 gma_read16(hw, port, i);
cd28ab6a
SH		 633 gma_write16(hw, port, GM_PHY_ADDR, reg);
634
635 /* transmit control */
636 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
637
638 /* receive control reg: unicast + multicast + no FCS */
639 gma_write16(hw, port, GM_RX_CTRL,
793b883e 640 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 641
642 /* transmit flow control */
643 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
644
645 /* transmit parameter */
646 gma_write16(hw, port, GM_TX_PARAM,
647 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
648 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
649 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
650 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
651
652 /* serial mode register */
653 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 654 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 655
6b1a3aef 656 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 657 reg |= GM_SMOD_JUMBO_ENA;
658
659 gma_write16(hw, port, GM_SERIAL_MODE, reg);
660
cd28ab6a
SH		 661 /* virtual address for data */
662 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
663
793b883e
SH		 664 /* physical address: used for pause frames */
665 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
666
667 /* ignore counter overflows */
cd28ab6a
SH		 668 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
669 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
670 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
671
672 /* Configure Rx MAC FIFO */
673 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 674 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
675 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 676
d571b694 677 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 678 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 679
8df9a876
SH		 680 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
681 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 682
683 /* Configure Tx MAC FIFO */
684 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
685 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 686
687 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
8df9a876 688 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 689 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
690 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
691 /* set Tx GMAC FIFO Almost Empty Threshold */
692 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
693 /* Disable Store & Forward mode for TX */
694 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
695 }
696 }
697
cd28ab6a
SH		 698}
699
470ea7eb
SH		 700/* Assign Ram Buffer allocation in units of 64bit (8 bytes) */
701static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 end)
cd28ab6a 702{
470ea7eb 703 pr_debug(PFX "q %d %#x %#x\n", q, start, end);
793b883e 704
cd28ab6a
SH		 705 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
706 sky2_write32(hw, RB_ADDR(q, RB_START), start);
707 sky2_write32(hw, RB_ADDR(q, RB_END), end);
708 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
709 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
710
711 if (q == Q_R1 || q == Q_R2) {
470ea7eb 712 u32 space = end - start + 1;
1c28f6ba 713 u32 tp = space - space/4;
793b883e 714
1c28f6ba
SH		 715 /* On receive queue's set the thresholds
716 * give receiver priority when > 3/4 full
717 * send pause when down to 2K
718 */
719 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
720 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 721
1c28f6ba
SH		 722 tp = space - 2048/8;
723 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
724 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 725 } else {
726 /* Enable store & forward on Tx queue's because
727 * Tx FIFO is only 1K on Yukon
728 */
729 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
730 }
731
732 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 733 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 734}
735
cd28ab6a 736/* Setup Bus Memory Interface */
af4ed7e6 737static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 738{
739 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
740 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
741 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 742 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 743}
744
cd28ab6a
SH		 745/* Setup prefetch unit registers. This is the interface between
746 * hardware and driver list elements
747 */
8cc048e3 748static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 749 u64 addr, u32 last)
750{
cd28ab6a
SH		 751 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
752 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
753 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
754 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
755 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
756 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 757
758 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 759}
760
793b883e
SH		 761static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
762{
763 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
764
cb5d9547 765 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 766 le->ctrl = 0;
793b883e
SH		 767 return le;
768}
cd28ab6a 769
291ea614
SH		 770static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
771 struct sky2_tx_le *le)
772{
773 return sky2->tx_ring + (le - sky2->tx_le);
774}
775
290d4de5
SH		 776/* Update chip's next pointer */
777static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 778{
98232f85 779 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
762c2de2 780 wmb();
98232f85 781 sky2_write16(hw, q, idx);
782 sky2_read16(hw, q);
cd28ab6a
SH		 783}
784
793b883e 785
cd28ab6a
SH		 786static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
787{
788 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 789 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 790 le->ctrl = 0;
cd28ab6a
SH		 791 return le;
792}
793
a018e330 794/* Return high part of DMA address (could be 32 or 64 bit) */
795static inline u32 high32(dma_addr_t a)
796{
a036119f 797 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330 798}
799
14d0263f
SH		 800/* Build description to hardware for one receive segment */
801static void sky2_rx_add(struct sky2_port *sky2, u8 op,
802 dma_addr_t map, unsigned len)
cd28ab6a
SH		 803{
804 struct sky2_rx_le *le;
734d1868 805 u32 hi = high32(map);
cd28ab6a 806
793b883e 807 if (sky2->rx_addr64 != hi) {
cd28ab6a 808 le = sky2_next_rx(sky2);
793b883e 809 le->addr = cpu_to_le32(hi);
cd28ab6a 810 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 811 sky2->rx_addr64 = high32(map + len);
cd28ab6a 812 }
793b883e 813
cd28ab6a 814 le = sky2_next_rx(sky2);
734d1868
SH		 815 le->addr = cpu_to_le32((u32) map);
816 le->length = cpu_to_le16(len);
14d0263f 817 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 818}
819
14d0263f
SH		 820/* Build description to hardware for one possibly fragmented skb */
821static void sky2_rx_submit(struct sky2_port *sky2,
822 const struct rx_ring_info *re)
823{
824 int i;
825
826 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
827
828 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
829 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
830}
831
832
833static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
834 unsigned size)
835{
836 struct sk_buff *skb = re->skb;
837 int i;
838
839 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
840 pci_unmap_len_set(re, data_size, size);
841
842 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
843 re->frag_addr[i] = pci_map_page(pdev,
844 skb_shinfo(skb)->frags[i].page,
845 skb_shinfo(skb)->frags[i].page_offset,
846 skb_shinfo(skb)->frags[i].size,
847 PCI_DMA_FROMDEVICE);
848}
849
850static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
851{
852 struct sk_buff *skb = re->skb;
853 int i;
854
855 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
856 PCI_DMA_FROMDEVICE);
857
858 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
859 pci_unmap_page(pdev, re->frag_addr[i],
860 skb_shinfo(skb)->frags[i].size,
861 PCI_DMA_FROMDEVICE);
862}
793b883e 863
cd28ab6a
SH		 864/* Tell chip where to start receive checksum.
865 * Actually has two checksums, but set both same to avoid possible byte
866 * order problems.
867 */
793b883e 868static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 869{
870 struct sky2_rx_le *le;
871
cd28ab6a 872 le = sky2_next_rx(sky2);
f65b138c 873 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
cd28ab6a
SH		 874 le->ctrl = 0;
875 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 876
793b883e
SH		 877 sky2_write32(sky2->hw,
878 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
879 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 880
881}
882
6b1a3aef 883/*
884 * The RX Stop command will not work for Yukon-2 if the BMU does not
885 * reach the end of packet and since we can't make sure that we have
886 * incoming data, we must reset the BMU while it is not doing a DMA
887 * transfer. Since it is possible that the RX path is still active,
888 * the RX RAM buffer will be stopped first, so any possible incoming
889 * data will not trigger a DMA. After the RAM buffer is stopped, the
890 * BMU is polled until any DMA in progress is ended and only then it
891 * will be reset.
892 */
893static void sky2_rx_stop(struct sky2_port *sky2)
894{
895 struct sky2_hw *hw = sky2->hw;
896 unsigned rxq = rxqaddr[sky2->port];
897 int i;
898
899 /* disable the RAM Buffer receive queue */
900 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
901
902 for (i = 0; i < 0xffff; i++)
903 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
904 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
905 goto stopped;
906
907 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
908 sky2->netdev->name);
909stopped:
910 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
911
912 /* reset the Rx prefetch unit */
913 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
914}
793b883e 915
d571b694 916/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 917static void sky2_rx_clean(struct sky2_port *sky2)
918{
919 unsigned i;
920
921 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 922 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 923 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 924
925 if (re->skb) {
14d0263f 926 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 927 kfree_skb(re->skb);
928 re->skb = NULL;
929 }
930 }
931}
932
ef743d33 933/* Basic MII support */
934static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
935{
936 struct mii_ioctl_data *data = if_mii(ifr);
937 struct sky2_port *sky2 = netdev_priv(dev);
938 struct sky2_hw *hw = sky2->hw;
939 int err = -EOPNOTSUPP;
940
941 if (!netif_running(dev))
942 return -ENODEV; /* Phy still in reset */
943
d89e1343 944 switch (cmd) {
ef743d33 945 case SIOCGMIIPHY:
946 data->phy_id = PHY_ADDR_MARV;
947
948 /* fallthru */
949 case SIOCGMIIREG: {
950 u16 val = 0;
91c86df5 951
e07b1aa8 952 spin_lock_bh(&sky2->phy_lock);
ef743d33 953 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 954 spin_unlock_bh(&sky2->phy_lock);
91c86df5 955
ef743d33 956 data->val_out = val;
957 break;
958 }
959
960 case SIOCSMIIREG:
961 if (!capable(CAP_NET_ADMIN))
962 return -EPERM;
963
e07b1aa8 964 spin_lock_bh(&sky2->phy_lock);
ef743d33 965 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
966 data->val_in);
e07b1aa8 967 spin_unlock_bh(&sky2->phy_lock);
ef743d33 968 break;
969 }
970 return err;
971}
972
d1f13708 973#ifdef SKY2_VLAN_TAG_USED
974static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
975{
976 struct sky2_port *sky2 = netdev_priv(dev);
977 struct sky2_hw *hw = sky2->hw;
978 u16 port = sky2->port;
d1f13708 979
2bb8c262 980 netif_tx_lock_bh(dev);
d1f13708 981
982 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
983 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
984 sky2->vlgrp = grp;
985
2bb8c262 986 netif_tx_unlock_bh(dev);
d1f13708 987}
988
989static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
990{
991 struct sky2_port *sky2 = netdev_priv(dev);
992 struct sky2_hw *hw = sky2->hw;
993 u16 port = sky2->port;
d1f13708 994
2bb8c262 995 netif_tx_lock_bh(dev);
d1f13708 996
997 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
998 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
999 if (sky2->vlgrp)
1000 sky2->vlgrp->vlan_devices[vid] = NULL;
1001
2bb8c262 1002 netif_tx_unlock_bh(dev);
d1f13708 1003}
1004#endif
1005
82788c7a 1006/*
14d0263f
SH		 1007 * Allocate an skb for receiving. If the MTU is large enough
1008 * make the skb non-linear with a fragment list of pages.
1009 *
82788c7a
SH		 1010 * It appears the hardware has a bug in the FIFO logic that
1011 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86 1012 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1013 * aligned except if slab debugging is enabled.
82788c7a 1014 */
14d0263f 1015static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1016{
1017 struct sk_buff *skb;
14d0263f
SH		 1018 unsigned long p;
1019 int i;
82788c7a 1020
14d0263f
SH		 1021 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1022 if (!skb)
1023 goto nomem;
1024
1025 p = (unsigned long) skb->data;
1026 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1027
1028 for (i = 0; i < sky2->rx_nfrags; i++) {
1029 struct page *page = alloc_page(GFP_ATOMIC);
1030
1031 if (!page)
1032 goto free_partial;
1033 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1034 }
1035
1036 return skb;
14d0263f
SH		 1037free_partial:
1038 kfree_skb(skb);
1039nomem:
1040 return NULL;
82788c7a
SH		 1041}
1042
cd28ab6a
SH		 1043/*
1044 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1045 * Normal case this ends up creating one list element for skb
1046 * in the receive ring. Worst case if using large MTU and each
1047 * allocation falls on a different 64 bit region, that results
1048 * in 6 list elements per ring entry.
1049 * One element is used for checksum enable/disable, and one
1050 * extra to avoid wrap.
cd28ab6a 1051 */
6b1a3aef 1052static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1053{
6b1a3aef 1054 struct sky2_hw *hw = sky2->hw;
14d0263f 1055 struct rx_ring_info *re;
6b1a3aef 1056 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1057 unsigned i, size, space, thresh;
cd28ab6a 1058
6b1a3aef 1059 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1060 sky2_qset(hw, rxq);
977bdf06 1061
8df9a876
SH		 1062 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1063 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0)) {
977bdf06
SH		 1064 /* MAC Rx RAM Read is controlled by hardware */
1065 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1066 }
1067
6b1a3aef 1068 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1069
1070 rx_set_checksum(sky2);
14d0263f
SH		 1071
1072 /* Space needed for frame data + headers rounded up */
1073 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1074 + 8;
1075
1076 /* Stopping point for hardware truncation */
1077 thresh = (size - 8) / sizeof(u32);
1078
1079 /* Account for overhead of skb - to avoid order > 0 allocation */
1080 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1081 + sizeof(struct skb_shared_info);
1082
1083 sky2->rx_nfrags = space >> PAGE_SHIFT;
1084 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1085
1086 if (sky2->rx_nfrags != 0) {
1087 /* Compute residue after pages */
1088 space = sky2->rx_nfrags << PAGE_SHIFT;
1089
1090 if (space < size)
1091 size -= space;
1092 else
1093 size = 0;
1094
1095 /* Optimize to handle small packets and headers */
1096 if (size < copybreak)
1097 size = copybreak;
1098 if (size < ETH_HLEN)
1099 size = ETH_HLEN;
1100 }
1101 sky2->rx_data_size = size;
1102
1103 /* Fill Rx ring */
793b883e 1104 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1105 re = sky2->rx_ring + i;
cd28ab6a 1106
14d0263f 1107 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1108 if (!re->skb)
1109 goto nomem;
1110
14d0263f
SH		 1111 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1112 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1113 }
1114
a1433ac4
SH		 1115 /*
1116 * The receiver hangs if it receives frames larger than the
1117 * packet buffer. As a workaround, truncate oversize frames, but
1118 * the register is limited to 9 bits, so if you do frames > 2052
1119 * you better get the MTU right!
1120 */
a1433ac4
SH		 1121 if (thresh > 0x1ff)
1122 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1123 else {
1124 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1125 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1126 }
1127
6b1a3aef 1128 /* Tell chip about available buffers */
1129 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1130 return 0;
1131nomem:
1132 sky2_rx_clean(sky2);
1133 return -ENOMEM;
1134}
1135
1136/* Bring up network interface. */
1137static int sky2_up(struct net_device *dev)
1138{
1139 struct sky2_port *sky2 = netdev_priv(dev);
1140 struct sky2_hw *hw = sky2->hw;
1141 unsigned port = sky2->port;
e07b1aa8 1142 u32 ramsize, rxspace, imask;
ee7abb04 1143 int cap, err = -ENOMEM;
843a46f4 1144 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1145
ee7abb04
SH		 1146 /*
1147 * On dual port PCI-X card, there is an problem where status
1148 * can be received out of order due to split transactions
843a46f4 1149 */
ee7abb04
SH		 1150 if (otherdev && netif_running(otherdev) &&
1151 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1152 struct sky2_port *osky2 = netdev_priv(otherdev);
1153 u16 cmd;
1154
1155 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1156 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1157 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1158
1159 sky2->rx_csum = 0;
1160 osky2->rx_csum = 0;
1161 }
843a46f4 1162
cd28ab6a
SH		 1163 if (netif_msg_ifup(sky2))
1164 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1165
1166 /* must be power of 2 */
1167 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1168 TX_RING_SIZE *
1169 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1170 &sky2->tx_le_map);
1171 if (!sky2->tx_le)
1172 goto err_out;
1173
6cdbbdf3 1174 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1175 GFP_KERNEL);
1176 if (!sky2->tx_ring)
1177 goto err_out;
1178 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1179
1180 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1181 &sky2->rx_le_map);
1182 if (!sky2->rx_le)
1183 goto err_out;
1184 memset(sky2->rx_le, 0, RX_LE_BYTES);
1185
291ea614 1186 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1187 GFP_KERNEL);
1188 if (!sky2->rx_ring)
1189 goto err_out;
1190
d3bcfbeb 1191 sky2_phy_power(hw, port, 1);
1192
cd28ab6a
SH		 1193 sky2_mac_init(hw, port);
1194
470ea7eb
SH		 1195 /* Determine available ram buffer space in qwords. */
1196 ramsize = sky2_read8(hw, B2_E_0) * 4096/8;
1c28f6ba 1197
470ea7eb
SH		 1198 if (ramsize > 6*1024/8)
1199 rxspace = ramsize - (ramsize + 2) / 3;
1200 else
1201 rxspace = ramsize / 2;
cd28ab6a 1202
470ea7eb
SH		 1203 sky2_ramset(hw, rxqaddr[port], 0, rxspace-1);
1204 sky2_ramset(hw, txqaddr[port], rxspace, ramsize-1);
cd28ab6a 1205
793b883e
SH		 1206 /* Make sure SyncQ is disabled */
1207 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1208 RB_RST_SET);
1209
af4ed7e6 1210 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1211
977bdf06 1212 /* Set almost empty threshold */
c2716fb4
SH		 1213 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1214 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
977bdf06 1215 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1216
6b1a3aef 1217 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1218 TX_RING_SIZE - 1);
cd28ab6a 1219
6b1a3aef 1220 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1221 if (err)
1222 goto err_out;
1223
cd28ab6a 1224 /* Enable interrupts from phy/mac for port */
e07b1aa8 1225 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1226 imask |= portirq_msk[port];
e07b1aa8
SH		 1227 sky2_write32(hw, B0_IMSK, imask);
1228
cd28ab6a
SH		 1229 return 0;
1230
1231err_out:
1b537565 1232 if (sky2->rx_le) {
cd28ab6a
SH		 1233 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1234 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1235 sky2->rx_le = NULL;
1236 }
1237 if (sky2->tx_le) {
cd28ab6a
SH		 1238 pci_free_consistent(hw->pdev,
1239 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1240 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1241 sky2->tx_le = NULL;
1242 }
1243 kfree(sky2->tx_ring);
1244 kfree(sky2->rx_ring);
cd28ab6a 1245
1b537565
SH		 1246 sky2->tx_ring = NULL;
1247 sky2->rx_ring = NULL;
cd28ab6a
SH		 1248 return err;
1249}
1250
793b883e
SH		 1251/* Modular subtraction in ring */
1252static inline int tx_dist(unsigned tail, unsigned head)
1253{
cb5d9547 1254 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1255}
cd28ab6a 1256
793b883e
SH		 1257/* Number of list elements available for next tx */
1258static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1259{
793b883e 1260 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1261}
1262
793b883e 1263/* Estimate of number of transmit list elements required */
28bd181a 1264static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1265{
793b883e
SH		 1266 unsigned count;
1267
1268 count = sizeof(dma_addr_t) / sizeof(u32);
1269 count += skb_shinfo(skb)->nr_frags * count;
1270
89114afd 1271 if (skb_is_gso(skb))
793b883e
SH		 1272 ++count;
1273
84fa7933 1274 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1275 ++count;
1276
1277 return count;
cd28ab6a
SH		 1278}
1279
793b883e
SH		 1280/*
1281 * Put one packet in ring for transmit.
1282 * A single packet can generate multiple list elements, and
1283 * the number of ring elements will probably be less than the number
1284 * of list elements used.
1285 */
cd28ab6a
SH		 1286static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1287{
1288 struct sky2_port *sky2 = netdev_priv(dev);
1289 struct sky2_hw *hw = sky2->hw;
d1f13708 1290 struct sky2_tx_le *le = NULL;
6cdbbdf3 1291 struct tx_ring_info *re;
cd28ab6a
SH		 1292 unsigned i, len;
1293 dma_addr_t mapping;
1294 u32 addr64;
1295 u16 mss;
1296 u8 ctrl;
1297
2bb8c262
SH		 1298 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1299 return NETDEV_TX_BUSY;
cd28ab6a 1300
793b883e 1301 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1302 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1303 dev->name, sky2->tx_prod, skb->len);
1304
cd28ab6a
SH		 1305 len = skb_headlen(skb);
1306 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1307 addr64 = high32(mapping);
793b883e 1308
a018e330 1309 /* Send high bits if changed or crosses boundary */
1310 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1311 le = get_tx_le(sky2);
f65b138c 1312 le->addr = cpu_to_le32(addr64);
793b883e 1313 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1314 sky2->tx_addr64 = high32(mapping + len);
793b883e 1315 }
cd28ab6a
SH		 1316
1317 /* Check for TCP Segmentation Offload */
7967168c 1318 mss = skb_shinfo(skb)->gso_size;
793b883e 1319 if (mss != 0) {
cd28ab6a
SH		 1320 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1321 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1322 mss += ETH_HLEN;
1323
e07560cd 1324 if (mss != sky2->tx_last_mss) {
1325 le = get_tx_le(sky2);
f65b138c 1326 le->addr = cpu_to_le32(mss);
e07560cd 1327 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1328 sky2->tx_last_mss = mss;
1329 }
cd28ab6a
SH		 1330 }
1331
cd28ab6a 1332 ctrl = 0;
d1f13708 1333#ifdef SKY2_VLAN_TAG_USED
1334 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1335 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1336 if (!le) {
1337 le = get_tx_le(sky2);
f65b138c 1338 le->addr = 0;
d1f13708 1339 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1340 } else
1341 le->opcode |= OP_VLAN;
1342 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1343 ctrl |= INS_VLAN;
1344 }
1345#endif
1346
1347 /* Handle TCP checksum offload */
84fa7933 1348 if (skb->ip_summed == CHECKSUM_PARTIAL) {
f65b138c
SH		 1349 unsigned offset = skb->h.raw - skb->data;
1350 u32 tcpsum;
1351
1352 tcpsum = offset << 16; /* sum start */
ff1dcadb 1353 tcpsum |= offset + skb->csum_offset; /* sum write */
cd28ab6a
SH		 1354
1355 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1356 if (skb->nh.iph->protocol == IPPROTO_UDP)
1357 ctrl |= UDPTCP;
1358
f65b138c
SH		 1359 if (tcpsum != sky2->tx_tcpsum) {
1360 sky2->tx_tcpsum = tcpsum;
1d179332 1361
1362 le = get_tx_le(sky2);
f65b138c 1363 le->addr = cpu_to_le32(tcpsum);
1d179332 1364 le->length = 0; /* initial checksum value */
1365 le->ctrl = 1; /* one packet */
1366 le->opcode = OP_TCPLISW | HW_OWNER;
1367 }
cd28ab6a
SH		 1368 }
1369
1370 le = get_tx_le(sky2);
f65b138c 1371 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1372 le->length = cpu_to_le16(len);
1373 le->ctrl = ctrl;
793b883e 1374 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1375
291ea614 1376 re = tx_le_re(sky2, le);
cd28ab6a 1377 re->skb = skb;
6cdbbdf3 1378 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1379 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1380
1381 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1382 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1383
1384 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1385 frag->size, PCI_DMA_TODEVICE);
a036119f 1386 addr64 = high32(mapping);
793b883e
SH		 1387 if (addr64 != sky2->tx_addr64) {
1388 le = get_tx_le(sky2);
f65b138c 1389 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1390 le->ctrl = 0;
1391 le->opcode = OP_ADDR64 | HW_OWNER;
1392 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1393 }
1394
1395 le = get_tx_le(sky2);
f65b138c 1396 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1397 le->length = cpu_to_le16(frag->size);
1398 le->ctrl = ctrl;
793b883e 1399 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1400
291ea614
SH		 1401 re = tx_le_re(sky2, le);
1402 re->skb = skb;
1403 pci_unmap_addr_set(re, mapaddr, mapping);
1404 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1405 }
6cdbbdf3 1406
cd28ab6a
SH		 1407 le->ctrl |= EOP;
1408
97bda706 1409 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1410 netif_stop_queue(dev);
b19666d9 1411
290d4de5 1412 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1413
cd28ab6a
SH		 1414 dev->trans_start = jiffies;
1415 return NETDEV_TX_OK;
1416}
1417
cd28ab6a 1418/*
793b883e
SH		 1419 * Free ring elements from starting at tx_cons until "done"
1420 *
1421 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1422 * buffers so make sure not to free skb to early.
cd28ab6a 1423 */
d11c13e7 1424static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1425{
d11c13e7 1426 struct net_device *dev = sky2->netdev;
af2a58ac 1427 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1428 unsigned idx;
cd28ab6a 1429
0e3ff6aa 1430 BUG_ON(done >= TX_RING_SIZE);
2224795d 1431
291ea614
SH		 1432 for (idx = sky2->tx_cons; idx != done;
1433 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1434 struct sky2_tx_le *le = sky2->tx_le + idx;
1435 struct tx_ring_info *re = sky2->tx_ring + idx;
1436
1437 switch(le->opcode & ~HW_OWNER) {
1438 case OP_LARGESEND:
1439 case OP_PACKET:
1440 pci_unmap_single(pdev,
1441 pci_unmap_addr(re, mapaddr),
1442 pci_unmap_len(re, maplen),
1443 PCI_DMA_TODEVICE);
af2a58ac 1444 break;
291ea614
SH		 1445 case OP_BUFFER:
1446 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1447 pci_unmap_len(re, maplen),
734d1868 1448 PCI_DMA_TODEVICE);
291ea614
SH		 1449 break;
1450 }
1451
1452 if (le->ctrl & EOP) {
1453 if (unlikely(netif_msg_tx_done(sky2)))
1454 printk(KERN_DEBUG "%s: tx done %u\n",
1455 dev->name, idx);
794b2bd2 1456 dev_kfree_skb_any(re->skb);
cd28ab6a
SH		 1457 }
1458
291ea614 1459 le->opcode = 0; /* paranoia */
793b883e 1460 }
793b883e 1461
291ea614 1462 sky2->tx_cons = idx;
22e11703 1463 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1464 netif_wake_queue(dev);
cd28ab6a
SH		 1465}
1466
1467/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1468static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1469{
2bb8c262
SH		 1470 struct sky2_port *sky2 = netdev_priv(dev);
1471
1472 netif_tx_lock_bh(dev);
d11c13e7 1473 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1474 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1475}
1476
1477/* Network shutdown */
1478static int sky2_down(struct net_device *dev)
1479{
1480 struct sky2_port *sky2 = netdev_priv(dev);
1481 struct sky2_hw *hw = sky2->hw;
1482 unsigned port = sky2->port;
1483 u16 ctrl;
e07b1aa8 1484 u32 imask;
cd28ab6a 1485
1b537565
SH		 1486 /* Never really got started! */
1487 if (!sky2->tx_le)
1488 return 0;
1489
cd28ab6a
SH		 1490 if (netif_msg_ifdown(sky2))
1491 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1492
018d1c66 1493 /* Stop more packets from being queued */
cd28ab6a
SH		 1494 netif_stop_queue(dev);
1495
ebc646f6
SH		 1496 /* Disable port IRQ */
1497 imask = sky2_read32(hw, B0_IMSK);
1498 imask &= ~portirq_msk[port];
1499 sky2_write32(hw, B0_IMSK, imask);
1500
d3bcfbeb 1501 sky2_gmac_reset(hw, port);
793b883e 1502
cd28ab6a
SH		 1503 /* Stop transmitter */
1504 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1505 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1506
1507 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1508 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a 1509
c2716fb4
SH		 1510 /* WA for dev. #4.209 */
1511 if (hw->chip_id == CHIP_ID_YUKON_EC_U
8df9a876 1512 && (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
c2716fb4
SH		 1513 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1514 sky2->speed != SPEED_1000 ?
1515 TX_STFW_ENA : TX_STFW_DIS);
1516
cd28ab6a 1517 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1518 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1519 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1520
1521 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1522
1523 /* Workaround shared GMAC reset */
793b883e
SH		 1524 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1525 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1526 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1527
1528 /* Disable Force Sync bit and Enable Alloc bit */
1529 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1530 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1531
1532 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1533 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1534 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1535
1536 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1537 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1538 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1539
1540 /* Reset the Tx prefetch units */
1541 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1542 PREF_UNIT_RST_SET);
1543
1544 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1545
6b1a3aef 1546 sky2_rx_stop(sky2);
cd28ab6a
SH		 1547
1548 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1549 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1550
d3bcfbeb 1551 sky2_phy_power(hw, port, 0);
1552
d571b694 1553 /* turn off LED's */
cd28ab6a
SH		 1554 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1555
018d1c66 1556 synchronize_irq(hw->pdev->irq);
1557
2bb8c262 1558 sky2_tx_clean(dev);
cd28ab6a
SH		 1559 sky2_rx_clean(sky2);
1560
1561 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1562 sky2->rx_le, sky2->rx_le_map);
1563 kfree(sky2->rx_ring);
1564
1565 pci_free_consistent(hw->pdev,
1566 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1567 sky2->tx_le, sky2->tx_le_map);
1568 kfree(sky2->tx_ring);
1569
1b537565
SH		 1570 sky2->tx_le = NULL;
1571 sky2->rx_le = NULL;
1572
1573 sky2->rx_ring = NULL;
1574 sky2->tx_ring = NULL;
1575
cd28ab6a
SH		 1576 return 0;
1577}
1578
1579static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1580{
b89165f2 1581 if (!sky2_is_copper(hw))
793b883e
SH		 1582 return SPEED_1000;
1583
cd28ab6a
SH		 1584 if (hw->chip_id == CHIP_ID_YUKON_FE)
1585 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1586
1587 switch (aux & PHY_M_PS_SPEED_MSK) {
1588 case PHY_M_PS_SPEED_1000:
1589 return SPEED_1000;
1590 case PHY_M_PS_SPEED_100:
1591 return SPEED_100;
1592 default:
1593 return SPEED_10;
1594 }
1595}
1596
1597static void sky2_link_up(struct sky2_port *sky2)
1598{
1599 struct sky2_hw *hw = sky2->hw;
1600 unsigned port = sky2->port;
1601 u16 reg;
16ad91e1
SH		 1602 static const char *fc_name[] = {
1603 [FC_NONE] = "none",
1604 [FC_TX] = "tx",
1605 [FC_RX] = "rx",
1606 [FC_BOTH] = "both",
1607 };
cd28ab6a 1608
cd28ab6a 1609 /* enable Rx/Tx */
2eaba1a2 1610 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1611 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1612 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1613
1614 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1615
1616 netif_carrier_on(sky2->netdev);
1617 netif_wake_queue(sky2->netdev);
1618
1619 /* Turn on link LED */
793b883e 1620 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1621 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1622
ed6d32c7 1623 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
793b883e 1624 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1625 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1626
1627 switch(sky2->speed) {
1628 case SPEED_10:
1629 led |= PHY_M_LEDC_INIT_CTRL(7);
1630 break;
1631
1632 case SPEED_100:
1633 led |= PHY_M_LEDC_STA1_CTRL(7);
1634 break;
1635
1636 case SPEED_1000:
1637 led |= PHY_M_LEDC_STA0_CTRL(7);
1638 break;
1639 }
793b883e
SH		 1640
1641 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1642 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1643 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1644 }
1645
cd28ab6a
SH		 1646 if (netif_msg_link(sky2))
1647 printk(KERN_INFO PFX
d571b694 1648 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1649 sky2->netdev->name, sky2->speed,
1650 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1651 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1652}
1653
1654static void sky2_link_down(struct sky2_port *sky2)
1655{
1656 struct sky2_hw *hw = sky2->hw;
1657 unsigned port = sky2->port;
1658 u16 reg;
1659
1660 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1661
1662 reg = gma_read16(hw, port, GM_GP_CTRL);
1663 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1664 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1665
16ad91e1 1666 if (sky2->flow_status == FC_RX) {
cd28ab6a
SH		 1667 /* restore Asymmetric Pause bit */
1668 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1669 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1670 | PHY_M_AN_ASP);
cd28ab6a
SH		 1671 }
1672
cd28ab6a
SH		 1673 netif_carrier_off(sky2->netdev);
1674 netif_stop_queue(sky2->netdev);
1675
1676 /* Turn on link LED */
1677 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1678
1679 if (netif_msg_link(sky2))
1680 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1681
cd28ab6a
SH		 1682 sky2_phy_init(hw, port);
1683}
1684
16ad91e1
SH		 1685static enum flow_control sky2_flow(int rx, int tx)
1686{
1687 if (rx)
1688 return tx ? FC_BOTH : FC_RX;
1689 else
1690 return tx ? FC_TX : FC_NONE;
1691}
1692
793b883e
SH		 1693static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1694{
1695 struct sky2_hw *hw = sky2->hw;
1696 unsigned port = sky2->port;
1697 u16 lpa;
1698
1699 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1700
1701 if (lpa & PHY_M_AN_RF) {
1702 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1703 return -1;
1704 }
1705
793b883e
SH		 1706 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1707 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1708 sky2->netdev->name);
1709 return -1;
1710 }
1711
793b883e 1712 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1713 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e
SH		 1714
1715 /* Pause bits are offset (9..8) */
ed6d32c7 1716 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
793b883e
SH		 1717 aux >>= 6;
1718
16ad91e1
SH		 1719 sky2->flow_status = sky2_flow(aux & PHY_M_PS_RX_P_EN,
1720 aux & PHY_M_PS_TX_P_EN);
793b883e 1721
16ad91e1 1722 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
2eaba1a2 1723 && hw->chip_id != CHIP_ID_YUKON_EC_U)
16ad91e1 1724 sky2->flow_status = FC_NONE;
2eaba1a2 1725
16ad91e1 1726 if (aux & PHY_M_PS_RX_P_EN)
793b883e
SH		 1727 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1728 else
1729 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1730
1731 return 0;
1732}
cd28ab6a 1733
e07b1aa8
SH		 1734/* Interrupt from PHY */
1735static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1736{
e07b1aa8
SH		 1737 struct net_device *dev = hw->dev[port];
1738 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1739 u16 istatus, phystat;
1740
ebc646f6
SH		 1741 if (!netif_running(dev))
1742 return;
1743
e07b1aa8
SH		 1744 spin_lock(&sky2->phy_lock);
1745 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1746 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1747
cd28ab6a
SH		 1748 if (netif_msg_intr(sky2))
1749 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1750 sky2->netdev->name, istatus, phystat);
1751
2eaba1a2 1752 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1753 if (sky2_autoneg_done(sky2, phystat) == 0)
1754 sky2_link_up(sky2);
1755 goto out;
1756 }
cd28ab6a 1757
793b883e
SH		 1758 if (istatus & PHY_M_IS_LSP_CHANGE)
1759 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1760
793b883e
SH		 1761 if (istatus & PHY_M_IS_DUP_CHANGE)
1762 sky2->duplex =
1763 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1764
793b883e
SH		 1765 if (istatus & PHY_M_IS_LST_CHANGE) {
1766 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1767 sky2_link_up(sky2);
793b883e
SH		 1768 else
1769 sky2_link_down(sky2);
cd28ab6a 1770 }
793b883e 1771out:
e07b1aa8 1772 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1773}
1774
302d1252
SH		 1775
1776/* Transmit timeout is only called if we are running, carries is up
1777 * and tx queue is full (stopped).
1778 */
cd28ab6a
SH		 1779static void sky2_tx_timeout(struct net_device *dev)
1780{
1781 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1782 struct sky2_hw *hw = sky2->hw;
1783 unsigned txq = txqaddr[sky2->port];
8f24664d 1784 u16 report, done;
cd28ab6a
SH		 1785
1786 if (netif_msg_timer(sky2))
1787 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1788
8f24664d
SH		 1789 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1790 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1791
8f24664d
SH		 1792 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1793 dev->name,
1794 sky2->tx_cons, sky2->tx_prod, report, done);
1795
1796 if (report != done) {
1797 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1798
1799 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1800 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1801 } else if (report != sky2->tx_cons) {
1802 printk(KERN_INFO PFX "status report lost?\n");
1803
2bb8c262 1804 netif_tx_lock_bh(dev);
8f24664d 1805 sky2_tx_complete(sky2, report);
2bb8c262 1806 netif_tx_unlock_bh(dev);
8f24664d
SH		 1807 } else {
1808 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1809
8f24664d
SH		 1810 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1811 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1812
2bb8c262 1813 sky2_tx_clean(dev);
8f24664d
SH		 1814
1815 sky2_qset(hw, txq);
1816 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1817 }
cd28ab6a
SH		 1818}
1819
1820static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1821{
6b1a3aef 1822 struct sky2_port *sky2 = netdev_priv(dev);
1823 struct sky2_hw *hw = sky2->hw;
1824 int err;
1825 u16 ctl, mode;
e07b1aa8 1826 u32 imask;
cd28ab6a
SH		 1827
1828 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1829 return -EINVAL;
1830
5a5b1ea0 1831 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1832 return -EINVAL;
1833
6b1a3aef 1834 if (!netif_running(dev)) {
1835 dev->mtu = new_mtu;
1836 return 0;
1837 }
1838
e07b1aa8 1839 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 1840 sky2_write32(hw, B0_IMSK, 0);
1841
018d1c66 1842 dev->trans_start = jiffies; /* prevent tx timeout */
1843 netif_stop_queue(dev);
1844 netif_poll_disable(hw->dev[0]);
1845
e07b1aa8
SH		 1846 synchronize_irq(hw->pdev->irq);
1847
6b1a3aef 1848 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1849 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1850 sky2_rx_stop(sky2);
1851 sky2_rx_clean(sky2);
cd28ab6a
SH		 1852
1853 dev->mtu = new_mtu;
14d0263f 1854
6b1a3aef 1855 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1856 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1857
1858 if (dev->mtu > ETH_DATA_LEN)
1859 mode |= GM_SMOD_JUMBO_ENA;
1860
1861 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1862
6b1a3aef 1863 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1864
6b1a3aef 1865 err = sky2_rx_start(sky2);
e07b1aa8 1866 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1867
1b537565
SH		 1868 if (err)
1869 dev_close(dev);
1870 else {
1871 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1872
1873 netif_poll_enable(hw->dev[0]);
1874 netif_wake_queue(dev);
1875 }
1876
cd28ab6a
SH		 1877 return err;
1878}
1879
14d0263f
SH		 1880/* For small just reuse existing skb for next receive */
1881static struct sk_buff *receive_copy(struct sky2_port *sky2,
1882 const struct rx_ring_info *re,
1883 unsigned length)
1884{
1885 struct sk_buff *skb;
1886
1887 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1888 if (likely(skb)) {
1889 skb_reserve(skb, 2);
1890 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1891 length, PCI_DMA_FROMDEVICE);
1892 memcpy(skb->data, re->skb->data, length);
1893 skb->ip_summed = re->skb->ip_summed;
1894 skb->csum = re->skb->csum;
1895 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1896 length, PCI_DMA_FROMDEVICE);
1897 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 1898 skb_put(skb, length);
14d0263f
SH		 1899 }
1900 return skb;
1901}
1902
1903/* Adjust length of skb with fragments to match received data */
1904static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1905 unsigned int length)
1906{
1907 int i, num_frags;
1908 unsigned int size;
1909
1910 /* put header into skb */
1911 size = min(length, hdr_space);
1912 skb->tail += size;
1913 skb->len += size;
1914 length -= size;
1915
1916 num_frags = skb_shinfo(skb)->nr_frags;
1917 for (i = 0; i < num_frags; i++) {
1918 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1919
1920 if (length == 0) {
1921 /* don't need this page */
1922 __free_page(frag->page);
1923 --skb_shinfo(skb)->nr_frags;
1924 } else {
1925 size = min(length, (unsigned) PAGE_SIZE);
1926
1927 frag->size = size;
1928 skb->data_len += size;
1929 skb->truesize += size;
1930 skb->len += size;
1931 length -= size;
1932 }
1933 }
1934}
1935
1936/* Normal packet - take skb from ring element and put in a new one */
1937static struct sk_buff *receive_new(struct sky2_port *sky2,
1938 struct rx_ring_info *re,
1939 unsigned int length)
1940{
1941 struct sk_buff *skb, *nskb;
1942 unsigned hdr_space = sky2->rx_data_size;
1943
1944 pr_debug(PFX "receive new length=%d\n", length);
1945
1946 /* Don't be tricky about reusing pages (yet) */
1947 nskb = sky2_rx_alloc(sky2);
1948 if (unlikely(!nskb))
1949 return NULL;
1950
1951 skb = re->skb;
1952 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1953
1954 prefetch(skb->data);
1955 re->skb = nskb;
1956 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
1957
1958 if (skb_shinfo(skb)->nr_frags)
1959 skb_put_frags(skb, hdr_space, length);
1960 else
489b10c1 1961 skb_put(skb, length);
14d0263f
SH		 1962 return skb;
1963}
1964
cd28ab6a
SH		 1965/*
1966 * Receive one packet.
d571b694 1967 * For larger packets, get new buffer.
cd28ab6a 1968 */
497d7c86 1969static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 1970 u16 length, u32 status)
1971{
497d7c86 1972 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 1973 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1974 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1975
1976 if (unlikely(netif_msg_rx_status(sky2)))
1977 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 1978 dev->name, sky2->rx_next, status, length);
cd28ab6a 1979
793b883e 1980 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1981 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1982
42eeea01 1983 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1984 goto error;
1985
42eeea01 1986 if (!(status & GMR_FS_RX_OK))
1987 goto resubmit;
1988
497d7c86 1989 if (length > dev->mtu + ETH_HLEN)
6e15b712
SH		 1990 goto oversize;
1991
14d0263f
SH		 1992 if (length < copybreak)
1993 skb = receive_copy(sky2, re, length);
1994 else
1995 skb = receive_new(sky2, re, length);
793b883e 1996resubmit:
14d0263f 1997 sky2_rx_submit(sky2, re);
79e57d32 1998
cd28ab6a
SH		 1999 return skb;
2000
6e15b712
SH		 2001oversize:
2002 ++sky2->net_stats.rx_over_errors;
2003 goto resubmit;
2004
cd28ab6a 2005error:
6e15b712 2006 ++sky2->net_stats.rx_errors;
b6d77734
SH		 2007 if (status & GMR_FS_RX_FF_OV) {
2008 sky2->net_stats.rx_fifo_errors++;
2009 goto resubmit;
2010 }
6e15b712 2011
3be92a70 2012 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2013 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2014 dev->name, status, length);
793b883e
SH		 2015
2016 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2017 sky2->net_stats.rx_length_errors++;
2018 if (status & GMR_FS_FRAGMENT)
2019 sky2->net_stats.rx_frame_errors++;
2020 if (status & GMR_FS_CRC_ERR)
2021 sky2->net_stats.rx_crc_errors++;
79e57d32 2022
793b883e 2023 goto resubmit;
cd28ab6a
SH		 2024}
2025
e07b1aa8
SH		 2026/* Transmit complete */
2027static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2028{
e07b1aa8 2029 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2030
e07b1aa8 2031 if (netif_running(dev)) {
2bb8c262 2032 netif_tx_lock(dev);
e07b1aa8 2033 sky2_tx_complete(sky2, last);
2bb8c262 2034 netif_tx_unlock(dev);
2224795d 2035 }
cd28ab6a
SH		 2036}
2037
e07b1aa8
SH		 2038/* Process status response ring */
2039static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2040{
22e11703 2041 struct sky2_port *sky2;
e07b1aa8 2042 int work_done = 0;
22e11703 2043 unsigned buf_write[2] = { 0, 0 };
e71ebd73 2044 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2045
af2a58ac 2046 rmb();
bea86103 2047
e71ebd73 2048 while (hw->st_idx != hwidx) {
13210ce5 2049 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2050 struct net_device *dev;
cd28ab6a 2051 struct sk_buff *skb;
cd28ab6a
SH		 2052 u32 status;
2053 u16 length;
2054
cb5d9547 2055 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2056
e71ebd73
SH		 2057 BUG_ON(le->link >= 2);
2058 dev = hw->dev[le->link];
13210ce5 2059
2060 sky2 = netdev_priv(dev);
f65b138c
SH		 2061 length = le16_to_cpu(le->length);
2062 status = le32_to_cpu(le->status);
cd28ab6a 2063
e71ebd73 2064 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2065 case OP_RXSTAT:
497d7c86 2066 skb = sky2_receive(dev, length, status);
d1f13708 2067 if (!skb)
5df79111 2068 goto force_update;
13210ce5 2069
13210ce5 2070 skb->protocol = eth_type_trans(skb, dev);
2071 dev->last_rx = jiffies;
2072
d1f13708 2073#ifdef SKY2_VLAN_TAG_USED
2074 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2075 vlan_hwaccel_receive_skb(skb,
2076 sky2->vlgrp,
2077 be16_to_cpu(sky2->rx_tag));
2078 } else
2079#endif
cd28ab6a 2080 netif_receive_skb(skb);
13210ce5 2081
22e11703
SH		 2082 /* Update receiver after 16 frames */
2083 if (++buf_write[le->link] == RX_BUF_WRITE) {
5df79111
SH		 2084force_update:
2085 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
22e11703
SH		 2086 buf_write[le->link] = 0;
2087 }
2088
2089 /* Stop after net poll weight */
13210ce5 2090 if (++work_done >= to_do)
2091 goto exit_loop;
cd28ab6a
SH		 2092 break;
2093
d1f13708 2094#ifdef SKY2_VLAN_TAG_USED
2095 case OP_RXVLAN:
2096 sky2->rx_tag = length;
2097 break;
2098
2099 case OP_RXCHKSVLAN:
2100 sky2->rx_tag = length;
2101 /* fall through */
2102#endif
cd28ab6a 2103 case OP_RXCHKS:
d11c13e7 2104 skb = sky2->rx_ring[sky2->rx_next].skb;
84fa7933 2105 skb->ip_summed = CHECKSUM_COMPLETE;
f65b138c 2106 skb->csum = status & 0xffff;
cd28ab6a
SH		 2107 break;
2108
2109 case OP_TXINDEXLE:
13b97b74 2110 /* TX index reports status for both ports */
f55925d7
SH		 2111 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2112 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2113 if (hw->dev[1])
2114 sky2_tx_done(hw->dev[1],
2115 ((status >> 24) & 0xff)
2116 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2117 break;
2118
cd28ab6a
SH		 2119 default:
2120 if (net_ratelimit())
793b883e 2121 printk(KERN_WARNING PFX
e71ebd73
SH		 2122 "unknown status opcode 0x%x\n", le->opcode);
2123 goto exit_loop;
cd28ab6a 2124 }
13210ce5 2125 }
cd28ab6a 2126
fe2a24df
SH		 2127 /* Fully processed status ring so clear irq */
2128 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2129
13210ce5 2130exit_loop:
22e11703
SH		 2131 if (buf_write[0]) {
2132 sky2 = netdev_priv(hw->dev[0]);
2133 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2134 }
2135
2136 if (buf_write[1]) {
2137 sky2 = netdev_priv(hw->dev[1]);
2138 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2139 }
2140
e07b1aa8 2141 return work_done;
cd28ab6a
SH		 2142}
2143
2144static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2145{
2146 struct net_device *dev = hw->dev[port];
2147
3be92a70
SH		 2148 if (net_ratelimit())
2149 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2150 dev->name, status);
cd28ab6a
SH		 2151
2152 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2153 if (net_ratelimit())
2154 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2155 dev->name);
cd28ab6a
SH		 2156 /* Clear IRQ */
2157 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2158 }
2159
2160 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2161 if (net_ratelimit())
2162 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2163 dev->name);
cd28ab6a
SH		 2164
2165 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2166 }
2167
2168 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2169 if (net_ratelimit())
2170 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2171 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2172 }
2173
2174 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2175 if (net_ratelimit())
2176 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2177 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2178 }
2179
2180 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2181 if (net_ratelimit())
2182 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2183 dev->name);
cd28ab6a
SH		 2184 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2185 }
2186}
2187
2188static void sky2_hw_intr(struct sky2_hw *hw)
2189{
2190 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2191
793b883e 2192 if (status & Y2_IS_TIST_OV)
cd28ab6a 2193 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2194
2195 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2196 u16 pci_err;
2197
56a645cc 2198 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2199 if (net_ratelimit())
2200 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2201 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2202
2203 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2204 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2205 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2206 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2207 }
2208
2209 if (status & Y2_IS_PCI_EXP) {
d571b694 2210 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2211 u32 pex_err;
2212
7bd656d1 2213 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2214
3be92a70
SH		 2215 if (net_ratelimit())
2216 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2217 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2218
2219 /* clear the interrupt */
2220 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2221 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2222 0xffffffffUL);
cd28ab6a
SH		 2223 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2224
7bd656d1 2225 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2226 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2227 hwmsk &= ~Y2_IS_PCI_EXP;
2228 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2229 }
2230 }
2231
2232 if (status & Y2_HWE_L1_MASK)
2233 sky2_hw_error(hw, 0, status);
2234 status >>= 8;
2235 if (status & Y2_HWE_L1_MASK)
2236 sky2_hw_error(hw, 1, status);
2237}
2238
2239static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2240{
2241 struct net_device *dev = hw->dev[port];
2242 struct sky2_port *sky2 = netdev_priv(dev);
2243 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2244
2245 if (netif_msg_intr(sky2))
2246 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2247 dev->name, status);
2248
2249 if (status & GM_IS_RX_FF_OR) {
2250 ++sky2->net_stats.rx_fifo_errors;
2251 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2252 }
2253
2254 if (status & GM_IS_TX_FF_UR) {
2255 ++sky2->net_stats.tx_fifo_errors;
2256 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2257 }
cd28ab6a
SH		 2258}
2259
d257924e
SH		 2260/* This should never happen it is a fatal situation */
2261static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2262 const char *rxtx, u32 mask)
2263{
2264 struct net_device *dev = hw->dev[port];
2265 struct sky2_port *sky2 = netdev_priv(dev);
2266 u32 imask;
2267
2268 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2269 dev ? dev->name : "<not registered>", rxtx);
2270
2271 imask = sky2_read32(hw, B0_IMSK);
2272 imask &= ~mask;
2273 sky2_write32(hw, B0_IMSK, imask);
2274
2275 if (dev) {
2276 spin_lock(&sky2->phy_lock);
2277 sky2_link_down(sky2);
2278 spin_unlock(&sky2->phy_lock);
2279 }
2280}
cd28ab6a 2281
d27ed387
SH		 2282/* If idle then force a fake soft NAPI poll once a second
2283 * to work around cases where sharing an edge triggered interrupt.
2284 */
eb35cf60
SH		 2285static inline void sky2_idle_start(struct sky2_hw *hw)
2286{
2287 if (idle_timeout > 0)
2288 mod_timer(&hw->idle_timer,
2289 jiffies + msecs_to_jiffies(idle_timeout));
2290}
2291
d27ed387
SH		 2292static void sky2_idle(unsigned long arg)
2293{
01bd7564
SH		 2294 struct sky2_hw *hw = (struct sky2_hw *) arg;
2295 struct net_device *dev = hw->dev[0];
d27ed387 2296
d27ed387
SH		 2297 if (__netif_rx_schedule_prep(dev))
2298 __netif_rx_schedule(dev);
01bd7564
SH		 2299
2300 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2301}
2302
2303
e07b1aa8 2304static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2305{
e07b1aa8
SH		 2306 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2307 int work_limit = min(dev0->quota, *budget);
2308 int work_done = 0;
fb2690a9 2309 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2310
1e5f1283
SH		 2311 if (status & Y2_IS_HW_ERR)
2312 sky2_hw_intr(hw);
d257924e 2313
1e5f1283
SH		 2314 if (status & Y2_IS_IRQ_PHY1)
2315 sky2_phy_intr(hw, 0);
cd28ab6a 2316
1e5f1283
SH		 2317 if (status & Y2_IS_IRQ_PHY2)
2318 sky2_phy_intr(hw, 1);
cd28ab6a 2319
1e5f1283
SH		 2320 if (status & Y2_IS_IRQ_MAC1)
2321 sky2_mac_intr(hw, 0);
cd28ab6a 2322
1e5f1283
SH		 2323 if (status & Y2_IS_IRQ_MAC2)
2324 sky2_mac_intr(hw, 1);
cd28ab6a 2325
1e5f1283
SH		 2326 if (status & Y2_IS_CHK_RX1)
2327 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2328
1e5f1283
SH		 2329 if (status & Y2_IS_CHK_RX2)
2330 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2331
1e5f1283
SH		 2332 if (status & Y2_IS_CHK_TXA1)
2333 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2334
1e5f1283
SH		 2335 if (status & Y2_IS_CHK_TXA2)
2336 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2337
1e5f1283 2338 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2339 if (work_done < work_limit) {
2340 netif_rx_complete(dev0);
86fba634 2341
fe2a24df
SH		 2342 sky2_read32(hw, B0_Y2_SP_LISR);
2343 return 0;
2344 } else {
2345 *budget -= work_done;
2346 dev0->quota -= work_done;
1e5f1283 2347 return 1;
fe2a24df 2348 }
e07b1aa8
SH		 2349}
2350
7d12e780 2351static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2352{
2353 struct sky2_hw *hw = dev_id;
2354 struct net_device *dev0 = hw->dev[0];
2355 u32 status;
2356
2357 /* Reading this mask interrupts as side effect */
2358 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2359 if (status == 0 || status == ~0)
2360 return IRQ_NONE;
793b883e 2361
e07b1aa8
SH		 2362 prefetch(&hw->st_le[hw->st_idx]);
2363 if (likely(__netif_rx_schedule_prep(dev0)))
2364 __netif_rx_schedule(dev0);
793b883e 2365
cd28ab6a
SH		 2366 return IRQ_HANDLED;
2367}
2368
2369#ifdef CONFIG_NET_POLL_CONTROLLER
2370static void sky2_netpoll(struct net_device *dev)
2371{
2372 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2373 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2374
88d11360
SH		 2375 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2376 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2377}
2378#endif
2379
2380/* Chip internal frequency for clock calculations */
fb17358f 2381static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2382{
793b883e 2383 switch (hw->chip_id) {
cd28ab6a 2384 case CHIP_ID_YUKON_EC:
5a5b1ea0 2385 case CHIP_ID_YUKON_EC_U:
fb17358f 2386 return 125; /* 125 Mhz */
cd28ab6a 2387 case CHIP_ID_YUKON_FE:
fb17358f 2388 return 100; /* 100 Mhz */
793b883e 2389 default: /* YUKON_XL */
fb17358f 2390 return 156; /* 156 Mhz */
cd28ab6a
SH		 2391 }
2392}
2393
fb17358f 2394static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2395{
fb17358f 2396 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2397}
2398
fb17358f 2399static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2400{
fb17358f 2401 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2402}
2403
fb17358f 2404
59139528 2405static int sky2_reset(struct sky2_hw *hw)
cd28ab6a 2406{
cd28ab6a 2407 u16 status;
b89165f2 2408 u8 t8;
56a645cc 2409 int i;
cd28ab6a 2410
cd28ab6a 2411 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2412
cd28ab6a
SH		 2413 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2414 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2415 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2416 pci_name(hw->pdev), hw->chip_id);
2417 return -EOPNOTSUPP;
2418 }
2419
290d4de5
SH		 2420 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2421
2422 /* This rev is really old, and requires untested workarounds */
2423 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2424 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2425 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2426 hw->chip_id, hw->chip_rev);
2427 return -EOPNOTSUPP;
2428 }
2429
cd28ab6a
SH		 2430 /* disable ASF */
2431 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2432 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2433 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2434 }
2435
2436 /* do a SW reset */
2437 sky2_write8(hw, B0_CTST, CS_RST_SET);
2438 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2439
2440 /* clear PCI errors, if any */
56a645cc 2441 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2442
cd28ab6a 2443 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2444 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2445
cd28ab6a
SH		 2446
2447 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2448
2449 /* clear any PEX errors */
7bd656d1
SH		 2450 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2451 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2452
cd28ab6a 2453
b89165f2 2454 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
cd28ab6a
SH		 2455 hw->ports = 1;
2456 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2457 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2458 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2459 ++hw->ports;
2460 }
cd28ab6a 2461
5afa0a9c 2462 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2463
2464 for (i = 0; i < hw->ports; i++) {
2465 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2466 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2467 }
2468
2469 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2470
793b883e
SH		 2471 /* Clear I2C IRQ noise */
2472 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2473
2474 /* turn off hardware timer (unused) */
2475 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2476 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2477
cd28ab6a
SH		 2478 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2479
69634ee7
SH		 2480 /* Turn off descriptor polling */
2481 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2482
2483 /* Turn off receive timestamp */
2484 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2485 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2486
2487 /* enable the Tx Arbiters */
2488 for (i = 0; i < hw->ports; i++)
2489 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2490
2491 /* Initialize ram interface */
2492 for (i = 0; i < hw->ports; i++) {
793b883e 2493 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2494
2495 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2496 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2497 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2498 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2499 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2500 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2501 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2502 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2503 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2504 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2505 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2506 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2507 }
2508
7bd656d1 2509 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2510
cd28ab6a 2511 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2512 sky2_gmac_reset(hw, i);
cd28ab6a 2513
cd28ab6a
SH		 2514 memset(hw->st_le, 0, STATUS_LE_BYTES);
2515 hw->st_idx = 0;
2516
2517 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2518 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2519
2520 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2521 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2522
2523 /* Set the list last index */
793b883e 2524 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2525
290d4de5
SH		 2526 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2527 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2528
290d4de5
SH		 2529 /* set Status-FIFO ISR watermark */
2530 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2531 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2532 else
2533 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2534
290d4de5 2535 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2536 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2537 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2538
793b883e 2539 /* enable status unit */
cd28ab6a
SH		 2540 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2541
2542 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2543 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2544 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2545
2546 return 0;
2547}
2548
28bd181a 2549static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2550{
b89165f2
SH		 2551 if (sky2_is_copper(hw)) {
2552 u32 modes = SUPPORTED_10baseT_Half
2553 | SUPPORTED_10baseT_Full
2554 | SUPPORTED_100baseT_Half
2555 | SUPPORTED_100baseT_Full
2556 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2557
2558 if (hw->chip_id != CHIP_ID_YUKON_FE)
2559 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2560 | SUPPORTED_1000baseT_Full;
2561 return modes;
cd28ab6a 2562 } else
b89165f2
SH		 2563 return SUPPORTED_1000baseT_Half
2564 | SUPPORTED_1000baseT_Full
2565 | SUPPORTED_Autoneg
2566 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2567}
2568
793b883e 2569static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2570{
2571 struct sky2_port *sky2 = netdev_priv(dev);
2572 struct sky2_hw *hw = sky2->hw;
2573
2574 ecmd->transceiver = XCVR_INTERNAL;
2575 ecmd->supported = sky2_supported_modes(hw);
2576 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2577 if (sky2_is_copper(hw)) {
cd28ab6a 2578 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2579 | SUPPORTED_10baseT_Full
2580 | SUPPORTED_100baseT_Half
2581 | SUPPORTED_100baseT_Full
2582 | SUPPORTED_1000baseT_Half
2583 | SUPPORTED_1000baseT_Full
2584 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2585 ecmd->port = PORT_TP;
b89165f2
SH		 2586 ecmd->speed = sky2->speed;
2587 } else {
2588 ecmd->speed = SPEED_1000;
cd28ab6a 2589 ecmd->port = PORT_FIBRE;
b89165f2 2590 }
cd28ab6a
SH		 2591
2592 ecmd->advertising = sky2->advertising;
2593 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2594 ecmd->duplex = sky2->duplex;
2595 return 0;
2596}
2597
2598static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2599{
2600 struct sky2_port *sky2 = netdev_priv(dev);
2601 const struct sky2_hw *hw = sky2->hw;
2602 u32 supported = sky2_supported_modes(hw);
2603
2604 if (ecmd->autoneg == AUTONEG_ENABLE) {
2605 ecmd->advertising = supported;
2606 sky2->duplex = -1;
2607 sky2->speed = -1;
2608 } else {
2609 u32 setting;
2610
793b883e 2611 switch (ecmd->speed) {
cd28ab6a
SH		 2612 case SPEED_1000:
2613 if (ecmd->duplex == DUPLEX_FULL)
2614 setting = SUPPORTED_1000baseT_Full;
2615 else if (ecmd->duplex == DUPLEX_HALF)
2616 setting = SUPPORTED_1000baseT_Half;
2617 else
2618 return -EINVAL;
2619 break;
2620 case SPEED_100:
2621 if (ecmd->duplex == DUPLEX_FULL)
2622 setting = SUPPORTED_100baseT_Full;
2623 else if (ecmd->duplex == DUPLEX_HALF)
2624 setting = SUPPORTED_100baseT_Half;
2625 else
2626 return -EINVAL;
2627 break;
2628
2629 case SPEED_10:
2630 if (ecmd->duplex == DUPLEX_FULL)
2631 setting = SUPPORTED_10baseT_Full;
2632 else if (ecmd->duplex == DUPLEX_HALF)
2633 setting = SUPPORTED_10baseT_Half;
2634 else
2635 return -EINVAL;
2636 break;
2637 default:
2638 return -EINVAL;
2639 }
2640
2641 if ((setting & supported) == 0)
2642 return -EINVAL;
2643
2644 sky2->speed = ecmd->speed;
2645 sky2->duplex = ecmd->duplex;
2646 }
2647
2648 sky2->autoneg = ecmd->autoneg;
2649 sky2->advertising = ecmd->advertising;
2650
1b537565
SH		 2651 if (netif_running(dev))
2652 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2653
2654 return 0;
2655}
2656
2657static void sky2_get_drvinfo(struct net_device *dev,
2658 struct ethtool_drvinfo *info)
2659{
2660 struct sky2_port *sky2 = netdev_priv(dev);
2661
2662 strcpy(info->driver, DRV_NAME);
2663 strcpy(info->version, DRV_VERSION);
2664 strcpy(info->fw_version, "N/A");
2665 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2666}
2667
2668static const struct sky2_stat {
793b883e
SH		 2669 char name[ETH_GSTRING_LEN];
2670 u16 offset;
cd28ab6a
SH		 2671} sky2_stats[] = {
2672 { "tx_bytes", GM_TXO_OK_HI },
2673 { "rx_bytes", GM_RXO_OK_HI },
2674 { "tx_broadcast", GM_TXF_BC_OK },
2675 { "rx_broadcast", GM_RXF_BC_OK },
2676 { "tx_multicast", GM_TXF_MC_OK },
2677 { "rx_multicast", GM_RXF_MC_OK },
2678 { "tx_unicast", GM_TXF_UC_OK },
2679 { "rx_unicast", GM_RXF_UC_OK },
2680 { "tx_mac_pause", GM_TXF_MPAUSE },
2681 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2682 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2683 { "late_collision",GM_TXF_LAT_COL },
2684 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2685 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2686 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2687
d2604540 2688 { "rx_short", GM_RXF_SHT },
cd28ab6a 2689 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2690 { "rx_64_byte_packets", GM_RXF_64B },
2691 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2692 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2693 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2694 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2695 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2696 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2697 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2698 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2699 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2700 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2701
2702 { "tx_64_byte_packets", GM_TXF_64B },
2703 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2704 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2705 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2706 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2707 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2708 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2709 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2710};
2711
cd28ab6a
SH		 2712static u32 sky2_get_rx_csum(struct net_device *dev)
2713{
2714 struct sky2_port *sky2 = netdev_priv(dev);
2715
2716 return sky2->rx_csum;
2717}
2718
2719static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2720{
2721 struct sky2_port *sky2 = netdev_priv(dev);
2722
2723 sky2->rx_csum = data;
793b883e 2724
cd28ab6a
SH		 2725 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2726 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2727
2728 return 0;
2729}
2730
2731static u32 sky2_get_msglevel(struct net_device *netdev)
2732{
2733 struct sky2_port *sky2 = netdev_priv(netdev);
2734 return sky2->msg_enable;
2735}
2736
9a7ae0a9
SH		 2737static int sky2_nway_reset(struct net_device *dev)
2738{
2739 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2740
16ad91e1 2741 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2742 return -EINVAL;
2743
1b537565 2744 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2745
2746 return 0;
2747}
2748
793b883e 2749static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2750{
2751 struct sky2_hw *hw = sky2->hw;
2752 unsigned port = sky2->port;
2753 int i;
2754
2755 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2756 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2757 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2758 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2759
793b883e 2760 for (i = 2; i < count; i++)
cd28ab6a
SH		 2761 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2762}
2763
cd28ab6a
SH		 2764static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2765{
2766 struct sky2_port *sky2 = netdev_priv(netdev);
2767 sky2->msg_enable = value;
2768}
2769
2770static int sky2_get_stats_count(struct net_device *dev)
2771{
2772 return ARRAY_SIZE(sky2_stats);
2773}
2774
2775static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2776 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2777{
2778 struct sky2_port *sky2 = netdev_priv(dev);
2779
793b883e 2780 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2781}
2782
793b883e 2783static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2784{
2785 int i;
2786
2787 switch (stringset) {
2788 case ETH_SS_STATS:
2789 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2790 memcpy(data + i * ETH_GSTRING_LEN,
2791 sky2_stats[i].name, ETH_GSTRING_LEN);
2792 break;
2793 }
2794}
2795
2796/* Use hardware MIB variables for critical path statistics and
2797 * transmit feedback not reported at interrupt.
2798 * Other errors are accounted for in interrupt handler.
2799 */
2800static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2801{
2802 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2803 u64 data[13];
cd28ab6a 2804
793b883e 2805 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2806
2807 sky2->net_stats.tx_bytes = data[0];
2808 sky2->net_stats.rx_bytes = data[1];
2809 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2810 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
050ff180 2811 sky2->net_stats.multicast = data[3] + data[5];
cd28ab6a
SH		 2812 sky2->net_stats.collisions = data[10];
2813 sky2->net_stats.tx_aborted_errors = data[12];
2814
2815 return &sky2->net_stats;
2816}
2817
2818static int sky2_set_mac_address(struct net_device *dev, void *p)
2819{
2820 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2821 struct sky2_hw *hw = sky2->hw;
2822 unsigned port = sky2->port;
2823 const struct sockaddr *addr = p;
cd28ab6a
SH		 2824
2825 if (!is_valid_ether_addr(addr->sa_data))
2826 return -EADDRNOTAVAIL;
2827
cd28ab6a 2828 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2829 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2830 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2831 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2832 dev->dev_addr, ETH_ALEN);
1b537565 2833
a8ab1ec0
SH		 2834 /* virtual address for data */
2835 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2836
2837 /* physical address: used for pause frames */
2838 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2839
2840 return 0;
cd28ab6a
SH		 2841}
2842
a052b52f
SH		 2843static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
2844{
2845 u32 bit;
2846
2847 bit = ether_crc(ETH_ALEN, addr) & 63;
2848 filter[bit >> 3] |= 1 << (bit & 7);
2849}
2850
cd28ab6a
SH		 2851static void sky2_set_multicast(struct net_device *dev)
2852{
2853 struct sky2_port *sky2 = netdev_priv(dev);
2854 struct sky2_hw *hw = sky2->hw;
2855 unsigned port = sky2->port;
2856 struct dev_mc_list *list = dev->mc_list;
2857 u16 reg;
2858 u8 filter[8];
a052b52f
SH		 2859 int rx_pause;
2860 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 2861
a052b52f 2862 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 2863 memset(filter, 0, sizeof(filter));
2864
2865 reg = gma_read16(hw, port, GM_RX_CTRL);
2866 reg |= GM_RXCR_UCF_ENA;
2867
d571b694 2868 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2869 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 2870 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 2871 memset(filter, 0xff, sizeof(filter));
a052b52f 2872 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 2873 reg &= ~GM_RXCR_MCF_ENA;
2874 else {
2875 int i;
2876 reg |= GM_RXCR_MCF_ENA;
2877
a052b52f
SH		 2878 if (rx_pause)
2879 sky2_add_filter(filter, pause_mc_addr);
2880
2881 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2882 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 2883 }
2884
cd28ab6a 2885 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2886 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2887 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2888 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2889 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2890 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2891 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2892 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2893
2894 gma_write16(hw, port, GM_RX_CTRL, reg);
2895}
2896
2897/* Can have one global because blinking is controlled by
2898 * ethtool and that is always under RTNL mutex
2899 */
91c86df5 2900static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2901{
793b883e
SH		 2902 u16 pg;
2903
793b883e
SH		 2904 switch (hw->chip_id) {
2905 case CHIP_ID_YUKON_XL:
2906 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2907 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2908 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2909 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2910 PHY_M_LEDC_INIT_CTRL(7) |
2911 PHY_M_LEDC_STA1_CTRL(7) |
2912 PHY_M_LEDC_STA0_CTRL(7))
2913 : 0);
2914
2915 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2916 break;
2917
2918 default:
2919 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2920 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2921 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2922 PHY_M_LED_MO_10(MO_LED_ON) |
2923 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2924 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2925 PHY_M_LED_MO_RX(MO_LED_ON)
2926 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2927 PHY_M_LED_MO_10(MO_LED_OFF) |
2928 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2929 PHY_M_LED_MO_1000(MO_LED_OFF) |
2930 PHY_M_LED_MO_RX(MO_LED_OFF));
2931
793b883e 2932 }
cd28ab6a
SH		 2933}
2934
2935/* blink LED's for finding board */
2936static int sky2_phys_id(struct net_device *dev, u32 data)
2937{
2938 struct sky2_port *sky2 = netdev_priv(dev);
2939 struct sky2_hw *hw = sky2->hw;
2940 unsigned port = sky2->port;
793b883e 2941 u16 ledctrl, ledover = 0;
cd28ab6a 2942 long ms;
91c86df5 2943 int interrupted;
cd28ab6a
SH		 2944 int onoff = 1;
2945
793b883e 2946 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2947 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2948 else
2949 ms = data * 1000;
2950
2951 /* save initial values */
e07b1aa8 2952 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2953 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2954 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2955 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2956 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2957 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2958 } else {
2959 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2960 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2961 }
cd28ab6a 2962
91c86df5
SH		 2963 interrupted = 0;
2964 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2965 sky2_led(hw, port, onoff);
2966 onoff = !onoff;
2967
e07b1aa8 2968 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2969 interrupted = msleep_interruptible(250);
e07b1aa8 2970 spin_lock_bh(&sky2->phy_lock);
91c86df5 2971
cd28ab6a
SH		 2972 ms -= 250;
2973 }
2974
2975 /* resume regularly scheduled programming */
793b883e
SH		 2976 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2977 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2978 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2979 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2980 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2981 } else {
2982 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2983 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2984 }
e07b1aa8 2985 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2986
2987 return 0;
2988}
2989
2990static void sky2_get_pauseparam(struct net_device *dev,
2991 struct ethtool_pauseparam *ecmd)
2992{
2993 struct sky2_port *sky2 = netdev_priv(dev);
2994
16ad91e1
SH		 2995 switch (sky2->flow_mode) {
2996 case FC_NONE:
2997 ecmd->tx_pause = ecmd->rx_pause = 0;
2998 break;
2999 case FC_TX:
3000 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3001 break;
3002 case FC_RX:
3003 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3004 break;
3005 case FC_BOTH:
3006 ecmd->tx_pause = ecmd->rx_pause = 1;
3007 }
3008
cd28ab6a
SH		 3009 ecmd->autoneg = sky2->autoneg;
3010}
3011
3012static int sky2_set_pauseparam(struct net_device *dev,
3013 struct ethtool_pauseparam *ecmd)
3014{
3015 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3016
3017 sky2->autoneg = ecmd->autoneg;
16ad91e1 3018 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3019
16ad91e1
SH		 3020 if (netif_running(dev))
3021 sky2_phy_reinit(sky2);
cd28ab6a 3022
2eaba1a2 3023 return 0;
cd28ab6a
SH		 3024}
3025
fb17358f
SH		 3026static int sky2_get_coalesce(struct net_device *dev,
3027 struct ethtool_coalesce *ecmd)
3028{
3029 struct sky2_port *sky2 = netdev_priv(dev);
3030 struct sky2_hw *hw = sky2->hw;
3031
3032 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3033 ecmd->tx_coalesce_usecs = 0;
3034 else {
3035 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3036 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3037 }
3038 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3039
3040 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3041 ecmd->rx_coalesce_usecs = 0;
3042 else {
3043 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3044 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3045 }
3046 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3047
3048 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3049 ecmd->rx_coalesce_usecs_irq = 0;
3050 else {
3051 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3052 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3053 }
3054
3055 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3056
3057 return 0;
3058}
3059
3060/* Note: this affect both ports */
3061static int sky2_set_coalesce(struct net_device *dev,
3062 struct ethtool_coalesce *ecmd)
3063{
3064 struct sky2_port *sky2 = netdev_priv(dev);
3065 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3066 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3067
77b3d6a2
SH		 3068 if (ecmd->tx_coalesce_usecs > tmax ||
3069 ecmd->rx_coalesce_usecs > tmax ||
3070 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3071 return -EINVAL;
3072
ff81fbbe 3073 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3074 return -EINVAL;
ff81fbbe 3075 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3076 return -EINVAL;
ff81fbbe 3077 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3078 return -EINVAL;
3079
3080 if (ecmd->tx_coalesce_usecs == 0)
3081 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3082 else {
3083 sky2_write32(hw, STAT_TX_TIMER_INI,
3084 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3085 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3086 }
3087 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3088
3089 if (ecmd->rx_coalesce_usecs == 0)
3090 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3091 else {
3092 sky2_write32(hw, STAT_LEV_TIMER_INI,
3093 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3094 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3095 }
3096 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3097
3098 if (ecmd->rx_coalesce_usecs_irq == 0)
3099 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3100 else {
d28d4870 3101 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3102 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3103 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3104 }
3105 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3106 return 0;
3107}
3108
793b883e
SH		 3109static void sky2_get_ringparam(struct net_device *dev,
3110 struct ethtool_ringparam *ering)
3111{
3112 struct sky2_port *sky2 = netdev_priv(dev);
3113
3114 ering->rx_max_pending = RX_MAX_PENDING;
3115 ering->rx_mini_max_pending = 0;
3116 ering->rx_jumbo_max_pending = 0;
3117 ering->tx_max_pending = TX_RING_SIZE - 1;
3118
3119 ering->rx_pending = sky2->rx_pending;
3120 ering->rx_mini_pending = 0;
3121 ering->rx_jumbo_pending = 0;
3122 ering->tx_pending = sky2->tx_pending;
3123}
3124
3125static int sky2_set_ringparam(struct net_device *dev,
3126 struct ethtool_ringparam *ering)
3127{
3128 struct sky2_port *sky2 = netdev_priv(dev);
3129 int err = 0;
3130
3131 if (ering->rx_pending > RX_MAX_PENDING ||
3132 ering->rx_pending < 8 ||
3133 ering->tx_pending < MAX_SKB_TX_LE ||
3134 ering->tx_pending > TX_RING_SIZE - 1)
3135 return -EINVAL;
3136
3137 if (netif_running(dev))
3138 sky2_down(dev);
3139
3140 sky2->rx_pending = ering->rx_pending;
3141 sky2->tx_pending = ering->tx_pending;
3142
1b537565 3143 if (netif_running(dev)) {
793b883e 3144 err = sky2_up(dev);
1b537565
SH		 3145 if (err)
3146 dev_close(dev);
6ed995bb
SH		 3147 else
3148 sky2_set_multicast(dev);
1b537565 3149 }
793b883e
SH		 3150
3151 return err;
3152}
3153
793b883e
SH		 3154static int sky2_get_regs_len(struct net_device *dev)
3155{
6e4cbb34 3156 return 0x4000;
793b883e
SH		 3157}
3158
3159/*
3160 * Returns copy of control register region
6e4cbb34 3161 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3162 */
3163static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3164 void *p)
3165{
3166 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3167 const void __iomem *io = sky2->hw->regs;
793b883e 3168
6e4cbb34 3169 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3170 regs->version = 1;
6e4cbb34 3171 memset(p, 0, regs->len);
793b883e 3172
6e4cbb34
SH		 3173 memcpy_fromio(p, io, B3_RAM_ADDR);
3174
3175 memcpy_fromio(p + B3_RI_WTO_R1,
3176 io + B3_RI_WTO_R1,
3177 regs->len - B3_RI_WTO_R1);
793b883e 3178}
cd28ab6a 3179
7282d491 3180static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3181 .get_settings = sky2_get_settings,
3182 .set_settings = sky2_set_settings,
3183 .get_drvinfo = sky2_get_drvinfo,
3184 .get_msglevel = sky2_get_msglevel,
3185 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3186 .nway_reset = sky2_nway_reset,
793b883e
SH		 3187 .get_regs_len = sky2_get_regs_len,
3188 .get_regs = sky2_get_regs,
3189 .get_link = ethtool_op_get_link,
3190 .get_sg = ethtool_op_get_sg,
3191 .set_sg = ethtool_op_set_sg,
3192 .get_tx_csum = ethtool_op_get_tx_csum,
3193 .set_tx_csum = ethtool_op_set_tx_csum,
3194 .get_tso = ethtool_op_get_tso,
3195 .set_tso = ethtool_op_set_tso,
3196 .get_rx_csum = sky2_get_rx_csum,
3197 .set_rx_csum = sky2_set_rx_csum,
3198 .get_strings = sky2_get_strings,
fb17358f
SH		 3199 .get_coalesce = sky2_get_coalesce,
3200 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3201 .get_ringparam = sky2_get_ringparam,
3202 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3203 .get_pauseparam = sky2_get_pauseparam,
3204 .set_pauseparam = sky2_set_pauseparam,
793b883e 3205 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3206 .get_stats_count = sky2_get_stats_count,
3207 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3208 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3209};
3210
3211/* Initialize network device */
3212static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3213 unsigned port, int highmem)
3214{
3215 struct sky2_port *sky2;
3216 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3217
3218 if (!dev) {
3219 printk(KERN_ERR "sky2 etherdev alloc failed");
3220 return NULL;
3221 }
3222
3223 SET_MODULE_OWNER(dev);
3224 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3225 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3226 dev->open = sky2_up;
3227 dev->stop = sky2_down;
ef743d33 3228 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3229 dev->hard_start_xmit = sky2_xmit_frame;
3230 dev->get_stats = sky2_get_stats;
3231 dev->set_multicast_list = sky2_set_multicast;
3232 dev->set_mac_address = sky2_set_mac_address;
3233 dev->change_mtu = sky2_change_mtu;
3234 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3235 dev->tx_timeout = sky2_tx_timeout;
3236 dev->watchdog_timeo = TX_WATCHDOG;
3237 if (port == 0)
3238 dev->poll = sky2_poll;
3239 dev->weight = NAPI_WEIGHT;
3240#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3241 /* Network console (only works on port 0)
3242 * because netpoll makes assumptions about NAPI
3243 */
3244 if (port == 0)
3245 dev->poll_controller = sky2_netpoll;
cd28ab6a 3246#endif
cd28ab6a
SH		 3247
3248 sky2 = netdev_priv(dev);
3249 sky2->netdev = dev;
3250 sky2->hw = hw;
3251 sky2->msg_enable = netif_msg_init(debug, default_msg);
3252
cd28ab6a
SH		 3253 /* Auto speed and flow control */
3254 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3255 sky2->flow_mode = FC_BOTH;
3256
cd28ab6a
SH		 3257 sky2->duplex = -1;
3258 sky2->speed = -1;
3259 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3260 sky2->rx_csum = 1;
75d070c5 3261
e07b1aa8 3262 spin_lock_init(&sky2->phy_lock);
793b883e 3263 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3264 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3265
3266 hw->dev[port] = dev;
3267
3268 sky2->port = port;
3269
5a5b1ea0 3270 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3271 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3272 if (highmem)
3273 dev->features |= NETIF_F_HIGHDMA;
793b883e 3274 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3275
d1f13708 3276#ifdef SKY2_VLAN_TAG_USED
3277 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3278 dev->vlan_rx_register = sky2_vlan_rx_register;
3279 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3280#endif
3281
cd28ab6a 3282 /* read the mac address */
793b883e 3283 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3284 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3285
3286 /* device is off until link detection */
3287 netif_carrier_off(dev);
3288 netif_stop_queue(dev);
3289
3290 return dev;
3291}
3292
28bd181a 3293static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3294{
3295 const struct sky2_port *sky2 = netdev_priv(dev);
3296
3297 if (netif_msg_probe(sky2))
3298 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3299 dev->name,
3300 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3301 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3302}
3303
fb2690a9 3304/* Handle software interrupt used during MSI test */
7d12e780 3305static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3306{
3307 struct sky2_hw *hw = dev_id;
3308 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3309
3310 if (status == 0)
3311 return IRQ_NONE;
3312
3313 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3314 hw->msi = 1;
fb2690a9
SH		 3315 wake_up(&hw->msi_wait);
3316 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3317 }
3318 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3319
3320 return IRQ_HANDLED;
3321}
3322
3323/* Test interrupt path by forcing a a software IRQ */
3324static int __devinit sky2_test_msi(struct sky2_hw *hw)
3325{
3326 struct pci_dev *pdev = hw->pdev;
3327 int err;
3328
bb507fe1 3329 init_waitqueue_head (&hw->msi_wait);
3330
fb2690a9
SH		 3331 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3332
b0a20ded 3333 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9
SH		 3334 if (err) {
3335 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3336 pci_name(pdev), pdev->irq);
3337 return err;
3338 }
3339
fb2690a9 3340 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3341 sky2_read8(hw, B0_CTST);
fb2690a9 3342
b0a20ded 3343 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3344
b0a20ded 3345 if (!hw->msi) {
fb2690a9 3346 /* MSI test failed, go back to INTx mode */
2bffc23a
SH		 3347 printk(KERN_INFO PFX "%s: No interrupt generated using MSI, "
3348 "switching to INTx mode.\n",
fb2690a9
SH		 3349 pci_name(pdev));
3350
3351 err = -EOPNOTSUPP;
3352 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3353 }
3354
3355 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3356 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3357
3358 free_irq(pdev->irq, hw);
3359
3360 return err;
3361}
3362
cd28ab6a
SH		 3363static int __devinit sky2_probe(struct pci_dev *pdev,
3364 const struct pci_device_id *ent)
3365{
793b883e 3366 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3367 struct sky2_hw *hw;
5afa0a9c 3368 int err, pm_cap, using_dac = 0;
cd28ab6a 3369
793b883e
SH		 3370 err = pci_enable_device(pdev);
3371 if (err) {
cd28ab6a
SH		 3372 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3373 pci_name(pdev));
3374 goto err_out;
3375 }
3376
793b883e
SH		 3377 err = pci_request_regions(pdev, DRV_NAME);
3378 if (err) {
cd28ab6a
SH		 3379 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3380 pci_name(pdev));
793b883e 3381 goto err_out;
cd28ab6a
SH		 3382 }
3383
3384 pci_set_master(pdev);
3385
5afa0a9c 3386 /* Find power-management capability. */
3387 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3388 if (pm_cap == 0) {
3389 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3390 "aborting.\n");
3391 err = -EIO;
3392 goto err_out_free_regions;
3393 }
3394
d1f3d4dd
SH		 3395 if (sizeof(dma_addr_t) > sizeof(u32) &&
3396 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3397 using_dac = 1;
3398 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3399 if (err < 0) {
3400 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3401 "for consistent allocations\n", pci_name(pdev));
3402 goto err_out_free_regions;
3403 }
cd28ab6a 3404
d1f3d4dd 3405 } else {
cd28ab6a
SH		 3406 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3407 if (err) {
3408 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3409 pci_name(pdev));
3410 goto err_out_free_regions;
3411 }
3412 }
d1f3d4dd 3413
cd28ab6a 3414 err = -ENOMEM;
6aad85d6 3415 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3416 if (!hw) {
3417 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3418 pci_name(pdev));
3419 goto err_out_free_regions;
3420 }
3421
cd28ab6a 3422 hw->pdev = pdev;
cd28ab6a
SH		 3423
3424 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3425 if (!hw->regs) {
3426 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3427 pci_name(pdev));
3428 goto err_out_free_hw;
3429 }
5afa0a9c 3430 hw->pm_cap = pm_cap;
cd28ab6a 3431
56a645cc 3432#ifdef __BIG_ENDIAN
f65b138c
SH		 3433 /* The sk98lin vendor driver uses hardware byte swapping but
3434 * this driver uses software swapping.
3435 */
56a645cc
SH		 3436 {
3437 u32 reg;
56a645cc 3438 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3439 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3440 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3441 }
3442#endif
3443
08c06d8a
SH		 3444 /* ring for status responses */
3445 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3446 &hw->st_dma);
3447 if (!hw->st_le)
3448 goto err_out_iounmap;
3449
cd28ab6a
SH		 3450 err = sky2_reset(hw);
3451 if (err)
793b883e 3452 goto err_out_iounmap;
cd28ab6a 3453
7c7459d1
GKH		 3454 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3455 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3456 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3457 hw->chip_id, hw->chip_rev);
cd28ab6a 3458
793b883e
SH		 3459 dev = sky2_init_netdev(hw, 0, using_dac);
3460 if (!dev)
cd28ab6a
SH		 3461 goto err_out_free_pci;
3462
9fa1b1f3
SH		 3463 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3464 err = sky2_test_msi(hw);
3465 if (err == -EOPNOTSUPP)
3466 pci_disable_msi(pdev);
3467 else if (err)
3468 goto err_out_free_netdev;
3469 }
3470
793b883e
SH		 3471 err = register_netdev(dev);
3472 if (err) {
cd28ab6a
SH		 3473 printk(KERN_ERR PFX "%s: cannot register net device\n",
3474 pci_name(pdev));
3475 goto err_out_free_netdev;
3476 }
3477
b0a20ded
SH		 3478 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3479 dev->name, hw);
9fa1b1f3
SH		 3480 if (err) {
3481 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3482 pci_name(pdev), pdev->irq);
3483 goto err_out_unregister;
3484 }
3485 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3486
cd28ab6a
SH		 3487 sky2_show_addr(dev);
3488
3489 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3490 if (register_netdev(dev1) == 0)
3491 sky2_show_addr(dev1);
3492 else {
3493 /* Failure to register second port need not be fatal */
793b883e
SH		 3494 printk(KERN_WARNING PFX
3495 "register of second port failed\n");
cd28ab6a
SH		 3496 hw->dev[1] = NULL;
3497 free_netdev(dev1);
3498 }
3499 }
3500
01bd7564 3501 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
eb35cf60 3502 sky2_idle_start(hw);
d27ed387 3503
793b883e
SH		 3504 pci_set_drvdata(pdev, hw);
3505
cd28ab6a
SH		 3506 return 0;
3507
793b883e 3508err_out_unregister:
b0a20ded
SH		 3509 if (hw->msi)
3510 pci_disable_msi(pdev);
793b883e 3511 unregister_netdev(dev);
cd28ab6a
SH		 3512err_out_free_netdev:
3513 free_netdev(dev);
cd28ab6a 3514err_out_free_pci:
793b883e 3515 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3516 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3517err_out_iounmap:
3518 iounmap(hw->regs);
3519err_out_free_hw:
3520 kfree(hw);
3521err_out_free_regions:
3522 pci_release_regions(pdev);
cd28ab6a 3523 pci_disable_device(pdev);
cd28ab6a
SH		 3524err_out:
3525 return err;
3526}
3527
3528static void __devexit sky2_remove(struct pci_dev *pdev)
3529{
793b883e 3530 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3531 struct net_device *dev0, *dev1;
3532
793b883e 3533 if (!hw)
cd28ab6a
SH		 3534 return;
3535
d27ed387
SH		 3536 del_timer_sync(&hw->idle_timer);
3537
3538 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3539 synchronize_irq(hw->pdev->irq);
3540
cd28ab6a 3541 dev0 = hw->dev[0];
793b883e
SH		 3542 dev1 = hw->dev[1];
3543 if (dev1)
3544 unregister_netdev(dev1);
cd28ab6a
SH		 3545 unregister_netdev(dev0);
3546
5afa0a9c 3547 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3548 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3549 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3550 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3551
3552 free_irq(pdev->irq, hw);
b0a20ded
SH		 3553 if (hw->msi)
3554 pci_disable_msi(pdev);
793b883e 3555 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3556 pci_release_regions(pdev);
3557 pci_disable_device(pdev);
793b883e 3558
cd28ab6a
SH		 3559 if (dev1)
3560 free_netdev(dev1);
3561 free_netdev(dev0);
3562 iounmap(hw->regs);
3563 kfree(hw);
5afa0a9c 3564
cd28ab6a
SH		 3565 pci_set_drvdata(pdev, NULL);
3566}
3567
3568#ifdef CONFIG_PM
3569static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3570{
793b883e 3571 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3572 int i;
2ccc99b7
SH		 3573 pci_power_t pstate = pci_choose_state(pdev, state);
3574
3575 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3576 return -EINVAL;
cd28ab6a 3577
eb35cf60 3578 del_timer_sync(&hw->idle_timer);
6a5706b9 3579 netif_poll_disable(hw->dev[0]);
eb35cf60 3580
f05267e7 3581 for (i = 0; i < hw->ports; i++) {
cd28ab6a
SH		 3582 struct net_device *dev = hw->dev[i];
3583
6a5706b9 3584 if (netif_running(dev)) {
5afa0a9c 3585 sky2_down(dev);
cd28ab6a 3586 netif_device_detach(dev);
cd28ab6a
SH		 3587 }
3588 }
3589
8ab8fca2 3590 sky2_write32(hw, B0_IMSK, 0);
d374c1c1 3591 pci_save_state(pdev);
2ccc99b7
SH		 3592 sky2_set_power_state(hw, pstate);
3593 return 0;
cd28ab6a
SH		 3594}
3595
3596static int sky2_resume(struct pci_dev *pdev)
3597{
793b883e 3598 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3599 int i, err;
cd28ab6a 3600
cd28ab6a
SH		 3601 pci_restore_state(pdev);
3602 pci_enable_wake(pdev, PCI_D0, 0);
2ccc99b7 3603 sky2_set_power_state(hw, PCI_D0);
cd28ab6a 3604
08c06d8a
SH		 3605 err = sky2_reset(hw);
3606 if (err)
3607 goto out;
cd28ab6a 3608
8ab8fca2
SH		 3609 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3610
f05267e7 3611 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3612 struct net_device *dev = hw->dev[i];
6a5706b9 3613 if (netif_running(dev)) {
08c06d8a 3614 netif_device_attach(dev);
88d11360 3615
08c06d8a
SH		 3616 err = sky2_up(dev);
3617 if (err) {
3618 printk(KERN_ERR PFX "%s: could not up: %d\n",
3619 dev->name, err);
3620 dev_close(dev);
eb35cf60 3621 goto out;
5afa0a9c 3622 }
cd28ab6a
SH		 3623 }
3624 }
eb35cf60 3625
6a5706b9 3626 netif_poll_enable(hw->dev[0]);
eb35cf60 3627 sky2_idle_start(hw);
08c06d8a
SH		 3628out:
3629 return err;
cd28ab6a
SH		 3630}
3631#endif
3632
3633static struct pci_driver sky2_driver = {
793b883e
SH		 3634 .name = DRV_NAME,
3635 .id_table = sky2_id_table,
3636 .probe = sky2_probe,
3637 .remove = __devexit_p(sky2_remove),
cd28ab6a 3638#ifdef CONFIG_PM
793b883e
SH		 3639 .suspend = sky2_suspend,
3640 .resume = sky2_resume,
cd28ab6a
SH		 3641#endif
3642};
3643
3644static int __init sky2_init_module(void)
3645{
50241c4c 3646 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3647}
3648
3649static void __exit sky2_cleanup_module(void)
3650{
3651 pci_unregister_driver(&sky2_driver);
3652}
3653
3654module_init(sky2_init_module);
3655module_exit(sky2_cleanup_module);
3656
3657MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3658MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3659MODULE_LICENSE("GPL");
5f4f9dc1 3660MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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