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iSeries: fix section mismatch in iseries_veth
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
3cf26753 42#include <linux/debugfs.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
bcc52894 54#define DRV_VERSION "1.21"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
793b883e
SH		 67
68#define TX_RING_SIZE 512
69#define TX_DEF_PENDING (TX_RING_SIZE - 1)
70#define TX_MIN_PENDING 64
b19666d9 71#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 72
793b883e 73#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 74#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 75#define TX_WATCHDOG (5 * HZ)
76#define NAPI_WEIGHT 64
77#define PHY_RETRIES 1000
78
f4331a6d
SH		 79#define SKY2_EEPROM_MAGIC 0x9955aabb
80
81
cb5d9547
SH		 82#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
cd28ab6a 84static const u32 default_msg =
793b883e
SH		 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 88
793b883e 89static int debug = -1; /* defaults above */
cd28ab6a
SH		 90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
14d0263f 93static int copybreak __read_mostly = 128;
bdb5c58e
SH		 94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
fb2690a9
SH		 97static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
cd28ab6a 101static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
e5b74c7d 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
cd28ab6a
SH		 139 { 0 }
140};
793b883e 141
cd28ab6a
SH		 142MODULE_DEVICE_TABLE(pci, sky2_id_table);
143
144/* Avoid conditionals by using array */
145static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
146static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 147static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 148
92f965e8
SH		 149/* This driver supports yukon2 chipset only */
150static const char *yukon2_name[] = {
151 "XL", /* 0xb3 */
152 "EC Ultra", /* 0xb4 */
93745494 153 "Extreme", /* 0xb5 */
92f965e8
SH		 154 "EC", /* 0xb6 */
155 "FE", /* 0xb7 */
05745c4a 156 "FE+", /* 0xb8 */
793b883e
SH		 157};
158
d1b139c0
SH		 159static void sky2_set_multicast(struct net_device *dev);
160
af043aa5 161/* Access to PHY via serial interconnect */
ef743d33 162static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 163{
164 int i;
165
166 gma_write16(hw, port, GM_SMI_DATA, val);
167 gma_write16(hw, port, GM_SMI_CTRL,
168 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
169
170 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 171 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
172 if (ctrl == 0xffff)
173 goto io_error;
174
175 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 176 return 0;
af043aa5
SH		 177
178 udelay(10);
cd28ab6a 179 }
ef743d33 180
af043aa5 181 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 182 return -ETIMEDOUT;
af043aa5
SH		 183
184io_error:
185 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
186 return -EIO;
cd28ab6a
SH		 187}
188
ef743d33 189static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 190{
191 int i;
192
793b883e 193 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 194 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
195
196 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 197 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
198 if (ctrl == 0xffff)
199 goto io_error;
200
201 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33 202 *val = gma_read16(hw, port, GM_SMI_DATA);
203 return 0;
204 }
205
af043aa5 206 udelay(10);
cd28ab6a
SH		 207 }
208
af043aa5 209 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 210 return -ETIMEDOUT;
af043aa5
SH		 211io_error:
212 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
213 return -EIO;
ef743d33 214}
215
af043aa5 216static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33 217{
218 u16 v;
af043aa5 219 __gm_phy_read(hw, port, reg, &v);
ef743d33 220 return v;
cd28ab6a
SH		 221}
222
5afa0a9c 223
ae306cca
SH		 224static void sky2_power_on(struct sky2_hw *hw)
225{
226 /* switch power to VCC (WA for VAUX problem) */
227 sky2_write8(hw, B0_POWER_CTRL,
228 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 229
ae306cca
SH		 230 /* disable Core Clock Division, */
231 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 232
ae306cca
SH		 233 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
234 /* enable bits are inverted */
235 sky2_write8(hw, B2_Y2_CLK_GATE,
236 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
237 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
238 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
239 else
240 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 241
ea76e635 242 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 243 u32 reg;
5afa0a9c 244
b32f40c4 245 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 246
b32f40c4 247 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 248 /* set all bits to 0 except bits 15..12 and 8 */
249 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 250 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 251
b32f40c4 252 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 253 /* set all bits to 0 except bits 28 & 27 */
254 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 255 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 256
b32f40c4 257 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 258
259 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
260 reg = sky2_read32(hw, B2_GP_IO);
261 reg |= GLB_GPIO_STAT_RACE_DIS;
262 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 263
264 sky2_read32(hw, B2_GP_IO);
5afa0a9c 265 }
ae306cca 266}
5afa0a9c 267
ae306cca
SH		 268static void sky2_power_aux(struct sky2_hw *hw)
269{
270 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
271 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
272 else
273 /* enable bits are inverted */
274 sky2_write8(hw, B2_Y2_CLK_GATE,
275 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
276 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
277 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
278
279 /* switch power to VAUX */
280 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
281 sky2_write8(hw, B0_POWER_CTRL,
282 (PC_VAUX_ENA | PC_VCC_ENA |
283 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c 284}
285
d3bcfbeb 286static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 287{
288 u16 reg;
289
290 /* disable all GMAC IRQ's */
291 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 292
cd28ab6a
SH		 293 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
294 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
297
298 reg = gma_read16(hw, port, GM_RX_CTRL);
299 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
300 gma_write16(hw, port, GM_RX_CTRL, reg);
301}
302
16ad91e1
SH		 303/* flow control to advertise bits */
304static const u16 copper_fc_adv[] = {
305 [FC_NONE] = 0,
306 [FC_TX] = PHY_M_AN_ASP,
307 [FC_RX] = PHY_M_AN_PC,
308 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
309};
310
311/* flow control to advertise bits when using 1000BaseX */
312static const u16 fiber_fc_adv[] = {
df3fe1f3 313 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 314 [FC_TX] = PHY_M_P_ASYM_MD_X,
315 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 316 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 317};
318
319/* flow control to GMA disable bits */
320static const u16 gm_fc_disable[] = {
321 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
322 [FC_TX] = GM_GPCR_FC_RX_DIS,
323 [FC_RX] = GM_GPCR_FC_TX_DIS,
324 [FC_BOTH] = 0,
325};
326
327
cd28ab6a
SH		 328static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
329{
330 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 331 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 332
ea76e635
SH		 333 if (sky2->autoneg == AUTONEG_ENABLE &&
334 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 335 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
336
337 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 338 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 339 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
340
53419c68 341 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 342 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 343 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 344 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
345 else
53419c68
SH		 346 /* set master & slave downshift counter to 1x */
347 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 348
349 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
350 }
351
352 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 353 if (sky2_is_copper(hw)) {
05745c4a 354 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 355 /* enable automatic crossover */
356 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 357
358 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
359 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
360 u16 spec;
361
362 /* Enable Class A driver for FE+ A0 */
363 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
364 spec |= PHY_M_FESC_SEL_CL_A;
365 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
366 }
cd28ab6a
SH		 367 } else {
368 /* disable energy detect */
369 ctrl &= ~PHY_M_PC_EN_DET_MSK;
370
371 /* enable automatic crossover */
372 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
373
53419c68 374 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 375 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 376 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 377 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 378 ctrl &= ~PHY_M_PC_DSC_MSK;
379 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
380 }
381 }
cd28ab6a
SH		 382 } else {
383 /* workaround for deviation #4.88 (CRC errors) */
384 /* disable Automatic Crossover */
385
386 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 387 }
cd28ab6a 388
b89165f2
SH		 389 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
390
391 /* special setup for PHY 88E1112 Fiber */
ea76e635 392 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 393 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 394
b89165f2
SH		 395 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
396 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
397 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
398 ctrl &= ~PHY_M_MAC_MD_MSK;
399 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
401
402 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 403 /* select page 1 to access Fiber registers */
404 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 405
406 /* for SFP-module set SIGDET polarity to low */
407 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
408 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 409 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 410 }
b89165f2
SH		 411
412 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 413 }
414
7800fddc 415 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 416 ct1000 = 0;
417 adv = PHY_AN_CSMA;
2eaba1a2 418 reg = 0;
cd28ab6a
SH		 419
420 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 421 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 422 if (sky2->advertising & ADVERTISED_1000baseT_Full)
423 ct1000 |= PHY_M_1000C_AFD;
424 if (sky2->advertising & ADVERTISED_1000baseT_Half)
425 ct1000 |= PHY_M_1000C_AHD;
426 if (sky2->advertising & ADVERTISED_100baseT_Full)
427 adv |= PHY_M_AN_100_FD;
428 if (sky2->advertising & ADVERTISED_100baseT_Half)
429 adv |= PHY_M_AN_100_HD;
430 if (sky2->advertising & ADVERTISED_10baseT_Full)
431 adv |= PHY_M_AN_10_FD;
432 if (sky2->advertising & ADVERTISED_10baseT_Half)
433 adv |= PHY_M_AN_10_HD;
709c6e7b 434
16ad91e1 435 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 436 } else { /* special defines for FIBER (88E1040S only) */
437 if (sky2->advertising & ADVERTISED_1000baseT_Full)
438 adv |= PHY_M_AN_1000X_AFD;
439 if (sky2->advertising & ADVERTISED_1000baseT_Half)
440 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 441
16ad91e1 442 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 443 }
cd28ab6a
SH		 444
445 /* Restart Auto-negotiation */
446 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
447 } else {
448 /* forced speed/duplex settings */
449 ct1000 = PHY_M_1000C_MSE;
450
2eaba1a2
SH		 451 /* Disable auto update for duplex flow control and speed */
452 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 453
454 switch (sky2->speed) {
455 case SPEED_1000:
456 ctrl |= PHY_CT_SP1000;
2eaba1a2 457 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 458 break;
459 case SPEED_100:
460 ctrl |= PHY_CT_SP100;
2eaba1a2 461 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 462 break;
463 }
464
2eaba1a2
SH		 465 if (sky2->duplex == DUPLEX_FULL) {
466 reg |= GM_GPCR_DUP_FULL;
467 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 468 } else if (sky2->speed < SPEED_1000)
469 sky2->flow_mode = FC_NONE;
2eaba1a2 470
2eaba1a2 471
16ad91e1 472 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 473
474 /* Forward pause packets to GMAC? */
16ad91e1 475 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 476 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
477 else
478 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 479 }
480
2eaba1a2
SH		 481 gma_write16(hw, port, GM_GP_CTRL, reg);
482
05745c4a 483 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 484 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
485
486 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
487 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
488
489 /* Setup Phy LED's */
490 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
491 ledover = 0;
492
493 switch (hw->chip_id) {
494 case CHIP_ID_YUKON_FE:
495 /* on 88E3082 these bits are at 11..9 (shifted left) */
496 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
497
498 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
499
500 /* delete ACT LED control bits */
501 ctrl &= ~PHY_M_FELP_LED1_MSK;
502 /* change ACT LED control to blink mode */
503 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
504 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
505 break;
506
05745c4a
SH		 507 case CHIP_ID_YUKON_FE_P:
508 /* Enable Link Partner Next Page */
509 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
510 ctrl |= PHY_M_PC_ENA_LIP_NP;
511
512 /* disable Energy Detect and enable scrambler */
513 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
514 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
515
516 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
517 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
518 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
519 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
520
521 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
522 break;
523
cd28ab6a 524 case CHIP_ID_YUKON_XL:
793b883e 525 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 526
527 /* select page 3 to access LED control register */
528 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
529
530 /* set LED Function Control register */
ed6d32c7
SH		 531 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
532 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
533 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
534 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
535 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 536
537 /* set Polarity Control register */
538 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 539 (PHY_M_POLC_LS1_P_MIX(4) |
540 PHY_M_POLC_IS0_P_MIX(4) |
541 PHY_M_POLC_LOS_CTRL(2) |
542 PHY_M_POLC_INIT_CTRL(2) |
543 PHY_M_POLC_STA1_CTRL(2) |
544 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 545
546 /* restore page register */
793b883e 547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 548 break;
93745494 549
ed6d32c7 550 case CHIP_ID_YUKON_EC_U:
93745494 551 case CHIP_ID_YUKON_EX:
ed4d4161 552 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 553 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
554
555 /* select page 3 to access LED control register */
556 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
557
558 /* set LED Function Control register */
559 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
560 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
561 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
562 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
563 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
564
565 /* set Blink Rate in LED Timer Control Register */
566 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
567 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
568 /* restore page register */
569 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
570 break;
cd28ab6a
SH		 571
572 default:
573 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
574 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
575 /* turn off the Rx LED (LED_RX) */
0efdf262 576 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 577 }
578
9467a8fc
SH		 579 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
580 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 581 /* apply fixes in PHY AFE */
ed6d32c7
SH		 582 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
583
977bdf06 584 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 585 gm_phy_write(hw, port, 0x18, 0xaa99);
586 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 587
977bdf06 588 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 589 gm_phy_write(hw, port, 0x18, 0xa204);
590 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 591
592 /* set page register to 0 */
9467a8fc 593 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 594 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
595 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
596 /* apply workaround for integrated resistors calibration */
597 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
598 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
93745494 599 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
05745c4a 600 /* no effect on Yukon-XL */
977bdf06 601 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 602
977bdf06
SH		 603 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
604 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 605 ledover |= PHY_M_LED_MO_100;
977bdf06 606 }
cd28ab6a 607
977bdf06
SH		 608 if (ledover)
609 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
610
611 }
2eaba1a2 612
d571b694 613 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 614 if (sky2->autoneg == AUTONEG_ENABLE)
615 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
616 else
617 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
618}
619
d3bcfbeb 620static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
621{
622 u32 reg1;
ff35164e
SH		 623 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
624 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
d3bcfbeb 625
82637e80 626 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 627 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
ff35164e 628 /* Turn on/off phy power saving */
d3bcfbeb 629 if (onoff)
d3bcfbeb 630 reg1 &= ~phy_power[port];
631 else
632 reg1 |= phy_power[port];
633
ff35164e
SH		 634 if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
635 reg1 |= coma_mode[port];
636
b32f40c4 637 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80
SH		 638 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
639 sky2_pci_read32(hw, PCI_DEV_REG1);
167f53d0 640
d3bcfbeb 641 udelay(100);
642}
643
1b537565
SH		 644/* Force a renegotiation */
645static void sky2_phy_reinit(struct sky2_port *sky2)
646{
e07b1aa8 647 spin_lock_bh(&sky2->phy_lock);
1b537565 648 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 649 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 650}
651
e3173832
SH		 652/* Put device in state to listen for Wake On Lan */
653static void sky2_wol_init(struct sky2_port *sky2)
654{
655 struct sky2_hw *hw = sky2->hw;
656 unsigned port = sky2->port;
657 enum flow_control save_mode;
658 u16 ctrl;
659 u32 reg1;
660
661 /* Bring hardware out of reset */
662 sky2_write16(hw, B0_CTST, CS_RST_CLR);
663 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
664
665 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
666 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
667
668 /* Force to 10/100
669 * sky2_reset will re-enable on resume
670 */
671 save_mode = sky2->flow_mode;
672 ctrl = sky2->advertising;
673
674 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
675 sky2->flow_mode = FC_NONE;
676 sky2_phy_power(hw, port, 1);
677 sky2_phy_reinit(sky2);
678
679 sky2->flow_mode = save_mode;
680 sky2->advertising = ctrl;
681
682 /* Set GMAC to no flow control and auto update for speed/duplex */
683 gma_write16(hw, port, GM_GP_CTRL,
684 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
685 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
686
687 /* Set WOL address */
688 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
689 sky2->netdev->dev_addr, ETH_ALEN);
690
691 /* Turn on appropriate WOL control bits */
692 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
693 ctrl = 0;
694 if (sky2->wol & WAKE_PHY)
695 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
696 else
697 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
698
699 if (sky2->wol & WAKE_MAGIC)
700 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
701 else
702 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
703
704 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
705 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
706
707 /* Turn on legacy PCI-Express PME mode */
b32f40c4 708 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 709 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 710 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 711
712 /* block receiver */
713 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
714
715}
716
69161611
SH		 717static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
718{
05745c4a
SH		 719 struct net_device *dev = hw->dev[port];
720
ed4d4161
SH		 721 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
722 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
723 hw->chip_id == CHIP_ID_YUKON_FE_P ||
724 hw->chip_id == CHIP_ID_YUKON_SUPR) {
725 /* Yukon-Extreme B0 and further Extreme devices */
726 /* enable Store & Forward mode for TX */
05745c4a 727
ed4d4161
SH		 728 if (dev->mtu <= ETH_DATA_LEN)
729 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
730 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 731
ed4d4161
SH		 732 else
733 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
734 TX_JUMBO_ENA| TX_STFW_ENA);
735 } else {
736 if (dev->mtu <= ETH_DATA_LEN)
737 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
738 else {
739 /* set Tx GMAC FIFO Almost Empty Threshold */
740 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
741 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 742
ed4d4161
SH		 743 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
744
745 /* Can't do offload because of lack of store/forward */
746 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
747 }
69161611
SH		 748 }
749}
750
cd28ab6a
SH		 751static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
752{
753 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
754 u16 reg;
25cccecc 755 u32 rx_reg;
cd28ab6a
SH		 756 int i;
757 const u8 *addr = hw->dev[port]->dev_addr;
758
f350339c
SH		 759 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
760 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 761
762 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
763
793b883e 764 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 765 /* WA DEV_472 -- looks like crossed wires on port 2 */
766 /* clear GMAC 1 Control reset */
767 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
768 do {
769 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
770 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
771 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
772 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
773 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
774 }
775
793b883e 776 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 777
2eaba1a2
SH		 778 /* Enable Transmit FIFO Underrun */
779 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
780
e07b1aa8 781 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 782 sky2_phy_init(hw, port);
e07b1aa8 783 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 784
785 /* MIB clear */
786 reg = gma_read16(hw, port, GM_PHY_ADDR);
787 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
788
43f2f104
SH		 789 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
790 gma_read16(hw, port, i);
cd28ab6a
SH		 791 gma_write16(hw, port, GM_PHY_ADDR, reg);
792
793 /* transmit control */
794 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
795
796 /* receive control reg: unicast + multicast + no FCS */
797 gma_write16(hw, port, GM_RX_CTRL,
793b883e 798 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 799
800 /* transmit flow control */
801 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
802
803 /* transmit parameter */
804 gma_write16(hw, port, GM_TX_PARAM,
805 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
806 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
807 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
808 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
809
810 /* serial mode register */
811 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 812 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 813
6b1a3aef 814 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 815 reg |= GM_SMOD_JUMBO_ENA;
816
817 gma_write16(hw, port, GM_SERIAL_MODE, reg);
818
cd28ab6a
SH		 819 /* virtual address for data */
820 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
821
793b883e
SH		 822 /* physical address: used for pause frames */
823 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
824
825 /* ignore counter overflows */
cd28ab6a
SH		 826 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
827 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
828 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
829
830 /* Configure Rx MAC FIFO */
831 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 832 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 833 if (hw->chip_id == CHIP_ID_YUKON_EX ||
834 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 835 rx_reg |= GMF_RX_OVER_ON;
69161611 836
25cccecc 837 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 838
798fdd07
SH		 839 if (hw->chip_id == CHIP_ID_YUKON_XL) {
840 /* Hardware errata - clear flush mask */
841 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
842 } else {
843 /* Flush Rx MAC FIFO on any flow control or error */
844 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
845 }
cd28ab6a 846
8df9a876 847 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 848 reg = RX_GMF_FL_THR_DEF + 1;
849 /* Another magic mystery workaround from sk98lin */
850 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
851 hw->chip_rev == CHIP_REV_YU_FE2_A0)
852 reg = 0x178;
853 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 854
855 /* Configure Tx MAC FIFO */
856 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
857 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 858
e0c28116
SH		 859 /* On chips without ram buffer, pause is controled by MAC level */
860 if (sky2_read8(hw, B2_E_0) == 0) {
8df9a876 861 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 862 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 863
69161611 864 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 865 }
866
e970d1f8
SH		 867 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
868 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
869 /* disable dynamic watermark */
870 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
871 reg &= ~TX_DYN_WM_ENA;
872 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
873 }
cd28ab6a
SH		 874}
875
67712901
SH		 876/* Assign Ram Buffer allocation to queue */
877static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 878{
67712901
SH		 879 u32 end;
880
881 /* convert from K bytes to qwords used for hw register */
882 start *= 1024/8;
883 space *= 1024/8;
884 end = start + space - 1;
793b883e 885
cd28ab6a
SH		 886 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
887 sky2_write32(hw, RB_ADDR(q, RB_START), start);
888 sky2_write32(hw, RB_ADDR(q, RB_END), end);
889 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
890 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
891
892 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 893 u32 tp = space - space/4;
793b883e 894
1c28f6ba
SH		 895 /* On receive queue's set the thresholds
896 * give receiver priority when > 3/4 full
897 * send pause when down to 2K
898 */
899 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
900 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 901
1c28f6ba
SH		 902 tp = space - 2048/8;
903 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
904 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 905 } else {
906 /* Enable store & forward on Tx queue's because
907 * Tx FIFO is only 1K on Yukon
908 */
909 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
910 }
911
912 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 913 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 914}
915
cd28ab6a 916/* Setup Bus Memory Interface */
af4ed7e6 917static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 918{
919 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
920 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
921 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 922 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 923}
924
cd28ab6a
SH		 925/* Setup prefetch unit registers. This is the interface between
926 * hardware and driver list elements
927 */
8cc048e3 928static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 929 u64 addr, u32 last)
930{
cd28ab6a
SH		 931 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
932 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
933 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
934 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
935 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
936 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 937
938 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 939}
940
793b883e
SH		 941static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
942{
943 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
944
cb5d9547 945 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 946 le->ctrl = 0;
793b883e
SH		 947 return le;
948}
cd28ab6a 949
88f5f0ca
SH		 950static void tx_init(struct sky2_port *sky2)
951{
952 struct sky2_tx_le *le;
953
954 sky2->tx_prod = sky2->tx_cons = 0;
955 sky2->tx_tcpsum = 0;
956 sky2->tx_last_mss = 0;
957
958 le = get_tx_le(sky2);
959 le->addr = 0;
960 le->opcode = OP_ADDR64 | HW_OWNER;
88f5f0ca
SH		 961}
962
291ea614
SH		 963static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
964 struct sky2_tx_le *le)
965{
966 return sky2->tx_ring + (le - sky2->tx_le);
967}
968
290d4de5
SH		 969/* Update chip's next pointer */
970static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 971{
50432cb5 972 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 973 wmb();
50432cb5
SH		 974 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
975
976 /* Synchronize I/O on since next processor may write to tail */
977 mmiowb();
cd28ab6a
SH		 978}
979
793b883e 980
cd28ab6a
SH		 981static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
982{
983 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 984 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 985 le->ctrl = 0;
cd28ab6a
SH		 986 return le;
987}
988
14d0263f
SH		 989/* Build description to hardware for one receive segment */
990static void sky2_rx_add(struct sky2_port *sky2, u8 op,
991 dma_addr_t map, unsigned len)
cd28ab6a
SH		 992{
993 struct sky2_rx_le *le;
994
86c6887e 995 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 996 le = sky2_next_rx(sky2);
86c6887e 997 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 998 le->opcode = OP_ADDR64 | HW_OWNER;
999 }
793b883e 1000
cd28ab6a 1001 le = sky2_next_rx(sky2);
734d1868
SH		 1002 le->addr = cpu_to_le32((u32) map);
1003 le->length = cpu_to_le16(len);
14d0263f 1004 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1005}
1006
14d0263f
SH		 1007/* Build description to hardware for one possibly fragmented skb */
1008static void sky2_rx_submit(struct sky2_port *sky2,
1009 const struct rx_ring_info *re)
1010{
1011 int i;
1012
1013 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1014
1015 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1016 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1017}
1018
1019
1020static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1021 unsigned size)
1022{
1023 struct sk_buff *skb = re->skb;
1024 int i;
1025
1026 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1027 pci_unmap_len_set(re, data_size, size);
1028
1029 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1030 re->frag_addr[i] = pci_map_page(pdev,
1031 skb_shinfo(skb)->frags[i].page,
1032 skb_shinfo(skb)->frags[i].page_offset,
1033 skb_shinfo(skb)->frags[i].size,
1034 PCI_DMA_FROMDEVICE);
1035}
1036
1037static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1038{
1039 struct sk_buff *skb = re->skb;
1040 int i;
1041
1042 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1043 PCI_DMA_FROMDEVICE);
1044
1045 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1046 pci_unmap_page(pdev, re->frag_addr[i],
1047 skb_shinfo(skb)->frags[i].size,
1048 PCI_DMA_FROMDEVICE);
1049}
793b883e 1050
cd28ab6a
SH		 1051/* Tell chip where to start receive checksum.
1052 * Actually has two checksums, but set both same to avoid possible byte
1053 * order problems.
1054 */
793b883e 1055static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1056{
ea76e635 1057 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1058
ea76e635
SH		 1059 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1060 le->ctrl = 0;
1061 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1062
ea76e635
SH		 1063 sky2_write32(sky2->hw,
1064 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1065 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1066}
1067
6b1a3aef 1068/*
1069 * The RX Stop command will not work for Yukon-2 if the BMU does not
1070 * reach the end of packet and since we can't make sure that we have
1071 * incoming data, we must reset the BMU while it is not doing a DMA
1072 * transfer. Since it is possible that the RX path is still active,
1073 * the RX RAM buffer will be stopped first, so any possible incoming
1074 * data will not trigger a DMA. After the RAM buffer is stopped, the
1075 * BMU is polled until any DMA in progress is ended and only then it
1076 * will be reset.
1077 */
1078static void sky2_rx_stop(struct sky2_port *sky2)
1079{
1080 struct sky2_hw *hw = sky2->hw;
1081 unsigned rxq = rxqaddr[sky2->port];
1082 int i;
1083
1084 /* disable the RAM Buffer receive queue */
1085 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1086
1087 for (i = 0; i < 0xffff; i++)
1088 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1089 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1090 goto stopped;
1091
1092 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1093 sky2->netdev->name);
1094stopped:
1095 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1096
1097 /* reset the Rx prefetch unit */
1098 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1099 mmiowb();
6b1a3aef 1100}
793b883e 1101
d571b694 1102/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1103static void sky2_rx_clean(struct sky2_port *sky2)
1104{
1105 unsigned i;
1106
1107 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1108 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1109 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1110
1111 if (re->skb) {
14d0263f 1112 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1113 kfree_skb(re->skb);
1114 re->skb = NULL;
1115 }
1116 }
1117}
1118
ef743d33 1119/* Basic MII support */
1120static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1121{
1122 struct mii_ioctl_data *data = if_mii(ifr);
1123 struct sky2_port *sky2 = netdev_priv(dev);
1124 struct sky2_hw *hw = sky2->hw;
1125 int err = -EOPNOTSUPP;
1126
1127 if (!netif_running(dev))
1128 return -ENODEV; /* Phy still in reset */
1129
d89e1343 1130 switch (cmd) {
ef743d33 1131 case SIOCGMIIPHY:
1132 data->phy_id = PHY_ADDR_MARV;
1133
1134 /* fallthru */
1135 case SIOCGMIIREG: {
1136 u16 val = 0;
91c86df5 1137
e07b1aa8 1138 spin_lock_bh(&sky2->phy_lock);
ef743d33 1139 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1140 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1141
ef743d33 1142 data->val_out = val;
1143 break;
1144 }
1145
1146 case SIOCSMIIREG:
1147 if (!capable(CAP_NET_ADMIN))
1148 return -EPERM;
1149
e07b1aa8 1150 spin_lock_bh(&sky2->phy_lock);
ef743d33 1151 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1152 data->val_in);
e07b1aa8 1153 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1154 break;
1155 }
1156 return err;
1157}
1158
d1f13708 1159#ifdef SKY2_VLAN_TAG_USED
1160static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1161{
1162 struct sky2_port *sky2 = netdev_priv(dev);
1163 struct sky2_hw *hw = sky2->hw;
1164 u16 port = sky2->port;
d1f13708 1165
2bb8c262 1166 netif_tx_lock_bh(dev);
bea3348e 1167 napi_disable(&hw->napi);
d1f13708 1168
d1f13708 1169 sky2->vlgrp = grp;
3d4e66f5
SH		 1170 if (grp) {
1171 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1172 RX_VLAN_STRIP_ON);
1173 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1174 TX_VLAN_TAG_ON);
1175 } else {
1176 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1177 RX_VLAN_STRIP_OFF);
1178 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1179 TX_VLAN_TAG_OFF);
1180 }
d1f13708 1181
d1d08d12 1182 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1183 napi_enable(&hw->napi);
2bb8c262 1184 netif_tx_unlock_bh(dev);
d1f13708 1185}
1186#endif
1187
82788c7a 1188/*
14d0263f
SH		 1189 * Allocate an skb for receiving. If the MTU is large enough
1190 * make the skb non-linear with a fragment list of pages.
82788c7a 1191 */
14d0263f 1192static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1193{
1194 struct sk_buff *skb;
14d0263f 1195 int i;
82788c7a 1196
f03b8654
SH		 1197 if (sky2->hw->flags & SKY2_HW_FIFO_HANG_CHECK) {
1198 unsigned char *start;
1199 /*
1200 * Workaround for a bug in FIFO that cause hang
1201 * if the FIFO if the receive buffer is not 64 byte aligned.
1202 * The buffer returned from netdev_alloc_skb is
1203 * aligned except if slab debugging is enabled.
1204 */
1205 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1206 if (!skb)
1207 goto nomem;
1208 start = PTR_ALIGN(skb->data, 8);
1209 skb_reserve(skb, start - skb->data);
1210 } else {
1211 skb = netdev_alloc_skb(sky2->netdev,
1212 sky2->rx_data_size + NET_IP_ALIGN);
1213 if (!skb)
1214 goto nomem;
1215 skb_reserve(skb, NET_IP_ALIGN);
1216 }
14d0263f
SH		 1217
1218 for (i = 0; i < sky2->rx_nfrags; i++) {
1219 struct page *page = alloc_page(GFP_ATOMIC);
1220
1221 if (!page)
1222 goto free_partial;
1223 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1224 }
1225
1226 return skb;
14d0263f
SH		 1227free_partial:
1228 kfree_skb(skb);
1229nomem:
1230 return NULL;
82788c7a
SH		 1231}
1232
55c9dd35
SH		 1233static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1234{
1235 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1236}
1237
cd28ab6a
SH		 1238/*
1239 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1240 * Normal case this ends up creating one list element for skb
1241 * in the receive ring. Worst case if using large MTU and each
1242 * allocation falls on a different 64 bit region, that results
1243 * in 6 list elements per ring entry.
1244 * One element is used for checksum enable/disable, and one
1245 * extra to avoid wrap.
cd28ab6a 1246 */
6b1a3aef 1247static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1248{
6b1a3aef 1249 struct sky2_hw *hw = sky2->hw;
14d0263f 1250 struct rx_ring_info *re;
6b1a3aef 1251 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1252 unsigned i, size, thresh;
cd28ab6a 1253
6b1a3aef 1254 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1255 sky2_qset(hw, rxq);
977bdf06 1256
c3905bc4
SH		 1257 /* On PCI express lowering the watermark gives better performance */
1258 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1259 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1260
1261 /* These chips have no ram buffer?
1262 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1263 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1264 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1265 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1266 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1267
6b1a3aef 1268 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1269
ea76e635
SH		 1270 if (!(hw->flags & SKY2_HW_NEW_LE))
1271 rx_set_checksum(sky2);
14d0263f
SH		 1272
1273 /* Space needed for frame data + headers rounded up */
f957da2a 1274 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1275
1276 /* Stopping point for hardware truncation */
1277 thresh = (size - 8) / sizeof(u32);
1278
5f06eba4 1279 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1280 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1281
5f06eba4
SH		 1282 /* Compute residue after pages */
1283 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1284
5f06eba4
SH		 1285 /* Optimize to handle small packets and headers */
1286 if (size < copybreak)
1287 size = copybreak;
1288 if (size < ETH_HLEN)
1289 size = ETH_HLEN;
14d0263f 1290
14d0263f
SH		 1291 sky2->rx_data_size = size;
1292
1293 /* Fill Rx ring */
793b883e 1294 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1295 re = sky2->rx_ring + i;
cd28ab6a 1296
14d0263f 1297 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1298 if (!re->skb)
1299 goto nomem;
1300
14d0263f
SH		 1301 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1302 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1303 }
1304
a1433ac4
SH		 1305 /*
1306 * The receiver hangs if it receives frames larger than the
1307 * packet buffer. As a workaround, truncate oversize frames, but
1308 * the register is limited to 9 bits, so if you do frames > 2052
1309 * you better get the MTU right!
1310 */
a1433ac4
SH		 1311 if (thresh > 0x1ff)
1312 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1313 else {
1314 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1315 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1316 }
1317
6b1a3aef 1318 /* Tell chip about available buffers */
55c9dd35 1319 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1320 return 0;
1321nomem:
1322 sky2_rx_clean(sky2);
1323 return -ENOMEM;
1324}
1325
1326/* Bring up network interface. */
1327static int sky2_up(struct net_device *dev)
1328{
1329 struct sky2_port *sky2 = netdev_priv(dev);
1330 struct sky2_hw *hw = sky2->hw;
1331 unsigned port = sky2->port;
e0c28116 1332 u32 imask, ramsize;
ee7abb04 1333 int cap, err = -ENOMEM;
843a46f4 1334 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1335
ee7abb04
SH		 1336 /*
1337 * On dual port PCI-X card, there is an problem where status
1338 * can be received out of order due to split transactions
843a46f4 1339 */
ee7abb04
SH		 1340 if (otherdev && netif_running(otherdev) &&
1341 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1342 u16 cmd;
1343
b32f40c4 1344 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1345 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1346 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1347
ee7abb04 1348 }
843a46f4 1349
cd28ab6a
SH		 1350 if (netif_msg_ifup(sky2))
1351 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1352
55d7b4e6
SH		 1353 netif_carrier_off(dev);
1354
cd28ab6a
SH		 1355 /* must be power of 2 */
1356 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1357 TX_RING_SIZE *
1358 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1359 &sky2->tx_le_map);
1360 if (!sky2->tx_le)
1361 goto err_out;
1362
6cdbbdf3 1363 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1364 GFP_KERNEL);
1365 if (!sky2->tx_ring)
1366 goto err_out;
88f5f0ca
SH		 1367
1368 tx_init(sky2);
cd28ab6a
SH		 1369
1370 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1371 &sky2->rx_le_map);
1372 if (!sky2->rx_le)
1373 goto err_out;
1374 memset(sky2->rx_le, 0, RX_LE_BYTES);
1375
291ea614 1376 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1377 GFP_KERNEL);
1378 if (!sky2->rx_ring)
1379 goto err_out;
1380
d3bcfbeb 1381 sky2_phy_power(hw, port, 1);
1382
cd28ab6a
SH		 1383 sky2_mac_init(hw, port);
1384
e0c28116
SH		 1385 /* Register is number of 4K blocks on internal RAM buffer. */
1386 ramsize = sky2_read8(hw, B2_E_0) * 4;
1387 if (ramsize > 0) {
67712901 1388 u32 rxspace;
cd28ab6a 1389
e0c28116 1390 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1391 if (ramsize < 16)
1392 rxspace = ramsize / 2;
1393 else
1394 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1395
67712901
SH		 1396 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1397 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1398
1399 /* Make sure SyncQ is disabled */
1400 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1401 RB_RST_SET);
1402 }
793b883e 1403
af4ed7e6 1404 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1405
69161611
SH		 1406 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1407 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1408 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1409
977bdf06 1410 /* Set almost empty threshold */
c2716fb4
SH		 1411 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1412 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1413 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1414
6b1a3aef 1415 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1416 TX_RING_SIZE - 1);
cd28ab6a 1417
6b1a3aef 1418 err = sky2_rx_start(sky2);
6de16237 1419 if (err)
cd28ab6a
SH		 1420 goto err_out;
1421
cd28ab6a 1422 /* Enable interrupts from phy/mac for port */
e07b1aa8 1423 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1424 imask |= portirq_msk[port];
e07b1aa8
SH		 1425 sky2_write32(hw, B0_IMSK, imask);
1426
a7bffe72 1427 sky2_set_multicast(dev);
cd28ab6a
SH		 1428 return 0;
1429
1430err_out:
1b537565 1431 if (sky2->rx_le) {
cd28ab6a
SH		 1432 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1433 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1434 sky2->rx_le = NULL;
1435 }
1436 if (sky2->tx_le) {
cd28ab6a
SH		 1437 pci_free_consistent(hw->pdev,
1438 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1439 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1440 sky2->tx_le = NULL;
1441 }
1442 kfree(sky2->tx_ring);
1443 kfree(sky2->rx_ring);
cd28ab6a 1444
1b537565
SH		 1445 sky2->tx_ring = NULL;
1446 sky2->rx_ring = NULL;
cd28ab6a
SH		 1447 return err;
1448}
1449
793b883e
SH		 1450/* Modular subtraction in ring */
1451static inline int tx_dist(unsigned tail, unsigned head)
1452{
cb5d9547 1453 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1454}
cd28ab6a 1455
793b883e
SH		 1456/* Number of list elements available for next tx */
1457static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1458{
793b883e 1459 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1460}
1461
793b883e 1462/* Estimate of number of transmit list elements required */
28bd181a 1463static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1464{
793b883e
SH		 1465 unsigned count;
1466
1467 count = sizeof(dma_addr_t) / sizeof(u32);
1468 count += skb_shinfo(skb)->nr_frags * count;
1469
89114afd 1470 if (skb_is_gso(skb))
793b883e
SH		 1471 ++count;
1472
84fa7933 1473 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1474 ++count;
1475
1476 return count;
cd28ab6a
SH		 1477}
1478
793b883e
SH		 1479/*
1480 * Put one packet in ring for transmit.
1481 * A single packet can generate multiple list elements, and
1482 * the number of ring elements will probably be less than the number
1483 * of list elements used.
1484 */
cd28ab6a
SH		 1485static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1486{
1487 struct sky2_port *sky2 = netdev_priv(dev);
1488 struct sky2_hw *hw = sky2->hw;
d1f13708 1489 struct sky2_tx_le *le = NULL;
6cdbbdf3 1490 struct tx_ring_info *re;
cd28ab6a
SH		 1491 unsigned i, len;
1492 dma_addr_t mapping;
cd28ab6a
SH		 1493 u16 mss;
1494 u8 ctrl;
1495
2bb8c262
SH		 1496 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1497 return NETDEV_TX_BUSY;
cd28ab6a 1498
793b883e 1499 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1500 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1501 dev->name, sky2->tx_prod, skb->len);
1502
cd28ab6a
SH		 1503 len = skb_headlen(skb);
1504 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1505
86c6887e
SH		 1506 /* Send high bits if needed */
1507 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1508 le = get_tx_le(sky2);
86c6887e 1509 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e 1510 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1511 }
cd28ab6a
SH		 1512
1513 /* Check for TCP Segmentation Offload */
7967168c 1514 mss = skb_shinfo(skb)->gso_size;
793b883e 1515 if (mss != 0) {
ea76e635
SH		 1516
1517 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1518 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1519
1520 if (mss != sky2->tx_last_mss) {
1521 le = get_tx_le(sky2);
1522 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1523
1524 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1525 le->opcode = OP_MSS | HW_OWNER;
1526 else
1527 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1528 sky2->tx_last_mss = mss;
1529 }
cd28ab6a
SH		 1530 }
1531
cd28ab6a 1532 ctrl = 0;
d1f13708 1533#ifdef SKY2_VLAN_TAG_USED
1534 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1535 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1536 if (!le) {
1537 le = get_tx_le(sky2);
f65b138c 1538 le->addr = 0;
d1f13708 1539 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1540 } else
1541 le->opcode |= OP_VLAN;
1542 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1543 ctrl |= INS_VLAN;
1544 }
1545#endif
1546
1547 /* Handle TCP checksum offload */
84fa7933 1548 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1549 /* On Yukon EX (some versions) encoding change. */
ea76e635 1550 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1551 ctrl |= CALSUM; /* auto checksum */
1552 else {
1553 const unsigned offset = skb_transport_offset(skb);
1554 u32 tcpsum;
1555
1556 tcpsum = offset << 16; /* sum start */
1557 tcpsum |= offset + skb->csum_offset; /* sum write */
1558
1559 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1560 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1561 ctrl |= UDPTCP;
1562
1563 if (tcpsum != sky2->tx_tcpsum) {
1564 sky2->tx_tcpsum = tcpsum;
1565
1566 le = get_tx_le(sky2);
1567 le->addr = cpu_to_le32(tcpsum);
1568 le->length = 0; /* initial checksum value */
1569 le->ctrl = 1; /* one packet */
1570 le->opcode = OP_TCPLISW | HW_OWNER;
1571 }
1d179332 1572 }
cd28ab6a
SH		 1573 }
1574
1575 le = get_tx_le(sky2);
f65b138c 1576 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1577 le->length = cpu_to_le16(len);
1578 le->ctrl = ctrl;
793b883e 1579 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1580
291ea614 1581 re = tx_le_re(sky2, le);
cd28ab6a 1582 re->skb = skb;
6cdbbdf3 1583 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1584 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1585
1586 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1587 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1588
1589 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1590 frag->size, PCI_DMA_TODEVICE);
86c6887e
SH		 1591
1592 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1593 le = get_tx_le(sky2);
86c6887e 1594 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e
SH		 1595 le->ctrl = 0;
1596 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1597 }
1598
1599 le = get_tx_le(sky2);
f65b138c 1600 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1601 le->length = cpu_to_le16(frag->size);
1602 le->ctrl = ctrl;
793b883e 1603 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1604
291ea614
SH		 1605 re = tx_le_re(sky2, le);
1606 re->skb = skb;
1607 pci_unmap_addr_set(re, mapaddr, mapping);
1608 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1609 }
6cdbbdf3 1610
cd28ab6a
SH		 1611 le->ctrl |= EOP;
1612
97bda706 1613 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1614 netif_stop_queue(dev);
b19666d9 1615
290d4de5 1616 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1617
cd28ab6a
SH		 1618 dev->trans_start = jiffies;
1619 return NETDEV_TX_OK;
1620}
1621
cd28ab6a 1622/*
793b883e
SH		 1623 * Free ring elements from starting at tx_cons until "done"
1624 *
1625 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1626 * buffers so make sure not to free skb to early.
cd28ab6a 1627 */
d11c13e7 1628static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1629{
d11c13e7 1630 struct net_device *dev = sky2->netdev;
af2a58ac 1631 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1632 unsigned idx;
cd28ab6a 1633
0e3ff6aa 1634 BUG_ON(done >= TX_RING_SIZE);
2224795d 1635
291ea614
SH		 1636 for (idx = sky2->tx_cons; idx != done;
1637 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1638 struct sky2_tx_le *le = sky2->tx_le + idx;
1639 struct tx_ring_info *re = sky2->tx_ring + idx;
1640
1641 switch(le->opcode & ~HW_OWNER) {
1642 case OP_LARGESEND:
1643 case OP_PACKET:
1644 pci_unmap_single(pdev,
1645 pci_unmap_addr(re, mapaddr),
1646 pci_unmap_len(re, maplen),
1647 PCI_DMA_TODEVICE);
af2a58ac 1648 break;
291ea614
SH		 1649 case OP_BUFFER:
1650 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1651 pci_unmap_len(re, maplen),
734d1868 1652 PCI_DMA_TODEVICE);
291ea614
SH		 1653 break;
1654 }
1655
1656 if (le->ctrl & EOP) {
1657 if (unlikely(netif_msg_tx_done(sky2)))
1658 printk(KERN_DEBUG "%s: tx done %u\n",
1659 dev->name, idx);
3cf26753 1660
7138a0f5
SH		 1661 dev->stats.tx_packets++;
1662 dev->stats.tx_bytes += re->skb->len;
2bf56fe2 1663
794b2bd2 1664 dev_kfree_skb_any(re->skb);
3cf26753 1665 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1666 }
793b883e 1667 }
793b883e 1668
291ea614 1669 sky2->tx_cons = idx;
50432cb5
SH		 1670 smp_mb();
1671
22e11703 1672 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1673 netif_wake_queue(dev);
cd28ab6a
SH		 1674}
1675
1676/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1677static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1678{
2bb8c262
SH		 1679 struct sky2_port *sky2 = netdev_priv(dev);
1680
1681 netif_tx_lock_bh(dev);
d11c13e7 1682 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1683 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1684}
1685
1686/* Network shutdown */
1687static int sky2_down(struct net_device *dev)
1688{
1689 struct sky2_port *sky2 = netdev_priv(dev);
1690 struct sky2_hw *hw = sky2->hw;
1691 unsigned port = sky2->port;
1692 u16 ctrl;
e07b1aa8 1693 u32 imask;
cd28ab6a 1694
1b537565
SH		 1695 /* Never really got started! */
1696 if (!sky2->tx_le)
1697 return 0;
1698
cd28ab6a
SH		 1699 if (netif_msg_ifdown(sky2))
1700 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1701
018d1c66 1702 /* Stop more packets from being queued */
cd28ab6a
SH		 1703 netif_stop_queue(dev);
1704
ebc646f6
SH		 1705 /* Disable port IRQ */
1706 imask = sky2_read32(hw, B0_IMSK);
1707 imask &= ~portirq_msk[port];
1708 sky2_write32(hw, B0_IMSK, imask);
1709
6de16237
SH		 1710 synchronize_irq(hw->pdev->irq);
1711
d3bcfbeb 1712 sky2_gmac_reset(hw, port);
793b883e 1713
cd28ab6a
SH		 1714 /* Stop transmitter */
1715 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1716 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1717
1718 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1719 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1720
1721 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1722 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1723 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1724
6de16237
SH		 1725 /* Make sure no packets are pending */
1726 napi_synchronize(&hw->napi);
1727
cd28ab6a
SH		 1728 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1729
1730 /* Workaround shared GMAC reset */
793b883e
SH		 1731 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1732 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1733 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1734
1735 /* Disable Force Sync bit and Enable Alloc bit */
1736 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1737 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1738
1739 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1740 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1741 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1742
1743 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1744 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1745 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1746
1747 /* Reset the Tx prefetch units */
1748 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1749 PREF_UNIT_RST_SET);
1750
1751 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1752
6b1a3aef 1753 sky2_rx_stop(sky2);
cd28ab6a
SH		 1754
1755 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1756 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1757
d3bcfbeb 1758 sky2_phy_power(hw, port, 0);
1759
55d7b4e6
SH		 1760 netif_carrier_off(dev);
1761
d571b694 1762 /* turn off LED's */
cd28ab6a
SH		 1763 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1764
2bb8c262 1765 sky2_tx_clean(dev);
cd28ab6a
SH		 1766 sky2_rx_clean(sky2);
1767
1768 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1769 sky2->rx_le, sky2->rx_le_map);
1770 kfree(sky2->rx_ring);
1771
1772 pci_free_consistent(hw->pdev,
1773 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1774 sky2->tx_le, sky2->tx_le_map);
1775 kfree(sky2->tx_ring);
1776
1b537565
SH		 1777 sky2->tx_le = NULL;
1778 sky2->rx_le = NULL;
1779
1780 sky2->rx_ring = NULL;
1781 sky2->tx_ring = NULL;
1782
cd28ab6a
SH		 1783 return 0;
1784}
1785
1786static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1787{
ea76e635 1788 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1789 return SPEED_1000;
1790
05745c4a
SH		 1791 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1792 if (aux & PHY_M_PS_SPEED_100)
1793 return SPEED_100;
1794 else
1795 return SPEED_10;
1796 }
cd28ab6a
SH		 1797
1798 switch (aux & PHY_M_PS_SPEED_MSK) {
1799 case PHY_M_PS_SPEED_1000:
1800 return SPEED_1000;
1801 case PHY_M_PS_SPEED_100:
1802 return SPEED_100;
1803 default:
1804 return SPEED_10;
1805 }
1806}
1807
1808static void sky2_link_up(struct sky2_port *sky2)
1809{
1810 struct sky2_hw *hw = sky2->hw;
1811 unsigned port = sky2->port;
1812 u16 reg;
16ad91e1
SH		 1813 static const char *fc_name[] = {
1814 [FC_NONE] = "none",
1815 [FC_TX] = "tx",
1816 [FC_RX] = "rx",
1817 [FC_BOTH] = "both",
1818 };
cd28ab6a 1819
cd28ab6a 1820 /* enable Rx/Tx */
2eaba1a2 1821 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1822 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1823 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1824
1825 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1826
1827 netif_carrier_on(sky2->netdev);
cd28ab6a 1828
75e80683 1829 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1830
cd28ab6a 1831 /* Turn on link LED */
793b883e 1832 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1833 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1834
1835 if (netif_msg_link(sky2))
1836 printk(KERN_INFO PFX
d571b694 1837 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1838 sky2->netdev->name, sky2->speed,
1839 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1840 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1841}
1842
1843static void sky2_link_down(struct sky2_port *sky2)
1844{
1845 struct sky2_hw *hw = sky2->hw;
1846 unsigned port = sky2->port;
1847 u16 reg;
1848
1849 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1850
1851 reg = gma_read16(hw, port, GM_GP_CTRL);
1852 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1853 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1854
cd28ab6a 1855 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1856
1857 /* Turn on link LED */
1858 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1859
1860 if (netif_msg_link(sky2))
1861 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1862
cd28ab6a
SH		 1863 sky2_phy_init(hw, port);
1864}
1865
16ad91e1
SH		 1866static enum flow_control sky2_flow(int rx, int tx)
1867{
1868 if (rx)
1869 return tx ? FC_BOTH : FC_RX;
1870 else
1871 return tx ? FC_TX : FC_NONE;
1872}
1873
793b883e
SH		 1874static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1875{
1876 struct sky2_hw *hw = sky2->hw;
1877 unsigned port = sky2->port;
da4c1ff4 1878 u16 advert, lpa;
793b883e 1879
da4c1ff4 1880 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1881 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1882 if (lpa & PHY_M_AN_RF) {
1883 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1884 return -1;
1885 }
1886
793b883e
SH		 1887 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1888 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1889 sky2->netdev->name);
1890 return -1;
1891 }
1892
793b883e 1893 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1894 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1895
da4c1ff4
SH		 1896 /* Since the pause result bits seem to in different positions on
1897 * different chips. look at registers.
1898 */
ea76e635 1899 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 1900 /* Shift for bits in fiber PHY */
1901 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1902 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1903
1904 if (advert & ADVERTISE_1000XPAUSE)
1905 advert |= ADVERTISE_PAUSE_CAP;
1906 if (advert & ADVERTISE_1000XPSE_ASYM)
1907 advert |= ADVERTISE_PAUSE_ASYM;
1908 if (lpa & LPA_1000XPAUSE)
1909 lpa |= LPA_PAUSE_CAP;
1910 if (lpa & LPA_1000XPAUSE_ASYM)
1911 lpa |= LPA_PAUSE_ASYM;
1912 }
793b883e 1913
da4c1ff4
SH		 1914 sky2->flow_status = FC_NONE;
1915 if (advert & ADVERTISE_PAUSE_CAP) {
1916 if (lpa & LPA_PAUSE_CAP)
1917 sky2->flow_status = FC_BOTH;
1918 else if (advert & ADVERTISE_PAUSE_ASYM)
1919 sky2->flow_status = FC_RX;
1920 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1921 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1922 sky2->flow_status = FC_TX;
1923 }
793b883e 1924
16ad91e1 1925 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1926 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1927 sky2->flow_status = FC_NONE;
2eaba1a2 1928
da4c1ff4 1929 if (sky2->flow_status & FC_TX)
793b883e
SH		 1930 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1931 else
1932 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1933
1934 return 0;
1935}
cd28ab6a 1936
e07b1aa8
SH		 1937/* Interrupt from PHY */
1938static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1939{
e07b1aa8
SH		 1940 struct net_device *dev = hw->dev[port];
1941 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1942 u16 istatus, phystat;
1943
ebc646f6
SH		 1944 if (!netif_running(dev))
1945 return;
1946
e07b1aa8
SH		 1947 spin_lock(&sky2->phy_lock);
1948 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1949 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1950
cd28ab6a
SH		 1951 if (netif_msg_intr(sky2))
1952 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1953 sky2->netdev->name, istatus, phystat);
1954
2eaba1a2 1955 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1956 if (sky2_autoneg_done(sky2, phystat) == 0)
1957 sky2_link_up(sky2);
1958 goto out;
1959 }
cd28ab6a 1960
793b883e
SH		 1961 if (istatus & PHY_M_IS_LSP_CHANGE)
1962 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1963
793b883e
SH		 1964 if (istatus & PHY_M_IS_DUP_CHANGE)
1965 sky2->duplex =
1966 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1967
793b883e
SH		 1968 if (istatus & PHY_M_IS_LST_CHANGE) {
1969 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1970 sky2_link_up(sky2);
793b883e
SH		 1971 else
1972 sky2_link_down(sky2);
cd28ab6a 1973 }
793b883e 1974out:
e07b1aa8 1975 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1976}
1977
62335ab0 1978/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1979 * and tx queue is full (stopped).
1980 */
cd28ab6a
SH		 1981static void sky2_tx_timeout(struct net_device *dev)
1982{
1983 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1984 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1985
1986 if (netif_msg_timer(sky2))
1987 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1988
8f24664d 1989 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1990 dev->name, sky2->tx_cons, sky2->tx_prod,
1991 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1992 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1993
81906791
SH		 1994 /* can't restart safely under softirq */
1995 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1996}
1997
1998static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1999{
6b1a3aef 2000 struct sky2_port *sky2 = netdev_priv(dev);
2001 struct sky2_hw *hw = sky2->hw;
b628ed98 2002 unsigned port = sky2->port;
6b1a3aef 2003 int err;
2004 u16 ctl, mode;
e07b1aa8 2005 u32 imask;
cd28ab6a
SH		 2006
2007 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2008 return -EINVAL;
2009
05745c4a
SH		 2010 if (new_mtu > ETH_DATA_LEN &&
2011 (hw->chip_id == CHIP_ID_YUKON_FE ||
2012 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2013 return -EINVAL;
2014
6b1a3aef 2015 if (!netif_running(dev)) {
2016 dev->mtu = new_mtu;
2017 return 0;
2018 }
2019
e07b1aa8 2020 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 2021 sky2_write32(hw, B0_IMSK, 0);
2022
018d1c66 2023 dev->trans_start = jiffies; /* prevent tx timeout */
2024 netif_stop_queue(dev);
bea3348e 2025 napi_disable(&hw->napi);
018d1c66 2026
e07b1aa8
SH		 2027 synchronize_irq(hw->pdev->irq);
2028
e0c28116 2029 if (sky2_read8(hw, B2_E_0) == 0)
69161611 2030 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2031
2032 ctl = gma_read16(hw, port, GM_GP_CTRL);
2033 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 2034 sky2_rx_stop(sky2);
2035 sky2_rx_clean(sky2);
cd28ab6a
SH		 2036
2037 dev->mtu = new_mtu;
14d0263f 2038
6b1a3aef 2039 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2040 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2041
2042 if (dev->mtu > ETH_DATA_LEN)
2043 mode |= GM_SMOD_JUMBO_ENA;
2044
b628ed98 2045 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2046
b628ed98 2047 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2048
6b1a3aef 2049 err = sky2_rx_start(sky2);
e07b1aa8 2050 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2051
d1d08d12 2052 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2053 napi_enable(&hw->napi);
2054
1b537565
SH		 2055 if (err)
2056 dev_close(dev);
2057 else {
b628ed98 2058 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2059
1b537565
SH		 2060 netif_wake_queue(dev);
2061 }
2062
cd28ab6a
SH		 2063 return err;
2064}
2065
14d0263f
SH		 2066/* For small just reuse existing skb for next receive */
2067static struct sk_buff *receive_copy(struct sky2_port *sky2,
2068 const struct rx_ring_info *re,
2069 unsigned length)
2070{
2071 struct sk_buff *skb;
2072
2073 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2074 if (likely(skb)) {
2075 skb_reserve(skb, 2);
2076 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2077 length, PCI_DMA_FROMDEVICE);
d626f62b 2078 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2079 skb->ip_summed = re->skb->ip_summed;
2080 skb->csum = re->skb->csum;
2081 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2082 length, PCI_DMA_FROMDEVICE);
2083 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2084 skb_put(skb, length);
14d0263f
SH		 2085 }
2086 return skb;
2087}
2088
2089/* Adjust length of skb with fragments to match received data */
2090static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2091 unsigned int length)
2092{
2093 int i, num_frags;
2094 unsigned int size;
2095
2096 /* put header into skb */
2097 size = min(length, hdr_space);
2098 skb->tail += size;
2099 skb->len += size;
2100 length -= size;
2101
2102 num_frags = skb_shinfo(skb)->nr_frags;
2103 for (i = 0; i < num_frags; i++) {
2104 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2105
2106 if (length == 0) {
2107 /* don't need this page */
2108 __free_page(frag->page);
2109 --skb_shinfo(skb)->nr_frags;
2110 } else {
2111 size = min(length, (unsigned) PAGE_SIZE);
2112
2113 frag->size = size;
2114 skb->data_len += size;
2115 skb->truesize += size;
2116 skb->len += size;
2117 length -= size;
2118 }
2119 }
2120}
2121
2122/* Normal packet - take skb from ring element and put in a new one */
2123static struct sk_buff *receive_new(struct sky2_port *sky2,
2124 struct rx_ring_info *re,
2125 unsigned int length)
2126{
2127 struct sk_buff *skb, *nskb;
2128 unsigned hdr_space = sky2->rx_data_size;
2129
14d0263f
SH		 2130 /* Don't be tricky about reusing pages (yet) */
2131 nskb = sky2_rx_alloc(sky2);
2132 if (unlikely(!nskb))
2133 return NULL;
2134
2135 skb = re->skb;
2136 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2137
2138 prefetch(skb->data);
2139 re->skb = nskb;
2140 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2141
2142 if (skb_shinfo(skb)->nr_frags)
2143 skb_put_frags(skb, hdr_space, length);
2144 else
489b10c1 2145 skb_put(skb, length);
14d0263f
SH		 2146 return skb;
2147}
2148
cd28ab6a
SH		 2149/*
2150 * Receive one packet.
d571b694 2151 * For larger packets, get new buffer.
cd28ab6a 2152 */
497d7c86 2153static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2154 u16 length, u32 status)
2155{
497d7c86 2156 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2157 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2158 struct sk_buff *skb = NULL;
d6532232
SH		 2159 u16 count = (status & GMR_FS_LEN) >> 16;
2160
2161#ifdef SKY2_VLAN_TAG_USED
2162 /* Account for vlan tag */
2163 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2164 count -= VLAN_HLEN;
2165#endif
cd28ab6a
SH		 2166
2167 if (unlikely(netif_msg_rx_status(sky2)))
2168 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2169 dev->name, sky2->rx_next, status, length);
cd28ab6a 2170
793b883e 2171 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2172 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2173
3b12e014
SH		 2174 /* This chip has hardware problems that generates bogus status.
2175 * So do only marginal checking and expect higher level protocols
2176 * to handle crap frames.
2177 */
2178 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2179 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2180 length != count)
2181 goto okay;
2182
42eeea01 2183 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2184 goto error;
2185
42eeea01 2186 if (!(status & GMR_FS_RX_OK))
2187 goto resubmit;
2188
d6532232
SH		 2189 /* if length reported by DMA does not match PHY, packet was truncated */
2190 if (length != count)
3b12e014 2191 goto len_error;
71749531 2192
3b12e014 2193okay:
14d0263f
SH		 2194 if (length < copybreak)
2195 skb = receive_copy(sky2, re, length);
2196 else
2197 skb = receive_new(sky2, re, length);
793b883e 2198resubmit:
14d0263f 2199 sky2_rx_submit(sky2, re);
79e57d32 2200
cd28ab6a
SH		 2201 return skb;
2202
3b12e014 2203len_error:
71749531
SH		 2204 /* Truncation of overlength packets
2205 causes PHY length to not match MAC length */
7138a0f5 2206 ++dev->stats.rx_length_errors;
d6532232 2207 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2208 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2209 dev->name, status, length);
d6532232 2210 goto resubmit;
71749531 2211
cd28ab6a 2212error:
7138a0f5 2213 ++dev->stats.rx_errors;
b6d77734 2214 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2215 dev->stats.rx_over_errors++;
b6d77734
SH		 2216 goto resubmit;
2217 }
6e15b712 2218
3be92a70 2219 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2220 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2221 dev->name, status, length);
793b883e
SH		 2222
2223 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2224 dev->stats.rx_length_errors++;
cd28ab6a 2225 if (status & GMR_FS_FRAGMENT)
7138a0f5 2226 dev->stats.rx_frame_errors++;
cd28ab6a 2227 if (status & GMR_FS_CRC_ERR)
7138a0f5 2228 dev->stats.rx_crc_errors++;
79e57d32 2229
793b883e 2230 goto resubmit;
cd28ab6a
SH		 2231}
2232
e07b1aa8
SH		 2233/* Transmit complete */
2234static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2235{
e07b1aa8 2236 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2237
e07b1aa8 2238 if (netif_running(dev)) {
2bb8c262 2239 netif_tx_lock(dev);
e07b1aa8 2240 sky2_tx_complete(sky2, last);
2bb8c262 2241 netif_tx_unlock(dev);
2224795d 2242 }
cd28ab6a
SH		 2243}
2244
e07b1aa8 2245/* Process status response ring */
26691830 2246static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2247{
e07b1aa8 2248 int work_done = 0;
55c9dd35 2249 unsigned rx[2] = { 0, 0 };
a8fd6266 2250
af2a58ac 2251 rmb();
26691830 2252 do {
55c9dd35 2253 struct sky2_port *sky2;
13210ce5 2254 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2255 unsigned port;
13210ce5 2256 struct net_device *dev;
cd28ab6a 2257 struct sk_buff *skb;
cd28ab6a
SH		 2258 u32 status;
2259 u16 length;
ab5adecb
SH		 2260 u8 opcode = le->opcode;
2261
2262 if (!(opcode & HW_OWNER))
2263 break;
cd28ab6a 2264
cb5d9547 2265 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2266
ab5adecb 2267 port = le->css & CSS_LINK_BIT;
69161611 2268 dev = hw->dev[port];
13210ce5 2269 sky2 = netdev_priv(dev);
f65b138c
SH		 2270 length = le16_to_cpu(le->length);
2271 status = le32_to_cpu(le->status);
cd28ab6a 2272
ab5adecb
SH		 2273 le->opcode = 0;
2274 switch (opcode & ~HW_OWNER) {
cd28ab6a 2275 case OP_RXSTAT:
55c9dd35 2276 ++rx[port];
497d7c86 2277 skb = sky2_receive(dev, length, status);
3225b919 2278 if (unlikely(!skb)) {
7138a0f5 2279 dev->stats.rx_dropped++;
55c9dd35 2280 break;
3225b919 2281 }
13210ce5 2282
69161611 2283 /* This chip reports checksum status differently */
05745c4a 2284 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2285 if (sky2->rx_csum &&
2286 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2287 (le->css & CSS_TCPUDPCSOK))
2288 skb->ip_summed = CHECKSUM_UNNECESSARY;
2289 else
2290 skb->ip_summed = CHECKSUM_NONE;
2291 }
2292
13210ce5 2293 skb->protocol = eth_type_trans(skb, dev);
7138a0f5
SH		 2294 dev->stats.rx_packets++;
2295 dev->stats.rx_bytes += skb->len;
13210ce5 2296 dev->last_rx = jiffies;
2297
d1f13708 2298#ifdef SKY2_VLAN_TAG_USED
2299 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2300 vlan_hwaccel_receive_skb(skb,
2301 sky2->vlgrp,
2302 be16_to_cpu(sky2->rx_tag));
2303 } else
2304#endif
cd28ab6a 2305 netif_receive_skb(skb);
13210ce5 2306
22e11703 2307 /* Stop after net poll weight */
13210ce5 2308 if (++work_done >= to_do)
2309 goto exit_loop;
cd28ab6a
SH		 2310 break;
2311
d1f13708 2312#ifdef SKY2_VLAN_TAG_USED
2313 case OP_RXVLAN:
2314 sky2->rx_tag = length;
2315 break;
2316
2317 case OP_RXCHKSVLAN:
2318 sky2->rx_tag = length;
2319 /* fall through */
2320#endif
cd28ab6a 2321 case OP_RXCHKS:
87418307
SH		 2322 if (!sky2->rx_csum)
2323 break;
2324
05745c4a
SH		 2325 /* If this happens then driver assuming wrong format */
2326 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2327 if (net_ratelimit())
2328 printk(KERN_NOTICE "%s: unexpected"
2329 " checksum status\n",
2330 dev->name);
69161611 2331 break;
05745c4a 2332 }
69161611 2333
87418307
SH		 2334 /* Both checksum counters are programmed to start at
2335 * the same offset, so unless there is a problem they
2336 * should match. This failure is an early indication that
2337 * hardware receive checksumming won't work.
2338 */
2339 if (likely(status >> 16 == (status & 0xffff))) {
2340 skb = sky2->rx_ring[sky2->rx_next].skb;
2341 skb->ip_summed = CHECKSUM_COMPLETE;
2342 skb->csum = status & 0xffff;
2343 } else {
2344 printk(KERN_NOTICE PFX "%s: hardware receive "
2345 "checksum problem (status = %#x)\n",
2346 dev->name, status);
2347 sky2->rx_csum = 0;
2348 sky2_write32(sky2->hw,
69161611 2349 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2350 BMU_DIS_RX_CHKSUM);
2351 }
cd28ab6a
SH		 2352 break;
2353
2354 case OP_TXINDEXLE:
13b97b74 2355 /* TX index reports status for both ports */
f55925d7
SH		 2356 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2357 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2358 if (hw->dev[1])
2359 sky2_tx_done(hw->dev[1],
2360 ((status >> 24) & 0xff)
2361 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2362 break;
2363
cd28ab6a
SH		 2364 default:
2365 if (net_ratelimit())
793b883e 2366 printk(KERN_WARNING PFX
ab5adecb 2367 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2368 }
26691830 2369 } while (hw->st_idx != idx);
cd28ab6a 2370
fe2a24df
SH		 2371 /* Fully processed status ring so clear irq */
2372 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2373
13210ce5 2374exit_loop:
55c9dd35
SH		 2375 if (rx[0])
2376 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2377
55c9dd35
SH		 2378 if (rx[1])
2379 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2380
e07b1aa8 2381 return work_done;
cd28ab6a
SH		 2382}
2383
2384static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2385{
2386 struct net_device *dev = hw->dev[port];
2387
3be92a70
SH		 2388 if (net_ratelimit())
2389 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2390 dev->name, status);
cd28ab6a
SH		 2391
2392 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2393 if (net_ratelimit())
2394 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2395 dev->name);
cd28ab6a
SH		 2396 /* Clear IRQ */
2397 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2398 }
2399
2400 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2401 if (net_ratelimit())
2402 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2403 dev->name);
cd28ab6a
SH		 2404
2405 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2406 }
2407
2408 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2409 if (net_ratelimit())
2410 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2411 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2412 }
2413
2414 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2415 if (net_ratelimit())
2416 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2417 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2418 }
2419
2420 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2421 if (net_ratelimit())
2422 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2423 dev->name);
cd28ab6a
SH		 2424 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2425 }
2426}
2427
2428static void sky2_hw_intr(struct sky2_hw *hw)
2429{
555382cb 2430 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2431 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2432 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2433
2434 status &= hwmsk;
cd28ab6a 2435
793b883e 2436 if (status & Y2_IS_TIST_OV)
cd28ab6a 2437 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2438
2439 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2440 u16 pci_err;
2441
82637e80 2442 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2443 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2444 if (net_ratelimit())
555382cb 2445 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2446 pci_err);
cd28ab6a 2447
b32f40c4 2448 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2449 pci_err | PCI_STATUS_ERROR_BITS);
82637e80 2450 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2451 }
2452
2453 if (status & Y2_IS_PCI_EXP) {
d571b694 2454 /* PCI-Express uncorrectable Error occurred */
555382cb 2455 u32 err;
cd28ab6a 2456
82637e80 2457 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2458 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2459 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2460 0xfffffffful);
3be92a70 2461 if (net_ratelimit())
555382cb 2462 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2463
7782c8c4 2464 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
82637e80 2465 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2466 }
2467
2468 if (status & Y2_HWE_L1_MASK)
2469 sky2_hw_error(hw, 0, status);
2470 status >>= 8;
2471 if (status & Y2_HWE_L1_MASK)
2472 sky2_hw_error(hw, 1, status);
2473}
2474
2475static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2476{
2477 struct net_device *dev = hw->dev[port];
2478 struct sky2_port *sky2 = netdev_priv(dev);
2479 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2480
2481 if (netif_msg_intr(sky2))
2482 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2483 dev->name, status);
2484
a3caeada
SH		 2485 if (status & GM_IS_RX_CO_OV)
2486 gma_read16(hw, port, GM_RX_IRQ_SRC);
2487
2488 if (status & GM_IS_TX_CO_OV)
2489 gma_read16(hw, port, GM_TX_IRQ_SRC);
2490
cd28ab6a 2491 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2492 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2493 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2494 }
2495
2496 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2497 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2498 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2499 }
cd28ab6a
SH		 2500}
2501
40b01727
SH		 2502/* This should never happen it is a bug. */
2503static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2504 u16 q, unsigned ring_size)
d257924e
SH		 2505{
2506 struct net_device *dev = hw->dev[port];
2507 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2508 unsigned idx;
2509 const u64 *le = (q == Q_R1 || q == Q_R2)
2510 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2511
40b01727
SH		 2512 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2513 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2514 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2515 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2516
40b01727 2517 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2518}
cd28ab6a 2519
75e80683
SH		 2520static int sky2_rx_hung(struct net_device *dev)
2521{
2522 struct sky2_port *sky2 = netdev_priv(dev);
2523 struct sky2_hw *hw = sky2->hw;
2524 unsigned port = sky2->port;
2525 unsigned rxq = rxqaddr[port];
2526 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2527 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2528 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2529 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2530
2531 /* If idle and MAC or PCI is stuck */
2532 if (sky2->check.last == dev->last_rx &&
2533 ((mac_rp == sky2->check.mac_rp &&
2534 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2535 /* Check if the PCI RX hang */
2536 (fifo_rp == sky2->check.fifo_rp &&
2537 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2538 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2539 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2540 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2541 return 1;
2542 } else {
2543 sky2->check.last = dev->last_rx;
2544 sky2->check.mac_rp = mac_rp;
2545 sky2->check.mac_lev = mac_lev;
2546 sky2->check.fifo_rp = fifo_rp;
2547 sky2->check.fifo_lev = fifo_lev;
2548 return 0;
2549 }
2550}
2551
32c2c300 2552static void sky2_watchdog(unsigned long arg)
d27ed387 2553{
01bd7564 2554 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2555
75e80683 2556 /* Check for lost IRQ once a second */
32c2c300 2557 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2558 napi_schedule(&hw->napi);
75e80683
SH		 2559 } else {
2560 int i, active = 0;
2561
2562 for (i = 0; i < hw->ports; i++) {
bea3348e 2563 struct net_device *dev = hw->dev[i];
75e80683
SH		 2564 if (!netif_running(dev))
2565 continue;
2566 ++active;
2567
2568 /* For chips with Rx FIFO, check if stuck */
e0c28116 2569 if ((hw->flags & SKY2_HW_FIFO_HANG_CHECK) &&
75e80683
SH		 2570 sky2_rx_hung(dev)) {
2571 pr_info(PFX "%s: receiver hang detected\n",
2572 dev->name);
2573 schedule_work(&hw->restart_work);
2574 return;
2575 }
2576 }
2577
2578 if (active == 0)
2579 return;
32c2c300 2580 }
01bd7564 2581
75e80683 2582 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2583}
2584
40b01727
SH		 2585/* Hardware/software error handling */
2586static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2587{
40b01727
SH		 2588 if (net_ratelimit())
2589 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2590
1e5f1283
SH		 2591 if (status & Y2_IS_HW_ERR)
2592 sky2_hw_intr(hw);
d257924e 2593
1e5f1283
SH		 2594 if (status & Y2_IS_IRQ_MAC1)
2595 sky2_mac_intr(hw, 0);
cd28ab6a 2596
1e5f1283
SH		 2597 if (status & Y2_IS_IRQ_MAC2)
2598 sky2_mac_intr(hw, 1);
cd28ab6a 2599
1e5f1283 2600 if (status & Y2_IS_CHK_RX1)
40b01727 2601 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2602
1e5f1283 2603 if (status & Y2_IS_CHK_RX2)
40b01727 2604 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2605
1e5f1283 2606 if (status & Y2_IS_CHK_TXA1)
40b01727 2607 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2608
1e5f1283 2609 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2610 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2611}
2612
bea3348e 2613static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2614{
bea3348e 2615 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2616 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2617 int work_done = 0;
26691830 2618 u16 idx;
40b01727
SH		 2619
2620 if (unlikely(status & Y2_IS_ERROR))
2621 sky2_err_intr(hw, status);
2622
2623 if (status & Y2_IS_IRQ_PHY1)
2624 sky2_phy_intr(hw, 0);
2625
2626 if (status & Y2_IS_IRQ_PHY2)
2627 sky2_phy_intr(hw, 1);
cd28ab6a 2628
26691830
SH		 2629 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2630 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2631
2632 if (work_done >= work_limit)
26691830
SH		 2633 goto done;
2634 }
6f535763 2635
26691830
SH		 2636 /* Bug/Errata workaround?
2637 * Need to kick the TX irq moderation timer.
2638 */
2639 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2640 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2641 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2642 }
26691830
SH		 2643 napi_complete(napi);
2644 sky2_read32(hw, B0_Y2_SP_LISR);
2645done:
6f535763 2646
bea3348e 2647 return work_done;
e07b1aa8
SH		 2648}
2649
7d12e780 2650static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2651{
2652 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2653 u32 status;
2654
2655 /* Reading this mask interrupts as side effect */
2656 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2657 if (status == 0 || status == ~0)
2658 return IRQ_NONE;
793b883e 2659
e07b1aa8 2660 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2661
2662 napi_schedule(&hw->napi);
793b883e 2663
cd28ab6a
SH		 2664 return IRQ_HANDLED;
2665}
2666
2667#ifdef CONFIG_NET_POLL_CONTROLLER
2668static void sky2_netpoll(struct net_device *dev)
2669{
2670 struct sky2_port *sky2 = netdev_priv(dev);
2671
bea3348e 2672 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2673}
2674#endif
2675
2676/* Chip internal frequency for clock calculations */
05745c4a 2677static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2678{
793b883e 2679 switch (hw->chip_id) {
cd28ab6a 2680 case CHIP_ID_YUKON_EC:
5a5b1ea0 2681 case CHIP_ID_YUKON_EC_U:
93745494 2682 case CHIP_ID_YUKON_EX:
ed4d4161 2683 case CHIP_ID_YUKON_SUPR:
05745c4a
SH		 2684 return 125;
2685
cd28ab6a 2686 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2687 return 100;
2688
2689 case CHIP_ID_YUKON_FE_P:
2690 return 50;
2691
2692 case CHIP_ID_YUKON_XL:
2693 return 156;
2694
2695 default:
2696 BUG();
cd28ab6a
SH		 2697 }
2698}
2699
fb17358f 2700static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2701{
fb17358f 2702 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2703}
2704
fb17358f 2705static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2706{
fb17358f 2707 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2708}
2709
fb17358f 2710
e3173832 2711static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2712{
b89165f2 2713 u8 t8;
cd28ab6a 2714
167f53d0 2715 /* Enable all clocks and check for bad PCI access */
b32f40c4 2716 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2717
cd28ab6a 2718 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2719
cd28ab6a 2720 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2721 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2722
2723 switch(hw->chip_id) {
2724 case CHIP_ID_YUKON_XL:
2725 hw->flags = SKY2_HW_GIGABIT
e0c28116
SH		 2726 | SKY2_HW_NEWER_PHY;
2727 if (hw->chip_rev < 3)
2728 hw->flags |= SKY2_HW_FIFO_HANG_CHECK;
2729
ea76e635
SH		 2730 break;
2731
2732 case CHIP_ID_YUKON_EC_U:
2733 hw->flags = SKY2_HW_GIGABIT
2734 | SKY2_HW_NEWER_PHY
2735 | SKY2_HW_ADV_POWER_CTL;
2736 break;
2737
2738 case CHIP_ID_YUKON_EX:
2739 hw->flags = SKY2_HW_GIGABIT
2740 | SKY2_HW_NEWER_PHY
2741 | SKY2_HW_NEW_LE
2742 | SKY2_HW_ADV_POWER_CTL;
2743
2744 /* New transmit checksum */
2745 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2746 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2747 break;
2748
2749 case CHIP_ID_YUKON_EC:
2750 /* This rev is really old, and requires untested workarounds */
2751 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2752 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2753 return -EOPNOTSUPP;
2754 }
e0c28116 2755 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_FIFO_HANG_CHECK;
ea76e635
SH		 2756 break;
2757
2758 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2759 break;
2760
05745c4a
SH		 2761 case CHIP_ID_YUKON_FE_P:
2762 hw->flags = SKY2_HW_NEWER_PHY
2763 | SKY2_HW_NEW_LE
2764 | SKY2_HW_AUTO_TX_SUM
2765 | SKY2_HW_ADV_POWER_CTL;
2766 break;
ed4d4161
SH		 2767
2768 case CHIP_ID_YUKON_SUPR:
2769 hw->flags = SKY2_HW_GIGABIT
2770 | SKY2_HW_NEWER_PHY
2771 | SKY2_HW_NEW_LE
2772 | SKY2_HW_AUTO_TX_SUM
2773 | SKY2_HW_ADV_POWER_CTL;
2774 break;
2775
ea76e635 2776 default:
b02a9258
SH		 2777 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2778 hw->chip_id);
cd28ab6a
SH		 2779 return -EOPNOTSUPP;
2780 }
2781
ea76e635
SH		 2782 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2783 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2784 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2785
290d4de5 2786
e3173832
SH		 2787 hw->ports = 1;
2788 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2789 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2790 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2791 ++hw->ports;
2792 }
2793
2794 return 0;
2795}
2796
2797static void sky2_reset(struct sky2_hw *hw)
2798{
555382cb 2799 struct pci_dev *pdev = hw->pdev;
e3173832 2800 u16 status;
555382cb
SH		 2801 int i, cap;
2802 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2803
cd28ab6a 2804 /* disable ASF */
4f44d8ba
SH		 2805 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2806 status = sky2_read16(hw, HCU_CCSR);
2807 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2808 HCU_CCSR_UC_STATE_MSK);
2809 sky2_write16(hw, HCU_CCSR, status);
2810 } else
2811 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2812 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2813
2814 /* do a SW reset */
2815 sky2_write8(hw, B0_CTST, CS_RST_SET);
2816 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2817
ac93a394
SH		 2818 /* allow writes to PCI config */
2819 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2820
cd28ab6a 2821 /* clear PCI errors, if any */
b32f40c4 2822 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2823 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2824 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2825
2826 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2827
555382cb
SH		 2828 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2829 if (cap) {
7782c8c4
SH		 2830 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2831 0xfffffffful);
555382cb
SH		 2832
2833 /* If error bit is stuck on ignore it */
2834 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2835 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2836 else
555382cb
SH		 2837 hwe_mask |= Y2_IS_PCI_EXP;
2838 }
cd28ab6a 2839
ae306cca 2840 sky2_power_on(hw);
82637e80 2841 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2842
2843 for (i = 0; i < hw->ports; i++) {
2844 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2845 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 2846
ed4d4161
SH		 2847 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2848 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 2849 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2850 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2851 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2852 }
2853
793b883e
SH		 2854 /* Clear I2C IRQ noise */
2855 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2856
2857 /* turn off hardware timer (unused) */
2858 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2859 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2860
cd28ab6a
SH		 2861 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2862
69634ee7
SH		 2863 /* Turn off descriptor polling */
2864 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2865
2866 /* Turn off receive timestamp */
2867 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2868 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2869
2870 /* enable the Tx Arbiters */
2871 for (i = 0; i < hw->ports; i++)
2872 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2873
2874 /* Initialize ram interface */
2875 for (i = 0; i < hw->ports; i++) {
793b883e 2876 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2877
2878 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2879 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2880 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2881 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2882 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2883 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2884 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2885 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2886 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2887 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2888 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2889 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2890 }
2891
555382cb 2892 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 2893
cd28ab6a 2894 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2895 sky2_gmac_reset(hw, i);
cd28ab6a 2896
cd28ab6a
SH		 2897 memset(hw->st_le, 0, STATUS_LE_BYTES);
2898 hw->st_idx = 0;
2899
2900 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2901 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2902
2903 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2904 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2905
2906 /* Set the list last index */
793b883e 2907 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2908
290d4de5
SH		 2909 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2910 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2911
290d4de5
SH		 2912 /* set Status-FIFO ISR watermark */
2913 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2914 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2915 else
2916 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2917
290d4de5 2918 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2919 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2920 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2921
793b883e 2922 /* enable status unit */
cd28ab6a
SH		 2923 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2924
2925 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2926 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2927 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2928}
2929
81906791
SH		 2930static void sky2_restart(struct work_struct *work)
2931{
2932 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2933 struct net_device *dev;
2934 int i, err;
2935
81906791 2936 rtnl_lock();
81906791
SH		 2937 for (i = 0; i < hw->ports; i++) {
2938 dev = hw->dev[i];
2939 if (netif_running(dev))
2940 sky2_down(dev);
2941 }
2942
8cfcbe99
SH		 2943 napi_disable(&hw->napi);
2944 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 2945 sky2_reset(hw);
2946 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 2947 napi_enable(&hw->napi);
81906791
SH		 2948
2949 for (i = 0; i < hw->ports; i++) {
2950 dev = hw->dev[i];
2951 if (netif_running(dev)) {
2952 err = sky2_up(dev);
2953 if (err) {
2954 printk(KERN_INFO PFX "%s: could not restart %d\n",
2955 dev->name, err);
2956 dev_close(dev);
2957 }
2958 }
2959 }
2960
81906791
SH		 2961 rtnl_unlock();
2962}
2963
e3173832
SH		 2964static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2965{
2966 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2967}
2968
2969static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2970{
2971 const struct sky2_port *sky2 = netdev_priv(dev);
2972
2973 wol->supported = sky2_wol_supported(sky2->hw);
2974 wol->wolopts = sky2->wol;
2975}
2976
2977static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2978{
2979 struct sky2_port *sky2 = netdev_priv(dev);
2980 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2981
e3173832
SH		 2982 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2983 return -EOPNOTSUPP;
2984
2985 sky2->wol = wol->wolopts;
2986
05745c4a
SH		 2987 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2988 hw->chip_id == CHIP_ID_YUKON_EX ||
2989 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 2990 sky2_write32(hw, B0_CTST, sky2->wol
2991 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2992
2993 if (!netif_running(dev))
2994 sky2_wol_init(sky2);
cd28ab6a
SH		 2995 return 0;
2996}
2997
28bd181a 2998static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2999{
b89165f2
SH		 3000 if (sky2_is_copper(hw)) {
3001 u32 modes = SUPPORTED_10baseT_Half
3002 | SUPPORTED_10baseT_Full
3003 | SUPPORTED_100baseT_Half
3004 | SUPPORTED_100baseT_Full
3005 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3006
ea76e635 3007 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3008 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3009 | SUPPORTED_1000baseT_Full;
3010 return modes;
cd28ab6a 3011 } else
b89165f2
SH		 3012 return SUPPORTED_1000baseT_Half
3013 | SUPPORTED_1000baseT_Full
3014 | SUPPORTED_Autoneg
3015 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3016}
3017
793b883e 3018static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3019{
3020 struct sky2_port *sky2 = netdev_priv(dev);
3021 struct sky2_hw *hw = sky2->hw;
3022
3023 ecmd->transceiver = XCVR_INTERNAL;
3024 ecmd->supported = sky2_supported_modes(hw);
3025 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3026 if (sky2_is_copper(hw)) {
cd28ab6a 3027 ecmd->port = PORT_TP;
b89165f2
SH		 3028 ecmd->speed = sky2->speed;
3029 } else {
3030 ecmd->speed = SPEED_1000;
cd28ab6a 3031 ecmd->port = PORT_FIBRE;
b89165f2 3032 }
cd28ab6a
SH		 3033
3034 ecmd->advertising = sky2->advertising;
3035 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3036 ecmd->duplex = sky2->duplex;
3037 return 0;
3038}
3039
3040static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3041{
3042 struct sky2_port *sky2 = netdev_priv(dev);
3043 const struct sky2_hw *hw = sky2->hw;
3044 u32 supported = sky2_supported_modes(hw);
3045
3046 if (ecmd->autoneg == AUTONEG_ENABLE) {
3047 ecmd->advertising = supported;
3048 sky2->duplex = -1;
3049 sky2->speed = -1;
3050 } else {
3051 u32 setting;
3052
793b883e 3053 switch (ecmd->speed) {
cd28ab6a
SH		 3054 case SPEED_1000:
3055 if (ecmd->duplex == DUPLEX_FULL)
3056 setting = SUPPORTED_1000baseT_Full;
3057 else if (ecmd->duplex == DUPLEX_HALF)
3058 setting = SUPPORTED_1000baseT_Half;
3059 else
3060 return -EINVAL;
3061 break;
3062 case SPEED_100:
3063 if (ecmd->duplex == DUPLEX_FULL)
3064 setting = SUPPORTED_100baseT_Full;
3065 else if (ecmd->duplex == DUPLEX_HALF)
3066 setting = SUPPORTED_100baseT_Half;
3067 else
3068 return -EINVAL;
3069 break;
3070
3071 case SPEED_10:
3072 if (ecmd->duplex == DUPLEX_FULL)
3073 setting = SUPPORTED_10baseT_Full;
3074 else if (ecmd->duplex == DUPLEX_HALF)
3075 setting = SUPPORTED_10baseT_Half;
3076 else
3077 return -EINVAL;
3078 break;
3079 default:
3080 return -EINVAL;
3081 }
3082
3083 if ((setting & supported) == 0)
3084 return -EINVAL;
3085
3086 sky2->speed = ecmd->speed;
3087 sky2->duplex = ecmd->duplex;
3088 }
3089
3090 sky2->autoneg = ecmd->autoneg;
3091 sky2->advertising = ecmd->advertising;
3092
d1b139c0 3093 if (netif_running(dev)) {
1b537565 3094 sky2_phy_reinit(sky2);
d1b139c0
SH		 3095 sky2_set_multicast(dev);
3096 }
cd28ab6a
SH		 3097
3098 return 0;
3099}
3100
3101static void sky2_get_drvinfo(struct net_device *dev,
3102 struct ethtool_drvinfo *info)
3103{
3104 struct sky2_port *sky2 = netdev_priv(dev);
3105
3106 strcpy(info->driver, DRV_NAME);
3107 strcpy(info->version, DRV_VERSION);
3108 strcpy(info->fw_version, "N/A");
3109 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3110}
3111
3112static const struct sky2_stat {
793b883e
SH		 3113 char name[ETH_GSTRING_LEN];
3114 u16 offset;
cd28ab6a
SH		 3115} sky2_stats[] = {
3116 { "tx_bytes", GM_TXO_OK_HI },
3117 { "rx_bytes", GM_RXO_OK_HI },
3118 { "tx_broadcast", GM_TXF_BC_OK },
3119 { "rx_broadcast", GM_RXF_BC_OK },
3120 { "tx_multicast", GM_TXF_MC_OK },
3121 { "rx_multicast", GM_RXF_MC_OK },
3122 { "tx_unicast", GM_TXF_UC_OK },
3123 { "rx_unicast", GM_RXF_UC_OK },
3124 { "tx_mac_pause", GM_TXF_MPAUSE },
3125 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3126 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3127 { "late_collision",GM_TXF_LAT_COL },
3128 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3129 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3130 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3131
d2604540 3132 { "rx_short", GM_RXF_SHT },
cd28ab6a 3133 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3134 { "rx_64_byte_packets", GM_RXF_64B },
3135 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3136 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3137 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3138 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3139 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3140 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3141 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3142 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3143 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3144 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3145
3146 { "tx_64_byte_packets", GM_TXF_64B },
3147 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3148 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3149 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3150 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3151 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3152 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3153 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3154};
3155
cd28ab6a
SH		 3156static u32 sky2_get_rx_csum(struct net_device *dev)
3157{
3158 struct sky2_port *sky2 = netdev_priv(dev);
3159
3160 return sky2->rx_csum;
3161}
3162
3163static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3164{
3165 struct sky2_port *sky2 = netdev_priv(dev);
3166
3167 sky2->rx_csum = data;
793b883e 3168
cd28ab6a
SH		 3169 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3170 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3171
3172 return 0;
3173}
3174
3175static u32 sky2_get_msglevel(struct net_device *netdev)
3176{
3177 struct sky2_port *sky2 = netdev_priv(netdev);
3178 return sky2->msg_enable;
3179}
3180
9a7ae0a9
SH		 3181static int sky2_nway_reset(struct net_device *dev)
3182{
3183 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3184
16ad91e1 3185 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3186 return -EINVAL;
3187
1b537565 3188 sky2_phy_reinit(sky2);
d1b139c0 3189 sky2_set_multicast(dev);
9a7ae0a9
SH		 3190
3191 return 0;
3192}
3193
793b883e 3194static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3195{
3196 struct sky2_hw *hw = sky2->hw;
3197 unsigned port = sky2->port;
3198 int i;
3199
3200 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3201 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3202 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3203 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3204
793b883e 3205 for (i = 2; i < count; i++)
cd28ab6a
SH		 3206 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3207}
3208
cd28ab6a
SH		 3209static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3210{
3211 struct sky2_port *sky2 = netdev_priv(netdev);
3212 sky2->msg_enable = value;
3213}
3214
b9f2c044 3215static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3216{
b9f2c044
JG		 3217 switch (sset) {
3218 case ETH_SS_STATS:
3219 return ARRAY_SIZE(sky2_stats);
3220 default:
3221 return -EOPNOTSUPP;
3222 }
cd28ab6a
SH		 3223}
3224
3225static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3226 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3227{
3228 struct sky2_port *sky2 = netdev_priv(dev);
3229
793b883e 3230 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3231}
3232
793b883e 3233static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3234{
3235 int i;
3236
3237 switch (stringset) {
3238 case ETH_SS_STATS:
3239 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3240 memcpy(data + i * ETH_GSTRING_LEN,
3241 sky2_stats[i].name, ETH_GSTRING_LEN);
3242 break;
3243 }
3244}
3245
cd28ab6a
SH		 3246static int sky2_set_mac_address(struct net_device *dev, void *p)
3247{
3248 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3249 struct sky2_hw *hw = sky2->hw;
3250 unsigned port = sky2->port;
3251 const struct sockaddr *addr = p;
cd28ab6a
SH		 3252
3253 if (!is_valid_ether_addr(addr->sa_data))
3254 return -EADDRNOTAVAIL;
3255
cd28ab6a 3256 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3257 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3258 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3259 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3260 dev->dev_addr, ETH_ALEN);
1b537565 3261
a8ab1ec0
SH		 3262 /* virtual address for data */
3263 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3264
3265 /* physical address: used for pause frames */
3266 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3267
3268 return 0;
cd28ab6a
SH		 3269}
3270
a052b52f
SH		 3271static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3272{
3273 u32 bit;
3274
3275 bit = ether_crc(ETH_ALEN, addr) & 63;
3276 filter[bit >> 3] |= 1 << (bit & 7);
3277}
3278
cd28ab6a
SH		 3279static void sky2_set_multicast(struct net_device *dev)
3280{
3281 struct sky2_port *sky2 = netdev_priv(dev);
3282 struct sky2_hw *hw = sky2->hw;
3283 unsigned port = sky2->port;
3284 struct dev_mc_list *list = dev->mc_list;
3285 u16 reg;
3286 u8 filter[8];
a052b52f
SH		 3287 int rx_pause;
3288 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3289
a052b52f 3290 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3291 memset(filter, 0, sizeof(filter));
3292
3293 reg = gma_read16(hw, port, GM_RX_CTRL);
3294 reg |= GM_RXCR_UCF_ENA;
3295
d571b694 3296 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3297 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3298 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3299 memset(filter, 0xff, sizeof(filter));
a052b52f 3300 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3301 reg &= ~GM_RXCR_MCF_ENA;
3302 else {
3303 int i;
3304 reg |= GM_RXCR_MCF_ENA;
3305
a052b52f
SH		 3306 if (rx_pause)
3307 sky2_add_filter(filter, pause_mc_addr);
3308
3309 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3310 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3311 }
3312
cd28ab6a 3313 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3314 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3315 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3316 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3317 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3318 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3319 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3320 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3321
3322 gma_write16(hw, port, GM_RX_CTRL, reg);
3323}
3324
3325/* Can have one global because blinking is controlled by
3326 * ethtool and that is always under RTNL mutex
3327 */
91c86df5 3328static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3329{
793b883e
SH		 3330 u16 pg;
3331
793b883e
SH		 3332 switch (hw->chip_id) {
3333 case CHIP_ID_YUKON_XL:
3334 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3335 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3336 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3337 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3338 PHY_M_LEDC_INIT_CTRL(7) |
3339 PHY_M_LEDC_STA1_CTRL(7) |
3340 PHY_M_LEDC_STA0_CTRL(7))
3341 : 0);
3342
3343 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3344 break;
3345
3346 default:
3347 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3348 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3349 on ? PHY_M_LED_ALL : 0);
793b883e 3350 }
cd28ab6a
SH		 3351}
3352
3353/* blink LED's for finding board */
3354static int sky2_phys_id(struct net_device *dev, u32 data)
3355{
3356 struct sky2_port *sky2 = netdev_priv(dev);
3357 struct sky2_hw *hw = sky2->hw;
3358 unsigned port = sky2->port;
793b883e 3359 u16 ledctrl, ledover = 0;
cd28ab6a 3360 long ms;
91c86df5 3361 int interrupted;
cd28ab6a
SH		 3362 int onoff = 1;
3363
793b883e 3364 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3365 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3366 else
3367 ms = data * 1000;
3368
3369 /* save initial values */
e07b1aa8 3370 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3371 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3372 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3373 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3374 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3375 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3376 } else {
3377 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3378 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3379 }
cd28ab6a 3380
91c86df5
SH		 3381 interrupted = 0;
3382 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3383 sky2_led(hw, port, onoff);
3384 onoff = !onoff;
3385
e07b1aa8 3386 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3387 interrupted = msleep_interruptible(250);
e07b1aa8 3388 spin_lock_bh(&sky2->phy_lock);
91c86df5 3389
cd28ab6a
SH		 3390 ms -= 250;
3391 }
3392
3393 /* resume regularly scheduled programming */
793b883e
SH		 3394 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3395 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3396 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3397 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3398 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3399 } else {
3400 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3401 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3402 }
e07b1aa8 3403 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3404
3405 return 0;
3406}
3407
3408static void sky2_get_pauseparam(struct net_device *dev,
3409 struct ethtool_pauseparam *ecmd)
3410{
3411 struct sky2_port *sky2 = netdev_priv(dev);
3412
16ad91e1
SH		 3413 switch (sky2->flow_mode) {
3414 case FC_NONE:
3415 ecmd->tx_pause = ecmd->rx_pause = 0;
3416 break;
3417 case FC_TX:
3418 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3419 break;
3420 case FC_RX:
3421 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3422 break;
3423 case FC_BOTH:
3424 ecmd->tx_pause = ecmd->rx_pause = 1;
3425 }
3426
cd28ab6a
SH		 3427 ecmd->autoneg = sky2->autoneg;
3428}
3429
3430static int sky2_set_pauseparam(struct net_device *dev,
3431 struct ethtool_pauseparam *ecmd)
3432{
3433 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3434
3435 sky2->autoneg = ecmd->autoneg;
16ad91e1 3436 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3437
16ad91e1
SH		 3438 if (netif_running(dev))
3439 sky2_phy_reinit(sky2);
cd28ab6a 3440
2eaba1a2 3441 return 0;
cd28ab6a
SH		 3442}
3443
fb17358f
SH		 3444static int sky2_get_coalesce(struct net_device *dev,
3445 struct ethtool_coalesce *ecmd)
3446{
3447 struct sky2_port *sky2 = netdev_priv(dev);
3448 struct sky2_hw *hw = sky2->hw;
3449
3450 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3451 ecmd->tx_coalesce_usecs = 0;
3452 else {
3453 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3454 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3455 }
3456 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3457
3458 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3459 ecmd->rx_coalesce_usecs = 0;
3460 else {
3461 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3462 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3463 }
3464 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3465
3466 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3467 ecmd->rx_coalesce_usecs_irq = 0;
3468 else {
3469 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3470 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3471 }
3472
3473 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3474
3475 return 0;
3476}
3477
3478/* Note: this affect both ports */
3479static int sky2_set_coalesce(struct net_device *dev,
3480 struct ethtool_coalesce *ecmd)
3481{
3482 struct sky2_port *sky2 = netdev_priv(dev);
3483 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3484 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3485
77b3d6a2
SH		 3486 if (ecmd->tx_coalesce_usecs > tmax ||
3487 ecmd->rx_coalesce_usecs > tmax ||
3488 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3489 return -EINVAL;
3490
ff81fbbe 3491 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3492 return -EINVAL;
ff81fbbe 3493 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3494 return -EINVAL;
ff81fbbe 3495 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3496 return -EINVAL;
3497
3498 if (ecmd->tx_coalesce_usecs == 0)
3499 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3500 else {
3501 sky2_write32(hw, STAT_TX_TIMER_INI,
3502 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3503 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3504 }
3505 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3506
3507 if (ecmd->rx_coalesce_usecs == 0)
3508 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3509 else {
3510 sky2_write32(hw, STAT_LEV_TIMER_INI,
3511 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3512 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3513 }
3514 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3515
3516 if (ecmd->rx_coalesce_usecs_irq == 0)
3517 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3518 else {
d28d4870 3519 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3520 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3521 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3522 }
3523 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3524 return 0;
3525}
3526
793b883e
SH		 3527static void sky2_get_ringparam(struct net_device *dev,
3528 struct ethtool_ringparam *ering)
3529{
3530 struct sky2_port *sky2 = netdev_priv(dev);
3531
3532 ering->rx_max_pending = RX_MAX_PENDING;
3533 ering->rx_mini_max_pending = 0;
3534 ering->rx_jumbo_max_pending = 0;
3535 ering->tx_max_pending = TX_RING_SIZE - 1;
3536
3537 ering->rx_pending = sky2->rx_pending;
3538 ering->rx_mini_pending = 0;
3539 ering->rx_jumbo_pending = 0;
3540 ering->tx_pending = sky2->tx_pending;
3541}
3542
3543static int sky2_set_ringparam(struct net_device *dev,
3544 struct ethtool_ringparam *ering)
3545{
3546 struct sky2_port *sky2 = netdev_priv(dev);
3547 int err = 0;
3548
3549 if (ering->rx_pending > RX_MAX_PENDING ||
3550 ering->rx_pending < 8 ||
3551 ering->tx_pending < MAX_SKB_TX_LE ||
3552 ering->tx_pending > TX_RING_SIZE - 1)
3553 return -EINVAL;
3554
3555 if (netif_running(dev))
3556 sky2_down(dev);
3557
3558 sky2->rx_pending = ering->rx_pending;
3559 sky2->tx_pending = ering->tx_pending;
3560
1b537565 3561 if (netif_running(dev)) {
793b883e 3562 err = sky2_up(dev);
1b537565
SH		 3563 if (err)
3564 dev_close(dev);
3565 }
793b883e
SH		 3566
3567 return err;
3568}
3569
793b883e
SH		 3570static int sky2_get_regs_len(struct net_device *dev)
3571{
6e4cbb34 3572 return 0x4000;
793b883e
SH		 3573}
3574
3575/*
3576 * Returns copy of control register region
3ead5db7 3577 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3578 */
3579static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3580 void *p)
3581{
3582 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3583 const void __iomem *io = sky2->hw->regs;
295b54c4 3584 unsigned int b;
793b883e
SH		 3585
3586 regs->version = 1;
793b883e 3587
295b54c4
SH		 3588 for (b = 0; b < 128; b++) {
3589 /* This complicated switch statement is to make sure and
3590 * only access regions that are unreserved.
3591 * Some blocks are only valid on dual port cards.
3592 * and block 3 has some special diagnostic registers that
3593 * are poison.
3594 */
3595 switch (b) {
3596 case 3:
3597 /* skip diagnostic ram region */
3598 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3599 break;
3ead5db7 3600
295b54c4
SH		 3601 /* dual port cards only */
3602 case 5: /* Tx Arbiter 2 */
3603 case 9: /* RX2 */
3604 case 14 ... 15: /* TX2 */
3605 case 17: case 19: /* Ram Buffer 2 */
3606 case 22 ... 23: /* Tx Ram Buffer 2 */
3607 case 25: /* Rx MAC Fifo 1 */
3608 case 27: /* Tx MAC Fifo 2 */
3609 case 31: /* GPHY 2 */
3610 case 40 ... 47: /* Pattern Ram 2 */
3611 case 52: case 54: /* TCP Segmentation 2 */
3612 case 112 ... 116: /* GMAC 2 */
3613 if (sky2->hw->ports == 1)
3614 goto reserved;
3615 /* fall through */
3616 case 0: /* Control */
3617 case 2: /* Mac address */
3618 case 4: /* Tx Arbiter 1 */
3619 case 7: /* PCI express reg */
3620 case 8: /* RX1 */
3621 case 12 ... 13: /* TX1 */
3622 case 16: case 18:/* Rx Ram Buffer 1 */
3623 case 20 ... 21: /* Tx Ram Buffer 1 */
3624 case 24: /* Rx MAC Fifo 1 */
3625 case 26: /* Tx MAC Fifo 1 */
3626 case 28 ... 29: /* Descriptor and status unit */
3627 case 30: /* GPHY 1*/
3628 case 32 ... 39: /* Pattern Ram 1 */
3629 case 48: case 50: /* TCP Segmentation 1 */
3630 case 56 ... 60: /* PCI space */
3631 case 80 ... 84: /* GMAC 1 */
3632 memcpy_fromio(p, io, 128);
3633 break;
3634 default:
3635reserved:
3636 memset(p, 0, 128);
3637 }
3ead5db7 3638
295b54c4
SH		 3639 p += 128;
3640 io += 128;
3641 }
793b883e 3642}
cd28ab6a 3643
b628ed98
SH		 3644/* In order to do Jumbo packets on these chips, need to turn off the
3645 * transmit store/forward. Therefore checksum offload won't work.
3646 */
3647static int no_tx_offload(struct net_device *dev)
3648{
3649 const struct sky2_port *sky2 = netdev_priv(dev);
3650 const struct sky2_hw *hw = sky2->hw;
3651
69161611 3652 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3653}
3654
3655static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3656{
3657 if (data && no_tx_offload(dev))
3658 return -EINVAL;
3659
3660 return ethtool_op_set_tx_csum(dev, data);
3661}
3662
3663
3664static int sky2_set_tso(struct net_device *dev, u32 data)
3665{
3666 if (data && no_tx_offload(dev))
3667 return -EINVAL;
3668
3669 return ethtool_op_set_tso(dev, data);
3670}
3671
f4331a6d
SH		 3672static int sky2_get_eeprom_len(struct net_device *dev)
3673{
3674 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3675 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3676 u16 reg2;
3677
b32f40c4 3678 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3679 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3680}
3681
b32f40c4 3682static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
f4331a6d 3683{
167f53d0 3684 u32 val;
f4331a6d 3685
b32f40c4 3686 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
167f53d0
SH		 3687
3688 do {
b32f40c4 3689 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0
SH		 3690 } while (!(offset & PCI_VPD_ADDR_F));
3691
b32f40c4 3692 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
167f53d0 3693 return val;
f4331a6d
SH		 3694}
3695
b32f40c4 3696static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
f4331a6d 3697{
b32f40c4
SH		 3698 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3699 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
f4331a6d 3700 do {
b32f40c4 3701 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0 3702 } while (offset & PCI_VPD_ADDR_F);
f4331a6d
SH		 3703}
3704
3705static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3706 u8 *data)
3707{
3708 struct sky2_port *sky2 = netdev_priv(dev);
3709 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3710 int length = eeprom->len;
3711 u16 offset = eeprom->offset;
3712
3713 if (!cap)
3714 return -EINVAL;
3715
3716 eeprom->magic = SKY2_EEPROM_MAGIC;
3717
3718 while (length > 0) {
b32f40c4 3719 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3720 int n = min_t(int, length, sizeof(val));
3721
3722 memcpy(data, &val, n);
3723 length -= n;
3724 data += n;
3725 offset += n;
3726 }
3727 return 0;
3728}
3729
3730static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3731 u8 *data)
3732{
3733 struct sky2_port *sky2 = netdev_priv(dev);
3734 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3735 int length = eeprom->len;
3736 u16 offset = eeprom->offset;
3737
3738 if (!cap)
3739 return -EINVAL;
3740
3741 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3742 return -EINVAL;
3743
3744 while (length > 0) {
3745 u32 val;
3746 int n = min_t(int, length, sizeof(val));
3747
3748 if (n < sizeof(val))
b32f40c4 3749 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3750 memcpy(&val, data, n);
3751
b32f40c4 3752 sky2_vpd_write(sky2->hw, cap, offset, val);
f4331a6d
SH		 3753
3754 length -= n;
3755 data += n;
3756 offset += n;
3757 }
3758 return 0;
3759}
3760
3761
7282d491 3762static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3763 .get_settings = sky2_get_settings,
3764 .set_settings = sky2_set_settings,
3765 .get_drvinfo = sky2_get_drvinfo,
3766 .get_wol = sky2_get_wol,
3767 .set_wol = sky2_set_wol,
3768 .get_msglevel = sky2_get_msglevel,
3769 .set_msglevel = sky2_set_msglevel,
3770 .nway_reset = sky2_nway_reset,
3771 .get_regs_len = sky2_get_regs_len,
3772 .get_regs = sky2_get_regs,
3773 .get_link = ethtool_op_get_link,
3774 .get_eeprom_len = sky2_get_eeprom_len,
3775 .get_eeprom = sky2_get_eeprom,
3776 .set_eeprom = sky2_set_eeprom,
f4331a6d 3777 .set_sg = ethtool_op_set_sg,
f4331a6d 3778 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3779 .set_tso = sky2_set_tso,
3780 .get_rx_csum = sky2_get_rx_csum,
3781 .set_rx_csum = sky2_set_rx_csum,
3782 .get_strings = sky2_get_strings,
3783 .get_coalesce = sky2_get_coalesce,
3784 .set_coalesce = sky2_set_coalesce,
3785 .get_ringparam = sky2_get_ringparam,
3786 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3787 .get_pauseparam = sky2_get_pauseparam,
3788 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3789 .phys_id = sky2_phys_id,
b9f2c044 3790 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3791 .get_ethtool_stats = sky2_get_ethtool_stats,
3792};
3793
3cf26753
SH		 3794#ifdef CONFIG_SKY2_DEBUG
3795
3796static struct dentry *sky2_debug;
3797
3798static int sky2_debug_show(struct seq_file *seq, void *v)
3799{
3800 struct net_device *dev = seq->private;
3801 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 3802 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 3803 unsigned port = sky2->port;
3804 unsigned idx, last;
3805 int sop;
3806
3807 if (!netif_running(dev))
3808 return -ENETDOWN;
3809
3810 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3811 sky2_read32(hw, B0_ISRC),
3812 sky2_read32(hw, B0_IMSK),
3813 sky2_read32(hw, B0_Y2_SP_ICR));
3814
bea3348e 3815 napi_disable(&hw->napi);
3cf26753
SH		 3816 last = sky2_read16(hw, STAT_PUT_IDX);
3817
3818 if (hw->st_idx == last)
3819 seq_puts(seq, "Status ring (empty)\n");
3820 else {
3821 seq_puts(seq, "Status ring\n");
3822 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3823 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3824 const struct sky2_status_le *le = hw->st_le + idx;
3825 seq_printf(seq, "[%d] %#x %d %#x\n",
3826 idx, le->opcode, le->length, le->status);
3827 }
3828 seq_puts(seq, "\n");
3829 }
3830
3831 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3832 sky2->tx_cons, sky2->tx_prod,
3833 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3834 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3835
3836 /* Dump contents of tx ring */
3837 sop = 1;
3838 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3839 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3840 const struct sky2_tx_le *le = sky2->tx_le + idx;
3841 u32 a = le32_to_cpu(le->addr);
3842
3843 if (sop)
3844 seq_printf(seq, "%u:", idx);
3845 sop = 0;
3846
3847 switch(le->opcode & ~HW_OWNER) {
3848 case OP_ADDR64:
3849 seq_printf(seq, " %#x:", a);
3850 break;
3851 case OP_LRGLEN:
3852 seq_printf(seq, " mtu=%d", a);
3853 break;
3854 case OP_VLAN:
3855 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3856 break;
3857 case OP_TCPLISW:
3858 seq_printf(seq, " csum=%#x", a);
3859 break;
3860 case OP_LARGESEND:
3861 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3862 break;
3863 case OP_PACKET:
3864 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3865 break;
3866 case OP_BUFFER:
3867 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3868 break;
3869 default:
3870 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3871 a, le16_to_cpu(le->length));
3872 }
3873
3874 if (le->ctrl & EOP) {
3875 seq_putc(seq, '\n');
3876 sop = 1;
3877 }
3878 }
3879
3880 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3881 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3882 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3883 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3884
d1d08d12 3885 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 3886 napi_enable(&hw->napi);
3cf26753
SH		 3887 return 0;
3888}
3889
3890static int sky2_debug_open(struct inode *inode, struct file *file)
3891{
3892 return single_open(file, sky2_debug_show, inode->i_private);
3893}
3894
3895static const struct file_operations sky2_debug_fops = {
3896 .owner = THIS_MODULE,
3897 .open = sky2_debug_open,
3898 .read = seq_read,
3899 .llseek = seq_lseek,
3900 .release = single_release,
3901};
3902
3903/*
3904 * Use network device events to create/remove/rename
3905 * debugfs file entries
3906 */
3907static int sky2_device_event(struct notifier_block *unused,
3908 unsigned long event, void *ptr)
3909{
3910 struct net_device *dev = ptr;
5b296bc9 3911 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 3912
5b296bc9
SH		 3913 if (dev->open != sky2_up || !sky2_debug)
3914 return NOTIFY_DONE;
3cf26753 3915
5b296bc9
SH		 3916 switch(event) {
3917 case NETDEV_CHANGENAME:
3918 if (sky2->debugfs) {
3919 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3920 sky2_debug, dev->name);
3921 }
3922 break;
3cf26753 3923
5b296bc9
SH		 3924 case NETDEV_GOING_DOWN:
3925 if (sky2->debugfs) {
3926 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3927 dev->name);
3928 debugfs_remove(sky2->debugfs);
3929 sky2->debugfs = NULL;
3cf26753 3930 }
5b296bc9
SH		 3931 break;
3932
3933 case NETDEV_UP:
3934 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3935 sky2_debug, dev,
3936 &sky2_debug_fops);
3937 if (IS_ERR(sky2->debugfs))
3938 sky2->debugfs = NULL;
3cf26753
SH		 3939 }
3940
3941 return NOTIFY_DONE;
3942}
3943
3944static struct notifier_block sky2_notifier = {
3945 .notifier_call = sky2_device_event,
3946};
3947
3948
3949static __init void sky2_debug_init(void)
3950{
3951 struct dentry *ent;
3952
3953 ent = debugfs_create_dir("sky2", NULL);
3954 if (!ent || IS_ERR(ent))
3955 return;
3956
3957 sky2_debug = ent;
3958 register_netdevice_notifier(&sky2_notifier);
3959}
3960
3961static __exit void sky2_debug_cleanup(void)
3962{
3963 if (sky2_debug) {
3964 unregister_netdevice_notifier(&sky2_notifier);
3965 debugfs_remove(sky2_debug);
3966 sky2_debug = NULL;
3967 }
3968}
3969
3970#else
3971#define sky2_debug_init()
3972#define sky2_debug_cleanup()
3973#endif
3974
3975
cd28ab6a
SH		 3976/* Initialize network device */
3977static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 3978 unsigned port,
be63a21c 3979 int highmem, int wol)
cd28ab6a
SH		 3980{
3981 struct sky2_port *sky2;
3982 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3983
3984 if (!dev) {
898eb71c 3985 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 3986 return NULL;
3987 }
3988
cd28ab6a 3989 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3990 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3991 dev->open = sky2_up;
3992 dev->stop = sky2_down;
ef743d33 3993 dev->do_ioctl = sky2_ioctl;
cd28ab6a 3994 dev->hard_start_xmit = sky2_xmit_frame;
cd28ab6a
SH		 3995 dev->set_multicast_list = sky2_set_multicast;
3996 dev->set_mac_address = sky2_set_mac_address;
3997 dev->change_mtu = sky2_change_mtu;
3998 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3999 dev->tx_timeout = sky2_tx_timeout;
4000 dev->watchdog_timeo = TX_WATCHDOG;
cd28ab6a 4001#ifdef CONFIG_NET_POLL_CONTROLLER
a5e68c02
SH		 4002 if (port == 0)
4003 dev->poll_controller = sky2_netpoll;
cd28ab6a 4004#endif
cd28ab6a
SH		 4005
4006 sky2 = netdev_priv(dev);
4007 sky2->netdev = dev;
4008 sky2->hw = hw;
4009 sky2->msg_enable = netif_msg_init(debug, default_msg);
4010
cd28ab6a
SH		 4011 /* Auto speed and flow control */
4012 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 4013 sky2->flow_mode = FC_BOTH;
4014
cd28ab6a
SH		 4015 sky2->duplex = -1;
4016 sky2->speed = -1;
4017 sky2->advertising = sky2_supported_modes(hw);
8b31cfbc 4018 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
be63a21c 4019 sky2->wol = wol;
75d070c5 4020
e07b1aa8 4021 spin_lock_init(&sky2->phy_lock);
793b883e 4022 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 4023 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4024
4025 hw->dev[port] = dev;
4026
4027 sky2->port = port;
4028
4a50a876 4029 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4030 if (highmem)
4031 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4032
d1f13708 4033#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4034 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4035 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4036 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4037 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4038 dev->vlan_rx_register = sky2_vlan_rx_register;
4039 }
d1f13708 4040#endif
4041
cd28ab6a 4042 /* read the mac address */
793b883e 4043 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4044 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4045
cd28ab6a
SH		 4046 return dev;
4047}
4048
28bd181a 4049static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4050{
4051 const struct sky2_port *sky2 = netdev_priv(dev);
0795af57 4052 DECLARE_MAC_BUF(mac);
cd28ab6a
SH		 4053
4054 if (netif_msg_probe(sky2))
0795af57
JP		 4055 printk(KERN_INFO PFX "%s: addr %s\n",
4056 dev->name, print_mac(mac, dev->dev_addr));
cd28ab6a
SH		 4057}
4058
fb2690a9 4059/* Handle software interrupt used during MSI test */
7d12e780 4060static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4061{
4062 struct sky2_hw *hw = dev_id;
4063 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4064
4065 if (status == 0)
4066 return IRQ_NONE;
4067
4068 if (status & Y2_IS_IRQ_SW) {
ea76e635 4069 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4070 wake_up(&hw->msi_wait);
4071 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4072 }
4073 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4074
4075 return IRQ_HANDLED;
4076}
4077
4078/* Test interrupt path by forcing a a software IRQ */
4079static int __devinit sky2_test_msi(struct sky2_hw *hw)
4080{
4081 struct pci_dev *pdev = hw->pdev;
4082 int err;
4083
bb507fe1 4084 init_waitqueue_head (&hw->msi_wait);
4085
fb2690a9
SH		 4086 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4087
b0a20ded 4088 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4089 if (err) {
b02a9258 4090 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4091 return err;
4092 }
4093
fb2690a9 4094 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4095 sky2_read8(hw, B0_CTST);
fb2690a9 4096
ea76e635 4097 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4098
ea76e635 4099 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4100 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4101 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4102 "switching to INTx mode.\n");
fb2690a9
SH		 4103
4104 err = -EOPNOTSUPP;
4105 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4106 }
4107
4108 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4109 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4110
4111 free_irq(pdev->irq, hw);
4112
4113 return err;
4114}
4115
be63a21c
SH		 4116static int __devinit pci_wake_enabled(struct pci_dev *dev)
4117{
4118 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4119 u16 value;
4120
4121 if (!pm)
4122 return 0;
4123 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4124 return 0;
4125 return value & PCI_PM_CTRL_PME_ENABLE;
4126}
4127
cd28ab6a
SH		 4128static int __devinit sky2_probe(struct pci_dev *pdev,
4129 const struct pci_device_id *ent)
4130{
7f60c64b 4131 struct net_device *dev;
cd28ab6a 4132 struct sky2_hw *hw;
be63a21c 4133 int err, using_dac = 0, wol_default;
cd28ab6a 4134
793b883e
SH		 4135 err = pci_enable_device(pdev);
4136 if (err) {
b02a9258 4137 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4138 goto err_out;
4139 }
4140
793b883e
SH		 4141 err = pci_request_regions(pdev, DRV_NAME);
4142 if (err) {
b02a9258 4143 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4144 goto err_out_disable;
cd28ab6a
SH		 4145 }
4146
4147 pci_set_master(pdev);
4148
d1f3d4dd
SH		 4149 if (sizeof(dma_addr_t) > sizeof(u32) &&
4150 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4151 using_dac = 1;
4152 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4153 if (err < 0) {
b02a9258
SH		 4154 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4155 "for consistent allocations\n");
d1f3d4dd
SH		 4156 goto err_out_free_regions;
4157 }
d1f3d4dd 4158 } else {
cd28ab6a
SH		 4159 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4160 if (err) {
b02a9258 4161 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4162 goto err_out_free_regions;
4163 }
4164 }
d1f3d4dd 4165
be63a21c
SH		 4166 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4167
cd28ab6a 4168 err = -ENOMEM;
6aad85d6 4169 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4170 if (!hw) {
b02a9258 4171 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4172 goto err_out_free_regions;
4173 }
4174
cd28ab6a 4175 hw->pdev = pdev;
cd28ab6a
SH		 4176
4177 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4178 if (!hw->regs) {
b02a9258 4179 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4180 goto err_out_free_hw;
4181 }
4182
56a645cc 4183#ifdef __BIG_ENDIAN
f65b138c
SH		 4184 /* The sk98lin vendor driver uses hardware byte swapping but
4185 * this driver uses software swapping.
4186 */
56a645cc
SH		 4187 {
4188 u32 reg;
b32f40c4 4189 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 4190 reg &= ~PCI_REV_DESC;
b32f40c4 4191 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
56a645cc
SH		 4192 }
4193#endif
4194
08c06d8a 4195 /* ring for status responses */
167f53d0 4196 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4197 if (!hw->st_le)
4198 goto err_out_iounmap;
4199
e3173832 4200 err = sky2_init(hw);
cd28ab6a 4201 if (err)
793b883e 4202 goto err_out_iounmap;
cd28ab6a 4203
b02a9258 4204 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 4205 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4206 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 4207 hw->chip_id, hw->chip_rev);
cd28ab6a 4208
e3173832
SH		 4209 sky2_reset(hw);
4210
be63a21c 4211 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4212 if (!dev) {
4213 err = -ENOMEM;
cd28ab6a 4214 goto err_out_free_pci;
7f60c64b 4215 }
cd28ab6a 4216
9fa1b1f3
SH		 4217 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4218 err = sky2_test_msi(hw);
4219 if (err == -EOPNOTSUPP)
4220 pci_disable_msi(pdev);
4221 else if (err)
4222 goto err_out_free_netdev;
4223 }
4224
793b883e
SH		 4225 err = register_netdev(dev);
4226 if (err) {
b02a9258 4227 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4228 goto err_out_free_netdev;
4229 }
4230
6de16237
SH		 4231 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4232
ea76e635
SH		 4233 err = request_irq(pdev->irq, sky2_intr,
4234 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4235 dev->name, hw);
9fa1b1f3 4236 if (err) {
b02a9258 4237 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4238 goto err_out_unregister;
4239 }
4240 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4241 napi_enable(&hw->napi);
9fa1b1f3 4242
cd28ab6a
SH		 4243 sky2_show_addr(dev);
4244
7f60c64b 4245 if (hw->ports > 1) {
4246 struct net_device *dev1;
4247
be63a21c 4248 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4249 if (!dev1)
4250 dev_warn(&pdev->dev, "allocation for second device failed\n");
4251 else if ((err = register_netdev(dev1))) {
4252 dev_warn(&pdev->dev,
4253 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4254 hw->dev[1] = NULL;
4255 free_netdev(dev1);
b02a9258
SH		 4256 } else
4257 sky2_show_addr(dev1);
cd28ab6a
SH		 4258 }
4259
32c2c300 4260 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4261 INIT_WORK(&hw->restart_work, sky2_restart);
4262
793b883e
SH		 4263 pci_set_drvdata(pdev, hw);
4264
cd28ab6a
SH		 4265 return 0;
4266
793b883e 4267err_out_unregister:
ea76e635 4268 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4269 pci_disable_msi(pdev);
793b883e 4270 unregister_netdev(dev);
cd28ab6a
SH		 4271err_out_free_netdev:
4272 free_netdev(dev);
cd28ab6a 4273err_out_free_pci:
793b883e 4274 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4275 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4276err_out_iounmap:
4277 iounmap(hw->regs);
4278err_out_free_hw:
4279 kfree(hw);
4280err_out_free_regions:
4281 pci_release_regions(pdev);
44a1d2e5 4282err_out_disable:
cd28ab6a 4283 pci_disable_device(pdev);
cd28ab6a 4284err_out:
549a68c3 4285 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4286 return err;
4287}
4288
4289static void __devexit sky2_remove(struct pci_dev *pdev)
4290{
793b883e 4291 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4292 int i;
cd28ab6a 4293
793b883e 4294 if (!hw)
cd28ab6a
SH		 4295 return;
4296
32c2c300 4297 del_timer_sync(&hw->watchdog_timer);
6de16237 4298 cancel_work_sync(&hw->restart_work);
d27ed387 4299
b877fe28 4300 for (i = hw->ports-1; i >= 0; --i)
6de16237 4301 unregister_netdev(hw->dev[i]);
81906791 4302
d27ed387 4303 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4304
ae306cca
SH		 4305 sky2_power_aux(hw);
4306
cd28ab6a 4307 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4308 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4309 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4310
4311 free_irq(pdev->irq, hw);
ea76e635 4312 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4313 pci_disable_msi(pdev);
793b883e 4314 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4315 pci_release_regions(pdev);
4316 pci_disable_device(pdev);
793b883e 4317
b877fe28 4318 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4319 free_netdev(hw->dev[i]);
4320
cd28ab6a
SH		 4321 iounmap(hw->regs);
4322 kfree(hw);
5afa0a9c 4323
cd28ab6a
SH		 4324 pci_set_drvdata(pdev, NULL);
4325}
4326
4327#ifdef CONFIG_PM
4328static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4329{
793b883e 4330 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4331 int i, wol = 0;
cd28ab6a 4332
549a68c3
SH		 4333 if (!hw)
4334 return 0;
4335
f05267e7 4336 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4337 struct net_device *dev = hw->dev[i];
e3173832 4338 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4339
e3173832 4340 if (netif_running(dev))
5afa0a9c 4341 sky2_down(dev);
e3173832
SH		 4342
4343 if (sky2->wol)
4344 sky2_wol_init(sky2);
4345
4346 wol |= sky2->wol;
cd28ab6a
SH		 4347 }
4348
8ab8fca2 4349 sky2_write32(hw, B0_IMSK, 0);
6de16237 4350 napi_disable(&hw->napi);
ae306cca 4351 sky2_power_aux(hw);
e3173832 4352
d374c1c1 4353 pci_save_state(pdev);
e3173832 4354 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 4355 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4356
2ccc99b7 4357 return 0;
cd28ab6a
SH		 4358}
4359
4360static int sky2_resume(struct pci_dev *pdev)
4361{
793b883e 4362 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4363 int i, err;
cd28ab6a 4364
549a68c3
SH		 4365 if (!hw)
4366 return 0;
4367
ae306cca
SH		 4368 err = pci_set_power_state(pdev, PCI_D0);
4369 if (err)
4370 goto out;
4371
4372 err = pci_restore_state(pdev);
4373 if (err)
4374 goto out;
4375
cd28ab6a 4376 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4377
4378 /* Re-enable all clocks */
05745c4a
SH		 4379 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4380 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4381 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4382 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4383
e3173832 4384 sky2_reset(hw);
8ab8fca2 4385 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4386 napi_enable(&hw->napi);
8ab8fca2 4387
f05267e7 4388 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4389 struct net_device *dev = hw->dev[i];
6a5706b9 4390 if (netif_running(dev)) {
08c06d8a
SH		 4391 err = sky2_up(dev);
4392 if (err) {
4393 printk(KERN_ERR PFX "%s: could not up: %d\n",
4394 dev->name, err);
4395 dev_close(dev);
eb35cf60 4396 goto out;
5afa0a9c 4397 }
cd28ab6a
SH		 4398 }
4399 }
eb35cf60 4400
ae306cca 4401 return 0;
08c06d8a 4402out:
b02a9258 4403 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4404 pci_disable_device(pdev);
08c06d8a 4405 return err;
cd28ab6a
SH		 4406}
4407#endif
4408
e3173832
SH		 4409static void sky2_shutdown(struct pci_dev *pdev)
4410{
4411 struct sky2_hw *hw = pci_get_drvdata(pdev);
4412 int i, wol = 0;
4413
549a68c3
SH		 4414 if (!hw)
4415 return;
4416
5c0d6b34 4417 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4418
4419 for (i = 0; i < hw->ports; i++) {
4420 struct net_device *dev = hw->dev[i];
4421 struct sky2_port *sky2 = netdev_priv(dev);
4422
4423 if (sky2->wol) {
4424 wol = 1;
4425 sky2_wol_init(sky2);
4426 }
4427 }
4428
4429 if (wol)
4430 sky2_power_aux(hw);
4431
4432 pci_enable_wake(pdev, PCI_D3hot, wol);
4433 pci_enable_wake(pdev, PCI_D3cold, wol);
4434
4435 pci_disable_device(pdev);
4436 pci_set_power_state(pdev, PCI_D3hot);
4437
4438}
4439
cd28ab6a 4440static struct pci_driver sky2_driver = {
793b883e
SH		 4441 .name = DRV_NAME,
4442 .id_table = sky2_id_table,
4443 .probe = sky2_probe,
4444 .remove = __devexit_p(sky2_remove),
cd28ab6a 4445#ifdef CONFIG_PM
793b883e
SH		 4446 .suspend = sky2_suspend,
4447 .resume = sky2_resume,
cd28ab6a 4448#endif
e3173832 4449 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4450};
4451
4452static int __init sky2_init_module(void)
4453{
3cf26753 4454 sky2_debug_init();
50241c4c 4455 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4456}
4457
4458static void __exit sky2_cleanup_module(void)
4459{
4460 pci_unregister_driver(&sky2_driver);
3cf26753 4461 sky2_debug_cleanup();
cd28ab6a
SH		 4462}
4463
4464module_init(sky2_init_module);
4465module_exit(sky2_cleanup_module);
4466
4467MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4468MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4469MODULE_LICENSE("GPL");
5f4f9dc1 4470MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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