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sky2: WoL changes
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a 26#include <linux/kernel.h>
cd28ab6a
SH		 27#include <linux/module.h>
28#include <linux/netdevice.h>
d0bbccfa 29#include <linux/dma-mapping.h>
cd28ab6a
SH		 30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/pci.h>
33#include <linux/ip.h>
c9bdd4b5 34#include <net/ip.h>
cd28ab6a
SH		 35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
3cf26753 41#include <linux/debugfs.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
ac958154 53#define DRV_VERSION "1.26"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
793b883e 66
ee5f68fe 67/* This is the worst case number of transmit list elements for a single skb:
07e31637
SH		 68 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
69#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
e9c1be80 70#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
ee5f68fe
SH		 71#define TX_MAX_PENDING 4096
72#define TX_DEF_PENDING 127
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
e6cac9ba 102static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
e30a4ac2 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
2d2a3871 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
0f5aac70 143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
cd28ab6a
SH		 144 { 0 }
145};
793b883e 146
cd28ab6a
SH		 147MODULE_DEVICE_TABLE(pci, sky2_id_table);
148
149/* Avoid conditionals by using array */
150static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
151static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 152static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 153
d1b139c0
SH		 154static void sky2_set_multicast(struct net_device *dev);
155
af043aa5 156/* Access to PHY via serial interconnect */
ef743d33 157static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 158{
159 int i;
160
161 gma_write16(hw, port, GM_SMI_DATA, val);
162 gma_write16(hw, port, GM_SMI_CTRL,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
164
165 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 166 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
167 if (ctrl == 0xffff)
168 goto io_error;
169
170 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 171 return 0;
af043aa5
SH		 172
173 udelay(10);
cd28ab6a 174 }
ef743d33 175
af043aa5 176 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 177 return -ETIMEDOUT;
af043aa5
SH		 178
179io_error:
180 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
181 return -EIO;
cd28ab6a
SH		 182}
183
ef743d33 184static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 185{
186 int i;
187
793b883e 188 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 189 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
190
191 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 192 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
193 if (ctrl == 0xffff)
194 goto io_error;
195
196 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33 197 *val = gma_read16(hw, port, GM_SMI_DATA);
198 return 0;
199 }
200
af043aa5 201 udelay(10);
cd28ab6a
SH		 202 }
203
af043aa5 204 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 205 return -ETIMEDOUT;
af043aa5
SH		 206io_error:
207 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
208 return -EIO;
ef743d33 209}
210
af043aa5 211static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33 212{
213 u16 v;
af043aa5 214 __gm_phy_read(hw, port, reg, &v);
ef743d33 215 return v;
cd28ab6a
SH		 216}
217
5afa0a9c 218
ae306cca
SH		 219static void sky2_power_on(struct sky2_hw *hw)
220{
221 /* switch power to VCC (WA for VAUX problem) */
222 sky2_write8(hw, B0_POWER_CTRL,
223 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 224
ae306cca
SH		 225 /* disable Core Clock Division, */
226 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 227
ae306cca
SH		 228 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
229 /* enable bits are inverted */
230 sky2_write8(hw, B2_Y2_CLK_GATE,
231 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
232 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
233 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
234 else
235 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 236
ea76e635 237 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 238 u32 reg;
5afa0a9c 239
b32f40c4 240 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 241
b32f40c4 242 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 243 /* set all bits to 0 except bits 15..12 and 8 */
244 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 245 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 246
b32f40c4 247 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 248 /* set all bits to 0 except bits 28 & 27 */
249 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 250 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 251
b32f40c4 252 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f 253
5f8ae5c5 254 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
255
8f70920f
SH		 256 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
257 reg = sky2_read32(hw, B2_GP_IO);
258 reg |= GLB_GPIO_STAT_RACE_DIS;
259 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 260
261 sky2_read32(hw, B2_GP_IO);
5afa0a9c 262 }
10547ae2
SH		 263
264 /* Turn on "driver loaded" LED */
265 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
ae306cca 266}
5afa0a9c 267
ae306cca
SH		 268static void sky2_power_aux(struct sky2_hw *hw)
269{
270 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
271 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
272 else
273 /* enable bits are inverted */
274 sky2_write8(hw, B2_Y2_CLK_GATE,
275 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
276 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
277 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
278
c23ddf8f
SH		 279 /* switch power to VAUX if supported and PME from D3cold */
280 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
281 pci_pme_capable(hw->pdev, PCI_D3cold))
ae306cca
SH		 282 sky2_write8(hw, B0_POWER_CTRL,
283 (PC_VAUX_ENA | PC_VCC_ENA |
284 PC_VAUX_ON | PC_VCC_OFF));
10547ae2
SH		 285
286 /* turn off "driver loaded LED" */
287 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
5afa0a9c 288}
289
d3bcfbeb 290static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 291{
292 u16 reg;
293
294 /* disable all GMAC IRQ's */
295 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 296
cd28ab6a
SH		 297 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
298 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
299 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
300 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
301
302 reg = gma_read16(hw, port, GM_RX_CTRL);
303 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
304 gma_write16(hw, port, GM_RX_CTRL, reg);
305}
306
16ad91e1
SH		 307/* flow control to advertise bits */
308static const u16 copper_fc_adv[] = {
309 [FC_NONE] = 0,
310 [FC_TX] = PHY_M_AN_ASP,
311 [FC_RX] = PHY_M_AN_PC,
312 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
313};
314
315/* flow control to advertise bits when using 1000BaseX */
316static const u16 fiber_fc_adv[] = {
df3fe1f3 317 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 318 [FC_TX] = PHY_M_P_ASYM_MD_X,
319 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 320 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 321};
322
323/* flow control to GMA disable bits */
324static const u16 gm_fc_disable[] = {
325 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
326 [FC_TX] = GM_GPCR_FC_RX_DIS,
327 [FC_RX] = GM_GPCR_FC_TX_DIS,
328 [FC_BOTH] = 0,
329};
330
331
cd28ab6a
SH		 332static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
333{
334 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 335 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 336
0ea065e5 337 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 338 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 339 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
340
341 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 342 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 343 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
344
53419c68 345 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 346 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 347 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 348 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
349 else
53419c68
SH		 350 /* set master & slave downshift counter to 1x */
351 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 352
353 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
354 }
355
356 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 357 if (sky2_is_copper(hw)) {
05745c4a 358 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 359 /* enable automatic crossover */
360 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 361
362 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
363 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
364 u16 spec;
365
366 /* Enable Class A driver for FE+ A0 */
367 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
368 spec |= PHY_M_FESC_SEL_CL_A;
369 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
370 }
cd28ab6a
SH		 371 } else {
372 /* disable energy detect */
373 ctrl &= ~PHY_M_PC_EN_DET_MSK;
374
375 /* enable automatic crossover */
376 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
377
53419c68 378 /* downshift on PHY 88E1112 and 88E1149 is changed */
8e95a202
JP		 379 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
380 (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 381 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 382 ctrl &= ~PHY_M_PC_DSC_MSK;
383 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
384 }
385 }
cd28ab6a
SH		 386 } else {
387 /* workaround for deviation #4.88 (CRC errors) */
388 /* disable Automatic Crossover */
389
390 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 391 }
cd28ab6a 392
b89165f2
SH		 393 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
394
395 /* special setup for PHY 88E1112 Fiber */
ea76e635 396 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 397 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 398
b89165f2
SH		 399 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
400 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
401 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
402 ctrl &= ~PHY_M_MAC_MD_MSK;
403 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
404 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
405
406 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 407 /* select page 1 to access Fiber registers */
408 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 409
410 /* for SFP-module set SIGDET polarity to low */
411 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
412 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 413 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 414 }
b89165f2
SH		 415
416 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 417 }
418
7800fddc 419 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 420 ct1000 = 0;
421 adv = PHY_AN_CSMA;
2eaba1a2 422 reg = 0;
cd28ab6a 423
0ea065e5 424 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 425 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 426 if (sky2->advertising & ADVERTISED_1000baseT_Full)
427 ct1000 |= PHY_M_1000C_AFD;
428 if (sky2->advertising & ADVERTISED_1000baseT_Half)
429 ct1000 |= PHY_M_1000C_AHD;
430 if (sky2->advertising & ADVERTISED_100baseT_Full)
431 adv |= PHY_M_AN_100_FD;
432 if (sky2->advertising & ADVERTISED_100baseT_Half)
433 adv |= PHY_M_AN_100_HD;
434 if (sky2->advertising & ADVERTISED_10baseT_Full)
435 adv |= PHY_M_AN_10_FD;
436 if (sky2->advertising & ADVERTISED_10baseT_Half)
437 adv |= PHY_M_AN_10_HD;
709c6e7b 438
b89165f2
SH		 439 } else { /* special defines for FIBER (88E1040S only) */
440 if (sky2->advertising & ADVERTISED_1000baseT_Full)
441 adv |= PHY_M_AN_1000X_AFD;
442 if (sky2->advertising & ADVERTISED_1000baseT_Half)
443 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 444 }
cd28ab6a
SH		 445
446 /* Restart Auto-negotiation */
447 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
448 } else {
449 /* forced speed/duplex settings */
450 ct1000 = PHY_M_1000C_MSE;
451
0ea065e5
SH		 452 /* Disable auto update for duplex flow control and duplex */
453 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 454
455 switch (sky2->speed) {
456 case SPEED_1000:
457 ctrl |= PHY_CT_SP1000;
2eaba1a2 458 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 459 break;
460 case SPEED_100:
461 ctrl |= PHY_CT_SP100;
2eaba1a2 462 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 463 break;
464 }
465
2eaba1a2
SH		 466 if (sky2->duplex == DUPLEX_FULL) {
467 reg |= GM_GPCR_DUP_FULL;
468 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 469 } else if (sky2->speed < SPEED_1000)
470 sky2->flow_mode = FC_NONE;
0ea065e5 471 }
2eaba1a2 472
0ea065e5
SH		 473 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
474 if (sky2_is_copper(hw))
475 adv |= copper_fc_adv[sky2->flow_mode];
476 else
477 adv |= fiber_fc_adv[sky2->flow_mode];
478 } else {
479 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 480 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 481
482 /* Forward pause packets to GMAC? */
16ad91e1 483 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 484 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
485 else
486 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 487 }
488
2eaba1a2
SH		 489 gma_write16(hw, port, GM_GP_CTRL, reg);
490
05745c4a 491 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 492 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
493
494 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
495 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
496
497 /* Setup Phy LED's */
498 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
499 ledover = 0;
500
501 switch (hw->chip_id) {
502 case CHIP_ID_YUKON_FE:
503 /* on 88E3082 these bits are at 11..9 (shifted left) */
504 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
505
506 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
507
508 /* delete ACT LED control bits */
509 ctrl &= ~PHY_M_FELP_LED1_MSK;
510 /* change ACT LED control to blink mode */
511 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
512 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
513 break;
514
05745c4a
SH		 515 case CHIP_ID_YUKON_FE_P:
516 /* Enable Link Partner Next Page */
517 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
518 ctrl |= PHY_M_PC_ENA_LIP_NP;
519
520 /* disable Energy Detect and enable scrambler */
521 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
523
524 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
525 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
526 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
527 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
528
529 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
530 break;
531
cd28ab6a 532 case CHIP_ID_YUKON_XL:
793b883e 533 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 534
535 /* select page 3 to access LED control register */
536 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
537
538 /* set LED Function Control register */
ed6d32c7
SH		 539 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
540 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
541 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
542 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
543 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 544
545 /* set Polarity Control register */
546 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 547 (PHY_M_POLC_LS1_P_MIX(4) |
548 PHY_M_POLC_IS0_P_MIX(4) |
549 PHY_M_POLC_LOS_CTRL(2) |
550 PHY_M_POLC_INIT_CTRL(2) |
551 PHY_M_POLC_STA1_CTRL(2) |
552 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 553
554 /* restore page register */
793b883e 555 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 556 break;
93745494 557
ed6d32c7 558 case CHIP_ID_YUKON_EC_U:
93745494 559 case CHIP_ID_YUKON_EX:
ed4d4161 560 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 561 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
562
563 /* select page 3 to access LED control register */
564 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
565
566 /* set LED Function Control register */
567 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
568 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
569 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
570 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
571 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
572
573 /* set Blink Rate in LED Timer Control Register */
574 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
575 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
576 /* restore page register */
577 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
578 break;
cd28ab6a
SH		 579
580 default:
581 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
582 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 583
cd28ab6a 584 /* turn off the Rx LED (LED_RX) */
a84d0a3d 585 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 586 }
587
0ce8b98d 588 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 589 /* apply fixes in PHY AFE */
ed6d32c7
SH		 590 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
591
977bdf06 592 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 593 gm_phy_write(hw, port, 0x18, 0xaa99);
594 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 595
0ce8b98d
SH		 596 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
597 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
598 gm_phy_write(hw, port, 0x18, 0xa204);
599 gm_phy_write(hw, port, 0x17, 0x2002);
600 }
977bdf06
SH		 601
602 /* set page register to 0 */
9467a8fc 603 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 604 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
605 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
606 /* apply workaround for integrated resistors calibration */
607 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
608 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
0f5aac70
SH		 609 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
610 /* apply fixes in PHY AFE */
611 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
612
613 /* apply RDAC termination workaround */
614 gm_phy_write(hw, port, 24, 0x2800);
615 gm_phy_write(hw, port, 23, 0x2001);
616
617 /* set page register back to 0 */
618 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
e1a74b37
SH		 619 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
620 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 621 /* no effect on Yukon-XL */
977bdf06 622 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 623
8e95a202
JP		 624 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
625 sky2->speed == SPEED_100) {
977bdf06 626 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 627 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 628 }
cd28ab6a 629
977bdf06
SH		 630 if (ledover)
631 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
632
633 }
2eaba1a2 634
d571b694 635 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 636 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 637 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
638 else
639 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
640}
641
b96936da
SH		 642static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
643static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
644
645static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb 646{
647 u32 reg1;
d3bcfbeb 648
a40ccc68 649 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 650 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 651 reg1 &= ~phy_power[port];
d3bcfbeb 652
b96936da 653 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 654 reg1 |= coma_mode[port];
655
b32f40c4 656 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 657 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
82637e80 658 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 659
660 if (hw->chip_id == CHIP_ID_YUKON_FE)
661 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
662 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
663 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 664}
167f53d0 665
b96936da
SH		 666static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
667{
668 u32 reg1;
db99b988
SH		 669 u16 ctrl;
670
671 /* release GPHY Control reset */
672 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
673
674 /* release GMAC reset */
675 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
676
677 if (hw->flags & SKY2_HW_NEWER_PHY) {
678 /* select page 2 to access MAC control register */
679 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
680
681 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
682 /* allow GMII Power Down */
683 ctrl &= ~PHY_M_MAC_GMIF_PUP;
684 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
685
686 /* set page register back to 0 */
687 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
688 }
689
690 /* setup General Purpose Control Register */
691 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 692 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
693 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
694 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 695
696 if (hw->chip_id != CHIP_ID_YUKON_EC) {
697 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 698 /* select page 2 to access MAC control register */
699 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 700
e484d5f5 701 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 702 /* enable Power Down */
703 ctrl |= PHY_M_PC_POW_D_ENA;
704 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 705
706 /* set page register back to 0 */
707 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 708 }
709
710 /* set IEEE compatible Power Down Mode (dev. #4.99) */
711 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
712 }
b96936da 713
a40ccc68 714 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b96936da 715 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 716 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da 717 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 718 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb 719}
720
1b537565
SH		 721/* Force a renegotiation */
722static void sky2_phy_reinit(struct sky2_port *sky2)
723{
e07b1aa8 724 spin_lock_bh(&sky2->phy_lock);
1b537565 725 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 726 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 727}
728
e3173832
SH		 729/* Put device in state to listen for Wake On Lan */
730static void sky2_wol_init(struct sky2_port *sky2)
731{
732 struct sky2_hw *hw = sky2->hw;
733 unsigned port = sky2->port;
734 enum flow_control save_mode;
735 u16 ctrl;
736 u32 reg1;
737
738 /* Bring hardware out of reset */
739 sky2_write16(hw, B0_CTST, CS_RST_CLR);
740 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
741
742 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
743 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
744
745 /* Force to 10/100
746 * sky2_reset will re-enable on resume
747 */
748 save_mode = sky2->flow_mode;
749 ctrl = sky2->advertising;
750
751 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
752 sky2->flow_mode = FC_NONE;
b96936da
SH		 753
754 spin_lock_bh(&sky2->phy_lock);
755 sky2_phy_power_up(hw, port);
756 sky2_phy_init(hw, port);
757 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 758
759 sky2->flow_mode = save_mode;
760 sky2->advertising = ctrl;
761
762 /* Set GMAC to no flow control and auto update for speed/duplex */
763 gma_write16(hw, port, GM_GP_CTRL,
764 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
765 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
766
767 /* Set WOL address */
768 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
769 sky2->netdev->dev_addr, ETH_ALEN);
770
771 /* Turn on appropriate WOL control bits */
772 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
773 ctrl = 0;
774 if (sky2->wol & WAKE_PHY)
775 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
776 else
777 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
778
779 if (sky2->wol & WAKE_MAGIC)
780 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
781 else
a419aef8 782 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
e3173832
SH		 783
784 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
785 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
786
5f8ae5c5 787 /* Disable PiG firmware */
788 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
789
e3173832 790 /* Turn on legacy PCI-Express PME mode */
b32f40c4 791 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 792 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 793 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 794
795 /* block receiver */
796 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
e3173832
SH		 797}
798
69161611
SH		 799static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
800{
05745c4a
SH		 801 struct net_device *dev = hw->dev[port];
802
ed4d4161
SH		 803 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
804 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
877c8570 805 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
ed4d4161
SH		 806 /* Yukon-Extreme B0 and further Extreme devices */
807 /* enable Store & Forward mode for TX */
05745c4a 808
ed4d4161
SH		 809 if (dev->mtu <= ETH_DATA_LEN)
810 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
811 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 812
ed4d4161
SH		 813 else
814 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
815 TX_JUMBO_ENA| TX_STFW_ENA);
816 } else {
817 if (dev->mtu <= ETH_DATA_LEN)
818 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
819 else {
820 /* set Tx GMAC FIFO Almost Empty Threshold */
821 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
822 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 823
ed4d4161
SH		 824 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
825
826 /* Can't do offload because of lack of store/forward */
827 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
828 }
69161611
SH		 829 }
830}
831
cd28ab6a
SH		 832static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
833{
834 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
835 u16 reg;
25cccecc 836 u32 rx_reg;
cd28ab6a
SH		 837 int i;
838 const u8 *addr = hw->dev[port]->dev_addr;
839
f350339c
SH		 840 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
841 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 842
843 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
844
793b883e 845 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 846 /* WA DEV_472 -- looks like crossed wires on port 2 */
847 /* clear GMAC 1 Control reset */
848 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
849 do {
850 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
851 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
852 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
853 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
854 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
855 }
856
793b883e 857 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 858
2eaba1a2
SH		 859 /* Enable Transmit FIFO Underrun */
860 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
861
e07b1aa8 862 spin_lock_bh(&sky2->phy_lock);
b96936da 863 sky2_phy_power_up(hw, port);
cd28ab6a 864 sky2_phy_init(hw, port);
e07b1aa8 865 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 866
867 /* MIB clear */
868 reg = gma_read16(hw, port, GM_PHY_ADDR);
869 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
870
43f2f104
SH		 871 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
872 gma_read16(hw, port, i);
cd28ab6a
SH		 873 gma_write16(hw, port, GM_PHY_ADDR, reg);
874
875 /* transmit control */
876 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
877
878 /* receive control reg: unicast + multicast + no FCS */
879 gma_write16(hw, port, GM_RX_CTRL,
793b883e 880 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 881
882 /* transmit flow control */
883 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
884
885 /* transmit parameter */
886 gma_write16(hw, port, GM_TX_PARAM,
887 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
888 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
889 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
890 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
891
892 /* serial mode register */
893 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 894 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 895
6b1a3aef 896 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 897 reg |= GM_SMOD_JUMBO_ENA;
898
899 gma_write16(hw, port, GM_SERIAL_MODE, reg);
900
cd28ab6a
SH		 901 /* virtual address for data */
902 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
903
793b883e
SH		 904 /* physical address: used for pause frames */
905 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
906
907 /* ignore counter overflows */
cd28ab6a
SH		 908 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
909 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
910 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
911
912 /* Configure Rx MAC FIFO */
913 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 914 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 915 if (hw->chip_id == CHIP_ID_YUKON_EX ||
916 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 917 rx_reg |= GMF_RX_OVER_ON;
69161611 918
25cccecc 919 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 920
798fdd07
SH		 921 if (hw->chip_id == CHIP_ID_YUKON_XL) {
922 /* Hardware errata - clear flush mask */
923 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
924 } else {
925 /* Flush Rx MAC FIFO on any flow control or error */
926 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
927 }
cd28ab6a 928
8df9a876 929 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 930 reg = RX_GMF_FL_THR_DEF + 1;
931 /* Another magic mystery workaround from sk98lin */
932 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
933 hw->chip_rev == CHIP_REV_YU_FE2_A0)
934 reg = 0x178;
935 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 936
937 /* Configure Tx MAC FIFO */
938 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
939 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 940
e0c28116 941 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 942 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
d6b54d24 943 /* Pause threshold is scaled by 8 in bytes */
8e95a202
JP		 944 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
945 hw->chip_rev == CHIP_REV_YU_FE2_A0)
d6b54d24
SH		 946 reg = 1568 / 8;
947 else
948 reg = 1024 / 8;
949 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
950 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
b628ed98 951
69161611 952 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 953 }
954
e970d1f8
SH		 955 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
956 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
957 /* disable dynamic watermark */
958 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
959 reg &= ~TX_DYN_WM_ENA;
960 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
961 }
cd28ab6a
SH		 962}
963
67712901
SH		 964/* Assign Ram Buffer allocation to queue */
965static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 966{
67712901
SH		 967 u32 end;
968
969 /* convert from K bytes to qwords used for hw register */
970 start *= 1024/8;
971 space *= 1024/8;
972 end = start + space - 1;
793b883e 973
cd28ab6a
SH		 974 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
975 sky2_write32(hw, RB_ADDR(q, RB_START), start);
976 sky2_write32(hw, RB_ADDR(q, RB_END), end);
977 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
978 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
979
980 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 981 u32 tp = space - space/4;
793b883e 982
1c28f6ba
SH		 983 /* On receive queue's set the thresholds
984 * give receiver priority when > 3/4 full
985 * send pause when down to 2K
986 */
987 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
988 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 989
1c28f6ba
SH		 990 tp = space - 2048/8;
991 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
992 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 993 } else {
994 /* Enable store & forward on Tx queue's because
995 * Tx FIFO is only 1K on Yukon
996 */
997 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
998 }
999
1000 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 1001 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 1002}
1003
cd28ab6a 1004/* Setup Bus Memory Interface */
af4ed7e6 1005static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 1006{
1007 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1008 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1009 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 1010 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 1011}
1012
cd28ab6a
SH		 1013/* Setup prefetch unit registers. This is the interface between
1014 * hardware and driver list elements
1015 */
8cc048e3 1016static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 1017 dma_addr_t addr, u32 last)
cd28ab6a 1018{
cd28ab6a
SH		 1019 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1020 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 1021 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1022 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 1023 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1024 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1025
1026 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1027}
1028
9b289c33 1029static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1030{
9b289c33 1031 struct sky2_tx_le *le = sky2->tx_le + *slot;
793b883e 1032
ee5f68fe 1033 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
291ea614 1034 le->ctrl = 0;
793b883e
SH		 1035 return le;
1036}
cd28ab6a 1037
88f5f0ca
SH		 1038static void tx_init(struct sky2_port *sky2)
1039{
1040 struct sky2_tx_le *le;
1041
1042 sky2->tx_prod = sky2->tx_cons = 0;
1043 sky2->tx_tcpsum = 0;
1044 sky2->tx_last_mss = 0;
1045
9b289c33 1046 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1047 le->addr = 0;
1048 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1049 sky2->tx_last_upper = 0;
88f5f0ca
SH		 1050}
1051
290d4de5
SH		 1052/* Update chip's next pointer */
1053static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1054{
50432cb5 1055 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1056 wmb();
50432cb5
SH		 1057 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1058
1059 /* Synchronize I/O on since next processor may write to tail */
1060 mmiowb();
cd28ab6a
SH		 1061}
1062
793b883e 1063
cd28ab6a
SH		 1064static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1065{
1066 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1067 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1068 le->ctrl = 0;
cd28ab6a
SH		 1069 return le;
1070}
1071
14d0263f
SH		 1072/* Build description to hardware for one receive segment */
1073static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1074 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1075{
1076 struct sky2_rx_le *le;
1077
86c6887e 1078 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1079 le = sky2_next_rx(sky2);
86c6887e 1080 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1081 le->opcode = OP_ADDR64 | HW_OWNER;
1082 }
793b883e 1083
cd28ab6a 1084 le = sky2_next_rx(sky2);
d6e74b6b 1085 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1086 le->length = cpu_to_le16(len);
14d0263f 1087 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1088}
1089
14d0263f
SH		 1090/* Build description to hardware for one possibly fragmented skb */
1091static void sky2_rx_submit(struct sky2_port *sky2,
1092 const struct rx_ring_info *re)
1093{
1094 int i;
1095
1096 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1097
1098 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1099 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1100}
1101
1102
454e6cb6 1103static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1104 unsigned size)
1105{
1106 struct sk_buff *skb = re->skb;
1107 int i;
1108
1109 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
3fbd9187 1110 if (pci_dma_mapping_error(pdev, re->data_addr))
1111 goto mapping_error;
454e6cb6 1112
14d0263f
SH		 1113 pci_unmap_len_set(re, data_size, size);
1114
3fbd9187 1115 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1116 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1117
1118 re->frag_addr[i] = pci_map_page(pdev, frag->page,
1119 frag->page_offset,
1120 frag->size,
14d0263f 1121 PCI_DMA_FROMDEVICE);
3fbd9187 1122
1123 if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
1124 goto map_page_error;
1125 }
454e6cb6 1126 return 0;
3fbd9187 1127
1128map_page_error:
1129 while (--i >= 0) {
1130 pci_unmap_page(pdev, re->frag_addr[i],
1131 skb_shinfo(skb)->frags[i].size,
1132 PCI_DMA_FROMDEVICE);
1133 }
1134
1135 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1136 PCI_DMA_FROMDEVICE);
1137
1138mapping_error:
1139 if (net_ratelimit())
1140 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1141 skb->dev->name);
1142 return -EIO;
14d0263f
SH		 1143}
1144
1145static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1146{
1147 struct sk_buff *skb = re->skb;
1148 int i;
1149
1150 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1151 PCI_DMA_FROMDEVICE);
1152
1153 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1154 pci_unmap_page(pdev, re->frag_addr[i],
1155 skb_shinfo(skb)->frags[i].size,
1156 PCI_DMA_FROMDEVICE);
1157}
793b883e 1158
cd28ab6a
SH		 1159/* Tell chip where to start receive checksum.
1160 * Actually has two checksums, but set both same to avoid possible byte
1161 * order problems.
1162 */
793b883e 1163static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1164{
ea76e635 1165 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1166
ea76e635
SH		 1167 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1168 le->ctrl = 0;
1169 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1170
ea76e635
SH		 1171 sky2_write32(sky2->hw,
1172 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
0ea065e5
SH		 1173 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1174 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1175}
1176
6b1a3aef 1177/*
1178 * The RX Stop command will not work for Yukon-2 if the BMU does not
1179 * reach the end of packet and since we can't make sure that we have
1180 * incoming data, we must reset the BMU while it is not doing a DMA
1181 * transfer. Since it is possible that the RX path is still active,
1182 * the RX RAM buffer will be stopped first, so any possible incoming
1183 * data will not trigger a DMA. After the RAM buffer is stopped, the
1184 * BMU is polled until any DMA in progress is ended and only then it
1185 * will be reset.
1186 */
1187static void sky2_rx_stop(struct sky2_port *sky2)
1188{
1189 struct sky2_hw *hw = sky2->hw;
1190 unsigned rxq = rxqaddr[sky2->port];
1191 int i;
1192
1193 /* disable the RAM Buffer receive queue */
1194 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1195
1196 for (i = 0; i < 0xffff; i++)
1197 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1198 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1199 goto stopped;
1200
1201 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1202 sky2->netdev->name);
1203stopped:
1204 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1205
1206 /* reset the Rx prefetch unit */
1207 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1208 mmiowb();
6b1a3aef 1209}
793b883e 1210
d571b694 1211/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1212static void sky2_rx_clean(struct sky2_port *sky2)
1213{
1214 unsigned i;
1215
1216 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1217 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1218 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1219
1220 if (re->skb) {
14d0263f 1221 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1222 kfree_skb(re->skb);
1223 re->skb = NULL;
1224 }
1225 }
1226}
1227
ef743d33 1228/* Basic MII support */
1229static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1230{
1231 struct mii_ioctl_data *data = if_mii(ifr);
1232 struct sky2_port *sky2 = netdev_priv(dev);
1233 struct sky2_hw *hw = sky2->hw;
1234 int err = -EOPNOTSUPP;
1235
1236 if (!netif_running(dev))
1237 return -ENODEV; /* Phy still in reset */
1238
d89e1343 1239 switch (cmd) {
ef743d33 1240 case SIOCGMIIPHY:
1241 data->phy_id = PHY_ADDR_MARV;
1242
1243 /* fallthru */
1244 case SIOCGMIIREG: {
1245 u16 val = 0;
91c86df5 1246
e07b1aa8 1247 spin_lock_bh(&sky2->phy_lock);
ef743d33 1248 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1249 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1250
ef743d33 1251 data->val_out = val;
1252 break;
1253 }
1254
1255 case SIOCSMIIREG:
e07b1aa8 1256 spin_lock_bh(&sky2->phy_lock);
ef743d33 1257 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1258 data->val_in);
e07b1aa8 1259 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1260 break;
1261 }
1262 return err;
1263}
1264
d1f13708 1265#ifdef SKY2_VLAN_TAG_USED
d494eacd 1266static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1267{
d494eacd 1268 if (onoff) {
3d4e66f5
SH		 1269 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1270 RX_VLAN_STRIP_ON);
1271 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1272 TX_VLAN_TAG_ON);
1273 } else {
1274 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1275 RX_VLAN_STRIP_OFF);
1276 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1277 TX_VLAN_TAG_OFF);
1278 }
d494eacd
SH		 1279}
1280
1281static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1282{
1283 struct sky2_port *sky2 = netdev_priv(dev);
1284 struct sky2_hw *hw = sky2->hw;
1285 u16 port = sky2->port;
1286
1287 netif_tx_lock_bh(dev);
1288 napi_disable(&hw->napi);
1289
1290 sky2->vlgrp = grp;
1291 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1292
d1d08d12 1293 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1294 napi_enable(&hw->napi);
2bb8c262 1295 netif_tx_unlock_bh(dev);
d1f13708 1296}
1297#endif
1298
bd1c6869
SH		 1299/* Amount of required worst case padding in rx buffer */
1300static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1301{
1302 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1303}
1304
82788c7a 1305/*
14d0263f
SH		 1306 * Allocate an skb for receiving. If the MTU is large enough
1307 * make the skb non-linear with a fragment list of pages.
82788c7a 1308 */
14d0263f 1309static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1310{
1311 struct sk_buff *skb;
14d0263f 1312 int i;
82788c7a 1313
724b6942
SH		 1314 skb = netdev_alloc_skb(sky2->netdev,
1315 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
bd1c6869
SH		 1316 if (!skb)
1317 goto nomem;
1318
39dbd958 1319 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1320 unsigned char *start;
1321 /*
1322 * Workaround for a bug in FIFO that cause hang
1323 * if the FIFO if the receive buffer is not 64 byte aligned.
1324 * The buffer returned from netdev_alloc_skb is
1325 * aligned except if slab debugging is enabled.
1326 */
f03b8654
SH		 1327 start = PTR_ALIGN(skb->data, 8);
1328 skb_reserve(skb, start - skb->data);
bd1c6869 1329 } else
f03b8654 1330 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1331
1332 for (i = 0; i < sky2->rx_nfrags; i++) {
1333 struct page *page = alloc_page(GFP_ATOMIC);
1334
1335 if (!page)
1336 goto free_partial;
1337 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1338 }
1339
1340 return skb;
14d0263f
SH		 1341free_partial:
1342 kfree_skb(skb);
1343nomem:
1344 return NULL;
82788c7a
SH		 1345}
1346
55c9dd35
SH		 1347static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1348{
1349 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1350}
1351
cd28ab6a
SH		 1352/*
1353 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1354 * Normal case this ends up creating one list element for skb
1355 * in the receive ring. Worst case if using large MTU and each
1356 * allocation falls on a different 64 bit region, that results
1357 * in 6 list elements per ring entry.
1358 * One element is used for checksum enable/disable, and one
1359 * extra to avoid wrap.
cd28ab6a 1360 */
6b1a3aef 1361static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1362{
6b1a3aef 1363 struct sky2_hw *hw = sky2->hw;
14d0263f 1364 struct rx_ring_info *re;
6b1a3aef 1365 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1366 unsigned i, size, thresh;
cd28ab6a 1367
6b1a3aef 1368 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1369 sky2_qset(hw, rxq);
977bdf06 1370
c3905bc4
SH		 1371 /* On PCI express lowering the watermark gives better performance */
1372 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1373 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1374
1375 /* These chips have no ram buffer?
1376 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1377 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
8e95a202
JP		 1378 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 ||
1379 hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1380 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1381
6b1a3aef 1382 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1383
ea76e635
SH		 1384 if (!(hw->flags & SKY2_HW_NEW_LE))
1385 rx_set_checksum(sky2);
14d0263f
SH		 1386
1387 /* Space needed for frame data + headers rounded up */
f957da2a 1388 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1389
1390 /* Stopping point for hardware truncation */
1391 thresh = (size - 8) / sizeof(u32);
1392
5f06eba4 1393 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1394 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1395
5f06eba4
SH		 1396 /* Compute residue after pages */
1397 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1398
5f06eba4
SH		 1399 /* Optimize to handle small packets and headers */
1400 if (size < copybreak)
1401 size = copybreak;
1402 if (size < ETH_HLEN)
1403 size = ETH_HLEN;
14d0263f 1404
14d0263f
SH		 1405 sky2->rx_data_size = size;
1406
1407 /* Fill Rx ring */
793b883e 1408 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1409 re = sky2->rx_ring + i;
cd28ab6a 1410
14d0263f 1411 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1412 if (!re->skb)
1413 goto nomem;
1414
454e6cb6
SH		 1415 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1416 dev_kfree_skb(re->skb);
1417 re->skb = NULL;
1418 goto nomem;
1419 }
1420
14d0263f 1421 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1422 }
1423
a1433ac4
SH		 1424 /*
1425 * The receiver hangs if it receives frames larger than the
1426 * packet buffer. As a workaround, truncate oversize frames, but
1427 * the register is limited to 9 bits, so if you do frames > 2052
1428 * you better get the MTU right!
1429 */
a1433ac4
SH		 1430 if (thresh > 0x1ff)
1431 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1432 else {
1433 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1434 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1435 }
1436
6b1a3aef 1437 /* Tell chip about available buffers */
55c9dd35 1438 sky2_rx_update(sky2, rxq);
877c8570
SH		 1439
1440 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1441 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1442 /*
1443 * Disable flushing of non ASF packets;
1444 * must be done after initializing the BMUs;
1445 * drivers without ASF support should do this too, otherwise
1446 * it may happen that they cannot run on ASF devices;
1447 * remember that the MAC FIFO isn't reset during initialization.
1448 */
1449 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1450 }
1451
1452 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1453 /* Enable RX Home Address & Routing Header checksum fix */
1454 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1455 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1456
1457 /* Enable TX Home Address & Routing Header checksum fix */
1458 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1459 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1460 }
1461
1462
1463
cd28ab6a
SH		 1464 return 0;
1465nomem:
1466 sky2_rx_clean(sky2);
1467 return -ENOMEM;
1468}
1469
90bbebb4
MM		 1470static int sky2_alloc_buffers(struct sky2_port *sky2)
1471{
1472 struct sky2_hw *hw = sky2->hw;
1473
1474 /* must be power of 2 */
1475 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1476 sky2->tx_ring_size *
1477 sizeof(struct sky2_tx_le),
1478 &sky2->tx_le_map);
1479 if (!sky2->tx_le)
1480 goto nomem;
1481
1482 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1483 GFP_KERNEL);
1484 if (!sky2->tx_ring)
1485 goto nomem;
1486
1487 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1488 &sky2->rx_le_map);
1489 if (!sky2->rx_le)
1490 goto nomem;
1491 memset(sky2->rx_le, 0, RX_LE_BYTES);
1492
1493 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1494 GFP_KERNEL);
1495 if (!sky2->rx_ring)
1496 goto nomem;
1497
1498 return 0;
1499nomem:
1500 return -ENOMEM;
1501}
1502
1503static void sky2_free_buffers(struct sky2_port *sky2)
1504{
1505 struct sky2_hw *hw = sky2->hw;
1506
1507 if (sky2->rx_le) {
1508 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1509 sky2->rx_le, sky2->rx_le_map);
1510 sky2->rx_le = NULL;
1511 }
1512 if (sky2->tx_le) {
1513 pci_free_consistent(hw->pdev,
1514 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1515 sky2->tx_le, sky2->tx_le_map);
1516 sky2->tx_le = NULL;
1517 }
1518 kfree(sky2->tx_ring);
1519 kfree(sky2->rx_ring);
1520
1521 sky2->tx_ring = NULL;
1522 sky2->rx_ring = NULL;
1523}
1524
cd28ab6a
SH		 1525/* Bring up network interface. */
1526static int sky2_up(struct net_device *dev)
1527{
1528 struct sky2_port *sky2 = netdev_priv(dev);
1529 struct sky2_hw *hw = sky2->hw;
1530 unsigned port = sky2->port;
e0c28116 1531 u32 imask, ramsize;
90bbebb4 1532 int cap, err;
843a46f4 1533 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1534
ee7abb04
SH		 1535 /*
1536 * On dual port PCI-X card, there is an problem where status
1537 * can be received out of order due to split transactions
843a46f4 1538 */
ee7abb04
SH		 1539 if (otherdev && netif_running(otherdev) &&
1540 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1541 u16 cmd;
1542
b32f40c4 1543 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1544 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1545 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1546
ee7abb04 1547 }
843a46f4 1548
55d7b4e6
SH		 1549 netif_carrier_off(dev);
1550
90bbebb4
MM		 1551 err = sky2_alloc_buffers(sky2);
1552 if (err)
cd28ab6a 1553 goto err_out;
88f5f0ca
SH		 1554
1555 tx_init(sky2);
cd28ab6a 1556
cd28ab6a
SH		 1557 sky2_mac_init(hw, port);
1558
e0c28116
SH		 1559 /* Register is number of 4K blocks on internal RAM buffer. */
1560 ramsize = sky2_read8(hw, B2_E_0) * 4;
1561 if (ramsize > 0) {
67712901 1562 u32 rxspace;
cd28ab6a 1563
e0c28116 1564 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1565 if (ramsize < 16)
1566 rxspace = ramsize / 2;
1567 else
1568 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1569
67712901
SH		 1570 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1571 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1572
1573 /* Make sure SyncQ is disabled */
1574 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1575 RB_RST_SET);
1576 }
793b883e 1577
af4ed7e6 1578 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1579
69161611
SH		 1580 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1581 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1582 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1583
977bdf06 1584 /* Set almost empty threshold */
8e95a202
JP		 1585 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1586 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1587 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1588
6b1a3aef 1589 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
ee5f68fe 1590 sky2->tx_ring_size - 1);
cd28ab6a 1591
d494eacd
SH		 1592#ifdef SKY2_VLAN_TAG_USED
1593 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1594#endif
1595
6b1a3aef 1596 err = sky2_rx_start(sky2);
6de16237 1597 if (err)
cd28ab6a
SH		 1598 goto err_out;
1599
cd28ab6a 1600 /* Enable interrupts from phy/mac for port */
e07b1aa8 1601 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1602 imask |= portirq_msk[port];
e07b1aa8 1603 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1604 sky2_read32(hw, B0_IMSK);
e07b1aa8 1605
a11da890
AD		 1606 if (netif_msg_ifup(sky2))
1607 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
af18d8b8 1608
cd28ab6a
SH		 1609 return 0;
1610
1611err_out:
90bbebb4 1612 sky2_free_buffers(sky2);
cd28ab6a
SH		 1613 return err;
1614}
1615
793b883e 1616/* Modular subtraction in ring */
ee5f68fe 1617static inline int tx_inuse(const struct sky2_port *sky2)
793b883e 1618{
ee5f68fe 1619 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
793b883e 1620}
cd28ab6a 1621
793b883e
SH		 1622/* Number of list elements available for next tx */
1623static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1624{
ee5f68fe 1625 return sky2->tx_pending - tx_inuse(sky2);
cd28ab6a
SH		 1626}
1627
793b883e 1628/* Estimate of number of transmit list elements required */
28bd181a 1629static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1630{
793b883e
SH		 1631 unsigned count;
1632
07e31637
SH		 1633 count = (skb_shinfo(skb)->nr_frags + 1)
1634 * (sizeof(dma_addr_t) / sizeof(u32));
793b883e 1635
89114afd 1636 if (skb_is_gso(skb))
793b883e 1637 ++count;
07e31637
SH		 1638 else if (sizeof(dma_addr_t) == sizeof(u32))
1639 ++count; /* possible vlan */
793b883e 1640
84fa7933 1641 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1642 ++count;
1643
1644 return count;
cd28ab6a
SH		 1645}
1646
f6815077 1647static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
6b84daca
SH		 1648{
1649 if (re->flags & TX_MAP_SINGLE)
1650 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1651 pci_unmap_len(re, maplen),
1652 PCI_DMA_TODEVICE);
1653 else if (re->flags & TX_MAP_PAGE)
1654 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1655 pci_unmap_len(re, maplen),
1656 PCI_DMA_TODEVICE);
f6815077 1657 re->flags = 0;
6b84daca
SH		 1658}
1659
793b883e
SH		 1660/*
1661 * Put one packet in ring for transmit.
1662 * A single packet can generate multiple list elements, and
1663 * the number of ring elements will probably be less than the number
1664 * of list elements used.
1665 */
61357325
SH		 1666static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1667 struct net_device *dev)
cd28ab6a
SH		 1668{
1669 struct sky2_port *sky2 = netdev_priv(dev);
1670 struct sky2_hw *hw = sky2->hw;
d1f13708 1671 struct sky2_tx_le *le = NULL;
6cdbbdf3 1672 struct tx_ring_info *re;
9b289c33 1673 unsigned i, len;
cd28ab6a 1674 dma_addr_t mapping;
5dce95e5
SH		 1675 u32 upper;
1676 u16 slot;
cd28ab6a
SH		 1677 u16 mss;
1678 u8 ctrl;
1679
2bb8c262
SH		 1680 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1681 return NETDEV_TX_BUSY;
cd28ab6a 1682
cd28ab6a
SH		 1683 len = skb_headlen(skb);
1684 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1685
454e6cb6
SH		 1686 if (pci_dma_mapping_error(hw->pdev, mapping))
1687 goto mapping_error;
1688
9b289c33 1689 slot = sky2->tx_prod;
454e6cb6
SH		 1690 if (unlikely(netif_msg_tx_queued(sky2)))
1691 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
9b289c33 1692 dev->name, slot, skb->len);
454e6cb6 1693
86c6887e 1694 /* Send high bits if needed */
5dce95e5
SH		 1695 upper = upper_32_bits(mapping);
1696 if (upper != sky2->tx_last_upper) {
9b289c33 1697 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1698 le->addr = cpu_to_le32(upper);
1699 sky2->tx_last_upper = upper;
793b883e 1700 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1701 }
cd28ab6a
SH		 1702
1703 /* Check for TCP Segmentation Offload */
7967168c 1704 mss = skb_shinfo(skb)->gso_size;
793b883e 1705 if (mss != 0) {
ea76e635
SH		 1706
1707 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1708 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1709
1710 if (mss != sky2->tx_last_mss) {
9b289c33 1711 le = get_tx_le(sky2, &slot);
69161611 1712 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1713
1714 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1715 le->opcode = OP_MSS | HW_OWNER;
1716 else
1717 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1718 sky2->tx_last_mss = mss;
1719 }
cd28ab6a
SH		 1720 }
1721
cd28ab6a 1722 ctrl = 0;
d1f13708 1723#ifdef SKY2_VLAN_TAG_USED
1724 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1725 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1726 if (!le) {
9b289c33 1727 le = get_tx_le(sky2, &slot);
f65b138c 1728 le->addr = 0;
d1f13708 1729 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1730 } else
1731 le->opcode |= OP_VLAN;
1732 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1733 ctrl |= INS_VLAN;
1734 }
1735#endif
1736
1737 /* Handle TCP checksum offload */
84fa7933 1738 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1739 /* On Yukon EX (some versions) encoding change. */
ea76e635 1740 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1741 ctrl |= CALSUM; /* auto checksum */
1742 else {
1743 const unsigned offset = skb_transport_offset(skb);
1744 u32 tcpsum;
1745
1746 tcpsum = offset << 16; /* sum start */
1747 tcpsum |= offset + skb->csum_offset; /* sum write */
1748
1749 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1750 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1751 ctrl |= UDPTCP;
1752
1753 if (tcpsum != sky2->tx_tcpsum) {
1754 sky2->tx_tcpsum = tcpsum;
1755
9b289c33 1756 le = get_tx_le(sky2, &slot);
69161611
SH		 1757 le->addr = cpu_to_le32(tcpsum);
1758 le->length = 0; /* initial checksum value */
1759 le->ctrl = 1; /* one packet */
1760 le->opcode = OP_TCPLISW | HW_OWNER;
1761 }
1d179332 1762 }
cd28ab6a
SH		 1763 }
1764
6b84daca
SH		 1765 re = sky2->tx_ring + slot;
1766 re->flags = TX_MAP_SINGLE;
1767 pci_unmap_addr_set(re, mapaddr, mapping);
1768 pci_unmap_len_set(re, maplen, len);
1769
9b289c33 1770 le = get_tx_le(sky2, &slot);
d6e74b6b 1771 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1772 le->length = cpu_to_le16(len);
1773 le->ctrl = ctrl;
793b883e 1774 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1775
cd28ab6a
SH		 1776
1777 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1778 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1779
1780 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1781 frag->size, PCI_DMA_TODEVICE);
86c6887e 1782
454e6cb6
SH		 1783 if (pci_dma_mapping_error(hw->pdev, mapping))
1784 goto mapping_unwind;
1785
5dce95e5
SH		 1786 upper = upper_32_bits(mapping);
1787 if (upper != sky2->tx_last_upper) {
9b289c33 1788 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1789 le->addr = cpu_to_le32(upper);
1790 sky2->tx_last_upper = upper;
793b883e 1791 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1792 }
1793
6b84daca
SH		 1794 re = sky2->tx_ring + slot;
1795 re->flags = TX_MAP_PAGE;
1796 pci_unmap_addr_set(re, mapaddr, mapping);
1797 pci_unmap_len_set(re, maplen, frag->size);
1798
9b289c33 1799 le = get_tx_le(sky2, &slot);
d6e74b6b 1800 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1801 le->length = cpu_to_le16(frag->size);
1802 le->ctrl = ctrl;
793b883e 1803 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1804 }
6cdbbdf3 1805
6b84daca 1806 re->skb = skb;
cd28ab6a
SH		 1807 le->ctrl |= EOP;
1808
9b289c33
MM		 1809 sky2->tx_prod = slot;
1810
97bda706 1811 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1812 netif_stop_queue(dev);
b19666d9 1813
290d4de5 1814 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1815
cd28ab6a 1816 return NETDEV_TX_OK;
454e6cb6
SH		 1817
1818mapping_unwind:
ee5f68fe 1819 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
454e6cb6
SH		 1820 re = sky2->tx_ring + i;
1821
6b84daca 1822 sky2_tx_unmap(hw->pdev, re);
454e6cb6
SH		 1823 }
1824
454e6cb6
SH		 1825mapping_error:
1826 if (net_ratelimit())
1827 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1828 dev_kfree_skb(skb);
1829 return NETDEV_TX_OK;
cd28ab6a
SH		 1830}
1831
cd28ab6a 1832/*
793b883e
SH		 1833 * Free ring elements from starting at tx_cons until "done"
1834 *
481cea4a
SH		 1835 * NB:
1836 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1837 * buffers so make sure not to free skb to early.
481cea4a
SH		 1838 * 2. This may run in parallel start_xmit because the it only
1839 * looks at the tail of the queue of FIFO (tx_cons), not
1840 * the head (tx_prod)
cd28ab6a 1841 */
d11c13e7 1842static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1843{
d11c13e7 1844 struct net_device *dev = sky2->netdev;
291ea614 1845 unsigned idx;
cd28ab6a 1846
ee5f68fe 1847 BUG_ON(done >= sky2->tx_ring_size);
2224795d 1848
291ea614 1849 for (idx = sky2->tx_cons; idx != done;
ee5f68fe 1850 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
291ea614 1851 struct tx_ring_info *re = sky2->tx_ring + idx;
6b84daca 1852 struct sk_buff *skb = re->skb;
291ea614 1853
6b84daca 1854 sky2_tx_unmap(sky2->hw->pdev, re);
bd1c6869 1855
6b84daca 1856 if (skb) {
291ea614
SH		 1857 if (unlikely(netif_msg_tx_done(sky2)))
1858 printk(KERN_DEBUG "%s: tx done %u\n",
1859 dev->name, idx);
3cf26753 1860
7138a0f5 1861 dev->stats.tx_packets++;
bd1c6869
SH		 1862 dev->stats.tx_bytes += skb->len;
1863
f6815077 1864 re->skb = NULL;
724b6942 1865 dev_kfree_skb_any(skb);
2bf56fe2 1866
ee5f68fe 1867 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
cd28ab6a 1868 }
793b883e 1869 }
793b883e 1870
291ea614 1871 sky2->tx_cons = idx;
50432cb5
SH		 1872 smp_mb();
1873
9db2f1be
JP		 1874 /* Wake unless it's detached, and called e.g. from sky2_down() */
1875 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4 && netif_device_present(dev))
cd28ab6a 1876 netif_wake_queue(dev);
cd28ab6a
SH		 1877}
1878
264bb4fa 1879static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 1880{
a510996b
MM		 1881 /* Disable Force Sync bit and Enable Alloc bit */
1882 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1883 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1884
1885 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1886 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1887 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1888
1889 /* Reset the PCI FIFO of the async Tx queue */
1890 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1891 BMU_RST_SET | BMU_FIFO_RST);
1892
1893 /* Reset the Tx prefetch units */
1894 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1895 PREF_UNIT_RST_SET);
1896
1897 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1898 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1899}
1900
cd28ab6a
SH		 1901/* Network shutdown */
1902static int sky2_down(struct net_device *dev)
1903{
1904 struct sky2_port *sky2 = netdev_priv(dev);
1905 struct sky2_hw *hw = sky2->hw;
1906 unsigned port = sky2->port;
1907 u16 ctrl;
e07b1aa8 1908 u32 imask;
cd28ab6a 1909
1b537565
SH		 1910 /* Never really got started! */
1911 if (!sky2->tx_le)
1912 return 0;
1913
cd28ab6a
SH		 1914 if (netif_msg_ifdown(sky2))
1915 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1916
d104acaf
SH		 1917 /* Force flow control off */
1918 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1919
cd28ab6a
SH		 1920 /* Stop transmitter */
1921 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1922 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1923
1924 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1925 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1926
1927 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1928 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1929 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1930
1931 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1932
1933 /* Workaround shared GMAC reset */
8e95a202
JP		 1934 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1935 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1936 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1937
cd28ab6a 1938 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 1939
6c83504f
SH		 1940 /* Force any delayed status interrrupt and NAPI */
1941 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1942 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1943 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1944 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1945
a947a39d
MM		 1946 sky2_rx_stop(sky2);
1947
1948 /* Disable port IRQ */
1949 imask = sky2_read32(hw, B0_IMSK);
1950 imask &= ~portirq_msk[port];
1951 sky2_write32(hw, B0_IMSK, imask);
1952 sky2_read32(hw, B0_IMSK);
1953
6c83504f
SH		 1954 synchronize_irq(hw->pdev->irq);
1955 napi_synchronize(&hw->napi);
1956
0da6d7b3 1957 spin_lock_bh(&sky2->phy_lock);
b96936da 1958 sky2_phy_power_down(hw, port);
0da6d7b3 1959 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 1960
264bb4fa
MM		 1961 sky2_tx_reset(hw, port);
1962
481cea4a
SH		 1963 /* Free any pending frames stuck in HW queue */
1964 sky2_tx_complete(sky2, sky2->tx_prod);
1965
cd28ab6a
SH		 1966 sky2_rx_clean(sky2);
1967
90bbebb4 1968 sky2_free_buffers(sky2);
1b537565 1969
cd28ab6a
SH		 1970 return 0;
1971}
1972
1973static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1974{
ea76e635 1975 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1976 return SPEED_1000;
1977
05745c4a
SH		 1978 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1979 if (aux & PHY_M_PS_SPEED_100)
1980 return SPEED_100;
1981 else
1982 return SPEED_10;
1983 }
cd28ab6a
SH		 1984
1985 switch (aux & PHY_M_PS_SPEED_MSK) {
1986 case PHY_M_PS_SPEED_1000:
1987 return SPEED_1000;
1988 case PHY_M_PS_SPEED_100:
1989 return SPEED_100;
1990 default:
1991 return SPEED_10;
1992 }
1993}
1994
1995static void sky2_link_up(struct sky2_port *sky2)
1996{
1997 struct sky2_hw *hw = sky2->hw;
1998 unsigned port = sky2->port;
1999 u16 reg;
16ad91e1
SH		 2000 static const char *fc_name[] = {
2001 [FC_NONE] = "none",
2002 [FC_TX] = "tx",
2003 [FC_RX] = "rx",
2004 [FC_BOTH] = "both",
2005 };
cd28ab6a 2006
cd28ab6a 2007 /* enable Rx/Tx */
2eaba1a2 2008 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 2009 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2010 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 2011
2012 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2013
2014 netif_carrier_on(sky2->netdev);
cd28ab6a 2015
75e80683 2016 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 2017
cd28ab6a 2018 /* Turn on link LED */
793b883e 2019 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 2020 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2021
2022 if (netif_msg_link(sky2))
2023 printk(KERN_INFO PFX
d571b694 2024 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 2025 sky2->netdev->name, sky2->speed,
2026 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 2027 fc_name[sky2->flow_status]);
cd28ab6a
SH		 2028}
2029
2030static void sky2_link_down(struct sky2_port *sky2)
2031{
2032 struct sky2_hw *hw = sky2->hw;
2033 unsigned port = sky2->port;
2034 u16 reg;
2035
2036 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2037
2038 reg = gma_read16(hw, port, GM_GP_CTRL);
2039 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2040 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 2041
cd28ab6a 2042 netif_carrier_off(sky2->netdev);
cd28ab6a 2043
809aaaae 2044 /* Turn off link LED */
cd28ab6a
SH		 2045 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2046
2047 if (netif_msg_link(sky2))
2048 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 2049
cd28ab6a
SH		 2050 sky2_phy_init(hw, port);
2051}
2052
16ad91e1
SH		 2053static enum flow_control sky2_flow(int rx, int tx)
2054{
2055 if (rx)
2056 return tx ? FC_BOTH : FC_RX;
2057 else
2058 return tx ? FC_TX : FC_NONE;
2059}
2060
793b883e
SH		 2061static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2062{
2063 struct sky2_hw *hw = sky2->hw;
2064 unsigned port = sky2->port;
da4c1ff4 2065 u16 advert, lpa;
793b883e 2066
da4c1ff4 2067 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2068 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 2069 if (lpa & PHY_M_AN_RF) {
2070 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2071 return -1;
2072 }
2073
793b883e
SH		 2074 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2075 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2076 sky2->netdev->name);
2077 return -1;
2078 }
2079
793b883e 2080 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2081 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2082
da4c1ff4
SH		 2083 /* Since the pause result bits seem to in different positions on
2084 * different chips. look at registers.
2085 */
ea76e635 2086 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2087 /* Shift for bits in fiber PHY */
2088 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2089 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2090
2091 if (advert & ADVERTISE_1000XPAUSE)
2092 advert |= ADVERTISE_PAUSE_CAP;
2093 if (advert & ADVERTISE_1000XPSE_ASYM)
2094 advert |= ADVERTISE_PAUSE_ASYM;
2095 if (lpa & LPA_1000XPAUSE)
2096 lpa |= LPA_PAUSE_CAP;
2097 if (lpa & LPA_1000XPAUSE_ASYM)
2098 lpa |= LPA_PAUSE_ASYM;
2099 }
793b883e 2100
da4c1ff4
SH		 2101 sky2->flow_status = FC_NONE;
2102 if (advert & ADVERTISE_PAUSE_CAP) {
2103 if (lpa & LPA_PAUSE_CAP)
2104 sky2->flow_status = FC_BOTH;
2105 else if (advert & ADVERTISE_PAUSE_ASYM)
2106 sky2->flow_status = FC_RX;
2107 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2108 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2109 sky2->flow_status = FC_TX;
2110 }
793b883e 2111
8e95a202
JP		 2112 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2113 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2114 sky2->flow_status = FC_NONE;
2eaba1a2 2115
da4c1ff4 2116 if (sky2->flow_status & FC_TX)
793b883e
SH		 2117 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2118 else
2119 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2120
2121 return 0;
2122}
cd28ab6a 2123
e07b1aa8
SH		 2124/* Interrupt from PHY */
2125static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2126{
e07b1aa8
SH		 2127 struct net_device *dev = hw->dev[port];
2128 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2129 u16 istatus, phystat;
2130
ebc646f6
SH		 2131 if (!netif_running(dev))
2132 return;
2133
e07b1aa8
SH		 2134 spin_lock(&sky2->phy_lock);
2135 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2136 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2137
cd28ab6a
SH		 2138 if (netif_msg_intr(sky2))
2139 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2140 sky2->netdev->name, istatus, phystat);
2141
0ea065e5 2142 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 2143 if (sky2_autoneg_done(sky2, phystat) == 0)
2144 sky2_link_up(sky2);
2145 goto out;
2146 }
cd28ab6a 2147
793b883e
SH		 2148 if (istatus & PHY_M_IS_LSP_CHANGE)
2149 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2150
793b883e
SH		 2151 if (istatus & PHY_M_IS_DUP_CHANGE)
2152 sky2->duplex =
2153 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2154
793b883e
SH		 2155 if (istatus & PHY_M_IS_LST_CHANGE) {
2156 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2157 sky2_link_up(sky2);
793b883e
SH		 2158 else
2159 sky2_link_down(sky2);
cd28ab6a 2160 }
793b883e 2161out:
e07b1aa8 2162 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2163}
2164
0f5aac70
SH		 2165/* Special quick link interrupt (Yukon-2 Optima only) */
2166static void sky2_qlink_intr(struct sky2_hw *hw)
2167{
2168 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2169 u32 imask;
2170 u16 phy;
2171
2172 /* disable irq */
2173 imask = sky2_read32(hw, B0_IMSK);
2174 imask &= ~Y2_IS_PHY_QLNK;
2175 sky2_write32(hw, B0_IMSK, imask);
2176
2177 /* reset PHY Link Detect */
2178 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
a40ccc68 2179 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70 2180 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
a40ccc68 2181 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 2182
2183 sky2_link_up(sky2);
2184}
2185
62335ab0 2186/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2187 * and tx queue is full (stopped).
2188 */
cd28ab6a
SH		 2189static void sky2_tx_timeout(struct net_device *dev)
2190{
2191 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2192 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2193
2194 if (netif_msg_timer(sky2))
2195 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2196
8f24664d 2197 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2198 dev->name, sky2->tx_cons, sky2->tx_prod,
2199 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2200 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2201
81906791
SH		 2202 /* can't restart safely under softirq */
2203 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2204}
2205
2206static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2207{
6b1a3aef 2208 struct sky2_port *sky2 = netdev_priv(dev);
2209 struct sky2_hw *hw = sky2->hw;
b628ed98 2210 unsigned port = sky2->port;
6b1a3aef 2211 int err;
2212 u16 ctl, mode;
e07b1aa8 2213 u32 imask;
cd28ab6a
SH		 2214
2215 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2216 return -EINVAL;
2217
05745c4a
SH		 2218 if (new_mtu > ETH_DATA_LEN &&
2219 (hw->chip_id == CHIP_ID_YUKON_FE ||
2220 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2221 return -EINVAL;
2222
6b1a3aef 2223 if (!netif_running(dev)) {
2224 dev->mtu = new_mtu;
2225 return 0;
2226 }
2227
e07b1aa8 2228 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 2229 sky2_write32(hw, B0_IMSK, 0);
2230
018d1c66 2231 dev->trans_start = jiffies; /* prevent tx timeout */
2232 netif_stop_queue(dev);
bea3348e 2233 napi_disable(&hw->napi);
018d1c66 2234
e07b1aa8
SH		 2235 synchronize_irq(hw->pdev->irq);
2236
39dbd958 2237 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2238 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2239
2240 ctl = gma_read16(hw, port, GM_GP_CTRL);
2241 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 2242 sky2_rx_stop(sky2);
2243 sky2_rx_clean(sky2);
cd28ab6a
SH		 2244
2245 dev->mtu = new_mtu;
14d0263f 2246
6b1a3aef 2247 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2248 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2249
2250 if (dev->mtu > ETH_DATA_LEN)
2251 mode |= GM_SMOD_JUMBO_ENA;
2252
b628ed98 2253 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2254
b628ed98 2255 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2256
6b1a3aef 2257 err = sky2_rx_start(sky2);
e07b1aa8 2258 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2259
d1d08d12 2260 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2261 napi_enable(&hw->napi);
2262
1b537565
SH		 2263 if (err)
2264 dev_close(dev);
2265 else {
b628ed98 2266 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2267
1b537565
SH		 2268 netif_wake_queue(dev);
2269 }
2270
cd28ab6a
SH		 2271 return err;
2272}
2273
14d0263f
SH		 2274/* For small just reuse existing skb for next receive */
2275static struct sk_buff *receive_copy(struct sky2_port *sky2,
2276 const struct rx_ring_info *re,
2277 unsigned length)
2278{
2279 struct sk_buff *skb;
2280
89d71a66 2281 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
14d0263f 2282 if (likely(skb)) {
14d0263f
SH		 2283 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2284 length, PCI_DMA_FROMDEVICE);
d626f62b 2285 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2286 skb->ip_summed = re->skb->ip_summed;
2287 skb->csum = re->skb->csum;
2288 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2289 length, PCI_DMA_FROMDEVICE);
2290 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2291 skb_put(skb, length);
14d0263f
SH		 2292 }
2293 return skb;
2294}
2295
2296/* Adjust length of skb with fragments to match received data */
2297static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2298 unsigned int length)
2299{
2300 int i, num_frags;
2301 unsigned int size;
2302
2303 /* put header into skb */
2304 size = min(length, hdr_space);
2305 skb->tail += size;
2306 skb->len += size;
2307 length -= size;
2308
2309 num_frags = skb_shinfo(skb)->nr_frags;
2310 for (i = 0; i < num_frags; i++) {
2311 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2312
2313 if (length == 0) {
2314 /* don't need this page */
2315 __free_page(frag->page);
2316 --skb_shinfo(skb)->nr_frags;
2317 } else {
2318 size = min(length, (unsigned) PAGE_SIZE);
2319
2320 frag->size = size;
2321 skb->data_len += size;
2322 skb->truesize += size;
2323 skb->len += size;
2324 length -= size;
2325 }
2326 }
2327}
2328
2329/* Normal packet - take skb from ring element and put in a new one */
2330static struct sk_buff *receive_new(struct sky2_port *sky2,
2331 struct rx_ring_info *re,
2332 unsigned int length)
2333{
3fbd9187 2334 struct sk_buff *skb;
2335 struct rx_ring_info nre;
14d0263f
SH		 2336 unsigned hdr_space = sky2->rx_data_size;
2337
3fbd9187 2338 nre.skb = sky2_rx_alloc(sky2);
2339 if (unlikely(!nre.skb))
2340 goto nobuf;
2341
2342 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2343 goto nomap;
14d0263f
SH		 2344
2345 skb = re->skb;
2346 sky2_rx_unmap_skb(sky2->hw->pdev, re);
14d0263f 2347 prefetch(skb->data);
3fbd9187 2348 *re = nre;
14d0263f
SH		 2349
2350 if (skb_shinfo(skb)->nr_frags)
2351 skb_put_frags(skb, hdr_space, length);
2352 else
489b10c1 2353 skb_put(skb, length);
14d0263f 2354 return skb;
3fbd9187 2355
2356nomap:
2357 dev_kfree_skb(nre.skb);
2358nobuf:
2359 return NULL;
14d0263f
SH		 2360}
2361
cd28ab6a
SH		 2362/*
2363 * Receive one packet.
d571b694 2364 * For larger packets, get new buffer.
cd28ab6a 2365 */
497d7c86 2366static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2367 u16 length, u32 status)
2368{
497d7c86 2369 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2370 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2371 struct sk_buff *skb = NULL;
d6532232
SH		 2372 u16 count = (status & GMR_FS_LEN) >> 16;
2373
2374#ifdef SKY2_VLAN_TAG_USED
2375 /* Account for vlan tag */
2376 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2377 count -= VLAN_HLEN;
2378#endif
cd28ab6a
SH		 2379
2380 if (unlikely(netif_msg_rx_status(sky2)))
2381 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2382 dev->name, sky2->rx_next, status, length);
cd28ab6a 2383
793b883e 2384 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2385 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2386
3b12e014
SH		 2387 /* This chip has hardware problems that generates bogus status.
2388 * So do only marginal checking and expect higher level protocols
2389 * to handle crap frames.
2390 */
2391 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2392 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2393 length != count)
2394 goto okay;
2395
42eeea01 2396 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2397 goto error;
2398
42eeea01 2399 if (!(status & GMR_FS_RX_OK))
2400 goto resubmit;
2401
d6532232
SH		 2402 /* if length reported by DMA does not match PHY, packet was truncated */
2403 if (length != count)
3b12e014 2404 goto len_error;
71749531 2405
3b12e014 2406okay:
14d0263f
SH		 2407 if (length < copybreak)
2408 skb = receive_copy(sky2, re, length);
2409 else
2410 skb = receive_new(sky2, re, length);
90c30335
SH		 2411
2412 dev->stats.rx_dropped += (skb == NULL);
2413
793b883e 2414resubmit:
14d0263f 2415 sky2_rx_submit(sky2, re);
79e57d32 2416
cd28ab6a
SH		 2417 return skb;
2418
3b12e014 2419len_error:
71749531
SH		 2420 /* Truncation of overlength packets
2421 causes PHY length to not match MAC length */
7138a0f5 2422 ++dev->stats.rx_length_errors;
d6532232 2423 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2424 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2425 dev->name, status, length);
d6532232 2426 goto resubmit;
71749531 2427
cd28ab6a 2428error:
7138a0f5 2429 ++dev->stats.rx_errors;
b6d77734 2430 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2431 dev->stats.rx_over_errors++;
b6d77734
SH		 2432 goto resubmit;
2433 }
6e15b712 2434
3be92a70 2435 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2436 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2437 dev->name, status, length);
793b883e
SH		 2438
2439 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2440 dev->stats.rx_length_errors++;
cd28ab6a 2441 if (status & GMR_FS_FRAGMENT)
7138a0f5 2442 dev->stats.rx_frame_errors++;
cd28ab6a 2443 if (status & GMR_FS_CRC_ERR)
7138a0f5 2444 dev->stats.rx_crc_errors++;
79e57d32 2445
793b883e 2446 goto resubmit;
cd28ab6a
SH		 2447}
2448
e07b1aa8
SH		 2449/* Transmit complete */
2450static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2451{
e07b1aa8 2452 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2453
49d4b8ba 2454 if (netif_running(dev))
e07b1aa8 2455 sky2_tx_complete(sky2, last);
cd28ab6a
SH		 2456}
2457
37e5a243
SH		 2458static inline void sky2_skb_rx(const struct sky2_port *sky2,
2459 u32 status, struct sk_buff *skb)
2460{
2461#ifdef SKY2_VLAN_TAG_USED
2462 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2463 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2464 if (skb->ip_summed == CHECKSUM_NONE)
2465 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2466 else
2467 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2468 vlan_tag, skb);
2469 return;
2470 }
2471#endif
2472 if (skb->ip_summed == CHECKSUM_NONE)
2473 netif_receive_skb(skb);
2474 else
2475 napi_gro_receive(&sky2->hw->napi, skb);
2476}
2477
bf15fe99
SH		 2478static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2479 unsigned packets, unsigned bytes)
2480{
2481 if (packets) {
2482 struct net_device *dev = hw->dev[port];
2483
2484 dev->stats.rx_packets += packets;
2485 dev->stats.rx_bytes += bytes;
2486 dev->last_rx = jiffies;
2487 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2488 }
2489}
2490
375c5688 2491static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2492{
2493 /* If this happens then driver assuming wrong format for chip type */
2494 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2495
2496 /* Both checksum counters are programmed to start at
2497 * the same offset, so unless there is a problem they
2498 * should match. This failure is an early indication that
2499 * hardware receive checksumming won't work.
2500 */
2501 if (likely((u16)(status >> 16) == (u16)status)) {
2502 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2503 skb->ip_summed = CHECKSUM_COMPLETE;
2504 skb->csum = le16_to_cpu(status);
2505 } else {
2506 dev_notice(&sky2->hw->pdev->dev,
2507 "%s: receive checksum problem (status = %#x)\n",
2508 sky2->netdev->name, status);
2509
2510 /* Disable checksum offload */
2511 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2512 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2513 BMU_DIS_RX_CHKSUM);
2514 }
2515}
2516
e07b1aa8 2517/* Process status response ring */
26691830 2518static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2519{
e07b1aa8 2520 int work_done = 0;
bf15fe99
SH		 2521 unsigned int total_bytes[2] = { 0 };
2522 unsigned int total_packets[2] = { 0 };
a8fd6266 2523
af2a58ac 2524 rmb();
26691830 2525 do {
55c9dd35 2526 struct sky2_port *sky2;
13210ce5 2527 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2528 unsigned port;
13210ce5 2529 struct net_device *dev;
cd28ab6a 2530 struct sk_buff *skb;
cd28ab6a
SH		 2531 u32 status;
2532 u16 length;
ab5adecb
SH		 2533 u8 opcode = le->opcode;
2534
2535 if (!(opcode & HW_OWNER))
2536 break;
cd28ab6a 2537
cb5d9547 2538 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2539
ab5adecb 2540 port = le->css & CSS_LINK_BIT;
69161611 2541 dev = hw->dev[port];
13210ce5 2542 sky2 = netdev_priv(dev);
f65b138c
SH		 2543 length = le16_to_cpu(le->length);
2544 status = le32_to_cpu(le->status);
cd28ab6a 2545
ab5adecb
SH		 2546 le->opcode = 0;
2547 switch (opcode & ~HW_OWNER) {
cd28ab6a 2548 case OP_RXSTAT:
bf15fe99
SH		 2549 total_packets[port]++;
2550 total_bytes[port] += length;
90c30335 2551
497d7c86 2552 skb = sky2_receive(dev, length, status);
90c30335 2553 if (!skb)
55c9dd35 2554 break;
13210ce5 2555
69161611 2556 /* This chip reports checksum status differently */
05745c4a 2557 if (hw->flags & SKY2_HW_NEW_LE) {
0ea065e5 2558 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
69161611
SH		 2559 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2560 (le->css & CSS_TCPUDPCSOK))
2561 skb->ip_summed = CHECKSUM_UNNECESSARY;
2562 else
2563 skb->ip_summed = CHECKSUM_NONE;
2564 }
2565
13210ce5 2566 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2567
37e5a243 2568 sky2_skb_rx(sky2, status, skb);
13210ce5 2569
22e11703 2570 /* Stop after net poll weight */
13210ce5 2571 if (++work_done >= to_do)
2572 goto exit_loop;
cd28ab6a
SH		 2573 break;
2574
d1f13708 2575#ifdef SKY2_VLAN_TAG_USED
2576 case OP_RXVLAN:
2577 sky2->rx_tag = length;
2578 break;
2579
2580 case OP_RXCHKSVLAN:
2581 sky2->rx_tag = length;
2582 /* fall through */
2583#endif
cd28ab6a 2584 case OP_RXCHKS:
375c5688 2585 if (likely(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2586 sky2_rx_checksum(sky2, status);
cd28ab6a
SH		 2587 break;
2588
2589 case OP_TXINDEXLE:
13b97b74 2590 /* TX index reports status for both ports */
f55925d7 2591 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2592 if (hw->dev[1])
2593 sky2_tx_done(hw->dev[1],
2594 ((status >> 24) & 0xff)
2595 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2596 break;
2597
cd28ab6a
SH		 2598 default:
2599 if (net_ratelimit())
793b883e 2600 printk(KERN_WARNING PFX
ab5adecb 2601 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2602 }
26691830 2603 } while (hw->st_idx != idx);
cd28ab6a 2604
fe2a24df
SH		 2605 /* Fully processed status ring so clear irq */
2606 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2607
13210ce5 2608exit_loop:
bf15fe99
SH		 2609 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2610 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2611
e07b1aa8 2612 return work_done;
cd28ab6a
SH		 2613}
2614
2615static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2616{
2617 struct net_device *dev = hw->dev[port];
2618
3be92a70
SH		 2619 if (net_ratelimit())
2620 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2621 dev->name, status);
cd28ab6a
SH		 2622
2623 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2624 if (net_ratelimit())
2625 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2626 dev->name);
cd28ab6a
SH		 2627 /* Clear IRQ */
2628 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2629 }
2630
2631 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2632 if (net_ratelimit())
2633 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2634 dev->name);
cd28ab6a
SH		 2635
2636 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2637 }
2638
2639 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2640 if (net_ratelimit())
2641 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2642 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2643 }
2644
2645 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2646 if (net_ratelimit())
2647 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2648 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2649 }
2650
2651 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2652 if (net_ratelimit())
2653 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2654 dev->name);
cd28ab6a
SH		 2655 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2656 }
2657}
2658
2659static void sky2_hw_intr(struct sky2_hw *hw)
2660{
555382cb 2661 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2662 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2663 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2664
2665 status &= hwmsk;
cd28ab6a 2666
793b883e 2667 if (status & Y2_IS_TIST_OV)
cd28ab6a 2668 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2669
2670 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2671 u16 pci_err;
2672
a40ccc68 2673 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2674 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2675 if (net_ratelimit())
555382cb 2676 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2677 pci_err);
cd28ab6a 2678
b32f40c4 2679 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2680 pci_err | PCI_STATUS_ERROR_BITS);
a40ccc68 2681 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2682 }
2683
2684 if (status & Y2_IS_PCI_EXP) {
d571b694 2685 /* PCI-Express uncorrectable Error occurred */
555382cb 2686 u32 err;
cd28ab6a 2687
a40ccc68 2688 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2689 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2690 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2691 0xfffffffful);
3be92a70 2692 if (net_ratelimit())
555382cb 2693 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2694
7782c8c4 2695 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
a40ccc68 2696 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2697 }
2698
2699 if (status & Y2_HWE_L1_MASK)
2700 sky2_hw_error(hw, 0, status);
2701 status >>= 8;
2702 if (status & Y2_HWE_L1_MASK)
2703 sky2_hw_error(hw, 1, status);
2704}
2705
2706static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2707{
2708 struct net_device *dev = hw->dev[port];
2709 struct sky2_port *sky2 = netdev_priv(dev);
2710 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2711
2712 if (netif_msg_intr(sky2))
2713 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2714 dev->name, status);
2715
a3caeada
SH		 2716 if (status & GM_IS_RX_CO_OV)
2717 gma_read16(hw, port, GM_RX_IRQ_SRC);
2718
2719 if (status & GM_IS_TX_CO_OV)
2720 gma_read16(hw, port, GM_TX_IRQ_SRC);
2721
cd28ab6a 2722 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2723 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2724 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2725 }
2726
2727 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2728 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2729 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2730 }
cd28ab6a
SH		 2731}
2732
40b01727 2733/* This should never happen it is a bug. */
c119731d 2734static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH		 2735{
2736 struct net_device *dev = hw->dev[port];
c119731d 2737 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2738
c119731d
SH		 2739 dev_err(&hw->pdev->dev, PFX
2740 "%s: descriptor error q=%#x get=%u put=%u\n",
2741 dev->name, (unsigned) q, (unsigned) idx,
2742 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2743
40b01727 2744 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2745}
cd28ab6a 2746
75e80683
SH		 2747static int sky2_rx_hung(struct net_device *dev)
2748{
2749 struct sky2_port *sky2 = netdev_priv(dev);
2750 struct sky2_hw *hw = sky2->hw;
2751 unsigned port = sky2->port;
2752 unsigned rxq = rxqaddr[port];
2753 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2754 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2755 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2756 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2757
2758 /* If idle and MAC or PCI is stuck */
2759 if (sky2->check.last == dev->last_rx &&
2760 ((mac_rp == sky2->check.mac_rp &&
2761 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2762 /* Check if the PCI RX hang */
2763 (fifo_rp == sky2->check.fifo_rp &&
2764 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2765 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2766 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2767 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2768 return 1;
2769 } else {
2770 sky2->check.last = dev->last_rx;
2771 sky2->check.mac_rp = mac_rp;
2772 sky2->check.mac_lev = mac_lev;
2773 sky2->check.fifo_rp = fifo_rp;
2774 sky2->check.fifo_lev = fifo_lev;
2775 return 0;
2776 }
2777}
2778
32c2c300 2779static void sky2_watchdog(unsigned long arg)
d27ed387 2780{
01bd7564 2781 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2782
75e80683 2783 /* Check for lost IRQ once a second */
32c2c300 2784 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2785 napi_schedule(&hw->napi);
75e80683
SH		 2786 } else {
2787 int i, active = 0;
2788
2789 for (i = 0; i < hw->ports; i++) {
bea3348e 2790 struct net_device *dev = hw->dev[i];
75e80683
SH		 2791 if (!netif_running(dev))
2792 continue;
2793 ++active;
2794
2795 /* For chips with Rx FIFO, check if stuck */
39dbd958 2796 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2797 sky2_rx_hung(dev)) {
2798 pr_info(PFX "%s: receiver hang detected\n",
2799 dev->name);
2800 schedule_work(&hw->restart_work);
2801 return;
2802 }
2803 }
2804
2805 if (active == 0)
2806 return;
32c2c300 2807 }
01bd7564 2808
75e80683 2809 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2810}
2811
40b01727
SH		 2812/* Hardware/software error handling */
2813static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2814{
40b01727
SH		 2815 if (net_ratelimit())
2816 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2817
1e5f1283
SH		 2818 if (status & Y2_IS_HW_ERR)
2819 sky2_hw_intr(hw);
d257924e 2820
1e5f1283
SH		 2821 if (status & Y2_IS_IRQ_MAC1)
2822 sky2_mac_intr(hw, 0);
cd28ab6a 2823
1e5f1283
SH		 2824 if (status & Y2_IS_IRQ_MAC2)
2825 sky2_mac_intr(hw, 1);
cd28ab6a 2826
1e5f1283 2827 if (status & Y2_IS_CHK_RX1)
c119731d 2828 sky2_le_error(hw, 0, Q_R1);
d257924e 2829
1e5f1283 2830 if (status & Y2_IS_CHK_RX2)
c119731d 2831 sky2_le_error(hw, 1, Q_R2);
d257924e 2832
1e5f1283 2833 if (status & Y2_IS_CHK_TXA1)
c119731d 2834 sky2_le_error(hw, 0, Q_XA1);
d257924e 2835
1e5f1283 2836 if (status & Y2_IS_CHK_TXA2)
c119731d 2837 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH		 2838}
2839
bea3348e 2840static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2841{
bea3348e 2842 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2843 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2844 int work_done = 0;
26691830 2845 u16 idx;
40b01727
SH		 2846
2847 if (unlikely(status & Y2_IS_ERROR))
2848 sky2_err_intr(hw, status);
2849
2850 if (status & Y2_IS_IRQ_PHY1)
2851 sky2_phy_intr(hw, 0);
2852
2853 if (status & Y2_IS_IRQ_PHY2)
2854 sky2_phy_intr(hw, 1);
cd28ab6a 2855
0f5aac70
SH		 2856 if (status & Y2_IS_PHY_QLNK)
2857 sky2_qlink_intr(hw);
2858
26691830
SH		 2859 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2860 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2861
2862 if (work_done >= work_limit)
26691830
SH		 2863 goto done;
2864 }
6f535763 2865
26691830
SH		 2866 napi_complete(napi);
2867 sky2_read32(hw, B0_Y2_SP_LISR);
2868done:
6f535763 2869
bea3348e 2870 return work_done;
e07b1aa8
SH		 2871}
2872
7d12e780 2873static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2874{
2875 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2876 u32 status;
2877
2878 /* Reading this mask interrupts as side effect */
2879 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2880 if (status == 0 || status == ~0)
2881 return IRQ_NONE;
793b883e 2882
e07b1aa8 2883 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2884
2885 napi_schedule(&hw->napi);
793b883e 2886
cd28ab6a
SH		 2887 return IRQ_HANDLED;
2888}
2889
2890#ifdef CONFIG_NET_POLL_CONTROLLER
2891static void sky2_netpoll(struct net_device *dev)
2892{
2893 struct sky2_port *sky2 = netdev_priv(dev);
2894
bea3348e 2895 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2896}
2897#endif
2898
2899/* Chip internal frequency for clock calculations */
05745c4a 2900static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2901{
793b883e 2902 switch (hw->chip_id) {
cd28ab6a 2903 case CHIP_ID_YUKON_EC:
5a5b1ea0 2904 case CHIP_ID_YUKON_EC_U:
93745494 2905 case CHIP_ID_YUKON_EX:
ed4d4161 2906 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2907 case CHIP_ID_YUKON_UL_2:
0f5aac70 2908 case CHIP_ID_YUKON_OPT:
05745c4a
SH		 2909 return 125;
2910
cd28ab6a 2911 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2912 return 100;
2913
2914 case CHIP_ID_YUKON_FE_P:
2915 return 50;
2916
2917 case CHIP_ID_YUKON_XL:
2918 return 156;
2919
2920 default:
2921 BUG();
cd28ab6a
SH		 2922 }
2923}
2924
fb17358f 2925static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2926{
fb17358f 2927 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2928}
2929
fb17358f 2930static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2931{
fb17358f 2932 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2933}
2934
fb17358f 2935
e3173832 2936static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2937{
b89165f2 2938 u8 t8;
cd28ab6a 2939
167f53d0 2940 /* Enable all clocks and check for bad PCI access */
b32f40c4 2941 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2942
cd28ab6a 2943 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2944
cd28ab6a 2945 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2946 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2947
2948 switch(hw->chip_id) {
2949 case CHIP_ID_YUKON_XL:
39dbd958 2950 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2951 break;
2952
2953 case CHIP_ID_YUKON_EC_U:
2954 hw->flags = SKY2_HW_GIGABIT
2955 | SKY2_HW_NEWER_PHY
2956 | SKY2_HW_ADV_POWER_CTL;
2957 break;
2958
2959 case CHIP_ID_YUKON_EX:
2960 hw->flags = SKY2_HW_GIGABIT
2961 | SKY2_HW_NEWER_PHY
2962 | SKY2_HW_NEW_LE
2963 | SKY2_HW_ADV_POWER_CTL;
2964
2965 /* New transmit checksum */
2966 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2967 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2968 break;
2969
2970 case CHIP_ID_YUKON_EC:
2971 /* This rev is really old, and requires untested workarounds */
2972 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2973 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2974 return -EOPNOTSUPP;
2975 }
39dbd958 2976 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2977 break;
2978
2979 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2980 break;
2981
05745c4a
SH		 2982 case CHIP_ID_YUKON_FE_P:
2983 hw->flags = SKY2_HW_NEWER_PHY
2984 | SKY2_HW_NEW_LE
2985 | SKY2_HW_AUTO_TX_SUM
2986 | SKY2_HW_ADV_POWER_CTL;
2987 break;
ed4d4161
SH		 2988
2989 case CHIP_ID_YUKON_SUPR:
2990 hw->flags = SKY2_HW_GIGABIT
2991 | SKY2_HW_NEWER_PHY
2992 | SKY2_HW_NEW_LE
2993 | SKY2_HW_AUTO_TX_SUM
2994 | SKY2_HW_ADV_POWER_CTL;
2995 break;
2996
0ce8b98d 2997 case CHIP_ID_YUKON_UL_2:
b338682d
TI		 2998 hw->flags = SKY2_HW_GIGABIT
2999 | SKY2_HW_ADV_POWER_CTL;
3000 break;
3001
0f5aac70 3002 case CHIP_ID_YUKON_OPT:
0ce8b98d 3003 hw->flags = SKY2_HW_GIGABIT
b338682d 3004 | SKY2_HW_NEW_LE
0ce8b98d
SH		 3005 | SKY2_HW_ADV_POWER_CTL;
3006 break;
3007
ea76e635 3008 default:
b02a9258
SH		 3009 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3010 hw->chip_id);
cd28ab6a
SH		 3011 return -EOPNOTSUPP;
3012 }
3013
ea76e635
SH		 3014 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3015 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3016 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 3017
e3173832
SH		 3018 hw->ports = 1;
3019 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3020 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3021 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3022 ++hw->ports;
3023 }
3024
74a61ebf
MM		 3025 if (sky2_read8(hw, B2_E_0))
3026 hw->flags |= SKY2_HW_RAM_BUFFER;
3027
e3173832
SH		 3028 return 0;
3029}
3030
3031static void sky2_reset(struct sky2_hw *hw)
3032{
555382cb 3033 struct pci_dev *pdev = hw->pdev;
e3173832 3034 u16 status;
555382cb
SH		 3035 int i, cap;
3036 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 3037
cd28ab6a 3038 /* disable ASF */
acd12dde 3039 if (hw->chip_id == CHIP_ID_YUKON_EX
3040 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3041 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3042 status = sky2_read16(hw, HCU_CCSR);
3043 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3044 HCU_CCSR_UC_STATE_MSK);
acd12dde 3045 /*
3046 * CPU clock divider shouldn't be used because
3047 * - ASF firmware may malfunction
3048 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3049 */
3050 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
4f44d8ba 3051 sky2_write16(hw, HCU_CCSR, status);
acd12dde 3052 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3053 } else
3054 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3055 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 3056
3057 /* do a SW reset */
3058 sky2_write8(hw, B0_CTST, CS_RST_SET);
3059 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3060
ac93a394
SH		 3061 /* allow writes to PCI config */
3062 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3063
cd28ab6a 3064 /* clear PCI errors, if any */
b32f40c4 3065 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 3066 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 3067 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 3068
3069 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3070
555382cb
SH		 3071 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3072 if (cap) {
7782c8c4
SH		 3073 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3074 0xfffffffful);
555382cb
SH		 3075
3076 /* If error bit is stuck on ignore it */
3077 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3078 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 3079 else
555382cb
SH		 3080 hwe_mask |= Y2_IS_PCI_EXP;
3081 }
cd28ab6a 3082
ae306cca 3083 sky2_power_on(hw);
a40ccc68 3084 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 3085
3086 for (i = 0; i < hw->ports; i++) {
3087 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3088 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 3089
ed4d4161
SH		 3090 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3091 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 3092 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3093 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3094 | GMC_BYP_RETR_ON);
877c8570
SH		 3095
3096 }
3097
3098 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3099 /* enable MACSec clock gating */
3100 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
cd28ab6a
SH		 3101 }
3102
0f5aac70
SH		 3103 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3104 u16 reg;
3105 u32 msk;
3106
3107 if (hw->chip_rev == 0) {
3108 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3109 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3110
3111 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3112 reg = 10;
3113 } else {
3114 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3115 reg = 3;
3116 }
3117
3118 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3119
3120 /* reset PHY Link Detect */
a40ccc68 3121 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70
SH		 3122 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3123 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3124 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3125
3126
3127 /* enable PHY Quick Link */
3128 msk = sky2_read32(hw, B0_IMSK);
3129 msk |= Y2_IS_PHY_QLNK;
3130 sky2_write32(hw, B0_IMSK, msk);
3131
3132 /* check if PSMv2 was running before */
3133 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3134 if (reg & PCI_EXP_LNKCTL_ASPMC) {
8b055431 3135 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
0f5aac70
SH		 3136 /* restore the PCIe Link Control register */
3137 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3138 }
a40ccc68 3139 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 3140
3141 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3142 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3143 }
3144
793b883e
SH		 3145 /* Clear I2C IRQ noise */
3146 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 3147
3148 /* turn off hardware timer (unused) */
3149 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3150 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3151
69634ee7
SH		 3152 /* Turn off descriptor polling */
3153 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3154
3155 /* Turn off receive timestamp */
3156 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3157 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3158
3159 /* enable the Tx Arbiters */
3160 for (i = 0; i < hw->ports; i++)
3161 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3162
3163 /* Initialize ram interface */
3164 for (i = 0; i < hw->ports; i++) {
793b883e 3165 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3166
3167 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3168 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3169 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3170 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3171 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3172 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3173 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3174 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3175 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3176 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3177 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3178 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3179 }
3180
555382cb 3181 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3182
cd28ab6a 3183 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3184 sky2_gmac_reset(hw, i);
cd28ab6a 3185
cd28ab6a
SH		 3186 memset(hw->st_le, 0, STATUS_LE_BYTES);
3187 hw->st_idx = 0;
3188
3189 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3190 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3191
3192 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3193 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3194
3195 /* Set the list last index */
793b883e 3196 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3197
290d4de5
SH		 3198 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3199 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3200
290d4de5
SH		 3201 /* set Status-FIFO ISR watermark */
3202 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3203 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3204 else
3205 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3206
290d4de5 3207 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3208 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3209 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3210
793b883e 3211 /* enable status unit */
cd28ab6a
SH		 3212 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3213
3214 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3215 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3216 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3217}
3218
af18d8b8
SH		 3219/* Take device down (offline).
3220 * Equivalent to doing dev_stop() but this does not
3221 * inform upper layers of the transistion.
3222 */
3223static void sky2_detach(struct net_device *dev)
3224{
3225 if (netif_running(dev)) {
c36531b9 3226 netif_tx_lock(dev);
af18d8b8 3227 netif_device_detach(dev); /* stop txq */
c36531b9 3228 netif_tx_unlock(dev);
af18d8b8
SH		 3229 sky2_down(dev);
3230 }
3231}
3232
3233/* Bring device back after doing sky2_detach */
3234static int sky2_reattach(struct net_device *dev)
3235{
3236 int err = 0;
3237
3238 if (netif_running(dev)) {
3239 err = sky2_up(dev);
3240 if (err) {
3241 printk(KERN_INFO PFX "%s: could not restart %d\n",
3242 dev->name, err);
3243 dev_close(dev);
3244 } else {
3245 netif_device_attach(dev);
3246 sky2_set_multicast(dev);
3247 }
3248 }
3249
3250 return err;
3251}
3252
81906791
SH		 3253static void sky2_restart(struct work_struct *work)
3254{
3255 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
af18d8b8 3256 int i;
81906791 3257
81906791 3258 rtnl_lock();
af18d8b8
SH		 3259 for (i = 0; i < hw->ports; i++)
3260 sky2_detach(hw->dev[i]);
81906791 3261
8cfcbe99
SH		 3262 napi_disable(&hw->napi);
3263 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 3264 sky2_reset(hw);
3265 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 3266 napi_enable(&hw->napi);
81906791 3267
af18d8b8
SH		 3268 for (i = 0; i < hw->ports; i++)
3269 sky2_reattach(hw->dev[i]);
81906791 3270
81906791
SH		 3271 rtnl_unlock();
3272}
3273
e3173832
SH		 3274static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3275{
3276 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3277}
3278
3279static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3280{
3281 const struct sky2_port *sky2 = netdev_priv(dev);
3282
3283 wol->supported = sky2_wol_supported(sky2->hw);
3284 wol->wolopts = sky2->wol;
3285}
3286
3287static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3288{
3289 struct sky2_port *sky2 = netdev_priv(dev);
3290 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3291
8e95a202
JP		 3292 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3293 !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3294 return -EOPNOTSUPP;
3295
3296 sky2->wol = wol->wolopts;
cd28ab6a
SH		 3297 return 0;
3298}
3299
28bd181a 3300static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3301{
b89165f2
SH		 3302 if (sky2_is_copper(hw)) {
3303 u32 modes = SUPPORTED_10baseT_Half
3304 | SUPPORTED_10baseT_Full
3305 | SUPPORTED_100baseT_Half
3306 | SUPPORTED_100baseT_Full
3307 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3308
ea76e635 3309 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3310 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3311 | SUPPORTED_1000baseT_Full;
3312 return modes;
cd28ab6a 3313 } else
b89165f2
SH		 3314 return SUPPORTED_1000baseT_Half
3315 | SUPPORTED_1000baseT_Full
3316 | SUPPORTED_Autoneg
3317 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3318}
3319
793b883e 3320static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3321{
3322 struct sky2_port *sky2 = netdev_priv(dev);
3323 struct sky2_hw *hw = sky2->hw;
3324
3325 ecmd->transceiver = XCVR_INTERNAL;
3326 ecmd->supported = sky2_supported_modes(hw);
3327 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3328 if (sky2_is_copper(hw)) {
cd28ab6a 3329 ecmd->port = PORT_TP;
b89165f2
SH		 3330 ecmd->speed = sky2->speed;
3331 } else {
3332 ecmd->speed = SPEED_1000;
cd28ab6a 3333 ecmd->port = PORT_FIBRE;
b89165f2 3334 }
cd28ab6a
SH		 3335
3336 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3337 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3338 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3339 ecmd->duplex = sky2->duplex;
3340 return 0;
3341}
3342
3343static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3344{
3345 struct sky2_port *sky2 = netdev_priv(dev);
3346 const struct sky2_hw *hw = sky2->hw;
3347 u32 supported = sky2_supported_modes(hw);
3348
3349 if (ecmd->autoneg == AUTONEG_ENABLE) {
0ea065e5 3350 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3351 ecmd->advertising = supported;
3352 sky2->duplex = -1;
3353 sky2->speed = -1;
3354 } else {
3355 u32 setting;
3356
793b883e 3357 switch (ecmd->speed) {
cd28ab6a
SH		 3358 case SPEED_1000:
3359 if (ecmd->duplex == DUPLEX_FULL)
3360 setting = SUPPORTED_1000baseT_Full;
3361 else if (ecmd->duplex == DUPLEX_HALF)
3362 setting = SUPPORTED_1000baseT_Half;
3363 else
3364 return -EINVAL;
3365 break;
3366 case SPEED_100:
3367 if (ecmd->duplex == DUPLEX_FULL)
3368 setting = SUPPORTED_100baseT_Full;
3369 else if (ecmd->duplex == DUPLEX_HALF)
3370 setting = SUPPORTED_100baseT_Half;
3371 else
3372 return -EINVAL;
3373 break;
3374
3375 case SPEED_10:
3376 if (ecmd->duplex == DUPLEX_FULL)
3377 setting = SUPPORTED_10baseT_Full;
3378 else if (ecmd->duplex == DUPLEX_HALF)
3379 setting = SUPPORTED_10baseT_Half;
3380 else
3381 return -EINVAL;
3382 break;
3383 default:
3384 return -EINVAL;
3385 }
3386
3387 if ((setting & supported) == 0)
3388 return -EINVAL;
3389
3390 sky2->speed = ecmd->speed;
3391 sky2->duplex = ecmd->duplex;
0ea065e5 3392 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3393 }
3394
cd28ab6a
SH		 3395 sky2->advertising = ecmd->advertising;
3396
d1b139c0 3397 if (netif_running(dev)) {
1b537565 3398 sky2_phy_reinit(sky2);
d1b139c0
SH		 3399 sky2_set_multicast(dev);
3400 }
cd28ab6a
SH		 3401
3402 return 0;
3403}
3404
3405static void sky2_get_drvinfo(struct net_device *dev,
3406 struct ethtool_drvinfo *info)
3407{
3408 struct sky2_port *sky2 = netdev_priv(dev);
3409
3410 strcpy(info->driver, DRV_NAME);
3411 strcpy(info->version, DRV_VERSION);
3412 strcpy(info->fw_version, "N/A");
3413 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3414}
3415
3416static const struct sky2_stat {
793b883e
SH		 3417 char name[ETH_GSTRING_LEN];
3418 u16 offset;
cd28ab6a
SH		 3419} sky2_stats[] = {
3420 { "tx_bytes", GM_TXO_OK_HI },
3421 { "rx_bytes", GM_RXO_OK_HI },
3422 { "tx_broadcast", GM_TXF_BC_OK },
3423 { "rx_broadcast", GM_RXF_BC_OK },
3424 { "tx_multicast", GM_TXF_MC_OK },
3425 { "rx_multicast", GM_RXF_MC_OK },
3426 { "tx_unicast", GM_TXF_UC_OK },
3427 { "rx_unicast", GM_RXF_UC_OK },
3428 { "tx_mac_pause", GM_TXF_MPAUSE },
3429 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3430 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3431 { "late_collision",GM_TXF_LAT_COL },
3432 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3433 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3434 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3435
d2604540 3436 { "rx_short", GM_RXF_SHT },
cd28ab6a 3437 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3438 { "rx_64_byte_packets", GM_RXF_64B },
3439 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3440 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3441 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3442 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3443 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3444 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3445 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3446 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3447 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3448 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3449
3450 { "tx_64_byte_packets", GM_TXF_64B },
3451 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3452 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3453 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3454 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3455 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3456 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3457 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3458};
3459
cd28ab6a
SH		 3460static u32 sky2_get_rx_csum(struct net_device *dev)
3461{
3462 struct sky2_port *sky2 = netdev_priv(dev);
3463
0ea065e5 3464 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
cd28ab6a
SH		 3465}
3466
3467static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3468{
3469 struct sky2_port *sky2 = netdev_priv(dev);
3470
0ea065e5
SH		 3471 if (data)
3472 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3473 else
3474 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
793b883e 3475
cd28ab6a
SH		 3476 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3477 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3478
3479 return 0;
3480}
3481
3482static u32 sky2_get_msglevel(struct net_device *netdev)
3483{
3484 struct sky2_port *sky2 = netdev_priv(netdev);
3485 return sky2->msg_enable;
3486}
3487
9a7ae0a9
SH		 3488static int sky2_nway_reset(struct net_device *dev)
3489{
3490 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3491
0ea065e5 3492 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3493 return -EINVAL;
3494
1b537565 3495 sky2_phy_reinit(sky2);
d1b139c0 3496 sky2_set_multicast(dev);
9a7ae0a9
SH		 3497
3498 return 0;
3499}
3500
793b883e 3501static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3502{
3503 struct sky2_hw *hw = sky2->hw;
3504 unsigned port = sky2->port;
3505 int i;
3506
3507 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3508 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3509 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3510 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3511
793b883e 3512 for (i = 2; i < count; i++)
cd28ab6a
SH		 3513 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3514}
3515
cd28ab6a
SH		 3516static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3517{
3518 struct sky2_port *sky2 = netdev_priv(netdev);
3519 sky2->msg_enable = value;
3520}
3521
b9f2c044 3522static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3523{
b9f2c044
JG		 3524 switch (sset) {
3525 case ETH_SS_STATS:
3526 return ARRAY_SIZE(sky2_stats);
3527 default:
3528 return -EOPNOTSUPP;
3529 }
cd28ab6a
SH		 3530}
3531
3532static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3533 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3534{
3535 struct sky2_port *sky2 = netdev_priv(dev);
3536
793b883e 3537 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3538}
3539
793b883e 3540static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3541{
3542 int i;
3543
3544 switch (stringset) {
3545 case ETH_SS_STATS:
3546 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3547 memcpy(data + i * ETH_GSTRING_LEN,
3548 sky2_stats[i].name, ETH_GSTRING_LEN);
3549 break;
3550 }
3551}
3552
cd28ab6a
SH		 3553static int sky2_set_mac_address(struct net_device *dev, void *p)
3554{
3555 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3556 struct sky2_hw *hw = sky2->hw;
3557 unsigned port = sky2->port;
3558 const struct sockaddr *addr = p;
cd28ab6a
SH		 3559
3560 if (!is_valid_ether_addr(addr->sa_data))
3561 return -EADDRNOTAVAIL;
3562
cd28ab6a 3563 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3564 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3565 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3566 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3567 dev->dev_addr, ETH_ALEN);
1b537565 3568
a8ab1ec0
SH		 3569 /* virtual address for data */
3570 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3571
3572 /* physical address: used for pause frames */
3573 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3574
3575 return 0;
cd28ab6a
SH		 3576}
3577
a052b52f
SH		 3578static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3579{
3580 u32 bit;
3581
3582 bit = ether_crc(ETH_ALEN, addr) & 63;
3583 filter[bit >> 3] |= 1 << (bit & 7);
3584}
3585
cd28ab6a
SH		 3586static void sky2_set_multicast(struct net_device *dev)
3587{
3588 struct sky2_port *sky2 = netdev_priv(dev);
3589 struct sky2_hw *hw = sky2->hw;
3590 unsigned port = sky2->port;
3591 struct dev_mc_list *list = dev->mc_list;
3592 u16 reg;
3593 u8 filter[8];
a052b52f
SH		 3594 int rx_pause;
3595 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3596
a052b52f 3597 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3598 memset(filter, 0, sizeof(filter));
3599
3600 reg = gma_read16(hw, port, GM_RX_CTRL);
3601 reg |= GM_RXCR_UCF_ENA;
3602
d571b694 3603 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3604 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3605 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3606 memset(filter, 0xff, sizeof(filter));
4cd24eaf 3607 else if (netdev_mc_empty(dev) && !rx_pause)
cd28ab6a
SH		 3608 reg &= ~GM_RXCR_MCF_ENA;
3609 else {
3610 int i;
3611 reg |= GM_RXCR_MCF_ENA;
3612
a052b52f
SH		 3613 if (rx_pause)
3614 sky2_add_filter(filter, pause_mc_addr);
3615
4cd24eaf 3616 for (i = 0; list && i < netdev_mc_count(dev); i++, list = list->next)
a052b52f 3617 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3618 }
3619
cd28ab6a 3620 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3621 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3622 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3623 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3624 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3625 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3626 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3627 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3628
3629 gma_write16(hw, port, GM_RX_CTRL, reg);
3630}
3631
3632/* Can have one global because blinking is controlled by
3633 * ethtool and that is always under RTNL mutex
3634 */
a84d0a3d 3635static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3636{
a84d0a3d
SH		 3637 struct sky2_hw *hw = sky2->hw;
3638 unsigned port = sky2->port;
793b883e 3639
a84d0a3d
SH		 3640 spin_lock_bh(&sky2->phy_lock);
3641 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3642 hw->chip_id == CHIP_ID_YUKON_EX ||
3643 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3644 u16 pg;
793b883e
SH		 3645 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3646 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3647
a84d0a3d
SH		 3648 switch (mode) {
3649 case MO_LED_OFF:
3650 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3651 PHY_M_LEDC_LOS_CTRL(8) |
3652 PHY_M_LEDC_INIT_CTRL(8) |
3653 PHY_M_LEDC_STA1_CTRL(8) |
3654 PHY_M_LEDC_STA0_CTRL(8));
3655 break;
3656 case MO_LED_ON:
3657 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3658 PHY_M_LEDC_LOS_CTRL(9) |
3659 PHY_M_LEDC_INIT_CTRL(9) |
3660 PHY_M_LEDC_STA1_CTRL(9) |
3661 PHY_M_LEDC_STA0_CTRL(9));
3662 break;
3663 case MO_LED_BLINK:
3664 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3665 PHY_M_LEDC_LOS_CTRL(0xa) |
3666 PHY_M_LEDC_INIT_CTRL(0xa) |
3667 PHY_M_LEDC_STA1_CTRL(0xa) |
3668 PHY_M_LEDC_STA0_CTRL(0xa));
3669 break;
3670 case MO_LED_NORM:
3671 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3672 PHY_M_LEDC_LOS_CTRL(1) |
3673 PHY_M_LEDC_INIT_CTRL(8) |
3674 PHY_M_LEDC_STA1_CTRL(7) |
3675 PHY_M_LEDC_STA0_CTRL(7));
3676 }
793b883e 3677
a84d0a3d
SH		 3678 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3679 } else
7d2e3cb7 3680 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3681 PHY_M_LED_MO_DUP(mode) |
3682 PHY_M_LED_MO_10(mode) |
3683 PHY_M_LED_MO_100(mode) |
3684 PHY_M_LED_MO_1000(mode) |
3685 PHY_M_LED_MO_RX(mode) |
3686 PHY_M_LED_MO_TX(mode));
3687
3688 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3689}
3690
3691/* blink LED's for finding board */
3692static int sky2_phys_id(struct net_device *dev, u32 data)
3693{
3694 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3695 unsigned int i;
cd28ab6a 3696
a84d0a3d
SH		 3697 if (data == 0)
3698 data = UINT_MAX;
cd28ab6a 3699
a84d0a3d
SH		 3700 for (i = 0; i < data; i++) {
3701 sky2_led(sky2, MO_LED_ON);
3702 if (msleep_interruptible(500))
3703 break;
3704 sky2_led(sky2, MO_LED_OFF);
3705 if (msleep_interruptible(500))
3706 break;
793b883e 3707 }
a84d0a3d 3708 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3709
3710 return 0;
3711}
3712
3713static void sky2_get_pauseparam(struct net_device *dev,
3714 struct ethtool_pauseparam *ecmd)
3715{
3716 struct sky2_port *sky2 = netdev_priv(dev);
3717
16ad91e1
SH		 3718 switch (sky2->flow_mode) {
3719 case FC_NONE:
3720 ecmd->tx_pause = ecmd->rx_pause = 0;
3721 break;
3722 case FC_TX:
3723 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3724 break;
3725 case FC_RX:
3726 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3727 break;
3728 case FC_BOTH:
3729 ecmd->tx_pause = ecmd->rx_pause = 1;
3730 }
3731
0ea065e5
SH		 3732 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3733 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3734}
3735
3736static int sky2_set_pauseparam(struct net_device *dev,
3737 struct ethtool_pauseparam *ecmd)
3738{
3739 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3740
0ea065e5
SH		 3741 if (ecmd->autoneg == AUTONEG_ENABLE)
3742 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3743 else
3744 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3745
16ad91e1 3746 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3747
16ad91e1
SH		 3748 if (netif_running(dev))
3749 sky2_phy_reinit(sky2);
cd28ab6a 3750
2eaba1a2 3751 return 0;
cd28ab6a
SH		 3752}
3753
fb17358f
SH		 3754static int sky2_get_coalesce(struct net_device *dev,
3755 struct ethtool_coalesce *ecmd)
3756{
3757 struct sky2_port *sky2 = netdev_priv(dev);
3758 struct sky2_hw *hw = sky2->hw;
3759
3760 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3761 ecmd->tx_coalesce_usecs = 0;
3762 else {
3763 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3764 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3765 }
3766 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3767
3768 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3769 ecmd->rx_coalesce_usecs = 0;
3770 else {
3771 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3772 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3773 }
3774 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3775
3776 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3777 ecmd->rx_coalesce_usecs_irq = 0;
3778 else {
3779 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3780 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3781 }
3782
3783 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3784
3785 return 0;
3786}
3787
3788/* Note: this affect both ports */
3789static int sky2_set_coalesce(struct net_device *dev,
3790 struct ethtool_coalesce *ecmd)
3791{
3792 struct sky2_port *sky2 = netdev_priv(dev);
3793 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3794 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3795
77b3d6a2
SH		 3796 if (ecmd->tx_coalesce_usecs > tmax ||
3797 ecmd->rx_coalesce_usecs > tmax ||
3798 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3799 return -EINVAL;
3800
ee5f68fe 3801 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
fb17358f 3802 return -EINVAL;
ff81fbbe 3803 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3804 return -EINVAL;
ff81fbbe 3805 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3806 return -EINVAL;
3807
3808 if (ecmd->tx_coalesce_usecs == 0)
3809 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3810 else {
3811 sky2_write32(hw, STAT_TX_TIMER_INI,
3812 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3813 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3814 }
3815 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3816
3817 if (ecmd->rx_coalesce_usecs == 0)
3818 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3819 else {
3820 sky2_write32(hw, STAT_LEV_TIMER_INI,
3821 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3822 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3823 }
3824 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3825
3826 if (ecmd->rx_coalesce_usecs_irq == 0)
3827 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3828 else {
d28d4870 3829 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3830 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3831 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3832 }
3833 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3834 return 0;
3835}
3836
793b883e
SH		 3837static void sky2_get_ringparam(struct net_device *dev,
3838 struct ethtool_ringparam *ering)
3839{
3840 struct sky2_port *sky2 = netdev_priv(dev);
3841
3842 ering->rx_max_pending = RX_MAX_PENDING;
3843 ering->rx_mini_max_pending = 0;
3844 ering->rx_jumbo_max_pending = 0;
ee5f68fe 3845 ering->tx_max_pending = TX_MAX_PENDING;
793b883e
SH		 3846
3847 ering->rx_pending = sky2->rx_pending;
3848 ering->rx_mini_pending = 0;
3849 ering->rx_jumbo_pending = 0;
3850 ering->tx_pending = sky2->tx_pending;
3851}
3852
3853static int sky2_set_ringparam(struct net_device *dev,
3854 struct ethtool_ringparam *ering)
3855{
3856 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 3857
3858 if (ering->rx_pending > RX_MAX_PENDING ||
3859 ering->rx_pending < 8 ||
ee5f68fe
SH		 3860 ering->tx_pending < TX_MIN_PENDING ||
3861 ering->tx_pending > TX_MAX_PENDING)
793b883e
SH		 3862 return -EINVAL;
3863
af18d8b8 3864 sky2_detach(dev);
793b883e
SH		 3865
3866 sky2->rx_pending = ering->rx_pending;
3867 sky2->tx_pending = ering->tx_pending;
ee5f68fe 3868 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
793b883e 3869
af18d8b8 3870 return sky2_reattach(dev);
793b883e
SH		 3871}
3872
793b883e
SH		 3873static int sky2_get_regs_len(struct net_device *dev)
3874{
6e4cbb34 3875 return 0x4000;
793b883e
SH		 3876}
3877
c32bbff8
MM		 3878static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
3879{
3880 /* This complicated switch statement is to make sure and
3881 * only access regions that are unreserved.
3882 * Some blocks are only valid on dual port cards.
3883 */
3884 switch (b) {
3885 /* second port */
3886 case 5: /* Tx Arbiter 2 */
3887 case 9: /* RX2 */
3888 case 14 ... 15: /* TX2 */
3889 case 17: case 19: /* Ram Buffer 2 */
3890 case 22 ... 23: /* Tx Ram Buffer 2 */
3891 case 25: /* Rx MAC Fifo 1 */
3892 case 27: /* Tx MAC Fifo 2 */
3893 case 31: /* GPHY 2 */
3894 case 40 ... 47: /* Pattern Ram 2 */
3895 case 52: case 54: /* TCP Segmentation 2 */
3896 case 112 ... 116: /* GMAC 2 */
3897 return hw->ports > 1;
3898
3899 case 0: /* Control */
3900 case 2: /* Mac address */
3901 case 4: /* Tx Arbiter 1 */
3902 case 7: /* PCI express reg */
3903 case 8: /* RX1 */
3904 case 12 ... 13: /* TX1 */
3905 case 16: case 18:/* Rx Ram Buffer 1 */
3906 case 20 ... 21: /* Tx Ram Buffer 1 */
3907 case 24: /* Rx MAC Fifo 1 */
3908 case 26: /* Tx MAC Fifo 1 */
3909 case 28 ... 29: /* Descriptor and status unit */
3910 case 30: /* GPHY 1*/
3911 case 32 ... 39: /* Pattern Ram 1 */
3912 case 48: case 50: /* TCP Segmentation 1 */
3913 case 56 ... 60: /* PCI space */
3914 case 80 ... 84: /* GMAC 1 */
3915 return 1;
3916
3917 default:
3918 return 0;
3919 }
3920}
3921
793b883e
SH		 3922/*
3923 * Returns copy of control register region
3ead5db7 3924 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3925 */
3926static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3927 void *p)
3928{
3929 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3930 const void __iomem *io = sky2->hw->regs;
295b54c4 3931 unsigned int b;
793b883e
SH		 3932
3933 regs->version = 1;
793b883e 3934
295b54c4 3935 for (b = 0; b < 128; b++) {
c32bbff8
MM		 3936 /* skip poisonous diagnostic ram region in block 3 */
3937 if (b == 3)
295b54c4 3938 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
c32bbff8 3939 else if (sky2_reg_access_ok(sky2->hw, b))
295b54c4 3940 memcpy_fromio(p, io, 128);
c32bbff8 3941 else
295b54c4 3942 memset(p, 0, 128);
3ead5db7 3943
295b54c4
SH		 3944 p += 128;
3945 io += 128;
3946 }
793b883e 3947}
cd28ab6a 3948
b628ed98
SH		 3949/* In order to do Jumbo packets on these chips, need to turn off the
3950 * transmit store/forward. Therefore checksum offload won't work.
3951 */
3952static int no_tx_offload(struct net_device *dev)
3953{
3954 const struct sky2_port *sky2 = netdev_priv(dev);
3955 const struct sky2_hw *hw = sky2->hw;
3956
69161611 3957 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3958}
3959
3960static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3961{
3962 if (data && no_tx_offload(dev))
3963 return -EINVAL;
3964
3965 return ethtool_op_set_tx_csum(dev, data);
3966}
3967
3968
3969static int sky2_set_tso(struct net_device *dev, u32 data)
3970{
3971 if (data && no_tx_offload(dev))
3972 return -EINVAL;
3973
3974 return ethtool_op_set_tso(dev, data);
3975}
3976
f4331a6d
SH		 3977static int sky2_get_eeprom_len(struct net_device *dev)
3978{
3979 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3980 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3981 u16 reg2;
3982
b32f40c4 3983 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3984 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3985}
3986
1413235c 3987static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 3988{
1413235c 3989 unsigned long start = jiffies;
f4331a6d 3990
1413235c
SH		 3991 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3992 /* Can take up to 10.6 ms for write */
3993 if (time_after(jiffies, start + HZ/4)) {
3994 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3995 return -ETIMEDOUT;
3996 }
3997 mdelay(1);
3998 }
167f53d0 3999
1413235c
SH		 4000 return 0;
4001}
167f53d0 4002
1413235c
SH		 4003static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4004 u16 offset, size_t length)
4005{
4006 int rc = 0;
4007
4008 while (length > 0) {
4009 u32 val;
4010
4011 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4012 rc = sky2_vpd_wait(hw, cap, 0);
4013 if (rc)
4014 break;
4015
4016 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4017
4018 memcpy(data, &val, min(sizeof(val), length));
4019 offset += sizeof(u32);
4020 data += sizeof(u32);
4021 length -= sizeof(u32);
4022 }
4023
4024 return rc;
f4331a6d
SH		 4025}
4026
1413235c
SH		 4027static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4028 u16 offset, unsigned int length)
f4331a6d 4029{
1413235c
SH		 4030 unsigned int i;
4031 int rc = 0;
4032
4033 for (i = 0; i < length; i += sizeof(u32)) {
4034 u32 val = *(u32 *)(data + i);
4035
4036 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4037 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4038
4039 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4040 if (rc)
4041 break;
4042 }
4043 return rc;
f4331a6d
SH		 4044}
4045
4046static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4047 u8 *data)
4048{
4049 struct sky2_port *sky2 = netdev_priv(dev);
4050 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4051
4052 if (!cap)
4053 return -EINVAL;
4054
4055 eeprom->magic = SKY2_EEPROM_MAGIC;
4056
1413235c 4057 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4058}
4059
4060static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4061 u8 *data)
4062{
4063 struct sky2_port *sky2 = netdev_priv(dev);
4064 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4065
4066 if (!cap)
4067 return -EINVAL;
4068
4069 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4070 return -EINVAL;
4071
1413235c
SH		 4072 /* Partial writes not supported */
4073 if ((eeprom->offset & 3) || (eeprom->len & 3))
4074 return -EINVAL;
f4331a6d 4075
1413235c 4076 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4077}
4078
4079
7282d491 4080static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 4081 .get_settings = sky2_get_settings,
4082 .set_settings = sky2_set_settings,
4083 .get_drvinfo = sky2_get_drvinfo,
4084 .get_wol = sky2_get_wol,
4085 .set_wol = sky2_set_wol,
4086 .get_msglevel = sky2_get_msglevel,
4087 .set_msglevel = sky2_set_msglevel,
4088 .nway_reset = sky2_nway_reset,
4089 .get_regs_len = sky2_get_regs_len,
4090 .get_regs = sky2_get_regs,
4091 .get_link = ethtool_op_get_link,
4092 .get_eeprom_len = sky2_get_eeprom_len,
4093 .get_eeprom = sky2_get_eeprom,
4094 .set_eeprom = sky2_set_eeprom,
f4331a6d 4095 .set_sg = ethtool_op_set_sg,
f4331a6d 4096 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 4097 .set_tso = sky2_set_tso,
4098 .get_rx_csum = sky2_get_rx_csum,
4099 .set_rx_csum = sky2_set_rx_csum,
4100 .get_strings = sky2_get_strings,
4101 .get_coalesce = sky2_get_coalesce,
4102 .set_coalesce = sky2_set_coalesce,
4103 .get_ringparam = sky2_get_ringparam,
4104 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 4105 .get_pauseparam = sky2_get_pauseparam,
4106 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 4107 .phys_id = sky2_phys_id,
b9f2c044 4108 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 4109 .get_ethtool_stats = sky2_get_ethtool_stats,
4110};
4111
3cf26753
SH		 4112#ifdef CONFIG_SKY2_DEBUG
4113
4114static struct dentry *sky2_debug;
4115
e4c2abe2
SH		 4116
4117/*
4118 * Read and parse the first part of Vital Product Data
4119 */
4120#define VPD_SIZE 128
4121#define VPD_MAGIC 0x82
4122
4123static const struct vpd_tag {
4124 char tag[2];
4125 char *label;
4126} vpd_tags[] = {
4127 { "PN", "Part Number" },
4128 { "EC", "Engineering Level" },
4129 { "MN", "Manufacturer" },
4130 { "SN", "Serial Number" },
4131 { "YA", "Asset Tag" },
4132 { "VL", "First Error Log Message" },
4133 { "VF", "Second Error Log Message" },
4134 { "VB", "Boot Agent ROM Configuration" },
4135 { "VE", "EFI UNDI Configuration" },
4136};
4137
4138static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4139{
4140 size_t vpd_size;
4141 loff_t offs;
4142 u8 len;
4143 unsigned char *buf;
4144 u16 reg2;
4145
4146 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4147 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4148
4149 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4150 buf = kmalloc(vpd_size, GFP_KERNEL);
4151 if (!buf) {
4152 seq_puts(seq, "no memory!\n");
4153 return;
4154 }
4155
4156 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4157 seq_puts(seq, "VPD read failed\n");
4158 goto out;
4159 }
4160
4161 if (buf[0] != VPD_MAGIC) {
4162 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4163 goto out;
4164 }
4165 len = buf[1];
4166 if (len == 0 || len > vpd_size - 4) {
4167 seq_printf(seq, "Invalid id length: %d\n", len);
4168 goto out;
4169 }
4170
4171 seq_printf(seq, "%.*s\n", len, buf + 3);
4172 offs = len + 3;
4173
4174 while (offs < vpd_size - 4) {
4175 int i;
4176
4177 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4178 break;
4179 len = buf[offs + 2];
4180 if (offs + len + 3 >= vpd_size)
4181 break;
4182
4183 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4184 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4185 seq_printf(seq, " %s: %.*s\n",
4186 vpd_tags[i].label, len, buf + offs + 3);
4187 break;
4188 }
4189 }
4190 offs += len + 3;
4191 }
4192out:
4193 kfree(buf);
4194}
4195
3cf26753
SH		 4196static int sky2_debug_show(struct seq_file *seq, void *v)
4197{
4198 struct net_device *dev = seq->private;
4199 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4200 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4201 unsigned port = sky2->port;
4202 unsigned idx, last;
4203 int sop;
4204
e4c2abe2 4205 sky2_show_vpd(seq, hw);
3cf26753 4206
e4c2abe2 4207 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4208 sky2_read32(hw, B0_ISRC),
4209 sky2_read32(hw, B0_IMSK),
4210 sky2_read32(hw, B0_Y2_SP_ICR));
4211
e4c2abe2
SH		 4212 if (!netif_running(dev)) {
4213 seq_printf(seq, "network not running\n");
4214 return 0;
4215 }
4216
bea3348e 4217 napi_disable(&hw->napi);
3cf26753
SH		 4218 last = sky2_read16(hw, STAT_PUT_IDX);
4219
4220 if (hw->st_idx == last)
4221 seq_puts(seq, "Status ring (empty)\n");
4222 else {
4223 seq_puts(seq, "Status ring\n");
4224 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4225 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4226 const struct sky2_status_le *le = hw->st_le + idx;
4227 seq_printf(seq, "[%d] %#x %d %#x\n",
4228 idx, le->opcode, le->length, le->status);
4229 }
4230 seq_puts(seq, "\n");
4231 }
4232
4233 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4234 sky2->tx_cons, sky2->tx_prod,
4235 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4236 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4237
4238 /* Dump contents of tx ring */
4239 sop = 1;
ee5f68fe
SH		 4240 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4241 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
3cf26753
SH		 4242 const struct sky2_tx_le *le = sky2->tx_le + idx;
4243 u32 a = le32_to_cpu(le->addr);
4244
4245 if (sop)
4246 seq_printf(seq, "%u:", idx);
4247 sop = 0;
4248
4249 switch(le->opcode & ~HW_OWNER) {
4250 case OP_ADDR64:
4251 seq_printf(seq, " %#x:", a);
4252 break;
4253 case OP_LRGLEN:
4254 seq_printf(seq, " mtu=%d", a);
4255 break;
4256 case OP_VLAN:
4257 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4258 break;
4259 case OP_TCPLISW:
4260 seq_printf(seq, " csum=%#x", a);
4261 break;
4262 case OP_LARGESEND:
4263 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4264 break;
4265 case OP_PACKET:
4266 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4267 break;
4268 case OP_BUFFER:
4269 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4270 break;
4271 default:
4272 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4273 a, le16_to_cpu(le->length));
4274 }
4275
4276 if (le->ctrl & EOP) {
4277 seq_putc(seq, '\n');
4278 sop = 1;
4279 }
4280 }
4281
4282 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4283 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4284 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4285 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4286
d1d08d12 4287 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4288 napi_enable(&hw->napi);
3cf26753
SH		 4289 return 0;
4290}
4291
4292static int sky2_debug_open(struct inode *inode, struct file *file)
4293{
4294 return single_open(file, sky2_debug_show, inode->i_private);
4295}
4296
4297static const struct file_operations sky2_debug_fops = {
4298 .owner = THIS_MODULE,
4299 .open = sky2_debug_open,
4300 .read = seq_read,
4301 .llseek = seq_lseek,
4302 .release = single_release,
4303};
4304
4305/*
4306 * Use network device events to create/remove/rename
4307 * debugfs file entries
4308 */
4309static int sky2_device_event(struct notifier_block *unused,
4310 unsigned long event, void *ptr)
4311{
4312 struct net_device *dev = ptr;
5b296bc9 4313 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4314
1436b301 4315 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4316 return NOTIFY_DONE;
3cf26753 4317
5b296bc9
SH		 4318 switch(event) {
4319 case NETDEV_CHANGENAME:
4320 if (sky2->debugfs) {
4321 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4322 sky2_debug, dev->name);
4323 }
4324 break;
3cf26753 4325
5b296bc9
SH		 4326 case NETDEV_GOING_DOWN:
4327 if (sky2->debugfs) {
4328 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4329 dev->name);
4330 debugfs_remove(sky2->debugfs);
4331 sky2->debugfs = NULL;
3cf26753 4332 }
5b296bc9
SH		 4333 break;
4334
4335 case NETDEV_UP:
4336 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4337 sky2_debug, dev,
4338 &sky2_debug_fops);
4339 if (IS_ERR(sky2->debugfs))
4340 sky2->debugfs = NULL;
3cf26753
SH		 4341 }
4342
4343 return NOTIFY_DONE;
4344}
4345
4346static struct notifier_block sky2_notifier = {
4347 .notifier_call = sky2_device_event,
4348};
4349
4350
4351static __init void sky2_debug_init(void)
4352{
4353 struct dentry *ent;
4354
4355 ent = debugfs_create_dir("sky2", NULL);
4356 if (!ent || IS_ERR(ent))
4357 return;
4358
4359 sky2_debug = ent;
4360 register_netdevice_notifier(&sky2_notifier);
4361}
4362
4363static __exit void sky2_debug_cleanup(void)
4364{
4365 if (sky2_debug) {
4366 unregister_netdevice_notifier(&sky2_notifier);
4367 debugfs_remove(sky2_debug);
4368 sky2_debug = NULL;
4369 }
4370}
4371
4372#else
4373#define sky2_debug_init()
4374#define sky2_debug_cleanup()
4375#endif
4376
1436b301
SH		 4377/* Two copies of network device operations to handle special case of
4378 not allowing netpoll on second port */
4379static const struct net_device_ops sky2_netdev_ops[2] = {
4380 {
4381 .ndo_open = sky2_up,
4382 .ndo_stop = sky2_down,
00829823 4383 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4384 .ndo_do_ioctl = sky2_ioctl,
4385 .ndo_validate_addr = eth_validate_addr,
4386 .ndo_set_mac_address = sky2_set_mac_address,
4387 .ndo_set_multicast_list = sky2_set_multicast,
4388 .ndo_change_mtu = sky2_change_mtu,
4389 .ndo_tx_timeout = sky2_tx_timeout,
4390#ifdef SKY2_VLAN_TAG_USED
4391 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4392#endif
4393#ifdef CONFIG_NET_POLL_CONTROLLER
4394 .ndo_poll_controller = sky2_netpoll,
4395#endif
4396 },
4397 {
4398 .ndo_open = sky2_up,
4399 .ndo_stop = sky2_down,
00829823 4400 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4401 .ndo_do_ioctl = sky2_ioctl,
4402 .ndo_validate_addr = eth_validate_addr,
4403 .ndo_set_mac_address = sky2_set_mac_address,
4404 .ndo_set_multicast_list = sky2_set_multicast,
4405 .ndo_change_mtu = sky2_change_mtu,
4406 .ndo_tx_timeout = sky2_tx_timeout,
4407#ifdef SKY2_VLAN_TAG_USED
4408 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4409#endif
4410 },
4411};
3cf26753 4412
cd28ab6a
SH		 4413/* Initialize network device */
4414static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4415 unsigned port,
be63a21c 4416 int highmem, int wol)
cd28ab6a
SH		 4417{
4418 struct sky2_port *sky2;
4419 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4420
4421 if (!dev) {
898eb71c 4422 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4423 return NULL;
4424 }
4425
cd28ab6a 4426 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4427 dev->irq = hw->pdev->irq;
cd28ab6a 4428 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4429 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4430 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4431
4432 sky2 = netdev_priv(dev);
4433 sky2->netdev = dev;
4434 sky2->hw = hw;
4435 sky2->msg_enable = netif_msg_init(debug, default_msg);
4436
cd28ab6a 4437 /* Auto speed and flow control */
0ea065e5
SH		 4438 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4439 if (hw->chip_id != CHIP_ID_YUKON_XL)
4440 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4441
16ad91e1
SH		 4442 sky2->flow_mode = FC_BOTH;
4443
cd28ab6a
SH		 4444 sky2->duplex = -1;
4445 sky2->speed = -1;
4446 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4447 sky2->wol = wol;
75d070c5 4448
e07b1aa8 4449 spin_lock_init(&sky2->phy_lock);
ee5f68fe 4450
793b883e 4451 sky2->tx_pending = TX_DEF_PENDING;
ee5f68fe 4452 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
290d4de5 4453 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4454
4455 hw->dev[port] = dev;
4456
4457 sky2->port = port;
4458
4a50a876 4459 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4460 if (highmem)
4461 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4462
d1f13708 4463#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4464 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4465 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4466 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4467 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4468 }
d1f13708 4469#endif
4470
cd28ab6a 4471 /* read the mac address */
793b883e 4472 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4473 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4474
cd28ab6a
SH		 4475 return dev;
4476}
4477
28bd181a 4478static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4479{
4480 const struct sky2_port *sky2 = netdev_priv(dev);
4481
4482 if (netif_msg_probe(sky2))
e174961c
JB		 4483 printk(KERN_INFO PFX "%s: addr %pM\n",
4484 dev->name, dev->dev_addr);
cd28ab6a
SH		 4485}
4486
fb2690a9 4487/* Handle software interrupt used during MSI test */
7d12e780 4488static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4489{
4490 struct sky2_hw *hw = dev_id;
4491 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4492
4493 if (status == 0)
4494 return IRQ_NONE;
4495
4496 if (status & Y2_IS_IRQ_SW) {
ea76e635 4497 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4498 wake_up(&hw->msi_wait);
4499 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4500 }
4501 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4502
4503 return IRQ_HANDLED;
4504}
4505
4506/* Test interrupt path by forcing a a software IRQ */
4507static int __devinit sky2_test_msi(struct sky2_hw *hw)
4508{
4509 struct pci_dev *pdev = hw->pdev;
4510 int err;
4511
bb507fe1 4512 init_waitqueue_head (&hw->msi_wait);
4513
fb2690a9
SH		 4514 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4515
b0a20ded 4516 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4517 if (err) {
b02a9258 4518 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4519 return err;
4520 }
4521
fb2690a9 4522 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4523 sky2_read8(hw, B0_CTST);
fb2690a9 4524
ea76e635 4525 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4526
ea76e635 4527 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4528 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4529 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4530 "switching to INTx mode.\n");
fb2690a9
SH		 4531
4532 err = -EOPNOTSUPP;
4533 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4534 }
4535
4536 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4537 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4538
4539 free_irq(pdev->irq, hw);
4540
4541 return err;
4542}
4543
c7127a34
SH		 4544/* This driver supports yukon2 chipset only */
4545static const char *sky2_name(u8 chipid, char *buf, int sz)
4546{
4547 const char *name[] = {
4548 "XL", /* 0xb3 */
4549 "EC Ultra", /* 0xb4 */
4550 "Extreme", /* 0xb5 */
4551 "EC", /* 0xb6 */
4552 "FE", /* 0xb7 */
4553 "FE+", /* 0xb8 */
4554 "Supreme", /* 0xb9 */
0ce8b98d 4555 "UL 2", /* 0xba */
0f5aac70
SH		 4556 "Unknown", /* 0xbb */
4557 "Optima", /* 0xbc */
c7127a34
SH		 4558 };
4559
dae3a511 4560 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
c7127a34
SH		 4561 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4562 else
4563 snprintf(buf, sz, "(chip %#x)", chipid);
4564 return buf;
4565}
4566
cd28ab6a
SH		 4567static int __devinit sky2_probe(struct pci_dev *pdev,
4568 const struct pci_device_id *ent)
4569{
7f60c64b 4570 struct net_device *dev;
cd28ab6a 4571 struct sky2_hw *hw;
be63a21c 4572 int err, using_dac = 0, wol_default;
3834507d 4573 u32 reg;
c7127a34 4574 char buf1[16];
cd28ab6a 4575
793b883e
SH		 4576 err = pci_enable_device(pdev);
4577 if (err) {
b02a9258 4578 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4579 goto err_out;
4580 }
4581
6cc90a5a
SH		 4582 /* Get configuration information
4583 * Note: only regular PCI config access once to test for HW issues
4584 * other PCI access through shared memory for speed and to
4585 * avoid MMCONFIG problems.
4586 */
4587 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4588 if (err) {
4589 dev_err(&pdev->dev, "PCI read config failed\n");
4590 goto err_out;
4591 }
4592
4593 if (~reg == 0) {
4594 dev_err(&pdev->dev, "PCI configuration read error\n");
4595 goto err_out;
4596 }
4597
793b883e
SH		 4598 err = pci_request_regions(pdev, DRV_NAME);
4599 if (err) {
b02a9258 4600 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4601 goto err_out_disable;
cd28ab6a
SH		 4602 }
4603
4604 pci_set_master(pdev);
4605
d1f3d4dd 4606 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4607 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4608 using_dac = 1;
6a35528a 4609 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4610 if (err < 0) {
b02a9258
SH		 4611 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4612 "for consistent allocations\n");
d1f3d4dd
SH		 4613 goto err_out_free_regions;
4614 }
d1f3d4dd 4615 } else {
284901a9 4616 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4617 if (err) {
b02a9258 4618 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4619 goto err_out_free_regions;
4620 }
4621 }
d1f3d4dd 4622
3834507d
SH		 4623
4624#ifdef __BIG_ENDIAN
4625 /* The sk98lin vendor driver uses hardware byte swapping but
4626 * this driver uses software swapping.
4627 */
4628 reg &= ~PCI_REV_DESC;
4629 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4630 if (err) {
4631 dev_err(&pdev->dev, "PCI write config failed\n");
4632 goto err_out_free_regions;
4633 }
4634#endif
4635
9d731d77 4636 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4637
cd28ab6a 4638 err = -ENOMEM;
66466797
SH		 4639
4640 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4641 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
cd28ab6a 4642 if (!hw) {
b02a9258 4643 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4644 goto err_out_free_regions;
4645 }
4646
cd28ab6a 4647 hw->pdev = pdev;
66466797 4648 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
cd28ab6a
SH		 4649
4650 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4651 if (!hw->regs) {
b02a9258 4652 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4653 goto err_out_free_hw;
4654 }
4655
08c06d8a 4656 /* ring for status responses */
167f53d0 4657 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4658 if (!hw->st_le)
4659 goto err_out_iounmap;
4660
e3173832 4661 err = sky2_init(hw);
cd28ab6a 4662 if (err)
793b883e 4663 goto err_out_iounmap;
cd28ab6a 4664
c844d483
SH		 4665 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4666 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4667
e3173832
SH		 4668 sky2_reset(hw);
4669
be63a21c 4670 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4671 if (!dev) {
4672 err = -ENOMEM;
cd28ab6a 4673 goto err_out_free_pci;
7f60c64b 4674 }
cd28ab6a 4675
9fa1b1f3
SH		 4676 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4677 err = sky2_test_msi(hw);
4678 if (err == -EOPNOTSUPP)
4679 pci_disable_msi(pdev);
4680 else if (err)
4681 goto err_out_free_netdev;
4682 }
4683
793b883e
SH		 4684 err = register_netdev(dev);
4685 if (err) {
b02a9258 4686 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4687 goto err_out_free_netdev;
4688 }
4689
33cb7d33
BP		 4690 netif_carrier_off(dev);
4691
6de16237
SH		 4692 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4693
ea76e635
SH		 4694 err = request_irq(pdev->irq, sky2_intr,
4695 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
66466797 4696 hw->irq_name, hw);
9fa1b1f3 4697 if (err) {
b02a9258 4698 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4699 goto err_out_unregister;
4700 }
4701 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4702 napi_enable(&hw->napi);
9fa1b1f3 4703
cd28ab6a
SH		 4704 sky2_show_addr(dev);
4705
7f60c64b 4706 if (hw->ports > 1) {
4707 struct net_device *dev1;
4708
ca519274 4709 err = -ENOMEM;
be63a21c 4710 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
ca519274
SH		 4711 if (dev1 && (err = register_netdev(dev1)) == 0)
4712 sky2_show_addr(dev1);
4713 else {
b02a9258
SH		 4714 dev_warn(&pdev->dev,
4715 "register of second port failed (%d)\n", err);
cd28ab6a 4716 hw->dev[1] = NULL;
ca519274
SH		 4717 hw->ports = 1;
4718 if (dev1)
4719 free_netdev(dev1);
4720 }
cd28ab6a
SH		 4721 }
4722
32c2c300 4723 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4724 INIT_WORK(&hw->restart_work, sky2_restart);
4725
793b883e 4726 pci_set_drvdata(pdev, hw);
1ae861e6 4727 pdev->d3_delay = 150;
793b883e 4728
cd28ab6a
SH		 4729 return 0;
4730
793b883e 4731err_out_unregister:
ea76e635 4732 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4733 pci_disable_msi(pdev);
793b883e 4734 unregister_netdev(dev);
cd28ab6a
SH		 4735err_out_free_netdev:
4736 free_netdev(dev);
cd28ab6a 4737err_out_free_pci:
793b883e 4738 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4739 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4740err_out_iounmap:
4741 iounmap(hw->regs);
4742err_out_free_hw:
4743 kfree(hw);
4744err_out_free_regions:
4745 pci_release_regions(pdev);
44a1d2e5 4746err_out_disable:
cd28ab6a 4747 pci_disable_device(pdev);
cd28ab6a 4748err_out:
549a68c3 4749 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4750 return err;
4751}
4752
4753static void __devexit sky2_remove(struct pci_dev *pdev)
4754{
793b883e 4755 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4756 int i;
cd28ab6a 4757
793b883e 4758 if (!hw)
cd28ab6a
SH		 4759 return;
4760
32c2c300 4761 del_timer_sync(&hw->watchdog_timer);
6de16237 4762 cancel_work_sync(&hw->restart_work);
d27ed387 4763
b877fe28 4764 for (i = hw->ports-1; i >= 0; --i)
6de16237 4765 unregister_netdev(hw->dev[i]);
81906791 4766
d27ed387 4767 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4768
ae306cca
SH		 4769 sky2_power_aux(hw);
4770
793b883e 4771 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4772 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4773
4774 free_irq(pdev->irq, hw);
ea76e635 4775 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4776 pci_disable_msi(pdev);
793b883e 4777 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4778 pci_release_regions(pdev);
4779 pci_disable_device(pdev);
793b883e 4780
b877fe28 4781 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4782 free_netdev(hw->dev[i]);
4783
cd28ab6a
SH		 4784 iounmap(hw->regs);
4785 kfree(hw);
5afa0a9c 4786
cd28ab6a
SH		 4787 pci_set_drvdata(pdev, NULL);
4788}
4789
cd28ab6a
SH		 4790static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4791{
793b883e 4792 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4793 int i, wol = 0;
cd28ab6a 4794
549a68c3
SH		 4795 if (!hw)
4796 return 0;
4797
063a0b38
SH		 4798 del_timer_sync(&hw->watchdog_timer);
4799 cancel_work_sync(&hw->restart_work);
4800
19720737 4801 rtnl_lock();
f05267e7 4802 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4803 struct net_device *dev = hw->dev[i];
e3173832 4804 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4805
af18d8b8 4806 sky2_detach(dev);
e3173832
SH		 4807
4808 if (sky2->wol)
4809 sky2_wol_init(sky2);
4810
4811 wol |= sky2->wol;
cd28ab6a
SH		 4812 }
4813
5f8ae5c5 4814 device_set_wakeup_enable(&pdev->dev, wol != 0);
4815
8ab8fca2 4816 sky2_write32(hw, B0_IMSK, 0);
6de16237 4817 napi_disable(&hw->napi);
ae306cca 4818 sky2_power_aux(hw);
19720737 4819 rtnl_unlock();
e3173832 4820
d374c1c1 4821 pci_save_state(pdev);
e3173832 4822 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4823 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4824
2ccc99b7 4825 return 0;
cd28ab6a
SH		 4826}
4827
5f8ae5c5 4828#ifdef CONFIG_PM
cd28ab6a
SH		 4829static int sky2_resume(struct pci_dev *pdev)
4830{
793b883e 4831 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4832 int i, err;
cd28ab6a 4833
549a68c3
SH		 4834 if (!hw)
4835 return 0;
4836
f71eb1a2
SH		 4837 err = pci_set_power_state(pdev, PCI_D0);
4838 if (err)
4839 goto out;
ae306cca
SH		 4840
4841 err = pci_restore_state(pdev);
4842 if (err)
4843 goto out;
4844
cd28ab6a 4845 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4846
4847 /* Re-enable all clocks */
a0db28b8 4848 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4849 if (err) {
4850 dev_err(&pdev->dev, "PCI write config failed\n");
4851 goto out;
4852 }
1ad5b4a5 4853
e3173832 4854 sky2_reset(hw);
8ab8fca2 4855 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4856 napi_enable(&hw->napi);
8ab8fca2 4857
af18d8b8 4858 rtnl_lock();
f05267e7 4859 for (i = 0; i < hw->ports; i++) {
af18d8b8
SH		 4860 err = sky2_reattach(hw->dev[i]);
4861 if (err)
4862 goto out;
cd28ab6a 4863 }
af18d8b8 4864 rtnl_unlock();
eb35cf60 4865
ae306cca 4866 return 0;
08c06d8a 4867out:
af18d8b8
SH		 4868 rtnl_unlock();
4869
b02a9258 4870 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4871 pci_disable_device(pdev);
08c06d8a 4872 return err;
cd28ab6a
SH		 4873}
4874#endif
4875
e3173832
SH		 4876static void sky2_shutdown(struct pci_dev *pdev)
4877{
5f8ae5c5 4878 sky2_suspend(pdev, PMSG_SUSPEND);
e3173832
SH		 4879}
4880
cd28ab6a 4881static struct pci_driver sky2_driver = {
793b883e
SH		 4882 .name = DRV_NAME,
4883 .id_table = sky2_id_table,
4884 .probe = sky2_probe,
4885 .remove = __devexit_p(sky2_remove),
cd28ab6a 4886#ifdef CONFIG_PM
793b883e
SH		 4887 .suspend = sky2_suspend,
4888 .resume = sky2_resume,
cd28ab6a 4889#endif
e3173832 4890 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4891};
4892
4893static int __init sky2_init_module(void)
4894{
c844d483
SH		 4895 pr_info(PFX "driver version " DRV_VERSION "\n");
4896
3cf26753 4897 sky2_debug_init();
50241c4c 4898 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4899}
4900
4901static void __exit sky2_cleanup_module(void)
4902{
4903 pci_unregister_driver(&sky2_driver);
3cf26753 4904 sky2_debug_cleanup();
cd28ab6a
SH		 4905}
4906
4907module_init(sky2_init_module);
4908module_exit(sky2_cleanup_module);
4909
4910MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4911MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4912MODULE_LICENSE("GPL");
5f4f9dc1 4913MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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