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drivers/net: const-ify ethtool_ops declarations
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
793b883e 26#include <linux/crc32.h>
cd28ab6a
SH		 27#include <linux/kernel.h>
28#include <linux/version.h>
29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
e981d47b 53#define DRV_VERSION "1.7"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3. A transmit can require several elements;
60 * a receive requires one (or two if using 64 bit dma).
61 */
62
13210ce5 63#define RX_LE_SIZE 512
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
bea86103 65#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 67#define RX_SKB_ALIGN 8
22e11703 68#define RX_BUF_WRITE 16
793b883e
SH		 69
70#define TX_RING_SIZE 512
71#define TX_DEF_PENDING (TX_RING_SIZE - 1)
72#define TX_MIN_PENDING 64
b19666d9 73#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 74
793b883e 75#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 76#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77#define ETH_JUMBO_MTU 9000
78#define TX_WATCHDOG (5 * HZ)
79#define NAPI_WEIGHT 64
80#define PHY_RETRIES 1000
81
cb5d9547
SH		 82#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
cd28ab6a 84static const u32 default_msg =
793b883e
SH		 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 88
793b883e 89static int debug = -1; /* defaults above */
cd28ab6a
SH		 90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
bdb5c58e
SH		 93static int copybreak __read_mostly = 256;
94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
fb2690a9
SH		 97static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
01bd7564
SH		 101static int idle_timeout = 100;
102module_param(idle_timeout, int, 0);
103MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
104
cd28ab6a 105static const struct pci_device_id sky2_id_table[] = {
793b883e 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a 107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
2d2a3871 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
cd28ab6a
SH		 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
2f4a66ad 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) },
cd28ab6a
SH		 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
5f5d83fd 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) },
57fa442c
SH		 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) },
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) },
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) },
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) },
2f4a66ad 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) },
cd28ab6a
SH		 132 { 0 }
133};
793b883e 134
cd28ab6a
SH		 135MODULE_DEVICE_TABLE(pci, sky2_id_table);
136
137/* Avoid conditionals by using array */
138static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
139static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 140static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 141
92f965e8
SH		 142/* This driver supports yukon2 chipset only */
143static const char *yukon2_name[] = {
144 "XL", /* 0xb3 */
145 "EC Ultra", /* 0xb4 */
146 "UNKNOWN", /* 0xb5 */
147 "EC", /* 0xb6 */
148 "FE", /* 0xb7 */
793b883e
SH		 149};
150
793b883e 151/* Access to external PHY */
ef743d33 152static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 153{
154 int i;
155
156 gma_write16(hw, port, GM_SMI_DATA, val);
157 gma_write16(hw, port, GM_SMI_CTRL,
158 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
159
160 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 161 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 162 return 0;
793b883e 163 udelay(1);
cd28ab6a 164 }
ef743d33 165
793b883e 166 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 167 return -ETIMEDOUT;
cd28ab6a
SH		 168}
169
ef743d33 170static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 171{
172 int i;
173
793b883e 174 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 175 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
176
177 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33 178 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
179 *val = gma_read16(hw, port, GM_SMI_DATA);
180 return 0;
181 }
182
793b883e 183 udelay(1);
cd28ab6a
SH		 184 }
185
ef743d33 186 return -ETIMEDOUT;
187}
188
189static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
190{
191 u16 v;
192
193 if (__gm_phy_read(hw, port, reg, &v) != 0)
194 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
195 return v;
cd28ab6a
SH		 196}
197
2ccc99b7 198static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
5afa0a9c 199{
200 u16 power_control;
5afa0a9c 201 int vaux;
5afa0a9c 202
203 pr_debug("sky2_set_power_state %d\n", state);
204 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
205
56a645cc 206 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 207 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c 208 (power_control & PCI_PM_CAP_PME_D3cold);
209
56a645cc 210 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c 211
212 power_control |= PCI_PM_CTRL_PME_STATUS;
213 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
214
215 switch (state) {
216 case PCI_D0:
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
220
221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
223
224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 else
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
232
977bdf06 233 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
d3bcfbeb 234 u32 reg1;
235
56a645cc
SH		 236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
237 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 238 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 239 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
240 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 241 }
242
5afa0a9c 243 break;
244
245 case PCI_D3hot:
246 case PCI_D3cold:
5afa0a9c 247 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
248 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
249 else
250 /* enable bits are inverted */
251 sky2_write8(hw, B2_Y2_CLK_GATE,
252 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
253 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
254 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
255
256 /* switch power to VAUX */
257 if (vaux && state != PCI_D3cold)
258 sky2_write8(hw, B0_POWER_CTRL,
259 (PC_VAUX_ENA | PC_VCC_ENA |
260 PC_VAUX_ON | PC_VCC_OFF));
261 break;
262 default:
263 printk(KERN_ERR PFX "Unknown power state %d\n", state);
5afa0a9c 264 }
265
56a645cc 266 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c 267 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
5afa0a9c 268}
269
d3bcfbeb 270static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 271{
272 u16 reg;
273
274 /* disable all GMAC IRQ's */
275 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
276 /* disable PHY IRQs */
277 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 278
cd28ab6a
SH		 279 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
280 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
281 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
282 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
283
284 reg = gma_read16(hw, port, GM_RX_CTRL);
285 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
286 gma_write16(hw, port, GM_RX_CTRL, reg);
287}
288
289static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
290{
291 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 292 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 293
ed6d32c7 294 if (sky2->autoneg == AUTONEG_ENABLE &&
86a31a75 295 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 296 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
297
298 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 299 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 300 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
301
302 if (hw->chip_id == CHIP_ID_YUKON_EC)
303 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
304 else
305 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
306
307 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
308 }
309
310 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 311 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 312 if (hw->chip_id == CHIP_ID_YUKON_FE) {
313 /* enable automatic crossover */
314 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
315 } else {
316 /* disable energy detect */
317 ctrl &= ~PHY_M_PC_EN_DET_MSK;
318
319 /* enable automatic crossover */
320 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
321
322 if (sky2->autoneg == AUTONEG_ENABLE &&
ed6d32c7 323 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 324 ctrl &= ~PHY_M_PC_DSC_MSK;
325 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
326 }
327 }
cd28ab6a
SH		 328 } else {
329 /* workaround for deviation #4.88 (CRC errors) */
330 /* disable Automatic Crossover */
331
332 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 333 }
cd28ab6a 334
b89165f2
SH		 335 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
336
337 /* special setup for PHY 88E1112 Fiber */
338 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
339 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 340
b89165f2
SH		 341 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
342 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
344 ctrl &= ~PHY_M_MAC_MD_MSK;
345 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
346 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
347
348 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 349 /* select page 1 to access Fiber registers */
350 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 351
352 /* for SFP-module set SIGDET polarity to low */
353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
354 ctrl |= PHY_M_FIB_SIGD_POL;
355 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
cd28ab6a 356 }
b89165f2
SH		 357
358 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 359 }
360
361 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
362 if (sky2->autoneg == AUTONEG_DISABLE)
363 ctrl &= ~PHY_CT_ANE;
364 else
365 ctrl |= PHY_CT_ANE;
366
367 ctrl |= PHY_CT_RESET;
368 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
369
370 ctrl = 0;
371 ct1000 = 0;
372 adv = PHY_AN_CSMA;
2eaba1a2 373 reg = 0;
cd28ab6a
SH		 374
375 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 376 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 377 if (sky2->advertising & ADVERTISED_1000baseT_Full)
378 ct1000 |= PHY_M_1000C_AFD;
379 if (sky2->advertising & ADVERTISED_1000baseT_Half)
380 ct1000 |= PHY_M_1000C_AHD;
381 if (sky2->advertising & ADVERTISED_100baseT_Full)
382 adv |= PHY_M_AN_100_FD;
383 if (sky2->advertising & ADVERTISED_100baseT_Half)
384 adv |= PHY_M_AN_100_HD;
385 if (sky2->advertising & ADVERTISED_10baseT_Full)
386 adv |= PHY_M_AN_10_FD;
387 if (sky2->advertising & ADVERTISED_10baseT_Half)
388 adv |= PHY_M_AN_10_HD;
b89165f2
SH		 389 } else { /* special defines for FIBER (88E1040S only) */
390 if (sky2->advertising & ADVERTISED_1000baseT_Full)
391 adv |= PHY_M_AN_1000X_AFD;
392 if (sky2->advertising & ADVERTISED_1000baseT_Half)
393 adv |= PHY_M_AN_1000X_AHD;
394 }
cd28ab6a
SH		 395
396 /* Set Flow-control capabilities */
397 if (sky2->tx_pause && sky2->rx_pause)
793b883e 398 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 399 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 400 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 401 else if (!sky2->rx_pause && sky2->tx_pause)
402 adv |= PHY_AN_PAUSE_ASYM; /* local */
403
404 /* Restart Auto-negotiation */
405 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
406 } else {
407 /* forced speed/duplex settings */
408 ct1000 = PHY_M_1000C_MSE;
409
2eaba1a2
SH		 410 /* Disable auto update for duplex flow control and speed */
411 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 412
413 switch (sky2->speed) {
414 case SPEED_1000:
415 ctrl |= PHY_CT_SP1000;
2eaba1a2 416 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 417 break;
418 case SPEED_100:
419 ctrl |= PHY_CT_SP100;
2eaba1a2 420 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 421 break;
422 }
423
2eaba1a2
SH		 424 if (sky2->duplex == DUPLEX_FULL) {
425 reg |= GM_GPCR_DUP_FULL;
426 ctrl |= PHY_CT_DUP_MD;
427 } else if (sky2->speed != SPEED_1000 && hw->chip_id != CHIP_ID_YUKON_EC_U) {
428 /* Turn off flow control for 10/100mbps */
429 sky2->rx_pause = 0;
430 sky2->tx_pause = 0;
431 }
432
433 if (!sky2->rx_pause)
434 reg |= GM_GPCR_FC_RX_DIS;
435
436 if (!sky2->tx_pause)
437 reg |= GM_GPCR_FC_TX_DIS;
438
439 /* Forward pause packets to GMAC? */
440 if (sky2->tx_pause || sky2->rx_pause)
441 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
442 else
443 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
444
cd28ab6a
SH		 445 ctrl |= PHY_CT_RESET;
446 }
447
2eaba1a2
SH		 448 gma_write16(hw, port, GM_GP_CTRL, reg);
449
cd28ab6a
SH		 450 if (hw->chip_id != CHIP_ID_YUKON_FE)
451 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
452
453 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
454 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
455
456 /* Setup Phy LED's */
457 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
458 ledover = 0;
459
460 switch (hw->chip_id) {
461 case CHIP_ID_YUKON_FE:
462 /* on 88E3082 these bits are at 11..9 (shifted left) */
463 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
464
465 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
466
467 /* delete ACT LED control bits */
468 ctrl &= ~PHY_M_FELP_LED1_MSK;
469 /* change ACT LED control to blink mode */
470 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
471 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
472 break;
473
474 case CHIP_ID_YUKON_XL:
793b883e 475 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 476
477 /* select page 3 to access LED control register */
478 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
479
480 /* set LED Function Control register */
ed6d32c7
SH		 481 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
482 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
483 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
484 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
485 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 486
487 /* set Polarity Control register */
488 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 489 (PHY_M_POLC_LS1_P_MIX(4) |
490 PHY_M_POLC_IS0_P_MIX(4) |
491 PHY_M_POLC_LOS_CTRL(2) |
492 PHY_M_POLC_INIT_CTRL(2) |
493 PHY_M_POLC_STA1_CTRL(2) |
494 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 495
496 /* restore page register */
793b883e 497 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 498 break;
ed6d32c7
SH		 499 case CHIP_ID_YUKON_EC_U:
500 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
501
502 /* select page 3 to access LED control register */
503 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
504
505 /* set LED Function Control register */
506 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
507 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
508 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
509 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
510 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
511
512 /* set Blink Rate in LED Timer Control Register */
513 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
514 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
515 /* restore page register */
516 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
517 break;
cd28ab6a
SH		 518
519 default:
520 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
521 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
522 /* turn off the Rx LED (LED_RX) */
523 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
524 }
525
ed6d32c7 526 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 527 /* apply fixes in PHY AFE */
ed6d32c7
SH		 528 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
529 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
530
977bdf06 531 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 532 gm_phy_write(hw, port, 0x18, 0xaa99);
533 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 534
977bdf06 535 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 536 gm_phy_write(hw, port, 0x18, 0xa204);
537 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 538
539 /* set page register to 0 */
ed6d32c7 540 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
977bdf06
SH		 541 } else {
542 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 543
977bdf06
SH		 544 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
545 /* turn on 100 Mbps LED (LED_LINK100) */
546 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
547 }
cd28ab6a 548
977bdf06
SH		 549 if (ledover)
550 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
551
552 }
2eaba1a2 553
d571b694 554 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 555 if (sky2->autoneg == AUTONEG_ENABLE)
556 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
557 else
558 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
559}
560
d3bcfbeb 561static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
562{
563 u32 reg1;
564 static const u32 phy_power[]
565 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
566
567 /* looks like this XL is back asswards .. */
568 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
569 onoff = !onoff;
570
571 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
572
573 if (onoff)
574 /* Turn off phy power saving */
575 reg1 &= ~phy_power[port];
576 else
577 reg1 |= phy_power[port];
578
579 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 580 sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb 581 udelay(100);
582}
583
1b537565
SH		 584/* Force a renegotiation */
585static void sky2_phy_reinit(struct sky2_port *sky2)
586{
e07b1aa8 587 spin_lock_bh(&sky2->phy_lock);
1b537565 588 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 589 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 590}
591
cd28ab6a
SH		 592static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
593{
594 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
595 u16 reg;
596 int i;
597 const u8 *addr = hw->dev[port]->dev_addr;
598
42eeea01 599 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
600 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 601
602 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
603
793b883e 604 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 605 /* WA DEV_472 -- looks like crossed wires on port 2 */
606 /* clear GMAC 1 Control reset */
607 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
608 do {
609 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
610 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
611 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
612 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
613 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
614 }
615
793b883e 616 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 617
2eaba1a2
SH		 618 /* Enable Transmit FIFO Underrun */
619 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
620
e07b1aa8 621 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 622 sky2_phy_init(hw, port);
e07b1aa8 623 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 624
625 /* MIB clear */
626 reg = gma_read16(hw, port, GM_PHY_ADDR);
627 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
628
43f2f104
SH		 629 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
630 gma_read16(hw, port, i);
cd28ab6a
SH		 631 gma_write16(hw, port, GM_PHY_ADDR, reg);
632
633 /* transmit control */
634 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
635
636 /* receive control reg: unicast + multicast + no FCS */
637 gma_write16(hw, port, GM_RX_CTRL,
793b883e 638 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 639
640 /* transmit flow control */
641 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
642
643 /* transmit parameter */
644 gma_write16(hw, port, GM_TX_PARAM,
645 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
646 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
647 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
648 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
649
650 /* serial mode register */
651 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 652 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 653
6b1a3aef 654 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 655 reg |= GM_SMOD_JUMBO_ENA;
656
657 gma_write16(hw, port, GM_SERIAL_MODE, reg);
658
cd28ab6a
SH		 659 /* virtual address for data */
660 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
661
793b883e
SH		 662 /* physical address: used for pause frames */
663 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
664
665 /* ignore counter overflows */
cd28ab6a
SH		 666 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
667 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
668 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
669
670 /* Configure Rx MAC FIFO */
671 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 672 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
673 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 674
d571b694 675 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 676 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 677
793b883e
SH		 678 /* Set threshold to 0xa (64 bytes)
679 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 680 */
681 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
682
683 /* Configure Tx MAC FIFO */
684 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
685 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 686
687 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
688 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
689 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
690 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
691 /* set Tx GMAC FIFO Almost Empty Threshold */
692 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
693 /* Disable Store & Forward mode for TX */
694 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
695 }
696 }
697
cd28ab6a
SH		 698}
699
1c28f6ba
SH		 700/* Assign Ram Buffer allocation.
701 * start and end are in units of 4k bytes
702 * ram registers are in units of 64bit words
703 */
704static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
cd28ab6a 705{
1c28f6ba 706 u32 start, end;
cd28ab6a 707
1c28f6ba
SH		 708 start = startk * 4096/8;
709 end = (endk * 4096/8) - 1;
793b883e 710
cd28ab6a
SH		 711 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
712 sky2_write32(hw, RB_ADDR(q, RB_START), start);
713 sky2_write32(hw, RB_ADDR(q, RB_END), end);
714 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
715 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
716
717 if (q == Q_R1 || q == Q_R2) {
1c28f6ba
SH		 718 u32 space = (endk - startk) * 4096/8;
719 u32 tp = space - space/4;
793b883e 720
1c28f6ba
SH		 721 /* On receive queue's set the thresholds
722 * give receiver priority when > 3/4 full
723 * send pause when down to 2K
724 */
725 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
726 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 727
1c28f6ba
SH		 728 tp = space - 2048/8;
729 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
730 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 731 } else {
732 /* Enable store & forward on Tx queue's because
733 * Tx FIFO is only 1K on Yukon
734 */
735 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
736 }
737
738 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 739 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 740}
741
cd28ab6a 742/* Setup Bus Memory Interface */
af4ed7e6 743static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 744{
745 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
746 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
747 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 748 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 749}
750
cd28ab6a
SH		 751/* Setup prefetch unit registers. This is the interface between
752 * hardware and driver list elements
753 */
8cc048e3 754static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 755 u64 addr, u32 last)
756{
cd28ab6a
SH		 757 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
758 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
759 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
760 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
761 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
762 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 763
764 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 765}
766
793b883e
SH		 767static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
768{
769 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
770
cb5d9547 771 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
793b883e
SH		 772 return le;
773}
cd28ab6a 774
290d4de5
SH		 775/* Update chip's next pointer */
776static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 777{
98232f85 778 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
762c2de2 779 wmb();
98232f85 780 sky2_write16(hw, q, idx);
781 sky2_read16(hw, q);
cd28ab6a
SH		 782}
783
793b883e 784
cd28ab6a
SH		 785static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
786{
787 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 788 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
cd28ab6a
SH		 789 return le;
790}
791
a018e330 792/* Return high part of DMA address (could be 32 or 64 bit) */
793static inline u32 high32(dma_addr_t a)
794{
a036119f 795 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330 796}
797
793b883e 798/* Build description to hardware about buffer */
28bd181a 799static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
cd28ab6a
SH		 800{
801 struct sky2_rx_le *le;
734d1868
SH		 802 u32 hi = high32(map);
803 u16 len = sky2->rx_bufsize;
cd28ab6a 804
793b883e 805 if (sky2->rx_addr64 != hi) {
cd28ab6a 806 le = sky2_next_rx(sky2);
793b883e 807 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 808 le->ctrl = 0;
809 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 810 sky2->rx_addr64 = high32(map + len);
cd28ab6a 811 }
793b883e 812
cd28ab6a 813 le = sky2_next_rx(sky2);
734d1868
SH		 814 le->addr = cpu_to_le32((u32) map);
815 le->length = cpu_to_le16(len);
cd28ab6a
SH		 816 le->ctrl = 0;
817 le->opcode = OP_PACKET | HW_OWNER;
818}
819
793b883e 820
cd28ab6a
SH		 821/* Tell chip where to start receive checksum.
822 * Actually has two checksums, but set both same to avoid possible byte
823 * order problems.
824 */
793b883e 825static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 826{
827 struct sky2_rx_le *le;
828
cd28ab6a 829 le = sky2_next_rx(sky2);
f65b138c 830 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
cd28ab6a
SH		 831 le->ctrl = 0;
832 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 833
793b883e
SH		 834 sky2_write32(sky2->hw,
835 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
836 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 837
838}
839
6b1a3aef 840/*
841 * The RX Stop command will not work for Yukon-2 if the BMU does not
842 * reach the end of packet and since we can't make sure that we have
843 * incoming data, we must reset the BMU while it is not doing a DMA
844 * transfer. Since it is possible that the RX path is still active,
845 * the RX RAM buffer will be stopped first, so any possible incoming
846 * data will not trigger a DMA. After the RAM buffer is stopped, the
847 * BMU is polled until any DMA in progress is ended and only then it
848 * will be reset.
849 */
850static void sky2_rx_stop(struct sky2_port *sky2)
851{
852 struct sky2_hw *hw = sky2->hw;
853 unsigned rxq = rxqaddr[sky2->port];
854 int i;
855
856 /* disable the RAM Buffer receive queue */
857 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
858
859 for (i = 0; i < 0xffff; i++)
860 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
861 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
862 goto stopped;
863
864 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
865 sky2->netdev->name);
866stopped:
867 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
868
869 /* reset the Rx prefetch unit */
870 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
871}
793b883e 872
d571b694 873/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 874static void sky2_rx_clean(struct sky2_port *sky2)
875{
876 unsigned i;
877
878 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 879 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 880 struct ring_info *re = sky2->rx_ring + i;
881
882 if (re->skb) {
793b883e 883 pci_unmap_single(sky2->hw->pdev,
734d1868 884 re->mapaddr, sky2->rx_bufsize,
cd28ab6a
SH		 885 PCI_DMA_FROMDEVICE);
886 kfree_skb(re->skb);
887 re->skb = NULL;
888 }
889 }
890}
891
ef743d33 892/* Basic MII support */
893static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
894{
895 struct mii_ioctl_data *data = if_mii(ifr);
896 struct sky2_port *sky2 = netdev_priv(dev);
897 struct sky2_hw *hw = sky2->hw;
898 int err = -EOPNOTSUPP;
899
900 if (!netif_running(dev))
901 return -ENODEV; /* Phy still in reset */
902
d89e1343 903 switch (cmd) {
ef743d33 904 case SIOCGMIIPHY:
905 data->phy_id = PHY_ADDR_MARV;
906
907 /* fallthru */
908 case SIOCGMIIREG: {
909 u16 val = 0;
91c86df5 910
e07b1aa8 911 spin_lock_bh(&sky2->phy_lock);
ef743d33 912 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 913 spin_unlock_bh(&sky2->phy_lock);
91c86df5 914
ef743d33 915 data->val_out = val;
916 break;
917 }
918
919 case SIOCSMIIREG:
920 if (!capable(CAP_NET_ADMIN))
921 return -EPERM;
922
e07b1aa8 923 spin_lock_bh(&sky2->phy_lock);
ef743d33 924 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
925 data->val_in);
e07b1aa8 926 spin_unlock_bh(&sky2->phy_lock);
ef743d33 927 break;
928 }
929 return err;
930}
931
d1f13708 932#ifdef SKY2_VLAN_TAG_USED
933static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
934{
935 struct sky2_port *sky2 = netdev_priv(dev);
936 struct sky2_hw *hw = sky2->hw;
937 u16 port = sky2->port;
d1f13708 938
302d1252 939 spin_lock_bh(&sky2->tx_lock);
d1f13708 940
941 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
942 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
943 sky2->vlgrp = grp;
944
302d1252 945 spin_unlock_bh(&sky2->tx_lock);
d1f13708 946}
947
948static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
949{
950 struct sky2_port *sky2 = netdev_priv(dev);
951 struct sky2_hw *hw = sky2->hw;
952 u16 port = sky2->port;
d1f13708 953
302d1252 954 spin_lock_bh(&sky2->tx_lock);
d1f13708 955
956 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
957 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
958 if (sky2->vlgrp)
959 sky2->vlgrp->vlan_devices[vid] = NULL;
960
302d1252 961 spin_unlock_bh(&sky2->tx_lock);
d1f13708 962}
963#endif
964
82788c7a
SH		 965/*
966 * It appears the hardware has a bug in the FIFO logic that
967 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86 968 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
969 * aligned except if slab debugging is enabled.
82788c7a 970 */
497d7c86 971static inline struct sk_buff *sky2_alloc_skb(struct net_device *dev,
972 unsigned int length,
973 gfp_t gfp_mask)
82788c7a
SH		 974{
975 struct sk_buff *skb;
976
497d7c86 977 skb = __netdev_alloc_skb(dev, length + RX_SKB_ALIGN, gfp_mask);
82788c7a
SH		 978 if (likely(skb)) {
979 unsigned long p = (unsigned long) skb->data;
4a15d56f 980 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
82788c7a
SH		 981 }
982
983 return skb;
984}
985
cd28ab6a
SH		 986/*
987 * Allocate and setup receiver buffer pool.
988 * In case of 64 bit dma, there are 2X as many list elements
989 * available as ring entries
990 * and need to reserve one list element so we don't wrap around.
991 */
6b1a3aef 992static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 993{
6b1a3aef 994 struct sky2_hw *hw = sky2->hw;
6b1a3aef 995 unsigned rxq = rxqaddr[sky2->port];
996 int i;
a1433ac4 997 unsigned thresh;
cd28ab6a 998
6b1a3aef 999 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1000 sky2_qset(hw, rxq);
977bdf06
SH		 1001
1002 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
1003 /* MAC Rx RAM Read is controlled by hardware */
1004 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1005 }
1006
6b1a3aef 1007 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1008
1009 rx_set_checksum(sky2);
793b883e 1010 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 1011 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 1012
497d7c86 1013 re->skb = sky2_alloc_skb(sky2->netdev, sky2->rx_bufsize,
1014 GFP_KERNEL);
cd28ab6a
SH		 1015 if (!re->skb)
1016 goto nomem;
1017
6b1a3aef 1018 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
734d1868
SH		 1019 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1020 sky2_rx_add(sky2, re->mapaddr);
cd28ab6a
SH		 1021 }
1022
a1433ac4
SH		 1023
1024 /*
1025 * The receiver hangs if it receives frames larger than the
1026 * packet buffer. As a workaround, truncate oversize frames, but
1027 * the register is limited to 9 bits, so if you do frames > 2052
1028 * you better get the MTU right!
1029 */
1030 thresh = (sky2->rx_bufsize - 8) / sizeof(u32);
1031 if (thresh > 0x1ff)
1032 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1033 else {
1034 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1035 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1036 }
1037
70f1be48 1038
6b1a3aef 1039 /* Tell chip about available buffers */
1040 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1041 return 0;
1042nomem:
1043 sky2_rx_clean(sky2);
1044 return -ENOMEM;
1045}
1046
1047/* Bring up network interface. */
1048static int sky2_up(struct net_device *dev)
1049{
1050 struct sky2_port *sky2 = netdev_priv(dev);
1051 struct sky2_hw *hw = sky2->hw;
1052 unsigned port = sky2->port;
e07b1aa8 1053 u32 ramsize, rxspace, imask;
ee7abb04 1054 int cap, err = -ENOMEM;
843a46f4 1055 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1056
ee7abb04
SH		 1057 /*
1058 * On dual port PCI-X card, there is an problem where status
1059 * can be received out of order due to split transactions
843a46f4 1060 */
ee7abb04
SH		 1061 if (otherdev && netif_running(otherdev) &&
1062 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1063 struct sky2_port *osky2 = netdev_priv(otherdev);
1064 u16 cmd;
1065
1066 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1067 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1068 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1069
1070 sky2->rx_csum = 0;
1071 osky2->rx_csum = 0;
1072 }
843a46f4 1073
cd28ab6a
SH		 1074 if (netif_msg_ifup(sky2))
1075 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1076
1077 /* must be power of 2 */
1078 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1079 TX_RING_SIZE *
1080 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1081 &sky2->tx_le_map);
1082 if (!sky2->tx_le)
1083 goto err_out;
1084
6cdbbdf3 1085 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1086 GFP_KERNEL);
1087 if (!sky2->tx_ring)
1088 goto err_out;
1089 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1090
1091 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1092 &sky2->rx_le_map);
1093 if (!sky2->rx_le)
1094 goto err_out;
1095 memset(sky2->rx_le, 0, RX_LE_BYTES);
1096
6cdbbdf3 1097 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
cd28ab6a
SH		 1098 GFP_KERNEL);
1099 if (!sky2->rx_ring)
1100 goto err_out;
1101
d3bcfbeb 1102 sky2_phy_power(hw, port, 1);
1103
cd28ab6a
SH		 1104 sky2_mac_init(hw, port);
1105
1c28f6ba
SH		 1106 /* Determine available ram buffer space (in 4K blocks).
1107 * Note: not sure about the FE setting below yet
1108 */
1109 if (hw->chip_id == CHIP_ID_YUKON_FE)
1110 ramsize = 4;
1111 else
1112 ramsize = sky2_read8(hw, B2_E_0);
1113
1114 /* Give transmitter one third (rounded up) */
1115 rxspace = ramsize - (ramsize + 2) / 3;
cd28ab6a 1116
cd28ab6a 1117 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1c28f6ba 1118 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
cd28ab6a 1119
793b883e
SH		 1120 /* Make sure SyncQ is disabled */
1121 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1122 RB_RST_SET);
1123
af4ed7e6 1124 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1125
977bdf06
SH		 1126 /* Set almost empty threshold */
1127 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1128 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1129
6b1a3aef 1130 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1131 TX_RING_SIZE - 1);
cd28ab6a 1132
6b1a3aef 1133 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1134 if (err)
1135 goto err_out;
1136
cd28ab6a 1137 /* Enable interrupts from phy/mac for port */
e07b1aa8 1138 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1139 imask |= portirq_msk[port];
e07b1aa8
SH		 1140 sky2_write32(hw, B0_IMSK, imask);
1141
cd28ab6a
SH		 1142 return 0;
1143
1144err_out:
1b537565 1145 if (sky2->rx_le) {
cd28ab6a
SH		 1146 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1147 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1148 sky2->rx_le = NULL;
1149 }
1150 if (sky2->tx_le) {
cd28ab6a
SH		 1151 pci_free_consistent(hw->pdev,
1152 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1153 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1154 sky2->tx_le = NULL;
1155 }
1156 kfree(sky2->tx_ring);
1157 kfree(sky2->rx_ring);
cd28ab6a 1158
1b537565
SH		 1159 sky2->tx_ring = NULL;
1160 sky2->rx_ring = NULL;
cd28ab6a
SH		 1161 return err;
1162}
1163
793b883e
SH		 1164/* Modular subtraction in ring */
1165static inline int tx_dist(unsigned tail, unsigned head)
1166{
cb5d9547 1167 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1168}
cd28ab6a 1169
793b883e
SH		 1170/* Number of list elements available for next tx */
1171static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1172{
793b883e 1173 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1174}
1175
793b883e 1176/* Estimate of number of transmit list elements required */
28bd181a 1177static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1178{
793b883e
SH		 1179 unsigned count;
1180
1181 count = sizeof(dma_addr_t) / sizeof(u32);
1182 count += skb_shinfo(skb)->nr_frags * count;
1183
89114afd 1184 if (skb_is_gso(skb))
793b883e
SH		 1185 ++count;
1186
0e3ff6aa 1187 if (skb->ip_summed == CHECKSUM_HW)
793b883e
SH		 1188 ++count;
1189
1190 return count;
cd28ab6a
SH		 1191}
1192
793b883e
SH		 1193/*
1194 * Put one packet in ring for transmit.
1195 * A single packet can generate multiple list elements, and
1196 * the number of ring elements will probably be less than the number
1197 * of list elements used.
f2e46561
SH		 1198 *
1199 * No BH disabling for tx_lock here (like tg3)
793b883e 1200 */
cd28ab6a
SH		 1201static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1202{
1203 struct sky2_port *sky2 = netdev_priv(dev);
1204 struct sky2_hw *hw = sky2->hw;
d1f13708 1205 struct sky2_tx_le *le = NULL;
6cdbbdf3 1206 struct tx_ring_info *re;
cd28ab6a
SH		 1207 unsigned i, len;
1208 dma_addr_t mapping;
1209 u32 addr64;
1210 u16 mss;
1211 u8 ctrl;
1212
302d1252
SH		 1213 /* No BH disabling for tx_lock here. We are running in BH disabled
1214 * context and TX reclaim runs via poll inside of a software
1215 * interrupt, and no related locks in IRQ processing.
1216 */
f2e46561 1217 if (!spin_trylock(&sky2->tx_lock))
cd28ab6a
SH		 1218 return NETDEV_TX_LOCKED;
1219
793b883e 1220 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
8c463ef7
SH		 1221 /* There is a known but harmless race with lockless tx
1222 * and netif_stop_queue.
1223 */
1224 if (!netif_queue_stopped(dev)) {
1225 netif_stop_queue(dev);
3be92a70
SH		 1226 if (net_ratelimit())
1227 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1228 dev->name);
8c463ef7 1229 }
f2e46561 1230 spin_unlock(&sky2->tx_lock);
cd28ab6a 1231
cd28ab6a
SH		 1232 return NETDEV_TX_BUSY;
1233 }
1234
793b883e 1235 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1236 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1237 dev->name, sky2->tx_prod, skb->len);
1238
cd28ab6a
SH		 1239 len = skb_headlen(skb);
1240 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1241 addr64 = high32(mapping);
793b883e
SH		 1242
1243 re = sky2->tx_ring + sky2->tx_prod;
1244
a018e330 1245 /* Send high bits if changed or crosses boundary */
1246 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1247 le = get_tx_le(sky2);
f65b138c 1248 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1249 le->ctrl = 0;
1250 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1251 sky2->tx_addr64 = high32(mapping + len);
793b883e 1252 }
cd28ab6a
SH		 1253
1254 /* Check for TCP Segmentation Offload */
7967168c 1255 mss = skb_shinfo(skb)->gso_size;
793b883e 1256 if (mss != 0) {
cd28ab6a
SH		 1257 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1258 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1259 mss += ETH_HLEN;
1260
e07560cd 1261 if (mss != sky2->tx_last_mss) {
1262 le = get_tx_le(sky2);
f65b138c 1263 le->addr = cpu_to_le32(mss);
e07560cd 1264 le->opcode = OP_LRGLEN | HW_OWNER;
1265 le->ctrl = 0;
1266 sky2->tx_last_mss = mss;
1267 }
cd28ab6a
SH		 1268 }
1269
cd28ab6a 1270 ctrl = 0;
d1f13708 1271#ifdef SKY2_VLAN_TAG_USED
1272 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1273 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1274 if (!le) {
1275 le = get_tx_le(sky2);
f65b138c 1276 le->addr = 0;
d1f13708 1277 le->opcode = OP_VLAN|HW_OWNER;
1278 le->ctrl = 0;
1279 } else
1280 le->opcode |= OP_VLAN;
1281 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1282 ctrl |= INS_VLAN;
1283 }
1284#endif
1285
1286 /* Handle TCP checksum offload */
cd28ab6a 1287 if (skb->ip_summed == CHECKSUM_HW) {
f65b138c
SH		 1288 unsigned offset = skb->h.raw - skb->data;
1289 u32 tcpsum;
1290
1291 tcpsum = offset << 16; /* sum start */
1292 tcpsum |= offset + skb->csum; /* sum write */
cd28ab6a
SH		 1293
1294 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1295 if (skb->nh.iph->protocol == IPPROTO_UDP)
1296 ctrl |= UDPTCP;
1297
f65b138c
SH		 1298 if (tcpsum != sky2->tx_tcpsum) {
1299 sky2->tx_tcpsum = tcpsum;
1d179332 1300
1301 le = get_tx_le(sky2);
f65b138c 1302 le->addr = cpu_to_le32(tcpsum);
1d179332 1303 le->length = 0; /* initial checksum value */
1304 le->ctrl = 1; /* one packet */
1305 le->opcode = OP_TCPLISW | HW_OWNER;
1306 }
cd28ab6a
SH		 1307 }
1308
1309 le = get_tx_le(sky2);
f65b138c 1310 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1311 le->length = cpu_to_le16(len);
1312 le->ctrl = ctrl;
793b883e 1313 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1314
793b883e 1315 /* Record the transmit mapping info */
cd28ab6a 1316 re->skb = skb;
6cdbbdf3 1317 pci_unmap_addr_set(re, mapaddr, mapping);
cd28ab6a
SH		 1318
1319 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1320 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6cdbbdf3 1321 struct tx_ring_info *fre;
cd28ab6a
SH		 1322
1323 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1324 frag->size, PCI_DMA_TODEVICE);
a036119f 1325 addr64 = high32(mapping);
793b883e
SH		 1326 if (addr64 != sky2->tx_addr64) {
1327 le = get_tx_le(sky2);
f65b138c 1328 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1329 le->ctrl = 0;
1330 le->opcode = OP_ADDR64 | HW_OWNER;
1331 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1332 }
1333
1334 le = get_tx_le(sky2);
f65b138c 1335 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1336 le->length = cpu_to_le16(frag->size);
1337 le->ctrl = ctrl;
793b883e 1338 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1339
793b883e 1340 fre = sky2->tx_ring
e07560cd 1341 + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
6cdbbdf3 1342 pci_unmap_addr_set(fre, mapaddr, mapping);
cd28ab6a 1343 }
6cdbbdf3 1344
793b883e 1345 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1346 le->ctrl |= EOP;
1347
97bda706 1348 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1349 netif_stop_queue(dev);
b19666d9 1350
290d4de5 1351 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1352
f2e46561 1353 spin_unlock(&sky2->tx_lock);
cd28ab6a
SH		 1354
1355 dev->trans_start = jiffies;
1356 return NETDEV_TX_OK;
1357}
1358
cd28ab6a 1359/*
793b883e
SH		 1360 * Free ring elements from starting at tx_cons until "done"
1361 *
1362 * NB: the hardware will tell us about partial completion of multi-part
d571b694 1363 * buffers; these are deferred until completion.
cd28ab6a 1364 */
d11c13e7 1365static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1366{
d11c13e7 1367 struct net_device *dev = sky2->netdev;
af2a58ac
SH		 1368 struct pci_dev *pdev = sky2->hw->pdev;
1369 u16 nxt, put;
793b883e 1370 unsigned i;
cd28ab6a 1371
0e3ff6aa 1372 BUG_ON(done >= TX_RING_SIZE);
2224795d 1373
d11c13e7 1374 if (unlikely(netif_msg_tx_done(sky2)))
d571b694 1375 printk(KERN_DEBUG "%s: tx done, up to %u\n",
d11c13e7 1376 dev->name, done);
cd28ab6a 1377
af2a58ac
SH		 1378 for (put = sky2->tx_cons; put != done; put = nxt) {
1379 struct tx_ring_info *re = sky2->tx_ring + put;
1380 struct sk_buff *skb = re->skb;
cd28ab6a 1381
d89e1343 1382 nxt = re->idx;
af2a58ac 1383 BUG_ON(nxt >= TX_RING_SIZE);
d70cd51a 1384 prefetch(sky2->tx_ring + nxt);
cd28ab6a 1385
793b883e 1386 /* Check for partial status */
af2a58ac
SH		 1387 if (tx_dist(put, done) < tx_dist(put, nxt))
1388 break;
793b883e
SH		 1389
1390 skb = re->skb;
af2a58ac 1391 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
734d1868 1392 skb_headlen(skb), PCI_DMA_TODEVICE);
793b883e
SH		 1393
1394 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6cdbbdf3 1395 struct tx_ring_info *fre;
cb5d9547 1396 fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
af2a58ac 1397 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
d89e1343 1398 skb_shinfo(skb)->frags[i].size,
734d1868 1399 PCI_DMA_TODEVICE);
cd28ab6a
SH		 1400 }
1401
15240072 1402 dev_kfree_skb(skb);
793b883e 1403 }
793b883e 1404
af2a58ac 1405 sky2->tx_cons = put;
22e11703 1406 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1407 netif_wake_queue(dev);
cd28ab6a
SH		 1408}
1409
1410/* Cleanup all untransmitted buffers, assume transmitter not running */
13b97b74 1411static void sky2_tx_clean(struct sky2_port *sky2)
cd28ab6a 1412{
302d1252 1413 spin_lock_bh(&sky2->tx_lock);
d11c13e7 1414 sky2_tx_complete(sky2, sky2->tx_prod);
302d1252 1415 spin_unlock_bh(&sky2->tx_lock);
cd28ab6a
SH		 1416}
1417
1418/* Network shutdown */
1419static int sky2_down(struct net_device *dev)
1420{
1421 struct sky2_port *sky2 = netdev_priv(dev);
1422 struct sky2_hw *hw = sky2->hw;
1423 unsigned port = sky2->port;
1424 u16 ctrl;
e07b1aa8 1425 u32 imask;
cd28ab6a 1426
1b537565
SH		 1427 /* Never really got started! */
1428 if (!sky2->tx_le)
1429 return 0;
1430
cd28ab6a
SH		 1431 if (netif_msg_ifdown(sky2))
1432 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1433
018d1c66 1434 /* Stop more packets from being queued */
cd28ab6a
SH		 1435 netif_stop_queue(dev);
1436
d3bcfbeb 1437 sky2_gmac_reset(hw, port);
793b883e 1438
cd28ab6a
SH		 1439 /* Stop transmitter */
1440 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1441 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1442
1443 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1444 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1445
1446 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1447 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1448 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1449
1450 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1451
1452 /* Workaround shared GMAC reset */
793b883e
SH		 1453 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1454 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1455 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1456
1457 /* Disable Force Sync bit and Enable Alloc bit */
1458 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1459 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1460
1461 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1462 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1463 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1464
1465 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1466 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1467 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1468
1469 /* Reset the Tx prefetch units */
1470 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1471 PREF_UNIT_RST_SET);
1472
1473 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1474
6b1a3aef 1475 sky2_rx_stop(sky2);
cd28ab6a
SH		 1476
1477 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1478 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1479
e07b1aa8
SH		 1480 /* Disable port IRQ */
1481 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1482 imask &= ~portirq_msk[port];
e07b1aa8
SH		 1483 sky2_write32(hw, B0_IMSK, imask);
1484
d3bcfbeb 1485 sky2_phy_power(hw, port, 0);
1486
d571b694 1487 /* turn off LED's */
cd28ab6a
SH		 1488 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1489
018d1c66 1490 synchronize_irq(hw->pdev->irq);
1491
cd28ab6a
SH		 1492 sky2_tx_clean(sky2);
1493 sky2_rx_clean(sky2);
1494
1495 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1496 sky2->rx_le, sky2->rx_le_map);
1497 kfree(sky2->rx_ring);
1498
1499 pci_free_consistent(hw->pdev,
1500 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1501 sky2->tx_le, sky2->tx_le_map);
1502 kfree(sky2->tx_ring);
1503
1b537565
SH		 1504 sky2->tx_le = NULL;
1505 sky2->rx_le = NULL;
1506
1507 sky2->rx_ring = NULL;
1508 sky2->tx_ring = NULL;
1509
cd28ab6a
SH		 1510 return 0;
1511}
1512
1513static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1514{
b89165f2 1515 if (!sky2_is_copper(hw))
793b883e
SH		 1516 return SPEED_1000;
1517
cd28ab6a
SH		 1518 if (hw->chip_id == CHIP_ID_YUKON_FE)
1519 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1520
1521 switch (aux & PHY_M_PS_SPEED_MSK) {
1522 case PHY_M_PS_SPEED_1000:
1523 return SPEED_1000;
1524 case PHY_M_PS_SPEED_100:
1525 return SPEED_100;
1526 default:
1527 return SPEED_10;
1528 }
1529}
1530
1531static void sky2_link_up(struct sky2_port *sky2)
1532{
1533 struct sky2_hw *hw = sky2->hw;
1534 unsigned port = sky2->port;
1535 u16 reg;
1536
cd28ab6a 1537 /* enable Rx/Tx */
2eaba1a2 1538 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1539 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1540 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1541
1542 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1543
1544 netif_carrier_on(sky2->netdev);
1545 netif_wake_queue(sky2->netdev);
1546
1547 /* Turn on link LED */
793b883e 1548 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1549 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1550
ed6d32c7 1551 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
793b883e 1552 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1553 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1554
1555 switch(sky2->speed) {
1556 case SPEED_10:
1557 led |= PHY_M_LEDC_INIT_CTRL(7);
1558 break;
1559
1560 case SPEED_100:
1561 led |= PHY_M_LEDC_STA1_CTRL(7);
1562 break;
1563
1564 case SPEED_1000:
1565 led |= PHY_M_LEDC_STA0_CTRL(7);
1566 break;
1567 }
793b883e
SH		 1568
1569 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1570 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1571 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1572 }
1573
cd28ab6a
SH		 1574 if (netif_msg_link(sky2))
1575 printk(KERN_INFO PFX
d571b694 1576 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1577 sky2->netdev->name, sky2->speed,
1578 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1579 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1580 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1581}
1582
1583static void sky2_link_down(struct sky2_port *sky2)
1584{
1585 struct sky2_hw *hw = sky2->hw;
1586 unsigned port = sky2->port;
1587 u16 reg;
1588
1589 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1590
1591 reg = gma_read16(hw, port, GM_GP_CTRL);
1592 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1593 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1594
1595 if (sky2->rx_pause && !sky2->tx_pause) {
1596 /* restore Asymmetric Pause bit */
1597 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1598 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1599 | PHY_M_AN_ASP);
cd28ab6a
SH		 1600 }
1601
cd28ab6a
SH		 1602 netif_carrier_off(sky2->netdev);
1603 netif_stop_queue(sky2->netdev);
1604
1605 /* Turn on link LED */
1606 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1607
1608 if (netif_msg_link(sky2))
1609 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1610
cd28ab6a
SH		 1611 sky2_phy_init(hw, port);
1612}
1613
793b883e
SH		 1614static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1615{
1616 struct sky2_hw *hw = sky2->hw;
1617 unsigned port = sky2->port;
1618 u16 lpa;
1619
1620 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1621
1622 if (lpa & PHY_M_AN_RF) {
1623 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1624 return -1;
1625 }
1626
1627 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1628 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1629 printk(KERN_ERR PFX "%s: master/slave fault",
1630 sky2->netdev->name);
1631 return -1;
1632 }
1633
1634 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1635 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1636 sky2->netdev->name);
1637 return -1;
1638 }
1639
1640 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1641
1642 sky2->speed = sky2_phy_speed(hw, aux);
1643
1644 /* Pause bits are offset (9..8) */
ed6d32c7 1645 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
793b883e
SH		 1646 aux >>= 6;
1647
1648 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1649 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1650
2eaba1a2
SH		 1651 if (sky2->duplex == DUPLEX_HALF && sky2->speed != SPEED_1000
1652 && hw->chip_id != CHIP_ID_YUKON_EC_U)
1653 sky2->rx_pause = sky2->tx_pause = 0;
1654
1655 if (sky2->rx_pause || sky2->tx_pause)
793b883e
SH		 1656 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1657 else
1658 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1659
1660 return 0;
1661}
cd28ab6a 1662
e07b1aa8
SH		 1663/* Interrupt from PHY */
1664static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1665{
e07b1aa8
SH		 1666 struct net_device *dev = hw->dev[port];
1667 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1668 u16 istatus, phystat;
1669
e07b1aa8
SH		 1670 spin_lock(&sky2->phy_lock);
1671 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1672 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1673
1674 if (!netif_running(dev))
1675 goto out;
cd28ab6a
SH		 1676
1677 if (netif_msg_intr(sky2))
1678 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1679 sky2->netdev->name, istatus, phystat);
1680
2eaba1a2 1681 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1682 if (sky2_autoneg_done(sky2, phystat) == 0)
1683 sky2_link_up(sky2);
1684 goto out;
1685 }
cd28ab6a 1686
793b883e
SH		 1687 if (istatus & PHY_M_IS_LSP_CHANGE)
1688 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1689
793b883e
SH		 1690 if (istatus & PHY_M_IS_DUP_CHANGE)
1691 sky2->duplex =
1692 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1693
793b883e
SH		 1694 if (istatus & PHY_M_IS_LST_CHANGE) {
1695 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1696 sky2_link_up(sky2);
793b883e
SH		 1697 else
1698 sky2_link_down(sky2);
cd28ab6a 1699 }
793b883e 1700out:
e07b1aa8 1701 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1702}
1703
302d1252
SH		 1704
1705/* Transmit timeout is only called if we are running, carries is up
1706 * and tx queue is full (stopped).
1707 */
cd28ab6a
SH		 1708static void sky2_tx_timeout(struct net_device *dev)
1709{
1710 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1711 struct sky2_hw *hw = sky2->hw;
1712 unsigned txq = txqaddr[sky2->port];
8f24664d 1713 u16 report, done;
cd28ab6a
SH		 1714
1715 if (netif_msg_timer(sky2))
1716 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1717
8f24664d
SH		 1718 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1719 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1720
8f24664d
SH		 1721 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1722 dev->name,
1723 sky2->tx_cons, sky2->tx_prod, report, done);
1724
1725 if (report != done) {
1726 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1727
1728 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1729 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1730 } else if (report != sky2->tx_cons) {
1731 printk(KERN_INFO PFX "status report lost?\n");
1732
1733 spin_lock_bh(&sky2->tx_lock);
1734 sky2_tx_complete(sky2, report);
1735 spin_unlock_bh(&sky2->tx_lock);
1736 } else {
1737 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1738
8f24664d
SH		 1739 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1740 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1741
1742 sky2_tx_clean(sky2);
1743
1744 sky2_qset(hw, txq);
1745 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1746 }
cd28ab6a
SH		 1747}
1748
734d1868 1749
70f1be48
SH		 1750/* Want receive buffer size to be multiple of 64 bits
1751 * and incl room for vlan and truncation
1752 */
734d1868
SH		 1753static inline unsigned sky2_buf_size(int mtu)
1754{
4a15d56f 1755 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
734d1868
SH		 1756}
1757
cd28ab6a
SH		 1758static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1759{
6b1a3aef 1760 struct sky2_port *sky2 = netdev_priv(dev);
1761 struct sky2_hw *hw = sky2->hw;
1762 int err;
1763 u16 ctl, mode;
e07b1aa8 1764 u32 imask;
cd28ab6a
SH		 1765
1766 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1767 return -EINVAL;
1768
5a5b1ea0 1769 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1770 return -EINVAL;
1771
6b1a3aef 1772 if (!netif_running(dev)) {
1773 dev->mtu = new_mtu;
1774 return 0;
1775 }
1776
e07b1aa8 1777 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 1778 sky2_write32(hw, B0_IMSK, 0);
1779
018d1c66 1780 dev->trans_start = jiffies; /* prevent tx timeout */
1781 netif_stop_queue(dev);
1782 netif_poll_disable(hw->dev[0]);
1783
e07b1aa8
SH		 1784 synchronize_irq(hw->pdev->irq);
1785
6b1a3aef 1786 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1787 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1788 sky2_rx_stop(sky2);
1789 sky2_rx_clean(sky2);
cd28ab6a
SH		 1790
1791 dev->mtu = new_mtu;
734d1868 1792 sky2->rx_bufsize = sky2_buf_size(new_mtu);
6b1a3aef 1793 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1794 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1795
1796 if (dev->mtu > ETH_DATA_LEN)
1797 mode |= GM_SMOD_JUMBO_ENA;
1798
1799 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1800
6b1a3aef 1801 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1802
6b1a3aef 1803 err = sky2_rx_start(sky2);
e07b1aa8 1804 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1805
1b537565
SH		 1806 if (err)
1807 dev_close(dev);
1808 else {
1809 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1810
1811 netif_poll_enable(hw->dev[0]);
1812 netif_wake_queue(dev);
1813 }
1814
cd28ab6a
SH		 1815 return err;
1816}
1817
1818/*
1819 * Receive one packet.
1820 * For small packets or errors, just reuse existing skb.
d571b694 1821 * For larger packets, get new buffer.
cd28ab6a 1822 */
497d7c86 1823static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 1824 u16 length, u32 status)
1825{
497d7c86 1826 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 1827 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1828 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1829
1830 if (unlikely(netif_msg_rx_status(sky2)))
1831 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 1832 dev->name, sky2->rx_next, status, length);
cd28ab6a 1833
793b883e 1834 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1835 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1836
42eeea01 1837 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1838 goto error;
1839
42eeea01 1840 if (!(status & GMR_FS_RX_OK))
1841 goto resubmit;
1842
497d7c86 1843 if (length > dev->mtu + ETH_HLEN)
6e15b712
SH		 1844 goto oversize;
1845
bdb5c58e 1846 if (length < copybreak) {
497d7c86 1847 skb = netdev_alloc_skb(dev, length + 2);
79e57d32 1848 if (!skb)
793b883e
SH		 1849 goto resubmit;
1850
79e57d32 1851 skb_reserve(skb, 2);
793b883e
SH		 1852 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1853 length, PCI_DMA_FROMDEVICE);
79e57d32 1854 memcpy(skb->data, re->skb->data, length);
d11c13e7 1855 skb->ip_summed = re->skb->ip_summed;
1856 skb->csum = re->skb->csum;
793b883e
SH		 1857 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1858 length, PCI_DMA_FROMDEVICE);
793b883e 1859 } else {
79e57d32
SH		 1860 struct sk_buff *nskb;
1861
497d7c86 1862 nskb = sky2_alloc_skb(dev, sky2->rx_bufsize, GFP_ATOMIC);
793b883e
SH		 1863 if (!nskb)
1864 goto resubmit;
cd28ab6a 1865
793b883e 1866 skb = re->skb;
79e57d32 1867 re->skb = nskb;
793b883e 1868 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
734d1868 1869 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1870 prefetch(skb->data);
cd28ab6a 1871
793b883e 1872 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
734d1868 1873 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1874 }
cd28ab6a 1875
79e57d32 1876 skb_put(skb, length);
793b883e 1877resubmit:
d11c13e7 1878 re->skb->ip_summed = CHECKSUM_NONE;
734d1868 1879 sky2_rx_add(sky2, re->mapaddr);
79e57d32 1880
cd28ab6a
SH		 1881 return skb;
1882
6e15b712
SH		 1883oversize:
1884 ++sky2->net_stats.rx_over_errors;
1885 goto resubmit;
1886
cd28ab6a 1887error:
6e15b712
SH		 1888 ++sky2->net_stats.rx_errors;
1889
3be92a70 1890 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 1891 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 1892 dev->name, status, length);
793b883e
SH		 1893
1894 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1895 sky2->net_stats.rx_length_errors++;
1896 if (status & GMR_FS_FRAGMENT)
1897 sky2->net_stats.rx_frame_errors++;
1898 if (status & GMR_FS_CRC_ERR)
1899 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1900 if (status & GMR_FS_RX_FF_OV)
1901 sky2->net_stats.rx_fifo_errors++;
79e57d32 1902
793b883e 1903 goto resubmit;
cd28ab6a
SH		 1904}
1905
e07b1aa8
SH		 1906/* Transmit complete */
1907static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 1908{
e07b1aa8 1909 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 1910
e07b1aa8
SH		 1911 if (netif_running(dev)) {
1912 spin_lock(&sky2->tx_lock);
1913 sky2_tx_complete(sky2, last);
1914 spin_unlock(&sky2->tx_lock);
2224795d 1915 }
cd28ab6a
SH		 1916}
1917
e07b1aa8
SH		 1918/* Process status response ring */
1919static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 1920{
22e11703 1921 struct sky2_port *sky2;
e07b1aa8 1922 int work_done = 0;
22e11703 1923 unsigned buf_write[2] = { 0, 0 };
e71ebd73 1924 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 1925
af2a58ac 1926 rmb();
bea86103 1927
e71ebd73 1928 while (hw->st_idx != hwidx) {
13210ce5 1929 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1930 struct net_device *dev;
cd28ab6a 1931 struct sk_buff *skb;
cd28ab6a
SH		 1932 u32 status;
1933 u16 length;
1934
cb5d9547 1935 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 1936
e71ebd73
SH		 1937 BUG_ON(le->link >= 2);
1938 dev = hw->dev[le->link];
13210ce5 1939
1940 sky2 = netdev_priv(dev);
f65b138c
SH		 1941 length = le16_to_cpu(le->length);
1942 status = le32_to_cpu(le->status);
cd28ab6a 1943
e71ebd73 1944 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 1945 case OP_RXSTAT:
497d7c86 1946 skb = sky2_receive(dev, length, status);
d1f13708 1947 if (!skb)
1948 break;
13210ce5 1949
13210ce5 1950 skb->protocol = eth_type_trans(skb, dev);
1951 dev->last_rx = jiffies;
1952
d1f13708 1953#ifdef SKY2_VLAN_TAG_USED
1954 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1955 vlan_hwaccel_receive_skb(skb,
1956 sky2->vlgrp,
1957 be16_to_cpu(sky2->rx_tag));
1958 } else
1959#endif
cd28ab6a 1960 netif_receive_skb(skb);
13210ce5 1961
22e11703
SH		 1962 /* Update receiver after 16 frames */
1963 if (++buf_write[le->link] == RX_BUF_WRITE) {
1964 sky2_put_idx(hw, rxqaddr[le->link],
1965 sky2->rx_put);
1966 buf_write[le->link] = 0;
1967 }
1968
1969 /* Stop after net poll weight */
13210ce5 1970 if (++work_done >= to_do)
1971 goto exit_loop;
cd28ab6a
SH		 1972 break;
1973
d1f13708 1974#ifdef SKY2_VLAN_TAG_USED
1975 case OP_RXVLAN:
1976 sky2->rx_tag = length;
1977 break;
1978
1979 case OP_RXCHKSVLAN:
1980 sky2->rx_tag = length;
1981 /* fall through */
1982#endif
cd28ab6a 1983 case OP_RXCHKS:
d11c13e7 1984 skb = sky2->rx_ring[sky2->rx_next].skb;
1985 skb->ip_summed = CHECKSUM_HW;
f65b138c 1986 skb->csum = status & 0xffff;
cd28ab6a
SH		 1987 break;
1988
1989 case OP_TXINDEXLE:
13b97b74 1990 /* TX index reports status for both ports */
f55925d7
SH		 1991 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
1992 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 1993 if (hw->dev[1])
1994 sky2_tx_done(hw->dev[1],
1995 ((status >> 24) & 0xff)
1996 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 1997 break;
1998
cd28ab6a
SH		 1999 default:
2000 if (net_ratelimit())
793b883e 2001 printk(KERN_WARNING PFX
e71ebd73
SH		 2002 "unknown status opcode 0x%x\n", le->opcode);
2003 goto exit_loop;
cd28ab6a 2004 }
13210ce5 2005 }
cd28ab6a 2006
fe2a24df
SH		 2007 /* Fully processed status ring so clear irq */
2008 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2009
13210ce5 2010exit_loop:
22e11703
SH		 2011 if (buf_write[0]) {
2012 sky2 = netdev_priv(hw->dev[0]);
2013 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2014 }
2015
2016 if (buf_write[1]) {
2017 sky2 = netdev_priv(hw->dev[1]);
2018 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2019 }
2020
e07b1aa8 2021 return work_done;
cd28ab6a
SH		 2022}
2023
2024static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2025{
2026 struct net_device *dev = hw->dev[port];
2027
3be92a70
SH		 2028 if (net_ratelimit())
2029 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2030 dev->name, status);
cd28ab6a
SH		 2031
2032 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2033 if (net_ratelimit())
2034 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2035 dev->name);
cd28ab6a
SH		 2036 /* Clear IRQ */
2037 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2038 }
2039
2040 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2041 if (net_ratelimit())
2042 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2043 dev->name);
cd28ab6a
SH		 2044
2045 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2046 }
2047
2048 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2049 if (net_ratelimit())
2050 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2051 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2052 }
2053
2054 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2055 if (net_ratelimit())
2056 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2057 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2058 }
2059
2060 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2061 if (net_ratelimit())
2062 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2063 dev->name);
cd28ab6a
SH		 2064 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2065 }
2066}
2067
2068static void sky2_hw_intr(struct sky2_hw *hw)
2069{
2070 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2071
793b883e 2072 if (status & Y2_IS_TIST_OV)
cd28ab6a 2073 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2074
2075 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2076 u16 pci_err;
2077
56a645cc 2078 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2079 if (net_ratelimit())
2080 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2081 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2082
2083 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2084 sky2_pci_write16(hw, PCI_STATUS,
793b883e 2085 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2086 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2087 }
2088
2089 if (status & Y2_IS_PCI_EXP) {
d571b694 2090 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2091 u32 pex_err;
2092
56a645cc 2093 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2094
3be92a70
SH		 2095 if (net_ratelimit())
2096 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2097 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2098
2099 /* clear the interrupt */
2100 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2101 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
793b883e 2102 0xffffffffUL);
cd28ab6a
SH		 2103 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2104
2105 if (pex_err & PEX_FATAL_ERRORS) {
2106 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2107 hwmsk &= ~Y2_IS_PCI_EXP;
2108 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2109 }
2110 }
2111
2112 if (status & Y2_HWE_L1_MASK)
2113 sky2_hw_error(hw, 0, status);
2114 status >>= 8;
2115 if (status & Y2_HWE_L1_MASK)
2116 sky2_hw_error(hw, 1, status);
2117}
2118
2119static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2120{
2121 struct net_device *dev = hw->dev[port];
2122 struct sky2_port *sky2 = netdev_priv(dev);
2123 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2124
2125 if (netif_msg_intr(sky2))
2126 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2127 dev->name, status);
2128
2129 if (status & GM_IS_RX_FF_OR) {
2130 ++sky2->net_stats.rx_fifo_errors;
2131 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2132 }
2133
2134 if (status & GM_IS_TX_FF_UR) {
2135 ++sky2->net_stats.tx_fifo_errors;
2136 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2137 }
cd28ab6a
SH		 2138}
2139
d257924e
SH		 2140/* This should never happen it is a fatal situation */
2141static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2142 const char *rxtx, u32 mask)
2143{
2144 struct net_device *dev = hw->dev[port];
2145 struct sky2_port *sky2 = netdev_priv(dev);
2146 u32 imask;
2147
2148 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2149 dev ? dev->name : "<not registered>", rxtx);
2150
2151 imask = sky2_read32(hw, B0_IMSK);
2152 imask &= ~mask;
2153 sky2_write32(hw, B0_IMSK, imask);
2154
2155 if (dev) {
2156 spin_lock(&sky2->phy_lock);
2157 sky2_link_down(sky2);
2158 spin_unlock(&sky2->phy_lock);
2159 }
2160}
cd28ab6a 2161
d27ed387
SH		 2162/* If idle then force a fake soft NAPI poll once a second
2163 * to work around cases where sharing an edge triggered interrupt.
2164 */
eb35cf60
SH		 2165static inline void sky2_idle_start(struct sky2_hw *hw)
2166{
2167 if (idle_timeout > 0)
2168 mod_timer(&hw->idle_timer,
2169 jiffies + msecs_to_jiffies(idle_timeout));
2170}
2171
d27ed387
SH		 2172static void sky2_idle(unsigned long arg)
2173{
01bd7564
SH		 2174 struct sky2_hw *hw = (struct sky2_hw *) arg;
2175 struct net_device *dev = hw->dev[0];
d27ed387 2176
d27ed387
SH		 2177 if (__netif_rx_schedule_prep(dev))
2178 __netif_rx_schedule(dev);
01bd7564
SH		 2179
2180 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2181}
2182
2183
e07b1aa8 2184static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2185{
e07b1aa8
SH		 2186 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2187 int work_limit = min(dev0->quota, *budget);
2188 int work_done = 0;
fb2690a9 2189 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2190
1e5f1283
SH		 2191 if (status & Y2_IS_HW_ERR)
2192 sky2_hw_intr(hw);
d257924e 2193
1e5f1283
SH		 2194 if (status & Y2_IS_IRQ_PHY1)
2195 sky2_phy_intr(hw, 0);
cd28ab6a 2196
1e5f1283
SH		 2197 if (status & Y2_IS_IRQ_PHY2)
2198 sky2_phy_intr(hw, 1);
cd28ab6a 2199
1e5f1283
SH		 2200 if (status & Y2_IS_IRQ_MAC1)
2201 sky2_mac_intr(hw, 0);
cd28ab6a 2202
1e5f1283
SH		 2203 if (status & Y2_IS_IRQ_MAC2)
2204 sky2_mac_intr(hw, 1);
cd28ab6a 2205
1e5f1283
SH		 2206 if (status & Y2_IS_CHK_RX1)
2207 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2208
1e5f1283
SH		 2209 if (status & Y2_IS_CHK_RX2)
2210 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2211
1e5f1283
SH		 2212 if (status & Y2_IS_CHK_TXA1)
2213 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2214
1e5f1283
SH		 2215 if (status & Y2_IS_CHK_TXA2)
2216 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2217
1e5f1283 2218 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2219 if (work_done < work_limit) {
2220 netif_rx_complete(dev0);
86fba634 2221
fe2a24df
SH		 2222 sky2_read32(hw, B0_Y2_SP_LISR);
2223 return 0;
2224 } else {
2225 *budget -= work_done;
2226 dev0->quota -= work_done;
1e5f1283 2227 return 1;
fe2a24df 2228 }
e07b1aa8
SH		 2229}
2230
2231static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2232{
2233 struct sky2_hw *hw = dev_id;
2234 struct net_device *dev0 = hw->dev[0];
2235 u32 status;
2236
2237 /* Reading this mask interrupts as side effect */
2238 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2239 if (status == 0 || status == ~0)
2240 return IRQ_NONE;
793b883e 2241
e07b1aa8
SH		 2242 prefetch(&hw->st_le[hw->st_idx]);
2243 if (likely(__netif_rx_schedule_prep(dev0)))
2244 __netif_rx_schedule(dev0);
793b883e 2245
cd28ab6a
SH		 2246 return IRQ_HANDLED;
2247}
2248
2249#ifdef CONFIG_NET_POLL_CONTROLLER
2250static void sky2_netpoll(struct net_device *dev)
2251{
2252 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2253 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2254
88d11360
SH		 2255 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2256 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2257}
2258#endif
2259
2260/* Chip internal frequency for clock calculations */
fb17358f 2261static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2262{
793b883e 2263 switch (hw->chip_id) {
cd28ab6a 2264 case CHIP_ID_YUKON_EC:
5a5b1ea0 2265 case CHIP_ID_YUKON_EC_U:
fb17358f 2266 return 125; /* 125 Mhz */
cd28ab6a 2267 case CHIP_ID_YUKON_FE:
fb17358f 2268 return 100; /* 100 Mhz */
793b883e 2269 default: /* YUKON_XL */
fb17358f 2270 return 156; /* 156 Mhz */
cd28ab6a
SH		 2271 }
2272}
2273
fb17358f 2274static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2275{
fb17358f 2276 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2277}
2278
fb17358f 2279static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2280{
fb17358f 2281 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2282}
2283
fb17358f 2284
59139528 2285static int sky2_reset(struct sky2_hw *hw)
cd28ab6a 2286{
cd28ab6a 2287 u16 status;
b89165f2 2288 u8 t8;
56a645cc 2289 int i;
cd28ab6a 2290
cd28ab6a 2291 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2292
cd28ab6a
SH		 2293 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2294 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2295 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2296 pci_name(hw->pdev), hw->chip_id);
2297 return -EOPNOTSUPP;
2298 }
2299
290d4de5
SH		 2300 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2301
2302 /* This rev is really old, and requires untested workarounds */
2303 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2304 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2305 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2306 hw->chip_id, hw->chip_rev);
2307 return -EOPNOTSUPP;
2308 }
2309
cd28ab6a
SH		 2310 /* disable ASF */
2311 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2312 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2313 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2314 }
2315
2316 /* do a SW reset */
2317 sky2_write8(hw, B0_CTST, CS_RST_SET);
2318 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2319
2320 /* clear PCI errors, if any */
56a645cc 2321 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2322
cd28ab6a 2323 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2324 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2325
cd28ab6a
SH		 2326
2327 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2328
2329 /* clear any PEX errors */
d89e1343 2330 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
56a645cc
SH		 2331 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2332
cd28ab6a 2333
b89165f2 2334 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
cd28ab6a
SH		 2335 hw->ports = 1;
2336 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2337 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2338 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2339 ++hw->ports;
2340 }
cd28ab6a 2341
5afa0a9c 2342 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2343
2344 for (i = 0; i < hw->ports; i++) {
2345 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2346 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2347 }
2348
2349 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2350
793b883e
SH		 2351 /* Clear I2C IRQ noise */
2352 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2353
2354 /* turn off hardware timer (unused) */
2355 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2356 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2357
cd28ab6a
SH		 2358 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2359
69634ee7
SH		 2360 /* Turn off descriptor polling */
2361 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2362
2363 /* Turn off receive timestamp */
2364 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2365 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2366
2367 /* enable the Tx Arbiters */
2368 for (i = 0; i < hw->ports; i++)
2369 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2370
2371 /* Initialize ram interface */
2372 for (i = 0; i < hw->ports; i++) {
793b883e 2373 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2374
2375 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2376 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2377 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2378 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2379 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2380 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2381 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2382 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2383 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2384 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2385 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2386 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2387 }
2388
cd28ab6a
SH		 2389 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2390
cd28ab6a 2391 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2392 sky2_gmac_reset(hw, i);
cd28ab6a 2393
cd28ab6a
SH		 2394 memset(hw->st_le, 0, STATUS_LE_BYTES);
2395 hw->st_idx = 0;
2396
2397 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2398 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2399
2400 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2401 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2402
2403 /* Set the list last index */
793b883e 2404 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2405
290d4de5
SH		 2406 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2407 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2408
290d4de5
SH		 2409 /* set Status-FIFO ISR watermark */
2410 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2411 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2412 else
2413 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2414
290d4de5 2415 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2416 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2417 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2418
793b883e 2419 /* enable status unit */
cd28ab6a
SH		 2420 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2421
2422 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2423 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2424 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2425
2426 return 0;
2427}
2428
28bd181a 2429static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2430{
b89165f2
SH		 2431 if (sky2_is_copper(hw)) {
2432 u32 modes = SUPPORTED_10baseT_Half
2433 | SUPPORTED_10baseT_Full
2434 | SUPPORTED_100baseT_Half
2435 | SUPPORTED_100baseT_Full
2436 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2437
2438 if (hw->chip_id != CHIP_ID_YUKON_FE)
2439 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2440 | SUPPORTED_1000baseT_Full;
2441 return modes;
cd28ab6a 2442 } else
b89165f2
SH		 2443 return SUPPORTED_1000baseT_Half
2444 | SUPPORTED_1000baseT_Full
2445 | SUPPORTED_Autoneg
2446 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2447}
2448
793b883e 2449static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2450{
2451 struct sky2_port *sky2 = netdev_priv(dev);
2452 struct sky2_hw *hw = sky2->hw;
2453
2454 ecmd->transceiver = XCVR_INTERNAL;
2455 ecmd->supported = sky2_supported_modes(hw);
2456 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2457 if (sky2_is_copper(hw)) {
cd28ab6a 2458 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2459 | SUPPORTED_10baseT_Full
2460 | SUPPORTED_100baseT_Half
2461 | SUPPORTED_100baseT_Full
2462 | SUPPORTED_1000baseT_Half
2463 | SUPPORTED_1000baseT_Full
2464 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2465 ecmd->port = PORT_TP;
b89165f2
SH		 2466 ecmd->speed = sky2->speed;
2467 } else {
2468 ecmd->speed = SPEED_1000;
cd28ab6a 2469 ecmd->port = PORT_FIBRE;
b89165f2 2470 }
cd28ab6a
SH		 2471
2472 ecmd->advertising = sky2->advertising;
2473 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2474 ecmd->duplex = sky2->duplex;
2475 return 0;
2476}
2477
2478static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2479{
2480 struct sky2_port *sky2 = netdev_priv(dev);
2481 const struct sky2_hw *hw = sky2->hw;
2482 u32 supported = sky2_supported_modes(hw);
2483
2484 if (ecmd->autoneg == AUTONEG_ENABLE) {
2485 ecmd->advertising = supported;
2486 sky2->duplex = -1;
2487 sky2->speed = -1;
2488 } else {
2489 u32 setting;
2490
793b883e 2491 switch (ecmd->speed) {
cd28ab6a
SH		 2492 case SPEED_1000:
2493 if (ecmd->duplex == DUPLEX_FULL)
2494 setting = SUPPORTED_1000baseT_Full;
2495 else if (ecmd->duplex == DUPLEX_HALF)
2496 setting = SUPPORTED_1000baseT_Half;
2497 else
2498 return -EINVAL;
2499 break;
2500 case SPEED_100:
2501 if (ecmd->duplex == DUPLEX_FULL)
2502 setting = SUPPORTED_100baseT_Full;
2503 else if (ecmd->duplex == DUPLEX_HALF)
2504 setting = SUPPORTED_100baseT_Half;
2505 else
2506 return -EINVAL;
2507 break;
2508
2509 case SPEED_10:
2510 if (ecmd->duplex == DUPLEX_FULL)
2511 setting = SUPPORTED_10baseT_Full;
2512 else if (ecmd->duplex == DUPLEX_HALF)
2513 setting = SUPPORTED_10baseT_Half;
2514 else
2515 return -EINVAL;
2516 break;
2517 default:
2518 return -EINVAL;
2519 }
2520
2521 if ((setting & supported) == 0)
2522 return -EINVAL;
2523
2524 sky2->speed = ecmd->speed;
2525 sky2->duplex = ecmd->duplex;
2526 }
2527
2528 sky2->autoneg = ecmd->autoneg;
2529 sky2->advertising = ecmd->advertising;
2530
1b537565
SH		 2531 if (netif_running(dev))
2532 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2533
2534 return 0;
2535}
2536
2537static void sky2_get_drvinfo(struct net_device *dev,
2538 struct ethtool_drvinfo *info)
2539{
2540 struct sky2_port *sky2 = netdev_priv(dev);
2541
2542 strcpy(info->driver, DRV_NAME);
2543 strcpy(info->version, DRV_VERSION);
2544 strcpy(info->fw_version, "N/A");
2545 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2546}
2547
2548static const struct sky2_stat {
793b883e
SH		 2549 char name[ETH_GSTRING_LEN];
2550 u16 offset;
cd28ab6a
SH		 2551} sky2_stats[] = {
2552 { "tx_bytes", GM_TXO_OK_HI },
2553 { "rx_bytes", GM_RXO_OK_HI },
2554 { "tx_broadcast", GM_TXF_BC_OK },
2555 { "rx_broadcast", GM_RXF_BC_OK },
2556 { "tx_multicast", GM_TXF_MC_OK },
2557 { "rx_multicast", GM_RXF_MC_OK },
2558 { "tx_unicast", GM_TXF_UC_OK },
2559 { "rx_unicast", GM_RXF_UC_OK },
2560 { "tx_mac_pause", GM_TXF_MPAUSE },
2561 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2562 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2563 { "late_collision",GM_TXF_LAT_COL },
2564 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2565 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2566 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2567
d2604540 2568 { "rx_short", GM_RXF_SHT },
cd28ab6a 2569 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2570 { "rx_64_byte_packets", GM_RXF_64B },
2571 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2572 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2573 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2574 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2575 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2576 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2577 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2578 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2579 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2580 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2581
2582 { "tx_64_byte_packets", GM_TXF_64B },
2583 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2584 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2585 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2586 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2587 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2588 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2589 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2590};
2591
cd28ab6a
SH		 2592static u32 sky2_get_rx_csum(struct net_device *dev)
2593{
2594 struct sky2_port *sky2 = netdev_priv(dev);
2595
2596 return sky2->rx_csum;
2597}
2598
2599static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2600{
2601 struct sky2_port *sky2 = netdev_priv(dev);
2602
2603 sky2->rx_csum = data;
793b883e 2604
cd28ab6a
SH		 2605 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2606 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2607
2608 return 0;
2609}
2610
2611static u32 sky2_get_msglevel(struct net_device *netdev)
2612{
2613 struct sky2_port *sky2 = netdev_priv(netdev);
2614 return sky2->msg_enable;
2615}
2616
9a7ae0a9
SH		 2617static int sky2_nway_reset(struct net_device *dev)
2618{
2619 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9
SH		 2620
2621 if (sky2->autoneg != AUTONEG_ENABLE)
2622 return -EINVAL;
2623
1b537565 2624 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2625
2626 return 0;
2627}
2628
793b883e 2629static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2630{
2631 struct sky2_hw *hw = sky2->hw;
2632 unsigned port = sky2->port;
2633 int i;
2634
2635 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2636 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2637 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2638 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2639
793b883e 2640 for (i = 2; i < count; i++)
cd28ab6a
SH		 2641 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2642}
2643
cd28ab6a
SH		 2644static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2645{
2646 struct sky2_port *sky2 = netdev_priv(netdev);
2647 sky2->msg_enable = value;
2648}
2649
2650static int sky2_get_stats_count(struct net_device *dev)
2651{
2652 return ARRAY_SIZE(sky2_stats);
2653}
2654
2655static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2656 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2657{
2658 struct sky2_port *sky2 = netdev_priv(dev);
2659
793b883e 2660 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2661}
2662
793b883e 2663static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2664{
2665 int i;
2666
2667 switch (stringset) {
2668 case ETH_SS_STATS:
2669 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2670 memcpy(data + i * ETH_GSTRING_LEN,
2671 sky2_stats[i].name, ETH_GSTRING_LEN);
2672 break;
2673 }
2674}
2675
2676/* Use hardware MIB variables for critical path statistics and
2677 * transmit feedback not reported at interrupt.
2678 * Other errors are accounted for in interrupt handler.
2679 */
2680static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2681{
2682 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2683 u64 data[13];
cd28ab6a 2684
793b883e 2685 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2686
2687 sky2->net_stats.tx_bytes = data[0];
2688 sky2->net_stats.rx_bytes = data[1];
2689 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2690 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
050ff180 2691 sky2->net_stats.multicast = data[3] + data[5];
cd28ab6a
SH		 2692 sky2->net_stats.collisions = data[10];
2693 sky2->net_stats.tx_aborted_errors = data[12];
2694
2695 return &sky2->net_stats;
2696}
2697
2698static int sky2_set_mac_address(struct net_device *dev, void *p)
2699{
2700 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2701 struct sky2_hw *hw = sky2->hw;
2702 unsigned port = sky2->port;
2703 const struct sockaddr *addr = p;
cd28ab6a
SH		 2704
2705 if (!is_valid_ether_addr(addr->sa_data))
2706 return -EADDRNOTAVAIL;
2707
cd28ab6a 2708 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2709 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2710 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2711 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2712 dev->dev_addr, ETH_ALEN);
1b537565 2713
a8ab1ec0
SH		 2714 /* virtual address for data */
2715 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2716
2717 /* physical address: used for pause frames */
2718 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2719
2720 return 0;
cd28ab6a
SH		 2721}
2722
2723static void sky2_set_multicast(struct net_device *dev)
2724{
2725 struct sky2_port *sky2 = netdev_priv(dev);
2726 struct sky2_hw *hw = sky2->hw;
2727 unsigned port = sky2->port;
2728 struct dev_mc_list *list = dev->mc_list;
2729 u16 reg;
2730 u8 filter[8];
2731
2732 memset(filter, 0, sizeof(filter));
2733
2734 reg = gma_read16(hw, port, GM_RX_CTRL);
2735 reg |= GM_RXCR_UCF_ENA;
2736
d571b694 2737 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2738 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2739 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2740 memset(filter, 0xff, sizeof(filter));
793b883e 2741 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2742 reg &= ~GM_RXCR_MCF_ENA;
2743 else {
2744 int i;
2745 reg |= GM_RXCR_MCF_ENA;
2746
2747 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2748 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2749 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2750 }
2751 }
2752
cd28ab6a 2753 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2754 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2755 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2756 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2757 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2758 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2759 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2760 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2761
2762 gma_write16(hw, port, GM_RX_CTRL, reg);
2763}
2764
2765/* Can have one global because blinking is controlled by
2766 * ethtool and that is always under RTNL mutex
2767 */
91c86df5 2768static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2769{
793b883e
SH		 2770 u16 pg;
2771
793b883e
SH		 2772 switch (hw->chip_id) {
2773 case CHIP_ID_YUKON_XL:
2774 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2775 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2776 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2777 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2778 PHY_M_LEDC_INIT_CTRL(7) |
2779 PHY_M_LEDC_STA1_CTRL(7) |
2780 PHY_M_LEDC_STA0_CTRL(7))
2781 : 0);
2782
2783 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2784 break;
2785
2786 default:
2787 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2788 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2789 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2790 PHY_M_LED_MO_10(MO_LED_ON) |
2791 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2792 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2793 PHY_M_LED_MO_RX(MO_LED_ON)
2794 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2795 PHY_M_LED_MO_10(MO_LED_OFF) |
2796 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2797 PHY_M_LED_MO_1000(MO_LED_OFF) |
2798 PHY_M_LED_MO_RX(MO_LED_OFF));
2799
793b883e 2800 }
cd28ab6a
SH		 2801}
2802
2803/* blink LED's for finding board */
2804static int sky2_phys_id(struct net_device *dev, u32 data)
2805{
2806 struct sky2_port *sky2 = netdev_priv(dev);
2807 struct sky2_hw *hw = sky2->hw;
2808 unsigned port = sky2->port;
793b883e 2809 u16 ledctrl, ledover = 0;
cd28ab6a 2810 long ms;
91c86df5 2811 int interrupted;
cd28ab6a
SH		 2812 int onoff = 1;
2813
793b883e 2814 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2815 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2816 else
2817 ms = data * 1000;
2818
2819 /* save initial values */
e07b1aa8 2820 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2821 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2822 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2823 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2824 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2825 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2826 } else {
2827 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2828 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2829 }
cd28ab6a 2830
91c86df5
SH		 2831 interrupted = 0;
2832 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2833 sky2_led(hw, port, onoff);
2834 onoff = !onoff;
2835
e07b1aa8 2836 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2837 interrupted = msleep_interruptible(250);
e07b1aa8 2838 spin_lock_bh(&sky2->phy_lock);
91c86df5 2839
cd28ab6a
SH		 2840 ms -= 250;
2841 }
2842
2843 /* resume regularly scheduled programming */
793b883e
SH		 2844 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2845 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2846 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2847 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2848 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2849 } else {
2850 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2851 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2852 }
e07b1aa8 2853 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2854
2855 return 0;
2856}
2857
2858static void sky2_get_pauseparam(struct net_device *dev,
2859 struct ethtool_pauseparam *ecmd)
2860{
2861 struct sky2_port *sky2 = netdev_priv(dev);
2862
2863 ecmd->tx_pause = sky2->tx_pause;
2864 ecmd->rx_pause = sky2->rx_pause;
2865 ecmd->autoneg = sky2->autoneg;
2866}
2867
2868static int sky2_set_pauseparam(struct net_device *dev,
2869 struct ethtool_pauseparam *ecmd)
2870{
2871 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2872
2873 sky2->autoneg = ecmd->autoneg;
2874 sky2->tx_pause = ecmd->tx_pause != 0;
2875 sky2->rx_pause = ecmd->rx_pause != 0;
2876
1b537565 2877 sky2_phy_reinit(sky2);
cd28ab6a 2878
2eaba1a2 2879 return 0;
cd28ab6a
SH		 2880}
2881
fb17358f
SH		 2882static int sky2_get_coalesce(struct net_device *dev,
2883 struct ethtool_coalesce *ecmd)
2884{
2885 struct sky2_port *sky2 = netdev_priv(dev);
2886 struct sky2_hw *hw = sky2->hw;
2887
2888 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2889 ecmd->tx_coalesce_usecs = 0;
2890 else {
2891 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2892 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2893 }
2894 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2895
2896 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2897 ecmd->rx_coalesce_usecs = 0;
2898 else {
2899 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2900 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2901 }
2902 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2903
2904 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2905 ecmd->rx_coalesce_usecs_irq = 0;
2906 else {
2907 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2908 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2909 }
2910
2911 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2912
2913 return 0;
2914}
2915
2916/* Note: this affect both ports */
2917static int sky2_set_coalesce(struct net_device *dev,
2918 struct ethtool_coalesce *ecmd)
2919{
2920 struct sky2_port *sky2 = netdev_priv(dev);
2921 struct sky2_hw *hw = sky2->hw;
77b3d6a2 2922 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 2923
77b3d6a2
SH		 2924 if (ecmd->tx_coalesce_usecs > tmax ||
2925 ecmd->rx_coalesce_usecs > tmax ||
2926 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 2927 return -EINVAL;
2928
ff81fbbe 2929 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 2930 return -EINVAL;
ff81fbbe 2931 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 2932 return -EINVAL;
ff81fbbe 2933 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 2934 return -EINVAL;
2935
2936 if (ecmd->tx_coalesce_usecs == 0)
2937 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2938 else {
2939 sky2_write32(hw, STAT_TX_TIMER_INI,
2940 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2941 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2942 }
2943 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2944
2945 if (ecmd->rx_coalesce_usecs == 0)
2946 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2947 else {
2948 sky2_write32(hw, STAT_LEV_TIMER_INI,
2949 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2950 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2951 }
2952 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2953
2954 if (ecmd->rx_coalesce_usecs_irq == 0)
2955 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2956 else {
d28d4870 2957 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 2958 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2959 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2960 }
2961 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2962 return 0;
2963}
2964
793b883e
SH		 2965static void sky2_get_ringparam(struct net_device *dev,
2966 struct ethtool_ringparam *ering)
2967{
2968 struct sky2_port *sky2 = netdev_priv(dev);
2969
2970 ering->rx_max_pending = RX_MAX_PENDING;
2971 ering->rx_mini_max_pending = 0;
2972 ering->rx_jumbo_max_pending = 0;
2973 ering->tx_max_pending = TX_RING_SIZE - 1;
2974
2975 ering->rx_pending = sky2->rx_pending;
2976 ering->rx_mini_pending = 0;
2977 ering->rx_jumbo_pending = 0;
2978 ering->tx_pending = sky2->tx_pending;
2979}
2980
2981static int sky2_set_ringparam(struct net_device *dev,
2982 struct ethtool_ringparam *ering)
2983{
2984 struct sky2_port *sky2 = netdev_priv(dev);
2985 int err = 0;
2986
2987 if (ering->rx_pending > RX_MAX_PENDING ||
2988 ering->rx_pending < 8 ||
2989 ering->tx_pending < MAX_SKB_TX_LE ||
2990 ering->tx_pending > TX_RING_SIZE - 1)
2991 return -EINVAL;
2992
2993 if (netif_running(dev))
2994 sky2_down(dev);
2995
2996 sky2->rx_pending = ering->rx_pending;
2997 sky2->tx_pending = ering->tx_pending;
2998
1b537565 2999 if (netif_running(dev)) {
793b883e 3000 err = sky2_up(dev);
1b537565
SH		 3001 if (err)
3002 dev_close(dev);
6ed995bb
SH		 3003 else
3004 sky2_set_multicast(dev);
1b537565 3005 }
793b883e
SH		 3006
3007 return err;
3008}
3009
793b883e
SH		 3010static int sky2_get_regs_len(struct net_device *dev)
3011{
6e4cbb34 3012 return 0x4000;
793b883e
SH		 3013}
3014
3015/*
3016 * Returns copy of control register region
6e4cbb34 3017 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3018 */
3019static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3020 void *p)
3021{
3022 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3023 const void __iomem *io = sky2->hw->regs;
793b883e 3024
6e4cbb34 3025 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3026 regs->version = 1;
6e4cbb34 3027 memset(p, 0, regs->len);
793b883e 3028
6e4cbb34
SH		 3029 memcpy_fromio(p, io, B3_RAM_ADDR);
3030
3031 memcpy_fromio(p + B3_RI_WTO_R1,
3032 io + B3_RI_WTO_R1,
3033 regs->len - B3_RI_WTO_R1);
793b883e 3034}
cd28ab6a 3035
7282d491 3036static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3037 .get_settings = sky2_get_settings,
3038 .set_settings = sky2_set_settings,
3039 .get_drvinfo = sky2_get_drvinfo,
3040 .get_msglevel = sky2_get_msglevel,
3041 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3042 .nway_reset = sky2_nway_reset,
793b883e
SH		 3043 .get_regs_len = sky2_get_regs_len,
3044 .get_regs = sky2_get_regs,
3045 .get_link = ethtool_op_get_link,
3046 .get_sg = ethtool_op_get_sg,
3047 .set_sg = ethtool_op_set_sg,
3048 .get_tx_csum = ethtool_op_get_tx_csum,
3049 .set_tx_csum = ethtool_op_set_tx_csum,
3050 .get_tso = ethtool_op_get_tso,
3051 .set_tso = ethtool_op_set_tso,
3052 .get_rx_csum = sky2_get_rx_csum,
3053 .set_rx_csum = sky2_set_rx_csum,
3054 .get_strings = sky2_get_strings,
fb17358f
SH		 3055 .get_coalesce = sky2_get_coalesce,
3056 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3057 .get_ringparam = sky2_get_ringparam,
3058 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3059 .get_pauseparam = sky2_get_pauseparam,
3060 .set_pauseparam = sky2_set_pauseparam,
793b883e 3061 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3062 .get_stats_count = sky2_get_stats_count,
3063 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3064 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3065};
3066
3067/* Initialize network device */
3068static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3069 unsigned port, int highmem)
3070{
3071 struct sky2_port *sky2;
3072 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3073
3074 if (!dev) {
3075 printk(KERN_ERR "sky2 etherdev alloc failed");
3076 return NULL;
3077 }
3078
3079 SET_MODULE_OWNER(dev);
3080 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3081 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3082 dev->open = sky2_up;
3083 dev->stop = sky2_down;
ef743d33 3084 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3085 dev->hard_start_xmit = sky2_xmit_frame;
3086 dev->get_stats = sky2_get_stats;
3087 dev->set_multicast_list = sky2_set_multicast;
3088 dev->set_mac_address = sky2_set_mac_address;
3089 dev->change_mtu = sky2_change_mtu;
3090 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3091 dev->tx_timeout = sky2_tx_timeout;
3092 dev->watchdog_timeo = TX_WATCHDOG;
3093 if (port == 0)
3094 dev->poll = sky2_poll;
3095 dev->weight = NAPI_WEIGHT;
3096#ifdef CONFIG_NET_POLL_CONTROLLER
3097 dev->poll_controller = sky2_netpoll;
3098#endif
cd28ab6a
SH		 3099
3100 sky2 = netdev_priv(dev);
3101 sky2->netdev = dev;
3102 sky2->hw = hw;
3103 sky2->msg_enable = netif_msg_init(debug, default_msg);
3104
3105 spin_lock_init(&sky2->tx_lock);
3106 /* Auto speed and flow control */
3107 sky2->autoneg = AUTONEG_ENABLE;
585b5601 3108 sky2->tx_pause = 1;
cd28ab6a
SH		 3109 sky2->rx_pause = 1;
3110 sky2->duplex = -1;
3111 sky2->speed = -1;
3112 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3113 sky2->rx_csum = 1;
75d070c5 3114
e07b1aa8 3115 spin_lock_init(&sky2->phy_lock);
793b883e 3116 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3117 sky2->rx_pending = RX_DEF_PENDING;
734d1868 3118 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
cd28ab6a
SH		 3119
3120 hw->dev[port] = dev;
3121
3122 sky2->port = port;
3123
5a5b1ea0 3124 dev->features |= NETIF_F_LLTX;
3125 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3126 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3127 if (highmem)
3128 dev->features |= NETIF_F_HIGHDMA;
793b883e 3129 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3130
d1f13708 3131#ifdef SKY2_VLAN_TAG_USED
3132 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3133 dev->vlan_rx_register = sky2_vlan_rx_register;
3134 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3135#endif
3136
cd28ab6a 3137 /* read the mac address */
793b883e 3138 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3139 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3140
3141 /* device is off until link detection */
3142 netif_carrier_off(dev);
3143 netif_stop_queue(dev);
3144
3145 return dev;
3146}
3147
28bd181a 3148static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3149{
3150 const struct sky2_port *sky2 = netdev_priv(dev);
3151
3152 if (netif_msg_probe(sky2))
3153 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3154 dev->name,
3155 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3156 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3157}
3158
fb2690a9
SH		 3159/* Handle software interrupt used during MSI test */
3160static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3161 struct pt_regs *regs)
3162{
3163 struct sky2_hw *hw = dev_id;
3164 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3165
3166 if (status == 0)
3167 return IRQ_NONE;
3168
3169 if (status & Y2_IS_IRQ_SW) {
3170 hw->msi_detected = 1;
3171 wake_up(&hw->msi_wait);
3172 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3173 }
3174 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3175
3176 return IRQ_HANDLED;
3177}
3178
3179/* Test interrupt path by forcing a a software IRQ */
3180static int __devinit sky2_test_msi(struct sky2_hw *hw)
3181{
3182 struct pci_dev *pdev = hw->pdev;
3183 int err;
3184
bb507fe1 3185 init_waitqueue_head (&hw->msi_wait);
3186
fb2690a9
SH		 3187 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3188
1fb9df5d 3189 err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw);
fb2690a9
SH		 3190 if (err) {
3191 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3192 pci_name(pdev), pdev->irq);
3193 return err;
3194 }
3195
fb2690a9 3196 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3197 sky2_read8(hw, B0_CTST);
fb2690a9
SH		 3198
3199 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3200
3201 if (!hw->msi_detected) {
3202 /* MSI test failed, go back to INTx mode */
3203 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3204 "switching to INTx mode. Please report this failure to "
3205 "the PCI maintainer and include system chipset information.\n",
3206 pci_name(pdev));
3207
3208 err = -EOPNOTSUPP;
3209 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3210 }
3211
3212 sky2_write32(hw, B0_IMSK, 0);
3213
3214 free_irq(pdev->irq, hw);
3215
3216 return err;
3217}
3218
cd28ab6a
SH		 3219static int __devinit sky2_probe(struct pci_dev *pdev,
3220 const struct pci_device_id *ent)
3221{
793b883e 3222 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3223 struct sky2_hw *hw;
5afa0a9c 3224 int err, pm_cap, using_dac = 0;
cd28ab6a 3225
793b883e
SH		 3226 err = pci_enable_device(pdev);
3227 if (err) {
cd28ab6a
SH		 3228 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3229 pci_name(pdev));
3230 goto err_out;
3231 }
3232
793b883e
SH		 3233 err = pci_request_regions(pdev, DRV_NAME);
3234 if (err) {
cd28ab6a
SH		 3235 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3236 pci_name(pdev));
793b883e 3237 goto err_out;
cd28ab6a
SH		 3238 }
3239
3240 pci_set_master(pdev);
3241
5afa0a9c 3242 /* Find power-management capability. */
3243 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3244 if (pm_cap == 0) {
3245 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3246 "aborting.\n");
3247 err = -EIO;
3248 goto err_out_free_regions;
3249 }
3250
d1f3d4dd
SH		 3251 if (sizeof(dma_addr_t) > sizeof(u32) &&
3252 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3253 using_dac = 1;
3254 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3255 if (err < 0) {
3256 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3257 "for consistent allocations\n", pci_name(pdev));
3258 goto err_out_free_regions;
3259 }
cd28ab6a 3260
d1f3d4dd 3261 } else {
cd28ab6a
SH		 3262 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3263 if (err) {
3264 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3265 pci_name(pdev));
3266 goto err_out_free_regions;
3267 }
3268 }
d1f3d4dd 3269
cd28ab6a 3270 err = -ENOMEM;
6aad85d6 3271 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3272 if (!hw) {
3273 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3274 pci_name(pdev));
3275 goto err_out_free_regions;
3276 }
3277
cd28ab6a 3278 hw->pdev = pdev;
cd28ab6a
SH		 3279
3280 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3281 if (!hw->regs) {
3282 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3283 pci_name(pdev));
3284 goto err_out_free_hw;
3285 }
5afa0a9c 3286 hw->pm_cap = pm_cap;
cd28ab6a 3287
56a645cc 3288#ifdef __BIG_ENDIAN
f65b138c
SH		 3289 /* The sk98lin vendor driver uses hardware byte swapping but
3290 * this driver uses software swapping.
3291 */
56a645cc
SH		 3292 {
3293 u32 reg;
56a645cc 3294 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3295 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3296 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3297 }
3298#endif
3299
08c06d8a
SH		 3300 /* ring for status responses */
3301 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3302 &hw->st_dma);
3303 if (!hw->st_le)
3304 goto err_out_iounmap;
3305
cd28ab6a
SH		 3306 err = sky2_reset(hw);
3307 if (err)
793b883e 3308 goto err_out_iounmap;
cd28ab6a 3309
7c7459d1
GKH		 3310 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3311 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3312 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3313 hw->chip_id, hw->chip_rev);
cd28ab6a 3314
793b883e
SH		 3315 dev = sky2_init_netdev(hw, 0, using_dac);
3316 if (!dev)
cd28ab6a
SH		 3317 goto err_out_free_pci;
3318
793b883e
SH		 3319 err = register_netdev(dev);
3320 if (err) {
cd28ab6a
SH		 3321 printk(KERN_ERR PFX "%s: cannot register net device\n",
3322 pci_name(pdev));
3323 goto err_out_free_netdev;
3324 }
3325
3326 sky2_show_addr(dev);
3327
3328 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3329 if (register_netdev(dev1) == 0)
3330 sky2_show_addr(dev1);
3331 else {
3332 /* Failure to register second port need not be fatal */
793b883e
SH		 3333 printk(KERN_WARNING PFX
3334 "register of second port failed\n");
cd28ab6a
SH		 3335 hw->dev[1] = NULL;
3336 free_netdev(dev1);
3337 }
3338 }
3339
fb2690a9
SH		 3340 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3341 err = sky2_test_msi(hw);
3342 if (err == -EOPNOTSUPP)
3343 pci_disable_msi(pdev);
3344 else if (err)
3345 goto err_out_unregister;
3346 }
3347
1fb9df5d 3348 err = request_irq(pdev->irq, sky2_intr, IRQF_SHARED, DRV_NAME, hw);
793b883e
SH		 3349 if (err) {
3350 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3351 pci_name(pdev), pdev->irq);
3352 goto err_out_unregister;
3353 }
3354
e07b1aa8 3355 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
793b883e 3356
01bd7564 3357 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
eb35cf60 3358 sky2_idle_start(hw);
d27ed387 3359
793b883e
SH		 3360 pci_set_drvdata(pdev, hw);
3361
cd28ab6a
SH		 3362 return 0;
3363
793b883e 3364err_out_unregister:
fb2690a9 3365 pci_disable_msi(pdev);
793b883e
SH		 3366 if (dev1) {
3367 unregister_netdev(dev1);
3368 free_netdev(dev1);
3369 }
3370 unregister_netdev(dev);
cd28ab6a
SH		 3371err_out_free_netdev:
3372 free_netdev(dev);
cd28ab6a 3373err_out_free_pci:
793b883e 3374 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3375 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3376err_out_iounmap:
3377 iounmap(hw->regs);
3378err_out_free_hw:
3379 kfree(hw);
3380err_out_free_regions:
3381 pci_release_regions(pdev);
cd28ab6a 3382 pci_disable_device(pdev);
cd28ab6a
SH		 3383err_out:
3384 return err;
3385}
3386
3387static void __devexit sky2_remove(struct pci_dev *pdev)
3388{
793b883e 3389 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3390 struct net_device *dev0, *dev1;
3391
793b883e 3392 if (!hw)
cd28ab6a
SH		 3393 return;
3394
d27ed387
SH		 3395 del_timer_sync(&hw->idle_timer);
3396
3397 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3398 synchronize_irq(hw->pdev->irq);
3399
cd28ab6a 3400 dev0 = hw->dev[0];
793b883e
SH		 3401 dev1 = hw->dev[1];
3402 if (dev1)
3403 unregister_netdev(dev1);
cd28ab6a
SH		 3404 unregister_netdev(dev0);
3405
5afa0a9c 3406 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3407 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3408 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3409 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3410
3411 free_irq(pdev->irq, hw);
fb2690a9 3412 pci_disable_msi(pdev);
793b883e 3413 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3414 pci_release_regions(pdev);
3415 pci_disable_device(pdev);
793b883e 3416
cd28ab6a
SH		 3417 if (dev1)
3418 free_netdev(dev1);
3419 free_netdev(dev0);
3420 iounmap(hw->regs);
3421 kfree(hw);
5afa0a9c 3422
cd28ab6a
SH		 3423 pci_set_drvdata(pdev, NULL);
3424}
3425
3426#ifdef CONFIG_PM
3427static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3428{
793b883e 3429 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3430 int i;
2ccc99b7
SH		 3431 pci_power_t pstate = pci_choose_state(pdev, state);
3432
3433 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3434 return -EINVAL;
cd28ab6a 3435
eb35cf60 3436 del_timer_sync(&hw->idle_timer);
6a5706b9 3437 netif_poll_disable(hw->dev[0]);
eb35cf60 3438
f05267e7 3439 for (i = 0; i < hw->ports; i++) {
cd28ab6a
SH		 3440 struct net_device *dev = hw->dev[i];
3441
6a5706b9 3442 if (netif_running(dev)) {
5afa0a9c 3443 sky2_down(dev);
cd28ab6a 3444 netif_device_detach(dev);
cd28ab6a
SH		 3445 }
3446 }
3447
8ab8fca2 3448 sky2_write32(hw, B0_IMSK, 0);
d374c1c1 3449 pci_save_state(pdev);
2ccc99b7
SH		 3450 sky2_set_power_state(hw, pstate);
3451 return 0;
cd28ab6a
SH		 3452}
3453
3454static int sky2_resume(struct pci_dev *pdev)
3455{
793b883e 3456 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3457 int i, err;
cd28ab6a 3458
cd28ab6a
SH		 3459 pci_restore_state(pdev);
3460 pci_enable_wake(pdev, PCI_D0, 0);
2ccc99b7 3461 sky2_set_power_state(hw, PCI_D0);
cd28ab6a 3462
08c06d8a
SH		 3463 err = sky2_reset(hw);
3464 if (err)
3465 goto out;
cd28ab6a 3466
8ab8fca2
SH		 3467 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3468
f05267e7 3469 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3470 struct net_device *dev = hw->dev[i];
6a5706b9 3471 if (netif_running(dev)) {
08c06d8a 3472 netif_device_attach(dev);
88d11360 3473
08c06d8a
SH		 3474 err = sky2_up(dev);
3475 if (err) {
3476 printk(KERN_ERR PFX "%s: could not up: %d\n",
3477 dev->name, err);
3478 dev_close(dev);
eb35cf60 3479 goto out;
5afa0a9c 3480 }
cd28ab6a
SH		 3481 }
3482 }
eb35cf60 3483
6a5706b9 3484 netif_poll_enable(hw->dev[0]);
eb35cf60 3485 sky2_idle_start(hw);
08c06d8a
SH		 3486out:
3487 return err;
cd28ab6a
SH		 3488}
3489#endif
3490
3491static struct pci_driver sky2_driver = {
793b883e
SH		 3492 .name = DRV_NAME,
3493 .id_table = sky2_id_table,
3494 .probe = sky2_probe,
3495 .remove = __devexit_p(sky2_remove),
cd28ab6a 3496#ifdef CONFIG_PM
793b883e
SH		 3497 .suspend = sky2_suspend,
3498 .resume = sky2_resume,
cd28ab6a
SH		 3499#endif
3500};
3501
3502static int __init sky2_init_module(void)
3503{
50241c4c 3504 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3505}
3506
3507static void __exit sky2_cleanup_module(void)
3508{
3509 pci_unregister_driver(&sky2_driver);
3510}
3511
3512module_init(sky2_init_module);
3513module_exit(sky2_cleanup_module);
3514
3515MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3516MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3517MODULE_LICENSE("GPL");
5f4f9dc1 3518MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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