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Merge branch 'upstream-fixes' into upstream
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
793b883e 26#include <linux/crc32.h>
cd28ab6a
SH		 27#include <linux/kernel.h>
28#include <linux/version.h>
29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
caa0371e 53#define DRV_VERSION "1.5"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3. A transmit can require several elements;
60 * a receive requires one (or two if using 64 bit dma).
61 */
62
13210ce5 63#define RX_LE_SIZE 512
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
bea86103 65#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 67#define RX_SKB_ALIGN 8
22e11703 68#define RX_BUF_WRITE 16
793b883e
SH		 69
70#define TX_RING_SIZE 512
71#define TX_DEF_PENDING (TX_RING_SIZE - 1)
72#define TX_MIN_PENDING 64
b19666d9 73#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 74
793b883e 75#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 76#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77#define ETH_JUMBO_MTU 9000
78#define TX_WATCHDOG (5 * HZ)
79#define NAPI_WEIGHT 64
80#define PHY_RETRIES 1000
81
cb5d9547
SH		 82#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
cd28ab6a 84static const u32 default_msg =
793b883e
SH		 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 88
793b883e 89static int debug = -1; /* defaults above */
cd28ab6a
SH		 90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
bdb5c58e
SH		 93static int copybreak __read_mostly = 256;
94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
fb2690a9
SH		 97static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
01bd7564
SH		 101static int idle_timeout = 100;
102module_param(idle_timeout, int, 0);
103MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
104
cd28ab6a 105static const struct pci_device_id sky2_id_table[] = {
793b883e 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a 107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
2d2a3871 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
cd28ab6a
SH		 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
cd28ab6a
SH		 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
5f5d83fd 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) },
57fa442c
SH		 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) },
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) },
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) },
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) },
cd28ab6a
SH		 129 { 0 }
130};
793b883e 131
cd28ab6a
SH		 132MODULE_DEVICE_TABLE(pci, sky2_id_table);
133
134/* Avoid conditionals by using array */
135static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
136static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 137static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 138
92f965e8
SH		 139/* This driver supports yukon2 chipset only */
140static const char *yukon2_name[] = {
141 "XL", /* 0xb3 */
142 "EC Ultra", /* 0xb4 */
143 "UNKNOWN", /* 0xb5 */
144 "EC", /* 0xb6 */
145 "FE", /* 0xb7 */
793b883e
SH		 146};
147
793b883e 148/* Access to external PHY */
ef743d33 149static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 150{
151 int i;
152
153 gma_write16(hw, port, GM_SMI_DATA, val);
154 gma_write16(hw, port, GM_SMI_CTRL,
155 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
156
157 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 158 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 159 return 0;
793b883e 160 udelay(1);
cd28ab6a 161 }
ef743d33 162
793b883e 163 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 164 return -ETIMEDOUT;
cd28ab6a
SH		 165}
166
ef743d33 167static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 168{
169 int i;
170
793b883e 171 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 172 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
173
174 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33 175 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
176 *val = gma_read16(hw, port, GM_SMI_DATA);
177 return 0;
178 }
179
793b883e 180 udelay(1);
cd28ab6a
SH		 181 }
182
ef743d33 183 return -ETIMEDOUT;
184}
185
186static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
187{
188 u16 v;
189
190 if (__gm_phy_read(hw, port, reg, &v) != 0)
191 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
192 return v;
cd28ab6a
SH		 193}
194
2ccc99b7 195static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
5afa0a9c 196{
197 u16 power_control;
198 u32 reg1;
199 int vaux;
5afa0a9c 200
201 pr_debug("sky2_set_power_state %d\n", state);
202 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
203
56a645cc 204 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 205 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c 206 (power_control & PCI_PM_CAP_PME_D3cold);
207
56a645cc 208 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c 209
210 power_control |= PCI_PM_CTRL_PME_STATUS;
211 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
212
213 switch (state) {
214 case PCI_D0:
215 /* switch power to VCC (WA for VAUX problem) */
216 sky2_write8(hw, B0_POWER_CTRL,
217 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
218
219 /* disable Core Clock Division, */
220 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
221
222 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
223 /* enable bits are inverted */
224 sky2_write8(hw, B2_Y2_CLK_GATE,
225 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
226 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
227 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
228 else
229 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
230
231 /* Turn off phy power saving */
56a645cc 232 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
5afa0a9c 233 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
234
d571b694 235 /* looks like this XL is back asswards .. */
5afa0a9c 236 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
237 reg1 |= PCI_Y2_PHY1_COMA;
238 if (hw->ports > 1)
239 reg1 |= PCI_Y2_PHY2_COMA;
240 }
977bdf06
SH		 241
242 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
56a645cc
SH		 243 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
244 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 245 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 246 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
247 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 248 }
249
56a645cc 250 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
afa195da 251 udelay(100);
977bdf06 252
5afa0a9c 253 break;
254
255 case PCI_D3hot:
256 case PCI_D3cold:
257 /* Turn on phy power saving */
56a645cc 258 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
5afa0a9c 259 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
260 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
261 else
262 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
56a645cc 263 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
afa195da 264 udelay(100);
5afa0a9c 265
266 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
267 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
268 else
269 /* enable bits are inverted */
270 sky2_write8(hw, B2_Y2_CLK_GATE,
271 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
272 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
273 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
274
275 /* switch power to VAUX */
276 if (vaux && state != PCI_D3cold)
277 sky2_write8(hw, B0_POWER_CTRL,
278 (PC_VAUX_ENA | PC_VCC_ENA |
279 PC_VAUX_ON | PC_VCC_OFF));
280 break;
281 default:
282 printk(KERN_ERR PFX "Unknown power state %d\n", state);
5afa0a9c 283 }
284
56a645cc 285 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c 286 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
5afa0a9c 287}
288
cd28ab6a
SH		 289static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
290{
291 u16 reg;
292
293 /* disable all GMAC IRQ's */
294 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
295 /* disable PHY IRQs */
296 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 297
cd28ab6a
SH		 298 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
299 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
300 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
301 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
302
303 reg = gma_read16(hw, port, GM_RX_CTRL);
304 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
305 gma_write16(hw, port, GM_RX_CTRL, reg);
306}
307
308static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
309{
310 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
793b883e 311 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
cd28ab6a 312
ed6d32c7 313 if (sky2->autoneg == AUTONEG_ENABLE &&
86a31a75 314 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 315 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
316
317 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 318 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 319 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
320
321 if (hw->chip_id == CHIP_ID_YUKON_EC)
322 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
323 else
324 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
325
326 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
327 }
328
329 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
330 if (hw->copper) {
331 if (hw->chip_id == CHIP_ID_YUKON_FE) {
332 /* enable automatic crossover */
333 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
334 } else {
335 /* disable energy detect */
336 ctrl &= ~PHY_M_PC_EN_DET_MSK;
337
338 /* enable automatic crossover */
339 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
340
341 if (sky2->autoneg == AUTONEG_ENABLE &&
ed6d32c7 342 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 343 ctrl &= ~PHY_M_PC_DSC_MSK;
344 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
345 }
346 }
347 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
348 } else {
349 /* workaround for deviation #4.88 (CRC errors) */
350 /* disable Automatic Crossover */
351
352 ctrl &= ~PHY_M_PC_MDIX_MSK;
353 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
354
355 if (hw->chip_id == CHIP_ID_YUKON_XL) {
356 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
357 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
358 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
359 ctrl &= ~PHY_M_MAC_MD_MSK;
360 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
361 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
362
363 /* select page 1 to access Fiber registers */
364 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
365 }
cd28ab6a
SH		 366 }
367
368 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
369 if (sky2->autoneg == AUTONEG_DISABLE)
370 ctrl &= ~PHY_CT_ANE;
371 else
372 ctrl |= PHY_CT_ANE;
373
374 ctrl |= PHY_CT_RESET;
375 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
376
377 ctrl = 0;
378 ct1000 = 0;
379 adv = PHY_AN_CSMA;
380
381 if (sky2->autoneg == AUTONEG_ENABLE) {
382 if (hw->copper) {
383 if (sky2->advertising & ADVERTISED_1000baseT_Full)
384 ct1000 |= PHY_M_1000C_AFD;
385 if (sky2->advertising & ADVERTISED_1000baseT_Half)
386 ct1000 |= PHY_M_1000C_AHD;
387 if (sky2->advertising & ADVERTISED_100baseT_Full)
388 adv |= PHY_M_AN_100_FD;
389 if (sky2->advertising & ADVERTISED_100baseT_Half)
390 adv |= PHY_M_AN_100_HD;
391 if (sky2->advertising & ADVERTISED_10baseT_Full)
392 adv |= PHY_M_AN_10_FD;
393 if (sky2->advertising & ADVERTISED_10baseT_Half)
394 adv |= PHY_M_AN_10_HD;
793b883e 395 } else /* special defines for FIBER (88E1011S only) */
cd28ab6a
SH		 396 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
397
398 /* Set Flow-control capabilities */
399 if (sky2->tx_pause && sky2->rx_pause)
793b883e 400 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 401 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 402 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 403 else if (!sky2->rx_pause && sky2->tx_pause)
404 adv |= PHY_AN_PAUSE_ASYM; /* local */
405
406 /* Restart Auto-negotiation */
407 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
408 } else {
409 /* forced speed/duplex settings */
410 ct1000 = PHY_M_1000C_MSE;
411
412 if (sky2->duplex == DUPLEX_FULL)
413 ctrl |= PHY_CT_DUP_MD;
414
415 switch (sky2->speed) {
416 case SPEED_1000:
417 ctrl |= PHY_CT_SP1000;
418 break;
419 case SPEED_100:
420 ctrl |= PHY_CT_SP100;
421 break;
422 }
423
424 ctrl |= PHY_CT_RESET;
425 }
426
427 if (hw->chip_id != CHIP_ID_YUKON_FE)
428 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
429
430 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
431 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
432
433 /* Setup Phy LED's */
434 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
435 ledover = 0;
436
437 switch (hw->chip_id) {
438 case CHIP_ID_YUKON_FE:
439 /* on 88E3082 these bits are at 11..9 (shifted left) */
440 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
441
442 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
443
444 /* delete ACT LED control bits */
445 ctrl &= ~PHY_M_FELP_LED1_MSK;
446 /* change ACT LED control to blink mode */
447 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
448 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
449 break;
450
451 case CHIP_ID_YUKON_XL:
793b883e 452 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 453
454 /* select page 3 to access LED control register */
455 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
456
457 /* set LED Function Control register */
ed6d32c7
SH		 458 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
459 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
460 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
461 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
462 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 463
464 /* set Polarity Control register */
465 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 466 (PHY_M_POLC_LS1_P_MIX(4) |
467 PHY_M_POLC_IS0_P_MIX(4) |
468 PHY_M_POLC_LOS_CTRL(2) |
469 PHY_M_POLC_INIT_CTRL(2) |
470 PHY_M_POLC_STA1_CTRL(2) |
471 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 472
473 /* restore page register */
793b883e 474 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 475 break;
ed6d32c7
SH		 476 case CHIP_ID_YUKON_EC_U:
477 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
478
479 /* select page 3 to access LED control register */
480 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
481
482 /* set LED Function Control register */
483 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
484 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
485 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
486 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
487 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
488
489 /* set Blink Rate in LED Timer Control Register */
490 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
491 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
492 /* restore page register */
493 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
494 break;
cd28ab6a
SH		 495
496 default:
497 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
498 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
499 /* turn off the Rx LED (LED_RX) */
500 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
501 }
502
ed6d32c7 503 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 504 /* apply fixes in PHY AFE */
ed6d32c7
SH		 505 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
506 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
507
977bdf06 508 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 509 gm_phy_write(hw, port, 0x18, 0xaa99);
510 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 511
977bdf06 512 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 513 gm_phy_write(hw, port, 0x18, 0xa204);
514 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 515
516 /* set page register to 0 */
ed6d32c7 517 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
977bdf06
SH		 518 } else {
519 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 520
977bdf06
SH		 521 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
522 /* turn on 100 Mbps LED (LED_LINK100) */
523 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
524 }
cd28ab6a 525
977bdf06
SH		 526 if (ledover)
527 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
528
529 }
d571b694 530 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 531 if (sky2->autoneg == AUTONEG_ENABLE)
532 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
533 else
534 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
535}
536
1b537565
SH		 537/* Force a renegotiation */
538static void sky2_phy_reinit(struct sky2_port *sky2)
539{
e07b1aa8 540 spin_lock_bh(&sky2->phy_lock);
1b537565 541 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 542 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 543}
544
cd28ab6a
SH		 545static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
546{
547 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
548 u16 reg;
549 int i;
550 const u8 *addr = hw->dev[port]->dev_addr;
551
42eeea01 552 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
553 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 554
555 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
556
793b883e 557 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 558 /* WA DEV_472 -- looks like crossed wires on port 2 */
559 /* clear GMAC 1 Control reset */
560 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
561 do {
562 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
563 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
564 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
565 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
566 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
567 }
568
cd28ab6a
SH		 569 if (sky2->autoneg == AUTONEG_DISABLE) {
570 reg = gma_read16(hw, port, GM_GP_CTRL);
571 reg |= GM_GPCR_AU_ALL_DIS;
572 gma_write16(hw, port, GM_GP_CTRL, reg);
573 gma_read16(hw, port, GM_GP_CTRL);
574
cd28ab6a
SH		 575 switch (sky2->speed) {
576 case SPEED_1000:
6f4c56b2 577 reg &= ~GM_GPCR_SPEED_100;
cd28ab6a 578 reg |= GM_GPCR_SPEED_1000;
6f4c56b2 579 break;
cd28ab6a 580 case SPEED_100:
6f4c56b2 581 reg &= ~GM_GPCR_SPEED_1000;
cd28ab6a 582 reg |= GM_GPCR_SPEED_100;
6f4c56b2
SH		 583 break;
584 case SPEED_10:
585 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
586 break;
cd28ab6a
SH		 587 }
588
589 if (sky2->duplex == DUPLEX_FULL)
590 reg |= GM_GPCR_DUP_FULL;
ed6d32c7
SH		 591
592 /* turn off pause in 10/100mbps half duplex */
593 else if (sky2->speed != SPEED_1000 &&
594 hw->chip_id != CHIP_ID_YUKON_EC_U)
595 sky2->tx_pause = sky2->rx_pause = 0;
cd28ab6a
SH		 596 } else
597 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
598
599 if (!sky2->tx_pause && !sky2->rx_pause) {
600 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e
SH		 601 reg |=
602 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
603 } else if (sky2->tx_pause && !sky2->rx_pause) {
cd28ab6a
SH		 604 /* disable Rx flow-control */
605 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
606 }
607
608 gma_write16(hw, port, GM_GP_CTRL, reg);
609
793b883e 610 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 611
e07b1aa8 612 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 613 sky2_phy_init(hw, port);
e07b1aa8 614 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 615
616 /* MIB clear */
617 reg = gma_read16(hw, port, GM_PHY_ADDR);
618 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
619
43f2f104
SH		 620 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
621 gma_read16(hw, port, i);
cd28ab6a
SH		 622 gma_write16(hw, port, GM_PHY_ADDR, reg);
623
624 /* transmit control */
625 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
626
627 /* receive control reg: unicast + multicast + no FCS */
628 gma_write16(hw, port, GM_RX_CTRL,
793b883e 629 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 630
631 /* transmit flow control */
632 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
633
634 /* transmit parameter */
635 gma_write16(hw, port, GM_TX_PARAM,
636 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
637 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
638 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
639 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
640
641 /* serial mode register */
642 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 643 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 644
6b1a3aef 645 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 646 reg |= GM_SMOD_JUMBO_ENA;
647
648 gma_write16(hw, port, GM_SERIAL_MODE, reg);
649
cd28ab6a
SH		 650 /* virtual address for data */
651 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
652
793b883e
SH		 653 /* physical address: used for pause frames */
654 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
655
656 /* ignore counter overflows */
cd28ab6a
SH		 657 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
658 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
659 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
660
661 /* Configure Rx MAC FIFO */
662 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 663 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
664 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 665
d571b694 666 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 667 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 668
793b883e
SH		 669 /* Set threshold to 0xa (64 bytes)
670 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 671 */
672 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
673
674 /* Configure Tx MAC FIFO */
675 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
676 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 677
678 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
679 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
680 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
681 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
682 /* set Tx GMAC FIFO Almost Empty Threshold */
683 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
684 /* Disable Store & Forward mode for TX */
685 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
686 }
687 }
688
cd28ab6a
SH		 689}
690
1c28f6ba
SH		 691/* Assign Ram Buffer allocation.
692 * start and end are in units of 4k bytes
693 * ram registers are in units of 64bit words
694 */
695static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
cd28ab6a 696{
1c28f6ba 697 u32 start, end;
cd28ab6a 698
1c28f6ba
SH		 699 start = startk * 4096/8;
700 end = (endk * 4096/8) - 1;
793b883e 701
cd28ab6a
SH		 702 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
703 sky2_write32(hw, RB_ADDR(q, RB_START), start);
704 sky2_write32(hw, RB_ADDR(q, RB_END), end);
705 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
706 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
707
708 if (q == Q_R1 || q == Q_R2) {
1c28f6ba
SH		 709 u32 space = (endk - startk) * 4096/8;
710 u32 tp = space - space/4;
793b883e 711
1c28f6ba
SH		 712 /* On receive queue's set the thresholds
713 * give receiver priority when > 3/4 full
714 * send pause when down to 2K
715 */
716 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
717 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 718
1c28f6ba
SH		 719 tp = space - 2048/8;
720 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
721 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 722 } else {
723 /* Enable store & forward on Tx queue's because
724 * Tx FIFO is only 1K on Yukon
725 */
726 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
727 }
728
729 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 730 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 731}
732
cd28ab6a 733/* Setup Bus Memory Interface */
af4ed7e6 734static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 735{
736 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
737 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
738 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 739 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 740}
741
cd28ab6a
SH		 742/* Setup prefetch unit registers. This is the interface between
743 * hardware and driver list elements
744 */
8cc048e3 745static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 746 u64 addr, u32 last)
747{
cd28ab6a
SH		 748 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
749 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
750 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
751 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
752 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
753 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 754
755 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 756}
757
793b883e
SH		 758static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
759{
760 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
761
cb5d9547 762 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
793b883e
SH		 763 return le;
764}
cd28ab6a 765
290d4de5
SH		 766/* Update chip's next pointer */
767static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 768{
762c2de2 769 wmb();
290d4de5 770 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
762c2de2 771 mmiowb();
cd28ab6a
SH		 772}
773
793b883e 774
cd28ab6a
SH		 775static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
776{
777 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 778 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
cd28ab6a
SH		 779 return le;
780}
781
a018e330 782/* Return high part of DMA address (could be 32 or 64 bit) */
783static inline u32 high32(dma_addr_t a)
784{
a036119f 785 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330 786}
787
793b883e 788/* Build description to hardware about buffer */
28bd181a 789static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
cd28ab6a
SH		 790{
791 struct sky2_rx_le *le;
734d1868
SH		 792 u32 hi = high32(map);
793 u16 len = sky2->rx_bufsize;
cd28ab6a 794
793b883e 795 if (sky2->rx_addr64 != hi) {
cd28ab6a 796 le = sky2_next_rx(sky2);
793b883e 797 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 798 le->ctrl = 0;
799 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 800 sky2->rx_addr64 = high32(map + len);
cd28ab6a 801 }
793b883e 802
cd28ab6a 803 le = sky2_next_rx(sky2);
734d1868
SH		 804 le->addr = cpu_to_le32((u32) map);
805 le->length = cpu_to_le16(len);
cd28ab6a
SH		 806 le->ctrl = 0;
807 le->opcode = OP_PACKET | HW_OWNER;
808}
809
793b883e 810
cd28ab6a
SH		 811/* Tell chip where to start receive checksum.
812 * Actually has two checksums, but set both same to avoid possible byte
813 * order problems.
814 */
793b883e 815static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 816{
817 struct sky2_rx_le *le;
818
cd28ab6a 819 le = sky2_next_rx(sky2);
793b883e 820 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
cd28ab6a
SH		 821 le->ctrl = 0;
822 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 823
793b883e
SH		 824 sky2_write32(sky2->hw,
825 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
826 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 827
828}
829
6b1a3aef 830/*
831 * The RX Stop command will not work for Yukon-2 if the BMU does not
832 * reach the end of packet and since we can't make sure that we have
833 * incoming data, we must reset the BMU while it is not doing a DMA
834 * transfer. Since it is possible that the RX path is still active,
835 * the RX RAM buffer will be stopped first, so any possible incoming
836 * data will not trigger a DMA. After the RAM buffer is stopped, the
837 * BMU is polled until any DMA in progress is ended and only then it
838 * will be reset.
839 */
840static void sky2_rx_stop(struct sky2_port *sky2)
841{
842 struct sky2_hw *hw = sky2->hw;
843 unsigned rxq = rxqaddr[sky2->port];
844 int i;
845
846 /* disable the RAM Buffer receive queue */
847 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
848
849 for (i = 0; i < 0xffff; i++)
850 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
851 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
852 goto stopped;
853
854 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
855 sky2->netdev->name);
856stopped:
857 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
858
859 /* reset the Rx prefetch unit */
860 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
861}
793b883e 862
d571b694 863/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 864static void sky2_rx_clean(struct sky2_port *sky2)
865{
866 unsigned i;
867
868 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 869 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 870 struct ring_info *re = sky2->rx_ring + i;
871
872 if (re->skb) {
793b883e 873 pci_unmap_single(sky2->hw->pdev,
734d1868 874 re->mapaddr, sky2->rx_bufsize,
cd28ab6a
SH		 875 PCI_DMA_FROMDEVICE);
876 kfree_skb(re->skb);
877 re->skb = NULL;
878 }
879 }
880}
881
ef743d33 882/* Basic MII support */
883static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
884{
885 struct mii_ioctl_data *data = if_mii(ifr);
886 struct sky2_port *sky2 = netdev_priv(dev);
887 struct sky2_hw *hw = sky2->hw;
888 int err = -EOPNOTSUPP;
889
890 if (!netif_running(dev))
891 return -ENODEV; /* Phy still in reset */
892
d89e1343 893 switch (cmd) {
ef743d33 894 case SIOCGMIIPHY:
895 data->phy_id = PHY_ADDR_MARV;
896
897 /* fallthru */
898 case SIOCGMIIREG: {
899 u16 val = 0;
91c86df5 900
e07b1aa8 901 spin_lock_bh(&sky2->phy_lock);
ef743d33 902 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 903 spin_unlock_bh(&sky2->phy_lock);
91c86df5 904
ef743d33 905 data->val_out = val;
906 break;
907 }
908
909 case SIOCSMIIREG:
910 if (!capable(CAP_NET_ADMIN))
911 return -EPERM;
912
e07b1aa8 913 spin_lock_bh(&sky2->phy_lock);
ef743d33 914 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
915 data->val_in);
e07b1aa8 916 spin_unlock_bh(&sky2->phy_lock);
ef743d33 917 break;
918 }
919 return err;
920}
921
d1f13708 922#ifdef SKY2_VLAN_TAG_USED
923static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
924{
925 struct sky2_port *sky2 = netdev_priv(dev);
926 struct sky2_hw *hw = sky2->hw;
927 u16 port = sky2->port;
d1f13708 928
302d1252 929 spin_lock_bh(&sky2->tx_lock);
d1f13708 930
931 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
932 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
933 sky2->vlgrp = grp;
934
302d1252 935 spin_unlock_bh(&sky2->tx_lock);
d1f13708 936}
937
938static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
939{
940 struct sky2_port *sky2 = netdev_priv(dev);
941 struct sky2_hw *hw = sky2->hw;
942 u16 port = sky2->port;
d1f13708 943
302d1252 944 spin_lock_bh(&sky2->tx_lock);
d1f13708 945
946 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
947 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
948 if (sky2->vlgrp)
949 sky2->vlgrp->vlan_devices[vid] = NULL;
950
302d1252 951 spin_unlock_bh(&sky2->tx_lock);
d1f13708 952}
953#endif
954
82788c7a
SH		 955/*
956 * It appears the hardware has a bug in the FIFO logic that
957 * cause it to hang if the FIFO gets overrun and the receive buffer
958 * is not aligned. ALso alloc_skb() won't align properly if slab
959 * debugging is enabled.
960 */
961static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
962{
963 struct sk_buff *skb;
964
965 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
966 if (likely(skb)) {
967 unsigned long p = (unsigned long) skb->data;
4a15d56f 968 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
82788c7a
SH		 969 }
970
971 return skb;
972}
973
cd28ab6a
SH		 974/*
975 * Allocate and setup receiver buffer pool.
976 * In case of 64 bit dma, there are 2X as many list elements
977 * available as ring entries
978 * and need to reserve one list element so we don't wrap around.
979 */
6b1a3aef 980static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 981{
6b1a3aef 982 struct sky2_hw *hw = sky2->hw;
6b1a3aef 983 unsigned rxq = rxqaddr[sky2->port];
984 int i;
a1433ac4 985 unsigned thresh;
cd28ab6a 986
6b1a3aef 987 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 988 sky2_qset(hw, rxq);
977bdf06
SH		 989
990 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
991 /* MAC Rx RAM Read is controlled by hardware */
992 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
993 }
994
6b1a3aef 995 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
996
997 rx_set_checksum(sky2);
793b883e 998 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 999 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 1000
82788c7a 1001 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
cd28ab6a
SH		 1002 if (!re->skb)
1003 goto nomem;
1004
6b1a3aef 1005 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
734d1868
SH		 1006 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1007 sky2_rx_add(sky2, re->mapaddr);
cd28ab6a
SH		 1008 }
1009
a1433ac4
SH		 1010
1011 /*
1012 * The receiver hangs if it receives frames larger than the
1013 * packet buffer. As a workaround, truncate oversize frames, but
1014 * the register is limited to 9 bits, so if you do frames > 2052
1015 * you better get the MTU right!
1016 */
1017 thresh = (sky2->rx_bufsize - 8) / sizeof(u32);
1018 if (thresh > 0x1ff)
1019 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1020 else {
1021 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1022 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1023 }
1024
70f1be48 1025
6b1a3aef 1026 /* Tell chip about available buffers */
1027 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1028 return 0;
1029nomem:
1030 sky2_rx_clean(sky2);
1031 return -ENOMEM;
1032}
1033
1034/* Bring up network interface. */
1035static int sky2_up(struct net_device *dev)
1036{
1037 struct sky2_port *sky2 = netdev_priv(dev);
1038 struct sky2_hw *hw = sky2->hw;
1039 unsigned port = sky2->port;
e07b1aa8 1040 u32 ramsize, rxspace, imask;
ee7abb04 1041 int cap, err = -ENOMEM;
843a46f4 1042 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1043
ee7abb04
SH		 1044 /*
1045 * On dual port PCI-X card, there is an problem where status
1046 * can be received out of order due to split transactions
843a46f4 1047 */
ee7abb04
SH		 1048 if (otherdev && netif_running(otherdev) &&
1049 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1050 struct sky2_port *osky2 = netdev_priv(otherdev);
1051 u16 cmd;
1052
1053 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1054 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1055 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1056
1057 sky2->rx_csum = 0;
1058 osky2->rx_csum = 0;
1059 }
843a46f4 1060
cd28ab6a
SH		 1061 if (netif_msg_ifup(sky2))
1062 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1063
1064 /* must be power of 2 */
1065 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1066 TX_RING_SIZE *
1067 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1068 &sky2->tx_le_map);
1069 if (!sky2->tx_le)
1070 goto err_out;
1071
6cdbbdf3 1072 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1073 GFP_KERNEL);
1074 if (!sky2->tx_ring)
1075 goto err_out;
1076 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1077
1078 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1079 &sky2->rx_le_map);
1080 if (!sky2->rx_le)
1081 goto err_out;
1082 memset(sky2->rx_le, 0, RX_LE_BYTES);
1083
6cdbbdf3 1084 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
cd28ab6a
SH		 1085 GFP_KERNEL);
1086 if (!sky2->rx_ring)
1087 goto err_out;
1088
1089 sky2_mac_init(hw, port);
1090
1c28f6ba
SH		 1091 /* Determine available ram buffer space (in 4K blocks).
1092 * Note: not sure about the FE setting below yet
1093 */
1094 if (hw->chip_id == CHIP_ID_YUKON_FE)
1095 ramsize = 4;
1096 else
1097 ramsize = sky2_read8(hw, B2_E_0);
1098
1099 /* Give transmitter one third (rounded up) */
1100 rxspace = ramsize - (ramsize + 2) / 3;
cd28ab6a 1101
cd28ab6a 1102 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1c28f6ba 1103 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
cd28ab6a 1104
793b883e
SH		 1105 /* Make sure SyncQ is disabled */
1106 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1107 RB_RST_SET);
1108
af4ed7e6 1109 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1110
977bdf06
SH		 1111 /* Set almost empty threshold */
1112 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1113 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1114
6b1a3aef 1115 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1116 TX_RING_SIZE - 1);
cd28ab6a 1117
6b1a3aef 1118 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1119 if (err)
1120 goto err_out;
1121
cd28ab6a 1122 /* Enable interrupts from phy/mac for port */
e07b1aa8 1123 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1124 imask |= portirq_msk[port];
e07b1aa8
SH		 1125 sky2_write32(hw, B0_IMSK, imask);
1126
cd28ab6a
SH		 1127 return 0;
1128
1129err_out:
1b537565 1130 if (sky2->rx_le) {
cd28ab6a
SH		 1131 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1132 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1133 sky2->rx_le = NULL;
1134 }
1135 if (sky2->tx_le) {
cd28ab6a
SH		 1136 pci_free_consistent(hw->pdev,
1137 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1138 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1139 sky2->tx_le = NULL;
1140 }
1141 kfree(sky2->tx_ring);
1142 kfree(sky2->rx_ring);
cd28ab6a 1143
1b537565
SH		 1144 sky2->tx_ring = NULL;
1145 sky2->rx_ring = NULL;
cd28ab6a
SH		 1146 return err;
1147}
1148
793b883e
SH		 1149/* Modular subtraction in ring */
1150static inline int tx_dist(unsigned tail, unsigned head)
1151{
cb5d9547 1152 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1153}
cd28ab6a 1154
793b883e
SH		 1155/* Number of list elements available for next tx */
1156static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1157{
793b883e 1158 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1159}
1160
793b883e 1161/* Estimate of number of transmit list elements required */
28bd181a 1162static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1163{
793b883e
SH		 1164 unsigned count;
1165
1166 count = sizeof(dma_addr_t) / sizeof(u32);
1167 count += skb_shinfo(skb)->nr_frags * count;
1168
89114afd 1169 if (skb_is_gso(skb))
793b883e
SH		 1170 ++count;
1171
0e3ff6aa 1172 if (skb->ip_summed == CHECKSUM_HW)
793b883e
SH		 1173 ++count;
1174
1175 return count;
cd28ab6a
SH		 1176}
1177
793b883e
SH		 1178/*
1179 * Put one packet in ring for transmit.
1180 * A single packet can generate multiple list elements, and
1181 * the number of ring elements will probably be less than the number
1182 * of list elements used.
f2e46561
SH		 1183 *
1184 * No BH disabling for tx_lock here (like tg3)
793b883e 1185 */
cd28ab6a
SH		 1186static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1187{
1188 struct sky2_port *sky2 = netdev_priv(dev);
1189 struct sky2_hw *hw = sky2->hw;
d1f13708 1190 struct sky2_tx_le *le = NULL;
6cdbbdf3 1191 struct tx_ring_info *re;
cd28ab6a 1192 unsigned i, len;
b19666d9 1193 int avail;
cd28ab6a
SH		 1194 dma_addr_t mapping;
1195 u32 addr64;
1196 u16 mss;
1197 u8 ctrl;
1198
302d1252
SH		 1199 /* No BH disabling for tx_lock here. We are running in BH disabled
1200 * context and TX reclaim runs via poll inside of a software
1201 * interrupt, and no related locks in IRQ processing.
1202 */
f2e46561 1203 if (!spin_trylock(&sky2->tx_lock))
cd28ab6a
SH		 1204 return NETDEV_TX_LOCKED;
1205
793b883e 1206 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
8c463ef7
SH		 1207 /* There is a known but harmless race with lockless tx
1208 * and netif_stop_queue.
1209 */
1210 if (!netif_queue_stopped(dev)) {
1211 netif_stop_queue(dev);
3be92a70
SH		 1212 if (net_ratelimit())
1213 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1214 dev->name);
8c463ef7 1215 }
f2e46561 1216 spin_unlock(&sky2->tx_lock);
cd28ab6a 1217
cd28ab6a
SH		 1218 return NETDEV_TX_BUSY;
1219 }
1220
793b883e 1221 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1222 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1223 dev->name, sky2->tx_prod, skb->len);
1224
cd28ab6a
SH		 1225 len = skb_headlen(skb);
1226 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1227 addr64 = high32(mapping);
793b883e
SH		 1228
1229 re = sky2->tx_ring + sky2->tx_prod;
1230
a018e330 1231 /* Send high bits if changed or crosses boundary */
1232 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e
SH		 1233 le = get_tx_le(sky2);
1234 le->tx.addr = cpu_to_le32(addr64);
1235 le->ctrl = 0;
1236 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1237 sky2->tx_addr64 = high32(mapping + len);
793b883e 1238 }
cd28ab6a
SH		 1239
1240 /* Check for TCP Segmentation Offload */
7967168c 1241 mss = skb_shinfo(skb)->gso_size;
793b883e 1242 if (mss != 0) {
cd28ab6a
SH		 1243 /* just drop the packet if non-linear expansion fails */
1244 if (skb_header_cloned(skb) &&
1245 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
15240072 1246 dev_kfree_skb(skb);
793b883e 1247 goto out_unlock;
cd28ab6a
SH		 1248 }
1249
1250 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1251 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1252 mss += ETH_HLEN;
793b883e 1253 }
cd28ab6a 1254
793b883e 1255 if (mss != sky2->tx_last_mss) {
cd28ab6a
SH		 1256 le = get_tx_le(sky2);
1257 le->tx.tso.size = cpu_to_le16(mss);
793b883e 1258 le->tx.tso.rsvd = 0;
cd28ab6a 1259 le->opcode = OP_LRGLEN | HW_OWNER;
cd28ab6a 1260 le->ctrl = 0;
793b883e 1261 sky2->tx_last_mss = mss;
cd28ab6a
SH		 1262 }
1263
cd28ab6a 1264 ctrl = 0;
d1f13708 1265#ifdef SKY2_VLAN_TAG_USED
1266 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1267 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1268 if (!le) {
1269 le = get_tx_le(sky2);
1270 le->tx.addr = 0;
1271 le->opcode = OP_VLAN|HW_OWNER;
1272 le->ctrl = 0;
1273 } else
1274 le->opcode |= OP_VLAN;
1275 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1276 ctrl |= INS_VLAN;
1277 }
1278#endif
1279
1280 /* Handle TCP checksum offload */
cd28ab6a 1281 if (skb->ip_summed == CHECKSUM_HW) {
793b883e
SH		 1282 u16 hdr = skb->h.raw - skb->data;
1283 u16 offset = hdr + skb->csum;
cd28ab6a
SH		 1284
1285 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1286 if (skb->nh.iph->protocol == IPPROTO_UDP)
1287 ctrl |= UDPTCP;
1288
1289 le = get_tx_le(sky2);
1290 le->tx.csum.start = cpu_to_le16(hdr);
793b883e
SH		 1291 le->tx.csum.offset = cpu_to_le16(offset);
1292 le->length = 0; /* initial checksum value */
cd28ab6a 1293 le->ctrl = 1; /* one packet */
793b883e 1294 le->opcode = OP_TCPLISW | HW_OWNER;
cd28ab6a
SH		 1295 }
1296
1297 le = get_tx_le(sky2);
1298 le->tx.addr = cpu_to_le32((u32) mapping);
1299 le->length = cpu_to_le16(len);
1300 le->ctrl = ctrl;
793b883e 1301 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1302
793b883e 1303 /* Record the transmit mapping info */
cd28ab6a 1304 re->skb = skb;
6cdbbdf3 1305 pci_unmap_addr_set(re, mapaddr, mapping);
cd28ab6a
SH		 1306
1307 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1308 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6cdbbdf3 1309 struct tx_ring_info *fre;
cd28ab6a
SH		 1310
1311 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1312 frag->size, PCI_DMA_TODEVICE);
a036119f 1313 addr64 = high32(mapping);
793b883e
SH		 1314 if (addr64 != sky2->tx_addr64) {
1315 le = get_tx_le(sky2);
1316 le->tx.addr = cpu_to_le32(addr64);
1317 le->ctrl = 0;
1318 le->opcode = OP_ADDR64 | HW_OWNER;
1319 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1320 }
1321
1322 le = get_tx_le(sky2);
1323 le->tx.addr = cpu_to_le32((u32) mapping);
1324 le->length = cpu_to_le16(frag->size);
1325 le->ctrl = ctrl;
793b883e 1326 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1327
793b883e 1328 fre = sky2->tx_ring
cb5d9547 1329 + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
6cdbbdf3 1330 pci_unmap_addr_set(fre, mapaddr, mapping);
cd28ab6a 1331 }
6cdbbdf3 1332
793b883e 1333 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1334 le->ctrl |= EOP;
1335
b19666d9
SH		 1336 avail = tx_avail(sky2);
1337 if (mss != 0 || avail < TX_MIN_PENDING) {
1338 le->ctrl |= FRC_STAT;
1339 if (avail <= MAX_SKB_TX_LE)
1340 netif_stop_queue(dev);
1341 }
1342
290d4de5 1343 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1344
793b883e 1345out_unlock:
f2e46561 1346 spin_unlock(&sky2->tx_lock);
cd28ab6a
SH		 1347
1348 dev->trans_start = jiffies;
1349 return NETDEV_TX_OK;
1350}
1351
cd28ab6a 1352/*
793b883e
SH		 1353 * Free ring elements from starting at tx_cons until "done"
1354 *
1355 * NB: the hardware will tell us about partial completion of multi-part
d571b694 1356 * buffers; these are deferred until completion.
cd28ab6a 1357 */
d11c13e7 1358static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1359{
d11c13e7 1360 struct net_device *dev = sky2->netdev;
af2a58ac
SH		 1361 struct pci_dev *pdev = sky2->hw->pdev;
1362 u16 nxt, put;
793b883e 1363 unsigned i;
cd28ab6a 1364
0e3ff6aa 1365 BUG_ON(done >= TX_RING_SIZE);
2224795d 1366
d11c13e7 1367 if (unlikely(netif_msg_tx_done(sky2)))
d571b694 1368 printk(KERN_DEBUG "%s: tx done, up to %u\n",
d11c13e7 1369 dev->name, done);
cd28ab6a 1370
af2a58ac
SH		 1371 for (put = sky2->tx_cons; put != done; put = nxt) {
1372 struct tx_ring_info *re = sky2->tx_ring + put;
1373 struct sk_buff *skb = re->skb;
cd28ab6a 1374
d89e1343 1375 nxt = re->idx;
af2a58ac 1376 BUG_ON(nxt >= TX_RING_SIZE);
d70cd51a 1377 prefetch(sky2->tx_ring + nxt);
cd28ab6a 1378
793b883e 1379 /* Check for partial status */
af2a58ac
SH		 1380 if (tx_dist(put, done) < tx_dist(put, nxt))
1381 break;
793b883e
SH		 1382
1383 skb = re->skb;
af2a58ac 1384 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
734d1868 1385 skb_headlen(skb), PCI_DMA_TODEVICE);
793b883e
SH		 1386
1387 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6cdbbdf3 1388 struct tx_ring_info *fre;
cb5d9547 1389 fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
af2a58ac 1390 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
d89e1343 1391 skb_shinfo(skb)->frags[i].size,
734d1868 1392 PCI_DMA_TODEVICE);
cd28ab6a
SH		 1393 }
1394
15240072 1395 dev_kfree_skb(skb);
793b883e 1396 }
793b883e 1397
af2a58ac 1398 sky2->tx_cons = put;
22e11703 1399 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1400 netif_wake_queue(dev);
cd28ab6a
SH		 1401}
1402
1403/* Cleanup all untransmitted buffers, assume transmitter not running */
13b97b74 1404static void sky2_tx_clean(struct sky2_port *sky2)
cd28ab6a 1405{
302d1252 1406 spin_lock_bh(&sky2->tx_lock);
d11c13e7 1407 sky2_tx_complete(sky2, sky2->tx_prod);
302d1252 1408 spin_unlock_bh(&sky2->tx_lock);
cd28ab6a
SH		 1409}
1410
1411/* Network shutdown */
1412static int sky2_down(struct net_device *dev)
1413{
1414 struct sky2_port *sky2 = netdev_priv(dev);
1415 struct sky2_hw *hw = sky2->hw;
1416 unsigned port = sky2->port;
1417 u16 ctrl;
e07b1aa8 1418 u32 imask;
cd28ab6a 1419
1b537565
SH		 1420 /* Never really got started! */
1421 if (!sky2->tx_le)
1422 return 0;
1423
cd28ab6a
SH		 1424 if (netif_msg_ifdown(sky2))
1425 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1426
018d1c66 1427 /* Stop more packets from being queued */
cd28ab6a
SH		 1428 netif_stop_queue(dev);
1429
793b883e
SH		 1430 sky2_phy_reset(hw, port);
1431
cd28ab6a
SH		 1432 /* Stop transmitter */
1433 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1434 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1435
1436 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1437 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1438
1439 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1440 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1441 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1442
1443 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1444
1445 /* Workaround shared GMAC reset */
793b883e
SH		 1446 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1447 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1448 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1449
1450 /* Disable Force Sync bit and Enable Alloc bit */
1451 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1452 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1453
1454 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1455 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1456 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1457
1458 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1459 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1460 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1461
1462 /* Reset the Tx prefetch units */
1463 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1464 PREF_UNIT_RST_SET);
1465
1466 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1467
6b1a3aef 1468 sky2_rx_stop(sky2);
cd28ab6a
SH		 1469
1470 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1471 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1472
e07b1aa8
SH		 1473 /* Disable port IRQ */
1474 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1475 imask &= ~portirq_msk[port];
e07b1aa8
SH		 1476 sky2_write32(hw, B0_IMSK, imask);
1477
d571b694 1478 /* turn off LED's */
cd28ab6a
SH		 1479 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1480
018d1c66 1481 synchronize_irq(hw->pdev->irq);
1482
cd28ab6a
SH		 1483 sky2_tx_clean(sky2);
1484 sky2_rx_clean(sky2);
1485
1486 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1487 sky2->rx_le, sky2->rx_le_map);
1488 kfree(sky2->rx_ring);
1489
1490 pci_free_consistent(hw->pdev,
1491 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1492 sky2->tx_le, sky2->tx_le_map);
1493 kfree(sky2->tx_ring);
1494
1b537565
SH		 1495 sky2->tx_le = NULL;
1496 sky2->rx_le = NULL;
1497
1498 sky2->rx_ring = NULL;
1499 sky2->tx_ring = NULL;
1500
cd28ab6a
SH		 1501 return 0;
1502}
1503
1504static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1505{
793b883e
SH		 1506 if (!hw->copper)
1507 return SPEED_1000;
1508
cd28ab6a
SH		 1509 if (hw->chip_id == CHIP_ID_YUKON_FE)
1510 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1511
1512 switch (aux & PHY_M_PS_SPEED_MSK) {
1513 case PHY_M_PS_SPEED_1000:
1514 return SPEED_1000;
1515 case PHY_M_PS_SPEED_100:
1516 return SPEED_100;
1517 default:
1518 return SPEED_10;
1519 }
1520}
1521
1522static void sky2_link_up(struct sky2_port *sky2)
1523{
1524 struct sky2_hw *hw = sky2->hw;
1525 unsigned port = sky2->port;
1526 u16 reg;
1527
1528 /* Enable Transmit FIFO Underrun */
793b883e 1529 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
cd28ab6a
SH		 1530
1531 reg = gma_read16(hw, port, GM_GP_CTRL);
6f4c56b2
SH		 1532 if (sky2->autoneg == AUTONEG_DISABLE) {
1533 reg |= GM_GPCR_AU_ALL_DIS;
1534
1535 /* Is write/read necessary? Copied from sky2_mac_init */
1536 gma_write16(hw, port, GM_GP_CTRL, reg);
1537 gma_read16(hw, port, GM_GP_CTRL);
1538
1539 switch (sky2->speed) {
1540 case SPEED_1000:
1541 reg &= ~GM_GPCR_SPEED_100;
1542 reg |= GM_GPCR_SPEED_1000;
1543 break;
1544 case SPEED_100:
1545 reg &= ~GM_GPCR_SPEED_1000;
1546 reg |= GM_GPCR_SPEED_100;
1547 break;
1548 case SPEED_10:
1549 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1550 break;
1551 }
1552 } else
1553 reg &= ~GM_GPCR_AU_ALL_DIS;
1554
cd28ab6a
SH		 1555 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1556 reg |= GM_GPCR_DUP_FULL;
1557
cd28ab6a
SH		 1558 /* enable Rx/Tx */
1559 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1560 gma_write16(hw, port, GM_GP_CTRL, reg);
1561 gma_read16(hw, port, GM_GP_CTRL);
1562
1563 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1564
1565 netif_carrier_on(sky2->netdev);
1566 netif_wake_queue(sky2->netdev);
1567
1568 /* Turn on link LED */
793b883e 1569 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1570 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1571
ed6d32c7 1572 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
793b883e 1573 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1574 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1575
1576 switch(sky2->speed) {
1577 case SPEED_10:
1578 led |= PHY_M_LEDC_INIT_CTRL(7);
1579 break;
1580
1581 case SPEED_100:
1582 led |= PHY_M_LEDC_STA1_CTRL(7);
1583 break;
1584
1585 case SPEED_1000:
1586 led |= PHY_M_LEDC_STA0_CTRL(7);
1587 break;
1588 }
793b883e
SH		 1589
1590 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1591 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1592 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1593 }
1594
cd28ab6a
SH		 1595 if (netif_msg_link(sky2))
1596 printk(KERN_INFO PFX
d571b694 1597 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1598 sky2->netdev->name, sky2->speed,
1599 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1600 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1601 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1602}
1603
1604static void sky2_link_down(struct sky2_port *sky2)
1605{
1606 struct sky2_hw *hw = sky2->hw;
1607 unsigned port = sky2->port;
1608 u16 reg;
1609
1610 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1611
1612 reg = gma_read16(hw, port, GM_GP_CTRL);
1613 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1614 gma_write16(hw, port, GM_GP_CTRL, reg);
1615 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1616
1617 if (sky2->rx_pause && !sky2->tx_pause) {
1618 /* restore Asymmetric Pause bit */
1619 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1620 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1621 | PHY_M_AN_ASP);
cd28ab6a
SH		 1622 }
1623
cd28ab6a
SH		 1624 netif_carrier_off(sky2->netdev);
1625 netif_stop_queue(sky2->netdev);
1626
1627 /* Turn on link LED */
1628 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1629
1630 if (netif_msg_link(sky2))
1631 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1632 sky2_phy_init(hw, port);
1633}
1634
793b883e
SH		 1635static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1636{
1637 struct sky2_hw *hw = sky2->hw;
1638 unsigned port = sky2->port;
1639 u16 lpa;
1640
1641 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1642
1643 if (lpa & PHY_M_AN_RF) {
1644 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1645 return -1;
1646 }
1647
1648 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1649 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1650 printk(KERN_ERR PFX "%s: master/slave fault",
1651 sky2->netdev->name);
1652 return -1;
1653 }
1654
1655 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1656 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1657 sky2->netdev->name);
1658 return -1;
1659 }
1660
1661 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1662
1663 sky2->speed = sky2_phy_speed(hw, aux);
1664
1665 /* Pause bits are offset (9..8) */
ed6d32c7 1666 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
793b883e
SH		 1667 aux >>= 6;
1668
1669 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1670 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1671
1672 if ((sky2->tx_pause || sky2->rx_pause)
1673 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1674 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1675 else
1676 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1677
1678 return 0;
1679}
cd28ab6a 1680
e07b1aa8
SH		 1681/* Interrupt from PHY */
1682static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1683{
e07b1aa8
SH		 1684 struct net_device *dev = hw->dev[port];
1685 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1686 u16 istatus, phystat;
1687
e07b1aa8
SH		 1688 spin_lock(&sky2->phy_lock);
1689 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1690 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1691
1692 if (!netif_running(dev))
1693 goto out;
cd28ab6a
SH		 1694
1695 if (netif_msg_intr(sky2))
1696 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1697 sky2->netdev->name, istatus, phystat);
1698
1699 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 1700 if (sky2_autoneg_done(sky2, phystat) == 0)
1701 sky2_link_up(sky2);
1702 goto out;
1703 }
cd28ab6a 1704
793b883e
SH		 1705 if (istatus & PHY_M_IS_LSP_CHANGE)
1706 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1707
793b883e
SH		 1708 if (istatus & PHY_M_IS_DUP_CHANGE)
1709 sky2->duplex =
1710 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1711
793b883e
SH		 1712 if (istatus & PHY_M_IS_LST_CHANGE) {
1713 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1714 sky2_link_up(sky2);
793b883e
SH		 1715 else
1716 sky2_link_down(sky2);
cd28ab6a 1717 }
793b883e 1718out:
e07b1aa8 1719 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1720}
1721
302d1252
SH		 1722
1723/* Transmit timeout is only called if we are running, carries is up
1724 * and tx queue is full (stopped).
1725 */
cd28ab6a
SH		 1726static void sky2_tx_timeout(struct net_device *dev)
1727{
1728 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1729 struct sky2_hw *hw = sky2->hw;
1730 unsigned txq = txqaddr[sky2->port];
8f24664d 1731 u16 report, done;
cd28ab6a
SH		 1732
1733 if (netif_msg_timer(sky2))
1734 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1735
8f24664d
SH		 1736 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1737 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1738
8f24664d
SH		 1739 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1740 dev->name,
1741 sky2->tx_cons, sky2->tx_prod, report, done);
1742
1743 if (report != done) {
1744 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1745
1746 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1747 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1748 } else if (report != sky2->tx_cons) {
1749 printk(KERN_INFO PFX "status report lost?\n");
1750
1751 spin_lock_bh(&sky2->tx_lock);
1752 sky2_tx_complete(sky2, report);
1753 spin_unlock_bh(&sky2->tx_lock);
1754 } else {
1755 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1756
8f24664d
SH		 1757 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1758 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1759
1760 sky2_tx_clean(sky2);
1761
1762 sky2_qset(hw, txq);
1763 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1764 }
cd28ab6a
SH		 1765}
1766
734d1868 1767
70f1be48
SH		 1768/* Want receive buffer size to be multiple of 64 bits
1769 * and incl room for vlan and truncation
1770 */
734d1868
SH		 1771static inline unsigned sky2_buf_size(int mtu)
1772{
4a15d56f 1773 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
734d1868
SH		 1774}
1775
cd28ab6a
SH		 1776static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1777{
6b1a3aef 1778 struct sky2_port *sky2 = netdev_priv(dev);
1779 struct sky2_hw *hw = sky2->hw;
1780 int err;
1781 u16 ctl, mode;
e07b1aa8 1782 u32 imask;
cd28ab6a
SH		 1783
1784 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1785 return -EINVAL;
1786
5a5b1ea0 1787 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1788 return -EINVAL;
1789
6b1a3aef 1790 if (!netif_running(dev)) {
1791 dev->mtu = new_mtu;
1792 return 0;
1793 }
1794
e07b1aa8 1795 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 1796 sky2_write32(hw, B0_IMSK, 0);
1797
018d1c66 1798 dev->trans_start = jiffies; /* prevent tx timeout */
1799 netif_stop_queue(dev);
1800 netif_poll_disable(hw->dev[0]);
1801
e07b1aa8
SH		 1802 synchronize_irq(hw->pdev->irq);
1803
6b1a3aef 1804 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1805 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1806 sky2_rx_stop(sky2);
1807 sky2_rx_clean(sky2);
cd28ab6a
SH		 1808
1809 dev->mtu = new_mtu;
734d1868 1810 sky2->rx_bufsize = sky2_buf_size(new_mtu);
6b1a3aef 1811 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1812 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1813
1814 if (dev->mtu > ETH_DATA_LEN)
1815 mode |= GM_SMOD_JUMBO_ENA;
1816
1817 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1818
6b1a3aef 1819 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1820
6b1a3aef 1821 err = sky2_rx_start(sky2);
e07b1aa8 1822 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1823
1b537565
SH		 1824 if (err)
1825 dev_close(dev);
1826 else {
1827 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1828
1829 netif_poll_enable(hw->dev[0]);
1830 netif_wake_queue(dev);
1831 }
1832
cd28ab6a
SH		 1833 return err;
1834}
1835
1836/*
1837 * Receive one packet.
1838 * For small packets or errors, just reuse existing skb.
d571b694 1839 * For larger packets, get new buffer.
cd28ab6a 1840 */
d11c13e7 1841static struct sk_buff *sky2_receive(struct sky2_port *sky2,
cd28ab6a
SH		 1842 u16 length, u32 status)
1843{
cd28ab6a 1844 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1845 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1846
1847 if (unlikely(netif_msg_rx_status(sky2)))
1848 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
d11c13e7 1849 sky2->netdev->name, sky2->rx_next, status, length);
cd28ab6a 1850
793b883e 1851 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1852 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1853
42eeea01 1854 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1855 goto error;
1856
42eeea01 1857 if (!(status & GMR_FS_RX_OK))
1858 goto resubmit;
1859
70f1be48 1860 if (length > sky2->netdev->mtu + ETH_HLEN)
6e15b712
SH		 1861 goto oversize;
1862
bdb5c58e 1863 if (length < copybreak) {
79e57d32
SH		 1864 skb = alloc_skb(length + 2, GFP_ATOMIC);
1865 if (!skb)
793b883e
SH		 1866 goto resubmit;
1867
79e57d32 1868 skb_reserve(skb, 2);
793b883e
SH		 1869 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1870 length, PCI_DMA_FROMDEVICE);
79e57d32 1871 memcpy(skb->data, re->skb->data, length);
d11c13e7 1872 skb->ip_summed = re->skb->ip_summed;
1873 skb->csum = re->skb->csum;
793b883e
SH		 1874 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1875 length, PCI_DMA_FROMDEVICE);
793b883e 1876 } else {
79e57d32
SH		 1877 struct sk_buff *nskb;
1878
82788c7a 1879 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
793b883e
SH		 1880 if (!nskb)
1881 goto resubmit;
cd28ab6a 1882
793b883e 1883 skb = re->skb;
79e57d32 1884 re->skb = nskb;
793b883e 1885 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
734d1868 1886 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1887 prefetch(skb->data);
cd28ab6a 1888
793b883e 1889 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
734d1868 1890 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1891 }
cd28ab6a 1892
79e57d32 1893 skb_put(skb, length);
793b883e 1894resubmit:
d11c13e7 1895 re->skb->ip_summed = CHECKSUM_NONE;
734d1868 1896 sky2_rx_add(sky2, re->mapaddr);
79e57d32 1897
cd28ab6a
SH		 1898 return skb;
1899
6e15b712
SH		 1900oversize:
1901 ++sky2->net_stats.rx_over_errors;
1902 goto resubmit;
1903
cd28ab6a 1904error:
6e15b712
SH		 1905 ++sky2->net_stats.rx_errors;
1906
3be92a70 1907 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a
SH		 1908 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1909 sky2->netdev->name, status, length);
793b883e
SH		 1910
1911 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1912 sky2->net_stats.rx_length_errors++;
1913 if (status & GMR_FS_FRAGMENT)
1914 sky2->net_stats.rx_frame_errors++;
1915 if (status & GMR_FS_CRC_ERR)
1916 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1917 if (status & GMR_FS_RX_FF_OV)
1918 sky2->net_stats.rx_fifo_errors++;
79e57d32 1919
793b883e 1920 goto resubmit;
cd28ab6a
SH		 1921}
1922
e07b1aa8
SH		 1923/* Transmit complete */
1924static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 1925{
e07b1aa8 1926 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 1927
e07b1aa8
SH		 1928 if (netif_running(dev)) {
1929 spin_lock(&sky2->tx_lock);
1930 sky2_tx_complete(sky2, last);
1931 spin_unlock(&sky2->tx_lock);
2224795d 1932 }
cd28ab6a
SH		 1933}
1934
86fba634
SH		 1935/* Is status ring empty or is there more to do? */
1936static inline int sky2_more_work(const struct sky2_hw *hw)
1937{
1938 return (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX));
1939}
1940
e07b1aa8
SH		 1941/* Process status response ring */
1942static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 1943{
22e11703 1944 struct sky2_port *sky2;
e07b1aa8 1945 int work_done = 0;
22e11703 1946 unsigned buf_write[2] = { 0, 0 };
e71ebd73 1947 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 1948
af2a58ac 1949 rmb();
bea86103 1950
e71ebd73 1951 while (hw->st_idx != hwidx) {
13210ce5 1952 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1953 struct net_device *dev;
cd28ab6a 1954 struct sk_buff *skb;
cd28ab6a
SH		 1955 u32 status;
1956 u16 length;
1957
cb5d9547 1958 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 1959
e71ebd73
SH		 1960 BUG_ON(le->link >= 2);
1961 dev = hw->dev[le->link];
13210ce5 1962
1963 sky2 = netdev_priv(dev);
e07b1aa8
SH		 1964 length = le->length;
1965 status = le->status;
cd28ab6a 1966
e71ebd73 1967 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 1968 case OP_RXSTAT:
d11c13e7 1969 skb = sky2_receive(sky2, length, status);
d1f13708 1970 if (!skb)
1971 break;
13210ce5 1972
1973 skb->dev = dev;
1974 skb->protocol = eth_type_trans(skb, dev);
1975 dev->last_rx = jiffies;
1976
d1f13708 1977#ifdef SKY2_VLAN_TAG_USED
1978 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1979 vlan_hwaccel_receive_skb(skb,
1980 sky2->vlgrp,
1981 be16_to_cpu(sky2->rx_tag));
1982 } else
1983#endif
cd28ab6a 1984 netif_receive_skb(skb);
13210ce5 1985
22e11703
SH		 1986 /* Update receiver after 16 frames */
1987 if (++buf_write[le->link] == RX_BUF_WRITE) {
1988 sky2_put_idx(hw, rxqaddr[le->link],
1989 sky2->rx_put);
1990 buf_write[le->link] = 0;
1991 }
1992
1993 /* Stop after net poll weight */
13210ce5 1994 if (++work_done >= to_do)
1995 goto exit_loop;
cd28ab6a
SH		 1996 break;
1997
d1f13708 1998#ifdef SKY2_VLAN_TAG_USED
1999 case OP_RXVLAN:
2000 sky2->rx_tag = length;
2001 break;
2002
2003 case OP_RXCHKSVLAN:
2004 sky2->rx_tag = length;
2005 /* fall through */
2006#endif
cd28ab6a 2007 case OP_RXCHKS:
d11c13e7 2008 skb = sky2->rx_ring[sky2->rx_next].skb;
2009 skb->ip_summed = CHECKSUM_HW;
2010 skb->csum = le16_to_cpu(status);
cd28ab6a
SH		 2011 break;
2012
2013 case OP_TXINDEXLE:
13b97b74 2014 /* TX index reports status for both ports */
f55925d7
SH		 2015 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2016 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2017 if (hw->dev[1])
2018 sky2_tx_done(hw->dev[1],
2019 ((status >> 24) & 0xff)
2020 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2021 break;
2022
cd28ab6a
SH		 2023 default:
2024 if (net_ratelimit())
793b883e 2025 printk(KERN_WARNING PFX
e71ebd73
SH		 2026 "unknown status opcode 0x%x\n", le->opcode);
2027 goto exit_loop;
cd28ab6a 2028 }
13210ce5 2029 }
cd28ab6a 2030
13210ce5 2031exit_loop:
22e11703
SH		 2032 if (buf_write[0]) {
2033 sky2 = netdev_priv(hw->dev[0]);
2034 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2035 }
2036
2037 if (buf_write[1]) {
2038 sky2 = netdev_priv(hw->dev[1]);
2039 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2040 }
2041
e07b1aa8 2042 return work_done;
cd28ab6a
SH		 2043}
2044
2045static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2046{
2047 struct net_device *dev = hw->dev[port];
2048
3be92a70
SH		 2049 if (net_ratelimit())
2050 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2051 dev->name, status);
cd28ab6a
SH		 2052
2053 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2054 if (net_ratelimit())
2055 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2056 dev->name);
cd28ab6a
SH		 2057 /* Clear IRQ */
2058 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2059 }
2060
2061 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2062 if (net_ratelimit())
2063 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2064 dev->name);
cd28ab6a
SH		 2065
2066 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2067 }
2068
2069 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2070 if (net_ratelimit())
2071 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2072 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2073 }
2074
2075 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2076 if (net_ratelimit())
2077 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2078 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2079 }
2080
2081 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2082 if (net_ratelimit())
2083 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2084 dev->name);
cd28ab6a
SH		 2085 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2086 }
2087}
2088
2089static void sky2_hw_intr(struct sky2_hw *hw)
2090{
2091 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2092
793b883e 2093 if (status & Y2_IS_TIST_OV)
cd28ab6a 2094 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2095
2096 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2097 u16 pci_err;
2098
56a645cc 2099 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2100 if (net_ratelimit())
2101 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2102 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2103
2104 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2105 sky2_pci_write16(hw, PCI_STATUS,
793b883e 2106 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2107 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2108 }
2109
2110 if (status & Y2_IS_PCI_EXP) {
d571b694 2111 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2112 u32 pex_err;
2113
56a645cc 2114 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2115
3be92a70
SH		 2116 if (net_ratelimit())
2117 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2118 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2119
2120 /* clear the interrupt */
2121 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2122 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
793b883e 2123 0xffffffffUL);
cd28ab6a
SH		 2124 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2125
2126 if (pex_err & PEX_FATAL_ERRORS) {
2127 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2128 hwmsk &= ~Y2_IS_PCI_EXP;
2129 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2130 }
2131 }
2132
2133 if (status & Y2_HWE_L1_MASK)
2134 sky2_hw_error(hw, 0, status);
2135 status >>= 8;
2136 if (status & Y2_HWE_L1_MASK)
2137 sky2_hw_error(hw, 1, status);
2138}
2139
2140static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2141{
2142 struct net_device *dev = hw->dev[port];
2143 struct sky2_port *sky2 = netdev_priv(dev);
2144 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2145
2146 if (netif_msg_intr(sky2))
2147 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2148 dev->name, status);
2149
2150 if (status & GM_IS_RX_FF_OR) {
2151 ++sky2->net_stats.rx_fifo_errors;
2152 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2153 }
2154
2155 if (status & GM_IS_TX_FF_UR) {
2156 ++sky2->net_stats.tx_fifo_errors;
2157 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2158 }
cd28ab6a
SH		 2159}
2160
d257924e
SH		 2161/* This should never happen it is a fatal situation */
2162static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2163 const char *rxtx, u32 mask)
2164{
2165 struct net_device *dev = hw->dev[port];
2166 struct sky2_port *sky2 = netdev_priv(dev);
2167 u32 imask;
2168
2169 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2170 dev ? dev->name : "<not registered>", rxtx);
2171
2172 imask = sky2_read32(hw, B0_IMSK);
2173 imask &= ~mask;
2174 sky2_write32(hw, B0_IMSK, imask);
2175
2176 if (dev) {
2177 spin_lock(&sky2->phy_lock);
2178 sky2_link_down(sky2);
2179 spin_unlock(&sky2->phy_lock);
2180 }
2181}
cd28ab6a 2182
d27ed387
SH		 2183/* If idle then force a fake soft NAPI poll once a second
2184 * to work around cases where sharing an edge triggered interrupt.
2185 */
eb35cf60
SH		 2186static inline void sky2_idle_start(struct sky2_hw *hw)
2187{
2188 if (idle_timeout > 0)
2189 mod_timer(&hw->idle_timer,
2190 jiffies + msecs_to_jiffies(idle_timeout));
2191}
2192
d27ed387
SH		 2193static void sky2_idle(unsigned long arg)
2194{
01bd7564
SH		 2195 struct sky2_hw *hw = (struct sky2_hw *) arg;
2196 struct net_device *dev = hw->dev[0];
d27ed387 2197
d27ed387
SH		 2198 if (__netif_rx_schedule_prep(dev))
2199 __netif_rx_schedule(dev);
01bd7564
SH		 2200
2201 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2202}
2203
2204
e07b1aa8 2205static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2206{
e07b1aa8
SH		 2207 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2208 int work_limit = min(dev0->quota, *budget);
2209 int work_done = 0;
fb2690a9 2210 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2211
1e5f1283
SH		 2212 if (status & Y2_IS_HW_ERR)
2213 sky2_hw_intr(hw);
d257924e 2214
1e5f1283
SH		 2215 if (status & Y2_IS_IRQ_PHY1)
2216 sky2_phy_intr(hw, 0);
cd28ab6a 2217
1e5f1283
SH		 2218 if (status & Y2_IS_IRQ_PHY2)
2219 sky2_phy_intr(hw, 1);
cd28ab6a 2220
1e5f1283
SH		 2221 if (status & Y2_IS_IRQ_MAC1)
2222 sky2_mac_intr(hw, 0);
cd28ab6a 2223
1e5f1283
SH		 2224 if (status & Y2_IS_IRQ_MAC2)
2225 sky2_mac_intr(hw, 1);
cd28ab6a 2226
1e5f1283
SH		 2227 if (status & Y2_IS_CHK_RX1)
2228 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2229
1e5f1283
SH		 2230 if (status & Y2_IS_CHK_RX2)
2231 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2232
1e5f1283
SH		 2233 if (status & Y2_IS_CHK_TXA1)
2234 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2235
1e5f1283
SH		 2236 if (status & Y2_IS_CHK_TXA2)
2237 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2238
1e5f1283
SH		 2239 work_done = sky2_status_intr(hw, work_limit);
2240 *budget -= work_done;
2241 dev0->quota -= work_done;
e07b1aa8 2242
86fba634
SH		 2243 if (status & Y2_IS_STAT_BMU)
2244 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2245
2246 if (sky2_more_work(hw))
1e5f1283 2247 return 1;
caa0371e 2248
d3240312 2249 netif_rx_complete(dev0);
e07b1aa8 2250
86fba634 2251 sky2_read32(hw, B0_Y2_SP_LISR);
e07b1aa8
SH		 2252 return 0;
2253}
2254
2255static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2256{
2257 struct sky2_hw *hw = dev_id;
2258 struct net_device *dev0 = hw->dev[0];
2259 u32 status;
2260
2261 /* Reading this mask interrupts as side effect */
2262 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2263 if (status == 0 || status == ~0)
2264 return IRQ_NONE;
793b883e 2265
e07b1aa8
SH		 2266 prefetch(&hw->st_le[hw->st_idx]);
2267 if (likely(__netif_rx_schedule_prep(dev0)))
2268 __netif_rx_schedule(dev0);
793b883e 2269
cd28ab6a
SH		 2270 return IRQ_HANDLED;
2271}
2272
2273#ifdef CONFIG_NET_POLL_CONTROLLER
2274static void sky2_netpoll(struct net_device *dev)
2275{
2276 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2277 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2278
88d11360
SH		 2279 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2280 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2281}
2282#endif
2283
2284/* Chip internal frequency for clock calculations */
fb17358f 2285static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2286{
793b883e 2287 switch (hw->chip_id) {
cd28ab6a 2288 case CHIP_ID_YUKON_EC:
5a5b1ea0 2289 case CHIP_ID_YUKON_EC_U:
fb17358f 2290 return 125; /* 125 Mhz */
cd28ab6a 2291 case CHIP_ID_YUKON_FE:
fb17358f 2292 return 100; /* 100 Mhz */
793b883e 2293 default: /* YUKON_XL */
fb17358f 2294 return 156; /* 156 Mhz */
cd28ab6a
SH		 2295 }
2296}
2297
fb17358f 2298static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2299{
fb17358f 2300 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2301}
2302
fb17358f 2303static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2304{
fb17358f 2305 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2306}
2307
fb17358f 2308
59139528 2309static int sky2_reset(struct sky2_hw *hw)
cd28ab6a 2310{
cd28ab6a
SH		 2311 u16 status;
2312 u8 t8, pmd_type;
56a645cc 2313 int i;
cd28ab6a 2314
cd28ab6a 2315 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2316
cd28ab6a
SH		 2317 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2318 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2319 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2320 pci_name(hw->pdev), hw->chip_id);
2321 return -EOPNOTSUPP;
2322 }
2323
290d4de5
SH		 2324 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2325
2326 /* This rev is really old, and requires untested workarounds */
2327 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2328 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2329 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2330 hw->chip_id, hw->chip_rev);
2331 return -EOPNOTSUPP;
2332 }
2333
cd28ab6a
SH		 2334 /* disable ASF */
2335 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2336 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2337 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2338 }
2339
2340 /* do a SW reset */
2341 sky2_write8(hw, B0_CTST, CS_RST_SET);
2342 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2343
2344 /* clear PCI errors, if any */
56a645cc 2345 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2346
cd28ab6a 2347 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2348 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2349
cd28ab6a
SH		 2350
2351 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2352
2353 /* clear any PEX errors */
d89e1343 2354 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
56a645cc
SH		 2355 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2356
cd28ab6a
SH		 2357
2358 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2359 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2360
2361 hw->ports = 1;
2362 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2363 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2364 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2365 ++hw->ports;
2366 }
cd28ab6a 2367
5afa0a9c 2368 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2369
2370 for (i = 0; i < hw->ports; i++) {
2371 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2372 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2373 }
2374
2375 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2376
793b883e
SH		 2377 /* Clear I2C IRQ noise */
2378 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2379
2380 /* turn off hardware timer (unused) */
2381 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2382 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2383
cd28ab6a
SH		 2384 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2385
69634ee7
SH		 2386 /* Turn off descriptor polling */
2387 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2388
2389 /* Turn off receive timestamp */
2390 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2391 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2392
2393 /* enable the Tx Arbiters */
2394 for (i = 0; i < hw->ports; i++)
2395 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2396
2397 /* Initialize ram interface */
2398 for (i = 0; i < hw->ports; i++) {
793b883e 2399 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2400
2401 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2402 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2403 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2404 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2405 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2406 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2407 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2408 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2409 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2410 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2411 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2412 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2413 }
2414
cd28ab6a
SH		 2415 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2416
cd28ab6a
SH		 2417 for (i = 0; i < hw->ports; i++)
2418 sky2_phy_reset(hw, i);
cd28ab6a 2419
cd28ab6a
SH		 2420 memset(hw->st_le, 0, STATUS_LE_BYTES);
2421 hw->st_idx = 0;
2422
2423 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2424 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2425
2426 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2427 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2428
2429 /* Set the list last index */
793b883e 2430 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2431
290d4de5
SH		 2432 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2433 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2434
290d4de5
SH		 2435 /* set Status-FIFO ISR watermark */
2436 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2437 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2438 else
2439 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2440
290d4de5 2441 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2442 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2443 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2444
793b883e 2445 /* enable status unit */
cd28ab6a
SH		 2446 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2447
2448 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2449 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2450 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2451
2452 return 0;
2453}
2454
28bd181a 2455static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a
SH		 2456{
2457 u32 modes;
2458 if (hw->copper) {
793b883e
SH		 2459 modes = SUPPORTED_10baseT_Half
2460 | SUPPORTED_10baseT_Full
2461 | SUPPORTED_100baseT_Half
2462 | SUPPORTED_100baseT_Full
2463 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2464
2465 if (hw->chip_id != CHIP_ID_YUKON_FE)
2466 modes |= SUPPORTED_1000baseT_Half
793b883e 2467 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 2468 } else
2469 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
793b883e 2470 | SUPPORTED_Autoneg;
cd28ab6a
SH		 2471 return modes;
2472}
2473
793b883e 2474static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2475{
2476 struct sky2_port *sky2 = netdev_priv(dev);
2477 struct sky2_hw *hw = sky2->hw;
2478
2479 ecmd->transceiver = XCVR_INTERNAL;
2480 ecmd->supported = sky2_supported_modes(hw);
2481 ecmd->phy_address = PHY_ADDR_MARV;
2482 if (hw->copper) {
2483 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2484 | SUPPORTED_10baseT_Full
2485 | SUPPORTED_100baseT_Half
2486 | SUPPORTED_100baseT_Full
2487 | SUPPORTED_1000baseT_Half
2488 | SUPPORTED_1000baseT_Full
2489 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2490 ecmd->port = PORT_TP;
2491 } else
2492 ecmd->port = PORT_FIBRE;
2493
2494 ecmd->advertising = sky2->advertising;
2495 ecmd->autoneg = sky2->autoneg;
2496 ecmd->speed = sky2->speed;
2497 ecmd->duplex = sky2->duplex;
2498 return 0;
2499}
2500
2501static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2502{
2503 struct sky2_port *sky2 = netdev_priv(dev);
2504 const struct sky2_hw *hw = sky2->hw;
2505 u32 supported = sky2_supported_modes(hw);
2506
2507 if (ecmd->autoneg == AUTONEG_ENABLE) {
2508 ecmd->advertising = supported;
2509 sky2->duplex = -1;
2510 sky2->speed = -1;
2511 } else {
2512 u32 setting;
2513
793b883e 2514 switch (ecmd->speed) {
cd28ab6a
SH		 2515 case SPEED_1000:
2516 if (ecmd->duplex == DUPLEX_FULL)
2517 setting = SUPPORTED_1000baseT_Full;
2518 else if (ecmd->duplex == DUPLEX_HALF)
2519 setting = SUPPORTED_1000baseT_Half;
2520 else
2521 return -EINVAL;
2522 break;
2523 case SPEED_100:
2524 if (ecmd->duplex == DUPLEX_FULL)
2525 setting = SUPPORTED_100baseT_Full;
2526 else if (ecmd->duplex == DUPLEX_HALF)
2527 setting = SUPPORTED_100baseT_Half;
2528 else
2529 return -EINVAL;
2530 break;
2531
2532 case SPEED_10:
2533 if (ecmd->duplex == DUPLEX_FULL)
2534 setting = SUPPORTED_10baseT_Full;
2535 else if (ecmd->duplex == DUPLEX_HALF)
2536 setting = SUPPORTED_10baseT_Half;
2537 else
2538 return -EINVAL;
2539 break;
2540 default:
2541 return -EINVAL;
2542 }
2543
2544 if ((setting & supported) == 0)
2545 return -EINVAL;
2546
2547 sky2->speed = ecmd->speed;
2548 sky2->duplex = ecmd->duplex;
2549 }
2550
2551 sky2->autoneg = ecmd->autoneg;
2552 sky2->advertising = ecmd->advertising;
2553
1b537565
SH		 2554 if (netif_running(dev))
2555 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2556
2557 return 0;
2558}
2559
2560static void sky2_get_drvinfo(struct net_device *dev,
2561 struct ethtool_drvinfo *info)
2562{
2563 struct sky2_port *sky2 = netdev_priv(dev);
2564
2565 strcpy(info->driver, DRV_NAME);
2566 strcpy(info->version, DRV_VERSION);
2567 strcpy(info->fw_version, "N/A");
2568 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2569}
2570
2571static const struct sky2_stat {
793b883e
SH		 2572 char name[ETH_GSTRING_LEN];
2573 u16 offset;
cd28ab6a
SH		 2574} sky2_stats[] = {
2575 { "tx_bytes", GM_TXO_OK_HI },
2576 { "rx_bytes", GM_RXO_OK_HI },
2577 { "tx_broadcast", GM_TXF_BC_OK },
2578 { "rx_broadcast", GM_RXF_BC_OK },
2579 { "tx_multicast", GM_TXF_MC_OK },
2580 { "rx_multicast", GM_RXF_MC_OK },
2581 { "tx_unicast", GM_TXF_UC_OK },
2582 { "rx_unicast", GM_RXF_UC_OK },
2583 { "tx_mac_pause", GM_TXF_MPAUSE },
2584 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2585 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2586 { "late_collision",GM_TXF_LAT_COL },
2587 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2588 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2589 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2590
d2604540 2591 { "rx_short", GM_RXF_SHT },
cd28ab6a 2592 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2593 { "rx_64_byte_packets", GM_RXF_64B },
2594 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2595 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2596 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2597 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2598 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2599 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2600 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2601 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2602 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2603 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2604
2605 { "tx_64_byte_packets", GM_TXF_64B },
2606 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2607 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2608 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2609 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2610 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2611 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2612 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2613};
2614
cd28ab6a
SH		 2615static u32 sky2_get_rx_csum(struct net_device *dev)
2616{
2617 struct sky2_port *sky2 = netdev_priv(dev);
2618
2619 return sky2->rx_csum;
2620}
2621
2622static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2623{
2624 struct sky2_port *sky2 = netdev_priv(dev);
2625
2626 sky2->rx_csum = data;
793b883e 2627
cd28ab6a
SH		 2628 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2629 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2630
2631 return 0;
2632}
2633
2634static u32 sky2_get_msglevel(struct net_device *netdev)
2635{
2636 struct sky2_port *sky2 = netdev_priv(netdev);
2637 return sky2->msg_enable;
2638}
2639
9a7ae0a9
SH		 2640static int sky2_nway_reset(struct net_device *dev)
2641{
2642 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9
SH		 2643
2644 if (sky2->autoneg != AUTONEG_ENABLE)
2645 return -EINVAL;
2646
1b537565 2647 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2648
2649 return 0;
2650}
2651
793b883e 2652static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2653{
2654 struct sky2_hw *hw = sky2->hw;
2655 unsigned port = sky2->port;
2656 int i;
2657
2658 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2659 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2660 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2661 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2662
793b883e 2663 for (i = 2; i < count; i++)
cd28ab6a
SH		 2664 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2665}
2666
cd28ab6a
SH		 2667static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2668{
2669 struct sky2_port *sky2 = netdev_priv(netdev);
2670 sky2->msg_enable = value;
2671}
2672
2673static int sky2_get_stats_count(struct net_device *dev)
2674{
2675 return ARRAY_SIZE(sky2_stats);
2676}
2677
2678static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2679 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2680{
2681 struct sky2_port *sky2 = netdev_priv(dev);
2682
793b883e 2683 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2684}
2685
793b883e 2686static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2687{
2688 int i;
2689
2690 switch (stringset) {
2691 case ETH_SS_STATS:
2692 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2693 memcpy(data + i * ETH_GSTRING_LEN,
2694 sky2_stats[i].name, ETH_GSTRING_LEN);
2695 break;
2696 }
2697}
2698
2699/* Use hardware MIB variables for critical path statistics and
2700 * transmit feedback not reported at interrupt.
2701 * Other errors are accounted for in interrupt handler.
2702 */
2703static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2704{
2705 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2706 u64 data[13];
cd28ab6a 2707
793b883e 2708 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2709
2710 sky2->net_stats.tx_bytes = data[0];
2711 sky2->net_stats.rx_bytes = data[1];
2712 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2713 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
050ff180 2714 sky2->net_stats.multicast = data[3] + data[5];
cd28ab6a
SH		 2715 sky2->net_stats.collisions = data[10];
2716 sky2->net_stats.tx_aborted_errors = data[12];
2717
2718 return &sky2->net_stats;
2719}
2720
2721static int sky2_set_mac_address(struct net_device *dev, void *p)
2722{
2723 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2724 struct sky2_hw *hw = sky2->hw;
2725 unsigned port = sky2->port;
2726 const struct sockaddr *addr = p;
cd28ab6a
SH		 2727
2728 if (!is_valid_ether_addr(addr->sa_data))
2729 return -EADDRNOTAVAIL;
2730
cd28ab6a 2731 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2732 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2733 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2734 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2735 dev->dev_addr, ETH_ALEN);
1b537565 2736
a8ab1ec0
SH		 2737 /* virtual address for data */
2738 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2739
2740 /* physical address: used for pause frames */
2741 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2742
2743 return 0;
cd28ab6a
SH		 2744}
2745
2746static void sky2_set_multicast(struct net_device *dev)
2747{
2748 struct sky2_port *sky2 = netdev_priv(dev);
2749 struct sky2_hw *hw = sky2->hw;
2750 unsigned port = sky2->port;
2751 struct dev_mc_list *list = dev->mc_list;
2752 u16 reg;
2753 u8 filter[8];
2754
2755 memset(filter, 0, sizeof(filter));
2756
2757 reg = gma_read16(hw, port, GM_RX_CTRL);
2758 reg |= GM_RXCR_UCF_ENA;
2759
d571b694 2760 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2761 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2762 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2763 memset(filter, 0xff, sizeof(filter));
793b883e 2764 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2765 reg &= ~GM_RXCR_MCF_ENA;
2766 else {
2767 int i;
2768 reg |= GM_RXCR_MCF_ENA;
2769
2770 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2771 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2772 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2773 }
2774 }
2775
cd28ab6a 2776 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2777 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2778 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2779 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2780 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2781 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2782 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2783 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2784
2785 gma_write16(hw, port, GM_RX_CTRL, reg);
2786}
2787
2788/* Can have one global because blinking is controlled by
2789 * ethtool and that is always under RTNL mutex
2790 */
91c86df5 2791static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2792{
793b883e
SH		 2793 u16 pg;
2794
793b883e
SH		 2795 switch (hw->chip_id) {
2796 case CHIP_ID_YUKON_XL:
2797 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2798 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2799 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2800 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2801 PHY_M_LEDC_INIT_CTRL(7) |
2802 PHY_M_LEDC_STA1_CTRL(7) |
2803 PHY_M_LEDC_STA0_CTRL(7))
2804 : 0);
2805
2806 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2807 break;
2808
2809 default:
2810 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2811 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2812 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2813 PHY_M_LED_MO_10(MO_LED_ON) |
2814 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2815 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2816 PHY_M_LED_MO_RX(MO_LED_ON)
2817 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2818 PHY_M_LED_MO_10(MO_LED_OFF) |
2819 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2820 PHY_M_LED_MO_1000(MO_LED_OFF) |
2821 PHY_M_LED_MO_RX(MO_LED_OFF));
2822
793b883e 2823 }
cd28ab6a
SH		 2824}
2825
2826/* blink LED's for finding board */
2827static int sky2_phys_id(struct net_device *dev, u32 data)
2828{
2829 struct sky2_port *sky2 = netdev_priv(dev);
2830 struct sky2_hw *hw = sky2->hw;
2831 unsigned port = sky2->port;
793b883e 2832 u16 ledctrl, ledover = 0;
cd28ab6a 2833 long ms;
91c86df5 2834 int interrupted;
cd28ab6a
SH		 2835 int onoff = 1;
2836
793b883e 2837 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2838 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2839 else
2840 ms = data * 1000;
2841
2842 /* save initial values */
e07b1aa8 2843 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2844 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2845 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2846 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2847 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2848 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2849 } else {
2850 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2851 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2852 }
cd28ab6a 2853
91c86df5
SH		 2854 interrupted = 0;
2855 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2856 sky2_led(hw, port, onoff);
2857 onoff = !onoff;
2858
e07b1aa8 2859 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2860 interrupted = msleep_interruptible(250);
e07b1aa8 2861 spin_lock_bh(&sky2->phy_lock);
91c86df5 2862
cd28ab6a
SH		 2863 ms -= 250;
2864 }
2865
2866 /* resume regularly scheduled programming */
793b883e
SH		 2867 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2868 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2869 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2870 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2871 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2872 } else {
2873 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2874 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2875 }
e07b1aa8 2876 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2877
2878 return 0;
2879}
2880
2881static void sky2_get_pauseparam(struct net_device *dev,
2882 struct ethtool_pauseparam *ecmd)
2883{
2884 struct sky2_port *sky2 = netdev_priv(dev);
2885
2886 ecmd->tx_pause = sky2->tx_pause;
2887 ecmd->rx_pause = sky2->rx_pause;
2888 ecmd->autoneg = sky2->autoneg;
2889}
2890
2891static int sky2_set_pauseparam(struct net_device *dev,
2892 struct ethtool_pauseparam *ecmd)
2893{
2894 struct sky2_port *sky2 = netdev_priv(dev);
2895 int err = 0;
2896
2897 sky2->autoneg = ecmd->autoneg;
2898 sky2->tx_pause = ecmd->tx_pause != 0;
2899 sky2->rx_pause = ecmd->rx_pause != 0;
2900
1b537565 2901 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2902
2903 return err;
2904}
2905
fb17358f
SH		 2906static int sky2_get_coalesce(struct net_device *dev,
2907 struct ethtool_coalesce *ecmd)
2908{
2909 struct sky2_port *sky2 = netdev_priv(dev);
2910 struct sky2_hw *hw = sky2->hw;
2911
2912 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2913 ecmd->tx_coalesce_usecs = 0;
2914 else {
2915 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2916 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2917 }
2918 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2919
2920 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2921 ecmd->rx_coalesce_usecs = 0;
2922 else {
2923 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2924 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2925 }
2926 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2927
2928 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2929 ecmd->rx_coalesce_usecs_irq = 0;
2930 else {
2931 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2932 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2933 }
2934
2935 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2936
2937 return 0;
2938}
2939
2940/* Note: this affect both ports */
2941static int sky2_set_coalesce(struct net_device *dev,
2942 struct ethtool_coalesce *ecmd)
2943{
2944 struct sky2_port *sky2 = netdev_priv(dev);
2945 struct sky2_hw *hw = sky2->hw;
77b3d6a2 2946 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 2947
77b3d6a2
SH		 2948 if (ecmd->tx_coalesce_usecs > tmax ||
2949 ecmd->rx_coalesce_usecs > tmax ||
2950 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 2951 return -EINVAL;
2952
ff81fbbe 2953 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 2954 return -EINVAL;
ff81fbbe 2955 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 2956 return -EINVAL;
ff81fbbe 2957 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 2958 return -EINVAL;
2959
2960 if (ecmd->tx_coalesce_usecs == 0)
2961 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2962 else {
2963 sky2_write32(hw, STAT_TX_TIMER_INI,
2964 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2965 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2966 }
2967 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2968
2969 if (ecmd->rx_coalesce_usecs == 0)
2970 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2971 else {
2972 sky2_write32(hw, STAT_LEV_TIMER_INI,
2973 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2974 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2975 }
2976 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2977
2978 if (ecmd->rx_coalesce_usecs_irq == 0)
2979 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2980 else {
d28d4870 2981 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 2982 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2983 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2984 }
2985 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2986 return 0;
2987}
2988
793b883e
SH		 2989static void sky2_get_ringparam(struct net_device *dev,
2990 struct ethtool_ringparam *ering)
2991{
2992 struct sky2_port *sky2 = netdev_priv(dev);
2993
2994 ering->rx_max_pending = RX_MAX_PENDING;
2995 ering->rx_mini_max_pending = 0;
2996 ering->rx_jumbo_max_pending = 0;
2997 ering->tx_max_pending = TX_RING_SIZE - 1;
2998
2999 ering->rx_pending = sky2->rx_pending;
3000 ering->rx_mini_pending = 0;
3001 ering->rx_jumbo_pending = 0;
3002 ering->tx_pending = sky2->tx_pending;
3003}
3004
3005static int sky2_set_ringparam(struct net_device *dev,
3006 struct ethtool_ringparam *ering)
3007{
3008 struct sky2_port *sky2 = netdev_priv(dev);
3009 int err = 0;
3010
3011 if (ering->rx_pending > RX_MAX_PENDING ||
3012 ering->rx_pending < 8 ||
3013 ering->tx_pending < MAX_SKB_TX_LE ||
3014 ering->tx_pending > TX_RING_SIZE - 1)
3015 return -EINVAL;
3016
3017 if (netif_running(dev))
3018 sky2_down(dev);
3019
3020 sky2->rx_pending = ering->rx_pending;
3021 sky2->tx_pending = ering->tx_pending;
3022
1b537565 3023 if (netif_running(dev)) {
793b883e 3024 err = sky2_up(dev);
1b537565
SH		 3025 if (err)
3026 dev_close(dev);
6ed995bb
SH		 3027 else
3028 sky2_set_multicast(dev);
1b537565 3029 }
793b883e
SH		 3030
3031 return err;
3032}
3033
793b883e
SH		 3034static int sky2_get_regs_len(struct net_device *dev)
3035{
6e4cbb34 3036 return 0x4000;
793b883e
SH		 3037}
3038
3039/*
3040 * Returns copy of control register region
6e4cbb34 3041 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3042 */
3043static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3044 void *p)
3045{
3046 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3047 const void __iomem *io = sky2->hw->regs;
793b883e 3048
6e4cbb34 3049 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3050 regs->version = 1;
6e4cbb34 3051 memset(p, 0, regs->len);
793b883e 3052
6e4cbb34
SH		 3053 memcpy_fromio(p, io, B3_RAM_ADDR);
3054
3055 memcpy_fromio(p + B3_RI_WTO_R1,
3056 io + B3_RI_WTO_R1,
3057 regs->len - B3_RI_WTO_R1);
793b883e 3058}
cd28ab6a
SH		 3059
3060static struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3061 .get_settings = sky2_get_settings,
3062 .set_settings = sky2_set_settings,
3063 .get_drvinfo = sky2_get_drvinfo,
3064 .get_msglevel = sky2_get_msglevel,
3065 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3066 .nway_reset = sky2_nway_reset,
793b883e
SH		 3067 .get_regs_len = sky2_get_regs_len,
3068 .get_regs = sky2_get_regs,
3069 .get_link = ethtool_op_get_link,
3070 .get_sg = ethtool_op_get_sg,
3071 .set_sg = ethtool_op_set_sg,
3072 .get_tx_csum = ethtool_op_get_tx_csum,
3073 .set_tx_csum = ethtool_op_set_tx_csum,
3074 .get_tso = ethtool_op_get_tso,
3075 .set_tso = ethtool_op_set_tso,
3076 .get_rx_csum = sky2_get_rx_csum,
3077 .set_rx_csum = sky2_set_rx_csum,
3078 .get_strings = sky2_get_strings,
fb17358f
SH		 3079 .get_coalesce = sky2_get_coalesce,
3080 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3081 .get_ringparam = sky2_get_ringparam,
3082 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3083 .get_pauseparam = sky2_get_pauseparam,
3084 .set_pauseparam = sky2_set_pauseparam,
793b883e 3085 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3086 .get_stats_count = sky2_get_stats_count,
3087 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3088 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3089};
3090
3091/* Initialize network device */
3092static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3093 unsigned port, int highmem)
3094{
3095 struct sky2_port *sky2;
3096 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3097
3098 if (!dev) {
3099 printk(KERN_ERR "sky2 etherdev alloc failed");
3100 return NULL;
3101 }
3102
3103 SET_MODULE_OWNER(dev);
3104 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3105 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3106 dev->open = sky2_up;
3107 dev->stop = sky2_down;
ef743d33 3108 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3109 dev->hard_start_xmit = sky2_xmit_frame;
3110 dev->get_stats = sky2_get_stats;
3111 dev->set_multicast_list = sky2_set_multicast;
3112 dev->set_mac_address = sky2_set_mac_address;
3113 dev->change_mtu = sky2_change_mtu;
3114 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3115 dev->tx_timeout = sky2_tx_timeout;
3116 dev->watchdog_timeo = TX_WATCHDOG;
3117 if (port == 0)
3118 dev->poll = sky2_poll;
3119 dev->weight = NAPI_WEIGHT;
3120#ifdef CONFIG_NET_POLL_CONTROLLER
3121 dev->poll_controller = sky2_netpoll;
3122#endif
cd28ab6a
SH		 3123
3124 sky2 = netdev_priv(dev);
3125 sky2->netdev = dev;
3126 sky2->hw = hw;
3127 sky2->msg_enable = netif_msg_init(debug, default_msg);
3128
3129 spin_lock_init(&sky2->tx_lock);
3130 /* Auto speed and flow control */
3131 sky2->autoneg = AUTONEG_ENABLE;
585b5601 3132 sky2->tx_pause = 1;
cd28ab6a
SH		 3133 sky2->rx_pause = 1;
3134 sky2->duplex = -1;
3135 sky2->speed = -1;
3136 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3137 sky2->rx_csum = 1;
75d070c5 3138
e07b1aa8 3139 spin_lock_init(&sky2->phy_lock);
793b883e 3140 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3141 sky2->rx_pending = RX_DEF_PENDING;
734d1868 3142 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
cd28ab6a
SH		 3143
3144 hw->dev[port] = dev;
3145
3146 sky2->port = port;
3147
5a5b1ea0 3148 dev->features |= NETIF_F_LLTX;
3149 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3150 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3151 if (highmem)
3152 dev->features |= NETIF_F_HIGHDMA;
793b883e 3153 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3154
d1f13708 3155#ifdef SKY2_VLAN_TAG_USED
3156 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3157 dev->vlan_rx_register = sky2_vlan_rx_register;
3158 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3159#endif
3160
cd28ab6a 3161 /* read the mac address */
793b883e 3162 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3163 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3164
3165 /* device is off until link detection */
3166 netif_carrier_off(dev);
3167 netif_stop_queue(dev);
3168
3169 return dev;
3170}
3171
28bd181a 3172static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3173{
3174 const struct sky2_port *sky2 = netdev_priv(dev);
3175
3176 if (netif_msg_probe(sky2))
3177 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3178 dev->name,
3179 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3180 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3181}
3182
fb2690a9
SH		 3183/* Handle software interrupt used during MSI test */
3184static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3185 struct pt_regs *regs)
3186{
3187 struct sky2_hw *hw = dev_id;
3188 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3189
3190 if (status == 0)
3191 return IRQ_NONE;
3192
3193 if (status & Y2_IS_IRQ_SW) {
3194 hw->msi_detected = 1;
3195 wake_up(&hw->msi_wait);
3196 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3197 }
3198 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3199
3200 return IRQ_HANDLED;
3201}
3202
3203/* Test interrupt path by forcing a a software IRQ */
3204static int __devinit sky2_test_msi(struct sky2_hw *hw)
3205{
3206 struct pci_dev *pdev = hw->pdev;
3207 int err;
3208
3209 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3210
1fb9df5d 3211 err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw);
fb2690a9
SH		 3212 if (err) {
3213 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3214 pci_name(pdev), pdev->irq);
3215 return err;
3216 }
3217
3218 init_waitqueue_head (&hw->msi_wait);
3219
3220 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3221 wmb();
3222
3223 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3224
3225 if (!hw->msi_detected) {
3226 /* MSI test failed, go back to INTx mode */
3227 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3228 "switching to INTx mode. Please report this failure to "
3229 "the PCI maintainer and include system chipset information.\n",
3230 pci_name(pdev));
3231
3232 err = -EOPNOTSUPP;
3233 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3234 }
3235
3236 sky2_write32(hw, B0_IMSK, 0);
3237
3238 free_irq(pdev->irq, hw);
3239
3240 return err;
3241}
3242
cd28ab6a
SH		 3243static int __devinit sky2_probe(struct pci_dev *pdev,
3244 const struct pci_device_id *ent)
3245{
793b883e 3246 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3247 struct sky2_hw *hw;
5afa0a9c 3248 int err, pm_cap, using_dac = 0;
cd28ab6a 3249
793b883e
SH		 3250 err = pci_enable_device(pdev);
3251 if (err) {
cd28ab6a
SH		 3252 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3253 pci_name(pdev));
3254 goto err_out;
3255 }
3256
793b883e
SH		 3257 err = pci_request_regions(pdev, DRV_NAME);
3258 if (err) {
cd28ab6a
SH		 3259 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3260 pci_name(pdev));
793b883e 3261 goto err_out;
cd28ab6a
SH		 3262 }
3263
3264 pci_set_master(pdev);
3265
5afa0a9c 3266 /* Find power-management capability. */
3267 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3268 if (pm_cap == 0) {
3269 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3270 "aborting.\n");
3271 err = -EIO;
3272 goto err_out_free_regions;
3273 }
3274
d1f3d4dd
SH		 3275 if (sizeof(dma_addr_t) > sizeof(u32) &&
3276 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3277 using_dac = 1;
3278 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3279 if (err < 0) {
3280 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3281 "for consistent allocations\n", pci_name(pdev));
3282 goto err_out_free_regions;
3283 }
cd28ab6a 3284
d1f3d4dd 3285 } else {
cd28ab6a
SH		 3286 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3287 if (err) {
3288 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3289 pci_name(pdev));
3290 goto err_out_free_regions;
3291 }
3292 }
d1f3d4dd 3293
cd28ab6a 3294 err = -ENOMEM;
6aad85d6 3295 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3296 if (!hw) {
3297 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3298 pci_name(pdev));
3299 goto err_out_free_regions;
3300 }
3301
cd28ab6a 3302 hw->pdev = pdev;
cd28ab6a
SH		 3303
3304 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3305 if (!hw->regs) {
3306 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3307 pci_name(pdev));
3308 goto err_out_free_hw;
3309 }
5afa0a9c 3310 hw->pm_cap = pm_cap;
cd28ab6a 3311
56a645cc
SH		 3312#ifdef __BIG_ENDIAN
3313 /* byte swap descriptors in hardware */
3314 {
3315 u32 reg;
3316
3317 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3318 reg |= PCI_REV_DESC;
3319 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3320 }
3321#endif
3322
08c06d8a
SH		 3323 /* ring for status responses */
3324 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3325 &hw->st_dma);
3326 if (!hw->st_le)
3327 goto err_out_iounmap;
3328
cd28ab6a
SH		 3329 err = sky2_reset(hw);
3330 if (err)
793b883e 3331 goto err_out_iounmap;
cd28ab6a 3332
7c7459d1
GKH		 3333 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3334 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3335 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3336 hw->chip_id, hw->chip_rev);
cd28ab6a 3337
793b883e
SH		 3338 dev = sky2_init_netdev(hw, 0, using_dac);
3339 if (!dev)
cd28ab6a
SH		 3340 goto err_out_free_pci;
3341
793b883e
SH		 3342 err = register_netdev(dev);
3343 if (err) {
cd28ab6a
SH		 3344 printk(KERN_ERR PFX "%s: cannot register net device\n",
3345 pci_name(pdev));
3346 goto err_out_free_netdev;
3347 }
3348
3349 sky2_show_addr(dev);
3350
3351 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3352 if (register_netdev(dev1) == 0)
3353 sky2_show_addr(dev1);
3354 else {
3355 /* Failure to register second port need not be fatal */
793b883e
SH		 3356 printk(KERN_WARNING PFX
3357 "register of second port failed\n");
cd28ab6a
SH		 3358 hw->dev[1] = NULL;
3359 free_netdev(dev1);
3360 }
3361 }
3362
fb2690a9
SH		 3363 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3364 err = sky2_test_msi(hw);
3365 if (err == -EOPNOTSUPP)
3366 pci_disable_msi(pdev);
3367 else if (err)
3368 goto err_out_unregister;
3369 }
3370
1fb9df5d 3371 err = request_irq(pdev->irq, sky2_intr, IRQF_SHARED, DRV_NAME, hw);
793b883e
SH		 3372 if (err) {
3373 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3374 pci_name(pdev), pdev->irq);
3375 goto err_out_unregister;
3376 }
3377
e07b1aa8 3378 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
793b883e 3379
01bd7564 3380 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
eb35cf60 3381 sky2_idle_start(hw);
d27ed387 3382
793b883e
SH		 3383 pci_set_drvdata(pdev, hw);
3384
cd28ab6a
SH		 3385 return 0;
3386
793b883e 3387err_out_unregister:
fb2690a9 3388 pci_disable_msi(pdev);
793b883e
SH		 3389 if (dev1) {
3390 unregister_netdev(dev1);
3391 free_netdev(dev1);
3392 }
3393 unregister_netdev(dev);
cd28ab6a
SH		 3394err_out_free_netdev:
3395 free_netdev(dev);
cd28ab6a 3396err_out_free_pci:
793b883e 3397 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3398 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3399err_out_iounmap:
3400 iounmap(hw->regs);
3401err_out_free_hw:
3402 kfree(hw);
3403err_out_free_regions:
3404 pci_release_regions(pdev);
cd28ab6a 3405 pci_disable_device(pdev);
cd28ab6a
SH		 3406err_out:
3407 return err;
3408}
3409
3410static void __devexit sky2_remove(struct pci_dev *pdev)
3411{
793b883e 3412 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3413 struct net_device *dev0, *dev1;
3414
793b883e 3415 if (!hw)
cd28ab6a
SH		 3416 return;
3417
d27ed387
SH		 3418 del_timer_sync(&hw->idle_timer);
3419
3420 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3421 synchronize_irq(hw->pdev->irq);
3422
cd28ab6a 3423 dev0 = hw->dev[0];
793b883e
SH		 3424 dev1 = hw->dev[1];
3425 if (dev1)
3426 unregister_netdev(dev1);
cd28ab6a
SH		 3427 unregister_netdev(dev0);
3428
5afa0a9c 3429 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3430 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3431 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3432 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3433
3434 free_irq(pdev->irq, hw);
fb2690a9 3435 pci_disable_msi(pdev);
793b883e 3436 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3437 pci_release_regions(pdev);
3438 pci_disable_device(pdev);
793b883e 3439
cd28ab6a
SH		 3440 if (dev1)
3441 free_netdev(dev1);
3442 free_netdev(dev0);
3443 iounmap(hw->regs);
3444 kfree(hw);
5afa0a9c 3445
cd28ab6a
SH		 3446 pci_set_drvdata(pdev, NULL);
3447}
3448
3449#ifdef CONFIG_PM
3450static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3451{
793b883e 3452 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3453 int i;
2ccc99b7
SH		 3454 pci_power_t pstate = pci_choose_state(pdev, state);
3455
3456 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3457 return -EINVAL;
cd28ab6a 3458
eb35cf60 3459 del_timer_sync(&hw->idle_timer);
6a5706b9 3460 netif_poll_disable(hw->dev[0]);
eb35cf60 3461
f05267e7 3462 for (i = 0; i < hw->ports; i++) {
cd28ab6a
SH		 3463 struct net_device *dev = hw->dev[i];
3464
6a5706b9 3465 if (netif_running(dev)) {
5afa0a9c 3466 sky2_down(dev);
cd28ab6a 3467 netif_device_detach(dev);
cd28ab6a
SH		 3468 }
3469 }
3470
8ab8fca2 3471 sky2_write32(hw, B0_IMSK, 0);
d374c1c1 3472 pci_save_state(pdev);
2ccc99b7
SH		 3473 sky2_set_power_state(hw, pstate);
3474 return 0;
cd28ab6a
SH		 3475}
3476
3477static int sky2_resume(struct pci_dev *pdev)
3478{
793b883e 3479 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3480 int i, err;
cd28ab6a 3481
cd28ab6a
SH		 3482 pci_restore_state(pdev);
3483 pci_enable_wake(pdev, PCI_D0, 0);
2ccc99b7 3484 sky2_set_power_state(hw, PCI_D0);
cd28ab6a 3485
08c06d8a
SH		 3486 err = sky2_reset(hw);
3487 if (err)
3488 goto out;
cd28ab6a 3489
8ab8fca2
SH		 3490 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3491
f05267e7 3492 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3493 struct net_device *dev = hw->dev[i];
6a5706b9 3494 if (netif_running(dev)) {
08c06d8a 3495 netif_device_attach(dev);
88d11360 3496
08c06d8a
SH		 3497 err = sky2_up(dev);
3498 if (err) {
3499 printk(KERN_ERR PFX "%s: could not up: %d\n",
3500 dev->name, err);
3501 dev_close(dev);
eb35cf60 3502 goto out;
5afa0a9c 3503 }
cd28ab6a
SH		 3504 }
3505 }
eb35cf60 3506
6a5706b9 3507 netif_poll_enable(hw->dev[0]);
eb35cf60 3508 sky2_idle_start(hw);
08c06d8a
SH		 3509out:
3510 return err;
cd28ab6a
SH		 3511}
3512#endif
3513
3514static struct pci_driver sky2_driver = {
793b883e
SH		 3515 .name = DRV_NAME,
3516 .id_table = sky2_id_table,
3517 .probe = sky2_probe,
3518 .remove = __devexit_p(sky2_remove),
cd28ab6a 3519#ifdef CONFIG_PM
793b883e
SH		 3520 .suspend = sky2_suspend,
3521 .resume = sky2_resume,
cd28ab6a
SH		 3522#endif
3523};
3524
3525static int __init sky2_init_module(void)
3526{
50241c4c 3527 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3528}
3529
3530static void __exit sky2_cleanup_module(void)
3531{
3532 pci_unregister_driver(&sky2_driver);
3533}
3534
3535module_init(sky2_init_module);
3536module_exit(sky2_cleanup_module);
3537
3538MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3539MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3540MODULE_LICENSE("GPL");
5f4f9dc1 3541MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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