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sky2: GPIO register
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
93cd791e 53#define DRV_VERSION "1.14"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 66#define RX_SKB_ALIGN 8
22e11703 67#define RX_BUF_WRITE 16
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
cb5d9547
SH		 80#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
81
cd28ab6a 82static const u32 default_msg =
793b883e
SH		 83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 86
793b883e 87static int debug = -1; /* defaults above */
cd28ab6a
SH		 88module_param(debug, int, 0);
89MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90
14d0263f 91static int copybreak __read_mostly = 128;
bdb5c58e
SH		 92module_param(copybreak, int, 0);
93MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94
fb2690a9
SH		 95static int disable_msi = 0;
96module_param(disable_msi, int, 0);
97MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98
e561a83b 99static int idle_timeout = 0;
01bd7564 100module_param(idle_timeout, int, 0);
e561a83b 101MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 102
cd28ab6a 103static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
78f0b62d 133// { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
cd28ab6a
SH		 134 { 0 }
135};
793b883e 136
cd28ab6a
SH		 137MODULE_DEVICE_TABLE(pci, sky2_id_table);
138
139/* Avoid conditionals by using array */
140static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
141static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 142static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 143
92f965e8
SH		 144/* This driver supports yukon2 chipset only */
145static const char *yukon2_name[] = {
146 "XL", /* 0xb3 */
147 "EC Ultra", /* 0xb4 */
93745494 148 "Extreme", /* 0xb5 */
92f965e8
SH		 149 "EC", /* 0xb6 */
150 "FE", /* 0xb7 */
793b883e
SH		 151};
152
793b883e 153/* Access to external PHY */
ef743d33 154static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 155{
156 int i;
157
158 gma_write16(hw, port, GM_SMI_DATA, val);
159 gma_write16(hw, port, GM_SMI_CTRL,
160 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
161
162 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 163 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 164 return 0;
793b883e 165 udelay(1);
cd28ab6a 166 }
ef743d33 167
793b883e 168 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 169 return -ETIMEDOUT;
cd28ab6a
SH		 170}
171
ef743d33 172static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 173{
174 int i;
175
793b883e 176 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 177 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
178
179 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33 180 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
181 *val = gma_read16(hw, port, GM_SMI_DATA);
182 return 0;
183 }
184
793b883e 185 udelay(1);
cd28ab6a
SH		 186 }
187
ef743d33 188 return -ETIMEDOUT;
189}
190
191static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
192{
193 u16 v;
194
195 if (__gm_phy_read(hw, port, reg, &v) != 0)
196 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
197 return v;
cd28ab6a
SH		 198}
199
5afa0a9c 200
ae306cca
SH		 201static void sky2_power_on(struct sky2_hw *hw)
202{
203 /* switch power to VCC (WA for VAUX problem) */
204 sky2_write8(hw, B0_POWER_CTRL,
205 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 206
ae306cca
SH		 207 /* disable Core Clock Division, */
208 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 209
ae306cca
SH		 210 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
211 /* enable bits are inverted */
212 sky2_write8(hw, B2_Y2_CLK_GATE,
213 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
214 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
215 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
216 else
217 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 218
93745494 219 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
fc99fe06 220 u32 reg;
5afa0a9c 221
fc99fe06
SH		 222 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
223 /* set all bits to 0 except bits 15..12 and 8 */
224 reg &= P_ASPM_CONTROL_MSK;
225 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
226
227 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
228 /* set all bits to 0 except bits 28 & 27 */
229 reg &= P_CTL_TIM_VMAIN_AV_MSK;
230 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
231
232 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 233
234 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
235 reg = sky2_read32(hw, B2_GP_IO);
236 reg |= GLB_GPIO_STAT_RACE_DIS;
237 sky2_write32(hw, B2_GP_IO, reg);
5afa0a9c 238 }
ae306cca 239}
5afa0a9c 240
ae306cca
SH		 241static void sky2_power_aux(struct sky2_hw *hw)
242{
243 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
244 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
245 else
246 /* enable bits are inverted */
247 sky2_write8(hw, B2_Y2_CLK_GATE,
248 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
249 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
250 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
251
252 /* switch power to VAUX */
253 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
254 sky2_write8(hw, B0_POWER_CTRL,
255 (PC_VAUX_ENA | PC_VCC_ENA |
256 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c 257}
258
d3bcfbeb 259static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 260{
261 u16 reg;
262
263 /* disable all GMAC IRQ's */
264 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
265 /* disable PHY IRQs */
266 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 267
cd28ab6a
SH		 268 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
269 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
270 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
271 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
272
273 reg = gma_read16(hw, port, GM_RX_CTRL);
274 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
275 gma_write16(hw, port, GM_RX_CTRL, reg);
276}
277
16ad91e1
SH		 278/* flow control to advertise bits */
279static const u16 copper_fc_adv[] = {
280 [FC_NONE] = 0,
281 [FC_TX] = PHY_M_AN_ASP,
282 [FC_RX] = PHY_M_AN_PC,
283 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
284};
285
286/* flow control to advertise bits when using 1000BaseX */
287static const u16 fiber_fc_adv[] = {
288 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
289 [FC_TX] = PHY_M_P_ASYM_MD_X,
290 [FC_RX] = PHY_M_P_SYM_MD_X,
291 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
292};
293
294/* flow control to GMA disable bits */
295static const u16 gm_fc_disable[] = {
296 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
297 [FC_TX] = GM_GPCR_FC_RX_DIS,
298 [FC_RX] = GM_GPCR_FC_TX_DIS,
299 [FC_BOTH] = 0,
300};
301
302
cd28ab6a
SH		 303static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
304{
305 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 306 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 307
93745494
SH		 308 if (sky2->autoneg == AUTONEG_ENABLE
309 && !(hw->chip_id == CHIP_ID_YUKON_XL
310 || hw->chip_id == CHIP_ID_YUKON_EC_U
311 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 312 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
313
314 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 315 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 316 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
317
53419c68 318 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 319 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 320 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 321 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
322 else
53419c68
SH		 323 /* set master & slave downshift counter to 1x */
324 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 325
326 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
327 }
328
329 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 330 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 331 if (hw->chip_id == CHIP_ID_YUKON_FE) {
332 /* enable automatic crossover */
333 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
334 } else {
335 /* disable energy detect */
336 ctrl &= ~PHY_M_PC_EN_DET_MSK;
337
338 /* enable automatic crossover */
339 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
340
53419c68 341 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494
SH		 342 if (sky2->autoneg == AUTONEG_ENABLE
343 && (hw->chip_id == CHIP_ID_YUKON_XL
344 || hw->chip_id == CHIP_ID_YUKON_EC_U
345 || hw->chip_id == CHIP_ID_YUKON_EX)) {
53419c68 346 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 347 ctrl &= ~PHY_M_PC_DSC_MSK;
348 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
349 }
350 }
cd28ab6a
SH		 351 } else {
352 /* workaround for deviation #4.88 (CRC errors) */
353 /* disable Automatic Crossover */
354
355 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 356 }
cd28ab6a 357
b89165f2
SH		 358 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
359
360 /* special setup for PHY 88E1112 Fiber */
361 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
362 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 363
b89165f2
SH		 364 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
365 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
366 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
367 ctrl &= ~PHY_M_MAC_MD_MSK;
368 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
369 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
370
371 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 372 /* select page 1 to access Fiber registers */
373 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 374
375 /* for SFP-module set SIGDET polarity to low */
376 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
377 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 378 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 379 }
b89165f2
SH		 380
381 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 382 }
383
7800fddc 384 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 385 ct1000 = 0;
386 adv = PHY_AN_CSMA;
2eaba1a2 387 reg = 0;
cd28ab6a
SH		 388
389 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 390 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 391 if (sky2->advertising & ADVERTISED_1000baseT_Full)
392 ct1000 |= PHY_M_1000C_AFD;
393 if (sky2->advertising & ADVERTISED_1000baseT_Half)
394 ct1000 |= PHY_M_1000C_AHD;
395 if (sky2->advertising & ADVERTISED_100baseT_Full)
396 adv |= PHY_M_AN_100_FD;
397 if (sky2->advertising & ADVERTISED_100baseT_Half)
398 adv |= PHY_M_AN_100_HD;
399 if (sky2->advertising & ADVERTISED_10baseT_Full)
400 adv |= PHY_M_AN_10_FD;
401 if (sky2->advertising & ADVERTISED_10baseT_Half)
402 adv |= PHY_M_AN_10_HD;
709c6e7b 403
16ad91e1 404 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 405 } else { /* special defines for FIBER (88E1040S only) */
406 if (sky2->advertising & ADVERTISED_1000baseT_Full)
407 adv |= PHY_M_AN_1000X_AFD;
408 if (sky2->advertising & ADVERTISED_1000baseT_Half)
409 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 410
16ad91e1 411 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 412 }
cd28ab6a
SH		 413
414 /* Restart Auto-negotiation */
415 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
416 } else {
417 /* forced speed/duplex settings */
418 ct1000 = PHY_M_1000C_MSE;
419
2eaba1a2
SH		 420 /* Disable auto update for duplex flow control and speed */
421 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 422
423 switch (sky2->speed) {
424 case SPEED_1000:
425 ctrl |= PHY_CT_SP1000;
2eaba1a2 426 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 427 break;
428 case SPEED_100:
429 ctrl |= PHY_CT_SP100;
2eaba1a2 430 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 431 break;
432 }
433
2eaba1a2
SH		 434 if (sky2->duplex == DUPLEX_FULL) {
435 reg |= GM_GPCR_DUP_FULL;
436 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 437 } else if (sky2->speed < SPEED_1000)
438 sky2->flow_mode = FC_NONE;
2eaba1a2 439
2eaba1a2 440
16ad91e1 441 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 442
443 /* Forward pause packets to GMAC? */
16ad91e1 444 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 445 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
446 else
447 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 448 }
449
2eaba1a2
SH		 450 gma_write16(hw, port, GM_GP_CTRL, reg);
451
cd28ab6a
SH		 452 if (hw->chip_id != CHIP_ID_YUKON_FE)
453 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
454
455 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
456 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
457
458 /* Setup Phy LED's */
459 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
460 ledover = 0;
461
462 switch (hw->chip_id) {
463 case CHIP_ID_YUKON_FE:
464 /* on 88E3082 these bits are at 11..9 (shifted left) */
465 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
466
467 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
468
469 /* delete ACT LED control bits */
470 ctrl &= ~PHY_M_FELP_LED1_MSK;
471 /* change ACT LED control to blink mode */
472 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
473 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
474 break;
475
476 case CHIP_ID_YUKON_XL:
793b883e 477 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 478
479 /* select page 3 to access LED control register */
480 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
481
482 /* set LED Function Control register */
ed6d32c7
SH		 483 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
484 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
485 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
486 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
487 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 488
489 /* set Polarity Control register */
490 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 491 (PHY_M_POLC_LS1_P_MIX(4) |
492 PHY_M_POLC_IS0_P_MIX(4) |
493 PHY_M_POLC_LOS_CTRL(2) |
494 PHY_M_POLC_INIT_CTRL(2) |
495 PHY_M_POLC_STA1_CTRL(2) |
496 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 497
498 /* restore page register */
793b883e 499 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 500 break;
93745494 501
ed6d32c7 502 case CHIP_ID_YUKON_EC_U:
93745494 503 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 504 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
505
506 /* select page 3 to access LED control register */
507 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
508
509 /* set LED Function Control register */
510 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
511 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
512 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
513 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
514 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
515
516 /* set Blink Rate in LED Timer Control Register */
517 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
518 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
519 /* restore page register */
520 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
521 break;
cd28ab6a
SH		 522
523 default:
524 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
525 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
526 /* turn off the Rx LED (LED_RX) */
0efdf262 527 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 528 }
529
9467a8fc
SH		 530 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
531 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 532 /* apply fixes in PHY AFE */
ed6d32c7
SH		 533 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
534
977bdf06 535 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 536 gm_phy_write(hw, port, 0x18, 0xaa99);
537 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 538
977bdf06 539 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 540 gm_phy_write(hw, port, 0x18, 0xa204);
541 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 542
543 /* set page register to 0 */
9467a8fc 544 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
93745494 545 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
977bdf06 546 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 547
977bdf06
SH		 548 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
549 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 550 ledover |= PHY_M_LED_MO_100;
977bdf06 551 }
cd28ab6a 552
977bdf06
SH		 553 if (ledover)
554 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
555
556 }
2eaba1a2 557
d571b694 558 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 559 if (sky2->autoneg == AUTONEG_ENABLE)
560 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
561 else
562 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
563}
564
d3bcfbeb 565static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
566{
567 u32 reg1;
568 static const u32 phy_power[]
569 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
570
571 /* looks like this XL is back asswards .. */
572 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
573 onoff = !onoff;
574
aed2cec4 575 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 576 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb 577 if (onoff)
578 /* Turn off phy power saving */
579 reg1 &= ~phy_power[port];
580 else
581 reg1 |= phy_power[port];
582
583 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 584 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 585 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb 586 udelay(100);
587}
588
1b537565
SH		 589/* Force a renegotiation */
590static void sky2_phy_reinit(struct sky2_port *sky2)
591{
e07b1aa8 592 spin_lock_bh(&sky2->phy_lock);
1b537565 593 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 594 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 595}
596
e3173832
SH		 597/* Put device in state to listen for Wake On Lan */
598static void sky2_wol_init(struct sky2_port *sky2)
599{
600 struct sky2_hw *hw = sky2->hw;
601 unsigned port = sky2->port;
602 enum flow_control save_mode;
603 u16 ctrl;
604 u32 reg1;
605
606 /* Bring hardware out of reset */
607 sky2_write16(hw, B0_CTST, CS_RST_CLR);
608 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
609
610 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
611 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
612
613 /* Force to 10/100
614 * sky2_reset will re-enable on resume
615 */
616 save_mode = sky2->flow_mode;
617 ctrl = sky2->advertising;
618
619 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
620 sky2->flow_mode = FC_NONE;
621 sky2_phy_power(hw, port, 1);
622 sky2_phy_reinit(sky2);
623
624 sky2->flow_mode = save_mode;
625 sky2->advertising = ctrl;
626
627 /* Set GMAC to no flow control and auto update for speed/duplex */
628 gma_write16(hw, port, GM_GP_CTRL,
629 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
630 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
631
632 /* Set WOL address */
633 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
634 sky2->netdev->dev_addr, ETH_ALEN);
635
636 /* Turn on appropriate WOL control bits */
637 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
638 ctrl = 0;
639 if (sky2->wol & WAKE_PHY)
640 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
641 else
642 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
643
644 if (sky2->wol & WAKE_MAGIC)
645 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
646 else
647 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
648
649 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
650 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
651
652 /* Turn on legacy PCI-Express PME mode */
653 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
654 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
655 reg1 |= PCI_Y2_PME_LEGACY;
656 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
657 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
658
659 /* block receiver */
660 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
661
662}
663
cd28ab6a
SH		 664static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
665{
666 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
667 u16 reg;
668 int i;
669 const u8 *addr = hw->dev[port]->dev_addr;
670
42eeea01 671 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
b4ed372b 672 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 673
674 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
675
793b883e 676 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 677 /* WA DEV_472 -- looks like crossed wires on port 2 */
678 /* clear GMAC 1 Control reset */
679 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
680 do {
681 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
682 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
683 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
684 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
685 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
686 }
687
793b883e 688 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 689
2eaba1a2
SH		 690 /* Enable Transmit FIFO Underrun */
691 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
692
e07b1aa8 693 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 694 sky2_phy_init(hw, port);
e07b1aa8 695 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 696
697 /* MIB clear */
698 reg = gma_read16(hw, port, GM_PHY_ADDR);
699 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
700
43f2f104
SH		 701 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
702 gma_read16(hw, port, i);
cd28ab6a
SH		 703 gma_write16(hw, port, GM_PHY_ADDR, reg);
704
705 /* transmit control */
706 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
707
708 /* receive control reg: unicast + multicast + no FCS */
709 gma_write16(hw, port, GM_RX_CTRL,
793b883e 710 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 711
712 /* transmit flow control */
713 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
714
715 /* transmit parameter */
716 gma_write16(hw, port, GM_TX_PARAM,
717 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
718 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
719 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
720 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
721
722 /* serial mode register */
723 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 724 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 725
6b1a3aef 726 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 727 reg |= GM_SMOD_JUMBO_ENA;
728
729 gma_write16(hw, port, GM_SERIAL_MODE, reg);
730
cd28ab6a
SH		 731 /* virtual address for data */
732 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
733
793b883e
SH		 734 /* physical address: used for pause frames */
735 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
736
737 /* ignore counter overflows */
cd28ab6a
SH		 738 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
739 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
740 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
741
742 /* Configure Rx MAC FIFO */
743 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 744 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
745 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 746
d571b694 747 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 748 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 749
8df9a876
SH		 750 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
751 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 752
753 /* Configure Tx MAC FIFO */
754 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
755 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 756
93745494 757 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
8df9a876 758 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 759 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98
SH		 760
761 /* set Tx GMAC FIFO Almost Empty Threshold */
762 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
763 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
764
765 if (hw->dev[port]->mtu > ETH_DATA_LEN)
766 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
767 TX_JUMBO_ENA | TX_STFW_DIS);
768 else
769 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
770 TX_JUMBO_DIS | TX_STFW_ENA);
5a5b1ea0 771 }
772
cd28ab6a
SH		 773}
774
67712901
SH		 775/* Assign Ram Buffer allocation to queue */
776static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 777{
67712901
SH		 778 u32 end;
779
780 /* convert from K bytes to qwords used for hw register */
781 start *= 1024/8;
782 space *= 1024/8;
783 end = start + space - 1;
793b883e 784
cd28ab6a
SH		 785 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
786 sky2_write32(hw, RB_ADDR(q, RB_START), start);
787 sky2_write32(hw, RB_ADDR(q, RB_END), end);
788 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
789 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
790
791 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 792 u32 tp = space - space/4;
793b883e 793
1c28f6ba
SH		 794 /* On receive queue's set the thresholds
795 * give receiver priority when > 3/4 full
796 * send pause when down to 2K
797 */
798 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
799 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 800
1c28f6ba
SH		 801 tp = space - 2048/8;
802 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
803 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 804 } else {
805 /* Enable store & forward on Tx queue's because
806 * Tx FIFO is only 1K on Yukon
807 */
808 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
809 }
810
811 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 812 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 813}
814
cd28ab6a 815/* Setup Bus Memory Interface */
af4ed7e6 816static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 817{
818 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
819 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
820 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 821 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 822}
823
cd28ab6a
SH		 824/* Setup prefetch unit registers. This is the interface between
825 * hardware and driver list elements
826 */
8cc048e3 827static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 828 u64 addr, u32 last)
829{
cd28ab6a
SH		 830 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
831 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
832 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
833 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
834 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
835 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 836
837 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 838}
839
793b883e
SH		 840static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
841{
842 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
843
cb5d9547 844 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 845 le->ctrl = 0;
793b883e
SH		 846 return le;
847}
cd28ab6a 848
291ea614
SH		 849static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
850 struct sky2_tx_le *le)
851{
852 return sky2->tx_ring + (le - sky2->tx_le);
853}
854
290d4de5
SH		 855/* Update chip's next pointer */
856static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 857{
50432cb5 858 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 859 wmb();
50432cb5
SH		 860 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
861
862 /* Synchronize I/O on since next processor may write to tail */
863 mmiowb();
cd28ab6a
SH		 864}
865
793b883e 866
cd28ab6a
SH		 867static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
868{
869 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 870 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 871 le->ctrl = 0;
cd28ab6a
SH		 872 return le;
873}
874
a018e330 875/* Return high part of DMA address (could be 32 or 64 bit) */
876static inline u32 high32(dma_addr_t a)
877{
a036119f 878 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330 879}
880
14d0263f
SH		 881/* Build description to hardware for one receive segment */
882static void sky2_rx_add(struct sky2_port *sky2, u8 op,
883 dma_addr_t map, unsigned len)
cd28ab6a
SH		 884{
885 struct sky2_rx_le *le;
734d1868 886 u32 hi = high32(map);
cd28ab6a 887
793b883e 888 if (sky2->rx_addr64 != hi) {
cd28ab6a 889 le = sky2_next_rx(sky2);
793b883e 890 le->addr = cpu_to_le32(hi);
cd28ab6a 891 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 892 sky2->rx_addr64 = high32(map + len);
cd28ab6a 893 }
793b883e 894
cd28ab6a 895 le = sky2_next_rx(sky2);
734d1868
SH		 896 le->addr = cpu_to_le32((u32) map);
897 le->length = cpu_to_le16(len);
14d0263f 898 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 899}
900
14d0263f
SH		 901/* Build description to hardware for one possibly fragmented skb */
902static void sky2_rx_submit(struct sky2_port *sky2,
903 const struct rx_ring_info *re)
904{
905 int i;
906
907 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
908
909 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
910 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
911}
912
913
914static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
915 unsigned size)
916{
917 struct sk_buff *skb = re->skb;
918 int i;
919
920 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
921 pci_unmap_len_set(re, data_size, size);
922
923 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
924 re->frag_addr[i] = pci_map_page(pdev,
925 skb_shinfo(skb)->frags[i].page,
926 skb_shinfo(skb)->frags[i].page_offset,
927 skb_shinfo(skb)->frags[i].size,
928 PCI_DMA_FROMDEVICE);
929}
930
931static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
932{
933 struct sk_buff *skb = re->skb;
934 int i;
935
936 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
937 PCI_DMA_FROMDEVICE);
938
939 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
940 pci_unmap_page(pdev, re->frag_addr[i],
941 skb_shinfo(skb)->frags[i].size,
942 PCI_DMA_FROMDEVICE);
943}
793b883e 944
cd28ab6a
SH		 945/* Tell chip where to start receive checksum.
946 * Actually has two checksums, but set both same to avoid possible byte
947 * order problems.
948 */
793b883e 949static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 950{
951 struct sky2_rx_le *le;
952
cd28ab6a 953 le = sky2_next_rx(sky2);
f65b138c 954 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
cd28ab6a
SH		 955 le->ctrl = 0;
956 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 957
793b883e
SH		 958 sky2_write32(sky2->hw,
959 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
960 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 961
962}
963
6b1a3aef 964/*
965 * The RX Stop command will not work for Yukon-2 if the BMU does not
966 * reach the end of packet and since we can't make sure that we have
967 * incoming data, we must reset the BMU while it is not doing a DMA
968 * transfer. Since it is possible that the RX path is still active,
969 * the RX RAM buffer will be stopped first, so any possible incoming
970 * data will not trigger a DMA. After the RAM buffer is stopped, the
971 * BMU is polled until any DMA in progress is ended and only then it
972 * will be reset.
973 */
974static void sky2_rx_stop(struct sky2_port *sky2)
975{
976 struct sky2_hw *hw = sky2->hw;
977 unsigned rxq = rxqaddr[sky2->port];
978 int i;
979
980 /* disable the RAM Buffer receive queue */
981 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
982
983 for (i = 0; i < 0xffff; i++)
984 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
985 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
986 goto stopped;
987
988 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
989 sky2->netdev->name);
990stopped:
991 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
992
993 /* reset the Rx prefetch unit */
994 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 995 mmiowb();
6b1a3aef 996}
793b883e 997
d571b694 998/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 999static void sky2_rx_clean(struct sky2_port *sky2)
1000{
1001 unsigned i;
1002
1003 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1004 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1005 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1006
1007 if (re->skb) {
14d0263f 1008 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1009 kfree_skb(re->skb);
1010 re->skb = NULL;
1011 }
1012 }
1013}
1014
ef743d33 1015/* Basic MII support */
1016static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1017{
1018 struct mii_ioctl_data *data = if_mii(ifr);
1019 struct sky2_port *sky2 = netdev_priv(dev);
1020 struct sky2_hw *hw = sky2->hw;
1021 int err = -EOPNOTSUPP;
1022
1023 if (!netif_running(dev))
1024 return -ENODEV; /* Phy still in reset */
1025
d89e1343 1026 switch (cmd) {
ef743d33 1027 case SIOCGMIIPHY:
1028 data->phy_id = PHY_ADDR_MARV;
1029
1030 /* fallthru */
1031 case SIOCGMIIREG: {
1032 u16 val = 0;
91c86df5 1033
e07b1aa8 1034 spin_lock_bh(&sky2->phy_lock);
ef743d33 1035 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1036 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1037
ef743d33 1038 data->val_out = val;
1039 break;
1040 }
1041
1042 case SIOCSMIIREG:
1043 if (!capable(CAP_NET_ADMIN))
1044 return -EPERM;
1045
e07b1aa8 1046 spin_lock_bh(&sky2->phy_lock);
ef743d33 1047 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1048 data->val_in);
e07b1aa8 1049 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1050 break;
1051 }
1052 return err;
1053}
1054
d1f13708 1055#ifdef SKY2_VLAN_TAG_USED
1056static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1057{
1058 struct sky2_port *sky2 = netdev_priv(dev);
1059 struct sky2_hw *hw = sky2->hw;
1060 u16 port = sky2->port;
d1f13708 1061
2bb8c262 1062 netif_tx_lock_bh(dev);
3d4e66f5 1063 netif_poll_disable(sky2->hw->dev[0]);
d1f13708 1064
d1f13708 1065 sky2->vlgrp = grp;
3d4e66f5
SH		 1066 if (grp) {
1067 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1068 RX_VLAN_STRIP_ON);
1069 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1070 TX_VLAN_TAG_ON);
1071 } else {
1072 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1073 RX_VLAN_STRIP_OFF);
1074 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1075 TX_VLAN_TAG_OFF);
1076 }
d1f13708 1077
3d4e66f5 1078 netif_poll_enable(sky2->hw->dev[0]);
2bb8c262 1079 netif_tx_unlock_bh(dev);
d1f13708 1080}
1081#endif
1082
82788c7a 1083/*
14d0263f
SH		 1084 * Allocate an skb for receiving. If the MTU is large enough
1085 * make the skb non-linear with a fragment list of pages.
1086 *
82788c7a
SH		 1087 * It appears the hardware has a bug in the FIFO logic that
1088 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86 1089 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1090 * aligned except if slab debugging is enabled.
82788c7a 1091 */
14d0263f 1092static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1093{
1094 struct sk_buff *skb;
14d0263f
SH		 1095 unsigned long p;
1096 int i;
82788c7a 1097
14d0263f
SH		 1098 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1099 if (!skb)
1100 goto nomem;
1101
1102 p = (unsigned long) skb->data;
1103 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1104
1105 for (i = 0; i < sky2->rx_nfrags; i++) {
1106 struct page *page = alloc_page(GFP_ATOMIC);
1107
1108 if (!page)
1109 goto free_partial;
1110 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1111 }
1112
1113 return skb;
14d0263f
SH		 1114free_partial:
1115 kfree_skb(skb);
1116nomem:
1117 return NULL;
82788c7a
SH		 1118}
1119
cd28ab6a
SH		 1120/*
1121 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1122 * Normal case this ends up creating one list element for skb
1123 * in the receive ring. Worst case if using large MTU and each
1124 * allocation falls on a different 64 bit region, that results
1125 * in 6 list elements per ring entry.
1126 * One element is used for checksum enable/disable, and one
1127 * extra to avoid wrap.
cd28ab6a 1128 */
6b1a3aef 1129static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1130{
6b1a3aef 1131 struct sky2_hw *hw = sky2->hw;
14d0263f 1132 struct rx_ring_info *re;
6b1a3aef 1133 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1134 unsigned i, size, space, thresh;
cd28ab6a 1135
6b1a3aef 1136 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1137 sky2_qset(hw, rxq);
977bdf06 1138
c3905bc4
SH		 1139 /* On PCI express lowering the watermark gives better performance */
1140 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1141 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1142
1143 /* These chips have no ram buffer?
1144 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1145 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1146 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1147 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1148 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1149
6b1a3aef 1150 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1151
1152 rx_set_checksum(sky2);
14d0263f
SH		 1153
1154 /* Space needed for frame data + headers rounded up */
1155 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1156 + 8;
1157
1158 /* Stopping point for hardware truncation */
1159 thresh = (size - 8) / sizeof(u32);
1160
1161 /* Account for overhead of skb - to avoid order > 0 allocation */
1162 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1163 + sizeof(struct skb_shared_info);
1164
1165 sky2->rx_nfrags = space >> PAGE_SHIFT;
1166 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1167
1168 if (sky2->rx_nfrags != 0) {
1169 /* Compute residue after pages */
1170 space = sky2->rx_nfrags << PAGE_SHIFT;
1171
1172 if (space < size)
1173 size -= space;
1174 else
1175 size = 0;
1176
1177 /* Optimize to handle small packets and headers */
1178 if (size < copybreak)
1179 size = copybreak;
1180 if (size < ETH_HLEN)
1181 size = ETH_HLEN;
1182 }
1183 sky2->rx_data_size = size;
1184
1185 /* Fill Rx ring */
793b883e 1186 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1187 re = sky2->rx_ring + i;
cd28ab6a 1188
14d0263f 1189 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1190 if (!re->skb)
1191 goto nomem;
1192
14d0263f
SH		 1193 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1194 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1195 }
1196
a1433ac4
SH		 1197 /*
1198 * The receiver hangs if it receives frames larger than the
1199 * packet buffer. As a workaround, truncate oversize frames, but
1200 * the register is limited to 9 bits, so if you do frames > 2052
1201 * you better get the MTU right!
1202 */
a1433ac4
SH		 1203 if (thresh > 0x1ff)
1204 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1205 else {
1206 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1207 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1208 }
1209
6b1a3aef 1210 /* Tell chip about available buffers */
50432cb5 1211 sky2_put_idx(hw, rxq, sky2->rx_put);
cd28ab6a
SH		 1212 return 0;
1213nomem:
1214 sky2_rx_clean(sky2);
1215 return -ENOMEM;
1216}
1217
1218/* Bring up network interface. */
1219static int sky2_up(struct net_device *dev)
1220{
1221 struct sky2_port *sky2 = netdev_priv(dev);
1222 struct sky2_hw *hw = sky2->hw;
1223 unsigned port = sky2->port;
67712901 1224 u32 ramsize, imask;
ee7abb04 1225 int cap, err = -ENOMEM;
843a46f4 1226 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1227
ee7abb04
SH		 1228 /*
1229 * On dual port PCI-X card, there is an problem where status
1230 * can be received out of order due to split transactions
843a46f4 1231 */
ee7abb04
SH		 1232 if (otherdev && netif_running(otherdev) &&
1233 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1234 struct sky2_port *osky2 = netdev_priv(otherdev);
1235 u16 cmd;
1236
1237 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1238 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1239 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1240
1241 sky2->rx_csum = 0;
1242 osky2->rx_csum = 0;
1243 }
843a46f4 1244
cd28ab6a
SH		 1245 if (netif_msg_ifup(sky2))
1246 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1247
1248 /* must be power of 2 */
1249 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1250 TX_RING_SIZE *
1251 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1252 &sky2->tx_le_map);
1253 if (!sky2->tx_le)
1254 goto err_out;
1255
6cdbbdf3 1256 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1257 GFP_KERNEL);
1258 if (!sky2->tx_ring)
1259 goto err_out;
1260 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1261
1262 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1263 &sky2->rx_le_map);
1264 if (!sky2->rx_le)
1265 goto err_out;
1266 memset(sky2->rx_le, 0, RX_LE_BYTES);
1267
291ea614 1268 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1269 GFP_KERNEL);
1270 if (!sky2->rx_ring)
1271 goto err_out;
1272
d3bcfbeb 1273 sky2_phy_power(hw, port, 1);
1274
cd28ab6a
SH		 1275 sky2_mac_init(hw, port);
1276
67712901
SH		 1277 /* Register is number of 4K blocks on internal RAM buffer. */
1278 ramsize = sky2_read8(hw, B2_E_0) * 4;
1279 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1c28f6ba 1280
67712901
SH		 1281 if (ramsize > 0) {
1282 u32 rxspace;
cd28ab6a 1283
67712901
SH		 1284 if (ramsize < 16)
1285 rxspace = ramsize / 2;
1286 else
1287 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1288
67712901
SH		 1289 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1290 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1291
1292 /* Make sure SyncQ is disabled */
1293 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1294 RB_RST_SET);
1295 }
793b883e 1296
af4ed7e6 1297 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1298
977bdf06 1299 /* Set almost empty threshold */
c2716fb4
SH		 1300 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1301 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1302 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1303
6b1a3aef 1304 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1305 TX_RING_SIZE - 1);
cd28ab6a 1306
6b1a3aef 1307 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1308 if (err)
1309 goto err_out;
1310
cd28ab6a 1311 /* Enable interrupts from phy/mac for port */
e07b1aa8 1312 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1313 imask |= portirq_msk[port];
e07b1aa8
SH		 1314 sky2_write32(hw, B0_IMSK, imask);
1315
cd28ab6a
SH		 1316 return 0;
1317
1318err_out:
1b537565 1319 if (sky2->rx_le) {
cd28ab6a
SH		 1320 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1321 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1322 sky2->rx_le = NULL;
1323 }
1324 if (sky2->tx_le) {
cd28ab6a
SH		 1325 pci_free_consistent(hw->pdev,
1326 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1327 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1328 sky2->tx_le = NULL;
1329 }
1330 kfree(sky2->tx_ring);
1331 kfree(sky2->rx_ring);
cd28ab6a 1332
1b537565
SH		 1333 sky2->tx_ring = NULL;
1334 sky2->rx_ring = NULL;
cd28ab6a
SH		 1335 return err;
1336}
1337
793b883e
SH		 1338/* Modular subtraction in ring */
1339static inline int tx_dist(unsigned tail, unsigned head)
1340{
cb5d9547 1341 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1342}
cd28ab6a 1343
793b883e
SH		 1344/* Number of list elements available for next tx */
1345static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1346{
793b883e 1347 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1348}
1349
793b883e 1350/* Estimate of number of transmit list elements required */
28bd181a 1351static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1352{
793b883e
SH		 1353 unsigned count;
1354
1355 count = sizeof(dma_addr_t) / sizeof(u32);
1356 count += skb_shinfo(skb)->nr_frags * count;
1357
89114afd 1358 if (skb_is_gso(skb))
793b883e
SH		 1359 ++count;
1360
84fa7933 1361 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1362 ++count;
1363
1364 return count;
cd28ab6a
SH		 1365}
1366
793b883e
SH		 1367/*
1368 * Put one packet in ring for transmit.
1369 * A single packet can generate multiple list elements, and
1370 * the number of ring elements will probably be less than the number
1371 * of list elements used.
1372 */
cd28ab6a
SH		 1373static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1374{
1375 struct sky2_port *sky2 = netdev_priv(dev);
1376 struct sky2_hw *hw = sky2->hw;
d1f13708 1377 struct sky2_tx_le *le = NULL;
6cdbbdf3 1378 struct tx_ring_info *re;
cd28ab6a
SH		 1379 unsigned i, len;
1380 dma_addr_t mapping;
1381 u32 addr64;
1382 u16 mss;
1383 u8 ctrl;
1384
2bb8c262
SH		 1385 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1386 return NETDEV_TX_BUSY;
cd28ab6a 1387
793b883e 1388 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1389 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1390 dev->name, sky2->tx_prod, skb->len);
1391
cd28ab6a
SH		 1392 len = skb_headlen(skb);
1393 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1394 addr64 = high32(mapping);
793b883e 1395
a018e330 1396 /* Send high bits if changed or crosses boundary */
1397 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1398 le = get_tx_le(sky2);
f65b138c 1399 le->addr = cpu_to_le32(addr64);
793b883e 1400 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1401 sky2->tx_addr64 = high32(mapping + len);
793b883e 1402 }
cd28ab6a
SH		 1403
1404 /* Check for TCP Segmentation Offload */
7967168c 1405 mss = skb_shinfo(skb)->gso_size;
793b883e 1406 if (mss != 0) {
ab6a5bb6 1407 mss += tcp_optlen(skb); /* TCP options */
c9bdd4b5 1408 mss += ip_hdrlen(skb) + sizeof(struct tcphdr);
cd28ab6a
SH		 1409 mss += ETH_HLEN;
1410
e07560cd 1411 if (mss != sky2->tx_last_mss) {
1412 le = get_tx_le(sky2);
f65b138c 1413 le->addr = cpu_to_le32(mss);
e07560cd 1414 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1415 sky2->tx_last_mss = mss;
1416 }
cd28ab6a
SH		 1417 }
1418
cd28ab6a 1419 ctrl = 0;
d1f13708 1420#ifdef SKY2_VLAN_TAG_USED
1421 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1422 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1423 if (!le) {
1424 le = get_tx_le(sky2);
f65b138c 1425 le->addr = 0;
d1f13708 1426 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1427 } else
1428 le->opcode |= OP_VLAN;
1429 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1430 ctrl |= INS_VLAN;
1431 }
1432#endif
1433
1434 /* Handle TCP checksum offload */
84fa7933 1435 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ea2ae17d 1436 const unsigned offset = skb_transport_offset(skb);
f65b138c
SH		 1437 u32 tcpsum;
1438
1439 tcpsum = offset << 16; /* sum start */
ff1dcadb 1440 tcpsum |= offset + skb->csum_offset; /* sum write */
cd28ab6a 1441
56069c0f 1442 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
eddc9ec5 1443 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
cd28ab6a
SH		 1444 ctrl |= UDPTCP;
1445
f65b138c
SH		 1446 if (tcpsum != sky2->tx_tcpsum) {
1447 sky2->tx_tcpsum = tcpsum;
1d179332 1448
1449 le = get_tx_le(sky2);
f65b138c 1450 le->addr = cpu_to_le32(tcpsum);
1d179332 1451 le->length = 0; /* initial checksum value */
1452 le->ctrl = 1; /* one packet */
1453 le->opcode = OP_TCPLISW | HW_OWNER;
1454 }
cd28ab6a
SH		 1455 }
1456
1457 le = get_tx_le(sky2);
f65b138c 1458 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1459 le->length = cpu_to_le16(len);
1460 le->ctrl = ctrl;
793b883e 1461 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1462
291ea614 1463 re = tx_le_re(sky2, le);
cd28ab6a 1464 re->skb = skb;
6cdbbdf3 1465 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1466 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1467
1468 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1469 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1470
1471 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1472 frag->size, PCI_DMA_TODEVICE);
a036119f 1473 addr64 = high32(mapping);
793b883e
SH		 1474 if (addr64 != sky2->tx_addr64) {
1475 le = get_tx_le(sky2);
f65b138c 1476 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1477 le->ctrl = 0;
1478 le->opcode = OP_ADDR64 | HW_OWNER;
1479 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1480 }
1481
1482 le = get_tx_le(sky2);
f65b138c 1483 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1484 le->length = cpu_to_le16(frag->size);
1485 le->ctrl = ctrl;
793b883e 1486 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1487
291ea614
SH		 1488 re = tx_le_re(sky2, le);
1489 re->skb = skb;
1490 pci_unmap_addr_set(re, mapaddr, mapping);
1491 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1492 }
6cdbbdf3 1493
cd28ab6a
SH		 1494 le->ctrl |= EOP;
1495
97bda706 1496 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1497 netif_stop_queue(dev);
b19666d9 1498
290d4de5 1499 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1500
cd28ab6a
SH		 1501 dev->trans_start = jiffies;
1502 return NETDEV_TX_OK;
1503}
1504
cd28ab6a 1505/*
793b883e
SH		 1506 * Free ring elements from starting at tx_cons until "done"
1507 *
1508 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1509 * buffers so make sure not to free skb to early.
cd28ab6a 1510 */
d11c13e7 1511static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1512{
d11c13e7 1513 struct net_device *dev = sky2->netdev;
af2a58ac 1514 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1515 unsigned idx;
cd28ab6a 1516
0e3ff6aa 1517 BUG_ON(done >= TX_RING_SIZE);
2224795d 1518
291ea614
SH		 1519 for (idx = sky2->tx_cons; idx != done;
1520 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1521 struct sky2_tx_le *le = sky2->tx_le + idx;
1522 struct tx_ring_info *re = sky2->tx_ring + idx;
1523
1524 switch(le->opcode & ~HW_OWNER) {
1525 case OP_LARGESEND:
1526 case OP_PACKET:
1527 pci_unmap_single(pdev,
1528 pci_unmap_addr(re, mapaddr),
1529 pci_unmap_len(re, maplen),
1530 PCI_DMA_TODEVICE);
af2a58ac 1531 break;
291ea614
SH		 1532 case OP_BUFFER:
1533 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1534 pci_unmap_len(re, maplen),
734d1868 1535 PCI_DMA_TODEVICE);
291ea614
SH		 1536 break;
1537 }
1538
1539 if (le->ctrl & EOP) {
1540 if (unlikely(netif_msg_tx_done(sky2)))
1541 printk(KERN_DEBUG "%s: tx done %u\n",
1542 dev->name, idx);
2bf56fe2 1543 sky2->net_stats.tx_packets++;
1544 sky2->net_stats.tx_bytes += re->skb->len;
1545
794b2bd2 1546 dev_kfree_skb_any(re->skb);
cd28ab6a
SH		 1547 }
1548
291ea614 1549 le->opcode = 0; /* paranoia */
793b883e 1550 }
793b883e 1551
291ea614 1552 sky2->tx_cons = idx;
50432cb5
SH		 1553 smp_mb();
1554
22e11703 1555 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1556 netif_wake_queue(dev);
cd28ab6a
SH		 1557}
1558
1559/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1560static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1561{
2bb8c262
SH		 1562 struct sky2_port *sky2 = netdev_priv(dev);
1563
1564 netif_tx_lock_bh(dev);
d11c13e7 1565 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1566 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1567}
1568
1569/* Network shutdown */
1570static int sky2_down(struct net_device *dev)
1571{
1572 struct sky2_port *sky2 = netdev_priv(dev);
1573 struct sky2_hw *hw = sky2->hw;
1574 unsigned port = sky2->port;
1575 u16 ctrl;
e07b1aa8 1576 u32 imask;
cd28ab6a 1577
1b537565
SH		 1578 /* Never really got started! */
1579 if (!sky2->tx_le)
1580 return 0;
1581
cd28ab6a
SH		 1582 if (netif_msg_ifdown(sky2))
1583 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1584
018d1c66 1585 /* Stop more packets from being queued */
cd28ab6a 1586 netif_stop_queue(dev);
9a87240c 1587 netif_carrier_off(dev);
cd28ab6a 1588
ebc646f6
SH		 1589 /* Disable port IRQ */
1590 imask = sky2_read32(hw, B0_IMSK);
1591 imask &= ~portirq_msk[port];
1592 sky2_write32(hw, B0_IMSK, imask);
1593
d3bcfbeb 1594 sky2_gmac_reset(hw, port);
793b883e 1595
cd28ab6a
SH		 1596 /* Stop transmitter */
1597 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1598 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1599
1600 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1601 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1602
1603 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1604 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1605 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1606
1607 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1608
1609 /* Workaround shared GMAC reset */
793b883e
SH		 1610 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1611 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1612 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1613
1614 /* Disable Force Sync bit and Enable Alloc bit */
1615 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1616 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1617
1618 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1619 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1620 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1621
1622 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1623 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1624 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1625
1626 /* Reset the Tx prefetch units */
1627 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1628 PREF_UNIT_RST_SET);
1629
1630 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1631
6b1a3aef 1632 sky2_rx_stop(sky2);
cd28ab6a
SH		 1633
1634 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1635 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1636
d3bcfbeb 1637 sky2_phy_power(hw, port, 0);
1638
d571b694 1639 /* turn off LED's */
cd28ab6a
SH		 1640 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1641
018d1c66 1642 synchronize_irq(hw->pdev->irq);
1643
2bb8c262 1644 sky2_tx_clean(dev);
cd28ab6a
SH		 1645 sky2_rx_clean(sky2);
1646
1647 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1648 sky2->rx_le, sky2->rx_le_map);
1649 kfree(sky2->rx_ring);
1650
1651 pci_free_consistent(hw->pdev,
1652 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1653 sky2->tx_le, sky2->tx_le_map);
1654 kfree(sky2->tx_ring);
1655
1b537565
SH		 1656 sky2->tx_le = NULL;
1657 sky2->rx_le = NULL;
1658
1659 sky2->rx_ring = NULL;
1660 sky2->tx_ring = NULL;
1661
cd28ab6a
SH		 1662 return 0;
1663}
1664
1665static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1666{
b89165f2 1667 if (!sky2_is_copper(hw))
793b883e
SH		 1668 return SPEED_1000;
1669
cd28ab6a
SH		 1670 if (hw->chip_id == CHIP_ID_YUKON_FE)
1671 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1672
1673 switch (aux & PHY_M_PS_SPEED_MSK) {
1674 case PHY_M_PS_SPEED_1000:
1675 return SPEED_1000;
1676 case PHY_M_PS_SPEED_100:
1677 return SPEED_100;
1678 default:
1679 return SPEED_10;
1680 }
1681}
1682
1683static void sky2_link_up(struct sky2_port *sky2)
1684{
1685 struct sky2_hw *hw = sky2->hw;
1686 unsigned port = sky2->port;
1687 u16 reg;
16ad91e1
SH		 1688 static const char *fc_name[] = {
1689 [FC_NONE] = "none",
1690 [FC_TX] = "tx",
1691 [FC_RX] = "rx",
1692 [FC_BOTH] = "both",
1693 };
cd28ab6a 1694
cd28ab6a 1695 /* enable Rx/Tx */
2eaba1a2 1696 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1697 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1698 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1699
1700 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1701
1702 netif_carrier_on(sky2->netdev);
1703 netif_wake_queue(sky2->netdev);
1704
1705 /* Turn on link LED */
793b883e 1706 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1707 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1708
93745494
SH		 1709 if (hw->chip_id == CHIP_ID_YUKON_XL
1710 || hw->chip_id == CHIP_ID_YUKON_EC_U
1711 || hw->chip_id == CHIP_ID_YUKON_EX) {
793b883e 1712 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1713 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1714
1715 switch(sky2->speed) {
1716 case SPEED_10:
1717 led |= PHY_M_LEDC_INIT_CTRL(7);
1718 break;
1719
1720 case SPEED_100:
1721 led |= PHY_M_LEDC_STA1_CTRL(7);
1722 break;
1723
1724 case SPEED_1000:
1725 led |= PHY_M_LEDC_STA0_CTRL(7);
1726 break;
1727 }
793b883e
SH		 1728
1729 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1730 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1731 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1732 }
1733
cd28ab6a
SH		 1734 if (netif_msg_link(sky2))
1735 printk(KERN_INFO PFX
d571b694 1736 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1737 sky2->netdev->name, sky2->speed,
1738 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1739 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1740}
1741
1742static void sky2_link_down(struct sky2_port *sky2)
1743{
1744 struct sky2_hw *hw = sky2->hw;
1745 unsigned port = sky2->port;
1746 u16 reg;
1747
1748 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1749
1750 reg = gma_read16(hw, port, GM_GP_CTRL);
1751 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1752 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1753
cd28ab6a
SH		 1754 netif_carrier_off(sky2->netdev);
1755 netif_stop_queue(sky2->netdev);
1756
1757 /* Turn on link LED */
1758 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1759
1760 if (netif_msg_link(sky2))
1761 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1762
cd28ab6a
SH		 1763 sky2_phy_init(hw, port);
1764}
1765
16ad91e1
SH		 1766static enum flow_control sky2_flow(int rx, int tx)
1767{
1768 if (rx)
1769 return tx ? FC_BOTH : FC_RX;
1770 else
1771 return tx ? FC_TX : FC_NONE;
1772}
1773
793b883e
SH		 1774static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1775{
1776 struct sky2_hw *hw = sky2->hw;
1777 unsigned port = sky2->port;
da4c1ff4 1778 u16 advert, lpa;
793b883e 1779
da4c1ff4 1780 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1781 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1782 if (lpa & PHY_M_AN_RF) {
1783 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1784 return -1;
1785 }
1786
793b883e
SH		 1787 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1788 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1789 sky2->netdev->name);
1790 return -1;
1791 }
1792
793b883e 1793 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1794 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1795
da4c1ff4
SH		 1796 /* Since the pause result bits seem to in different positions on
1797 * different chips. look at registers.
1798 */
1799 if (!sky2_is_copper(hw)) {
1800 /* Shift for bits in fiber PHY */
1801 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1802 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1803
1804 if (advert & ADVERTISE_1000XPAUSE)
1805 advert |= ADVERTISE_PAUSE_CAP;
1806 if (advert & ADVERTISE_1000XPSE_ASYM)
1807 advert |= ADVERTISE_PAUSE_ASYM;
1808 if (lpa & LPA_1000XPAUSE)
1809 lpa |= LPA_PAUSE_CAP;
1810 if (lpa & LPA_1000XPAUSE_ASYM)
1811 lpa |= LPA_PAUSE_ASYM;
1812 }
793b883e 1813
da4c1ff4
SH		 1814 sky2->flow_status = FC_NONE;
1815 if (advert & ADVERTISE_PAUSE_CAP) {
1816 if (lpa & LPA_PAUSE_CAP)
1817 sky2->flow_status = FC_BOTH;
1818 else if (advert & ADVERTISE_PAUSE_ASYM)
1819 sky2->flow_status = FC_RX;
1820 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1821 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1822 sky2->flow_status = FC_TX;
1823 }
793b883e 1824
16ad91e1 1825 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1826 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1827 sky2->flow_status = FC_NONE;
2eaba1a2 1828
da4c1ff4 1829 if (sky2->flow_status & FC_TX)
793b883e
SH		 1830 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1831 else
1832 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1833
1834 return 0;
1835}
cd28ab6a 1836
e07b1aa8
SH		 1837/* Interrupt from PHY */
1838static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1839{
e07b1aa8
SH		 1840 struct net_device *dev = hw->dev[port];
1841 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1842 u16 istatus, phystat;
1843
ebc646f6
SH		 1844 if (!netif_running(dev))
1845 return;
1846
e07b1aa8
SH		 1847 spin_lock(&sky2->phy_lock);
1848 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1849 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1850
cd28ab6a
SH		 1851 if (netif_msg_intr(sky2))
1852 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1853 sky2->netdev->name, istatus, phystat);
1854
2eaba1a2 1855 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1856 if (sky2_autoneg_done(sky2, phystat) == 0)
1857 sky2_link_up(sky2);
1858 goto out;
1859 }
cd28ab6a 1860
793b883e
SH		 1861 if (istatus & PHY_M_IS_LSP_CHANGE)
1862 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1863
793b883e
SH		 1864 if (istatus & PHY_M_IS_DUP_CHANGE)
1865 sky2->duplex =
1866 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1867
793b883e
SH		 1868 if (istatus & PHY_M_IS_LST_CHANGE) {
1869 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1870 sky2_link_up(sky2);
793b883e
SH		 1871 else
1872 sky2_link_down(sky2);
cd28ab6a 1873 }
793b883e 1874out:
e07b1aa8 1875 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1876}
1877
62335ab0 1878/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1879 * and tx queue is full (stopped).
1880 */
cd28ab6a
SH		 1881static void sky2_tx_timeout(struct net_device *dev)
1882{
1883 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1884 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1885
1886 if (netif_msg_timer(sky2))
1887 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1888
8f24664d 1889 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1890 dev->name, sky2->tx_cons, sky2->tx_prod,
1891 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1892 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1893
81906791
SH		 1894 /* can't restart safely under softirq */
1895 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1896}
1897
1898static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1899{
6b1a3aef 1900 struct sky2_port *sky2 = netdev_priv(dev);
1901 struct sky2_hw *hw = sky2->hw;
b628ed98 1902 unsigned port = sky2->port;
6b1a3aef 1903 int err;
1904 u16 ctl, mode;
e07b1aa8 1905 u32 imask;
cd28ab6a
SH		 1906
1907 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1908 return -EINVAL;
1909
d2adf4f6
SH		 1910 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1911 return -EINVAL;
1912
6b1a3aef 1913 if (!netif_running(dev)) {
1914 dev->mtu = new_mtu;
1915 return 0;
1916 }
1917
e07b1aa8 1918 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 1919 sky2_write32(hw, B0_IMSK, 0);
1920
018d1c66 1921 dev->trans_start = jiffies; /* prevent tx timeout */
1922 netif_stop_queue(dev);
1923 netif_poll_disable(hw->dev[0]);
1924
e07b1aa8
SH		 1925 synchronize_irq(hw->pdev->irq);
1926
b628ed98
SH		 1927 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
1928 if (new_mtu > ETH_DATA_LEN) {
1929 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1930 TX_JUMBO_ENA | TX_STFW_DIS);
1931 dev->features &= NETIF_F_TSO | NETIF_F_SG | NETIF_F_IP_CSUM;
1932 } else
1933 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1934 TX_JUMBO_DIS | TX_STFW_ENA);
1935 }
1936
1937 ctl = gma_read16(hw, port, GM_GP_CTRL);
1938 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 1939 sky2_rx_stop(sky2);
1940 sky2_rx_clean(sky2);
cd28ab6a
SH		 1941
1942 dev->mtu = new_mtu;
14d0263f 1943
6b1a3aef 1944 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1945 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1946
1947 if (dev->mtu > ETH_DATA_LEN)
1948 mode |= GM_SMOD_JUMBO_ENA;
1949
b628ed98 1950 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 1951
b628ed98 1952 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1953
6b1a3aef 1954 err = sky2_rx_start(sky2);
e07b1aa8 1955 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1956
1b537565
SH		 1957 if (err)
1958 dev_close(dev);
1959 else {
b628ed98 1960 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565
SH		 1961
1962 netif_poll_enable(hw->dev[0]);
1963 netif_wake_queue(dev);
1964 }
1965
cd28ab6a
SH		 1966 return err;
1967}
1968
14d0263f
SH		 1969/* For small just reuse existing skb for next receive */
1970static struct sk_buff *receive_copy(struct sky2_port *sky2,
1971 const struct rx_ring_info *re,
1972 unsigned length)
1973{
1974 struct sk_buff *skb;
1975
1976 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1977 if (likely(skb)) {
1978 skb_reserve(skb, 2);
1979 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1980 length, PCI_DMA_FROMDEVICE);
d626f62b 1981 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 1982 skb->ip_summed = re->skb->ip_summed;
1983 skb->csum = re->skb->csum;
1984 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1985 length, PCI_DMA_FROMDEVICE);
1986 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 1987 skb_put(skb, length);
14d0263f
SH		 1988 }
1989 return skb;
1990}
1991
1992/* Adjust length of skb with fragments to match received data */
1993static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1994 unsigned int length)
1995{
1996 int i, num_frags;
1997 unsigned int size;
1998
1999 /* put header into skb */
2000 size = min(length, hdr_space);
2001 skb->tail += size;
2002 skb->len += size;
2003 length -= size;
2004
2005 num_frags = skb_shinfo(skb)->nr_frags;
2006 for (i = 0; i < num_frags; i++) {
2007 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2008
2009 if (length == 0) {
2010 /* don't need this page */
2011 __free_page(frag->page);
2012 --skb_shinfo(skb)->nr_frags;
2013 } else {
2014 size = min(length, (unsigned) PAGE_SIZE);
2015
2016 frag->size = size;
2017 skb->data_len += size;
2018 skb->truesize += size;
2019 skb->len += size;
2020 length -= size;
2021 }
2022 }
2023}
2024
2025/* Normal packet - take skb from ring element and put in a new one */
2026static struct sk_buff *receive_new(struct sky2_port *sky2,
2027 struct rx_ring_info *re,
2028 unsigned int length)
2029{
2030 struct sk_buff *skb, *nskb;
2031 unsigned hdr_space = sky2->rx_data_size;
2032
2033 pr_debug(PFX "receive new length=%d\n", length);
2034
2035 /* Don't be tricky about reusing pages (yet) */
2036 nskb = sky2_rx_alloc(sky2);
2037 if (unlikely(!nskb))
2038 return NULL;
2039
2040 skb = re->skb;
2041 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2042
2043 prefetch(skb->data);
2044 re->skb = nskb;
2045 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2046
2047 if (skb_shinfo(skb)->nr_frags)
2048 skb_put_frags(skb, hdr_space, length);
2049 else
489b10c1 2050 skb_put(skb, length);
14d0263f
SH		 2051 return skb;
2052}
2053
cd28ab6a
SH		 2054/*
2055 * Receive one packet.
d571b694 2056 * For larger packets, get new buffer.
cd28ab6a 2057 */
497d7c86 2058static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2059 u16 length, u32 status)
2060{
497d7c86 2061 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2062 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2063 struct sk_buff *skb = NULL;
cd28ab6a
SH		 2064
2065 if (unlikely(netif_msg_rx_status(sky2)))
2066 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2067 dev->name, sky2->rx_next, status, length);
cd28ab6a 2068
793b883e 2069 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2070 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2071
42eeea01 2072 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2073 goto error;
2074
42eeea01 2075 if (!(status & GMR_FS_RX_OK))
2076 goto resubmit;
2077
14d0263f
SH		 2078 if (length < copybreak)
2079 skb = receive_copy(sky2, re, length);
2080 else
2081 skb = receive_new(sky2, re, length);
793b883e 2082resubmit:
14d0263f 2083 sky2_rx_submit(sky2, re);
79e57d32 2084
cd28ab6a
SH		 2085 return skb;
2086
2087error:
6e15b712 2088 ++sky2->net_stats.rx_errors;
b6d77734 2089 if (status & GMR_FS_RX_FF_OV) {
a79abdc6 2090 sky2->net_stats.rx_over_errors++;
b6d77734
SH		 2091 goto resubmit;
2092 }
6e15b712 2093
3be92a70 2094 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2095 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2096 dev->name, status, length);
793b883e
SH		 2097
2098 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2099 sky2->net_stats.rx_length_errors++;
2100 if (status & GMR_FS_FRAGMENT)
2101 sky2->net_stats.rx_frame_errors++;
2102 if (status & GMR_FS_CRC_ERR)
2103 sky2->net_stats.rx_crc_errors++;
79e57d32 2104
793b883e 2105 goto resubmit;
cd28ab6a
SH		 2106}
2107
e07b1aa8
SH		 2108/* Transmit complete */
2109static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2110{
e07b1aa8 2111 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2112
e07b1aa8 2113 if (netif_running(dev)) {
2bb8c262 2114 netif_tx_lock(dev);
e07b1aa8 2115 sky2_tx_complete(sky2, last);
2bb8c262 2116 netif_tx_unlock(dev);
2224795d 2117 }
cd28ab6a
SH		 2118}
2119
e07b1aa8
SH		 2120/* Process status response ring */
2121static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2122{
22e11703 2123 struct sky2_port *sky2;
e07b1aa8 2124 int work_done = 0;
22e11703 2125 unsigned buf_write[2] = { 0, 0 };
e71ebd73 2126 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2127
af2a58ac 2128 rmb();
bea86103 2129
e71ebd73 2130 while (hw->st_idx != hwidx) {
13210ce5 2131 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2132 struct net_device *dev;
cd28ab6a 2133 struct sk_buff *skb;
cd28ab6a
SH		 2134 u32 status;
2135 u16 length;
2136
cb5d9547 2137 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2138
e71ebd73
SH		 2139 BUG_ON(le->link >= 2);
2140 dev = hw->dev[le->link];
13210ce5 2141
2142 sky2 = netdev_priv(dev);
f65b138c
SH		 2143 length = le16_to_cpu(le->length);
2144 status = le32_to_cpu(le->status);
cd28ab6a 2145
e71ebd73 2146 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2147 case OP_RXSTAT:
497d7c86 2148 skb = sky2_receive(dev, length, status);
3225b919
SH		 2149 if (unlikely(!skb)) {
2150 sky2->net_stats.rx_dropped++;
5df79111 2151 goto force_update;
3225b919 2152 }
13210ce5 2153
13210ce5 2154 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2155 sky2->net_stats.rx_packets++;
2156 sky2->net_stats.rx_bytes += skb->len;
13210ce5 2157 dev->last_rx = jiffies;
2158
d1f13708 2159#ifdef SKY2_VLAN_TAG_USED
2160 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2161 vlan_hwaccel_receive_skb(skb,
2162 sky2->vlgrp,
2163 be16_to_cpu(sky2->rx_tag));
2164 } else
2165#endif
cd28ab6a 2166 netif_receive_skb(skb);
13210ce5 2167
22e11703
SH		 2168 /* Update receiver after 16 frames */
2169 if (++buf_write[le->link] == RX_BUF_WRITE) {
5df79111
SH		 2170force_update:
2171 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
22e11703
SH		 2172 buf_write[le->link] = 0;
2173 }
2174
2175 /* Stop after net poll weight */
13210ce5 2176 if (++work_done >= to_do)
2177 goto exit_loop;
cd28ab6a
SH		 2178 break;
2179
d1f13708 2180#ifdef SKY2_VLAN_TAG_USED
2181 case OP_RXVLAN:
2182 sky2->rx_tag = length;
2183 break;
2184
2185 case OP_RXCHKSVLAN:
2186 sky2->rx_tag = length;
2187 /* fall through */
2188#endif
cd28ab6a 2189 case OP_RXCHKS:
87418307
SH		 2190 if (!sky2->rx_csum)
2191 break;
2192
2193 /* Both checksum counters are programmed to start at
2194 * the same offset, so unless there is a problem they
2195 * should match. This failure is an early indication that
2196 * hardware receive checksumming won't work.
2197 */
2198 if (likely(status >> 16 == (status & 0xffff))) {
2199 skb = sky2->rx_ring[sky2->rx_next].skb;
2200 skb->ip_summed = CHECKSUM_COMPLETE;
2201 skb->csum = status & 0xffff;
2202 } else {
2203 printk(KERN_NOTICE PFX "%s: hardware receive "
2204 "checksum problem (status = %#x)\n",
2205 dev->name, status);
2206 sky2->rx_csum = 0;
2207 sky2_write32(sky2->hw,
2208 Q_ADDR(rxqaddr[le->link], Q_CSR),
2209 BMU_DIS_RX_CHKSUM);
2210 }
cd28ab6a
SH		 2211 break;
2212
2213 case OP_TXINDEXLE:
13b97b74 2214 /* TX index reports status for both ports */
f55925d7
SH		 2215 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2216 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2217 if (hw->dev[1])
2218 sky2_tx_done(hw->dev[1],
2219 ((status >> 24) & 0xff)
2220 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2221 break;
2222
cd28ab6a
SH		 2223 default:
2224 if (net_ratelimit())
793b883e 2225 printk(KERN_WARNING PFX
e71ebd73
SH		 2226 "unknown status opcode 0x%x\n", le->opcode);
2227 goto exit_loop;
cd28ab6a 2228 }
13210ce5 2229 }
cd28ab6a 2230
fe2a24df
SH		 2231 /* Fully processed status ring so clear irq */
2232 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
50432cb5 2233 mmiowb();
fe2a24df 2234
13210ce5 2235exit_loop:
22e11703
SH		 2236 if (buf_write[0]) {
2237 sky2 = netdev_priv(hw->dev[0]);
2238 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2239 }
2240
2241 if (buf_write[1]) {
2242 sky2 = netdev_priv(hw->dev[1]);
2243 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2244 }
2245
e07b1aa8 2246 return work_done;
cd28ab6a
SH		 2247}
2248
2249static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2250{
2251 struct net_device *dev = hw->dev[port];
2252
3be92a70
SH		 2253 if (net_ratelimit())
2254 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2255 dev->name, status);
cd28ab6a
SH		 2256
2257 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2258 if (net_ratelimit())
2259 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2260 dev->name);
cd28ab6a
SH		 2261 /* Clear IRQ */
2262 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2263 }
2264
2265 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2266 if (net_ratelimit())
2267 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2268 dev->name);
cd28ab6a
SH		 2269
2270 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2271 }
2272
2273 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2274 if (net_ratelimit())
2275 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2276 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2277 }
2278
2279 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2280 if (net_ratelimit())
2281 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2282 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2283 }
2284
2285 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2286 if (net_ratelimit())
2287 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2288 dev->name);
cd28ab6a
SH		 2289 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2290 }
2291}
2292
2293static void sky2_hw_intr(struct sky2_hw *hw)
2294{
2295 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2296
793b883e 2297 if (status & Y2_IS_TIST_OV)
cd28ab6a 2298 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2299
2300 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2301 u16 pci_err;
2302
56a645cc 2303 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2304 if (net_ratelimit())
b02a9258
SH		 2305 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2306 pci_err);
cd28ab6a
SH		 2307
2308 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2309 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2310 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2311 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2312 }
2313
2314 if (status & Y2_IS_PCI_EXP) {
d571b694 2315 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2316 u32 pex_err;
2317
7bd656d1 2318 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2319
3be92a70 2320 if (net_ratelimit())
b02a9258
SH		 2321 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2322 pex_err);
cd28ab6a
SH		 2323
2324 /* clear the interrupt */
2325 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2326 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2327 0xffffffffUL);
cd28ab6a
SH		 2328 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2329
7bd656d1 2330 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2331 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2332 hwmsk &= ~Y2_IS_PCI_EXP;
2333 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2334 }
2335 }
2336
2337 if (status & Y2_HWE_L1_MASK)
2338 sky2_hw_error(hw, 0, status);
2339 status >>= 8;
2340 if (status & Y2_HWE_L1_MASK)
2341 sky2_hw_error(hw, 1, status);
2342}
2343
2344static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2345{
2346 struct net_device *dev = hw->dev[port];
2347 struct sky2_port *sky2 = netdev_priv(dev);
2348 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2349
2350 if (netif_msg_intr(sky2))
2351 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2352 dev->name, status);
2353
a3caeada
SH		 2354 if (status & GM_IS_RX_CO_OV)
2355 gma_read16(hw, port, GM_RX_IRQ_SRC);
2356
2357 if (status & GM_IS_TX_CO_OV)
2358 gma_read16(hw, port, GM_TX_IRQ_SRC);
2359
cd28ab6a
SH		 2360 if (status & GM_IS_RX_FF_OR) {
2361 ++sky2->net_stats.rx_fifo_errors;
2362 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2363 }
2364
2365 if (status & GM_IS_TX_FF_UR) {
2366 ++sky2->net_stats.tx_fifo_errors;
2367 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2368 }
cd28ab6a
SH		 2369}
2370
40b01727
SH		 2371/* This should never happen it is a bug. */
2372static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2373 u16 q, unsigned ring_size)
d257924e
SH		 2374{
2375 struct net_device *dev = hw->dev[port];
2376 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2377 unsigned idx;
2378 const u64 *le = (q == Q_R1 || q == Q_R2)
2379 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2380
40b01727
SH		 2381 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2382 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2383 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2384 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2385
40b01727 2386 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2387}
cd28ab6a 2388
d27ed387
SH		 2389/* If idle then force a fake soft NAPI poll once a second
2390 * to work around cases where sharing an edge triggered interrupt.
2391 */
eb35cf60
SH		 2392static inline void sky2_idle_start(struct sky2_hw *hw)
2393{
2394 if (idle_timeout > 0)
2395 mod_timer(&hw->idle_timer,
2396 jiffies + msecs_to_jiffies(idle_timeout));
2397}
2398
d27ed387
SH		 2399static void sky2_idle(unsigned long arg)
2400{
01bd7564
SH		 2401 struct sky2_hw *hw = (struct sky2_hw *) arg;
2402 struct net_device *dev = hw->dev[0];
d27ed387 2403
d27ed387
SH		 2404 if (__netif_rx_schedule_prep(dev))
2405 __netif_rx_schedule(dev);
01bd7564
SH		 2406
2407 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2408}
2409
40b01727
SH		 2410/* Hardware/software error handling */
2411static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2412{
40b01727
SH		 2413 if (net_ratelimit())
2414 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2415
1e5f1283
SH		 2416 if (status & Y2_IS_HW_ERR)
2417 sky2_hw_intr(hw);
d257924e 2418
1e5f1283
SH		 2419 if (status & Y2_IS_IRQ_MAC1)
2420 sky2_mac_intr(hw, 0);
cd28ab6a 2421
1e5f1283
SH		 2422 if (status & Y2_IS_IRQ_MAC2)
2423 sky2_mac_intr(hw, 1);
cd28ab6a 2424
1e5f1283 2425 if (status & Y2_IS_CHK_RX1)
40b01727 2426 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2427
1e5f1283 2428 if (status & Y2_IS_CHK_RX2)
40b01727 2429 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2430
1e5f1283 2431 if (status & Y2_IS_CHK_TXA1)
40b01727 2432 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2433
1e5f1283 2434 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2435 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2436}
2437
2438static int sky2_poll(struct net_device *dev0, int *budget)
2439{
2440 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2441 int work_limit = min(dev0->quota, *budget);
2442 int work_done = 0;
2443 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2444
2445 if (unlikely(status & Y2_IS_ERROR))
2446 sky2_err_intr(hw, status);
2447
2448 if (status & Y2_IS_IRQ_PHY1)
2449 sky2_phy_intr(hw, 0);
2450
2451 if (status & Y2_IS_IRQ_PHY2)
2452 sky2_phy_intr(hw, 1);
cd28ab6a 2453
1e5f1283 2454 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2455 if (work_done < work_limit) {
2456 netif_rx_complete(dev0);
86fba634 2457
50432cb5 2458 /* end of interrupt, re-enables also acts as I/O synchronization */
fe2a24df
SH		 2459 sky2_read32(hw, B0_Y2_SP_LISR);
2460 return 0;
2461 } else {
2462 *budget -= work_done;
2463 dev0->quota -= work_done;
1e5f1283 2464 return 1;
fe2a24df 2465 }
e07b1aa8
SH		 2466}
2467
7d12e780 2468static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2469{
2470 struct sky2_hw *hw = dev_id;
2471 struct net_device *dev0 = hw->dev[0];
2472 u32 status;
2473
2474 /* Reading this mask interrupts as side effect */
2475 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2476 if (status == 0 || status == ~0)
2477 return IRQ_NONE;
793b883e 2478
e07b1aa8
SH		 2479 prefetch(&hw->st_le[hw->st_idx]);
2480 if (likely(__netif_rx_schedule_prep(dev0)))
2481 __netif_rx_schedule(dev0);
793b883e 2482
cd28ab6a
SH		 2483 return IRQ_HANDLED;
2484}
2485
2486#ifdef CONFIG_NET_POLL_CONTROLLER
2487static void sky2_netpoll(struct net_device *dev)
2488{
2489 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2490 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2491
88d11360
SH		 2492 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2493 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2494}
2495#endif
2496
2497/* Chip internal frequency for clock calculations */
fb17358f 2498static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2499{
793b883e 2500 switch (hw->chip_id) {
cd28ab6a 2501 case CHIP_ID_YUKON_EC:
5a5b1ea0 2502 case CHIP_ID_YUKON_EC_U:
93745494 2503 case CHIP_ID_YUKON_EX:
fb17358f 2504 return 125; /* 125 Mhz */
cd28ab6a 2505 case CHIP_ID_YUKON_FE:
fb17358f 2506 return 100; /* 100 Mhz */
793b883e 2507 default: /* YUKON_XL */
fb17358f 2508 return 156; /* 156 Mhz */
cd28ab6a
SH		 2509 }
2510}
2511
fb17358f 2512static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2513{
fb17358f 2514 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2515}
2516
fb17358f 2517static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2518{
fb17358f 2519 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2520}
2521
fb17358f 2522
e3173832 2523static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2524{
b89165f2 2525 u8 t8;
cd28ab6a 2526
451af335
SH		 2527 /* Enable all clocks */
2528 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2529
cd28ab6a 2530 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2531
cd28ab6a
SH		 2532 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2533 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
b02a9258
SH		 2534 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2535 hw->chip_id);
cd28ab6a
SH		 2536 return -EOPNOTSUPP;
2537 }
2538
93745494
SH		 2539 if (hw->chip_id == CHIP_ID_YUKON_EX)
2540 dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n"
2541 "Please report success or failure to <netdev@vger.kernel.org>\n");
2542
290d4de5
SH		 2543 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2544
2545 /* This rev is really old, and requires untested workarounds */
2546 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
b02a9258
SH		 2547 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2548 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2549 hw->chip_id, hw->chip_rev);
290d4de5
SH		 2550 return -EOPNOTSUPP;
2551 }
2552
e3173832
SH		 2553 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2554 hw->ports = 1;
2555 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2556 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2557 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2558 ++hw->ports;
2559 }
2560
2561 return 0;
2562}
2563
2564static void sky2_reset(struct sky2_hw *hw)
2565{
2566 u16 status;
2567 int i;
2568
cd28ab6a 2569 /* disable ASF */
4f44d8ba
SH		 2570 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2571 status = sky2_read16(hw, HCU_CCSR);
2572 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2573 HCU_CCSR_UC_STATE_MSK);
2574 sky2_write16(hw, HCU_CCSR, status);
2575 } else
2576 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2577 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2578
2579 /* do a SW reset */
2580 sky2_write8(hw, B0_CTST, CS_RST_SET);
2581 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2582
2583 /* clear PCI errors, if any */
56a645cc 2584 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2585
cd28ab6a 2586 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2587 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2588
cd28ab6a
SH		 2589
2590 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2591
2592 /* clear any PEX errors */
7bd656d1
SH		 2593 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2594 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2595
cd28ab6a 2596
ae306cca 2597 sky2_power_on(hw);
cd28ab6a
SH		 2598
2599 for (i = 0; i < hw->ports; i++) {
2600 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2601 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2602 }
2603
2604 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2605
793b883e
SH		 2606 /* Clear I2C IRQ noise */
2607 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2608
2609 /* turn off hardware timer (unused) */
2610 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2611 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2612
cd28ab6a
SH		 2613 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2614
69634ee7
SH		 2615 /* Turn off descriptor polling */
2616 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2617
2618 /* Turn off receive timestamp */
2619 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2620 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2621
2622 /* enable the Tx Arbiters */
2623 for (i = 0; i < hw->ports; i++)
2624 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2625
2626 /* Initialize ram interface */
2627 for (i = 0; i < hw->ports; i++) {
793b883e 2628 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2629
2630 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2631 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2632 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2633 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2634 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2635 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2636 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2637 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2638 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2639 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2640 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2641 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2642 }
2643
7bd656d1 2644 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2645
cd28ab6a 2646 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2647 sky2_gmac_reset(hw, i);
cd28ab6a 2648
cd28ab6a
SH		 2649 memset(hw->st_le, 0, STATUS_LE_BYTES);
2650 hw->st_idx = 0;
2651
2652 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2653 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2654
2655 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2656 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2657
2658 /* Set the list last index */
793b883e 2659 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2660
290d4de5
SH		 2661 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2662 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2663
290d4de5
SH		 2664 /* set Status-FIFO ISR watermark */
2665 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2666 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2667 else
2668 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2669
290d4de5 2670 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2671 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2672 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2673
793b883e 2674 /* enable status unit */
cd28ab6a
SH		 2675 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2676
2677 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2678 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2679 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2680}
2681
81906791
SH		 2682static void sky2_restart(struct work_struct *work)
2683{
2684 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2685 struct net_device *dev;
2686 int i, err;
2687
2688 dev_dbg(&hw->pdev->dev, "restarting\n");
2689
2690 del_timer_sync(&hw->idle_timer);
2691
2692 rtnl_lock();
2693 sky2_write32(hw, B0_IMSK, 0);
2694 sky2_read32(hw, B0_IMSK);
2695
2696 netif_poll_disable(hw->dev[0]);
2697
2698 for (i = 0; i < hw->ports; i++) {
2699 dev = hw->dev[i];
2700 if (netif_running(dev))
2701 sky2_down(dev);
2702 }
2703
2704 sky2_reset(hw);
2705 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2706 netif_poll_enable(hw->dev[0]);
2707
2708 for (i = 0; i < hw->ports; i++) {
2709 dev = hw->dev[i];
2710 if (netif_running(dev)) {
2711 err = sky2_up(dev);
2712 if (err) {
2713 printk(KERN_INFO PFX "%s: could not restart %d\n",
2714 dev->name, err);
2715 dev_close(dev);
2716 }
2717 }
2718 }
2719
2720 sky2_idle_start(hw);
2721
2722 rtnl_unlock();
2723}
2724
e3173832
SH		 2725static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2726{
2727 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2728}
2729
2730static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2731{
2732 const struct sky2_port *sky2 = netdev_priv(dev);
2733
2734 wol->supported = sky2_wol_supported(sky2->hw);
2735 wol->wolopts = sky2->wol;
2736}
2737
2738static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2739{
2740 struct sky2_port *sky2 = netdev_priv(dev);
2741 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2742
e3173832
SH		 2743 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2744 return -EOPNOTSUPP;
2745
2746 sky2->wol = wol->wolopts;
2747
2748 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
2749 sky2_write32(hw, B0_CTST, sky2->wol
2750 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2751
2752 if (!netif_running(dev))
2753 sky2_wol_init(sky2);
cd28ab6a
SH		 2754 return 0;
2755}
2756
28bd181a 2757static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2758{
b89165f2
SH		 2759 if (sky2_is_copper(hw)) {
2760 u32 modes = SUPPORTED_10baseT_Half
2761 | SUPPORTED_10baseT_Full
2762 | SUPPORTED_100baseT_Half
2763 | SUPPORTED_100baseT_Full
2764 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2765
2766 if (hw->chip_id != CHIP_ID_YUKON_FE)
2767 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2768 | SUPPORTED_1000baseT_Full;
2769 return modes;
cd28ab6a 2770 } else
b89165f2
SH		 2771 return SUPPORTED_1000baseT_Half
2772 | SUPPORTED_1000baseT_Full
2773 | SUPPORTED_Autoneg
2774 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2775}
2776
793b883e 2777static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2778{
2779 struct sky2_port *sky2 = netdev_priv(dev);
2780 struct sky2_hw *hw = sky2->hw;
2781
2782 ecmd->transceiver = XCVR_INTERNAL;
2783 ecmd->supported = sky2_supported_modes(hw);
2784 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2785 if (sky2_is_copper(hw)) {
cd28ab6a 2786 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2787 | SUPPORTED_10baseT_Full
2788 | SUPPORTED_100baseT_Half
2789 | SUPPORTED_100baseT_Full
2790 | SUPPORTED_1000baseT_Half
2791 | SUPPORTED_1000baseT_Full
2792 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2793 ecmd->port = PORT_TP;
b89165f2
SH		 2794 ecmd->speed = sky2->speed;
2795 } else {
2796 ecmd->speed = SPEED_1000;
cd28ab6a 2797 ecmd->port = PORT_FIBRE;
b89165f2 2798 }
cd28ab6a
SH		 2799
2800 ecmd->advertising = sky2->advertising;
2801 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2802 ecmd->duplex = sky2->duplex;
2803 return 0;
2804}
2805
2806static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2807{
2808 struct sky2_port *sky2 = netdev_priv(dev);
2809 const struct sky2_hw *hw = sky2->hw;
2810 u32 supported = sky2_supported_modes(hw);
2811
2812 if (ecmd->autoneg == AUTONEG_ENABLE) {
2813 ecmd->advertising = supported;
2814 sky2->duplex = -1;
2815 sky2->speed = -1;
2816 } else {
2817 u32 setting;
2818
793b883e 2819 switch (ecmd->speed) {
cd28ab6a
SH		 2820 case SPEED_1000:
2821 if (ecmd->duplex == DUPLEX_FULL)
2822 setting = SUPPORTED_1000baseT_Full;
2823 else if (ecmd->duplex == DUPLEX_HALF)
2824 setting = SUPPORTED_1000baseT_Half;
2825 else
2826 return -EINVAL;
2827 break;
2828 case SPEED_100:
2829 if (ecmd->duplex == DUPLEX_FULL)
2830 setting = SUPPORTED_100baseT_Full;
2831 else if (ecmd->duplex == DUPLEX_HALF)
2832 setting = SUPPORTED_100baseT_Half;
2833 else
2834 return -EINVAL;
2835 break;
2836
2837 case SPEED_10:
2838 if (ecmd->duplex == DUPLEX_FULL)
2839 setting = SUPPORTED_10baseT_Full;
2840 else if (ecmd->duplex == DUPLEX_HALF)
2841 setting = SUPPORTED_10baseT_Half;
2842 else
2843 return -EINVAL;
2844 break;
2845 default:
2846 return -EINVAL;
2847 }
2848
2849 if ((setting & supported) == 0)
2850 return -EINVAL;
2851
2852 sky2->speed = ecmd->speed;
2853 sky2->duplex = ecmd->duplex;
2854 }
2855
2856 sky2->autoneg = ecmd->autoneg;
2857 sky2->advertising = ecmd->advertising;
2858
1b537565
SH		 2859 if (netif_running(dev))
2860 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2861
2862 return 0;
2863}
2864
2865static void sky2_get_drvinfo(struct net_device *dev,
2866 struct ethtool_drvinfo *info)
2867{
2868 struct sky2_port *sky2 = netdev_priv(dev);
2869
2870 strcpy(info->driver, DRV_NAME);
2871 strcpy(info->version, DRV_VERSION);
2872 strcpy(info->fw_version, "N/A");
2873 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2874}
2875
2876static const struct sky2_stat {
793b883e
SH		 2877 char name[ETH_GSTRING_LEN];
2878 u16 offset;
cd28ab6a
SH		 2879} sky2_stats[] = {
2880 { "tx_bytes", GM_TXO_OK_HI },
2881 { "rx_bytes", GM_RXO_OK_HI },
2882 { "tx_broadcast", GM_TXF_BC_OK },
2883 { "rx_broadcast", GM_RXF_BC_OK },
2884 { "tx_multicast", GM_TXF_MC_OK },
2885 { "rx_multicast", GM_RXF_MC_OK },
2886 { "tx_unicast", GM_TXF_UC_OK },
2887 { "rx_unicast", GM_RXF_UC_OK },
2888 { "tx_mac_pause", GM_TXF_MPAUSE },
2889 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2890 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2891 { "late_collision",GM_TXF_LAT_COL },
2892 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2893 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2894 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2895
d2604540 2896 { "rx_short", GM_RXF_SHT },
cd28ab6a 2897 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2898 { "rx_64_byte_packets", GM_RXF_64B },
2899 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2900 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2901 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2902 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2903 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2904 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2905 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2906 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2907 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2908 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2909
2910 { "tx_64_byte_packets", GM_TXF_64B },
2911 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2912 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2913 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2914 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2915 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2916 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2917 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2918};
2919
cd28ab6a
SH		 2920static u32 sky2_get_rx_csum(struct net_device *dev)
2921{
2922 struct sky2_port *sky2 = netdev_priv(dev);
2923
2924 return sky2->rx_csum;
2925}
2926
2927static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2928{
2929 struct sky2_port *sky2 = netdev_priv(dev);
2930
2931 sky2->rx_csum = data;
793b883e 2932
cd28ab6a
SH		 2933 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2934 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2935
2936 return 0;
2937}
2938
2939static u32 sky2_get_msglevel(struct net_device *netdev)
2940{
2941 struct sky2_port *sky2 = netdev_priv(netdev);
2942 return sky2->msg_enable;
2943}
2944
9a7ae0a9
SH		 2945static int sky2_nway_reset(struct net_device *dev)
2946{
2947 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2948
16ad91e1 2949 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2950 return -EINVAL;
2951
1b537565 2952 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2953
2954 return 0;
2955}
2956
793b883e 2957static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2958{
2959 struct sky2_hw *hw = sky2->hw;
2960 unsigned port = sky2->port;
2961 int i;
2962
2963 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2964 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2965 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2966 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2967
793b883e 2968 for (i = 2; i < count; i++)
cd28ab6a
SH		 2969 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2970}
2971
cd28ab6a
SH		 2972static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2973{
2974 struct sky2_port *sky2 = netdev_priv(netdev);
2975 sky2->msg_enable = value;
2976}
2977
2978static int sky2_get_stats_count(struct net_device *dev)
2979{
2980 return ARRAY_SIZE(sky2_stats);
2981}
2982
2983static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2984 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2985{
2986 struct sky2_port *sky2 = netdev_priv(dev);
2987
793b883e 2988 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2989}
2990
793b883e 2991static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2992{
2993 int i;
2994
2995 switch (stringset) {
2996 case ETH_SS_STATS:
2997 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2998 memcpy(data + i * ETH_GSTRING_LEN,
2999 sky2_stats[i].name, ETH_GSTRING_LEN);
3000 break;
3001 }
3002}
3003
cd28ab6a
SH		 3004static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3005{
3006 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3007 return &sky2->net_stats;
3008}
3009
3010static int sky2_set_mac_address(struct net_device *dev, void *p)
3011{
3012 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3013 struct sky2_hw *hw = sky2->hw;
3014 unsigned port = sky2->port;
3015 const struct sockaddr *addr = p;
cd28ab6a
SH		 3016
3017 if (!is_valid_ether_addr(addr->sa_data))
3018 return -EADDRNOTAVAIL;
3019
cd28ab6a 3020 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3021 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3022 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3023 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3024 dev->dev_addr, ETH_ALEN);
1b537565 3025
a8ab1ec0
SH		 3026 /* virtual address for data */
3027 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3028
3029 /* physical address: used for pause frames */
3030 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3031
3032 return 0;
cd28ab6a
SH		 3033}
3034
a052b52f
SH		 3035static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3036{
3037 u32 bit;
3038
3039 bit = ether_crc(ETH_ALEN, addr) & 63;
3040 filter[bit >> 3] |= 1 << (bit & 7);
3041}
3042
cd28ab6a
SH		 3043static void sky2_set_multicast(struct net_device *dev)
3044{
3045 struct sky2_port *sky2 = netdev_priv(dev);
3046 struct sky2_hw *hw = sky2->hw;
3047 unsigned port = sky2->port;
3048 struct dev_mc_list *list = dev->mc_list;
3049 u16 reg;
3050 u8 filter[8];
a052b52f
SH		 3051 int rx_pause;
3052 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3053
a052b52f 3054 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3055 memset(filter, 0, sizeof(filter));
3056
3057 reg = gma_read16(hw, port, GM_RX_CTRL);
3058 reg |= GM_RXCR_UCF_ENA;
3059
d571b694 3060 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3061 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3062 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3063 memset(filter, 0xff, sizeof(filter));
a052b52f 3064 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3065 reg &= ~GM_RXCR_MCF_ENA;
3066 else {
3067 int i;
3068 reg |= GM_RXCR_MCF_ENA;
3069
a052b52f
SH		 3070 if (rx_pause)
3071 sky2_add_filter(filter, pause_mc_addr);
3072
3073 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3074 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3075 }
3076
cd28ab6a 3077 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3078 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3079 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3080 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3081 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3082 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3083 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3084 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3085
3086 gma_write16(hw, port, GM_RX_CTRL, reg);
3087}
3088
3089/* Can have one global because blinking is controlled by
3090 * ethtool and that is always under RTNL mutex
3091 */
91c86df5 3092static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3093{
793b883e
SH		 3094 u16 pg;
3095
793b883e
SH		 3096 switch (hw->chip_id) {
3097 case CHIP_ID_YUKON_XL:
3098 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3099 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3100 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3101 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3102 PHY_M_LEDC_INIT_CTRL(7) |
3103 PHY_M_LEDC_STA1_CTRL(7) |
3104 PHY_M_LEDC_STA0_CTRL(7))
3105 : 0);
3106
3107 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3108 break;
3109
3110 default:
3111 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3112 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3113 on ? PHY_M_LED_ALL : 0);
793b883e 3114 }
cd28ab6a
SH		 3115}
3116
3117/* blink LED's for finding board */
3118static int sky2_phys_id(struct net_device *dev, u32 data)
3119{
3120 struct sky2_port *sky2 = netdev_priv(dev);
3121 struct sky2_hw *hw = sky2->hw;
3122 unsigned port = sky2->port;
793b883e 3123 u16 ledctrl, ledover = 0;
cd28ab6a 3124 long ms;
91c86df5 3125 int interrupted;
cd28ab6a
SH		 3126 int onoff = 1;
3127
793b883e 3128 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3129 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3130 else
3131 ms = data * 1000;
3132
3133 /* save initial values */
e07b1aa8 3134 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3135 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3136 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3137 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3138 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3139 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3140 } else {
3141 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3142 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3143 }
cd28ab6a 3144
91c86df5
SH		 3145 interrupted = 0;
3146 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3147 sky2_led(hw, port, onoff);
3148 onoff = !onoff;
3149
e07b1aa8 3150 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3151 interrupted = msleep_interruptible(250);
e07b1aa8 3152 spin_lock_bh(&sky2->phy_lock);
91c86df5 3153
cd28ab6a
SH		 3154 ms -= 250;
3155 }
3156
3157 /* resume regularly scheduled programming */
793b883e
SH		 3158 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3159 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3160 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3161 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3162 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3163 } else {
3164 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3165 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3166 }
e07b1aa8 3167 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3168
3169 return 0;
3170}
3171
3172static void sky2_get_pauseparam(struct net_device *dev,
3173 struct ethtool_pauseparam *ecmd)
3174{
3175 struct sky2_port *sky2 = netdev_priv(dev);
3176
16ad91e1
SH		 3177 switch (sky2->flow_mode) {
3178 case FC_NONE:
3179 ecmd->tx_pause = ecmd->rx_pause = 0;
3180 break;
3181 case FC_TX:
3182 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3183 break;
3184 case FC_RX:
3185 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3186 break;
3187 case FC_BOTH:
3188 ecmd->tx_pause = ecmd->rx_pause = 1;
3189 }
3190
cd28ab6a
SH		 3191 ecmd->autoneg = sky2->autoneg;
3192}
3193
3194static int sky2_set_pauseparam(struct net_device *dev,
3195 struct ethtool_pauseparam *ecmd)
3196{
3197 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3198
3199 sky2->autoneg = ecmd->autoneg;
16ad91e1 3200 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3201
16ad91e1
SH		 3202 if (netif_running(dev))
3203 sky2_phy_reinit(sky2);
cd28ab6a 3204
2eaba1a2 3205 return 0;
cd28ab6a
SH		 3206}
3207
fb17358f
SH		 3208static int sky2_get_coalesce(struct net_device *dev,
3209 struct ethtool_coalesce *ecmd)
3210{
3211 struct sky2_port *sky2 = netdev_priv(dev);
3212 struct sky2_hw *hw = sky2->hw;
3213
3214 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3215 ecmd->tx_coalesce_usecs = 0;
3216 else {
3217 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3218 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3219 }
3220 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3221
3222 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3223 ecmd->rx_coalesce_usecs = 0;
3224 else {
3225 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3226 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3227 }
3228 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3229
3230 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3231 ecmd->rx_coalesce_usecs_irq = 0;
3232 else {
3233 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3234 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3235 }
3236
3237 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3238
3239 return 0;
3240}
3241
3242/* Note: this affect both ports */
3243static int sky2_set_coalesce(struct net_device *dev,
3244 struct ethtool_coalesce *ecmd)
3245{
3246 struct sky2_port *sky2 = netdev_priv(dev);
3247 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3248 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3249
77b3d6a2
SH		 3250 if (ecmd->tx_coalesce_usecs > tmax ||
3251 ecmd->rx_coalesce_usecs > tmax ||
3252 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3253 return -EINVAL;
3254
ff81fbbe 3255 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3256 return -EINVAL;
ff81fbbe 3257 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3258 return -EINVAL;
ff81fbbe 3259 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3260 return -EINVAL;
3261
3262 if (ecmd->tx_coalesce_usecs == 0)
3263 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3264 else {
3265 sky2_write32(hw, STAT_TX_TIMER_INI,
3266 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3267 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3268 }
3269 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3270
3271 if (ecmd->rx_coalesce_usecs == 0)
3272 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3273 else {
3274 sky2_write32(hw, STAT_LEV_TIMER_INI,
3275 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3276 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3277 }
3278 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3279
3280 if (ecmd->rx_coalesce_usecs_irq == 0)
3281 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3282 else {
d28d4870 3283 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3284 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3285 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3286 }
3287 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3288 return 0;
3289}
3290
793b883e
SH		 3291static void sky2_get_ringparam(struct net_device *dev,
3292 struct ethtool_ringparam *ering)
3293{
3294 struct sky2_port *sky2 = netdev_priv(dev);
3295
3296 ering->rx_max_pending = RX_MAX_PENDING;
3297 ering->rx_mini_max_pending = 0;
3298 ering->rx_jumbo_max_pending = 0;
3299 ering->tx_max_pending = TX_RING_SIZE - 1;
3300
3301 ering->rx_pending = sky2->rx_pending;
3302 ering->rx_mini_pending = 0;
3303 ering->rx_jumbo_pending = 0;
3304 ering->tx_pending = sky2->tx_pending;
3305}
3306
3307static int sky2_set_ringparam(struct net_device *dev,
3308 struct ethtool_ringparam *ering)
3309{
3310 struct sky2_port *sky2 = netdev_priv(dev);
3311 int err = 0;
3312
3313 if (ering->rx_pending > RX_MAX_PENDING ||
3314 ering->rx_pending < 8 ||
3315 ering->tx_pending < MAX_SKB_TX_LE ||
3316 ering->tx_pending > TX_RING_SIZE - 1)
3317 return -EINVAL;
3318
3319 if (netif_running(dev))
3320 sky2_down(dev);
3321
3322 sky2->rx_pending = ering->rx_pending;
3323 sky2->tx_pending = ering->tx_pending;
3324
1b537565 3325 if (netif_running(dev)) {
793b883e 3326 err = sky2_up(dev);
1b537565
SH		 3327 if (err)
3328 dev_close(dev);
6ed995bb
SH		 3329 else
3330 sky2_set_multicast(dev);
1b537565 3331 }
793b883e
SH		 3332
3333 return err;
3334}
3335
793b883e
SH		 3336static int sky2_get_regs_len(struct net_device *dev)
3337{
6e4cbb34 3338 return 0x4000;
793b883e
SH		 3339}
3340
3341/*
3342 * Returns copy of control register region
3ead5db7 3343 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3344 */
3345static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3346 void *p)
3347{
3348 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3349 const void __iomem *io = sky2->hw->regs;
793b883e
SH		 3350
3351 regs->version = 1;
6e4cbb34 3352 memset(p, 0, regs->len);
793b883e 3353
6e4cbb34
SH		 3354 memcpy_fromio(p, io, B3_RAM_ADDR);
3355
3ead5db7
SH		 3356 /* skip diagnostic ram region */
3357 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 0x2000 - B3_RI_WTO_R1);
3358
3359 /* copy GMAC registers */
3360 memcpy_fromio(p + BASE_GMAC_1, io + BASE_GMAC_1, 0x1000);
3361 if (sky2->hw->ports > 1)
3362 memcpy_fromio(p + BASE_GMAC_2, io + BASE_GMAC_2, 0x1000);
3363
793b883e 3364}
cd28ab6a 3365
b628ed98
SH		 3366/* In order to do Jumbo packets on these chips, need to turn off the
3367 * transmit store/forward. Therefore checksum offload won't work.
3368 */
3369static int no_tx_offload(struct net_device *dev)
3370{
3371 const struct sky2_port *sky2 = netdev_priv(dev);
3372 const struct sky2_hw *hw = sky2->hw;
3373
3374 return dev->mtu > ETH_DATA_LEN &&
3375 (hw->chip_id == CHIP_ID_YUKON_EX
3376 || hw->chip_id == CHIP_ID_YUKON_EC_U);
3377}
3378
3379static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3380{
3381 if (data && no_tx_offload(dev))
3382 return -EINVAL;
3383
3384 return ethtool_op_set_tx_csum(dev, data);
3385}
3386
3387
3388static int sky2_set_tso(struct net_device *dev, u32 data)
3389{
3390 if (data && no_tx_offload(dev))
3391 return -EINVAL;
3392
3393 return ethtool_op_set_tso(dev, data);
3394}
3395
7282d491 3396static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3397 .get_settings = sky2_get_settings,
3398 .set_settings = sky2_set_settings,
e3173832
SH		 3399 .get_drvinfo = sky2_get_drvinfo,
3400 .get_wol = sky2_get_wol,
3401 .set_wol = sky2_set_wol,
793b883e
SH		 3402 .get_msglevel = sky2_get_msglevel,
3403 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3404 .nway_reset = sky2_nway_reset,
793b883e
SH		 3405 .get_regs_len = sky2_get_regs_len,
3406 .get_regs = sky2_get_regs,
3407 .get_link = ethtool_op_get_link,
3408 .get_sg = ethtool_op_get_sg,
3409 .set_sg = ethtool_op_set_sg,
3410 .get_tx_csum = ethtool_op_get_tx_csum,
b628ed98 3411 .set_tx_csum = sky2_set_tx_csum,
793b883e 3412 .get_tso = ethtool_op_get_tso,
b628ed98 3413 .set_tso = sky2_set_tso,
793b883e
SH		 3414 .get_rx_csum = sky2_get_rx_csum,
3415 .set_rx_csum = sky2_set_rx_csum,
3416 .get_strings = sky2_get_strings,
fb17358f
SH		 3417 .get_coalesce = sky2_get_coalesce,
3418 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3419 .get_ringparam = sky2_get_ringparam,
3420 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3421 .get_pauseparam = sky2_get_pauseparam,
3422 .set_pauseparam = sky2_set_pauseparam,
793b883e 3423 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3424 .get_stats_count = sky2_get_stats_count,
3425 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3426 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3427};
3428
3429/* Initialize network device */
3430static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3431 unsigned port,
3432 int highmem, int wol)
cd28ab6a
SH		 3433{
3434 struct sky2_port *sky2;
3435 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3436
3437 if (!dev) {
b02a9258 3438 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3439 return NULL;
3440 }
3441
3442 SET_MODULE_OWNER(dev);
3443 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3444 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3445 dev->open = sky2_up;
3446 dev->stop = sky2_down;
ef743d33 3447 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3448 dev->hard_start_xmit = sky2_xmit_frame;
3449 dev->get_stats = sky2_get_stats;
3450 dev->set_multicast_list = sky2_set_multicast;
3451 dev->set_mac_address = sky2_set_mac_address;
3452 dev->change_mtu = sky2_change_mtu;
3453 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3454 dev->tx_timeout = sky2_tx_timeout;
3455 dev->watchdog_timeo = TX_WATCHDOG;
3456 if (port == 0)
3457 dev->poll = sky2_poll;
3458 dev->weight = NAPI_WEIGHT;
3459#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3460 /* Network console (only works on port 0)
3461 * because netpoll makes assumptions about NAPI
3462 */
3463 if (port == 0)
3464 dev->poll_controller = sky2_netpoll;
cd28ab6a 3465#endif
cd28ab6a
SH		 3466
3467 sky2 = netdev_priv(dev);
3468 sky2->netdev = dev;
3469 sky2->hw = hw;
3470 sky2->msg_enable = netif_msg_init(debug, default_msg);
3471
cd28ab6a
SH		 3472 /* Auto speed and flow control */
3473 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3474 sky2->flow_mode = FC_BOTH;
3475
cd28ab6a
SH		 3476 sky2->duplex = -1;
3477 sky2->speed = -1;
3478 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3479 sky2->rx_csum = 1;
e3173832 3480 sky2->wol = wol;
75d070c5 3481
e07b1aa8 3482 spin_lock_init(&sky2->phy_lock);
793b883e 3483 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3484 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3485
3486 hw->dev[port] = dev;
3487
3488 sky2->port = port;
3489
4a50a876 3490 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3491 if (highmem)
3492 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3493
d1f13708 3494#ifdef SKY2_VLAN_TAG_USED
3495 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3496 dev->vlan_rx_register = sky2_vlan_rx_register;
d1f13708 3497#endif
3498
cd28ab6a 3499 /* read the mac address */
793b883e 3500 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3501 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3502
3503 /* device is off until link detection */
3504 netif_carrier_off(dev);
3505 netif_stop_queue(dev);
3506
3507 return dev;
3508}
3509
28bd181a 3510static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3511{
3512 const struct sky2_port *sky2 = netdev_priv(dev);
3513
3514 if (netif_msg_probe(sky2))
3515 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3516 dev->name,
3517 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3518 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3519}
3520
fb2690a9 3521/* Handle software interrupt used during MSI test */
7d12e780 3522static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3523{
3524 struct sky2_hw *hw = dev_id;
3525 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3526
3527 if (status == 0)
3528 return IRQ_NONE;
3529
3530 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3531 hw->msi = 1;
fb2690a9
SH		 3532 wake_up(&hw->msi_wait);
3533 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3534 }
3535 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3536
3537 return IRQ_HANDLED;
3538}
3539
3540/* Test interrupt path by forcing a a software IRQ */
3541static int __devinit sky2_test_msi(struct sky2_hw *hw)
3542{
3543 struct pci_dev *pdev = hw->pdev;
3544 int err;
3545
bb507fe1 3546 init_waitqueue_head (&hw->msi_wait);
3547
fb2690a9
SH		 3548 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3549
b0a20ded 3550 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 3551 if (err) {
b02a9258 3552 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 3553 return err;
3554 }
3555
fb2690a9 3556 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3557 sky2_read8(hw, B0_CTST);
fb2690a9 3558
b0a20ded 3559 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3560
b0a20ded 3561 if (!hw->msi) {
fb2690a9 3562 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 3563 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3564 "switching to INTx mode.\n");
fb2690a9
SH		 3565
3566 err = -EOPNOTSUPP;
3567 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3568 }
3569
3570 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3571 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3572
3573 free_irq(pdev->irq, hw);
3574
3575 return err;
3576}
3577
e3173832
SH		 3578static int __devinit pci_wake_enabled(struct pci_dev *dev)
3579{
3580 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3581 u16 value;
3582
3583 if (!pm)
3584 return 0;
3585 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3586 return 0;
3587 return value & PCI_PM_CTRL_PME_ENABLE;
3588}
3589
cd28ab6a
SH		 3590static int __devinit sky2_probe(struct pci_dev *pdev,
3591 const struct pci_device_id *ent)
3592{
7f60c64b 3593 struct net_device *dev;
cd28ab6a 3594 struct sky2_hw *hw;
e3173832 3595 int err, using_dac = 0, wol_default;
cd28ab6a 3596
793b883e
SH		 3597 err = pci_enable_device(pdev);
3598 if (err) {
b02a9258 3599 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 3600 goto err_out;
3601 }
3602
793b883e
SH		 3603 err = pci_request_regions(pdev, DRV_NAME);
3604 if (err) {
b02a9258 3605 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 3606 goto err_out_disable;
cd28ab6a
SH		 3607 }
3608
3609 pci_set_master(pdev);
3610
d1f3d4dd
SH		 3611 if (sizeof(dma_addr_t) > sizeof(u32) &&
3612 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3613 using_dac = 1;
3614 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3615 if (err < 0) {
b02a9258
SH		 3616 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3617 "for consistent allocations\n");
d1f3d4dd
SH		 3618 goto err_out_free_regions;
3619 }
d1f3d4dd 3620 } else {
cd28ab6a
SH		 3621 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3622 if (err) {
b02a9258 3623 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 3624 goto err_out_free_regions;
3625 }
3626 }
d1f3d4dd 3627
e3173832
SH		 3628 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3629
cd28ab6a 3630 err = -ENOMEM;
6aad85d6 3631 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 3632 if (!hw) {
b02a9258 3633 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 3634 goto err_out_free_regions;
3635 }
3636
cd28ab6a 3637 hw->pdev = pdev;
cd28ab6a
SH		 3638
3639 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3640 if (!hw->regs) {
b02a9258 3641 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 3642 goto err_out_free_hw;
3643 }
3644
56a645cc 3645#ifdef __BIG_ENDIAN
f65b138c
SH		 3646 /* The sk98lin vendor driver uses hardware byte swapping but
3647 * this driver uses software swapping.
3648 */
56a645cc
SH		 3649 {
3650 u32 reg;
56a645cc 3651 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3652 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3653 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3654 }
3655#endif
3656
08c06d8a
SH		 3657 /* ring for status responses */
3658 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3659 &hw->st_dma);
3660 if (!hw->st_le)
3661 goto err_out_iounmap;
3662
e3173832 3663 err = sky2_init(hw);
cd28ab6a 3664 if (err)
793b883e 3665 goto err_out_iounmap;
cd28ab6a 3666
b02a9258 3667 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 3668 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3669 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3670 hw->chip_id, hw->chip_rev);
cd28ab6a 3671
e3173832
SH		 3672 sky2_reset(hw);
3673
3674 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 3675 if (!dev) {
3676 err = -ENOMEM;
cd28ab6a 3677 goto err_out_free_pci;
7f60c64b 3678 }
cd28ab6a 3679
9fa1b1f3
SH		 3680 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3681 err = sky2_test_msi(hw);
3682 if (err == -EOPNOTSUPP)
3683 pci_disable_msi(pdev);
3684 else if (err)
3685 goto err_out_free_netdev;
3686 }
3687
793b883e
SH		 3688 err = register_netdev(dev);
3689 if (err) {
b02a9258 3690 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 3691 goto err_out_free_netdev;
3692 }
3693
b0a20ded
SH		 3694 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3695 dev->name, hw);
9fa1b1f3 3696 if (err) {
b02a9258 3697 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 3698 goto err_out_unregister;
3699 }
3700 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3701
cd28ab6a
SH		 3702 sky2_show_addr(dev);
3703
7f60c64b 3704 if (hw->ports > 1) {
3705 struct net_device *dev1;
3706
e3173832 3707 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 3708 if (!dev1)
3709 dev_warn(&pdev->dev, "allocation for second device failed\n");
3710 else if ((err = register_netdev(dev1))) {
3711 dev_warn(&pdev->dev,
3712 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 3713 hw->dev[1] = NULL;
3714 free_netdev(dev1);
b02a9258
SH		 3715 } else
3716 sky2_show_addr(dev1);
cd28ab6a
SH		 3717 }
3718
01bd7564 3719 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
81906791
SH		 3720 INIT_WORK(&hw->restart_work, sky2_restart);
3721
eb35cf60 3722 sky2_idle_start(hw);
d27ed387 3723
793b883e
SH		 3724 pci_set_drvdata(pdev, hw);
3725
cd28ab6a
SH		 3726 return 0;
3727
793b883e 3728err_out_unregister:
b0a20ded
SH		 3729 if (hw->msi)
3730 pci_disable_msi(pdev);
793b883e 3731 unregister_netdev(dev);
cd28ab6a
SH		 3732err_out_free_netdev:
3733 free_netdev(dev);
cd28ab6a 3734err_out_free_pci:
793b883e 3735 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3736 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3737err_out_iounmap:
3738 iounmap(hw->regs);
3739err_out_free_hw:
3740 kfree(hw);
3741err_out_free_regions:
3742 pci_release_regions(pdev);
44a1d2e5 3743err_out_disable:
cd28ab6a 3744 pci_disable_device(pdev);
cd28ab6a 3745err_out:
549a68c3 3746 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 3747 return err;
3748}
3749
3750static void __devexit sky2_remove(struct pci_dev *pdev)
3751{
793b883e 3752 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3753 struct net_device *dev0, *dev1;
3754
793b883e 3755 if (!hw)
cd28ab6a
SH		 3756 return;
3757
d27ed387
SH		 3758 del_timer_sync(&hw->idle_timer);
3759
81906791
SH		 3760 flush_scheduled_work();
3761
d27ed387 3762 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3763 synchronize_irq(hw->pdev->irq);
3764
cd28ab6a 3765 dev0 = hw->dev[0];
793b883e
SH		 3766 dev1 = hw->dev[1];
3767 if (dev1)
3768 unregister_netdev(dev1);
cd28ab6a
SH		 3769 unregister_netdev(dev0);
3770
ae306cca
SH		 3771 sky2_power_aux(hw);
3772
cd28ab6a 3773 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3774 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3775 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3776
3777 free_irq(pdev->irq, hw);
b0a20ded
SH		 3778 if (hw->msi)
3779 pci_disable_msi(pdev);
793b883e 3780 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3781 pci_release_regions(pdev);
3782 pci_disable_device(pdev);
793b883e 3783
cd28ab6a
SH		 3784 if (dev1)
3785 free_netdev(dev1);
3786 free_netdev(dev0);
3787 iounmap(hw->regs);
3788 kfree(hw);
5afa0a9c 3789
cd28ab6a
SH		 3790 pci_set_drvdata(pdev, NULL);
3791}
3792
3793#ifdef CONFIG_PM
3794static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3795{
793b883e 3796 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 3797 int i, wol = 0;
cd28ab6a 3798
549a68c3
SH		 3799 if (!hw)
3800 return 0;
3801
eb35cf60 3802 del_timer_sync(&hw->idle_timer);
6a5706b9 3803 netif_poll_disable(hw->dev[0]);
eb35cf60 3804
f05267e7 3805 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3806 struct net_device *dev = hw->dev[i];
e3173832 3807 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3808
e3173832 3809 if (netif_running(dev))
5afa0a9c 3810 sky2_down(dev);
e3173832
SH		 3811
3812 if (sky2->wol)
3813 sky2_wol_init(sky2);
3814
3815 wol |= sky2->wol;
cd28ab6a
SH		 3816 }
3817
8ab8fca2 3818 sky2_write32(hw, B0_IMSK, 0);
ae306cca 3819 sky2_power_aux(hw);
e3173832 3820
d374c1c1 3821 pci_save_state(pdev);
e3173832 3822 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 3823 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3824
2ccc99b7 3825 return 0;
cd28ab6a
SH		 3826}
3827
3828static int sky2_resume(struct pci_dev *pdev)
3829{
793b883e 3830 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3831 int i, err;
cd28ab6a 3832
549a68c3
SH		 3833 if (!hw)
3834 return 0;
3835
ae306cca
SH		 3836 err = pci_set_power_state(pdev, PCI_D0);
3837 if (err)
3838 goto out;
3839
3840 err = pci_restore_state(pdev);
3841 if (err)
3842 goto out;
3843
cd28ab6a 3844 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 3845
3846 /* Re-enable all clocks */
3847 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
3848 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3849
e3173832 3850 sky2_reset(hw);
cd28ab6a 3851
8ab8fca2
SH		 3852 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3853
f05267e7 3854 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3855 struct net_device *dev = hw->dev[i];
6a5706b9 3856 if (netif_running(dev)) {
08c06d8a
SH		 3857 err = sky2_up(dev);
3858 if (err) {
3859 printk(KERN_ERR PFX "%s: could not up: %d\n",
3860 dev->name, err);
3861 dev_close(dev);
eb35cf60 3862 goto out;
5afa0a9c 3863 }
cd28ab6a
SH		 3864 }
3865 }
eb35cf60 3866
6a5706b9 3867 netif_poll_enable(hw->dev[0]);
eb35cf60 3868 sky2_idle_start(hw);
ae306cca 3869 return 0;
08c06d8a 3870out:
b02a9258 3871 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 3872 pci_disable_device(pdev);
08c06d8a 3873 return err;
cd28ab6a
SH		 3874}
3875#endif
3876
e3173832
SH		 3877static void sky2_shutdown(struct pci_dev *pdev)
3878{
3879 struct sky2_hw *hw = pci_get_drvdata(pdev);
3880 int i, wol = 0;
3881
549a68c3
SH		 3882 if (!hw)
3883 return;
3884
e3173832
SH		 3885 del_timer_sync(&hw->idle_timer);
3886 netif_poll_disable(hw->dev[0]);
3887
3888 for (i = 0; i < hw->ports; i++) {
3889 struct net_device *dev = hw->dev[i];
3890 struct sky2_port *sky2 = netdev_priv(dev);
3891
3892 if (sky2->wol) {
3893 wol = 1;
3894 sky2_wol_init(sky2);
3895 }
3896 }
3897
3898 if (wol)
3899 sky2_power_aux(hw);
3900
3901 pci_enable_wake(pdev, PCI_D3hot, wol);
3902 pci_enable_wake(pdev, PCI_D3cold, wol);
3903
3904 pci_disable_device(pdev);
3905 pci_set_power_state(pdev, PCI_D3hot);
3906
3907}
3908
cd28ab6a 3909static struct pci_driver sky2_driver = {
793b883e
SH		 3910 .name = DRV_NAME,
3911 .id_table = sky2_id_table,
3912 .probe = sky2_probe,
3913 .remove = __devexit_p(sky2_remove),
cd28ab6a 3914#ifdef CONFIG_PM
793b883e
SH		 3915 .suspend = sky2_suspend,
3916 .resume = sky2_resume,
cd28ab6a 3917#endif
e3173832 3918 .shutdown = sky2_shutdown,
cd28ab6a
SH		 3919};
3920
3921static int __init sky2_init_module(void)
3922{
50241c4c 3923 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3924}
3925
3926static void __exit sky2_cleanup_module(void)
3927{
3928 pci_unregister_driver(&sky2_driver);
3929}
3930
3931module_init(sky2_init_module);
3932module_exit(sky2_cleanup_module);
3933
3934MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 3935MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 3936MODULE_LICENSE("GPL");
5f4f9dc1 3937MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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