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DM9000: fix interface hang under load
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
3cf26753 42#include <linux/debugfs.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
0640b8dc 54#define DRV_VERSION "1.16"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 67#define RX_SKB_ALIGN 8
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
c59697e0 102static int idle_timeout = 100;
01bd7564 103module_param(idle_timeout, int, 0);
e561a83b 104MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 105
cd28ab6a 106static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
108 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 110 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 111 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 112 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
cd28ab6a
SH		 137 { 0 }
138};
793b883e 139
cd28ab6a
SH		 140MODULE_DEVICE_TABLE(pci, sky2_id_table);
141
142/* Avoid conditionals by using array */
143static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
144static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 145static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 146
92f965e8
SH		 147/* This driver supports yukon2 chipset only */
148static const char *yukon2_name[] = {
149 "XL", /* 0xb3 */
150 "EC Ultra", /* 0xb4 */
93745494 151 "Extreme", /* 0xb5 */
92f965e8
SH		 152 "EC", /* 0xb6 */
153 "FE", /* 0xb7 */
793b883e
SH		 154};
155
793b883e 156/* Access to external PHY */
ef743d33 157static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 158{
159 int i;
160
161 gma_write16(hw, port, GM_SMI_DATA, val);
162 gma_write16(hw, port, GM_SMI_CTRL,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
164
165 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 166 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 167 return 0;
793b883e 168 udelay(1);
cd28ab6a 169 }
ef743d33 170
793b883e 171 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 172 return -ETIMEDOUT;
cd28ab6a
SH		 173}
174
ef743d33 175static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 176{
177 int i;
178
793b883e 179 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 180 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
181
182 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33 183 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
184 *val = gma_read16(hw, port, GM_SMI_DATA);
185 return 0;
186 }
187
793b883e 188 udelay(1);
cd28ab6a
SH		 189 }
190
ef743d33 191 return -ETIMEDOUT;
192}
193
194static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
195{
196 u16 v;
197
198 if (__gm_phy_read(hw, port, reg, &v) != 0)
199 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
200 return v;
cd28ab6a
SH		 201}
202
5afa0a9c 203
ae306cca
SH		 204static void sky2_power_on(struct sky2_hw *hw)
205{
206 /* switch power to VCC (WA for VAUX problem) */
207 sky2_write8(hw, B0_POWER_CTRL,
208 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 209
ae306cca
SH		 210 /* disable Core Clock Division, */
211 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 212
ae306cca
SH		 213 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
214 /* enable bits are inverted */
215 sky2_write8(hw, B2_Y2_CLK_GATE,
216 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
217 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
218 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
219 else
220 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 221
93745494 222 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
fc99fe06 223 u32 reg;
5afa0a9c 224
fc99fe06
SH		 225 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
226 /* set all bits to 0 except bits 15..12 and 8 */
227 reg &= P_ASPM_CONTROL_MSK;
228 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
229
230 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
231 /* set all bits to 0 except bits 28 & 27 */
232 reg &= P_CTL_TIM_VMAIN_AV_MSK;
233 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
234
235 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 236
237 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
238 reg = sky2_read32(hw, B2_GP_IO);
239 reg |= GLB_GPIO_STAT_RACE_DIS;
240 sky2_write32(hw, B2_GP_IO, reg);
5afa0a9c 241 }
ae306cca 242}
5afa0a9c 243
ae306cca
SH		 244static void sky2_power_aux(struct sky2_hw *hw)
245{
246 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
247 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
248 else
249 /* enable bits are inverted */
250 sky2_write8(hw, B2_Y2_CLK_GATE,
251 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
252 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
253 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
254
255 /* switch power to VAUX */
256 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
257 sky2_write8(hw, B0_POWER_CTRL,
258 (PC_VAUX_ENA | PC_VCC_ENA |
259 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c 260}
261
d3bcfbeb 262static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 263{
264 u16 reg;
265
266 /* disable all GMAC IRQ's */
267 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
268 /* disable PHY IRQs */
269 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 270
cd28ab6a
SH		 271 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
272 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
273 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
274 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
275
276 reg = gma_read16(hw, port, GM_RX_CTRL);
277 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
278 gma_write16(hw, port, GM_RX_CTRL, reg);
279}
280
16ad91e1
SH		 281/* flow control to advertise bits */
282static const u16 copper_fc_adv[] = {
283 [FC_NONE] = 0,
284 [FC_TX] = PHY_M_AN_ASP,
285 [FC_RX] = PHY_M_AN_PC,
286 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
287};
288
289/* flow control to advertise bits when using 1000BaseX */
290static const u16 fiber_fc_adv[] = {
291 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
292 [FC_TX] = PHY_M_P_ASYM_MD_X,
293 [FC_RX] = PHY_M_P_SYM_MD_X,
294 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
295};
296
297/* flow control to GMA disable bits */
298static const u16 gm_fc_disable[] = {
299 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
300 [FC_TX] = GM_GPCR_FC_RX_DIS,
301 [FC_RX] = GM_GPCR_FC_TX_DIS,
302 [FC_BOTH] = 0,
303};
304
305
cd28ab6a
SH		 306static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
307{
308 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 309 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 310
93745494
SH		 311 if (sky2->autoneg == AUTONEG_ENABLE
312 && !(hw->chip_id == CHIP_ID_YUKON_XL
313 || hw->chip_id == CHIP_ID_YUKON_EC_U
314 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 315 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
316
317 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 318 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 319 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
320
53419c68 321 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 322 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 323 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 324 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
325 else
53419c68
SH		 326 /* set master & slave downshift counter to 1x */
327 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 328
329 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
330 }
331
332 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 333 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 334 if (hw->chip_id == CHIP_ID_YUKON_FE) {
335 /* enable automatic crossover */
336 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
337 } else {
338 /* disable energy detect */
339 ctrl &= ~PHY_M_PC_EN_DET_MSK;
340
341 /* enable automatic crossover */
342 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
343
53419c68 344 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494
SH		 345 if (sky2->autoneg == AUTONEG_ENABLE
346 && (hw->chip_id == CHIP_ID_YUKON_XL
347 || hw->chip_id == CHIP_ID_YUKON_EC_U
348 || hw->chip_id == CHIP_ID_YUKON_EX)) {
53419c68 349 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 350 ctrl &= ~PHY_M_PC_DSC_MSK;
351 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
352 }
353 }
cd28ab6a
SH		 354 } else {
355 /* workaround for deviation #4.88 (CRC errors) */
356 /* disable Automatic Crossover */
357
358 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 359 }
cd28ab6a 360
b89165f2
SH		 361 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
362
363 /* special setup for PHY 88E1112 Fiber */
364 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
365 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 366
b89165f2
SH		 367 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
368 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
369 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
370 ctrl &= ~PHY_M_MAC_MD_MSK;
371 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
372 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
373
374 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 375 /* select page 1 to access Fiber registers */
376 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 377
378 /* for SFP-module set SIGDET polarity to low */
379 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
380 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 381 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 382 }
b89165f2
SH		 383
384 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 385 }
386
7800fddc 387 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 388 ct1000 = 0;
389 adv = PHY_AN_CSMA;
2eaba1a2 390 reg = 0;
cd28ab6a
SH		 391
392 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 393 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 394 if (sky2->advertising & ADVERTISED_1000baseT_Full)
395 ct1000 |= PHY_M_1000C_AFD;
396 if (sky2->advertising & ADVERTISED_1000baseT_Half)
397 ct1000 |= PHY_M_1000C_AHD;
398 if (sky2->advertising & ADVERTISED_100baseT_Full)
399 adv |= PHY_M_AN_100_FD;
400 if (sky2->advertising & ADVERTISED_100baseT_Half)
401 adv |= PHY_M_AN_100_HD;
402 if (sky2->advertising & ADVERTISED_10baseT_Full)
403 adv |= PHY_M_AN_10_FD;
404 if (sky2->advertising & ADVERTISED_10baseT_Half)
405 adv |= PHY_M_AN_10_HD;
709c6e7b 406
16ad91e1 407 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 408 } else { /* special defines for FIBER (88E1040S only) */
409 if (sky2->advertising & ADVERTISED_1000baseT_Full)
410 adv |= PHY_M_AN_1000X_AFD;
411 if (sky2->advertising & ADVERTISED_1000baseT_Half)
412 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 413
16ad91e1 414 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 415 }
cd28ab6a
SH		 416
417 /* Restart Auto-negotiation */
418 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
419 } else {
420 /* forced speed/duplex settings */
421 ct1000 = PHY_M_1000C_MSE;
422
2eaba1a2
SH		 423 /* Disable auto update for duplex flow control and speed */
424 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 425
426 switch (sky2->speed) {
427 case SPEED_1000:
428 ctrl |= PHY_CT_SP1000;
2eaba1a2 429 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 430 break;
431 case SPEED_100:
432 ctrl |= PHY_CT_SP100;
2eaba1a2 433 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 434 break;
435 }
436
2eaba1a2
SH		 437 if (sky2->duplex == DUPLEX_FULL) {
438 reg |= GM_GPCR_DUP_FULL;
439 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 440 } else if (sky2->speed < SPEED_1000)
441 sky2->flow_mode = FC_NONE;
2eaba1a2 442
2eaba1a2 443
16ad91e1 444 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 445
446 /* Forward pause packets to GMAC? */
16ad91e1 447 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 448 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
449 else
450 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 451 }
452
2eaba1a2
SH		 453 gma_write16(hw, port, GM_GP_CTRL, reg);
454
cd28ab6a
SH		 455 if (hw->chip_id != CHIP_ID_YUKON_FE)
456 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
457
458 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
459 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
460
461 /* Setup Phy LED's */
462 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
463 ledover = 0;
464
465 switch (hw->chip_id) {
466 case CHIP_ID_YUKON_FE:
467 /* on 88E3082 these bits are at 11..9 (shifted left) */
468 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
469
470 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
471
472 /* delete ACT LED control bits */
473 ctrl &= ~PHY_M_FELP_LED1_MSK;
474 /* change ACT LED control to blink mode */
475 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
476 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
477 break;
478
479 case CHIP_ID_YUKON_XL:
793b883e 480 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 481
482 /* select page 3 to access LED control register */
483 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
484
485 /* set LED Function Control register */
ed6d32c7
SH		 486 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
487 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
488 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
489 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
490 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 491
492 /* set Polarity Control register */
493 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 494 (PHY_M_POLC_LS1_P_MIX(4) |
495 PHY_M_POLC_IS0_P_MIX(4) |
496 PHY_M_POLC_LOS_CTRL(2) |
497 PHY_M_POLC_INIT_CTRL(2) |
498 PHY_M_POLC_STA1_CTRL(2) |
499 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 500
501 /* restore page register */
793b883e 502 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 503 break;
93745494 504
ed6d32c7 505 case CHIP_ID_YUKON_EC_U:
93745494 506 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 507 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
508
509 /* select page 3 to access LED control register */
510 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
511
512 /* set LED Function Control register */
513 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
514 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
515 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
516 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
517 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
518
519 /* set Blink Rate in LED Timer Control Register */
520 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
521 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
522 /* restore page register */
523 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
524 break;
cd28ab6a
SH		 525
526 default:
527 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
528 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
529 /* turn off the Rx LED (LED_RX) */
0efdf262 530 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 531 }
532
9467a8fc
SH		 533 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
534 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 535 /* apply fixes in PHY AFE */
ed6d32c7
SH		 536 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
537
977bdf06 538 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 539 gm_phy_write(hw, port, 0x18, 0xaa99);
540 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 541
977bdf06 542 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 543 gm_phy_write(hw, port, 0x18, 0xa204);
544 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 545
546 /* set page register to 0 */
9467a8fc 547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
93745494 548 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
977bdf06 549 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 550
977bdf06
SH		 551 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
552 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 553 ledover |= PHY_M_LED_MO_100;
977bdf06 554 }
cd28ab6a 555
977bdf06
SH		 556 if (ledover)
557 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
558
559 }
2eaba1a2 560
d571b694 561 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 562 if (sky2->autoneg == AUTONEG_ENABLE)
563 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
564 else
565 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
566}
567
d3bcfbeb 568static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
569{
570 u32 reg1;
571 static const u32 phy_power[]
572 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
573
574 /* looks like this XL is back asswards .. */
575 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
576 onoff = !onoff;
577
aed2cec4 578 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 579 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb 580 if (onoff)
581 /* Turn off phy power saving */
582 reg1 &= ~phy_power[port];
583 else
584 reg1 |= phy_power[port];
585
586 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 587 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 588 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb 589 udelay(100);
590}
591
1b537565
SH		 592/* Force a renegotiation */
593static void sky2_phy_reinit(struct sky2_port *sky2)
594{
e07b1aa8 595 spin_lock_bh(&sky2->phy_lock);
1b537565 596 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 597 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 598}
599
e3173832
SH		 600/* Put device in state to listen for Wake On Lan */
601static void sky2_wol_init(struct sky2_port *sky2)
602{
603 struct sky2_hw *hw = sky2->hw;
604 unsigned port = sky2->port;
605 enum flow_control save_mode;
606 u16 ctrl;
607 u32 reg1;
608
609 /* Bring hardware out of reset */
610 sky2_write16(hw, B0_CTST, CS_RST_CLR);
611 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
612
613 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
614 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
615
616 /* Force to 10/100
617 * sky2_reset will re-enable on resume
618 */
619 save_mode = sky2->flow_mode;
620 ctrl = sky2->advertising;
621
622 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
623 sky2->flow_mode = FC_NONE;
624 sky2_phy_power(hw, port, 1);
625 sky2_phy_reinit(sky2);
626
627 sky2->flow_mode = save_mode;
628 sky2->advertising = ctrl;
629
630 /* Set GMAC to no flow control and auto update for speed/duplex */
631 gma_write16(hw, port, GM_GP_CTRL,
632 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
633 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
634
635 /* Set WOL address */
636 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
637 sky2->netdev->dev_addr, ETH_ALEN);
638
639 /* Turn on appropriate WOL control bits */
640 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
641 ctrl = 0;
642 if (sky2->wol & WAKE_PHY)
643 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
644 else
645 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
646
647 if (sky2->wol & WAKE_MAGIC)
648 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
649 else
650 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
651
652 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
653 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
654
655 /* Turn on legacy PCI-Express PME mode */
656 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
657 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
658 reg1 |= PCI_Y2_PME_LEGACY;
659 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
660 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
661
662 /* block receiver */
663 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
664
665}
666
69161611
SH		 667static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
668{
669 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev != CHIP_REV_YU_EX_A0) {
670 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
671 TX_STFW_ENA |
672 (hw->dev[port]->mtu > ETH_DATA_LEN) ? TX_JUMBO_ENA : TX_JUMBO_DIS);
673 } else {
674 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
675 /* set Tx GMAC FIFO Almost Empty Threshold */
676 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
677 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
678
679 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
680 TX_JUMBO_ENA | TX_STFW_DIS);
681
682 /* Can't do offload because of lack of store/forward */
683 hw->dev[port]->features &= ~(NETIF_F_TSO | NETIF_F_SG
684 | NETIF_F_ALL_CSUM);
685 } else
686 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
687 TX_JUMBO_DIS | TX_STFW_ENA);
688 }
689}
690
cd28ab6a
SH		 691static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
692{
693 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
694 u16 reg;
25cccecc 695 u32 rx_reg;
cd28ab6a
SH		 696 int i;
697 const u8 *addr = hw->dev[port]->dev_addr;
698
f350339c
SH		 699 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
700 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 701
702 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
703
793b883e 704 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 705 /* WA DEV_472 -- looks like crossed wires on port 2 */
706 /* clear GMAC 1 Control reset */
707 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
708 do {
709 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
710 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
711 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
712 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
713 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
714 }
715
793b883e 716 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 717
2eaba1a2
SH		 718 /* Enable Transmit FIFO Underrun */
719 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
720
e07b1aa8 721 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 722 sky2_phy_init(hw, port);
e07b1aa8 723 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 724
725 /* MIB clear */
726 reg = gma_read16(hw, port, GM_PHY_ADDR);
727 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
728
43f2f104
SH		 729 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
730 gma_read16(hw, port, i);
cd28ab6a
SH		 731 gma_write16(hw, port, GM_PHY_ADDR, reg);
732
733 /* transmit control */
734 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
735
736 /* receive control reg: unicast + multicast + no FCS */
737 gma_write16(hw, port, GM_RX_CTRL,
793b883e 738 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 739
740 /* transmit flow control */
741 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
742
743 /* transmit parameter */
744 gma_write16(hw, port, GM_TX_PARAM,
745 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
746 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
747 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
748 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
749
750 /* serial mode register */
751 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 752 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 753
6b1a3aef 754 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 755 reg |= GM_SMOD_JUMBO_ENA;
756
757 gma_write16(hw, port, GM_SERIAL_MODE, reg);
758
cd28ab6a
SH		 759 /* virtual address for data */
760 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
761
793b883e
SH		 762 /* physical address: used for pause frames */
763 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
764
765 /* ignore counter overflows */
cd28ab6a
SH		 766 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
767 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
768 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
769
770 /* Configure Rx MAC FIFO */
771 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 772 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
69161611 773 if (hw->chip_id == CHIP_ID_YUKON_EX)
25cccecc 774 rx_reg |= GMF_RX_OVER_ON;
69161611 775
25cccecc 776 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 777
d571b694 778 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 779 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 780
8df9a876
SH		 781 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
782 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 783
784 /* Configure Tx MAC FIFO */
785 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
786 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 787
93745494 788 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
8df9a876 789 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 790 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 791
69161611 792 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 793 }
794
cd28ab6a
SH		 795}
796
67712901
SH		 797/* Assign Ram Buffer allocation to queue */
798static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 799{
67712901
SH		 800 u32 end;
801
802 /* convert from K bytes to qwords used for hw register */
803 start *= 1024/8;
804 space *= 1024/8;
805 end = start + space - 1;
793b883e 806
cd28ab6a
SH		 807 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
808 sky2_write32(hw, RB_ADDR(q, RB_START), start);
809 sky2_write32(hw, RB_ADDR(q, RB_END), end);
810 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
811 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
812
813 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 814 u32 tp = space - space/4;
793b883e 815
1c28f6ba
SH		 816 /* On receive queue's set the thresholds
817 * give receiver priority when > 3/4 full
818 * send pause when down to 2K
819 */
820 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
821 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 822
1c28f6ba
SH		 823 tp = space - 2048/8;
824 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
825 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 826 } else {
827 /* Enable store & forward on Tx queue's because
828 * Tx FIFO is only 1K on Yukon
829 */
830 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
831 }
832
833 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 834 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 835}
836
cd28ab6a 837/* Setup Bus Memory Interface */
af4ed7e6 838static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 839{
840 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
841 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
842 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 843 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 844}
845
cd28ab6a
SH		 846/* Setup prefetch unit registers. This is the interface between
847 * hardware and driver list elements
848 */
8cc048e3 849static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 850 u64 addr, u32 last)
851{
cd28ab6a
SH		 852 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
853 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
854 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
855 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
856 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
857 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 858
859 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 860}
861
793b883e
SH		 862static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
863{
864 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
865
cb5d9547 866 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 867 le->ctrl = 0;
793b883e
SH		 868 return le;
869}
cd28ab6a 870
291ea614
SH		 871static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
872 struct sky2_tx_le *le)
873{
874 return sky2->tx_ring + (le - sky2->tx_le);
875}
876
290d4de5
SH		 877/* Update chip's next pointer */
878static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 879{
50432cb5 880 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 881 wmb();
50432cb5
SH		 882 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
883
884 /* Synchronize I/O on since next processor may write to tail */
885 mmiowb();
cd28ab6a
SH		 886}
887
793b883e 888
cd28ab6a
SH		 889static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
890{
891 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 892 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 893 le->ctrl = 0;
cd28ab6a
SH		 894 return le;
895}
896
14d0263f
SH		 897/* Build description to hardware for one receive segment */
898static void sky2_rx_add(struct sky2_port *sky2, u8 op,
899 dma_addr_t map, unsigned len)
cd28ab6a
SH		 900{
901 struct sky2_rx_le *le;
36eb0c71 902 u32 hi = upper_32_bits(map);
cd28ab6a 903
793b883e 904 if (sky2->rx_addr64 != hi) {
cd28ab6a 905 le = sky2_next_rx(sky2);
793b883e 906 le->addr = cpu_to_le32(hi);
cd28ab6a 907 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 908 sky2->rx_addr64 = upper_32_bits(map + len);
cd28ab6a 909 }
793b883e 910
cd28ab6a 911 le = sky2_next_rx(sky2);
734d1868
SH		 912 le->addr = cpu_to_le32((u32) map);
913 le->length = cpu_to_le16(len);
14d0263f 914 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 915}
916
14d0263f
SH		 917/* Build description to hardware for one possibly fragmented skb */
918static void sky2_rx_submit(struct sky2_port *sky2,
919 const struct rx_ring_info *re)
920{
921 int i;
922
923 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
924
925 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
926 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
927}
928
929
930static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
931 unsigned size)
932{
933 struct sk_buff *skb = re->skb;
934 int i;
935
936 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
937 pci_unmap_len_set(re, data_size, size);
938
939 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
940 re->frag_addr[i] = pci_map_page(pdev,
941 skb_shinfo(skb)->frags[i].page,
942 skb_shinfo(skb)->frags[i].page_offset,
943 skb_shinfo(skb)->frags[i].size,
944 PCI_DMA_FROMDEVICE);
945}
946
947static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
948{
949 struct sk_buff *skb = re->skb;
950 int i;
951
952 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
953 PCI_DMA_FROMDEVICE);
954
955 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
956 pci_unmap_page(pdev, re->frag_addr[i],
957 skb_shinfo(skb)->frags[i].size,
958 PCI_DMA_FROMDEVICE);
959}
793b883e 960
cd28ab6a
SH		 961/* Tell chip where to start receive checksum.
962 * Actually has two checksums, but set both same to avoid possible byte
963 * order problems.
964 */
793b883e 965static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 966{
967 struct sky2_rx_le *le;
968
69161611
SH		 969 if (sky2->hw->chip_id != CHIP_ID_YUKON_EX) {
970 le = sky2_next_rx(sky2);
971 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
972 le->ctrl = 0;
973 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 974
69161611
SH		 975 sky2_write32(sky2->hw,
976 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
977 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
978 }
cd28ab6a
SH		 979
980}
981
6b1a3aef 982/*
983 * The RX Stop command will not work for Yukon-2 if the BMU does not
984 * reach the end of packet and since we can't make sure that we have
985 * incoming data, we must reset the BMU while it is not doing a DMA
986 * transfer. Since it is possible that the RX path is still active,
987 * the RX RAM buffer will be stopped first, so any possible incoming
988 * data will not trigger a DMA. After the RAM buffer is stopped, the
989 * BMU is polled until any DMA in progress is ended and only then it
990 * will be reset.
991 */
992static void sky2_rx_stop(struct sky2_port *sky2)
993{
994 struct sky2_hw *hw = sky2->hw;
995 unsigned rxq = rxqaddr[sky2->port];
996 int i;
997
998 /* disable the RAM Buffer receive queue */
999 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1000
1001 for (i = 0; i < 0xffff; i++)
1002 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1003 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1004 goto stopped;
1005
1006 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1007 sky2->netdev->name);
1008stopped:
1009 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1010
1011 /* reset the Rx prefetch unit */
1012 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1013 mmiowb();
6b1a3aef 1014}
793b883e 1015
d571b694 1016/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1017static void sky2_rx_clean(struct sky2_port *sky2)
1018{
1019 unsigned i;
1020
1021 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1022 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1023 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1024
1025 if (re->skb) {
14d0263f 1026 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1027 kfree_skb(re->skb);
1028 re->skb = NULL;
1029 }
1030 }
1031}
1032
ef743d33 1033/* Basic MII support */
1034static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1035{
1036 struct mii_ioctl_data *data = if_mii(ifr);
1037 struct sky2_port *sky2 = netdev_priv(dev);
1038 struct sky2_hw *hw = sky2->hw;
1039 int err = -EOPNOTSUPP;
1040
1041 if (!netif_running(dev))
1042 return -ENODEV; /* Phy still in reset */
1043
d89e1343 1044 switch (cmd) {
ef743d33 1045 case SIOCGMIIPHY:
1046 data->phy_id = PHY_ADDR_MARV;
1047
1048 /* fallthru */
1049 case SIOCGMIIREG: {
1050 u16 val = 0;
91c86df5 1051
e07b1aa8 1052 spin_lock_bh(&sky2->phy_lock);
ef743d33 1053 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1054 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1055
ef743d33 1056 data->val_out = val;
1057 break;
1058 }
1059
1060 case SIOCSMIIREG:
1061 if (!capable(CAP_NET_ADMIN))
1062 return -EPERM;
1063
e07b1aa8 1064 spin_lock_bh(&sky2->phy_lock);
ef743d33 1065 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1066 data->val_in);
e07b1aa8 1067 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1068 break;
1069 }
1070 return err;
1071}
1072
d1f13708 1073#ifdef SKY2_VLAN_TAG_USED
1074static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1075{
1076 struct sky2_port *sky2 = netdev_priv(dev);
1077 struct sky2_hw *hw = sky2->hw;
1078 u16 port = sky2->port;
d1f13708 1079
2bb8c262 1080 netif_tx_lock_bh(dev);
3d4e66f5 1081 netif_poll_disable(sky2->hw->dev[0]);
d1f13708 1082
d1f13708 1083 sky2->vlgrp = grp;
3d4e66f5
SH		 1084 if (grp) {
1085 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1086 RX_VLAN_STRIP_ON);
1087 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1088 TX_VLAN_TAG_ON);
1089 } else {
1090 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1091 RX_VLAN_STRIP_OFF);
1092 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1093 TX_VLAN_TAG_OFF);
1094 }
d1f13708 1095
3d4e66f5 1096 netif_poll_enable(sky2->hw->dev[0]);
2bb8c262 1097 netif_tx_unlock_bh(dev);
d1f13708 1098}
1099#endif
1100
82788c7a 1101/*
14d0263f
SH		 1102 * Allocate an skb for receiving. If the MTU is large enough
1103 * make the skb non-linear with a fragment list of pages.
1104 *
82788c7a
SH		 1105 * It appears the hardware has a bug in the FIFO logic that
1106 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86 1107 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1108 * aligned except if slab debugging is enabled.
82788c7a 1109 */
14d0263f 1110static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1111{
1112 struct sk_buff *skb;
14d0263f
SH		 1113 unsigned long p;
1114 int i;
82788c7a 1115
14d0263f
SH		 1116 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1117 if (!skb)
1118 goto nomem;
1119
1120 p = (unsigned long) skb->data;
1121 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1122
1123 for (i = 0; i < sky2->rx_nfrags; i++) {
1124 struct page *page = alloc_page(GFP_ATOMIC);
1125
1126 if (!page)
1127 goto free_partial;
1128 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1129 }
1130
1131 return skb;
14d0263f
SH		 1132free_partial:
1133 kfree_skb(skb);
1134nomem:
1135 return NULL;
82788c7a
SH		 1136}
1137
55c9dd35
SH		 1138static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1139{
1140 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1141}
1142
cd28ab6a
SH		 1143/*
1144 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1145 * Normal case this ends up creating one list element for skb
1146 * in the receive ring. Worst case if using large MTU and each
1147 * allocation falls on a different 64 bit region, that results
1148 * in 6 list elements per ring entry.
1149 * One element is used for checksum enable/disable, and one
1150 * extra to avoid wrap.
cd28ab6a 1151 */
6b1a3aef 1152static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1153{
6b1a3aef 1154 struct sky2_hw *hw = sky2->hw;
14d0263f 1155 struct rx_ring_info *re;
6b1a3aef 1156 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1157 unsigned i, size, space, thresh;
cd28ab6a 1158
6b1a3aef 1159 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1160 sky2_qset(hw, rxq);
977bdf06 1161
c3905bc4
SH		 1162 /* On PCI express lowering the watermark gives better performance */
1163 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1164 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1165
1166 /* These chips have no ram buffer?
1167 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1168 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1169 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1170 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1171 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1172
6b1a3aef 1173 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1174
1175 rx_set_checksum(sky2);
14d0263f
SH		 1176
1177 /* Space needed for frame data + headers rounded up */
f957da2a 1178 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1179
1180 /* Stopping point for hardware truncation */
1181 thresh = (size - 8) / sizeof(u32);
1182
1183 /* Account for overhead of skb - to avoid order > 0 allocation */
1184 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1185 + sizeof(struct skb_shared_info);
1186
1187 sky2->rx_nfrags = space >> PAGE_SHIFT;
1188 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1189
1190 if (sky2->rx_nfrags != 0) {
1191 /* Compute residue after pages */
1192 space = sky2->rx_nfrags << PAGE_SHIFT;
1193
1194 if (space < size)
1195 size -= space;
1196 else
1197 size = 0;
1198
1199 /* Optimize to handle small packets and headers */
1200 if (size < copybreak)
1201 size = copybreak;
1202 if (size < ETH_HLEN)
1203 size = ETH_HLEN;
1204 }
1205 sky2->rx_data_size = size;
1206
1207 /* Fill Rx ring */
793b883e 1208 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1209 re = sky2->rx_ring + i;
cd28ab6a 1210
14d0263f 1211 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1212 if (!re->skb)
1213 goto nomem;
1214
14d0263f
SH		 1215 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1216 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1217 }
1218
a1433ac4
SH		 1219 /*
1220 * The receiver hangs if it receives frames larger than the
1221 * packet buffer. As a workaround, truncate oversize frames, but
1222 * the register is limited to 9 bits, so if you do frames > 2052
1223 * you better get the MTU right!
1224 */
a1433ac4
SH		 1225 if (thresh > 0x1ff)
1226 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1227 else {
1228 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1229 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1230 }
1231
6b1a3aef 1232 /* Tell chip about available buffers */
55c9dd35 1233 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1234 return 0;
1235nomem:
1236 sky2_rx_clean(sky2);
1237 return -ENOMEM;
1238}
1239
1240/* Bring up network interface. */
1241static int sky2_up(struct net_device *dev)
1242{
1243 struct sky2_port *sky2 = netdev_priv(dev);
1244 struct sky2_hw *hw = sky2->hw;
1245 unsigned port = sky2->port;
67712901 1246 u32 ramsize, imask;
ee7abb04 1247 int cap, err = -ENOMEM;
843a46f4 1248 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1249
ee7abb04
SH		 1250 /*
1251 * On dual port PCI-X card, there is an problem where status
1252 * can be received out of order due to split transactions
843a46f4 1253 */
ee7abb04
SH		 1254 if (otherdev && netif_running(otherdev) &&
1255 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1256 struct sky2_port *osky2 = netdev_priv(otherdev);
1257 u16 cmd;
1258
1259 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1260 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1261 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1262
1263 sky2->rx_csum = 0;
1264 osky2->rx_csum = 0;
1265 }
843a46f4 1266
cd28ab6a
SH		 1267 if (netif_msg_ifup(sky2))
1268 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1269
55d7b4e6
SH		 1270 netif_carrier_off(dev);
1271
cd28ab6a
SH		 1272 /* must be power of 2 */
1273 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1274 TX_RING_SIZE *
1275 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1276 &sky2->tx_le_map);
1277 if (!sky2->tx_le)
1278 goto err_out;
1279
6cdbbdf3 1280 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1281 GFP_KERNEL);
1282 if (!sky2->tx_ring)
1283 goto err_out;
1284 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1285
1286 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1287 &sky2->rx_le_map);
1288 if (!sky2->rx_le)
1289 goto err_out;
1290 memset(sky2->rx_le, 0, RX_LE_BYTES);
1291
291ea614 1292 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1293 GFP_KERNEL);
1294 if (!sky2->rx_ring)
1295 goto err_out;
1296
d3bcfbeb 1297 sky2_phy_power(hw, port, 1);
1298
cd28ab6a
SH		 1299 sky2_mac_init(hw, port);
1300
67712901
SH		 1301 /* Register is number of 4K blocks on internal RAM buffer. */
1302 ramsize = sky2_read8(hw, B2_E_0) * 4;
1303 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1c28f6ba 1304
67712901
SH		 1305 if (ramsize > 0) {
1306 u32 rxspace;
cd28ab6a 1307
67712901
SH		 1308 if (ramsize < 16)
1309 rxspace = ramsize / 2;
1310 else
1311 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1312
67712901
SH		 1313 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1314 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1315
1316 /* Make sure SyncQ is disabled */
1317 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1318 RB_RST_SET);
1319 }
793b883e 1320
af4ed7e6 1321 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1322
69161611
SH		 1323 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1324 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1325 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1326
977bdf06 1327 /* Set almost empty threshold */
c2716fb4
SH		 1328 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1329 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1330 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1331
6b1a3aef 1332 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1333 TX_RING_SIZE - 1);
cd28ab6a 1334
6b1a3aef 1335 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1336 if (err)
1337 goto err_out;
1338
cd28ab6a 1339 /* Enable interrupts from phy/mac for port */
e07b1aa8 1340 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1341 imask |= portirq_msk[port];
e07b1aa8
SH		 1342 sky2_write32(hw, B0_IMSK, imask);
1343
cd28ab6a
SH		 1344 return 0;
1345
1346err_out:
1b537565 1347 if (sky2->rx_le) {
cd28ab6a
SH		 1348 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1349 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1350 sky2->rx_le = NULL;
1351 }
1352 if (sky2->tx_le) {
cd28ab6a
SH		 1353 pci_free_consistent(hw->pdev,
1354 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1355 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1356 sky2->tx_le = NULL;
1357 }
1358 kfree(sky2->tx_ring);
1359 kfree(sky2->rx_ring);
cd28ab6a 1360
1b537565
SH		 1361 sky2->tx_ring = NULL;
1362 sky2->rx_ring = NULL;
cd28ab6a
SH		 1363 return err;
1364}
1365
793b883e
SH		 1366/* Modular subtraction in ring */
1367static inline int tx_dist(unsigned tail, unsigned head)
1368{
cb5d9547 1369 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1370}
cd28ab6a 1371
793b883e
SH		 1372/* Number of list elements available for next tx */
1373static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1374{
793b883e 1375 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1376}
1377
793b883e 1378/* Estimate of number of transmit list elements required */
28bd181a 1379static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1380{
793b883e
SH		 1381 unsigned count;
1382
1383 count = sizeof(dma_addr_t) / sizeof(u32);
1384 count += skb_shinfo(skb)->nr_frags * count;
1385
89114afd 1386 if (skb_is_gso(skb))
793b883e
SH		 1387 ++count;
1388
84fa7933 1389 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1390 ++count;
1391
1392 return count;
cd28ab6a
SH		 1393}
1394
793b883e
SH		 1395/*
1396 * Put one packet in ring for transmit.
1397 * A single packet can generate multiple list elements, and
1398 * the number of ring elements will probably be less than the number
1399 * of list elements used.
1400 */
cd28ab6a
SH		 1401static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1402{
1403 struct sky2_port *sky2 = netdev_priv(dev);
1404 struct sky2_hw *hw = sky2->hw;
d1f13708 1405 struct sky2_tx_le *le = NULL;
6cdbbdf3 1406 struct tx_ring_info *re;
cd28ab6a
SH		 1407 unsigned i, len;
1408 dma_addr_t mapping;
1409 u32 addr64;
1410 u16 mss;
1411 u8 ctrl;
1412
2bb8c262
SH		 1413 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1414 return NETDEV_TX_BUSY;
cd28ab6a 1415
793b883e 1416 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1417 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1418 dev->name, sky2->tx_prod, skb->len);
1419
cd28ab6a
SH		 1420 len = skb_headlen(skb);
1421 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
36eb0c71 1422 addr64 = upper_32_bits(mapping);
793b883e 1423
a018e330 1424 /* Send high bits if changed or crosses boundary */
36eb0c71
SH		 1425 if (addr64 != sky2->tx_addr64 ||
1426 upper_32_bits(mapping + len) != sky2->tx_addr64) {
793b883e 1427 le = get_tx_le(sky2);
f65b138c 1428 le->addr = cpu_to_le32(addr64);
793b883e 1429 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 1430 sky2->tx_addr64 = upper_32_bits(mapping + len);
793b883e 1431 }
cd28ab6a
SH		 1432
1433 /* Check for TCP Segmentation Offload */
7967168c 1434 mss = skb_shinfo(skb)->gso_size;
793b883e 1435 if (mss != 0) {
69161611
SH		 1436 if (hw->chip_id != CHIP_ID_YUKON_EX)
1437 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1438
1439 if (mss != sky2->tx_last_mss) {
1440 le = get_tx_le(sky2);
1441 le->addr = cpu_to_le32(mss);
1442 if (hw->chip_id == CHIP_ID_YUKON_EX)
1443 le->opcode = OP_MSS | HW_OWNER;
1444 else
1445 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1446 sky2->tx_last_mss = mss;
1447 }
cd28ab6a
SH		 1448 }
1449
cd28ab6a 1450 ctrl = 0;
d1f13708 1451#ifdef SKY2_VLAN_TAG_USED
1452 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1453 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1454 if (!le) {
1455 le = get_tx_le(sky2);
f65b138c 1456 le->addr = 0;
d1f13708 1457 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1458 } else
1459 le->opcode |= OP_VLAN;
1460 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1461 ctrl |= INS_VLAN;
1462 }
1463#endif
1464
1465 /* Handle TCP checksum offload */
84fa7933 1466 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611
SH		 1467 /* On Yukon EX (some versions) encoding change. */
1468 if (hw->chip_id == CHIP_ID_YUKON_EX
1469 && hw->chip_rev != CHIP_REV_YU_EX_B0)
1470 ctrl |= CALSUM; /* auto checksum */
1471 else {
1472 const unsigned offset = skb_transport_offset(skb);
1473 u32 tcpsum;
1474
1475 tcpsum = offset << 16; /* sum start */
1476 tcpsum |= offset + skb->csum_offset; /* sum write */
1477
1478 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1479 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1480 ctrl |= UDPTCP;
1481
1482 if (tcpsum != sky2->tx_tcpsum) {
1483 sky2->tx_tcpsum = tcpsum;
1484
1485 le = get_tx_le(sky2);
1486 le->addr = cpu_to_le32(tcpsum);
1487 le->length = 0; /* initial checksum value */
1488 le->ctrl = 1; /* one packet */
1489 le->opcode = OP_TCPLISW | HW_OWNER;
1490 }
1d179332 1491 }
cd28ab6a
SH		 1492 }
1493
1494 le = get_tx_le(sky2);
f65b138c 1495 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1496 le->length = cpu_to_le16(len);
1497 le->ctrl = ctrl;
793b883e 1498 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1499
291ea614 1500 re = tx_le_re(sky2, le);
cd28ab6a 1501 re->skb = skb;
6cdbbdf3 1502 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1503 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1504
1505 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1506 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1507
1508 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1509 frag->size, PCI_DMA_TODEVICE);
36eb0c71 1510 addr64 = upper_32_bits(mapping);
793b883e
SH		 1511 if (addr64 != sky2->tx_addr64) {
1512 le = get_tx_le(sky2);
f65b138c 1513 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1514 le->ctrl = 0;
1515 le->opcode = OP_ADDR64 | HW_OWNER;
1516 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1517 }
1518
1519 le = get_tx_le(sky2);
f65b138c 1520 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1521 le->length = cpu_to_le16(frag->size);
1522 le->ctrl = ctrl;
793b883e 1523 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1524
291ea614
SH		 1525 re = tx_le_re(sky2, le);
1526 re->skb = skb;
1527 pci_unmap_addr_set(re, mapaddr, mapping);
1528 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1529 }
6cdbbdf3 1530
cd28ab6a
SH		 1531 le->ctrl |= EOP;
1532
97bda706 1533 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1534 netif_stop_queue(dev);
b19666d9 1535
290d4de5 1536 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1537
cd28ab6a
SH		 1538 dev->trans_start = jiffies;
1539 return NETDEV_TX_OK;
1540}
1541
cd28ab6a 1542/*
793b883e
SH		 1543 * Free ring elements from starting at tx_cons until "done"
1544 *
1545 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1546 * buffers so make sure not to free skb to early.
cd28ab6a 1547 */
d11c13e7 1548static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1549{
d11c13e7 1550 struct net_device *dev = sky2->netdev;
af2a58ac 1551 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1552 unsigned idx;
cd28ab6a 1553
0e3ff6aa 1554 BUG_ON(done >= TX_RING_SIZE);
2224795d 1555
291ea614
SH		 1556 for (idx = sky2->tx_cons; idx != done;
1557 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1558 struct sky2_tx_le *le = sky2->tx_le + idx;
1559 struct tx_ring_info *re = sky2->tx_ring + idx;
1560
1561 switch(le->opcode & ~HW_OWNER) {
1562 case OP_LARGESEND:
1563 case OP_PACKET:
1564 pci_unmap_single(pdev,
1565 pci_unmap_addr(re, mapaddr),
1566 pci_unmap_len(re, maplen),
1567 PCI_DMA_TODEVICE);
af2a58ac 1568 break;
291ea614
SH		 1569 case OP_BUFFER:
1570 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1571 pci_unmap_len(re, maplen),
734d1868 1572 PCI_DMA_TODEVICE);
291ea614
SH		 1573 break;
1574 }
1575
1576 if (le->ctrl & EOP) {
1577 if (unlikely(netif_msg_tx_done(sky2)))
1578 printk(KERN_DEBUG "%s: tx done %u\n",
1579 dev->name, idx);
3cf26753 1580
2bf56fe2 1581 sky2->net_stats.tx_packets++;
1582 sky2->net_stats.tx_bytes += re->skb->len;
1583
794b2bd2 1584 dev_kfree_skb_any(re->skb);
3cf26753 1585 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1586 }
793b883e 1587 }
793b883e 1588
291ea614 1589 sky2->tx_cons = idx;
50432cb5
SH		 1590 smp_mb();
1591
22e11703 1592 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1593 netif_wake_queue(dev);
cd28ab6a
SH		 1594}
1595
1596/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1597static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1598{
2bb8c262
SH		 1599 struct sky2_port *sky2 = netdev_priv(dev);
1600
1601 netif_tx_lock_bh(dev);
d11c13e7 1602 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1603 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1604}
1605
1606/* Network shutdown */
1607static int sky2_down(struct net_device *dev)
1608{
1609 struct sky2_port *sky2 = netdev_priv(dev);
1610 struct sky2_hw *hw = sky2->hw;
1611 unsigned port = sky2->port;
1612 u16 ctrl;
e07b1aa8 1613 u32 imask;
cd28ab6a 1614
1b537565
SH		 1615 /* Never really got started! */
1616 if (!sky2->tx_le)
1617 return 0;
1618
cd28ab6a
SH		 1619 if (netif_msg_ifdown(sky2))
1620 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1621
018d1c66 1622 /* Stop more packets from being queued */
cd28ab6a
SH		 1623 netif_stop_queue(dev);
1624
ebc646f6
SH		 1625 /* Disable port IRQ */
1626 imask = sky2_read32(hw, B0_IMSK);
1627 imask &= ~portirq_msk[port];
1628 sky2_write32(hw, B0_IMSK, imask);
1629
d3bcfbeb 1630 sky2_gmac_reset(hw, port);
793b883e 1631
cd28ab6a
SH		 1632 /* Stop transmitter */
1633 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1634 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1635
1636 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1637 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1638
1639 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1640 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1641 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1642
1643 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1644
1645 /* Workaround shared GMAC reset */
793b883e
SH		 1646 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1647 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1648 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1649
1650 /* Disable Force Sync bit and Enable Alloc bit */
1651 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1652 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1653
1654 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1655 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1656 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1657
1658 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1659 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1660 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1661
1662 /* Reset the Tx prefetch units */
1663 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1664 PREF_UNIT_RST_SET);
1665
1666 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1667
6b1a3aef 1668 sky2_rx_stop(sky2);
cd28ab6a
SH		 1669
1670 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1671 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1672
d3bcfbeb 1673 sky2_phy_power(hw, port, 0);
1674
55d7b4e6
SH		 1675 netif_carrier_off(dev);
1676
d571b694 1677 /* turn off LED's */
cd28ab6a
SH		 1678 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1679
018d1c66 1680 synchronize_irq(hw->pdev->irq);
1681
2bb8c262 1682 sky2_tx_clean(dev);
cd28ab6a
SH		 1683 sky2_rx_clean(sky2);
1684
1685 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1686 sky2->rx_le, sky2->rx_le_map);
1687 kfree(sky2->rx_ring);
1688
1689 pci_free_consistent(hw->pdev,
1690 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1691 sky2->tx_le, sky2->tx_le_map);
1692 kfree(sky2->tx_ring);
1693
1b537565
SH		 1694 sky2->tx_le = NULL;
1695 sky2->rx_le = NULL;
1696
1697 sky2->rx_ring = NULL;
1698 sky2->tx_ring = NULL;
1699
cd28ab6a
SH		 1700 return 0;
1701}
1702
1703static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1704{
b89165f2 1705 if (!sky2_is_copper(hw))
793b883e
SH		 1706 return SPEED_1000;
1707
cd28ab6a
SH		 1708 if (hw->chip_id == CHIP_ID_YUKON_FE)
1709 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1710
1711 switch (aux & PHY_M_PS_SPEED_MSK) {
1712 case PHY_M_PS_SPEED_1000:
1713 return SPEED_1000;
1714 case PHY_M_PS_SPEED_100:
1715 return SPEED_100;
1716 default:
1717 return SPEED_10;
1718 }
1719}
1720
1721static void sky2_link_up(struct sky2_port *sky2)
1722{
1723 struct sky2_hw *hw = sky2->hw;
1724 unsigned port = sky2->port;
1725 u16 reg;
16ad91e1
SH		 1726 static const char *fc_name[] = {
1727 [FC_NONE] = "none",
1728 [FC_TX] = "tx",
1729 [FC_RX] = "rx",
1730 [FC_BOTH] = "both",
1731 };
cd28ab6a 1732
cd28ab6a 1733 /* enable Rx/Tx */
2eaba1a2 1734 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1735 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1736 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1737
1738 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1739
1740 netif_carrier_on(sky2->netdev);
cd28ab6a
SH		 1741
1742 /* Turn on link LED */
793b883e 1743 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1744 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1745
93745494
SH		 1746 if (hw->chip_id == CHIP_ID_YUKON_XL
1747 || hw->chip_id == CHIP_ID_YUKON_EC_U
1748 || hw->chip_id == CHIP_ID_YUKON_EX) {
793b883e 1749 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1750 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1751
1752 switch(sky2->speed) {
1753 case SPEED_10:
1754 led |= PHY_M_LEDC_INIT_CTRL(7);
1755 break;
1756
1757 case SPEED_100:
1758 led |= PHY_M_LEDC_STA1_CTRL(7);
1759 break;
1760
1761 case SPEED_1000:
1762 led |= PHY_M_LEDC_STA0_CTRL(7);
1763 break;
1764 }
793b883e
SH		 1765
1766 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1767 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1768 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1769 }
1770
cd28ab6a
SH		 1771 if (netif_msg_link(sky2))
1772 printk(KERN_INFO PFX
d571b694 1773 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1774 sky2->netdev->name, sky2->speed,
1775 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1776 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1777}
1778
1779static void sky2_link_down(struct sky2_port *sky2)
1780{
1781 struct sky2_hw *hw = sky2->hw;
1782 unsigned port = sky2->port;
1783 u16 reg;
1784
1785 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1786
1787 reg = gma_read16(hw, port, GM_GP_CTRL);
1788 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1789 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1790
cd28ab6a 1791 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1792
1793 /* Turn on link LED */
1794 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1795
1796 if (netif_msg_link(sky2))
1797 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1798
cd28ab6a
SH		 1799 sky2_phy_init(hw, port);
1800}
1801
16ad91e1
SH		 1802static enum flow_control sky2_flow(int rx, int tx)
1803{
1804 if (rx)
1805 return tx ? FC_BOTH : FC_RX;
1806 else
1807 return tx ? FC_TX : FC_NONE;
1808}
1809
793b883e
SH		 1810static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1811{
1812 struct sky2_hw *hw = sky2->hw;
1813 unsigned port = sky2->port;
da4c1ff4 1814 u16 advert, lpa;
793b883e 1815
da4c1ff4 1816 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1817 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1818 if (lpa & PHY_M_AN_RF) {
1819 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1820 return -1;
1821 }
1822
793b883e
SH		 1823 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1824 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1825 sky2->netdev->name);
1826 return -1;
1827 }
1828
793b883e 1829 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1830 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1831
da4c1ff4
SH		 1832 /* Since the pause result bits seem to in different positions on
1833 * different chips. look at registers.
1834 */
1835 if (!sky2_is_copper(hw)) {
1836 /* Shift for bits in fiber PHY */
1837 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1838 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1839
1840 if (advert & ADVERTISE_1000XPAUSE)
1841 advert |= ADVERTISE_PAUSE_CAP;
1842 if (advert & ADVERTISE_1000XPSE_ASYM)
1843 advert |= ADVERTISE_PAUSE_ASYM;
1844 if (lpa & LPA_1000XPAUSE)
1845 lpa |= LPA_PAUSE_CAP;
1846 if (lpa & LPA_1000XPAUSE_ASYM)
1847 lpa |= LPA_PAUSE_ASYM;
1848 }
793b883e 1849
da4c1ff4
SH		 1850 sky2->flow_status = FC_NONE;
1851 if (advert & ADVERTISE_PAUSE_CAP) {
1852 if (lpa & LPA_PAUSE_CAP)
1853 sky2->flow_status = FC_BOTH;
1854 else if (advert & ADVERTISE_PAUSE_ASYM)
1855 sky2->flow_status = FC_RX;
1856 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1857 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1858 sky2->flow_status = FC_TX;
1859 }
793b883e 1860
16ad91e1 1861 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1862 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1863 sky2->flow_status = FC_NONE;
2eaba1a2 1864
da4c1ff4 1865 if (sky2->flow_status & FC_TX)
793b883e
SH		 1866 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1867 else
1868 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1869
1870 return 0;
1871}
cd28ab6a 1872
e07b1aa8
SH		 1873/* Interrupt from PHY */
1874static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1875{
e07b1aa8
SH		 1876 struct net_device *dev = hw->dev[port];
1877 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1878 u16 istatus, phystat;
1879
ebc646f6
SH		 1880 if (!netif_running(dev))
1881 return;
1882
e07b1aa8
SH		 1883 spin_lock(&sky2->phy_lock);
1884 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1885 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1886
cd28ab6a
SH		 1887 if (netif_msg_intr(sky2))
1888 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1889 sky2->netdev->name, istatus, phystat);
1890
2eaba1a2 1891 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1892 if (sky2_autoneg_done(sky2, phystat) == 0)
1893 sky2_link_up(sky2);
1894 goto out;
1895 }
cd28ab6a 1896
793b883e
SH		 1897 if (istatus & PHY_M_IS_LSP_CHANGE)
1898 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1899
793b883e
SH		 1900 if (istatus & PHY_M_IS_DUP_CHANGE)
1901 sky2->duplex =
1902 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1903
793b883e
SH		 1904 if (istatus & PHY_M_IS_LST_CHANGE) {
1905 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1906 sky2_link_up(sky2);
793b883e
SH		 1907 else
1908 sky2_link_down(sky2);
cd28ab6a 1909 }
793b883e 1910out:
e07b1aa8 1911 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1912}
1913
62335ab0 1914/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1915 * and tx queue is full (stopped).
1916 */
cd28ab6a
SH		 1917static void sky2_tx_timeout(struct net_device *dev)
1918{
1919 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1920 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1921
1922 if (netif_msg_timer(sky2))
1923 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1924
8f24664d 1925 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1926 dev->name, sky2->tx_cons, sky2->tx_prod,
1927 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1928 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1929
81906791
SH		 1930 /* can't restart safely under softirq */
1931 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1932}
1933
1934static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1935{
6b1a3aef 1936 struct sky2_port *sky2 = netdev_priv(dev);
1937 struct sky2_hw *hw = sky2->hw;
b628ed98 1938 unsigned port = sky2->port;
6b1a3aef 1939 int err;
1940 u16 ctl, mode;
e07b1aa8 1941 u32 imask;
cd28ab6a
SH		 1942
1943 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1944 return -EINVAL;
1945
d2adf4f6
SH		 1946 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1947 return -EINVAL;
1948
6b1a3aef 1949 if (!netif_running(dev)) {
1950 dev->mtu = new_mtu;
1951 return 0;
1952 }
1953
e07b1aa8 1954 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 1955 sky2_write32(hw, B0_IMSK, 0);
1956
018d1c66 1957 dev->trans_start = jiffies; /* prevent tx timeout */
1958 netif_stop_queue(dev);
1959 netif_poll_disable(hw->dev[0]);
1960
e07b1aa8
SH		 1961 synchronize_irq(hw->pdev->irq);
1962
69161611
SH		 1963 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
1964 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 1965
1966 ctl = gma_read16(hw, port, GM_GP_CTRL);
1967 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 1968 sky2_rx_stop(sky2);
1969 sky2_rx_clean(sky2);
cd28ab6a
SH		 1970
1971 dev->mtu = new_mtu;
14d0263f 1972
6b1a3aef 1973 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1974 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1975
1976 if (dev->mtu > ETH_DATA_LEN)
1977 mode |= GM_SMOD_JUMBO_ENA;
1978
b628ed98 1979 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 1980
b628ed98 1981 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1982
6b1a3aef 1983 err = sky2_rx_start(sky2);
e07b1aa8 1984 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1985
1b537565
SH		 1986 if (err)
1987 dev_close(dev);
1988 else {
b628ed98 1989 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565
SH		 1990
1991 netif_poll_enable(hw->dev[0]);
1992 netif_wake_queue(dev);
1993 }
1994
cd28ab6a
SH		 1995 return err;
1996}
1997
14d0263f
SH		 1998/* For small just reuse existing skb for next receive */
1999static struct sk_buff *receive_copy(struct sky2_port *sky2,
2000 const struct rx_ring_info *re,
2001 unsigned length)
2002{
2003 struct sk_buff *skb;
2004
2005 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2006 if (likely(skb)) {
2007 skb_reserve(skb, 2);
2008 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2009 length, PCI_DMA_FROMDEVICE);
d626f62b 2010 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2011 skb->ip_summed = re->skb->ip_summed;
2012 skb->csum = re->skb->csum;
2013 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2014 length, PCI_DMA_FROMDEVICE);
2015 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2016 skb_put(skb, length);
14d0263f
SH		 2017 }
2018 return skb;
2019}
2020
2021/* Adjust length of skb with fragments to match received data */
2022static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2023 unsigned int length)
2024{
2025 int i, num_frags;
2026 unsigned int size;
2027
2028 /* put header into skb */
2029 size = min(length, hdr_space);
2030 skb->tail += size;
2031 skb->len += size;
2032 length -= size;
2033
2034 num_frags = skb_shinfo(skb)->nr_frags;
2035 for (i = 0; i < num_frags; i++) {
2036 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2037
2038 if (length == 0) {
2039 /* don't need this page */
2040 __free_page(frag->page);
2041 --skb_shinfo(skb)->nr_frags;
2042 } else {
2043 size = min(length, (unsigned) PAGE_SIZE);
2044
2045 frag->size = size;
2046 skb->data_len += size;
2047 skb->truesize += size;
2048 skb->len += size;
2049 length -= size;
2050 }
2051 }
2052}
2053
2054/* Normal packet - take skb from ring element and put in a new one */
2055static struct sk_buff *receive_new(struct sky2_port *sky2,
2056 struct rx_ring_info *re,
2057 unsigned int length)
2058{
2059 struct sk_buff *skb, *nskb;
2060 unsigned hdr_space = sky2->rx_data_size;
2061
14d0263f
SH		 2062 /* Don't be tricky about reusing pages (yet) */
2063 nskb = sky2_rx_alloc(sky2);
2064 if (unlikely(!nskb))
2065 return NULL;
2066
2067 skb = re->skb;
2068 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2069
2070 prefetch(skb->data);
2071 re->skb = nskb;
2072 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2073
2074 if (skb_shinfo(skb)->nr_frags)
2075 skb_put_frags(skb, hdr_space, length);
2076 else
489b10c1 2077 skb_put(skb, length);
14d0263f
SH		 2078 return skb;
2079}
2080
cd28ab6a
SH		 2081/*
2082 * Receive one packet.
d571b694 2083 * For larger packets, get new buffer.
cd28ab6a 2084 */
497d7c86 2085static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2086 u16 length, u32 status)
2087{
497d7c86 2088 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2089 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2090 struct sk_buff *skb = NULL;
cd28ab6a
SH		 2091
2092 if (unlikely(netif_msg_rx_status(sky2)))
2093 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2094 dev->name, sky2->rx_next, status, length);
cd28ab6a 2095
793b883e 2096 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2097 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2098
42eeea01 2099 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2100 goto error;
2101
42eeea01 2102 if (!(status & GMR_FS_RX_OK))
2103 goto resubmit;
2104
71749531
SH		 2105 if (status >> 16 != length)
2106 goto len_mismatch;
2107
14d0263f
SH		 2108 if (length < copybreak)
2109 skb = receive_copy(sky2, re, length);
2110 else
2111 skb = receive_new(sky2, re, length);
793b883e 2112resubmit:
14d0263f 2113 sky2_rx_submit(sky2, re);
79e57d32 2114
cd28ab6a
SH		 2115 return skb;
2116
71749531
SH		 2117len_mismatch:
2118 /* Truncation of overlength packets
2119 causes PHY length to not match MAC length */
2120 ++sky2->net_stats.rx_length_errors;
2121
cd28ab6a 2122error:
6e15b712 2123 ++sky2->net_stats.rx_errors;
b6d77734 2124 if (status & GMR_FS_RX_FF_OV) {
a79abdc6 2125 sky2->net_stats.rx_over_errors++;
b6d77734
SH		 2126 goto resubmit;
2127 }
6e15b712 2128
3be92a70 2129 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2130 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2131 dev->name, status, length);
793b883e
SH		 2132
2133 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2134 sky2->net_stats.rx_length_errors++;
2135 if (status & GMR_FS_FRAGMENT)
2136 sky2->net_stats.rx_frame_errors++;
2137 if (status & GMR_FS_CRC_ERR)
2138 sky2->net_stats.rx_crc_errors++;
79e57d32 2139
793b883e 2140 goto resubmit;
cd28ab6a
SH		 2141}
2142
e07b1aa8
SH		 2143/* Transmit complete */
2144static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2145{
e07b1aa8 2146 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2147
e07b1aa8 2148 if (netif_running(dev)) {
2bb8c262 2149 netif_tx_lock(dev);
e07b1aa8 2150 sky2_tx_complete(sky2, last);
2bb8c262 2151 netif_tx_unlock(dev);
2224795d 2152 }
cd28ab6a
SH		 2153}
2154
e07b1aa8
SH		 2155/* Process status response ring */
2156static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2157{
e07b1aa8 2158 int work_done = 0;
55c9dd35 2159 unsigned rx[2] = { 0, 0 };
e71ebd73 2160 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2161
af2a58ac 2162 rmb();
bea86103 2163
e71ebd73 2164 while (hw->st_idx != hwidx) {
55c9dd35 2165 struct sky2_port *sky2;
13210ce5 2166 struct sky2_status_le *le = hw->st_le + hw->st_idx;
69161611 2167 unsigned port = le->css & CSS_LINK_BIT;
13210ce5 2168 struct net_device *dev;
cd28ab6a 2169 struct sk_buff *skb;
cd28ab6a
SH		 2170 u32 status;
2171 u16 length;
2172
cb5d9547 2173 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2174
69161611 2175 dev = hw->dev[port];
13210ce5 2176 sky2 = netdev_priv(dev);
f65b138c
SH		 2177 length = le16_to_cpu(le->length);
2178 status = le32_to_cpu(le->status);
cd28ab6a 2179
e71ebd73 2180 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2181 case OP_RXSTAT:
55c9dd35 2182 ++rx[port];
497d7c86 2183 skb = sky2_receive(dev, length, status);
3225b919
SH		 2184 if (unlikely(!skb)) {
2185 sky2->net_stats.rx_dropped++;
55c9dd35 2186 break;
3225b919 2187 }
13210ce5 2188
69161611
SH		 2189 /* This chip reports checksum status differently */
2190 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2191 if (sky2->rx_csum &&
2192 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2193 (le->css & CSS_TCPUDPCSOK))
2194 skb->ip_summed = CHECKSUM_UNNECESSARY;
2195 else
2196 skb->ip_summed = CHECKSUM_NONE;
2197 }
2198
13210ce5 2199 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2200 sky2->net_stats.rx_packets++;
2201 sky2->net_stats.rx_bytes += skb->len;
13210ce5 2202 dev->last_rx = jiffies;
2203
d1f13708 2204#ifdef SKY2_VLAN_TAG_USED
2205 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2206 vlan_hwaccel_receive_skb(skb,
2207 sky2->vlgrp,
2208 be16_to_cpu(sky2->rx_tag));
2209 } else
2210#endif
cd28ab6a 2211 netif_receive_skb(skb);
13210ce5 2212
22e11703 2213 /* Stop after net poll weight */
13210ce5 2214 if (++work_done >= to_do)
2215 goto exit_loop;
cd28ab6a
SH		 2216 break;
2217
d1f13708 2218#ifdef SKY2_VLAN_TAG_USED
2219 case OP_RXVLAN:
2220 sky2->rx_tag = length;
2221 break;
2222
2223 case OP_RXCHKSVLAN:
2224 sky2->rx_tag = length;
2225 /* fall through */
2226#endif
cd28ab6a 2227 case OP_RXCHKS:
87418307
SH		 2228 if (!sky2->rx_csum)
2229 break;
2230
69161611
SH		 2231 if (hw->chip_id == CHIP_ID_YUKON_EX)
2232 break;
2233
87418307
SH		 2234 /* Both checksum counters are programmed to start at
2235 * the same offset, so unless there is a problem they
2236 * should match. This failure is an early indication that
2237 * hardware receive checksumming won't work.
2238 */
2239 if (likely(status >> 16 == (status & 0xffff))) {
2240 skb = sky2->rx_ring[sky2->rx_next].skb;
2241 skb->ip_summed = CHECKSUM_COMPLETE;
2242 skb->csum = status & 0xffff;
2243 } else {
2244 printk(KERN_NOTICE PFX "%s: hardware receive "
2245 "checksum problem (status = %#x)\n",
2246 dev->name, status);
2247 sky2->rx_csum = 0;
2248 sky2_write32(sky2->hw,
69161611 2249 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2250 BMU_DIS_RX_CHKSUM);
2251 }
cd28ab6a
SH		 2252 break;
2253
2254 case OP_TXINDEXLE:
13b97b74 2255 /* TX index reports status for both ports */
f55925d7
SH		 2256 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2257 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2258 if (hw->dev[1])
2259 sky2_tx_done(hw->dev[1],
2260 ((status >> 24) & 0xff)
2261 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2262 break;
2263
cd28ab6a
SH		 2264 default:
2265 if (net_ratelimit())
793b883e 2266 printk(KERN_WARNING PFX
e71ebd73 2267 "unknown status opcode 0x%x\n", le->opcode);
cd28ab6a 2268 }
13210ce5 2269 }
cd28ab6a 2270
fe2a24df
SH		 2271 /* Fully processed status ring so clear irq */
2272 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2273
13210ce5 2274exit_loop:
55c9dd35
SH		 2275 if (rx[0])
2276 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2277
55c9dd35
SH		 2278 if (rx[1])
2279 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2280
e07b1aa8 2281 return work_done;
cd28ab6a
SH		 2282}
2283
2284static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2285{
2286 struct net_device *dev = hw->dev[port];
2287
3be92a70
SH		 2288 if (net_ratelimit())
2289 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2290 dev->name, status);
cd28ab6a
SH		 2291
2292 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2293 if (net_ratelimit())
2294 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2295 dev->name);
cd28ab6a
SH		 2296 /* Clear IRQ */
2297 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2298 }
2299
2300 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2301 if (net_ratelimit())
2302 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2303 dev->name);
cd28ab6a
SH		 2304
2305 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2306 }
2307
2308 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2309 if (net_ratelimit())
2310 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2311 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2312 }
2313
2314 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2315 if (net_ratelimit())
2316 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2317 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2318 }
2319
2320 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2321 if (net_ratelimit())
2322 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2323 dev->name);
cd28ab6a
SH		 2324 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2325 }
2326}
2327
2328static void sky2_hw_intr(struct sky2_hw *hw)
2329{
2330 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2331
793b883e 2332 if (status & Y2_IS_TIST_OV)
cd28ab6a 2333 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2334
2335 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2336 u16 pci_err;
2337
56a645cc 2338 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2339 if (net_ratelimit())
b02a9258
SH		 2340 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2341 pci_err);
cd28ab6a
SH		 2342
2343 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2344 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2345 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2346 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2347 }
2348
2349 if (status & Y2_IS_PCI_EXP) {
d571b694 2350 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2351 u32 pex_err;
2352
7bd656d1 2353 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2354
3be92a70 2355 if (net_ratelimit())
b02a9258
SH		 2356 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2357 pex_err);
cd28ab6a
SH		 2358
2359 /* clear the interrupt */
2360 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2361 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2362 0xffffffffUL);
cd28ab6a
SH		 2363 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2364
7bd656d1 2365 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2366 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2367 hwmsk &= ~Y2_IS_PCI_EXP;
2368 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2369 }
2370 }
2371
2372 if (status & Y2_HWE_L1_MASK)
2373 sky2_hw_error(hw, 0, status);
2374 status >>= 8;
2375 if (status & Y2_HWE_L1_MASK)
2376 sky2_hw_error(hw, 1, status);
2377}
2378
2379static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2380{
2381 struct net_device *dev = hw->dev[port];
2382 struct sky2_port *sky2 = netdev_priv(dev);
2383 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2384
2385 if (netif_msg_intr(sky2))
2386 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2387 dev->name, status);
2388
a3caeada
SH		 2389 if (status & GM_IS_RX_CO_OV)
2390 gma_read16(hw, port, GM_RX_IRQ_SRC);
2391
2392 if (status & GM_IS_TX_CO_OV)
2393 gma_read16(hw, port, GM_TX_IRQ_SRC);
2394
cd28ab6a
SH		 2395 if (status & GM_IS_RX_FF_OR) {
2396 ++sky2->net_stats.rx_fifo_errors;
2397 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2398 }
2399
2400 if (status & GM_IS_TX_FF_UR) {
2401 ++sky2->net_stats.tx_fifo_errors;
2402 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2403 }
cd28ab6a
SH		 2404}
2405
40b01727
SH		 2406/* This should never happen it is a bug. */
2407static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2408 u16 q, unsigned ring_size)
d257924e
SH		 2409{
2410 struct net_device *dev = hw->dev[port];
2411 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2412 unsigned idx;
2413 const u64 *le = (q == Q_R1 || q == Q_R2)
2414 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2415
40b01727
SH		 2416 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2417 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2418 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2419 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2420
40b01727 2421 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2422}
cd28ab6a 2423
d27ed387
SH		 2424/* If idle then force a fake soft NAPI poll once a second
2425 * to work around cases where sharing an edge triggered interrupt.
2426 */
eb35cf60
SH		 2427static inline void sky2_idle_start(struct sky2_hw *hw)
2428{
2429 if (idle_timeout > 0)
2430 mod_timer(&hw->idle_timer,
2431 jiffies + msecs_to_jiffies(idle_timeout));
2432}
2433
d27ed387
SH		 2434static void sky2_idle(unsigned long arg)
2435{
01bd7564
SH		 2436 struct sky2_hw *hw = (struct sky2_hw *) arg;
2437 struct net_device *dev = hw->dev[0];
d27ed387 2438
d27ed387
SH		 2439 if (__netif_rx_schedule_prep(dev))
2440 __netif_rx_schedule(dev);
01bd7564
SH		 2441
2442 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2443}
2444
40b01727
SH		 2445/* Hardware/software error handling */
2446static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2447{
40b01727
SH		 2448 if (net_ratelimit())
2449 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2450
1e5f1283
SH		 2451 if (status & Y2_IS_HW_ERR)
2452 sky2_hw_intr(hw);
d257924e 2453
1e5f1283
SH		 2454 if (status & Y2_IS_IRQ_MAC1)
2455 sky2_mac_intr(hw, 0);
cd28ab6a 2456
1e5f1283
SH		 2457 if (status & Y2_IS_IRQ_MAC2)
2458 sky2_mac_intr(hw, 1);
cd28ab6a 2459
1e5f1283 2460 if (status & Y2_IS_CHK_RX1)
40b01727 2461 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2462
1e5f1283 2463 if (status & Y2_IS_CHK_RX2)
40b01727 2464 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2465
1e5f1283 2466 if (status & Y2_IS_CHK_TXA1)
40b01727 2467 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2468
1e5f1283 2469 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2470 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2471}
2472
2473static int sky2_poll(struct net_device *dev0, int *budget)
2474{
2475 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
5c11ce70 2476 int work_done;
40b01727
SH		 2477 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2478
2479 if (unlikely(status & Y2_IS_ERROR))
2480 sky2_err_intr(hw, status);
2481
2482 if (status & Y2_IS_IRQ_PHY1)
2483 sky2_phy_intr(hw, 0);
2484
2485 if (status & Y2_IS_IRQ_PHY2)
2486 sky2_phy_intr(hw, 1);
cd28ab6a 2487
5c11ce70
SH		 2488 work_done = sky2_status_intr(hw, min(dev0->quota, *budget));
2489 *budget -= work_done;
2490 dev0->quota -= work_done;
86fba634 2491
5c11ce70
SH		 2492 /* More work? */
2493 if (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX))
1e5f1283 2494 return 1;
5c11ce70
SH		 2495
2496 /* Bug/Errata workaround?
2497 * Need to kick the TX irq moderation timer.
2498 */
2499 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2500 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2501 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2502 }
5c11ce70
SH		 2503 netif_rx_complete(dev0);
2504
2505 sky2_read32(hw, B0_Y2_SP_LISR);
2506 return 0;
e07b1aa8
SH		 2507}
2508
7d12e780 2509static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2510{
2511 struct sky2_hw *hw = dev_id;
2512 struct net_device *dev0 = hw->dev[0];
2513 u32 status;
2514
2515 /* Reading this mask interrupts as side effect */
2516 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2517 if (status == 0 || status == ~0)
2518 return IRQ_NONE;
793b883e 2519
e07b1aa8
SH		 2520 prefetch(&hw->st_le[hw->st_idx]);
2521 if (likely(__netif_rx_schedule_prep(dev0)))
2522 __netif_rx_schedule(dev0);
793b883e 2523
cd28ab6a
SH		 2524 return IRQ_HANDLED;
2525}
2526
2527#ifdef CONFIG_NET_POLL_CONTROLLER
2528static void sky2_netpoll(struct net_device *dev)
2529{
2530 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2531 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2532
88d11360
SH		 2533 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2534 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2535}
2536#endif
2537
2538/* Chip internal frequency for clock calculations */
fb17358f 2539static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2540{
793b883e 2541 switch (hw->chip_id) {
cd28ab6a 2542 case CHIP_ID_YUKON_EC:
5a5b1ea0 2543 case CHIP_ID_YUKON_EC_U:
93745494 2544 case CHIP_ID_YUKON_EX:
fb17358f 2545 return 125; /* 125 Mhz */
cd28ab6a 2546 case CHIP_ID_YUKON_FE:
fb17358f 2547 return 100; /* 100 Mhz */
793b883e 2548 default: /* YUKON_XL */
fb17358f 2549 return 156; /* 156 Mhz */
cd28ab6a
SH		 2550 }
2551}
2552
fb17358f 2553static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2554{
fb17358f 2555 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2556}
2557
fb17358f 2558static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2559{
fb17358f 2560 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2561}
2562
fb17358f 2563
e3173832 2564static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2565{
b89165f2 2566 u8 t8;
cd28ab6a 2567
451af335
SH		 2568 /* Enable all clocks */
2569 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2570
cd28ab6a 2571 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2572
cd28ab6a
SH		 2573 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2574 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
b02a9258
SH		 2575 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2576 hw->chip_id);
cd28ab6a
SH		 2577 return -EOPNOTSUPP;
2578 }
2579
290d4de5
SH		 2580 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2581
2582 /* This rev is really old, and requires untested workarounds */
2583 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
b02a9258
SH		 2584 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2585 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2586 hw->chip_id, hw->chip_rev);
290d4de5
SH		 2587 return -EOPNOTSUPP;
2588 }
2589
e3173832
SH		 2590 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2591 hw->ports = 1;
2592 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2593 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2594 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2595 ++hw->ports;
2596 }
2597
2598 return 0;
2599}
2600
2601static void sky2_reset(struct sky2_hw *hw)
2602{
2603 u16 status;
2604 int i;
2605
cd28ab6a 2606 /* disable ASF */
4f44d8ba
SH		 2607 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2608 status = sky2_read16(hw, HCU_CCSR);
2609 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2610 HCU_CCSR_UC_STATE_MSK);
2611 sky2_write16(hw, HCU_CCSR, status);
2612 } else
2613 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2614 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2615
2616 /* do a SW reset */
2617 sky2_write8(hw, B0_CTST, CS_RST_SET);
2618 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2619
2620 /* clear PCI errors, if any */
56a645cc 2621 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2622
cd28ab6a 2623 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2624 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2625
cd28ab6a
SH		 2626
2627 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2628
2629 /* clear any PEX errors */
7bd656d1
SH		 2630 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2631 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2632
cd28ab6a 2633
ae306cca 2634 sky2_power_on(hw);
cd28ab6a
SH		 2635
2636 for (i = 0; i < hw->ports; i++) {
2637 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2638 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611
SH		 2639
2640 if (hw->chip_id == CHIP_ID_YUKON_EX)
2641 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2642 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2643 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2644 }
2645
2646 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2647
793b883e
SH		 2648 /* Clear I2C IRQ noise */
2649 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2650
2651 /* turn off hardware timer (unused) */
2652 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2653 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2654
cd28ab6a
SH		 2655 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2656
69634ee7
SH		 2657 /* Turn off descriptor polling */
2658 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2659
2660 /* Turn off receive timestamp */
2661 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2662 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2663
2664 /* enable the Tx Arbiters */
2665 for (i = 0; i < hw->ports; i++)
2666 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2667
2668 /* Initialize ram interface */
2669 for (i = 0; i < hw->ports; i++) {
793b883e 2670 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2671
2672 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2673 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2674 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2675 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2676 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2677 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2678 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2679 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2680 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2681 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2682 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2683 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2684 }
2685
7bd656d1 2686 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2687
cd28ab6a 2688 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2689 sky2_gmac_reset(hw, i);
cd28ab6a 2690
cd28ab6a
SH		 2691 memset(hw->st_le, 0, STATUS_LE_BYTES);
2692 hw->st_idx = 0;
2693
2694 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2695 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2696
2697 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2698 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2699
2700 /* Set the list last index */
793b883e 2701 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2702
290d4de5
SH		 2703 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2704 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2705
290d4de5
SH		 2706 /* set Status-FIFO ISR watermark */
2707 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2708 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2709 else
2710 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2711
290d4de5 2712 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2713 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2714 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2715
793b883e 2716 /* enable status unit */
cd28ab6a
SH		 2717 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2718
2719 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2720 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2721 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2722}
2723
81906791
SH		 2724static void sky2_restart(struct work_struct *work)
2725{
2726 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2727 struct net_device *dev;
2728 int i, err;
2729
81906791
SH		 2730 del_timer_sync(&hw->idle_timer);
2731
2732 rtnl_lock();
2733 sky2_write32(hw, B0_IMSK, 0);
2734 sky2_read32(hw, B0_IMSK);
2735
2736 netif_poll_disable(hw->dev[0]);
2737
2738 for (i = 0; i < hw->ports; i++) {
2739 dev = hw->dev[i];
2740 if (netif_running(dev))
2741 sky2_down(dev);
2742 }
2743
2744 sky2_reset(hw);
2745 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2746 netif_poll_enable(hw->dev[0]);
2747
2748 for (i = 0; i < hw->ports; i++) {
2749 dev = hw->dev[i];
2750 if (netif_running(dev)) {
2751 err = sky2_up(dev);
2752 if (err) {
2753 printk(KERN_INFO PFX "%s: could not restart %d\n",
2754 dev->name, err);
2755 dev_close(dev);
2756 }
2757 }
2758 }
2759
2760 sky2_idle_start(hw);
2761
2762 rtnl_unlock();
2763}
2764
e3173832
SH		 2765static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2766{
2767 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2768}
2769
2770static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2771{
2772 const struct sky2_port *sky2 = netdev_priv(dev);
2773
2774 wol->supported = sky2_wol_supported(sky2->hw);
2775 wol->wolopts = sky2->wol;
2776}
2777
2778static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2779{
2780 struct sky2_port *sky2 = netdev_priv(dev);
2781 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2782
e3173832
SH		 2783 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2784 return -EOPNOTSUPP;
2785
2786 sky2->wol = wol->wolopts;
2787
69161611 2788 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
e3173832
SH		 2789 sky2_write32(hw, B0_CTST, sky2->wol
2790 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2791
2792 if (!netif_running(dev))
2793 sky2_wol_init(sky2);
cd28ab6a
SH		 2794 return 0;
2795}
2796
28bd181a 2797static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2798{
b89165f2
SH		 2799 if (sky2_is_copper(hw)) {
2800 u32 modes = SUPPORTED_10baseT_Half
2801 | SUPPORTED_10baseT_Full
2802 | SUPPORTED_100baseT_Half
2803 | SUPPORTED_100baseT_Full
2804 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2805
2806 if (hw->chip_id != CHIP_ID_YUKON_FE)
2807 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2808 | SUPPORTED_1000baseT_Full;
2809 return modes;
cd28ab6a 2810 } else
b89165f2
SH		 2811 return SUPPORTED_1000baseT_Half
2812 | SUPPORTED_1000baseT_Full
2813 | SUPPORTED_Autoneg
2814 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2815}
2816
793b883e 2817static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2818{
2819 struct sky2_port *sky2 = netdev_priv(dev);
2820 struct sky2_hw *hw = sky2->hw;
2821
2822 ecmd->transceiver = XCVR_INTERNAL;
2823 ecmd->supported = sky2_supported_modes(hw);
2824 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2825 if (sky2_is_copper(hw)) {
cd28ab6a 2826 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2827 | SUPPORTED_10baseT_Full
2828 | SUPPORTED_100baseT_Half
2829 | SUPPORTED_100baseT_Full
2830 | SUPPORTED_1000baseT_Half
2831 | SUPPORTED_1000baseT_Full
2832 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2833 ecmd->port = PORT_TP;
b89165f2
SH		 2834 ecmd->speed = sky2->speed;
2835 } else {
2836 ecmd->speed = SPEED_1000;
cd28ab6a 2837 ecmd->port = PORT_FIBRE;
b89165f2 2838 }
cd28ab6a
SH		 2839
2840 ecmd->advertising = sky2->advertising;
2841 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2842 ecmd->duplex = sky2->duplex;
2843 return 0;
2844}
2845
2846static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2847{
2848 struct sky2_port *sky2 = netdev_priv(dev);
2849 const struct sky2_hw *hw = sky2->hw;
2850 u32 supported = sky2_supported_modes(hw);
2851
2852 if (ecmd->autoneg == AUTONEG_ENABLE) {
2853 ecmd->advertising = supported;
2854 sky2->duplex = -1;
2855 sky2->speed = -1;
2856 } else {
2857 u32 setting;
2858
793b883e 2859 switch (ecmd->speed) {
cd28ab6a
SH		 2860 case SPEED_1000:
2861 if (ecmd->duplex == DUPLEX_FULL)
2862 setting = SUPPORTED_1000baseT_Full;
2863 else if (ecmd->duplex == DUPLEX_HALF)
2864 setting = SUPPORTED_1000baseT_Half;
2865 else
2866 return -EINVAL;
2867 break;
2868 case SPEED_100:
2869 if (ecmd->duplex == DUPLEX_FULL)
2870 setting = SUPPORTED_100baseT_Full;
2871 else if (ecmd->duplex == DUPLEX_HALF)
2872 setting = SUPPORTED_100baseT_Half;
2873 else
2874 return -EINVAL;
2875 break;
2876
2877 case SPEED_10:
2878 if (ecmd->duplex == DUPLEX_FULL)
2879 setting = SUPPORTED_10baseT_Full;
2880 else if (ecmd->duplex == DUPLEX_HALF)
2881 setting = SUPPORTED_10baseT_Half;
2882 else
2883 return -EINVAL;
2884 break;
2885 default:
2886 return -EINVAL;
2887 }
2888
2889 if ((setting & supported) == 0)
2890 return -EINVAL;
2891
2892 sky2->speed = ecmd->speed;
2893 sky2->duplex = ecmd->duplex;
2894 }
2895
2896 sky2->autoneg = ecmd->autoneg;
2897 sky2->advertising = ecmd->advertising;
2898
1b537565
SH		 2899 if (netif_running(dev))
2900 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2901
2902 return 0;
2903}
2904
2905static void sky2_get_drvinfo(struct net_device *dev,
2906 struct ethtool_drvinfo *info)
2907{
2908 struct sky2_port *sky2 = netdev_priv(dev);
2909
2910 strcpy(info->driver, DRV_NAME);
2911 strcpy(info->version, DRV_VERSION);
2912 strcpy(info->fw_version, "N/A");
2913 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2914}
2915
2916static const struct sky2_stat {
793b883e
SH		 2917 char name[ETH_GSTRING_LEN];
2918 u16 offset;
cd28ab6a
SH		 2919} sky2_stats[] = {
2920 { "tx_bytes", GM_TXO_OK_HI },
2921 { "rx_bytes", GM_RXO_OK_HI },
2922 { "tx_broadcast", GM_TXF_BC_OK },
2923 { "rx_broadcast", GM_RXF_BC_OK },
2924 { "tx_multicast", GM_TXF_MC_OK },
2925 { "rx_multicast", GM_RXF_MC_OK },
2926 { "tx_unicast", GM_TXF_UC_OK },
2927 { "rx_unicast", GM_RXF_UC_OK },
2928 { "tx_mac_pause", GM_TXF_MPAUSE },
2929 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2930 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2931 { "late_collision",GM_TXF_LAT_COL },
2932 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2933 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2934 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2935
d2604540 2936 { "rx_short", GM_RXF_SHT },
cd28ab6a 2937 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2938 { "rx_64_byte_packets", GM_RXF_64B },
2939 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2940 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2941 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2942 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2943 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2944 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2945 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2946 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2947 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2948 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2949
2950 { "tx_64_byte_packets", GM_TXF_64B },
2951 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2952 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2953 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2954 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2955 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2956 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2957 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2958};
2959
cd28ab6a
SH		 2960static u32 sky2_get_rx_csum(struct net_device *dev)
2961{
2962 struct sky2_port *sky2 = netdev_priv(dev);
2963
2964 return sky2->rx_csum;
2965}
2966
2967static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2968{
2969 struct sky2_port *sky2 = netdev_priv(dev);
2970
2971 sky2->rx_csum = data;
793b883e 2972
cd28ab6a
SH		 2973 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2974 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2975
2976 return 0;
2977}
2978
2979static u32 sky2_get_msglevel(struct net_device *netdev)
2980{
2981 struct sky2_port *sky2 = netdev_priv(netdev);
2982 return sky2->msg_enable;
2983}
2984
9a7ae0a9
SH		 2985static int sky2_nway_reset(struct net_device *dev)
2986{
2987 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2988
16ad91e1 2989 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2990 return -EINVAL;
2991
1b537565 2992 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2993
2994 return 0;
2995}
2996
793b883e 2997static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2998{
2999 struct sky2_hw *hw = sky2->hw;
3000 unsigned port = sky2->port;
3001 int i;
3002
3003 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3004 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3005 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3006 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3007
793b883e 3008 for (i = 2; i < count; i++)
cd28ab6a
SH		 3009 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3010}
3011
cd28ab6a
SH		 3012static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3013{
3014 struct sky2_port *sky2 = netdev_priv(netdev);
3015 sky2->msg_enable = value;
3016}
3017
3018static int sky2_get_stats_count(struct net_device *dev)
3019{
3020 return ARRAY_SIZE(sky2_stats);
3021}
3022
3023static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3024 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3025{
3026 struct sky2_port *sky2 = netdev_priv(dev);
3027
793b883e 3028 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3029}
3030
793b883e 3031static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3032{
3033 int i;
3034
3035 switch (stringset) {
3036 case ETH_SS_STATS:
3037 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3038 memcpy(data + i * ETH_GSTRING_LEN,
3039 sky2_stats[i].name, ETH_GSTRING_LEN);
3040 break;
3041 }
3042}
3043
cd28ab6a
SH		 3044static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3045{
3046 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3047 return &sky2->net_stats;
3048}
3049
3050static int sky2_set_mac_address(struct net_device *dev, void *p)
3051{
3052 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3053 struct sky2_hw *hw = sky2->hw;
3054 unsigned port = sky2->port;
3055 const struct sockaddr *addr = p;
cd28ab6a
SH		 3056
3057 if (!is_valid_ether_addr(addr->sa_data))
3058 return -EADDRNOTAVAIL;
3059
cd28ab6a 3060 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3061 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3062 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3063 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3064 dev->dev_addr, ETH_ALEN);
1b537565 3065
a8ab1ec0
SH		 3066 /* virtual address for data */
3067 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3068
3069 /* physical address: used for pause frames */
3070 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3071
3072 return 0;
cd28ab6a
SH		 3073}
3074
a052b52f
SH		 3075static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3076{
3077 u32 bit;
3078
3079 bit = ether_crc(ETH_ALEN, addr) & 63;
3080 filter[bit >> 3] |= 1 << (bit & 7);
3081}
3082
cd28ab6a
SH		 3083static void sky2_set_multicast(struct net_device *dev)
3084{
3085 struct sky2_port *sky2 = netdev_priv(dev);
3086 struct sky2_hw *hw = sky2->hw;
3087 unsigned port = sky2->port;
3088 struct dev_mc_list *list = dev->mc_list;
3089 u16 reg;
3090 u8 filter[8];
a052b52f
SH		 3091 int rx_pause;
3092 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3093
a052b52f 3094 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3095 memset(filter, 0, sizeof(filter));
3096
3097 reg = gma_read16(hw, port, GM_RX_CTRL);
3098 reg |= GM_RXCR_UCF_ENA;
3099
d571b694 3100 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3101 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3102 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3103 memset(filter, 0xff, sizeof(filter));
a052b52f 3104 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3105 reg &= ~GM_RXCR_MCF_ENA;
3106 else {
3107 int i;
3108 reg |= GM_RXCR_MCF_ENA;
3109
a052b52f
SH		 3110 if (rx_pause)
3111 sky2_add_filter(filter, pause_mc_addr);
3112
3113 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3114 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3115 }
3116
cd28ab6a 3117 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3118 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3119 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3120 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3121 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3122 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3123 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3124 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3125
3126 gma_write16(hw, port, GM_RX_CTRL, reg);
3127}
3128
3129/* Can have one global because blinking is controlled by
3130 * ethtool and that is always under RTNL mutex
3131 */
91c86df5 3132static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3133{
793b883e
SH		 3134 u16 pg;
3135
793b883e
SH		 3136 switch (hw->chip_id) {
3137 case CHIP_ID_YUKON_XL:
3138 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3139 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3140 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3141 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3142 PHY_M_LEDC_INIT_CTRL(7) |
3143 PHY_M_LEDC_STA1_CTRL(7) |
3144 PHY_M_LEDC_STA0_CTRL(7))
3145 : 0);
3146
3147 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3148 break;
3149
3150 default:
3151 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3152 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3153 on ? PHY_M_LED_ALL : 0);
793b883e 3154 }
cd28ab6a
SH		 3155}
3156
3157/* blink LED's for finding board */
3158static int sky2_phys_id(struct net_device *dev, u32 data)
3159{
3160 struct sky2_port *sky2 = netdev_priv(dev);
3161 struct sky2_hw *hw = sky2->hw;
3162 unsigned port = sky2->port;
793b883e 3163 u16 ledctrl, ledover = 0;
cd28ab6a 3164 long ms;
91c86df5 3165 int interrupted;
cd28ab6a
SH		 3166 int onoff = 1;
3167
793b883e 3168 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3169 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3170 else
3171 ms = data * 1000;
3172
3173 /* save initial values */
e07b1aa8 3174 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3175 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3176 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3177 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3178 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3179 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3180 } else {
3181 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3182 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3183 }
cd28ab6a 3184
91c86df5
SH		 3185 interrupted = 0;
3186 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3187 sky2_led(hw, port, onoff);
3188 onoff = !onoff;
3189
e07b1aa8 3190 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3191 interrupted = msleep_interruptible(250);
e07b1aa8 3192 spin_lock_bh(&sky2->phy_lock);
91c86df5 3193
cd28ab6a
SH		 3194 ms -= 250;
3195 }
3196
3197 /* resume regularly scheduled programming */
793b883e
SH		 3198 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3199 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3200 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3201 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3202 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3203 } else {
3204 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3205 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3206 }
e07b1aa8 3207 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3208
3209 return 0;
3210}
3211
3212static void sky2_get_pauseparam(struct net_device *dev,
3213 struct ethtool_pauseparam *ecmd)
3214{
3215 struct sky2_port *sky2 = netdev_priv(dev);
3216
16ad91e1
SH		 3217 switch (sky2->flow_mode) {
3218 case FC_NONE:
3219 ecmd->tx_pause = ecmd->rx_pause = 0;
3220 break;
3221 case FC_TX:
3222 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3223 break;
3224 case FC_RX:
3225 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3226 break;
3227 case FC_BOTH:
3228 ecmd->tx_pause = ecmd->rx_pause = 1;
3229 }
3230
cd28ab6a
SH		 3231 ecmd->autoneg = sky2->autoneg;
3232}
3233
3234static int sky2_set_pauseparam(struct net_device *dev,
3235 struct ethtool_pauseparam *ecmd)
3236{
3237 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3238
3239 sky2->autoneg = ecmd->autoneg;
16ad91e1 3240 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3241
16ad91e1
SH		 3242 if (netif_running(dev))
3243 sky2_phy_reinit(sky2);
cd28ab6a 3244
2eaba1a2 3245 return 0;
cd28ab6a
SH		 3246}
3247
fb17358f
SH		 3248static int sky2_get_coalesce(struct net_device *dev,
3249 struct ethtool_coalesce *ecmd)
3250{
3251 struct sky2_port *sky2 = netdev_priv(dev);
3252 struct sky2_hw *hw = sky2->hw;
3253
3254 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3255 ecmd->tx_coalesce_usecs = 0;
3256 else {
3257 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3258 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3259 }
3260 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3261
3262 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3263 ecmd->rx_coalesce_usecs = 0;
3264 else {
3265 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3266 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3267 }
3268 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3269
3270 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3271 ecmd->rx_coalesce_usecs_irq = 0;
3272 else {
3273 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3274 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3275 }
3276
3277 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3278
3279 return 0;
3280}
3281
3282/* Note: this affect both ports */
3283static int sky2_set_coalesce(struct net_device *dev,
3284 struct ethtool_coalesce *ecmd)
3285{
3286 struct sky2_port *sky2 = netdev_priv(dev);
3287 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3288 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3289
77b3d6a2
SH		 3290 if (ecmd->tx_coalesce_usecs > tmax ||
3291 ecmd->rx_coalesce_usecs > tmax ||
3292 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3293 return -EINVAL;
3294
ff81fbbe 3295 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3296 return -EINVAL;
ff81fbbe 3297 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3298 return -EINVAL;
ff81fbbe 3299 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3300 return -EINVAL;
3301
3302 if (ecmd->tx_coalesce_usecs == 0)
3303 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3304 else {
3305 sky2_write32(hw, STAT_TX_TIMER_INI,
3306 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3307 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3308 }
3309 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3310
3311 if (ecmd->rx_coalesce_usecs == 0)
3312 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3313 else {
3314 sky2_write32(hw, STAT_LEV_TIMER_INI,
3315 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3316 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3317 }
3318 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3319
3320 if (ecmd->rx_coalesce_usecs_irq == 0)
3321 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3322 else {
d28d4870 3323 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3324 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3325 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3326 }
3327 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3328 return 0;
3329}
3330
793b883e
SH		 3331static void sky2_get_ringparam(struct net_device *dev,
3332 struct ethtool_ringparam *ering)
3333{
3334 struct sky2_port *sky2 = netdev_priv(dev);
3335
3336 ering->rx_max_pending = RX_MAX_PENDING;
3337 ering->rx_mini_max_pending = 0;
3338 ering->rx_jumbo_max_pending = 0;
3339 ering->tx_max_pending = TX_RING_SIZE - 1;
3340
3341 ering->rx_pending = sky2->rx_pending;
3342 ering->rx_mini_pending = 0;
3343 ering->rx_jumbo_pending = 0;
3344 ering->tx_pending = sky2->tx_pending;
3345}
3346
3347static int sky2_set_ringparam(struct net_device *dev,
3348 struct ethtool_ringparam *ering)
3349{
3350 struct sky2_port *sky2 = netdev_priv(dev);
3351 int err = 0;
3352
3353 if (ering->rx_pending > RX_MAX_PENDING ||
3354 ering->rx_pending < 8 ||
3355 ering->tx_pending < MAX_SKB_TX_LE ||
3356 ering->tx_pending > TX_RING_SIZE - 1)
3357 return -EINVAL;
3358
3359 if (netif_running(dev))
3360 sky2_down(dev);
3361
3362 sky2->rx_pending = ering->rx_pending;
3363 sky2->tx_pending = ering->tx_pending;
3364
1b537565 3365 if (netif_running(dev)) {
793b883e 3366 err = sky2_up(dev);
1b537565
SH		 3367 if (err)
3368 dev_close(dev);
6ed995bb
SH		 3369 else
3370 sky2_set_multicast(dev);
1b537565 3371 }
793b883e
SH		 3372
3373 return err;
3374}
3375
793b883e
SH		 3376static int sky2_get_regs_len(struct net_device *dev)
3377{
6e4cbb34 3378 return 0x4000;
793b883e
SH		 3379}
3380
3381/*
3382 * Returns copy of control register region
3ead5db7 3383 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3384 */
3385static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3386 void *p)
3387{
3388 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3389 const void __iomem *io = sky2->hw->regs;
793b883e
SH		 3390
3391 regs->version = 1;
6e4cbb34 3392 memset(p, 0, regs->len);
793b883e 3393
6e4cbb34
SH		 3394 memcpy_fromio(p, io, B3_RAM_ADDR);
3395
3ead5db7
SH		 3396 /* skip diagnostic ram region */
3397 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 0x2000 - B3_RI_WTO_R1);
3398
3399 /* copy GMAC registers */
3400 memcpy_fromio(p + BASE_GMAC_1, io + BASE_GMAC_1, 0x1000);
3401 if (sky2->hw->ports > 1)
3402 memcpy_fromio(p + BASE_GMAC_2, io + BASE_GMAC_2, 0x1000);
3403
793b883e 3404}
cd28ab6a 3405
b628ed98
SH		 3406/* In order to do Jumbo packets on these chips, need to turn off the
3407 * transmit store/forward. Therefore checksum offload won't work.
3408 */
3409static int no_tx_offload(struct net_device *dev)
3410{
3411 const struct sky2_port *sky2 = netdev_priv(dev);
3412 const struct sky2_hw *hw = sky2->hw;
3413
69161611 3414 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3415}
3416
3417static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3418{
3419 if (data && no_tx_offload(dev))
3420 return -EINVAL;
3421
3422 return ethtool_op_set_tx_csum(dev, data);
3423}
3424
3425
3426static int sky2_set_tso(struct net_device *dev, u32 data)
3427{
3428 if (data && no_tx_offload(dev))
3429 return -EINVAL;
3430
3431 return ethtool_op_set_tso(dev, data);
3432}
3433
f4331a6d
SH		 3434static int sky2_get_eeprom_len(struct net_device *dev)
3435{
3436 struct sky2_port *sky2 = netdev_priv(dev);
3437 u16 reg2;
3438
3439 reg2 = sky2_pci_read32(sky2->hw, PCI_DEV_REG2);
3440 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3441}
3442
3443static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3444{
3445 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3446
3447 while (!(sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F))
3448 cpu_relax();
3449 return sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3450}
3451
3452static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3453{
3454 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3455 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3456 do {
3457 cpu_relax();
3458 } while (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F);
3459}
3460
3461static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3462 u8 *data)
3463{
3464 struct sky2_port *sky2 = netdev_priv(dev);
3465 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3466 int length = eeprom->len;
3467 u16 offset = eeprom->offset;
3468
3469 if (!cap)
3470 return -EINVAL;
3471
3472 eeprom->magic = SKY2_EEPROM_MAGIC;
3473
3474 while (length > 0) {
3475 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3476 int n = min_t(int, length, sizeof(val));
3477
3478 memcpy(data, &val, n);
3479 length -= n;
3480 data += n;
3481 offset += n;
3482 }
3483 return 0;
3484}
3485
3486static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3487 u8 *data)
3488{
3489 struct sky2_port *sky2 = netdev_priv(dev);
3490 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3491 int length = eeprom->len;
3492 u16 offset = eeprom->offset;
3493
3494 if (!cap)
3495 return -EINVAL;
3496
3497 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3498 return -EINVAL;
3499
3500 while (length > 0) {
3501 u32 val;
3502 int n = min_t(int, length, sizeof(val));
3503
3504 if (n < sizeof(val))
3505 val = sky2_vpd_read(sky2->hw, cap, offset);
3506 memcpy(&val, data, n);
3507
3508 sky2_vpd_write(sky2->hw, cap, offset, val);
3509
3510 length -= n;
3511 data += n;
3512 offset += n;
3513 }
3514 return 0;
3515}
3516
3517
7282d491 3518static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3519 .get_settings = sky2_get_settings,
3520 .set_settings = sky2_set_settings,
3521 .get_drvinfo = sky2_get_drvinfo,
3522 .get_wol = sky2_get_wol,
3523 .set_wol = sky2_set_wol,
3524 .get_msglevel = sky2_get_msglevel,
3525 .set_msglevel = sky2_set_msglevel,
3526 .nway_reset = sky2_nway_reset,
3527 .get_regs_len = sky2_get_regs_len,
3528 .get_regs = sky2_get_regs,
3529 .get_link = ethtool_op_get_link,
3530 .get_eeprom_len = sky2_get_eeprom_len,
3531 .get_eeprom = sky2_get_eeprom,
3532 .set_eeprom = sky2_set_eeprom,
3533 .get_sg = ethtool_op_get_sg,
3534 .set_sg = ethtool_op_set_sg,
3535 .get_tx_csum = ethtool_op_get_tx_csum,
3536 .set_tx_csum = sky2_set_tx_csum,
3537 .get_tso = ethtool_op_get_tso,
3538 .set_tso = sky2_set_tso,
3539 .get_rx_csum = sky2_get_rx_csum,
3540 .set_rx_csum = sky2_set_rx_csum,
3541 .get_strings = sky2_get_strings,
3542 .get_coalesce = sky2_get_coalesce,
3543 .set_coalesce = sky2_set_coalesce,
3544 .get_ringparam = sky2_get_ringparam,
3545 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3546 .get_pauseparam = sky2_get_pauseparam,
3547 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3548 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3549 .get_stats_count = sky2_get_stats_count,
3550 .get_ethtool_stats = sky2_get_ethtool_stats,
3551};
3552
3cf26753
SH		 3553#ifdef CONFIG_SKY2_DEBUG
3554
3555static struct dentry *sky2_debug;
3556
3557static int sky2_debug_show(struct seq_file *seq, void *v)
3558{
3559 struct net_device *dev = seq->private;
3560 const struct sky2_port *sky2 = netdev_priv(dev);
3561 const struct sky2_hw *hw = sky2->hw;
3562 unsigned port = sky2->port;
3563 unsigned idx, last;
3564 int sop;
3565
3566 if (!netif_running(dev))
3567 return -ENETDOWN;
3568
3569 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3570 sky2_read32(hw, B0_ISRC),
3571 sky2_read32(hw, B0_IMSK),
3572 sky2_read32(hw, B0_Y2_SP_ICR));
3573
3574 netif_poll_disable(hw->dev[0]);
3575 last = sky2_read16(hw, STAT_PUT_IDX);
3576
3577 if (hw->st_idx == last)
3578 seq_puts(seq, "Status ring (empty)\n");
3579 else {
3580 seq_puts(seq, "Status ring\n");
3581 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3582 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3583 const struct sky2_status_le *le = hw->st_le + idx;
3584 seq_printf(seq, "[%d] %#x %d %#x\n",
3585 idx, le->opcode, le->length, le->status);
3586 }
3587 seq_puts(seq, "\n");
3588 }
3589
3590 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3591 sky2->tx_cons, sky2->tx_prod,
3592 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3593 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3594
3595 /* Dump contents of tx ring */
3596 sop = 1;
3597 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3598 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3599 const struct sky2_tx_le *le = sky2->tx_le + idx;
3600 u32 a = le32_to_cpu(le->addr);
3601
3602 if (sop)
3603 seq_printf(seq, "%u:", idx);
3604 sop = 0;
3605
3606 switch(le->opcode & ~HW_OWNER) {
3607 case OP_ADDR64:
3608 seq_printf(seq, " %#x:", a);
3609 break;
3610 case OP_LRGLEN:
3611 seq_printf(seq, " mtu=%d", a);
3612 break;
3613 case OP_VLAN:
3614 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3615 break;
3616 case OP_TCPLISW:
3617 seq_printf(seq, " csum=%#x", a);
3618 break;
3619 case OP_LARGESEND:
3620 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3621 break;
3622 case OP_PACKET:
3623 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3624 break;
3625 case OP_BUFFER:
3626 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3627 break;
3628 default:
3629 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3630 a, le16_to_cpu(le->length));
3631 }
3632
3633 if (le->ctrl & EOP) {
3634 seq_putc(seq, '\n');
3635 sop = 1;
3636 }
3637 }
3638
3639 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3640 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3641 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3642 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3643
3644 netif_poll_enable(hw->dev[0]);
3645 return 0;
3646}
3647
3648static int sky2_debug_open(struct inode *inode, struct file *file)
3649{
3650 return single_open(file, sky2_debug_show, inode->i_private);
3651}
3652
3653static const struct file_operations sky2_debug_fops = {
3654 .owner = THIS_MODULE,
3655 .open = sky2_debug_open,
3656 .read = seq_read,
3657 .llseek = seq_lseek,
3658 .release = single_release,
3659};
3660
3661/*
3662 * Use network device events to create/remove/rename
3663 * debugfs file entries
3664 */
3665static int sky2_device_event(struct notifier_block *unused,
3666 unsigned long event, void *ptr)
3667{
3668 struct net_device *dev = ptr;
3669
3670 if (dev->open == sky2_up) {
3671 struct sky2_port *sky2 = netdev_priv(dev);
3672
3673 switch(event) {
3674 case NETDEV_CHANGENAME:
3675 if (!netif_running(dev))
3676 break;
3677 /* fallthrough */
3678 case NETDEV_DOWN:
3679 case NETDEV_GOING_DOWN:
3680 if (sky2->debugfs) {
3681 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3682 dev->name);
3683 debugfs_remove(sky2->debugfs);
3684 sky2->debugfs = NULL;
3685 }
3686
3687 if (event != NETDEV_CHANGENAME)
3688 break;
3689 /* fallthrough for changename */
3690 case NETDEV_UP:
3691 if (sky2_debug) {
3692 struct dentry *d;
3693 d = debugfs_create_file(dev->name, S_IRUGO,
3694 sky2_debug, dev,
3695 &sky2_debug_fops);
3696 if (d == NULL || IS_ERR(d))
3697 printk(KERN_INFO PFX
3698 "%s: debugfs create failed\n",
3699 dev->name);
3700 else
3701 sky2->debugfs = d;
3702 }
3703 break;
3704 }
3705 }
3706
3707 return NOTIFY_DONE;
3708}
3709
3710static struct notifier_block sky2_notifier = {
3711 .notifier_call = sky2_device_event,
3712};
3713
3714
3715static __init void sky2_debug_init(void)
3716{
3717 struct dentry *ent;
3718
3719 ent = debugfs_create_dir("sky2", NULL);
3720 if (!ent || IS_ERR(ent))
3721 return;
3722
3723 sky2_debug = ent;
3724 register_netdevice_notifier(&sky2_notifier);
3725}
3726
3727static __exit void sky2_debug_cleanup(void)
3728{
3729 if (sky2_debug) {
3730 unregister_netdevice_notifier(&sky2_notifier);
3731 debugfs_remove(sky2_debug);
3732 sky2_debug = NULL;
3733 }
3734}
3735
3736#else
3737#define sky2_debug_init()
3738#define sky2_debug_cleanup()
3739#endif
3740
3741
cd28ab6a
SH		 3742/* Initialize network device */
3743static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3744 unsigned port,
3745 int highmem, int wol)
cd28ab6a
SH		 3746{
3747 struct sky2_port *sky2;
3748 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3749
3750 if (!dev) {
b02a9258 3751 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3752 return NULL;
3753 }
3754
3755 SET_MODULE_OWNER(dev);
3756 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3757 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3758 dev->open = sky2_up;
3759 dev->stop = sky2_down;
ef743d33 3760 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3761 dev->hard_start_xmit = sky2_xmit_frame;
3762 dev->get_stats = sky2_get_stats;
3763 dev->set_multicast_list = sky2_set_multicast;
3764 dev->set_mac_address = sky2_set_mac_address;
3765 dev->change_mtu = sky2_change_mtu;
3766 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3767 dev->tx_timeout = sky2_tx_timeout;
3768 dev->watchdog_timeo = TX_WATCHDOG;
3769 if (port == 0)
3770 dev->poll = sky2_poll;
3771 dev->weight = NAPI_WEIGHT;
3772#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3773 /* Network console (only works on port 0)
3774 * because netpoll makes assumptions about NAPI
3775 */
3776 if (port == 0)
3777 dev->poll_controller = sky2_netpoll;
cd28ab6a 3778#endif
cd28ab6a
SH		 3779
3780 sky2 = netdev_priv(dev);
3781 sky2->netdev = dev;
3782 sky2->hw = hw;
3783 sky2->msg_enable = netif_msg_init(debug, default_msg);
3784
cd28ab6a
SH		 3785 /* Auto speed and flow control */
3786 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3787 sky2->flow_mode = FC_BOTH;
3788
cd28ab6a
SH		 3789 sky2->duplex = -1;
3790 sky2->speed = -1;
3791 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3792 sky2->rx_csum = 1;
e3173832 3793 sky2->wol = wol;
75d070c5 3794
e07b1aa8 3795 spin_lock_init(&sky2->phy_lock);
793b883e 3796 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3797 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3798
3799 hw->dev[port] = dev;
3800
3801 sky2->port = port;
3802
4a50a876 3803 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3804 if (highmem)
3805 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3806
d1f13708 3807#ifdef SKY2_VLAN_TAG_USED
3808 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3809 dev->vlan_rx_register = sky2_vlan_rx_register;
d1f13708 3810#endif
3811
cd28ab6a 3812 /* read the mac address */
793b883e 3813 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3814 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 3815
cd28ab6a
SH		 3816 return dev;
3817}
3818
28bd181a 3819static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3820{
3821 const struct sky2_port *sky2 = netdev_priv(dev);
3822
3823 if (netif_msg_probe(sky2))
3824 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3825 dev->name,
3826 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3827 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3828}
3829
fb2690a9 3830/* Handle software interrupt used during MSI test */
7d12e780 3831static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3832{
3833 struct sky2_hw *hw = dev_id;
3834 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3835
3836 if (status == 0)
3837 return IRQ_NONE;
3838
3839 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3840 hw->msi = 1;
fb2690a9
SH		 3841 wake_up(&hw->msi_wait);
3842 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3843 }
3844 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3845
3846 return IRQ_HANDLED;
3847}
3848
3849/* Test interrupt path by forcing a a software IRQ */
3850static int __devinit sky2_test_msi(struct sky2_hw *hw)
3851{
3852 struct pci_dev *pdev = hw->pdev;
3853 int err;
3854
bb507fe1 3855 init_waitqueue_head (&hw->msi_wait);
3856
fb2690a9
SH		 3857 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3858
b0a20ded 3859 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 3860 if (err) {
b02a9258 3861 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 3862 return err;
3863 }
3864
fb2690a9 3865 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3866 sky2_read8(hw, B0_CTST);
fb2690a9 3867
b0a20ded 3868 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3869
b0a20ded 3870 if (!hw->msi) {
fb2690a9 3871 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 3872 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3873 "switching to INTx mode.\n");
fb2690a9
SH		 3874
3875 err = -EOPNOTSUPP;
3876 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3877 }
3878
3879 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3880 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3881
3882 free_irq(pdev->irq, hw);
3883
3884 return err;
3885}
3886
e3173832
SH		 3887static int __devinit pci_wake_enabled(struct pci_dev *dev)
3888{
3889 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3890 u16 value;
3891
3892 if (!pm)
3893 return 0;
3894 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3895 return 0;
3896 return value & PCI_PM_CTRL_PME_ENABLE;
3897}
3898
cd28ab6a
SH		 3899static int __devinit sky2_probe(struct pci_dev *pdev,
3900 const struct pci_device_id *ent)
3901{
7f60c64b 3902 struct net_device *dev;
cd28ab6a 3903 struct sky2_hw *hw;
e3173832 3904 int err, using_dac = 0, wol_default;
cd28ab6a 3905
793b883e
SH		 3906 err = pci_enable_device(pdev);
3907 if (err) {
b02a9258 3908 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 3909 goto err_out;
3910 }
3911
793b883e
SH		 3912 err = pci_request_regions(pdev, DRV_NAME);
3913 if (err) {
b02a9258 3914 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 3915 goto err_out_disable;
cd28ab6a
SH		 3916 }
3917
3918 pci_set_master(pdev);
3919
d1f3d4dd
SH		 3920 if (sizeof(dma_addr_t) > sizeof(u32) &&
3921 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3922 using_dac = 1;
3923 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3924 if (err < 0) {
b02a9258
SH		 3925 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3926 "for consistent allocations\n");
d1f3d4dd
SH		 3927 goto err_out_free_regions;
3928 }
d1f3d4dd 3929 } else {
cd28ab6a
SH		 3930 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3931 if (err) {
b02a9258 3932 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 3933 goto err_out_free_regions;
3934 }
3935 }
d1f3d4dd 3936
e3173832
SH		 3937 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3938
cd28ab6a 3939 err = -ENOMEM;
6aad85d6 3940 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 3941 if (!hw) {
b02a9258 3942 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 3943 goto err_out_free_regions;
3944 }
3945
cd28ab6a 3946 hw->pdev = pdev;
cd28ab6a
SH		 3947
3948 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3949 if (!hw->regs) {
b02a9258 3950 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 3951 goto err_out_free_hw;
3952 }
3953
56a645cc 3954#ifdef __BIG_ENDIAN
f65b138c
SH		 3955 /* The sk98lin vendor driver uses hardware byte swapping but
3956 * this driver uses software swapping.
3957 */
56a645cc
SH		 3958 {
3959 u32 reg;
56a645cc 3960 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3961 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3962 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3963 }
3964#endif
3965
08c06d8a
SH		 3966 /* ring for status responses */
3967 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3968 &hw->st_dma);
3969 if (!hw->st_le)
3970 goto err_out_iounmap;
3971
e3173832 3972 err = sky2_init(hw);
cd28ab6a 3973 if (err)
793b883e 3974 goto err_out_iounmap;
cd28ab6a 3975
b02a9258 3976 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 3977 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3978 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3979 hw->chip_id, hw->chip_rev);
cd28ab6a 3980
e3173832
SH		 3981 sky2_reset(hw);
3982
3983 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 3984 if (!dev) {
3985 err = -ENOMEM;
cd28ab6a 3986 goto err_out_free_pci;
7f60c64b 3987 }
cd28ab6a 3988
9fa1b1f3
SH		 3989 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3990 err = sky2_test_msi(hw);
3991 if (err == -EOPNOTSUPP)
3992 pci_disable_msi(pdev);
3993 else if (err)
3994 goto err_out_free_netdev;
3995 }
3996
793b883e
SH		 3997 err = register_netdev(dev);
3998 if (err) {
b02a9258 3999 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4000 goto err_out_free_netdev;
4001 }
4002
b0a20ded
SH		 4003 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
4004 dev->name, hw);
9fa1b1f3 4005 if (err) {
b02a9258 4006 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4007 goto err_out_unregister;
4008 }
4009 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4010
cd28ab6a
SH		 4011 sky2_show_addr(dev);
4012
7f60c64b 4013 if (hw->ports > 1) {
4014 struct net_device *dev1;
4015
e3173832 4016 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4017 if (!dev1)
4018 dev_warn(&pdev->dev, "allocation for second device failed\n");
4019 else if ((err = register_netdev(dev1))) {
4020 dev_warn(&pdev->dev,
4021 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4022 hw->dev[1] = NULL;
4023 free_netdev(dev1);
b02a9258
SH		 4024 } else
4025 sky2_show_addr(dev1);
cd28ab6a
SH		 4026 }
4027
01bd7564 4028 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
81906791
SH		 4029 INIT_WORK(&hw->restart_work, sky2_restart);
4030
eb35cf60 4031 sky2_idle_start(hw);
d27ed387 4032
793b883e
SH		 4033 pci_set_drvdata(pdev, hw);
4034
cd28ab6a
SH		 4035 return 0;
4036
793b883e 4037err_out_unregister:
b0a20ded
SH		 4038 if (hw->msi)
4039 pci_disable_msi(pdev);
793b883e 4040 unregister_netdev(dev);
cd28ab6a
SH		 4041err_out_free_netdev:
4042 free_netdev(dev);
cd28ab6a 4043err_out_free_pci:
793b883e 4044 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 4045 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4046err_out_iounmap:
4047 iounmap(hw->regs);
4048err_out_free_hw:
4049 kfree(hw);
4050err_out_free_regions:
4051 pci_release_regions(pdev);
44a1d2e5 4052err_out_disable:
cd28ab6a 4053 pci_disable_device(pdev);
cd28ab6a 4054err_out:
549a68c3 4055 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4056 return err;
4057}
4058
4059static void __devexit sky2_remove(struct pci_dev *pdev)
4060{
793b883e 4061 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 4062 struct net_device *dev0, *dev1;
4063
793b883e 4064 if (!hw)
cd28ab6a
SH		 4065 return;
4066
d27ed387
SH		 4067 del_timer_sync(&hw->idle_timer);
4068
81906791
SH		 4069 flush_scheduled_work();
4070
d27ed387 4071 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 4072 synchronize_irq(hw->pdev->irq);
4073
cd28ab6a 4074 dev0 = hw->dev[0];
793b883e
SH		 4075 dev1 = hw->dev[1];
4076 if (dev1)
4077 unregister_netdev(dev1);
cd28ab6a
SH		 4078 unregister_netdev(dev0);
4079
ae306cca
SH		 4080 sky2_power_aux(hw);
4081
cd28ab6a 4082 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4083 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4084 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4085
4086 free_irq(pdev->irq, hw);
b0a20ded
SH		 4087 if (hw->msi)
4088 pci_disable_msi(pdev);
793b883e 4089 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4090 pci_release_regions(pdev);
4091 pci_disable_device(pdev);
793b883e 4092
cd28ab6a
SH		 4093 if (dev1)
4094 free_netdev(dev1);
4095 free_netdev(dev0);
4096 iounmap(hw->regs);
4097 kfree(hw);
5afa0a9c 4098
cd28ab6a
SH		 4099 pci_set_drvdata(pdev, NULL);
4100}
4101
4102#ifdef CONFIG_PM
4103static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4104{
793b883e 4105 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4106 int i, wol = 0;
cd28ab6a 4107
549a68c3
SH		 4108 if (!hw)
4109 return 0;
4110
eb35cf60 4111 del_timer_sync(&hw->idle_timer);
6a5706b9 4112 netif_poll_disable(hw->dev[0]);
eb35cf60 4113
f05267e7 4114 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4115 struct net_device *dev = hw->dev[i];
e3173832 4116 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4117
e3173832 4118 if (netif_running(dev))
5afa0a9c 4119 sky2_down(dev);
e3173832
SH		 4120
4121 if (sky2->wol)
4122 sky2_wol_init(sky2);
4123
4124 wol |= sky2->wol;
cd28ab6a
SH		 4125 }
4126
8ab8fca2 4127 sky2_write32(hw, B0_IMSK, 0);
ae306cca 4128 sky2_power_aux(hw);
e3173832 4129
d374c1c1 4130 pci_save_state(pdev);
e3173832 4131 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 4132 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4133
2ccc99b7 4134 return 0;
cd28ab6a
SH		 4135}
4136
4137static int sky2_resume(struct pci_dev *pdev)
4138{
793b883e 4139 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4140 int i, err;
cd28ab6a 4141
549a68c3
SH		 4142 if (!hw)
4143 return 0;
4144
ae306cca
SH		 4145 err = pci_set_power_state(pdev, PCI_D0);
4146 if (err)
4147 goto out;
4148
4149 err = pci_restore_state(pdev);
4150 if (err)
4151 goto out;
4152
cd28ab6a 4153 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4154
4155 /* Re-enable all clocks */
4156 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
4157 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4158
e3173832 4159 sky2_reset(hw);
cd28ab6a 4160
8ab8fca2
SH		 4161 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4162
f05267e7 4163 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4164 struct net_device *dev = hw->dev[i];
6a5706b9 4165 if (netif_running(dev)) {
08c06d8a
SH		 4166 err = sky2_up(dev);
4167 if (err) {
4168 printk(KERN_ERR PFX "%s: could not up: %d\n",
4169 dev->name, err);
4170 dev_close(dev);
eb35cf60 4171 goto out;
5afa0a9c 4172 }
cd28ab6a
SH		 4173 }
4174 }
eb35cf60 4175
6a5706b9 4176 netif_poll_enable(hw->dev[0]);
eb35cf60 4177 sky2_idle_start(hw);
ae306cca 4178 return 0;
08c06d8a 4179out:
b02a9258 4180 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4181 pci_disable_device(pdev);
08c06d8a 4182 return err;
cd28ab6a
SH		 4183}
4184#endif
4185
e3173832
SH		 4186static void sky2_shutdown(struct pci_dev *pdev)
4187{
4188 struct sky2_hw *hw = pci_get_drvdata(pdev);
4189 int i, wol = 0;
4190
549a68c3
SH		 4191 if (!hw)
4192 return;
4193
e3173832
SH		 4194 del_timer_sync(&hw->idle_timer);
4195 netif_poll_disable(hw->dev[0]);
4196
4197 for (i = 0; i < hw->ports; i++) {
4198 struct net_device *dev = hw->dev[i];
4199 struct sky2_port *sky2 = netdev_priv(dev);
4200
4201 if (sky2->wol) {
4202 wol = 1;
4203 sky2_wol_init(sky2);
4204 }
4205 }
4206
4207 if (wol)
4208 sky2_power_aux(hw);
4209
4210 pci_enable_wake(pdev, PCI_D3hot, wol);
4211 pci_enable_wake(pdev, PCI_D3cold, wol);
4212
4213 pci_disable_device(pdev);
4214 pci_set_power_state(pdev, PCI_D3hot);
4215
4216}
4217
cd28ab6a 4218static struct pci_driver sky2_driver = {
793b883e
SH		 4219 .name = DRV_NAME,
4220 .id_table = sky2_id_table,
4221 .probe = sky2_probe,
4222 .remove = __devexit_p(sky2_remove),
cd28ab6a 4223#ifdef CONFIG_PM
793b883e
SH		 4224 .suspend = sky2_suspend,
4225 .resume = sky2_resume,
cd28ab6a 4226#endif
e3173832 4227 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4228};
4229
4230static int __init sky2_init_module(void)
4231{
3cf26753 4232 sky2_debug_init();
50241c4c 4233 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4234}
4235
4236static void __exit sky2_cleanup_module(void)
4237{
4238 pci_unregister_driver(&sky2_driver);
3cf26753 4239 sky2_debug_cleanup();
cd28ab6a
SH		 4240}
4241
4242module_init(sky2_init_module);
4243module_exit(sky2_cleanup_module);
4244
4245MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4246MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4247MODULE_LICENSE("GPL");
5f4f9dc1 4248MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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