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sky2: chip version printout
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
3cf26753 42#include <linux/debugfs.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
bcc52894 54#define DRV_VERSION "1.21"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
793b883e
SH		 67
68#define TX_RING_SIZE 512
69#define TX_DEF_PENDING (TX_RING_SIZE - 1)
70#define TX_MIN_PENDING 64
b19666d9 71#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 72
793b883e 73#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 74#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 75#define TX_WATCHDOG (5 * HZ)
76#define NAPI_WEIGHT 64
77#define PHY_RETRIES 1000
78
f4331a6d
SH		 79#define SKY2_EEPROM_MAGIC 0x9955aabb
80
81
cb5d9547
SH		 82#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
cd28ab6a 84static const u32 default_msg =
793b883e
SH		 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 88
793b883e 89static int debug = -1; /* defaults above */
cd28ab6a
SH		 90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
14d0263f 93static int copybreak __read_mostly = 128;
bdb5c58e
SH		 94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
fb2690a9
SH		 97static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
cd28ab6a 101static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
e5b74c7d 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
cd28ab6a
SH		 139 { 0 }
140};
793b883e 141
cd28ab6a
SH		 142MODULE_DEVICE_TABLE(pci, sky2_id_table);
143
144/* Avoid conditionals by using array */
145static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
146static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 147static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 148
d1b139c0
SH		 149static void sky2_set_multicast(struct net_device *dev);
150
af043aa5 151/* Access to PHY via serial interconnect */
ef743d33 152static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 153{
154 int i;
155
156 gma_write16(hw, port, GM_SMI_DATA, val);
157 gma_write16(hw, port, GM_SMI_CTRL,
158 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
159
160 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 161 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
162 if (ctrl == 0xffff)
163 goto io_error;
164
165 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 166 return 0;
af043aa5
SH		 167
168 udelay(10);
cd28ab6a 169 }
ef743d33 170
af043aa5 171 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 172 return -ETIMEDOUT;
af043aa5
SH		 173
174io_error:
175 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
176 return -EIO;
cd28ab6a
SH		 177}
178
ef743d33 179static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 180{
181 int i;
182
793b883e 183 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 184 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
185
186 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 187 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
188 if (ctrl == 0xffff)
189 goto io_error;
190
191 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33 192 *val = gma_read16(hw, port, GM_SMI_DATA);
193 return 0;
194 }
195
af043aa5 196 udelay(10);
cd28ab6a
SH		 197 }
198
af043aa5 199 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 200 return -ETIMEDOUT;
af043aa5
SH		 201io_error:
202 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
203 return -EIO;
ef743d33 204}
205
af043aa5 206static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33 207{
208 u16 v;
af043aa5 209 __gm_phy_read(hw, port, reg, &v);
ef743d33 210 return v;
cd28ab6a
SH		 211}
212
5afa0a9c 213
ae306cca
SH		 214static void sky2_power_on(struct sky2_hw *hw)
215{
216 /* switch power to VCC (WA for VAUX problem) */
217 sky2_write8(hw, B0_POWER_CTRL,
218 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 219
ae306cca
SH		 220 /* disable Core Clock Division, */
221 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 222
ae306cca
SH		 223 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
224 /* enable bits are inverted */
225 sky2_write8(hw, B2_Y2_CLK_GATE,
226 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
227 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
228 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
229 else
230 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 231
ea76e635 232 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 233 u32 reg;
5afa0a9c 234
b32f40c4 235 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 236
b32f40c4 237 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 238 /* set all bits to 0 except bits 15..12 and 8 */
239 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 240 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 241
b32f40c4 242 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 243 /* set all bits to 0 except bits 28 & 27 */
244 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 245 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 246
b32f40c4 247 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 248
249 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
250 reg = sky2_read32(hw, B2_GP_IO);
251 reg |= GLB_GPIO_STAT_RACE_DIS;
252 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 253
254 sky2_read32(hw, B2_GP_IO);
5afa0a9c 255 }
ae306cca 256}
5afa0a9c 257
ae306cca
SH		 258static void sky2_power_aux(struct sky2_hw *hw)
259{
260 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
261 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
262 else
263 /* enable bits are inverted */
264 sky2_write8(hw, B2_Y2_CLK_GATE,
265 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
266 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
267 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
268
269 /* switch power to VAUX */
270 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
271 sky2_write8(hw, B0_POWER_CTRL,
272 (PC_VAUX_ENA | PC_VCC_ENA |
273 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c 274}
275
a068c0ad
SH		 276static void sky2_power_state(struct sky2_hw *hw, pci_power_t state)
277{
278 u16 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
279 int pex = pci_find_capability(hw->pdev, PCI_CAP_ID_EXP);
280 u32 reg;
281
282 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
283
284 switch (state) {
285 case PCI_D0:
286 break;
287
288 case PCI_D1:
289 power_control |= 1;
290 break;
291
292 case PCI_D2:
293 power_control |= 2;
294 break;
295
296 case PCI_D3hot:
297 case PCI_D3cold:
298 power_control |= 3;
299 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
300 /* additional power saving measurements */
301 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
302
303 /* set gating core clock for LTSSM in L1 state */
304 reg |= P_PEX_LTSSM_STAT(P_PEX_LTSSM_L1_STAT) |
305 /* auto clock gated scheme controlled by CLKREQ */
306 P_ASPM_A1_MODE_SELECT |
307 /* enable Gate Root Core Clock */
308 P_CLK_GATE_ROOT_COR_ENA;
309
310 if (pex && (hw->flags & SKY2_HW_CLK_POWER)) {
311 /* enable Clock Power Management (CLKREQ) */
312 u16 ctrl = sky2_pci_read16(hw, pex + PCI_EXP_DEVCTL);
313
314 ctrl |= PCI_EXP_DEVCTL_AUX_PME;
315 sky2_pci_write16(hw, pex + PCI_EXP_DEVCTL, ctrl);
316 } else
317 /* force CLKREQ Enable in Our4 (A1b only) */
318 reg |= P_ASPM_FORCE_CLKREQ_ENA;
319
320 /* set Mask Register for Release/Gate Clock */
321 sky2_pci_write32(hw, PCI_DEV_REG5,
322 P_REL_PCIE_EXIT_L1_ST | P_GAT_PCIE_ENTER_L1_ST |
323 P_REL_PCIE_RX_EX_IDLE | P_GAT_PCIE_RX_EL_IDLE |
324 P_REL_GPHY_LINK_UP | P_GAT_GPHY_LINK_DOWN);
325 } else
326 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_CLK_HALT);
327
328 /* put CPU into reset state */
329 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, HCU_CCSR_ASF_RESET);
330 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev == CHIP_REV_YU_SU_A0)
331 /* put CPU into halt state */
332 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, HCU_CCSR_ASF_HALTED);
333
334 if (pex && !(hw->flags & SKY2_HW_RAM_BUFFER)) {
335 reg = sky2_pci_read32(hw, PCI_DEV_REG1);
336 /* force to PCIe L1 */
337 reg |= PCI_FORCE_PEX_L1;
338 sky2_pci_write32(hw, PCI_DEV_REG1, reg);
339 }
340 break;
341
342 default:
343 dev_warn(&hw->pdev->dev, PFX "Invalid power state (%d) ",
344 state);
345 return;
346 }
347
348 power_control |= PCI_PM_CTRL_PME_ENABLE;
349 /* Finally, set the new power state. */
350 sky2_pci_write32(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
351
352 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
353 sky2_pci_read32(hw, B0_CTST);
354}
355
d3bcfbeb 356static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 357{
358 u16 reg;
359
360 /* disable all GMAC IRQ's */
361 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 362
cd28ab6a
SH		 363 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
364 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
365 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
366 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
367
368 reg = gma_read16(hw, port, GM_RX_CTRL);
369 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
370 gma_write16(hw, port, GM_RX_CTRL, reg);
371}
372
16ad91e1
SH		 373/* flow control to advertise bits */
374static const u16 copper_fc_adv[] = {
375 [FC_NONE] = 0,
376 [FC_TX] = PHY_M_AN_ASP,
377 [FC_RX] = PHY_M_AN_PC,
378 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
379};
380
381/* flow control to advertise bits when using 1000BaseX */
382static const u16 fiber_fc_adv[] = {
df3fe1f3 383 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 384 [FC_TX] = PHY_M_P_ASYM_MD_X,
385 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 386 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 387};
388
389/* flow control to GMA disable bits */
390static const u16 gm_fc_disable[] = {
391 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
392 [FC_TX] = GM_GPCR_FC_RX_DIS,
393 [FC_RX] = GM_GPCR_FC_TX_DIS,
394 [FC_BOTH] = 0,
395};
396
397
cd28ab6a
SH		 398static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
399{
400 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 401 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 402
ea76e635
SH		 403 if (sky2->autoneg == AUTONEG_ENABLE &&
404 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 405 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
406
407 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 408 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 409 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
410
53419c68 411 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 412 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 413 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 414 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
415 else
53419c68
SH		 416 /* set master & slave downshift counter to 1x */
417 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 418
419 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
420 }
421
422 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 423 if (sky2_is_copper(hw)) {
05745c4a 424 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 425 /* enable automatic crossover */
426 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 427
428 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
429 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
430 u16 spec;
431
432 /* Enable Class A driver for FE+ A0 */
433 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
434 spec |= PHY_M_FESC_SEL_CL_A;
435 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
436 }
cd28ab6a
SH		 437 } else {
438 /* disable energy detect */
439 ctrl &= ~PHY_M_PC_EN_DET_MSK;
440
441 /* enable automatic crossover */
442 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
443
53419c68 444 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 445 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 446 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 447 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 448 ctrl &= ~PHY_M_PC_DSC_MSK;
449 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
450 }
451 }
cd28ab6a
SH		 452 } else {
453 /* workaround for deviation #4.88 (CRC errors) */
454 /* disable Automatic Crossover */
455
456 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 457 }
cd28ab6a 458
b89165f2
SH		 459 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
460
461 /* special setup for PHY 88E1112 Fiber */
ea76e635 462 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 463 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 464
b89165f2
SH		 465 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
466 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
467 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
468 ctrl &= ~PHY_M_MAC_MD_MSK;
469 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
470 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
471
472 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 473 /* select page 1 to access Fiber registers */
474 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 475
476 /* for SFP-module set SIGDET polarity to low */
477 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
478 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 479 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 480 }
b89165f2
SH		 481
482 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 483 }
484
7800fddc 485 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 486 ct1000 = 0;
487 adv = PHY_AN_CSMA;
2eaba1a2 488 reg = 0;
cd28ab6a
SH		 489
490 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 491 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 492 if (sky2->advertising & ADVERTISED_1000baseT_Full)
493 ct1000 |= PHY_M_1000C_AFD;
494 if (sky2->advertising & ADVERTISED_1000baseT_Half)
495 ct1000 |= PHY_M_1000C_AHD;
496 if (sky2->advertising & ADVERTISED_100baseT_Full)
497 adv |= PHY_M_AN_100_FD;
498 if (sky2->advertising & ADVERTISED_100baseT_Half)
499 adv |= PHY_M_AN_100_HD;
500 if (sky2->advertising & ADVERTISED_10baseT_Full)
501 adv |= PHY_M_AN_10_FD;
502 if (sky2->advertising & ADVERTISED_10baseT_Half)
503 adv |= PHY_M_AN_10_HD;
709c6e7b 504
16ad91e1 505 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 506 } else { /* special defines for FIBER (88E1040S only) */
507 if (sky2->advertising & ADVERTISED_1000baseT_Full)
508 adv |= PHY_M_AN_1000X_AFD;
509 if (sky2->advertising & ADVERTISED_1000baseT_Half)
510 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 511
16ad91e1 512 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 513 }
cd28ab6a
SH		 514
515 /* Restart Auto-negotiation */
516 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
517 } else {
518 /* forced speed/duplex settings */
519 ct1000 = PHY_M_1000C_MSE;
520
2eaba1a2
SH		 521 /* Disable auto update for duplex flow control and speed */
522 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 523
524 switch (sky2->speed) {
525 case SPEED_1000:
526 ctrl |= PHY_CT_SP1000;
2eaba1a2 527 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 528 break;
529 case SPEED_100:
530 ctrl |= PHY_CT_SP100;
2eaba1a2 531 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 532 break;
533 }
534
2eaba1a2
SH		 535 if (sky2->duplex == DUPLEX_FULL) {
536 reg |= GM_GPCR_DUP_FULL;
537 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 538 } else if (sky2->speed < SPEED_1000)
539 sky2->flow_mode = FC_NONE;
2eaba1a2 540
2eaba1a2 541
16ad91e1 542 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 543
544 /* Forward pause packets to GMAC? */
16ad91e1 545 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 546 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
547 else
548 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 549 }
550
2eaba1a2
SH		 551 gma_write16(hw, port, GM_GP_CTRL, reg);
552
05745c4a 553 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 554 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
555
556 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
557 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
558
559 /* Setup Phy LED's */
560 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
561 ledover = 0;
562
563 switch (hw->chip_id) {
564 case CHIP_ID_YUKON_FE:
565 /* on 88E3082 these bits are at 11..9 (shifted left) */
566 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
567
568 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
569
570 /* delete ACT LED control bits */
571 ctrl &= ~PHY_M_FELP_LED1_MSK;
572 /* change ACT LED control to blink mode */
573 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
574 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
575 break;
576
05745c4a
SH		 577 case CHIP_ID_YUKON_FE_P:
578 /* Enable Link Partner Next Page */
579 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
580 ctrl |= PHY_M_PC_ENA_LIP_NP;
581
582 /* disable Energy Detect and enable scrambler */
583 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
584 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
585
586 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
587 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
588 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
589 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
590
591 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
592 break;
593
cd28ab6a 594 case CHIP_ID_YUKON_XL:
793b883e 595 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 596
597 /* select page 3 to access LED control register */
598 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
599
600 /* set LED Function Control register */
ed6d32c7
SH		 601 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
602 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
603 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
604 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
605 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 606
607 /* set Polarity Control register */
608 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 609 (PHY_M_POLC_LS1_P_MIX(4) |
610 PHY_M_POLC_IS0_P_MIX(4) |
611 PHY_M_POLC_LOS_CTRL(2) |
612 PHY_M_POLC_INIT_CTRL(2) |
613 PHY_M_POLC_STA1_CTRL(2) |
614 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 615
616 /* restore page register */
793b883e 617 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 618 break;
93745494 619
ed6d32c7 620 case CHIP_ID_YUKON_EC_U:
93745494 621 case CHIP_ID_YUKON_EX:
ed4d4161 622 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 623 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
624
625 /* select page 3 to access LED control register */
626 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
627
628 /* set LED Function Control register */
629 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
630 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
631 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
632 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
633 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
634
635 /* set Blink Rate in LED Timer Control Register */
636 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
637 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
638 /* restore page register */
639 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
640 break;
cd28ab6a
SH		 641
642 default:
643 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
644 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 645
cd28ab6a 646 /* turn off the Rx LED (LED_RX) */
a84d0a3d 647 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 648 }
649
e1a74b37 650 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
977bdf06 651 /* apply fixes in PHY AFE */
ed6d32c7
SH		 652 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
653
977bdf06 654 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 655 gm_phy_write(hw, port, 0x18, 0xaa99);
656 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 657
977bdf06 658 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 659 gm_phy_write(hw, port, 0x18, 0xa204);
660 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 661
662 /* set page register to 0 */
9467a8fc 663 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 664 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
665 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
666 /* apply workaround for integrated resistors calibration */
667 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
668 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
e1a74b37
SH		 669 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
670 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 671 /* no effect on Yukon-XL */
977bdf06 672 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 673
977bdf06
SH		 674 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
675 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 676 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 677 }
cd28ab6a 678
977bdf06
SH		 679 if (ledover)
680 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
681
682 }
2eaba1a2 683
d571b694 684 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 685 if (sky2->autoneg == AUTONEG_ENABLE)
686 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
687 else
688 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
689}
690
b96936da
SH		 691static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
692static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
693
694static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb 695{
696 u32 reg1;
d3bcfbeb 697
82637e80 698 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 699 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 700 reg1 &= ~phy_power[port];
d3bcfbeb 701
b96936da 702 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 703 reg1 |= coma_mode[port];
704
b32f40c4 705 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80
SH		 706 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
707 sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 708}
167f53d0 709
b96936da
SH		 710static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
711{
712 u32 reg1;
db99b988
SH		 713 u16 ctrl;
714
715 /* release GPHY Control reset */
716 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
717
718 /* release GMAC reset */
719 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
720
721 if (hw->flags & SKY2_HW_NEWER_PHY) {
722 /* select page 2 to access MAC control register */
723 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
724
725 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
726 /* allow GMII Power Down */
727 ctrl &= ~PHY_M_MAC_GMIF_PUP;
728 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
729
730 /* set page register back to 0 */
731 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
732 }
733
734 /* setup General Purpose Control Register */
735 gma_write16(hw, port, GM_GP_CTRL,
736 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
737
738 if (hw->chip_id != CHIP_ID_YUKON_EC) {
739 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
740 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
741
742 /* enable Power Down */
743 ctrl |= PHY_M_PC_POW_D_ENA;
744 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
745 }
746
747 /* set IEEE compatible Power Down Mode (dev. #4.99) */
748 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
749 }
b96936da
SH		 750
751 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
752 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 753 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da
SH		 754 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
755 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb 756}
757
1b537565
SH		 758/* Force a renegotiation */
759static void sky2_phy_reinit(struct sky2_port *sky2)
760{
e07b1aa8 761 spin_lock_bh(&sky2->phy_lock);
1b537565 762 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 763 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 764}
765
e3173832
SH		 766/* Put device in state to listen for Wake On Lan */
767static void sky2_wol_init(struct sky2_port *sky2)
768{
769 struct sky2_hw *hw = sky2->hw;
770 unsigned port = sky2->port;
771 enum flow_control save_mode;
772 u16 ctrl;
773 u32 reg1;
774
775 /* Bring hardware out of reset */
776 sky2_write16(hw, B0_CTST, CS_RST_CLR);
777 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
778
779 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
780 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
781
782 /* Force to 10/100
783 * sky2_reset will re-enable on resume
784 */
785 save_mode = sky2->flow_mode;
786 ctrl = sky2->advertising;
787
788 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
789 sky2->flow_mode = FC_NONE;
b96936da
SH		 790
791 spin_lock_bh(&sky2->phy_lock);
792 sky2_phy_power_up(hw, port);
793 sky2_phy_init(hw, port);
794 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 795
796 sky2->flow_mode = save_mode;
797 sky2->advertising = ctrl;
798
799 /* Set GMAC to no flow control and auto update for speed/duplex */
800 gma_write16(hw, port, GM_GP_CTRL,
801 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
802 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
803
804 /* Set WOL address */
805 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
806 sky2->netdev->dev_addr, ETH_ALEN);
807
808 /* Turn on appropriate WOL control bits */
809 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
810 ctrl = 0;
811 if (sky2->wol & WAKE_PHY)
812 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
813 else
814 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
815
816 if (sky2->wol & WAKE_MAGIC)
817 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
818 else
819 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
820
821 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
822 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
823
824 /* Turn on legacy PCI-Express PME mode */
b32f40c4 825 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 826 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 827 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 828
829 /* block receiver */
830 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
831
832}
833
69161611
SH		 834static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
835{
05745c4a
SH		 836 struct net_device *dev = hw->dev[port];
837
ed4d4161
SH		 838 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
839 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
840 hw->chip_id == CHIP_ID_YUKON_FE_P ||
841 hw->chip_id == CHIP_ID_YUKON_SUPR) {
842 /* Yukon-Extreme B0 and further Extreme devices */
843 /* enable Store & Forward mode for TX */
05745c4a 844
ed4d4161
SH		 845 if (dev->mtu <= ETH_DATA_LEN)
846 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
847 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 848
ed4d4161
SH		 849 else
850 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
851 TX_JUMBO_ENA| TX_STFW_ENA);
852 } else {
853 if (dev->mtu <= ETH_DATA_LEN)
854 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
855 else {
856 /* set Tx GMAC FIFO Almost Empty Threshold */
857 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
858 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 859
ed4d4161
SH		 860 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
861
862 /* Can't do offload because of lack of store/forward */
863 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
864 }
69161611
SH		 865 }
866}
867
cd28ab6a
SH		 868static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
869{
870 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
871 u16 reg;
25cccecc 872 u32 rx_reg;
cd28ab6a
SH		 873 int i;
874 const u8 *addr = hw->dev[port]->dev_addr;
875
f350339c
SH		 876 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
877 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 878
879 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
880
793b883e 881 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 882 /* WA DEV_472 -- looks like crossed wires on port 2 */
883 /* clear GMAC 1 Control reset */
884 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
885 do {
886 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
887 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
888 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
889 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
890 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
891 }
892
793b883e 893 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 894
2eaba1a2
SH		 895 /* Enable Transmit FIFO Underrun */
896 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
897
e07b1aa8 898 spin_lock_bh(&sky2->phy_lock);
b96936da 899 sky2_phy_power_up(hw, port);
cd28ab6a 900 sky2_phy_init(hw, port);
e07b1aa8 901 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 902
903 /* MIB clear */
904 reg = gma_read16(hw, port, GM_PHY_ADDR);
905 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
906
43f2f104
SH		 907 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
908 gma_read16(hw, port, i);
cd28ab6a
SH		 909 gma_write16(hw, port, GM_PHY_ADDR, reg);
910
911 /* transmit control */
912 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
913
914 /* receive control reg: unicast + multicast + no FCS */
915 gma_write16(hw, port, GM_RX_CTRL,
793b883e 916 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 917
918 /* transmit flow control */
919 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
920
921 /* transmit parameter */
922 gma_write16(hw, port, GM_TX_PARAM,
923 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
924 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
925 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
926 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
927
928 /* serial mode register */
929 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 930 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 931
6b1a3aef 932 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 933 reg |= GM_SMOD_JUMBO_ENA;
934
935 gma_write16(hw, port, GM_SERIAL_MODE, reg);
936
cd28ab6a
SH		 937 /* virtual address for data */
938 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
939
793b883e
SH		 940 /* physical address: used for pause frames */
941 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
942
943 /* ignore counter overflows */
cd28ab6a
SH		 944 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
945 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
946 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
947
948 /* Configure Rx MAC FIFO */
949 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 950 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 951 if (hw->chip_id == CHIP_ID_YUKON_EX ||
952 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 953 rx_reg |= GMF_RX_OVER_ON;
69161611 954
25cccecc 955 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 956
798fdd07
SH		 957 if (hw->chip_id == CHIP_ID_YUKON_XL) {
958 /* Hardware errata - clear flush mask */
959 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
960 } else {
961 /* Flush Rx MAC FIFO on any flow control or error */
962 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
963 }
cd28ab6a 964
8df9a876 965 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 966 reg = RX_GMF_FL_THR_DEF + 1;
967 /* Another magic mystery workaround from sk98lin */
968 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
969 hw->chip_rev == CHIP_REV_YU_FE2_A0)
970 reg = 0x178;
971 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 972
973 /* Configure Tx MAC FIFO */
974 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
975 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 976
e0c28116 977 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 978 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
8df9a876 979 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 980 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 981
69161611 982 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 983 }
984
e970d1f8
SH		 985 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
986 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
987 /* disable dynamic watermark */
988 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
989 reg &= ~TX_DYN_WM_ENA;
990 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
991 }
cd28ab6a
SH		 992}
993
67712901
SH		 994/* Assign Ram Buffer allocation to queue */
995static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 996{
67712901
SH		 997 u32 end;
998
999 /* convert from K bytes to qwords used for hw register */
1000 start *= 1024/8;
1001 space *= 1024/8;
1002 end = start + space - 1;
793b883e 1003
cd28ab6a
SH		 1004 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1005 sky2_write32(hw, RB_ADDR(q, RB_START), start);
1006 sky2_write32(hw, RB_ADDR(q, RB_END), end);
1007 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
1008 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
1009
1010 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 1011 u32 tp = space - space/4;
793b883e 1012
1c28f6ba
SH		 1013 /* On receive queue's set the thresholds
1014 * give receiver priority when > 3/4 full
1015 * send pause when down to 2K
1016 */
1017 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
1018 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 1019
1c28f6ba
SH		 1020 tp = space - 2048/8;
1021 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1022 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 1023 } else {
1024 /* Enable store & forward on Tx queue's because
1025 * Tx FIFO is only 1K on Yukon
1026 */
1027 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1028 }
1029
1030 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 1031 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 1032}
1033
cd28ab6a 1034/* Setup Bus Memory Interface */
af4ed7e6 1035static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 1036{
1037 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1038 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1039 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 1040 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 1041}
1042
cd28ab6a
SH		 1043/* Setup prefetch unit registers. This is the interface between
1044 * hardware and driver list elements
1045 */
8cc048e3 1046static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 1047 u64 addr, u32 last)
1048{
cd28ab6a
SH		 1049 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1050 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1051 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
1052 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
1053 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1054 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1055
1056 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1057}
1058
793b883e
SH		 1059static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
1060{
1061 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
1062
cb5d9547 1063 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 1064 le->ctrl = 0;
793b883e
SH		 1065 return le;
1066}
cd28ab6a 1067
88f5f0ca
SH		 1068static void tx_init(struct sky2_port *sky2)
1069{
1070 struct sky2_tx_le *le;
1071
1072 sky2->tx_prod = sky2->tx_cons = 0;
1073 sky2->tx_tcpsum = 0;
1074 sky2->tx_last_mss = 0;
1075
1076 le = get_tx_le(sky2);
1077 le->addr = 0;
1078 le->opcode = OP_ADDR64 | HW_OWNER;
88f5f0ca
SH		 1079}
1080
291ea614
SH		 1081static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1082 struct sky2_tx_le *le)
1083{
1084 return sky2->tx_ring + (le - sky2->tx_le);
1085}
1086
290d4de5
SH		 1087/* Update chip's next pointer */
1088static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1089{
50432cb5 1090 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1091 wmb();
50432cb5
SH		 1092 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1093
1094 /* Synchronize I/O on since next processor may write to tail */
1095 mmiowb();
cd28ab6a
SH		 1096}
1097
793b883e 1098
cd28ab6a
SH		 1099static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1100{
1101 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1102 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1103 le->ctrl = 0;
cd28ab6a
SH		 1104 return le;
1105}
1106
14d0263f
SH		 1107/* Build description to hardware for one receive segment */
1108static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1109 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1110{
1111 struct sky2_rx_le *le;
1112
86c6887e 1113 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1114 le = sky2_next_rx(sky2);
86c6887e 1115 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1116 le->opcode = OP_ADDR64 | HW_OWNER;
1117 }
793b883e 1118
cd28ab6a 1119 le = sky2_next_rx(sky2);
734d1868
SH		 1120 le->addr = cpu_to_le32((u32) map);
1121 le->length = cpu_to_le16(len);
14d0263f 1122 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1123}
1124
14d0263f
SH		 1125/* Build description to hardware for one possibly fragmented skb */
1126static void sky2_rx_submit(struct sky2_port *sky2,
1127 const struct rx_ring_info *re)
1128{
1129 int i;
1130
1131 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1132
1133 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1134 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1135}
1136
1137
1138static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1139 unsigned size)
1140{
1141 struct sk_buff *skb = re->skb;
1142 int i;
1143
1144 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1145 pci_unmap_len_set(re, data_size, size);
1146
1147 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1148 re->frag_addr[i] = pci_map_page(pdev,
1149 skb_shinfo(skb)->frags[i].page,
1150 skb_shinfo(skb)->frags[i].page_offset,
1151 skb_shinfo(skb)->frags[i].size,
1152 PCI_DMA_FROMDEVICE);
1153}
1154
1155static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1156{
1157 struct sk_buff *skb = re->skb;
1158 int i;
1159
1160 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1161 PCI_DMA_FROMDEVICE);
1162
1163 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1164 pci_unmap_page(pdev, re->frag_addr[i],
1165 skb_shinfo(skb)->frags[i].size,
1166 PCI_DMA_FROMDEVICE);
1167}
793b883e 1168
cd28ab6a
SH		 1169/* Tell chip where to start receive checksum.
1170 * Actually has two checksums, but set both same to avoid possible byte
1171 * order problems.
1172 */
793b883e 1173static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1174{
ea76e635 1175 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1176
ea76e635
SH		 1177 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1178 le->ctrl = 0;
1179 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1180
ea76e635
SH		 1181 sky2_write32(sky2->hw,
1182 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1183 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1184}
1185
6b1a3aef 1186/*
1187 * The RX Stop command will not work for Yukon-2 if the BMU does not
1188 * reach the end of packet and since we can't make sure that we have
1189 * incoming data, we must reset the BMU while it is not doing a DMA
1190 * transfer. Since it is possible that the RX path is still active,
1191 * the RX RAM buffer will be stopped first, so any possible incoming
1192 * data will not trigger a DMA. After the RAM buffer is stopped, the
1193 * BMU is polled until any DMA in progress is ended and only then it
1194 * will be reset.
1195 */
1196static void sky2_rx_stop(struct sky2_port *sky2)
1197{
1198 struct sky2_hw *hw = sky2->hw;
1199 unsigned rxq = rxqaddr[sky2->port];
1200 int i;
1201
1202 /* disable the RAM Buffer receive queue */
1203 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1204
1205 for (i = 0; i < 0xffff; i++)
1206 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1207 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1208 goto stopped;
1209
1210 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1211 sky2->netdev->name);
1212stopped:
1213 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1214
1215 /* reset the Rx prefetch unit */
1216 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1217 mmiowb();
6b1a3aef 1218}
793b883e 1219
d571b694 1220/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1221static void sky2_rx_clean(struct sky2_port *sky2)
1222{
1223 unsigned i;
1224
1225 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1226 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1227 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1228
1229 if (re->skb) {
14d0263f 1230 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1231 kfree_skb(re->skb);
1232 re->skb = NULL;
1233 }
1234 }
1235}
1236
ef743d33 1237/* Basic MII support */
1238static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1239{
1240 struct mii_ioctl_data *data = if_mii(ifr);
1241 struct sky2_port *sky2 = netdev_priv(dev);
1242 struct sky2_hw *hw = sky2->hw;
1243 int err = -EOPNOTSUPP;
1244
1245 if (!netif_running(dev))
1246 return -ENODEV; /* Phy still in reset */
1247
d89e1343 1248 switch (cmd) {
ef743d33 1249 case SIOCGMIIPHY:
1250 data->phy_id = PHY_ADDR_MARV;
1251
1252 /* fallthru */
1253 case SIOCGMIIREG: {
1254 u16 val = 0;
91c86df5 1255
e07b1aa8 1256 spin_lock_bh(&sky2->phy_lock);
ef743d33 1257 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1258 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1259
ef743d33 1260 data->val_out = val;
1261 break;
1262 }
1263
1264 case SIOCSMIIREG:
1265 if (!capable(CAP_NET_ADMIN))
1266 return -EPERM;
1267
e07b1aa8 1268 spin_lock_bh(&sky2->phy_lock);
ef743d33 1269 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1270 data->val_in);
e07b1aa8 1271 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1272 break;
1273 }
1274 return err;
1275}
1276
d1f13708 1277#ifdef SKY2_VLAN_TAG_USED
d494eacd 1278static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1279{
d494eacd 1280 if (onoff) {
3d4e66f5
SH		 1281 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1282 RX_VLAN_STRIP_ON);
1283 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1284 TX_VLAN_TAG_ON);
1285 } else {
1286 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1287 RX_VLAN_STRIP_OFF);
1288 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1289 TX_VLAN_TAG_OFF);
1290 }
d494eacd
SH		 1291}
1292
1293static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1294{
1295 struct sky2_port *sky2 = netdev_priv(dev);
1296 struct sky2_hw *hw = sky2->hw;
1297 u16 port = sky2->port;
1298
1299 netif_tx_lock_bh(dev);
1300 napi_disable(&hw->napi);
1301
1302 sky2->vlgrp = grp;
1303 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1304
d1d08d12 1305 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1306 napi_enable(&hw->napi);
2bb8c262 1307 netif_tx_unlock_bh(dev);
d1f13708 1308}
1309#endif
1310
82788c7a 1311/*
14d0263f
SH		 1312 * Allocate an skb for receiving. If the MTU is large enough
1313 * make the skb non-linear with a fragment list of pages.
82788c7a 1314 */
14d0263f 1315static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1316{
1317 struct sk_buff *skb;
14d0263f 1318 int i;
82788c7a 1319
39dbd958 1320 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1321 unsigned char *start;
1322 /*
1323 * Workaround for a bug in FIFO that cause hang
1324 * if the FIFO if the receive buffer is not 64 byte aligned.
1325 * The buffer returned from netdev_alloc_skb is
1326 * aligned except if slab debugging is enabled.
1327 */
1328 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1329 if (!skb)
1330 goto nomem;
1331 start = PTR_ALIGN(skb->data, 8);
1332 skb_reserve(skb, start - skb->data);
1333 } else {
1334 skb = netdev_alloc_skb(sky2->netdev,
1335 sky2->rx_data_size + NET_IP_ALIGN);
1336 if (!skb)
1337 goto nomem;
1338 skb_reserve(skb, NET_IP_ALIGN);
1339 }
14d0263f
SH		 1340
1341 for (i = 0; i < sky2->rx_nfrags; i++) {
1342 struct page *page = alloc_page(GFP_ATOMIC);
1343
1344 if (!page)
1345 goto free_partial;
1346 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1347 }
1348
1349 return skb;
14d0263f
SH		 1350free_partial:
1351 kfree_skb(skb);
1352nomem:
1353 return NULL;
82788c7a
SH		 1354}
1355
55c9dd35
SH		 1356static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1357{
1358 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1359}
1360
cd28ab6a
SH		 1361/*
1362 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1363 * Normal case this ends up creating one list element for skb
1364 * in the receive ring. Worst case if using large MTU and each
1365 * allocation falls on a different 64 bit region, that results
1366 * in 6 list elements per ring entry.
1367 * One element is used for checksum enable/disable, and one
1368 * extra to avoid wrap.
cd28ab6a 1369 */
6b1a3aef 1370static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1371{
6b1a3aef 1372 struct sky2_hw *hw = sky2->hw;
14d0263f 1373 struct rx_ring_info *re;
6b1a3aef 1374 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1375 unsigned i, size, thresh;
cd28ab6a 1376
6b1a3aef 1377 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1378 sky2_qset(hw, rxq);
977bdf06 1379
c3905bc4
SH		 1380 /* On PCI express lowering the watermark gives better performance */
1381 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1382 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1383
1384 /* These chips have no ram buffer?
1385 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1386 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1387 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1388 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1389 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1390
6b1a3aef 1391 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1392
ea76e635
SH		 1393 if (!(hw->flags & SKY2_HW_NEW_LE))
1394 rx_set_checksum(sky2);
14d0263f
SH		 1395
1396 /* Space needed for frame data + headers rounded up */
f957da2a 1397 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1398
1399 /* Stopping point for hardware truncation */
1400 thresh = (size - 8) / sizeof(u32);
1401
5f06eba4 1402 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1403 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1404
5f06eba4
SH		 1405 /* Compute residue after pages */
1406 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1407
5f06eba4
SH		 1408 /* Optimize to handle small packets and headers */
1409 if (size < copybreak)
1410 size = copybreak;
1411 if (size < ETH_HLEN)
1412 size = ETH_HLEN;
14d0263f 1413
14d0263f
SH		 1414 sky2->rx_data_size = size;
1415
1416 /* Fill Rx ring */
793b883e 1417 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1418 re = sky2->rx_ring + i;
cd28ab6a 1419
14d0263f 1420 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1421 if (!re->skb)
1422 goto nomem;
1423
14d0263f
SH		 1424 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1425 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1426 }
1427
a1433ac4
SH		 1428 /*
1429 * The receiver hangs if it receives frames larger than the
1430 * packet buffer. As a workaround, truncate oversize frames, but
1431 * the register is limited to 9 bits, so if you do frames > 2052
1432 * you better get the MTU right!
1433 */
a1433ac4
SH		 1434 if (thresh > 0x1ff)
1435 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1436 else {
1437 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1438 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1439 }
1440
6b1a3aef 1441 /* Tell chip about available buffers */
55c9dd35 1442 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1443 return 0;
1444nomem:
1445 sky2_rx_clean(sky2);
1446 return -ENOMEM;
1447}
1448
1449/* Bring up network interface. */
1450static int sky2_up(struct net_device *dev)
1451{
1452 struct sky2_port *sky2 = netdev_priv(dev);
1453 struct sky2_hw *hw = sky2->hw;
1454 unsigned port = sky2->port;
e0c28116 1455 u32 imask, ramsize;
ee7abb04 1456 int cap, err = -ENOMEM;
843a46f4 1457 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1458
ee7abb04
SH		 1459 /*
1460 * On dual port PCI-X card, there is an problem where status
1461 * can be received out of order due to split transactions
843a46f4 1462 */
ee7abb04
SH		 1463 if (otherdev && netif_running(otherdev) &&
1464 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1465 u16 cmd;
1466
b32f40c4 1467 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1468 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1469 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1470
ee7abb04 1471 }
843a46f4 1472
cd28ab6a
SH		 1473 if (netif_msg_ifup(sky2))
1474 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1475
55d7b4e6
SH		 1476 netif_carrier_off(dev);
1477
cd28ab6a
SH		 1478 /* must be power of 2 */
1479 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1480 TX_RING_SIZE *
1481 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1482 &sky2->tx_le_map);
1483 if (!sky2->tx_le)
1484 goto err_out;
1485
6cdbbdf3 1486 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1487 GFP_KERNEL);
1488 if (!sky2->tx_ring)
1489 goto err_out;
88f5f0ca
SH		 1490
1491 tx_init(sky2);
cd28ab6a
SH		 1492
1493 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1494 &sky2->rx_le_map);
1495 if (!sky2->rx_le)
1496 goto err_out;
1497 memset(sky2->rx_le, 0, RX_LE_BYTES);
1498
291ea614 1499 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1500 GFP_KERNEL);
1501 if (!sky2->rx_ring)
1502 goto err_out;
1503
1504 sky2_mac_init(hw, port);
1505
e0c28116
SH		 1506 /* Register is number of 4K blocks on internal RAM buffer. */
1507 ramsize = sky2_read8(hw, B2_E_0) * 4;
1508 if (ramsize > 0) {
67712901 1509 u32 rxspace;
cd28ab6a 1510
39dbd958 1511 hw->flags |= SKY2_HW_RAM_BUFFER;
e0c28116 1512 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1513 if (ramsize < 16)
1514 rxspace = ramsize / 2;
1515 else
1516 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1517
67712901
SH		 1518 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1519 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1520
1521 /* Make sure SyncQ is disabled */
1522 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1523 RB_RST_SET);
1524 }
793b883e 1525
af4ed7e6 1526 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1527
69161611
SH		 1528 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1529 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1530 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1531
977bdf06 1532 /* Set almost empty threshold */
c2716fb4
SH		 1533 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1534 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1535 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1536
6b1a3aef 1537 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1538 TX_RING_SIZE - 1);
cd28ab6a 1539
d494eacd
SH		 1540#ifdef SKY2_VLAN_TAG_USED
1541 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1542#endif
1543
6b1a3aef 1544 err = sky2_rx_start(sky2);
6de16237 1545 if (err)
cd28ab6a
SH		 1546 goto err_out;
1547
cd28ab6a 1548 /* Enable interrupts from phy/mac for port */
e07b1aa8 1549 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1550 imask |= portirq_msk[port];
e07b1aa8
SH		 1551 sky2_write32(hw, B0_IMSK, imask);
1552
a7bffe72 1553 sky2_set_multicast(dev);
cd28ab6a
SH		 1554 return 0;
1555
1556err_out:
1b537565 1557 if (sky2->rx_le) {
cd28ab6a
SH		 1558 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1559 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1560 sky2->rx_le = NULL;
1561 }
1562 if (sky2->tx_le) {
cd28ab6a
SH		 1563 pci_free_consistent(hw->pdev,
1564 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1565 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1566 sky2->tx_le = NULL;
1567 }
1568 kfree(sky2->tx_ring);
1569 kfree(sky2->rx_ring);
cd28ab6a 1570
1b537565
SH		 1571 sky2->tx_ring = NULL;
1572 sky2->rx_ring = NULL;
cd28ab6a
SH		 1573 return err;
1574}
1575
793b883e
SH		 1576/* Modular subtraction in ring */
1577static inline int tx_dist(unsigned tail, unsigned head)
1578{
cb5d9547 1579 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1580}
cd28ab6a 1581
793b883e
SH		 1582/* Number of list elements available for next tx */
1583static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1584{
793b883e 1585 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1586}
1587
793b883e 1588/* Estimate of number of transmit list elements required */
28bd181a 1589static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1590{
793b883e
SH		 1591 unsigned count;
1592
1593 count = sizeof(dma_addr_t) / sizeof(u32);
1594 count += skb_shinfo(skb)->nr_frags * count;
1595
89114afd 1596 if (skb_is_gso(skb))
793b883e
SH		 1597 ++count;
1598
84fa7933 1599 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1600 ++count;
1601
1602 return count;
cd28ab6a
SH		 1603}
1604
793b883e
SH		 1605/*
1606 * Put one packet in ring for transmit.
1607 * A single packet can generate multiple list elements, and
1608 * the number of ring elements will probably be less than the number
1609 * of list elements used.
1610 */
cd28ab6a
SH		 1611static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1612{
1613 struct sky2_port *sky2 = netdev_priv(dev);
1614 struct sky2_hw *hw = sky2->hw;
d1f13708 1615 struct sky2_tx_le *le = NULL;
6cdbbdf3 1616 struct tx_ring_info *re;
cd28ab6a
SH		 1617 unsigned i, len;
1618 dma_addr_t mapping;
cd28ab6a
SH		 1619 u16 mss;
1620 u8 ctrl;
1621
2bb8c262
SH		 1622 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1623 return NETDEV_TX_BUSY;
cd28ab6a 1624
793b883e 1625 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1626 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1627 dev->name, sky2->tx_prod, skb->len);
1628
cd28ab6a
SH		 1629 len = skb_headlen(skb);
1630 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1631
86c6887e
SH		 1632 /* Send high bits if needed */
1633 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1634 le = get_tx_le(sky2);
86c6887e 1635 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e 1636 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1637 }
cd28ab6a
SH		 1638
1639 /* Check for TCP Segmentation Offload */
7967168c 1640 mss = skb_shinfo(skb)->gso_size;
793b883e 1641 if (mss != 0) {
ea76e635
SH		 1642
1643 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1644 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1645
1646 if (mss != sky2->tx_last_mss) {
1647 le = get_tx_le(sky2);
1648 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1649
1650 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1651 le->opcode = OP_MSS | HW_OWNER;
1652 else
1653 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1654 sky2->tx_last_mss = mss;
1655 }
cd28ab6a
SH		 1656 }
1657
cd28ab6a 1658 ctrl = 0;
d1f13708 1659#ifdef SKY2_VLAN_TAG_USED
1660 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1661 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1662 if (!le) {
1663 le = get_tx_le(sky2);
f65b138c 1664 le->addr = 0;
d1f13708 1665 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1666 } else
1667 le->opcode |= OP_VLAN;
1668 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1669 ctrl |= INS_VLAN;
1670 }
1671#endif
1672
1673 /* Handle TCP checksum offload */
84fa7933 1674 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1675 /* On Yukon EX (some versions) encoding change. */
ea76e635 1676 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1677 ctrl |= CALSUM; /* auto checksum */
1678 else {
1679 const unsigned offset = skb_transport_offset(skb);
1680 u32 tcpsum;
1681
1682 tcpsum = offset << 16; /* sum start */
1683 tcpsum |= offset + skb->csum_offset; /* sum write */
1684
1685 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1686 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1687 ctrl |= UDPTCP;
1688
1689 if (tcpsum != sky2->tx_tcpsum) {
1690 sky2->tx_tcpsum = tcpsum;
1691
1692 le = get_tx_le(sky2);
1693 le->addr = cpu_to_le32(tcpsum);
1694 le->length = 0; /* initial checksum value */
1695 le->ctrl = 1; /* one packet */
1696 le->opcode = OP_TCPLISW | HW_OWNER;
1697 }
1d179332 1698 }
cd28ab6a
SH		 1699 }
1700
1701 le = get_tx_le(sky2);
f65b138c 1702 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1703 le->length = cpu_to_le16(len);
1704 le->ctrl = ctrl;
793b883e 1705 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1706
291ea614 1707 re = tx_le_re(sky2, le);
cd28ab6a 1708 re->skb = skb;
6cdbbdf3 1709 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1710 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1711
1712 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1713 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1714
1715 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1716 frag->size, PCI_DMA_TODEVICE);
86c6887e
SH		 1717
1718 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1719 le = get_tx_le(sky2);
86c6887e 1720 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e
SH		 1721 le->ctrl = 0;
1722 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1723 }
1724
1725 le = get_tx_le(sky2);
f65b138c 1726 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1727 le->length = cpu_to_le16(frag->size);
1728 le->ctrl = ctrl;
793b883e 1729 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1730
291ea614
SH		 1731 re = tx_le_re(sky2, le);
1732 re->skb = skb;
1733 pci_unmap_addr_set(re, mapaddr, mapping);
1734 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1735 }
6cdbbdf3 1736
cd28ab6a
SH		 1737 le->ctrl |= EOP;
1738
97bda706 1739 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1740 netif_stop_queue(dev);
b19666d9 1741
290d4de5 1742 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1743
cd28ab6a
SH		 1744 dev->trans_start = jiffies;
1745 return NETDEV_TX_OK;
1746}
1747
cd28ab6a 1748/*
793b883e
SH		 1749 * Free ring elements from starting at tx_cons until "done"
1750 *
1751 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1752 * buffers so make sure not to free skb to early.
cd28ab6a 1753 */
d11c13e7 1754static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1755{
d11c13e7 1756 struct net_device *dev = sky2->netdev;
af2a58ac 1757 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1758 unsigned idx;
cd28ab6a 1759
0e3ff6aa 1760 BUG_ON(done >= TX_RING_SIZE);
2224795d 1761
291ea614
SH		 1762 for (idx = sky2->tx_cons; idx != done;
1763 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1764 struct sky2_tx_le *le = sky2->tx_le + idx;
1765 struct tx_ring_info *re = sky2->tx_ring + idx;
1766
1767 switch(le->opcode & ~HW_OWNER) {
1768 case OP_LARGESEND:
1769 case OP_PACKET:
1770 pci_unmap_single(pdev,
1771 pci_unmap_addr(re, mapaddr),
1772 pci_unmap_len(re, maplen),
1773 PCI_DMA_TODEVICE);
af2a58ac 1774 break;
291ea614
SH		 1775 case OP_BUFFER:
1776 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1777 pci_unmap_len(re, maplen),
734d1868 1778 PCI_DMA_TODEVICE);
291ea614
SH		 1779 break;
1780 }
1781
1782 if (le->ctrl & EOP) {
1783 if (unlikely(netif_msg_tx_done(sky2)))
1784 printk(KERN_DEBUG "%s: tx done %u\n",
1785 dev->name, idx);
3cf26753 1786
7138a0f5
SH		 1787 dev->stats.tx_packets++;
1788 dev->stats.tx_bytes += re->skb->len;
2bf56fe2 1789
794b2bd2 1790 dev_kfree_skb_any(re->skb);
3cf26753 1791 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1792 }
793b883e 1793 }
793b883e 1794
291ea614 1795 sky2->tx_cons = idx;
50432cb5
SH		 1796 smp_mb();
1797
22e11703 1798 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1799 netif_wake_queue(dev);
cd28ab6a
SH		 1800}
1801
1802/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1803static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1804{
2bb8c262
SH		 1805 struct sky2_port *sky2 = netdev_priv(dev);
1806
1807 netif_tx_lock_bh(dev);
d11c13e7 1808 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1809 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1810}
1811
1812/* Network shutdown */
1813static int sky2_down(struct net_device *dev)
1814{
1815 struct sky2_port *sky2 = netdev_priv(dev);
1816 struct sky2_hw *hw = sky2->hw;
1817 unsigned port = sky2->port;
1818 u16 ctrl;
e07b1aa8 1819 u32 imask;
cd28ab6a 1820
1b537565
SH		 1821 /* Never really got started! */
1822 if (!sky2->tx_le)
1823 return 0;
1824
cd28ab6a
SH		 1825 if (netif_msg_ifdown(sky2))
1826 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1827
018d1c66 1828 /* Stop more packets from being queued */
cd28ab6a
SH		 1829 netif_stop_queue(dev);
1830
ebc646f6
SH		 1831 /* Disable port IRQ */
1832 imask = sky2_read32(hw, B0_IMSK);
1833 imask &= ~portirq_msk[port];
1834 sky2_write32(hw, B0_IMSK, imask);
1835
6de16237
SH		 1836 synchronize_irq(hw->pdev->irq);
1837
d3bcfbeb 1838 sky2_gmac_reset(hw, port);
793b883e 1839
cd28ab6a
SH		 1840 /* Stop transmitter */
1841 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1842 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1843
1844 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1845 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1846
1847 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1848 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1849 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1850
6de16237
SH		 1851 /* Make sure no packets are pending */
1852 napi_synchronize(&hw->napi);
1853
cd28ab6a
SH		 1854 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1855
1856 /* Workaround shared GMAC reset */
793b883e
SH		 1857 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1858 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1859 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1860
1861 /* Disable Force Sync bit and Enable Alloc bit */
1862 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1863 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1864
1865 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1866 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1867 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1868
1869 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1870 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1871 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1872
1873 /* Reset the Tx prefetch units */
1874 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1875 PREF_UNIT_RST_SET);
1876
1877 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1878
6b1a3aef 1879 sky2_rx_stop(sky2);
cd28ab6a
SH		 1880
1881 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1882 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1883
b96936da 1884 sky2_phy_power_down(hw, port);
d3bcfbeb 1885
55d7b4e6
SH		 1886 netif_carrier_off(dev);
1887
d571b694 1888 /* turn off LED's */
cd28ab6a
SH		 1889 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1890
2bb8c262 1891 sky2_tx_clean(dev);
cd28ab6a
SH		 1892 sky2_rx_clean(sky2);
1893
1894 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1895 sky2->rx_le, sky2->rx_le_map);
1896 kfree(sky2->rx_ring);
1897
1898 pci_free_consistent(hw->pdev,
1899 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1900 sky2->tx_le, sky2->tx_le_map);
1901 kfree(sky2->tx_ring);
1902
1b537565
SH		 1903 sky2->tx_le = NULL;
1904 sky2->rx_le = NULL;
1905
1906 sky2->rx_ring = NULL;
1907 sky2->tx_ring = NULL;
1908
cd28ab6a
SH		 1909 return 0;
1910}
1911
1912static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1913{
ea76e635 1914 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1915 return SPEED_1000;
1916
05745c4a
SH		 1917 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1918 if (aux & PHY_M_PS_SPEED_100)
1919 return SPEED_100;
1920 else
1921 return SPEED_10;
1922 }
cd28ab6a
SH		 1923
1924 switch (aux & PHY_M_PS_SPEED_MSK) {
1925 case PHY_M_PS_SPEED_1000:
1926 return SPEED_1000;
1927 case PHY_M_PS_SPEED_100:
1928 return SPEED_100;
1929 default:
1930 return SPEED_10;
1931 }
1932}
1933
1934static void sky2_link_up(struct sky2_port *sky2)
1935{
1936 struct sky2_hw *hw = sky2->hw;
1937 unsigned port = sky2->port;
1938 u16 reg;
16ad91e1
SH		 1939 static const char *fc_name[] = {
1940 [FC_NONE] = "none",
1941 [FC_TX] = "tx",
1942 [FC_RX] = "rx",
1943 [FC_BOTH] = "both",
1944 };
cd28ab6a 1945
cd28ab6a 1946 /* enable Rx/Tx */
2eaba1a2 1947 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1948 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1949 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1950
1951 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1952
1953 netif_carrier_on(sky2->netdev);
cd28ab6a 1954
75e80683 1955 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1956
cd28ab6a 1957 /* Turn on link LED */
793b883e 1958 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1959 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1960
1961 if (netif_msg_link(sky2))
1962 printk(KERN_INFO PFX
d571b694 1963 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1964 sky2->netdev->name, sky2->speed,
1965 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1966 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1967}
1968
1969static void sky2_link_down(struct sky2_port *sky2)
1970{
1971 struct sky2_hw *hw = sky2->hw;
1972 unsigned port = sky2->port;
1973 u16 reg;
1974
1975 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1976
1977 reg = gma_read16(hw, port, GM_GP_CTRL);
1978 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1979 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1980
cd28ab6a 1981 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1982
1983 /* Turn on link LED */
1984 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1985
1986 if (netif_msg_link(sky2))
1987 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1988
cd28ab6a
SH		 1989 sky2_phy_init(hw, port);
1990}
1991
16ad91e1
SH		 1992static enum flow_control sky2_flow(int rx, int tx)
1993{
1994 if (rx)
1995 return tx ? FC_BOTH : FC_RX;
1996 else
1997 return tx ? FC_TX : FC_NONE;
1998}
1999
793b883e
SH		 2000static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2001{
2002 struct sky2_hw *hw = sky2->hw;
2003 unsigned port = sky2->port;
da4c1ff4 2004 u16 advert, lpa;
793b883e 2005
da4c1ff4 2006 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2007 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 2008 if (lpa & PHY_M_AN_RF) {
2009 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2010 return -1;
2011 }
2012
793b883e
SH		 2013 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2014 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2015 sky2->netdev->name);
2016 return -1;
2017 }
2018
793b883e 2019 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2020 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2021
da4c1ff4
SH		 2022 /* Since the pause result bits seem to in different positions on
2023 * different chips. look at registers.
2024 */
ea76e635 2025 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2026 /* Shift for bits in fiber PHY */
2027 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2028 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2029
2030 if (advert & ADVERTISE_1000XPAUSE)
2031 advert |= ADVERTISE_PAUSE_CAP;
2032 if (advert & ADVERTISE_1000XPSE_ASYM)
2033 advert |= ADVERTISE_PAUSE_ASYM;
2034 if (lpa & LPA_1000XPAUSE)
2035 lpa |= LPA_PAUSE_CAP;
2036 if (lpa & LPA_1000XPAUSE_ASYM)
2037 lpa |= LPA_PAUSE_ASYM;
2038 }
793b883e 2039
da4c1ff4
SH		 2040 sky2->flow_status = FC_NONE;
2041 if (advert & ADVERTISE_PAUSE_CAP) {
2042 if (lpa & LPA_PAUSE_CAP)
2043 sky2->flow_status = FC_BOTH;
2044 else if (advert & ADVERTISE_PAUSE_ASYM)
2045 sky2->flow_status = FC_RX;
2046 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2047 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2048 sky2->flow_status = FC_TX;
2049 }
793b883e 2050
16ad91e1 2051 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 2052 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2053 sky2->flow_status = FC_NONE;
2eaba1a2 2054
da4c1ff4 2055 if (sky2->flow_status & FC_TX)
793b883e
SH		 2056 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2057 else
2058 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2059
2060 return 0;
2061}
cd28ab6a 2062
e07b1aa8
SH		 2063/* Interrupt from PHY */
2064static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2065{
e07b1aa8
SH		 2066 struct net_device *dev = hw->dev[port];
2067 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2068 u16 istatus, phystat;
2069
ebc646f6
SH		 2070 if (!netif_running(dev))
2071 return;
2072
e07b1aa8
SH		 2073 spin_lock(&sky2->phy_lock);
2074 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2075 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2076
cd28ab6a
SH		 2077 if (netif_msg_intr(sky2))
2078 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2079 sky2->netdev->name, istatus, phystat);
2080
2eaba1a2 2081 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 2082 if (sky2_autoneg_done(sky2, phystat) == 0)
2083 sky2_link_up(sky2);
2084 goto out;
2085 }
cd28ab6a 2086
793b883e
SH		 2087 if (istatus & PHY_M_IS_LSP_CHANGE)
2088 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2089
793b883e
SH		 2090 if (istatus & PHY_M_IS_DUP_CHANGE)
2091 sky2->duplex =
2092 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2093
793b883e
SH		 2094 if (istatus & PHY_M_IS_LST_CHANGE) {
2095 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2096 sky2_link_up(sky2);
793b883e
SH		 2097 else
2098 sky2_link_down(sky2);
cd28ab6a 2099 }
793b883e 2100out:
e07b1aa8 2101 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2102}
2103
62335ab0 2104/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2105 * and tx queue is full (stopped).
2106 */
cd28ab6a
SH		 2107static void sky2_tx_timeout(struct net_device *dev)
2108{
2109 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2110 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2111
2112 if (netif_msg_timer(sky2))
2113 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2114
8f24664d 2115 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2116 dev->name, sky2->tx_cons, sky2->tx_prod,
2117 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2118 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2119
81906791
SH		 2120 /* can't restart safely under softirq */
2121 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2122}
2123
2124static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2125{
6b1a3aef 2126 struct sky2_port *sky2 = netdev_priv(dev);
2127 struct sky2_hw *hw = sky2->hw;
b628ed98 2128 unsigned port = sky2->port;
6b1a3aef 2129 int err;
2130 u16 ctl, mode;
e07b1aa8 2131 u32 imask;
cd28ab6a
SH		 2132
2133 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2134 return -EINVAL;
2135
05745c4a
SH		 2136 if (new_mtu > ETH_DATA_LEN &&
2137 (hw->chip_id == CHIP_ID_YUKON_FE ||
2138 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2139 return -EINVAL;
2140
6b1a3aef 2141 if (!netif_running(dev)) {
2142 dev->mtu = new_mtu;
2143 return 0;
2144 }
2145
e07b1aa8 2146 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 2147 sky2_write32(hw, B0_IMSK, 0);
2148
018d1c66 2149 dev->trans_start = jiffies; /* prevent tx timeout */
2150 netif_stop_queue(dev);
bea3348e 2151 napi_disable(&hw->napi);
018d1c66 2152
e07b1aa8
SH		 2153 synchronize_irq(hw->pdev->irq);
2154
39dbd958 2155 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2156 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2157
2158 ctl = gma_read16(hw, port, GM_GP_CTRL);
2159 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 2160 sky2_rx_stop(sky2);
2161 sky2_rx_clean(sky2);
cd28ab6a
SH		 2162
2163 dev->mtu = new_mtu;
14d0263f 2164
6b1a3aef 2165 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2166 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2167
2168 if (dev->mtu > ETH_DATA_LEN)
2169 mode |= GM_SMOD_JUMBO_ENA;
2170
b628ed98 2171 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2172
b628ed98 2173 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2174
6b1a3aef 2175 err = sky2_rx_start(sky2);
e07b1aa8 2176 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2177
d1d08d12 2178 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2179 napi_enable(&hw->napi);
2180
1b537565
SH		 2181 if (err)
2182 dev_close(dev);
2183 else {
b628ed98 2184 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2185
1b537565
SH		 2186 netif_wake_queue(dev);
2187 }
2188
cd28ab6a
SH		 2189 return err;
2190}
2191
14d0263f
SH		 2192/* For small just reuse existing skb for next receive */
2193static struct sk_buff *receive_copy(struct sky2_port *sky2,
2194 const struct rx_ring_info *re,
2195 unsigned length)
2196{
2197 struct sk_buff *skb;
2198
2199 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2200 if (likely(skb)) {
2201 skb_reserve(skb, 2);
2202 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2203 length, PCI_DMA_FROMDEVICE);
d626f62b 2204 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2205 skb->ip_summed = re->skb->ip_summed;
2206 skb->csum = re->skb->csum;
2207 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2208 length, PCI_DMA_FROMDEVICE);
2209 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2210 skb_put(skb, length);
14d0263f
SH		 2211 }
2212 return skb;
2213}
2214
2215/* Adjust length of skb with fragments to match received data */
2216static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2217 unsigned int length)
2218{
2219 int i, num_frags;
2220 unsigned int size;
2221
2222 /* put header into skb */
2223 size = min(length, hdr_space);
2224 skb->tail += size;
2225 skb->len += size;
2226 length -= size;
2227
2228 num_frags = skb_shinfo(skb)->nr_frags;
2229 for (i = 0; i < num_frags; i++) {
2230 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2231
2232 if (length == 0) {
2233 /* don't need this page */
2234 __free_page(frag->page);
2235 --skb_shinfo(skb)->nr_frags;
2236 } else {
2237 size = min(length, (unsigned) PAGE_SIZE);
2238
2239 frag->size = size;
2240 skb->data_len += size;
2241 skb->truesize += size;
2242 skb->len += size;
2243 length -= size;
2244 }
2245 }
2246}
2247
2248/* Normal packet - take skb from ring element and put in a new one */
2249static struct sk_buff *receive_new(struct sky2_port *sky2,
2250 struct rx_ring_info *re,
2251 unsigned int length)
2252{
2253 struct sk_buff *skb, *nskb;
2254 unsigned hdr_space = sky2->rx_data_size;
2255
14d0263f
SH		 2256 /* Don't be tricky about reusing pages (yet) */
2257 nskb = sky2_rx_alloc(sky2);
2258 if (unlikely(!nskb))
2259 return NULL;
2260
2261 skb = re->skb;
2262 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2263
2264 prefetch(skb->data);
2265 re->skb = nskb;
2266 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2267
2268 if (skb_shinfo(skb)->nr_frags)
2269 skb_put_frags(skb, hdr_space, length);
2270 else
489b10c1 2271 skb_put(skb, length);
14d0263f
SH		 2272 return skb;
2273}
2274
cd28ab6a
SH		 2275/*
2276 * Receive one packet.
d571b694 2277 * For larger packets, get new buffer.
cd28ab6a 2278 */
497d7c86 2279static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2280 u16 length, u32 status)
2281{
497d7c86 2282 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2283 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2284 struct sk_buff *skb = NULL;
d6532232
SH		 2285 u16 count = (status & GMR_FS_LEN) >> 16;
2286
2287#ifdef SKY2_VLAN_TAG_USED
2288 /* Account for vlan tag */
2289 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2290 count -= VLAN_HLEN;
2291#endif
cd28ab6a
SH		 2292
2293 if (unlikely(netif_msg_rx_status(sky2)))
2294 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2295 dev->name, sky2->rx_next, status, length);
cd28ab6a 2296
793b883e 2297 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2298 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2299
3b12e014
SH		 2300 /* This chip has hardware problems that generates bogus status.
2301 * So do only marginal checking and expect higher level protocols
2302 * to handle crap frames.
2303 */
2304 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2305 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2306 length != count)
2307 goto okay;
2308
42eeea01 2309 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2310 goto error;
2311
42eeea01 2312 if (!(status & GMR_FS_RX_OK))
2313 goto resubmit;
2314
d6532232
SH		 2315 /* if length reported by DMA does not match PHY, packet was truncated */
2316 if (length != count)
3b12e014 2317 goto len_error;
71749531 2318
3b12e014 2319okay:
14d0263f
SH		 2320 if (length < copybreak)
2321 skb = receive_copy(sky2, re, length);
2322 else
2323 skb = receive_new(sky2, re, length);
793b883e 2324resubmit:
14d0263f 2325 sky2_rx_submit(sky2, re);
79e57d32 2326
cd28ab6a
SH		 2327 return skb;
2328
3b12e014 2329len_error:
71749531
SH		 2330 /* Truncation of overlength packets
2331 causes PHY length to not match MAC length */
7138a0f5 2332 ++dev->stats.rx_length_errors;
d6532232 2333 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2334 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2335 dev->name, status, length);
d6532232 2336 goto resubmit;
71749531 2337
cd28ab6a 2338error:
7138a0f5 2339 ++dev->stats.rx_errors;
b6d77734 2340 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2341 dev->stats.rx_over_errors++;
b6d77734
SH		 2342 goto resubmit;
2343 }
6e15b712 2344
3be92a70 2345 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2346 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2347 dev->name, status, length);
793b883e
SH		 2348
2349 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2350 dev->stats.rx_length_errors++;
cd28ab6a 2351 if (status & GMR_FS_FRAGMENT)
7138a0f5 2352 dev->stats.rx_frame_errors++;
cd28ab6a 2353 if (status & GMR_FS_CRC_ERR)
7138a0f5 2354 dev->stats.rx_crc_errors++;
79e57d32 2355
793b883e 2356 goto resubmit;
cd28ab6a
SH		 2357}
2358
e07b1aa8
SH		 2359/* Transmit complete */
2360static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2361{
e07b1aa8 2362 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2363
e07b1aa8 2364 if (netif_running(dev)) {
2bb8c262 2365 netif_tx_lock(dev);
e07b1aa8 2366 sky2_tx_complete(sky2, last);
2bb8c262 2367 netif_tx_unlock(dev);
2224795d 2368 }
cd28ab6a
SH		 2369}
2370
e07b1aa8 2371/* Process status response ring */
26691830 2372static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2373{
e07b1aa8 2374 int work_done = 0;
55c9dd35 2375 unsigned rx[2] = { 0, 0 };
a8fd6266 2376
af2a58ac 2377 rmb();
26691830 2378 do {
55c9dd35 2379 struct sky2_port *sky2;
13210ce5 2380 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2381 unsigned port;
13210ce5 2382 struct net_device *dev;
cd28ab6a 2383 struct sk_buff *skb;
cd28ab6a
SH		 2384 u32 status;
2385 u16 length;
ab5adecb
SH		 2386 u8 opcode = le->opcode;
2387
2388 if (!(opcode & HW_OWNER))
2389 break;
cd28ab6a 2390
cb5d9547 2391 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2392
ab5adecb 2393 port = le->css & CSS_LINK_BIT;
69161611 2394 dev = hw->dev[port];
13210ce5 2395 sky2 = netdev_priv(dev);
f65b138c
SH		 2396 length = le16_to_cpu(le->length);
2397 status = le32_to_cpu(le->status);
cd28ab6a 2398
ab5adecb
SH		 2399 le->opcode = 0;
2400 switch (opcode & ~HW_OWNER) {
cd28ab6a 2401 case OP_RXSTAT:
55c9dd35 2402 ++rx[port];
497d7c86 2403 skb = sky2_receive(dev, length, status);
3225b919 2404 if (unlikely(!skb)) {
7138a0f5 2405 dev->stats.rx_dropped++;
55c9dd35 2406 break;
3225b919 2407 }
13210ce5 2408
69161611 2409 /* This chip reports checksum status differently */
05745c4a 2410 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2411 if (sky2->rx_csum &&
2412 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2413 (le->css & CSS_TCPUDPCSOK))
2414 skb->ip_summed = CHECKSUM_UNNECESSARY;
2415 else
2416 skb->ip_summed = CHECKSUM_NONE;
2417 }
2418
13210ce5 2419 skb->protocol = eth_type_trans(skb, dev);
7138a0f5
SH		 2420 dev->stats.rx_packets++;
2421 dev->stats.rx_bytes += skb->len;
13210ce5 2422 dev->last_rx = jiffies;
2423
d1f13708 2424#ifdef SKY2_VLAN_TAG_USED
2425 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2426 vlan_hwaccel_receive_skb(skb,
2427 sky2->vlgrp,
2428 be16_to_cpu(sky2->rx_tag));
2429 } else
2430#endif
cd28ab6a 2431 netif_receive_skb(skb);
13210ce5 2432
22e11703 2433 /* Stop after net poll weight */
13210ce5 2434 if (++work_done >= to_do)
2435 goto exit_loop;
cd28ab6a
SH		 2436 break;
2437
d1f13708 2438#ifdef SKY2_VLAN_TAG_USED
2439 case OP_RXVLAN:
2440 sky2->rx_tag = length;
2441 break;
2442
2443 case OP_RXCHKSVLAN:
2444 sky2->rx_tag = length;
2445 /* fall through */
2446#endif
cd28ab6a 2447 case OP_RXCHKS:
87418307
SH		 2448 if (!sky2->rx_csum)
2449 break;
2450
05745c4a
SH		 2451 /* If this happens then driver assuming wrong format */
2452 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2453 if (net_ratelimit())
2454 printk(KERN_NOTICE "%s: unexpected"
2455 " checksum status\n",
2456 dev->name);
69161611 2457 break;
05745c4a 2458 }
69161611 2459
87418307
SH		 2460 /* Both checksum counters are programmed to start at
2461 * the same offset, so unless there is a problem they
2462 * should match. This failure is an early indication that
2463 * hardware receive checksumming won't work.
2464 */
2465 if (likely(status >> 16 == (status & 0xffff))) {
2466 skb = sky2->rx_ring[sky2->rx_next].skb;
2467 skb->ip_summed = CHECKSUM_COMPLETE;
2468 skb->csum = status & 0xffff;
2469 } else {
2470 printk(KERN_NOTICE PFX "%s: hardware receive "
2471 "checksum problem (status = %#x)\n",
2472 dev->name, status);
2473 sky2->rx_csum = 0;
2474 sky2_write32(sky2->hw,
69161611 2475 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2476 BMU_DIS_RX_CHKSUM);
2477 }
cd28ab6a
SH		 2478 break;
2479
2480 case OP_TXINDEXLE:
13b97b74 2481 /* TX index reports status for both ports */
f55925d7
SH		 2482 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2483 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2484 if (hw->dev[1])
2485 sky2_tx_done(hw->dev[1],
2486 ((status >> 24) & 0xff)
2487 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2488 break;
2489
cd28ab6a
SH		 2490 default:
2491 if (net_ratelimit())
793b883e 2492 printk(KERN_WARNING PFX
ab5adecb 2493 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2494 }
26691830 2495 } while (hw->st_idx != idx);
cd28ab6a 2496
fe2a24df
SH		 2497 /* Fully processed status ring so clear irq */
2498 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2499
13210ce5 2500exit_loop:
55c9dd35
SH		 2501 if (rx[0])
2502 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2503
55c9dd35
SH		 2504 if (rx[1])
2505 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2506
e07b1aa8 2507 return work_done;
cd28ab6a
SH		 2508}
2509
2510static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2511{
2512 struct net_device *dev = hw->dev[port];
2513
3be92a70
SH		 2514 if (net_ratelimit())
2515 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2516 dev->name, status);
cd28ab6a
SH		 2517
2518 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2519 if (net_ratelimit())
2520 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2521 dev->name);
cd28ab6a
SH		 2522 /* Clear IRQ */
2523 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2524 }
2525
2526 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2527 if (net_ratelimit())
2528 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2529 dev->name);
cd28ab6a
SH		 2530
2531 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2532 }
2533
2534 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2535 if (net_ratelimit())
2536 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2537 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2538 }
2539
2540 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2541 if (net_ratelimit())
2542 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2543 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2544 }
2545
2546 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2547 if (net_ratelimit())
2548 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2549 dev->name);
cd28ab6a
SH		 2550 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2551 }
2552}
2553
2554static void sky2_hw_intr(struct sky2_hw *hw)
2555{
555382cb 2556 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2557 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2558 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2559
2560 status &= hwmsk;
cd28ab6a 2561
793b883e 2562 if (status & Y2_IS_TIST_OV)
cd28ab6a 2563 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2564
2565 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2566 u16 pci_err;
2567
82637e80 2568 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2569 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2570 if (net_ratelimit())
555382cb 2571 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2572 pci_err);
cd28ab6a 2573
b32f40c4 2574 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2575 pci_err | PCI_STATUS_ERROR_BITS);
82637e80 2576 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2577 }
2578
2579 if (status & Y2_IS_PCI_EXP) {
d571b694 2580 /* PCI-Express uncorrectable Error occurred */
555382cb 2581 u32 err;
cd28ab6a 2582
82637e80 2583 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2584 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2585 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2586 0xfffffffful);
3be92a70 2587 if (net_ratelimit())
555382cb 2588 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2589
7782c8c4 2590 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
82637e80 2591 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2592 }
2593
2594 if (status & Y2_HWE_L1_MASK)
2595 sky2_hw_error(hw, 0, status);
2596 status >>= 8;
2597 if (status & Y2_HWE_L1_MASK)
2598 sky2_hw_error(hw, 1, status);
2599}
2600
2601static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2602{
2603 struct net_device *dev = hw->dev[port];
2604 struct sky2_port *sky2 = netdev_priv(dev);
2605 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2606
2607 if (netif_msg_intr(sky2))
2608 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2609 dev->name, status);
2610
a3caeada
SH		 2611 if (status & GM_IS_RX_CO_OV)
2612 gma_read16(hw, port, GM_RX_IRQ_SRC);
2613
2614 if (status & GM_IS_TX_CO_OV)
2615 gma_read16(hw, port, GM_TX_IRQ_SRC);
2616
cd28ab6a 2617 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2618 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2619 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2620 }
2621
2622 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2623 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2624 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2625 }
cd28ab6a
SH		 2626}
2627
40b01727
SH		 2628/* This should never happen it is a bug. */
2629static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2630 u16 q, unsigned ring_size)
d257924e
SH		 2631{
2632 struct net_device *dev = hw->dev[port];
2633 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2634 unsigned idx;
2635 const u64 *le = (q == Q_R1 || q == Q_R2)
2636 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2637
40b01727
SH		 2638 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2639 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2640 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2641 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2642
40b01727 2643 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2644}
cd28ab6a 2645
75e80683
SH		 2646static int sky2_rx_hung(struct net_device *dev)
2647{
2648 struct sky2_port *sky2 = netdev_priv(dev);
2649 struct sky2_hw *hw = sky2->hw;
2650 unsigned port = sky2->port;
2651 unsigned rxq = rxqaddr[port];
2652 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2653 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2654 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2655 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2656
2657 /* If idle and MAC or PCI is stuck */
2658 if (sky2->check.last == dev->last_rx &&
2659 ((mac_rp == sky2->check.mac_rp &&
2660 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2661 /* Check if the PCI RX hang */
2662 (fifo_rp == sky2->check.fifo_rp &&
2663 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2664 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2665 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2666 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2667 return 1;
2668 } else {
2669 sky2->check.last = dev->last_rx;
2670 sky2->check.mac_rp = mac_rp;
2671 sky2->check.mac_lev = mac_lev;
2672 sky2->check.fifo_rp = fifo_rp;
2673 sky2->check.fifo_lev = fifo_lev;
2674 return 0;
2675 }
2676}
2677
32c2c300 2678static void sky2_watchdog(unsigned long arg)
d27ed387 2679{
01bd7564 2680 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2681
75e80683 2682 /* Check for lost IRQ once a second */
32c2c300 2683 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2684 napi_schedule(&hw->napi);
75e80683
SH		 2685 } else {
2686 int i, active = 0;
2687
2688 for (i = 0; i < hw->ports; i++) {
bea3348e 2689 struct net_device *dev = hw->dev[i];
75e80683
SH		 2690 if (!netif_running(dev))
2691 continue;
2692 ++active;
2693
2694 /* For chips with Rx FIFO, check if stuck */
39dbd958 2695 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2696 sky2_rx_hung(dev)) {
2697 pr_info(PFX "%s: receiver hang detected\n",
2698 dev->name);
2699 schedule_work(&hw->restart_work);
2700 return;
2701 }
2702 }
2703
2704 if (active == 0)
2705 return;
32c2c300 2706 }
01bd7564 2707
75e80683 2708 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2709}
2710
40b01727
SH		 2711/* Hardware/software error handling */
2712static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2713{
40b01727
SH		 2714 if (net_ratelimit())
2715 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2716
1e5f1283
SH		 2717 if (status & Y2_IS_HW_ERR)
2718 sky2_hw_intr(hw);
d257924e 2719
1e5f1283
SH		 2720 if (status & Y2_IS_IRQ_MAC1)
2721 sky2_mac_intr(hw, 0);
cd28ab6a 2722
1e5f1283
SH		 2723 if (status & Y2_IS_IRQ_MAC2)
2724 sky2_mac_intr(hw, 1);
cd28ab6a 2725
1e5f1283 2726 if (status & Y2_IS_CHK_RX1)
40b01727 2727 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2728
1e5f1283 2729 if (status & Y2_IS_CHK_RX2)
40b01727 2730 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2731
1e5f1283 2732 if (status & Y2_IS_CHK_TXA1)
40b01727 2733 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2734
1e5f1283 2735 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2736 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2737}
2738
bea3348e 2739static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2740{
bea3348e 2741 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2742 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2743 int work_done = 0;
26691830 2744 u16 idx;
40b01727
SH		 2745
2746 if (unlikely(status & Y2_IS_ERROR))
2747 sky2_err_intr(hw, status);
2748
2749 if (status & Y2_IS_IRQ_PHY1)
2750 sky2_phy_intr(hw, 0);
2751
2752 if (status & Y2_IS_IRQ_PHY2)
2753 sky2_phy_intr(hw, 1);
cd28ab6a 2754
26691830
SH		 2755 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2756 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2757
2758 if (work_done >= work_limit)
26691830
SH		 2759 goto done;
2760 }
6f535763 2761
26691830
SH		 2762 /* Bug/Errata workaround?
2763 * Need to kick the TX irq moderation timer.
2764 */
2765 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2766 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2767 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2768 }
26691830
SH		 2769 napi_complete(napi);
2770 sky2_read32(hw, B0_Y2_SP_LISR);
2771done:
6f535763 2772
bea3348e 2773 return work_done;
e07b1aa8
SH		 2774}
2775
7d12e780 2776static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2777{
2778 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2779 u32 status;
2780
2781 /* Reading this mask interrupts as side effect */
2782 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2783 if (status == 0 || status == ~0)
2784 return IRQ_NONE;
793b883e 2785
e07b1aa8 2786 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2787
2788 napi_schedule(&hw->napi);
793b883e 2789
cd28ab6a
SH		 2790 return IRQ_HANDLED;
2791}
2792
2793#ifdef CONFIG_NET_POLL_CONTROLLER
2794static void sky2_netpoll(struct net_device *dev)
2795{
2796 struct sky2_port *sky2 = netdev_priv(dev);
2797
bea3348e 2798 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2799}
2800#endif
2801
2802/* Chip internal frequency for clock calculations */
05745c4a 2803static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2804{
793b883e 2805 switch (hw->chip_id) {
cd28ab6a 2806 case CHIP_ID_YUKON_EC:
5a5b1ea0 2807 case CHIP_ID_YUKON_EC_U:
93745494 2808 case CHIP_ID_YUKON_EX:
ed4d4161 2809 case CHIP_ID_YUKON_SUPR:
05745c4a
SH		 2810 return 125;
2811
cd28ab6a 2812 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2813 return 100;
2814
2815 case CHIP_ID_YUKON_FE_P:
2816 return 50;
2817
2818 case CHIP_ID_YUKON_XL:
2819 return 156;
2820
2821 default:
2822 BUG();
cd28ab6a
SH		 2823 }
2824}
2825
fb17358f 2826static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2827{
fb17358f 2828 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2829}
2830
fb17358f 2831static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2832{
fb17358f 2833 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2834}
2835
fb17358f 2836
e3173832 2837static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2838{
b89165f2 2839 u8 t8;
cd28ab6a 2840
167f53d0 2841 /* Enable all clocks and check for bad PCI access */
b32f40c4 2842 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2843
cd28ab6a 2844 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2845
cd28ab6a 2846 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2847 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2848
2849 switch(hw->chip_id) {
2850 case CHIP_ID_YUKON_XL:
39dbd958 2851 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2852 break;
2853
2854 case CHIP_ID_YUKON_EC_U:
2855 hw->flags = SKY2_HW_GIGABIT
2856 | SKY2_HW_NEWER_PHY
2857 | SKY2_HW_ADV_POWER_CTL;
a068c0ad
SH		 2858
2859 /* check for Rev. A1 dev 4200 */
2860 if (sky2_read16(hw, Q_ADDR(Q_XA1, Q_WM)) == 0)
2861 hw->flags |= SKY2_HW_CLK_POWER;
ea76e635
SH		 2862 break;
2863
2864 case CHIP_ID_YUKON_EX:
2865 hw->flags = SKY2_HW_GIGABIT
2866 | SKY2_HW_NEWER_PHY
2867 | SKY2_HW_NEW_LE
2868 | SKY2_HW_ADV_POWER_CTL;
2869
2870 /* New transmit checksum */
2871 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2872 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2873 break;
2874
2875 case CHIP_ID_YUKON_EC:
2876 /* This rev is really old, and requires untested workarounds */
2877 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2878 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2879 return -EOPNOTSUPP;
2880 }
39dbd958 2881 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2882 break;
2883
2884 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2885 break;
2886
05745c4a
SH		 2887 case CHIP_ID_YUKON_FE_P:
2888 hw->flags = SKY2_HW_NEWER_PHY
2889 | SKY2_HW_NEW_LE
2890 | SKY2_HW_AUTO_TX_SUM
2891 | SKY2_HW_ADV_POWER_CTL;
2892 break;
ed4d4161
SH		 2893
2894 case CHIP_ID_YUKON_SUPR:
2895 hw->flags = SKY2_HW_GIGABIT
2896 | SKY2_HW_NEWER_PHY
2897 | SKY2_HW_NEW_LE
2898 | SKY2_HW_AUTO_TX_SUM
2899 | SKY2_HW_ADV_POWER_CTL;
2900 break;
2901
ea76e635 2902 default:
b02a9258
SH		 2903 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2904 hw->chip_id);
cd28ab6a
SH		 2905 return -EOPNOTSUPP;
2906 }
2907
ea76e635
SH		 2908 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2909 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2910 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2911
a068c0ad
SH		 2912 hw->pm_cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PM);
2913 if (hw->pm_cap == 0) {
2914 dev_err(&hw->pdev->dev, "cannot find PowerManagement capability\n");
2915 return -EIO;
2916 }
290d4de5 2917
e3173832
SH		 2918 hw->ports = 1;
2919 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2920 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2921 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2922 ++hw->ports;
2923 }
2924
2925 return 0;
2926}
2927
2928static void sky2_reset(struct sky2_hw *hw)
2929{
555382cb 2930 struct pci_dev *pdev = hw->pdev;
e3173832 2931 u16 status;
555382cb
SH		 2932 int i, cap;
2933 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2934
cd28ab6a 2935 /* disable ASF */
4f44d8ba
SH		 2936 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2937 status = sky2_read16(hw, HCU_CCSR);
2938 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2939 HCU_CCSR_UC_STATE_MSK);
2940 sky2_write16(hw, HCU_CCSR, status);
2941 } else
2942 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2943 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2944
2945 /* do a SW reset */
2946 sky2_write8(hw, B0_CTST, CS_RST_SET);
2947 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2948
ac93a394
SH		 2949 /* allow writes to PCI config */
2950 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2951
cd28ab6a 2952 /* clear PCI errors, if any */
b32f40c4 2953 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2954 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2955 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2956
2957 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2958
555382cb
SH		 2959 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2960 if (cap) {
7782c8c4
SH		 2961 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2962 0xfffffffful);
555382cb
SH		 2963
2964 /* If error bit is stuck on ignore it */
2965 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2966 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2967 else
555382cb
SH		 2968 hwe_mask |= Y2_IS_PCI_EXP;
2969 }
cd28ab6a 2970
ae306cca 2971 sky2_power_on(hw);
82637e80 2972 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2973
2974 for (i = 0; i < hw->ports; i++) {
2975 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2976 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 2977
ed4d4161
SH		 2978 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2979 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 2980 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2981 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2982 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2983 }
2984
793b883e
SH		 2985 /* Clear I2C IRQ noise */
2986 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2987
2988 /* turn off hardware timer (unused) */
2989 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2990 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2991
cd28ab6a
SH		 2992 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2993
69634ee7
SH		 2994 /* Turn off descriptor polling */
2995 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2996
2997 /* Turn off receive timestamp */
2998 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2999 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3000
3001 /* enable the Tx Arbiters */
3002 for (i = 0; i < hw->ports; i++)
3003 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3004
3005 /* Initialize ram interface */
3006 for (i = 0; i < hw->ports; i++) {
793b883e 3007 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3008
3009 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3010 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3011 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3012 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3013 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3014 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3015 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3016 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3017 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3018 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3019 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3020 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3021 }
3022
555382cb 3023 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3024
cd28ab6a 3025 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3026 sky2_gmac_reset(hw, i);
cd28ab6a 3027
cd28ab6a
SH		 3028 memset(hw->st_le, 0, STATUS_LE_BYTES);
3029 hw->st_idx = 0;
3030
3031 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3032 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3033
3034 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3035 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3036
3037 /* Set the list last index */
793b883e 3038 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3039
290d4de5
SH		 3040 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3041 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3042
290d4de5
SH		 3043 /* set Status-FIFO ISR watermark */
3044 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3045 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3046 else
3047 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3048
290d4de5 3049 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3050 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3051 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3052
793b883e 3053 /* enable status unit */
cd28ab6a
SH		 3054 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3055
3056 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3057 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3058 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3059}
3060
81906791
SH		 3061static void sky2_restart(struct work_struct *work)
3062{
3063 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3064 struct net_device *dev;
3065 int i, err;
3066
81906791 3067 rtnl_lock();
81906791
SH		 3068 for (i = 0; i < hw->ports; i++) {
3069 dev = hw->dev[i];
3070 if (netif_running(dev))
3071 sky2_down(dev);
3072 }
3073
8cfcbe99
SH		 3074 napi_disable(&hw->napi);
3075 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 3076 sky2_reset(hw);
3077 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 3078 napi_enable(&hw->napi);
81906791
SH		 3079
3080 for (i = 0; i < hw->ports; i++) {
3081 dev = hw->dev[i];
3082 if (netif_running(dev)) {
3083 err = sky2_up(dev);
3084 if (err) {
3085 printk(KERN_INFO PFX "%s: could not restart %d\n",
3086 dev->name, err);
3087 dev_close(dev);
3088 }
3089 }
3090 }
3091
81906791
SH		 3092 rtnl_unlock();
3093}
3094
e3173832
SH		 3095static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3096{
3097 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3098}
3099
3100static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3101{
3102 const struct sky2_port *sky2 = netdev_priv(dev);
3103
3104 wol->supported = sky2_wol_supported(sky2->hw);
3105 wol->wolopts = sky2->wol;
3106}
3107
3108static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3109{
3110 struct sky2_port *sky2 = netdev_priv(dev);
3111 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3112
e3173832
SH		 3113 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
3114 return -EOPNOTSUPP;
3115
3116 sky2->wol = wol->wolopts;
3117
05745c4a
SH		 3118 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3119 hw->chip_id == CHIP_ID_YUKON_EX ||
3120 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 3121 sky2_write32(hw, B0_CTST, sky2->wol
3122 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3123
3124 if (!netif_running(dev))
3125 sky2_wol_init(sky2);
cd28ab6a
SH		 3126 return 0;
3127}
3128
28bd181a 3129static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3130{
b89165f2
SH		 3131 if (sky2_is_copper(hw)) {
3132 u32 modes = SUPPORTED_10baseT_Half
3133 | SUPPORTED_10baseT_Full
3134 | SUPPORTED_100baseT_Half
3135 | SUPPORTED_100baseT_Full
3136 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3137
ea76e635 3138 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3139 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3140 | SUPPORTED_1000baseT_Full;
3141 return modes;
cd28ab6a 3142 } else
b89165f2
SH		 3143 return SUPPORTED_1000baseT_Half
3144 | SUPPORTED_1000baseT_Full
3145 | SUPPORTED_Autoneg
3146 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3147}
3148
793b883e 3149static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3150{
3151 struct sky2_port *sky2 = netdev_priv(dev);
3152 struct sky2_hw *hw = sky2->hw;
3153
3154 ecmd->transceiver = XCVR_INTERNAL;
3155 ecmd->supported = sky2_supported_modes(hw);
3156 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3157 if (sky2_is_copper(hw)) {
cd28ab6a 3158 ecmd->port = PORT_TP;
b89165f2
SH		 3159 ecmd->speed = sky2->speed;
3160 } else {
3161 ecmd->speed = SPEED_1000;
cd28ab6a 3162 ecmd->port = PORT_FIBRE;
b89165f2 3163 }
cd28ab6a
SH		 3164
3165 ecmd->advertising = sky2->advertising;
3166 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3167 ecmd->duplex = sky2->duplex;
3168 return 0;
3169}
3170
3171static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3172{
3173 struct sky2_port *sky2 = netdev_priv(dev);
3174 const struct sky2_hw *hw = sky2->hw;
3175 u32 supported = sky2_supported_modes(hw);
3176
3177 if (ecmd->autoneg == AUTONEG_ENABLE) {
3178 ecmd->advertising = supported;
3179 sky2->duplex = -1;
3180 sky2->speed = -1;
3181 } else {
3182 u32 setting;
3183
793b883e 3184 switch (ecmd->speed) {
cd28ab6a
SH		 3185 case SPEED_1000:
3186 if (ecmd->duplex == DUPLEX_FULL)
3187 setting = SUPPORTED_1000baseT_Full;
3188 else if (ecmd->duplex == DUPLEX_HALF)
3189 setting = SUPPORTED_1000baseT_Half;
3190 else
3191 return -EINVAL;
3192 break;
3193 case SPEED_100:
3194 if (ecmd->duplex == DUPLEX_FULL)
3195 setting = SUPPORTED_100baseT_Full;
3196 else if (ecmd->duplex == DUPLEX_HALF)
3197 setting = SUPPORTED_100baseT_Half;
3198 else
3199 return -EINVAL;
3200 break;
3201
3202 case SPEED_10:
3203 if (ecmd->duplex == DUPLEX_FULL)
3204 setting = SUPPORTED_10baseT_Full;
3205 else if (ecmd->duplex == DUPLEX_HALF)
3206 setting = SUPPORTED_10baseT_Half;
3207 else
3208 return -EINVAL;
3209 break;
3210 default:
3211 return -EINVAL;
3212 }
3213
3214 if ((setting & supported) == 0)
3215 return -EINVAL;
3216
3217 sky2->speed = ecmd->speed;
3218 sky2->duplex = ecmd->duplex;
3219 }
3220
3221 sky2->autoneg = ecmd->autoneg;
3222 sky2->advertising = ecmd->advertising;
3223
d1b139c0 3224 if (netif_running(dev)) {
1b537565 3225 sky2_phy_reinit(sky2);
d1b139c0
SH		 3226 sky2_set_multicast(dev);
3227 }
cd28ab6a
SH		 3228
3229 return 0;
3230}
3231
3232static void sky2_get_drvinfo(struct net_device *dev,
3233 struct ethtool_drvinfo *info)
3234{
3235 struct sky2_port *sky2 = netdev_priv(dev);
3236
3237 strcpy(info->driver, DRV_NAME);
3238 strcpy(info->version, DRV_VERSION);
3239 strcpy(info->fw_version, "N/A");
3240 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3241}
3242
3243static const struct sky2_stat {
793b883e
SH		 3244 char name[ETH_GSTRING_LEN];
3245 u16 offset;
cd28ab6a
SH		 3246} sky2_stats[] = {
3247 { "tx_bytes", GM_TXO_OK_HI },
3248 { "rx_bytes", GM_RXO_OK_HI },
3249 { "tx_broadcast", GM_TXF_BC_OK },
3250 { "rx_broadcast", GM_RXF_BC_OK },
3251 { "tx_multicast", GM_TXF_MC_OK },
3252 { "rx_multicast", GM_RXF_MC_OK },
3253 { "tx_unicast", GM_TXF_UC_OK },
3254 { "rx_unicast", GM_RXF_UC_OK },
3255 { "tx_mac_pause", GM_TXF_MPAUSE },
3256 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3257 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3258 { "late_collision",GM_TXF_LAT_COL },
3259 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3260 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3261 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3262
d2604540 3263 { "rx_short", GM_RXF_SHT },
cd28ab6a 3264 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3265 { "rx_64_byte_packets", GM_RXF_64B },
3266 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3267 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3268 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3269 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3270 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3271 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3272 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3273 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3274 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3275 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3276
3277 { "tx_64_byte_packets", GM_TXF_64B },
3278 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3279 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3280 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3281 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3282 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3283 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3284 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3285};
3286
cd28ab6a
SH		 3287static u32 sky2_get_rx_csum(struct net_device *dev)
3288{
3289 struct sky2_port *sky2 = netdev_priv(dev);
3290
3291 return sky2->rx_csum;
3292}
3293
3294static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3295{
3296 struct sky2_port *sky2 = netdev_priv(dev);
3297
3298 sky2->rx_csum = data;
793b883e 3299
cd28ab6a
SH		 3300 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3301 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3302
3303 return 0;
3304}
3305
3306static u32 sky2_get_msglevel(struct net_device *netdev)
3307{
3308 struct sky2_port *sky2 = netdev_priv(netdev);
3309 return sky2->msg_enable;
3310}
3311
9a7ae0a9
SH		 3312static int sky2_nway_reset(struct net_device *dev)
3313{
3314 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3315
16ad91e1 3316 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3317 return -EINVAL;
3318
1b537565 3319 sky2_phy_reinit(sky2);
d1b139c0 3320 sky2_set_multicast(dev);
9a7ae0a9
SH		 3321
3322 return 0;
3323}
3324
793b883e 3325static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3326{
3327 struct sky2_hw *hw = sky2->hw;
3328 unsigned port = sky2->port;
3329 int i;
3330
3331 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3332 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3333 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3334 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3335
793b883e 3336 for (i = 2; i < count; i++)
cd28ab6a
SH		 3337 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3338}
3339
cd28ab6a
SH		 3340static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3341{
3342 struct sky2_port *sky2 = netdev_priv(netdev);
3343 sky2->msg_enable = value;
3344}
3345
b9f2c044 3346static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3347{
b9f2c044
JG		 3348 switch (sset) {
3349 case ETH_SS_STATS:
3350 return ARRAY_SIZE(sky2_stats);
3351 default:
3352 return -EOPNOTSUPP;
3353 }
cd28ab6a
SH		 3354}
3355
3356static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3357 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3358{
3359 struct sky2_port *sky2 = netdev_priv(dev);
3360
793b883e 3361 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3362}
3363
793b883e 3364static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3365{
3366 int i;
3367
3368 switch (stringset) {
3369 case ETH_SS_STATS:
3370 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3371 memcpy(data + i * ETH_GSTRING_LEN,
3372 sky2_stats[i].name, ETH_GSTRING_LEN);
3373 break;
3374 }
3375}
3376
cd28ab6a
SH		 3377static int sky2_set_mac_address(struct net_device *dev, void *p)
3378{
3379 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3380 struct sky2_hw *hw = sky2->hw;
3381 unsigned port = sky2->port;
3382 const struct sockaddr *addr = p;
cd28ab6a
SH		 3383
3384 if (!is_valid_ether_addr(addr->sa_data))
3385 return -EADDRNOTAVAIL;
3386
cd28ab6a 3387 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3388 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3389 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3390 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3391 dev->dev_addr, ETH_ALEN);
1b537565 3392
a8ab1ec0
SH		 3393 /* virtual address for data */
3394 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3395
3396 /* physical address: used for pause frames */
3397 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3398
3399 return 0;
cd28ab6a
SH		 3400}
3401
a052b52f
SH		 3402static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3403{
3404 u32 bit;
3405
3406 bit = ether_crc(ETH_ALEN, addr) & 63;
3407 filter[bit >> 3] |= 1 << (bit & 7);
3408}
3409
cd28ab6a
SH		 3410static void sky2_set_multicast(struct net_device *dev)
3411{
3412 struct sky2_port *sky2 = netdev_priv(dev);
3413 struct sky2_hw *hw = sky2->hw;
3414 unsigned port = sky2->port;
3415 struct dev_mc_list *list = dev->mc_list;
3416 u16 reg;
3417 u8 filter[8];
a052b52f
SH		 3418 int rx_pause;
3419 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3420
a052b52f 3421 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3422 memset(filter, 0, sizeof(filter));
3423
3424 reg = gma_read16(hw, port, GM_RX_CTRL);
3425 reg |= GM_RXCR_UCF_ENA;
3426
d571b694 3427 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3428 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3429 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3430 memset(filter, 0xff, sizeof(filter));
a052b52f 3431 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3432 reg &= ~GM_RXCR_MCF_ENA;
3433 else {
3434 int i;
3435 reg |= GM_RXCR_MCF_ENA;
3436
a052b52f
SH		 3437 if (rx_pause)
3438 sky2_add_filter(filter, pause_mc_addr);
3439
3440 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3441 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3442 }
3443
cd28ab6a 3444 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3445 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3446 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3447 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3448 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3449 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3450 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3451 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3452
3453 gma_write16(hw, port, GM_RX_CTRL, reg);
3454}
3455
3456/* Can have one global because blinking is controlled by
3457 * ethtool and that is always under RTNL mutex
3458 */
a84d0a3d 3459static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3460{
a84d0a3d
SH		 3461 struct sky2_hw *hw = sky2->hw;
3462 unsigned port = sky2->port;
793b883e 3463
a84d0a3d
SH		 3464 spin_lock_bh(&sky2->phy_lock);
3465 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3466 hw->chip_id == CHIP_ID_YUKON_EX ||
3467 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3468 u16 pg;
793b883e
SH		 3469 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3470 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3471
a84d0a3d
SH		 3472 switch (mode) {
3473 case MO_LED_OFF:
3474 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3475 PHY_M_LEDC_LOS_CTRL(8) |
3476 PHY_M_LEDC_INIT_CTRL(8) |
3477 PHY_M_LEDC_STA1_CTRL(8) |
3478 PHY_M_LEDC_STA0_CTRL(8));
3479 break;
3480 case MO_LED_ON:
3481 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3482 PHY_M_LEDC_LOS_CTRL(9) |
3483 PHY_M_LEDC_INIT_CTRL(9) |
3484 PHY_M_LEDC_STA1_CTRL(9) |
3485 PHY_M_LEDC_STA0_CTRL(9));
3486 break;
3487 case MO_LED_BLINK:
3488 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3489 PHY_M_LEDC_LOS_CTRL(0xa) |
3490 PHY_M_LEDC_INIT_CTRL(0xa) |
3491 PHY_M_LEDC_STA1_CTRL(0xa) |
3492 PHY_M_LEDC_STA0_CTRL(0xa));
3493 break;
3494 case MO_LED_NORM:
3495 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3496 PHY_M_LEDC_LOS_CTRL(1) |
3497 PHY_M_LEDC_INIT_CTRL(8) |
3498 PHY_M_LEDC_STA1_CTRL(7) |
3499 PHY_M_LEDC_STA0_CTRL(7));
3500 }
793b883e 3501
a84d0a3d
SH		 3502 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3503 } else
7d2e3cb7 3504 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3505 PHY_M_LED_MO_DUP(mode) |
3506 PHY_M_LED_MO_10(mode) |
3507 PHY_M_LED_MO_100(mode) |
3508 PHY_M_LED_MO_1000(mode) |
3509 PHY_M_LED_MO_RX(mode) |
3510 PHY_M_LED_MO_TX(mode));
3511
3512 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3513}
3514
3515/* blink LED's for finding board */
3516static int sky2_phys_id(struct net_device *dev, u32 data)
3517{
3518 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3519 unsigned int i;
cd28ab6a 3520
a84d0a3d
SH		 3521 if (data == 0)
3522 data = UINT_MAX;
cd28ab6a 3523
a84d0a3d
SH		 3524 for (i = 0; i < data; i++) {
3525 sky2_led(sky2, MO_LED_ON);
3526 if (msleep_interruptible(500))
3527 break;
3528 sky2_led(sky2, MO_LED_OFF);
3529 if (msleep_interruptible(500))
3530 break;
793b883e 3531 }
a84d0a3d 3532 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3533
3534 return 0;
3535}
3536
3537static void sky2_get_pauseparam(struct net_device *dev,
3538 struct ethtool_pauseparam *ecmd)
3539{
3540 struct sky2_port *sky2 = netdev_priv(dev);
3541
16ad91e1
SH		 3542 switch (sky2->flow_mode) {
3543 case FC_NONE:
3544 ecmd->tx_pause = ecmd->rx_pause = 0;
3545 break;
3546 case FC_TX:
3547 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3548 break;
3549 case FC_RX:
3550 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3551 break;
3552 case FC_BOTH:
3553 ecmd->tx_pause = ecmd->rx_pause = 1;
3554 }
3555
cd28ab6a
SH		 3556 ecmd->autoneg = sky2->autoneg;
3557}
3558
3559static int sky2_set_pauseparam(struct net_device *dev,
3560 struct ethtool_pauseparam *ecmd)
3561{
3562 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3563
3564 sky2->autoneg = ecmd->autoneg;
16ad91e1 3565 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3566
16ad91e1
SH		 3567 if (netif_running(dev))
3568 sky2_phy_reinit(sky2);
cd28ab6a 3569
2eaba1a2 3570 return 0;
cd28ab6a
SH		 3571}
3572
fb17358f
SH		 3573static int sky2_get_coalesce(struct net_device *dev,
3574 struct ethtool_coalesce *ecmd)
3575{
3576 struct sky2_port *sky2 = netdev_priv(dev);
3577 struct sky2_hw *hw = sky2->hw;
3578
3579 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3580 ecmd->tx_coalesce_usecs = 0;
3581 else {
3582 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3583 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3584 }
3585 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3586
3587 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3588 ecmd->rx_coalesce_usecs = 0;
3589 else {
3590 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3591 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3592 }
3593 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3594
3595 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3596 ecmd->rx_coalesce_usecs_irq = 0;
3597 else {
3598 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3599 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3600 }
3601
3602 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3603
3604 return 0;
3605}
3606
3607/* Note: this affect both ports */
3608static int sky2_set_coalesce(struct net_device *dev,
3609 struct ethtool_coalesce *ecmd)
3610{
3611 struct sky2_port *sky2 = netdev_priv(dev);
3612 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3613 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3614
77b3d6a2
SH		 3615 if (ecmd->tx_coalesce_usecs > tmax ||
3616 ecmd->rx_coalesce_usecs > tmax ||
3617 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3618 return -EINVAL;
3619
ff81fbbe 3620 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3621 return -EINVAL;
ff81fbbe 3622 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3623 return -EINVAL;
ff81fbbe 3624 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3625 return -EINVAL;
3626
3627 if (ecmd->tx_coalesce_usecs == 0)
3628 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3629 else {
3630 sky2_write32(hw, STAT_TX_TIMER_INI,
3631 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3632 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3633 }
3634 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3635
3636 if (ecmd->rx_coalesce_usecs == 0)
3637 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3638 else {
3639 sky2_write32(hw, STAT_LEV_TIMER_INI,
3640 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3641 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3642 }
3643 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3644
3645 if (ecmd->rx_coalesce_usecs_irq == 0)
3646 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3647 else {
d28d4870 3648 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3649 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3650 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3651 }
3652 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3653 return 0;
3654}
3655
793b883e
SH		 3656static void sky2_get_ringparam(struct net_device *dev,
3657 struct ethtool_ringparam *ering)
3658{
3659 struct sky2_port *sky2 = netdev_priv(dev);
3660
3661 ering->rx_max_pending = RX_MAX_PENDING;
3662 ering->rx_mini_max_pending = 0;
3663 ering->rx_jumbo_max_pending = 0;
3664 ering->tx_max_pending = TX_RING_SIZE - 1;
3665
3666 ering->rx_pending = sky2->rx_pending;
3667 ering->rx_mini_pending = 0;
3668 ering->rx_jumbo_pending = 0;
3669 ering->tx_pending = sky2->tx_pending;
3670}
3671
3672static int sky2_set_ringparam(struct net_device *dev,
3673 struct ethtool_ringparam *ering)
3674{
3675 struct sky2_port *sky2 = netdev_priv(dev);
3676 int err = 0;
3677
3678 if (ering->rx_pending > RX_MAX_PENDING ||
3679 ering->rx_pending < 8 ||
3680 ering->tx_pending < MAX_SKB_TX_LE ||
3681 ering->tx_pending > TX_RING_SIZE - 1)
3682 return -EINVAL;
3683
3684 if (netif_running(dev))
3685 sky2_down(dev);
3686
3687 sky2->rx_pending = ering->rx_pending;
3688 sky2->tx_pending = ering->tx_pending;
3689
1b537565 3690 if (netif_running(dev)) {
793b883e 3691 err = sky2_up(dev);
1b537565
SH		 3692 if (err)
3693 dev_close(dev);
3694 }
793b883e
SH		 3695
3696 return err;
3697}
3698
793b883e
SH		 3699static int sky2_get_regs_len(struct net_device *dev)
3700{
6e4cbb34 3701 return 0x4000;
793b883e
SH		 3702}
3703
3704/*
3705 * Returns copy of control register region
3ead5db7 3706 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3707 */
3708static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3709 void *p)
3710{
3711 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3712 const void __iomem *io = sky2->hw->regs;
295b54c4 3713 unsigned int b;
793b883e
SH		 3714
3715 regs->version = 1;
793b883e 3716
295b54c4
SH		 3717 for (b = 0; b < 128; b++) {
3718 /* This complicated switch statement is to make sure and
3719 * only access regions that are unreserved.
3720 * Some blocks are only valid on dual port cards.
3721 * and block 3 has some special diagnostic registers that
3722 * are poison.
3723 */
3724 switch (b) {
3725 case 3:
3726 /* skip diagnostic ram region */
3727 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3728 break;
3ead5db7 3729
295b54c4
SH		 3730 /* dual port cards only */
3731 case 5: /* Tx Arbiter 2 */
3732 case 9: /* RX2 */
3733 case 14 ... 15: /* TX2 */
3734 case 17: case 19: /* Ram Buffer 2 */
3735 case 22 ... 23: /* Tx Ram Buffer 2 */
3736 case 25: /* Rx MAC Fifo 1 */
3737 case 27: /* Tx MAC Fifo 2 */
3738 case 31: /* GPHY 2 */
3739 case 40 ... 47: /* Pattern Ram 2 */
3740 case 52: case 54: /* TCP Segmentation 2 */
3741 case 112 ... 116: /* GMAC 2 */
3742 if (sky2->hw->ports == 1)
3743 goto reserved;
3744 /* fall through */
3745 case 0: /* Control */
3746 case 2: /* Mac address */
3747 case 4: /* Tx Arbiter 1 */
3748 case 7: /* PCI express reg */
3749 case 8: /* RX1 */
3750 case 12 ... 13: /* TX1 */
3751 case 16: case 18:/* Rx Ram Buffer 1 */
3752 case 20 ... 21: /* Tx Ram Buffer 1 */
3753 case 24: /* Rx MAC Fifo 1 */
3754 case 26: /* Tx MAC Fifo 1 */
3755 case 28 ... 29: /* Descriptor and status unit */
3756 case 30: /* GPHY 1*/
3757 case 32 ... 39: /* Pattern Ram 1 */
3758 case 48: case 50: /* TCP Segmentation 1 */
3759 case 56 ... 60: /* PCI space */
3760 case 80 ... 84: /* GMAC 1 */
3761 memcpy_fromio(p, io, 128);
3762 break;
3763 default:
3764reserved:
3765 memset(p, 0, 128);
3766 }
3ead5db7 3767
295b54c4
SH		 3768 p += 128;
3769 io += 128;
3770 }
793b883e 3771}
cd28ab6a 3772
b628ed98
SH		 3773/* In order to do Jumbo packets on these chips, need to turn off the
3774 * transmit store/forward. Therefore checksum offload won't work.
3775 */
3776static int no_tx_offload(struct net_device *dev)
3777{
3778 const struct sky2_port *sky2 = netdev_priv(dev);
3779 const struct sky2_hw *hw = sky2->hw;
3780
69161611 3781 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3782}
3783
3784static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3785{
3786 if (data && no_tx_offload(dev))
3787 return -EINVAL;
3788
3789 return ethtool_op_set_tx_csum(dev, data);
3790}
3791
3792
3793static int sky2_set_tso(struct net_device *dev, u32 data)
3794{
3795 if (data && no_tx_offload(dev))
3796 return -EINVAL;
3797
3798 return ethtool_op_set_tso(dev, data);
3799}
3800
f4331a6d
SH		 3801static int sky2_get_eeprom_len(struct net_device *dev)
3802{
3803 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3804 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3805 u16 reg2;
3806
b32f40c4 3807 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3808 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3809}
3810
b32f40c4 3811static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
f4331a6d 3812{
167f53d0 3813 u32 val;
f4331a6d 3814
b32f40c4 3815 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
167f53d0
SH		 3816
3817 do {
b32f40c4 3818 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0
SH		 3819 } while (!(offset & PCI_VPD_ADDR_F));
3820
b32f40c4 3821 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
167f53d0 3822 return val;
f4331a6d
SH		 3823}
3824
b32f40c4 3825static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
f4331a6d 3826{
b32f40c4
SH		 3827 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3828 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
f4331a6d 3829 do {
b32f40c4 3830 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0 3831 } while (offset & PCI_VPD_ADDR_F);
f4331a6d
SH		 3832}
3833
3834static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3835 u8 *data)
3836{
3837 struct sky2_port *sky2 = netdev_priv(dev);
3838 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3839 int length = eeprom->len;
3840 u16 offset = eeprom->offset;
3841
3842 if (!cap)
3843 return -EINVAL;
3844
3845 eeprom->magic = SKY2_EEPROM_MAGIC;
3846
3847 while (length > 0) {
b32f40c4 3848 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3849 int n = min_t(int, length, sizeof(val));
3850
3851 memcpy(data, &val, n);
3852 length -= n;
3853 data += n;
3854 offset += n;
3855 }
3856 return 0;
3857}
3858
3859static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3860 u8 *data)
3861{
3862 struct sky2_port *sky2 = netdev_priv(dev);
3863 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3864 int length = eeprom->len;
3865 u16 offset = eeprom->offset;
3866
3867 if (!cap)
3868 return -EINVAL;
3869
3870 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3871 return -EINVAL;
3872
3873 while (length > 0) {
3874 u32 val;
3875 int n = min_t(int, length, sizeof(val));
3876
3877 if (n < sizeof(val))
b32f40c4 3878 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3879 memcpy(&val, data, n);
3880
b32f40c4 3881 sky2_vpd_write(sky2->hw, cap, offset, val);
f4331a6d
SH		 3882
3883 length -= n;
3884 data += n;
3885 offset += n;
3886 }
3887 return 0;
3888}
3889
3890
7282d491 3891static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3892 .get_settings = sky2_get_settings,
3893 .set_settings = sky2_set_settings,
3894 .get_drvinfo = sky2_get_drvinfo,
3895 .get_wol = sky2_get_wol,
3896 .set_wol = sky2_set_wol,
3897 .get_msglevel = sky2_get_msglevel,
3898 .set_msglevel = sky2_set_msglevel,
3899 .nway_reset = sky2_nway_reset,
3900 .get_regs_len = sky2_get_regs_len,
3901 .get_regs = sky2_get_regs,
3902 .get_link = ethtool_op_get_link,
3903 .get_eeprom_len = sky2_get_eeprom_len,
3904 .get_eeprom = sky2_get_eeprom,
3905 .set_eeprom = sky2_set_eeprom,
f4331a6d 3906 .set_sg = ethtool_op_set_sg,
f4331a6d 3907 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3908 .set_tso = sky2_set_tso,
3909 .get_rx_csum = sky2_get_rx_csum,
3910 .set_rx_csum = sky2_set_rx_csum,
3911 .get_strings = sky2_get_strings,
3912 .get_coalesce = sky2_get_coalesce,
3913 .set_coalesce = sky2_set_coalesce,
3914 .get_ringparam = sky2_get_ringparam,
3915 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3916 .get_pauseparam = sky2_get_pauseparam,
3917 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3918 .phys_id = sky2_phys_id,
b9f2c044 3919 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3920 .get_ethtool_stats = sky2_get_ethtool_stats,
3921};
3922
3cf26753
SH		 3923#ifdef CONFIG_SKY2_DEBUG
3924
3925static struct dentry *sky2_debug;
3926
3927static int sky2_debug_show(struct seq_file *seq, void *v)
3928{
3929 struct net_device *dev = seq->private;
3930 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 3931 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 3932 unsigned port = sky2->port;
3933 unsigned idx, last;
3934 int sop;
3935
3936 if (!netif_running(dev))
3937 return -ENETDOWN;
3938
3939 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3940 sky2_read32(hw, B0_ISRC),
3941 sky2_read32(hw, B0_IMSK),
3942 sky2_read32(hw, B0_Y2_SP_ICR));
3943
bea3348e 3944 napi_disable(&hw->napi);
3cf26753
SH		 3945 last = sky2_read16(hw, STAT_PUT_IDX);
3946
3947 if (hw->st_idx == last)
3948 seq_puts(seq, "Status ring (empty)\n");
3949 else {
3950 seq_puts(seq, "Status ring\n");
3951 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3952 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3953 const struct sky2_status_le *le = hw->st_le + idx;
3954 seq_printf(seq, "[%d] %#x %d %#x\n",
3955 idx, le->opcode, le->length, le->status);
3956 }
3957 seq_puts(seq, "\n");
3958 }
3959
3960 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3961 sky2->tx_cons, sky2->tx_prod,
3962 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3963 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3964
3965 /* Dump contents of tx ring */
3966 sop = 1;
3967 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3968 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3969 const struct sky2_tx_le *le = sky2->tx_le + idx;
3970 u32 a = le32_to_cpu(le->addr);
3971
3972 if (sop)
3973 seq_printf(seq, "%u:", idx);
3974 sop = 0;
3975
3976 switch(le->opcode & ~HW_OWNER) {
3977 case OP_ADDR64:
3978 seq_printf(seq, " %#x:", a);
3979 break;
3980 case OP_LRGLEN:
3981 seq_printf(seq, " mtu=%d", a);
3982 break;
3983 case OP_VLAN:
3984 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3985 break;
3986 case OP_TCPLISW:
3987 seq_printf(seq, " csum=%#x", a);
3988 break;
3989 case OP_LARGESEND:
3990 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3991 break;
3992 case OP_PACKET:
3993 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3994 break;
3995 case OP_BUFFER:
3996 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3997 break;
3998 default:
3999 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4000 a, le16_to_cpu(le->length));
4001 }
4002
4003 if (le->ctrl & EOP) {
4004 seq_putc(seq, '\n');
4005 sop = 1;
4006 }
4007 }
4008
4009 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4010 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4011 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4012 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4013
d1d08d12 4014 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4015 napi_enable(&hw->napi);
3cf26753
SH		 4016 return 0;
4017}
4018
4019static int sky2_debug_open(struct inode *inode, struct file *file)
4020{
4021 return single_open(file, sky2_debug_show, inode->i_private);
4022}
4023
4024static const struct file_operations sky2_debug_fops = {
4025 .owner = THIS_MODULE,
4026 .open = sky2_debug_open,
4027 .read = seq_read,
4028 .llseek = seq_lseek,
4029 .release = single_release,
4030};
4031
4032/*
4033 * Use network device events to create/remove/rename
4034 * debugfs file entries
4035 */
4036static int sky2_device_event(struct notifier_block *unused,
4037 unsigned long event, void *ptr)
4038{
4039 struct net_device *dev = ptr;
5b296bc9 4040 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4041
5b296bc9
SH		 4042 if (dev->open != sky2_up || !sky2_debug)
4043 return NOTIFY_DONE;
3cf26753 4044
5b296bc9
SH		 4045 switch(event) {
4046 case NETDEV_CHANGENAME:
4047 if (sky2->debugfs) {
4048 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4049 sky2_debug, dev->name);
4050 }
4051 break;
3cf26753 4052
5b296bc9
SH		 4053 case NETDEV_GOING_DOWN:
4054 if (sky2->debugfs) {
4055 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4056 dev->name);
4057 debugfs_remove(sky2->debugfs);
4058 sky2->debugfs = NULL;
3cf26753 4059 }
5b296bc9
SH		 4060 break;
4061
4062 case NETDEV_UP:
4063 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4064 sky2_debug, dev,
4065 &sky2_debug_fops);
4066 if (IS_ERR(sky2->debugfs))
4067 sky2->debugfs = NULL;
3cf26753
SH		 4068 }
4069
4070 return NOTIFY_DONE;
4071}
4072
4073static struct notifier_block sky2_notifier = {
4074 .notifier_call = sky2_device_event,
4075};
4076
4077
4078static __init void sky2_debug_init(void)
4079{
4080 struct dentry *ent;
4081
4082 ent = debugfs_create_dir("sky2", NULL);
4083 if (!ent || IS_ERR(ent))
4084 return;
4085
4086 sky2_debug = ent;
4087 register_netdevice_notifier(&sky2_notifier);
4088}
4089
4090static __exit void sky2_debug_cleanup(void)
4091{
4092 if (sky2_debug) {
4093 unregister_netdevice_notifier(&sky2_notifier);
4094 debugfs_remove(sky2_debug);
4095 sky2_debug = NULL;
4096 }
4097}
4098
4099#else
4100#define sky2_debug_init()
4101#define sky2_debug_cleanup()
4102#endif
4103
4104
cd28ab6a
SH		 4105/* Initialize network device */
4106static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4107 unsigned port,
be63a21c 4108 int highmem, int wol)
cd28ab6a
SH		 4109{
4110 struct sky2_port *sky2;
4111 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4112
4113 if (!dev) {
898eb71c 4114 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4115 return NULL;
4116 }
4117
cd28ab6a 4118 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4119 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 4120 dev->open = sky2_up;
4121 dev->stop = sky2_down;
ef743d33 4122 dev->do_ioctl = sky2_ioctl;
cd28ab6a 4123 dev->hard_start_xmit = sky2_xmit_frame;
cd28ab6a
SH		 4124 dev->set_multicast_list = sky2_set_multicast;
4125 dev->set_mac_address = sky2_set_mac_address;
4126 dev->change_mtu = sky2_change_mtu;
4127 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4128 dev->tx_timeout = sky2_tx_timeout;
4129 dev->watchdog_timeo = TX_WATCHDOG;
cd28ab6a 4130#ifdef CONFIG_NET_POLL_CONTROLLER
a5e68c02
SH		 4131 if (port == 0)
4132 dev->poll_controller = sky2_netpoll;
cd28ab6a 4133#endif
cd28ab6a
SH		 4134
4135 sky2 = netdev_priv(dev);
4136 sky2->netdev = dev;
4137 sky2->hw = hw;
4138 sky2->msg_enable = netif_msg_init(debug, default_msg);
4139
cd28ab6a
SH		 4140 /* Auto speed and flow control */
4141 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 4142 sky2->flow_mode = FC_BOTH;
4143
cd28ab6a
SH		 4144 sky2->duplex = -1;
4145 sky2->speed = -1;
4146 sky2->advertising = sky2_supported_modes(hw);
8b31cfbc 4147 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
be63a21c 4148 sky2->wol = wol;
75d070c5 4149
e07b1aa8 4150 spin_lock_init(&sky2->phy_lock);
793b883e 4151 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 4152 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4153
4154 hw->dev[port] = dev;
4155
4156 sky2->port = port;
4157
4a50a876 4158 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4159 if (highmem)
4160 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4161
d1f13708 4162#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4163 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4164 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4165 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4166 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4167 dev->vlan_rx_register = sky2_vlan_rx_register;
4168 }
d1f13708 4169#endif
4170
cd28ab6a 4171 /* read the mac address */
793b883e 4172 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4173 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4174
cd28ab6a
SH		 4175 return dev;
4176}
4177
28bd181a 4178static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4179{
4180 const struct sky2_port *sky2 = netdev_priv(dev);
0795af57 4181 DECLARE_MAC_BUF(mac);
cd28ab6a
SH		 4182
4183 if (netif_msg_probe(sky2))
0795af57
JP		 4184 printk(KERN_INFO PFX "%s: addr %s\n",
4185 dev->name, print_mac(mac, dev->dev_addr));
cd28ab6a
SH		 4186}
4187
fb2690a9 4188/* Handle software interrupt used during MSI test */
7d12e780 4189static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4190{
4191 struct sky2_hw *hw = dev_id;
4192 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4193
4194 if (status == 0)
4195 return IRQ_NONE;
4196
4197 if (status & Y2_IS_IRQ_SW) {
ea76e635 4198 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4199 wake_up(&hw->msi_wait);
4200 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4201 }
4202 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4203
4204 return IRQ_HANDLED;
4205}
4206
4207/* Test interrupt path by forcing a a software IRQ */
4208static int __devinit sky2_test_msi(struct sky2_hw *hw)
4209{
4210 struct pci_dev *pdev = hw->pdev;
4211 int err;
4212
bb507fe1 4213 init_waitqueue_head (&hw->msi_wait);
4214
fb2690a9
SH		 4215 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4216
b0a20ded 4217 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4218 if (err) {
b02a9258 4219 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4220 return err;
4221 }
4222
fb2690a9 4223 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4224 sky2_read8(hw, B0_CTST);
fb2690a9 4225
ea76e635 4226 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4227
ea76e635 4228 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4229 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4230 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4231 "switching to INTx mode.\n");
fb2690a9
SH		 4232
4233 err = -EOPNOTSUPP;
4234 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4235 }
4236
4237 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4238 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4239
4240 free_irq(pdev->irq, hw);
4241
4242 return err;
4243}
4244
be63a21c
SH		 4245static int __devinit pci_wake_enabled(struct pci_dev *dev)
4246{
4247 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4248 u16 value;
4249
4250 if (!pm)
4251 return 0;
4252 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4253 return 0;
4254 return value & PCI_PM_CTRL_PME_ENABLE;
4255}
4256
c7127a34
SH		 4257/* This driver supports yukon2 chipset only */
4258static const char *sky2_name(u8 chipid, char *buf, int sz)
4259{
4260 const char *name[] = {
4261 "XL", /* 0xb3 */
4262 "EC Ultra", /* 0xb4 */
4263 "Extreme", /* 0xb5 */
4264 "EC", /* 0xb6 */
4265 "FE", /* 0xb7 */
4266 "FE+", /* 0xb8 */
4267 "Supreme", /* 0xb9 */
4268 };
4269
4270 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_SUPR)
4271 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4272 else
4273 snprintf(buf, sz, "(chip %#x)", chipid);
4274 return buf;
4275}
4276
cd28ab6a
SH		 4277static int __devinit sky2_probe(struct pci_dev *pdev,
4278 const struct pci_device_id *ent)
4279{
7f60c64b 4280 struct net_device *dev;
cd28ab6a 4281 struct sky2_hw *hw;
be63a21c 4282 int err, using_dac = 0, wol_default;
c7127a34 4283 char buf1[16];
cd28ab6a 4284
793b883e
SH		 4285 err = pci_enable_device(pdev);
4286 if (err) {
b02a9258 4287 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4288 goto err_out;
4289 }
4290
793b883e
SH		 4291 err = pci_request_regions(pdev, DRV_NAME);
4292 if (err) {
b02a9258 4293 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4294 goto err_out_disable;
cd28ab6a
SH		 4295 }
4296
4297 pci_set_master(pdev);
4298
d1f3d4dd
SH		 4299 if (sizeof(dma_addr_t) > sizeof(u32) &&
4300 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4301 using_dac = 1;
4302 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4303 if (err < 0) {
b02a9258
SH		 4304 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4305 "for consistent allocations\n");
d1f3d4dd
SH		 4306 goto err_out_free_regions;
4307 }
d1f3d4dd 4308 } else {
cd28ab6a
SH		 4309 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4310 if (err) {
b02a9258 4311 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4312 goto err_out_free_regions;
4313 }
4314 }
d1f3d4dd 4315
be63a21c
SH		 4316 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4317
cd28ab6a 4318 err = -ENOMEM;
6aad85d6 4319 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4320 if (!hw) {
b02a9258 4321 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4322 goto err_out_free_regions;
4323 }
4324
cd28ab6a 4325 hw->pdev = pdev;
cd28ab6a
SH		 4326
4327 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4328 if (!hw->regs) {
b02a9258 4329 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4330 goto err_out_free_hw;
4331 }
4332
56a645cc 4333#ifdef __BIG_ENDIAN
f65b138c
SH		 4334 /* The sk98lin vendor driver uses hardware byte swapping but
4335 * this driver uses software swapping.
4336 */
56a645cc
SH		 4337 {
4338 u32 reg;
b32f40c4 4339 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 4340 reg &= ~PCI_REV_DESC;
b32f40c4 4341 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
56a645cc
SH		 4342 }
4343#endif
4344
08c06d8a 4345 /* ring for status responses */
167f53d0 4346 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4347 if (!hw->st_le)
4348 goto err_out_iounmap;
4349
e3173832 4350 err = sky2_init(hw);
cd28ab6a 4351 if (err)
793b883e 4352 goto err_out_iounmap;
cd28ab6a 4353
c7127a34
SH		 4354 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-2 %s rev %d\n",
4355 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4356 pdev->irq, sky2_name(hw->chip_id, buf1, sizeof(buf1)),
4357 hw->chip_rev);
cd28ab6a 4358
e3173832
SH		 4359 sky2_reset(hw);
4360
be63a21c 4361 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4362 if (!dev) {
4363 err = -ENOMEM;
cd28ab6a 4364 goto err_out_free_pci;
7f60c64b 4365 }
cd28ab6a 4366
9fa1b1f3
SH		 4367 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4368 err = sky2_test_msi(hw);
4369 if (err == -EOPNOTSUPP)
4370 pci_disable_msi(pdev);
4371 else if (err)
4372 goto err_out_free_netdev;
4373 }
4374
793b883e
SH		 4375 err = register_netdev(dev);
4376 if (err) {
b02a9258 4377 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4378 goto err_out_free_netdev;
4379 }
4380
6de16237
SH		 4381 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4382
ea76e635
SH		 4383 err = request_irq(pdev->irq, sky2_intr,
4384 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4385 dev->name, hw);
9fa1b1f3 4386 if (err) {
b02a9258 4387 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4388 goto err_out_unregister;
4389 }
4390 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4391 napi_enable(&hw->napi);
9fa1b1f3 4392
cd28ab6a
SH		 4393 sky2_show_addr(dev);
4394
7f60c64b 4395 if (hw->ports > 1) {
4396 struct net_device *dev1;
4397
be63a21c 4398 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4399 if (!dev1)
4400 dev_warn(&pdev->dev, "allocation for second device failed\n");
4401 else if ((err = register_netdev(dev1))) {
4402 dev_warn(&pdev->dev,
4403 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4404 hw->dev[1] = NULL;
4405 free_netdev(dev1);
b02a9258
SH		 4406 } else
4407 sky2_show_addr(dev1);
cd28ab6a
SH		 4408 }
4409
32c2c300 4410 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4411 INIT_WORK(&hw->restart_work, sky2_restart);
4412
793b883e
SH		 4413 pci_set_drvdata(pdev, hw);
4414
cd28ab6a
SH		 4415 return 0;
4416
793b883e 4417err_out_unregister:
ea76e635 4418 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4419 pci_disable_msi(pdev);
793b883e 4420 unregister_netdev(dev);
cd28ab6a
SH		 4421err_out_free_netdev:
4422 free_netdev(dev);
cd28ab6a 4423err_out_free_pci:
793b883e 4424 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4425 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4426err_out_iounmap:
4427 iounmap(hw->regs);
4428err_out_free_hw:
4429 kfree(hw);
4430err_out_free_regions:
4431 pci_release_regions(pdev);
44a1d2e5 4432err_out_disable:
cd28ab6a 4433 pci_disable_device(pdev);
cd28ab6a 4434err_out:
549a68c3 4435 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4436 return err;
4437}
4438
4439static void __devexit sky2_remove(struct pci_dev *pdev)
4440{
793b883e 4441 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4442 int i;
cd28ab6a 4443
793b883e 4444 if (!hw)
cd28ab6a
SH		 4445 return;
4446
32c2c300 4447 del_timer_sync(&hw->watchdog_timer);
6de16237 4448 cancel_work_sync(&hw->restart_work);
d27ed387 4449
b877fe28 4450 for (i = hw->ports-1; i >= 0; --i)
6de16237 4451 unregister_netdev(hw->dev[i]);
81906791 4452
d27ed387 4453 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4454
ae306cca
SH		 4455 sky2_power_aux(hw);
4456
cd28ab6a 4457 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4458 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4459 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4460
4461 free_irq(pdev->irq, hw);
ea76e635 4462 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4463 pci_disable_msi(pdev);
793b883e 4464 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4465 pci_release_regions(pdev);
4466 pci_disable_device(pdev);
793b883e 4467
b877fe28 4468 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4469 free_netdev(hw->dev[i]);
4470
cd28ab6a
SH		 4471 iounmap(hw->regs);
4472 kfree(hw);
5afa0a9c 4473
cd28ab6a
SH		 4474 pci_set_drvdata(pdev, NULL);
4475}
4476
4477#ifdef CONFIG_PM
4478static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4479{
793b883e 4480 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4481 int i, wol = 0;
cd28ab6a 4482
549a68c3
SH		 4483 if (!hw)
4484 return 0;
4485
063a0b38
SH		 4486 del_timer_sync(&hw->watchdog_timer);
4487 cancel_work_sync(&hw->restart_work);
4488
f05267e7 4489 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4490 struct net_device *dev = hw->dev[i];
e3173832 4491 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4492
063a0b38 4493 netif_device_detach(dev);
e3173832 4494 if (netif_running(dev))
5afa0a9c 4495 sky2_down(dev);
e3173832
SH		 4496
4497 if (sky2->wol)
4498 sky2_wol_init(sky2);
4499
4500 wol |= sky2->wol;
cd28ab6a
SH		 4501 }
4502
8ab8fca2 4503 sky2_write32(hw, B0_IMSK, 0);
6de16237 4504 napi_disable(&hw->napi);
ae306cca 4505 sky2_power_aux(hw);
e3173832 4506
d374c1c1 4507 pci_save_state(pdev);
e3173832 4508 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
a068c0ad 4509 sky2_power_state(hw, pci_choose_state(pdev, state));
ae306cca 4510
2ccc99b7 4511 return 0;
cd28ab6a
SH		 4512}
4513
4514static int sky2_resume(struct pci_dev *pdev)
4515{
793b883e 4516 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4517 int i, err;
cd28ab6a 4518
549a68c3
SH		 4519 if (!hw)
4520 return 0;
4521
a068c0ad 4522 sky2_power_state(hw, PCI_D0);
ae306cca
SH		 4523
4524 err = pci_restore_state(pdev);
4525 if (err)
4526 goto out;
4527
cd28ab6a 4528 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4529
4530 /* Re-enable all clocks */
05745c4a
SH		 4531 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4532 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4533 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4534 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4535
e3173832 4536 sky2_reset(hw);
8ab8fca2 4537 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4538 napi_enable(&hw->napi);
8ab8fca2 4539
f05267e7 4540 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4541 struct net_device *dev = hw->dev[i];
063a0b38
SH		 4542
4543 netif_device_attach(dev);
6a5706b9 4544 if (netif_running(dev)) {
08c06d8a
SH		 4545 err = sky2_up(dev);
4546 if (err) {
4547 printk(KERN_ERR PFX "%s: could not up: %d\n",
4548 dev->name, err);
68c28898 4549 rtnl_lock();
08c06d8a 4550 dev_close(dev);
68c28898 4551 rtnl_unlock();
eb35cf60 4552 goto out;
5afa0a9c 4553 }
cd28ab6a
SH		 4554 }
4555 }
eb35cf60 4556
ae306cca 4557 return 0;
08c06d8a 4558out:
b02a9258 4559 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4560 pci_disable_device(pdev);
08c06d8a 4561 return err;
cd28ab6a
SH		 4562}
4563#endif
4564
e3173832
SH		 4565static void sky2_shutdown(struct pci_dev *pdev)
4566{
4567 struct sky2_hw *hw = pci_get_drvdata(pdev);
4568 int i, wol = 0;
4569
549a68c3
SH		 4570 if (!hw)
4571 return;
4572
5c0d6b34 4573 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4574
4575 for (i = 0; i < hw->ports; i++) {
4576 struct net_device *dev = hw->dev[i];
4577 struct sky2_port *sky2 = netdev_priv(dev);
4578
4579 if (sky2->wol) {
4580 wol = 1;
4581 sky2_wol_init(sky2);
4582 }
4583 }
4584
4585 if (wol)
4586 sky2_power_aux(hw);
4587
4588 pci_enable_wake(pdev, PCI_D3hot, wol);
4589 pci_enable_wake(pdev, PCI_D3cold, wol);
4590
4591 pci_disable_device(pdev);
a068c0ad 4592 sky2_power_state(hw, PCI_D3hot);
e3173832
SH		 4593}
4594
cd28ab6a 4595static struct pci_driver sky2_driver = {
793b883e
SH		 4596 .name = DRV_NAME,
4597 .id_table = sky2_id_table,
4598 .probe = sky2_probe,
4599 .remove = __devexit_p(sky2_remove),
cd28ab6a 4600#ifdef CONFIG_PM
793b883e
SH		 4601 .suspend = sky2_suspend,
4602 .resume = sky2_resume,
cd28ab6a 4603#endif
e3173832 4604 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4605};
4606
4607static int __init sky2_init_module(void)
4608{
3cf26753 4609 sky2_debug_init();
50241c4c 4610 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4611}
4612
4613static void __exit sky2_cleanup_module(void)
4614{
4615 pci_unregister_driver(&sky2_driver);
3cf26753 4616 sky2_debug_cleanup();
cd28ab6a
SH		 4617}
4618
4619module_init(sky2_init_module);
4620module_exit(sky2_cleanup_module);
4621
4622MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4623MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4624MODULE_LICENSE("GPL");
5f4f9dc1 4625MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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