projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sky2: fix receive pause thresholds
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a 26#include <linux/kernel.h>
cd28ab6a
SH		 27#include <linux/module.h>
28#include <linux/netdevice.h>
d0bbccfa 29#include <linux/dma-mapping.h>
cd28ab6a
SH		 30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/pci.h>
33#include <linux/ip.h>
c9bdd4b5 34#include <net/ip.h>
cd28ab6a
SH		 35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
3cf26753 41#include <linux/debugfs.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
0c3f450b 53#define DRV_VERSION "1.25"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
793b883e 66
ee5f68fe 67/* This is the worst case number of transmit list elements for a single skb:
07e31637
SH		 68 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
69#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
e9c1be80 70#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
ee5f68fe
SH		 71#define TX_MAX_PENDING 4096
72#define TX_DEF_PENDING 127
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
e6cac9ba 102static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
e30a4ac2 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
2d2a3871 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
cd28ab6a
SH		 143 { 0 }
144};
793b883e 145
cd28ab6a
SH		 146MODULE_DEVICE_TABLE(pci, sky2_id_table);
147
148/* Avoid conditionals by using array */
149static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
150static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 151static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 152
d1b139c0
SH		 153static void sky2_set_multicast(struct net_device *dev);
154
af043aa5 155/* Access to PHY via serial interconnect */
ef743d33 156static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 157{
158 int i;
159
160 gma_write16(hw, port, GM_SMI_DATA, val);
161 gma_write16(hw, port, GM_SMI_CTRL,
162 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
163
164 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 165 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
166 if (ctrl == 0xffff)
167 goto io_error;
168
169 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 170 return 0;
af043aa5
SH		 171
172 udelay(10);
cd28ab6a 173 }
ef743d33 174
af043aa5 175 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 176 return -ETIMEDOUT;
af043aa5
SH		 177
178io_error:
179 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
180 return -EIO;
cd28ab6a
SH		 181}
182
ef743d33 183static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 184{
185 int i;
186
793b883e 187 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 188 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
189
190 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 191 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
192 if (ctrl == 0xffff)
193 goto io_error;
194
195 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33 196 *val = gma_read16(hw, port, GM_SMI_DATA);
197 return 0;
198 }
199
af043aa5 200 udelay(10);
cd28ab6a
SH		 201 }
202
af043aa5 203 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 204 return -ETIMEDOUT;
af043aa5
SH		 205io_error:
206 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
207 return -EIO;
ef743d33 208}
209
af043aa5 210static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33 211{
212 u16 v;
af043aa5 213 __gm_phy_read(hw, port, reg, &v);
ef743d33 214 return v;
cd28ab6a
SH		 215}
216
5afa0a9c 217
ae306cca
SH		 218static void sky2_power_on(struct sky2_hw *hw)
219{
220 /* switch power to VCC (WA for VAUX problem) */
221 sky2_write8(hw, B0_POWER_CTRL,
222 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 223
ae306cca
SH		 224 /* disable Core Clock Division, */
225 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 226
ae306cca
SH		 227 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
228 /* enable bits are inverted */
229 sky2_write8(hw, B2_Y2_CLK_GATE,
230 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
231 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
232 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
233 else
234 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 235
ea76e635 236 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 237 u32 reg;
5afa0a9c 238
b32f40c4 239 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 240
b32f40c4 241 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 242 /* set all bits to 0 except bits 15..12 and 8 */
243 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 244 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 245
b32f40c4 246 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 247 /* set all bits to 0 except bits 28 & 27 */
248 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 249 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 250
b32f40c4 251 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 252
253 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
254 reg = sky2_read32(hw, B2_GP_IO);
255 reg |= GLB_GPIO_STAT_RACE_DIS;
256 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 257
258 sky2_read32(hw, B2_GP_IO);
5afa0a9c 259 }
10547ae2
SH		 260
261 /* Turn on "driver loaded" LED */
262 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
ae306cca 263}
5afa0a9c 264
ae306cca
SH		 265static void sky2_power_aux(struct sky2_hw *hw)
266{
267 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
268 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
269 else
270 /* enable bits are inverted */
271 sky2_write8(hw, B2_Y2_CLK_GATE,
272 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
273 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
274 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
275
c23ddf8f
SH		 276 /* switch power to VAUX if supported and PME from D3cold */
277 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
278 pci_pme_capable(hw->pdev, PCI_D3cold))
ae306cca
SH		 279 sky2_write8(hw, B0_POWER_CTRL,
280 (PC_VAUX_ENA | PC_VCC_ENA |
281 PC_VAUX_ON | PC_VCC_OFF));
10547ae2
SH		 282
283 /* turn off "driver loaded LED" */
284 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
5afa0a9c 285}
286
d3bcfbeb 287static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 288{
289 u16 reg;
290
291 /* disable all GMAC IRQ's */
292 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 293
cd28ab6a
SH		 294 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
295 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
298
299 reg = gma_read16(hw, port, GM_RX_CTRL);
300 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
301 gma_write16(hw, port, GM_RX_CTRL, reg);
302}
303
16ad91e1
SH		 304/* flow control to advertise bits */
305static const u16 copper_fc_adv[] = {
306 [FC_NONE] = 0,
307 [FC_TX] = PHY_M_AN_ASP,
308 [FC_RX] = PHY_M_AN_PC,
309 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
310};
311
312/* flow control to advertise bits when using 1000BaseX */
313static const u16 fiber_fc_adv[] = {
df3fe1f3 314 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 315 [FC_TX] = PHY_M_P_ASYM_MD_X,
316 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 317 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 318};
319
320/* flow control to GMA disable bits */
321static const u16 gm_fc_disable[] = {
322 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
323 [FC_TX] = GM_GPCR_FC_RX_DIS,
324 [FC_RX] = GM_GPCR_FC_TX_DIS,
325 [FC_BOTH] = 0,
326};
327
328
cd28ab6a
SH		 329static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
330{
331 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 332 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 333
0ea065e5 334 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 335 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 336 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
337
338 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 339 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 340 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
341
53419c68 342 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 343 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 344 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 345 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
346 else
53419c68
SH		 347 /* set master & slave downshift counter to 1x */
348 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 349
350 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
351 }
352
353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 354 if (sky2_is_copper(hw)) {
05745c4a 355 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 356 /* enable automatic crossover */
357 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 358
359 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
360 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
361 u16 spec;
362
363 /* Enable Class A driver for FE+ A0 */
364 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
365 spec |= PHY_M_FESC_SEL_CL_A;
366 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
367 }
cd28ab6a
SH		 368 } else {
369 /* disable energy detect */
370 ctrl &= ~PHY_M_PC_EN_DET_MSK;
371
372 /* enable automatic crossover */
373 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
374
53419c68 375 /* downshift on PHY 88E1112 and 88E1149 is changed */
0ea065e5 376 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED)
ea76e635 377 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 378 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 379 ctrl &= ~PHY_M_PC_DSC_MSK;
380 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
381 }
382 }
cd28ab6a
SH		 383 } else {
384 /* workaround for deviation #4.88 (CRC errors) */
385 /* disable Automatic Crossover */
386
387 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 388 }
cd28ab6a 389
b89165f2
SH		 390 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
391
392 /* special setup for PHY 88E1112 Fiber */
ea76e635 393 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 394 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 395
b89165f2
SH		 396 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
397 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl &= ~PHY_M_MAC_MD_MSK;
400 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
401 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
402
403 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 404 /* select page 1 to access Fiber registers */
405 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 406
407 /* for SFP-module set SIGDET polarity to low */
408 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
409 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 410 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 411 }
b89165f2
SH		 412
413 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 414 }
415
7800fddc 416 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 417 ct1000 = 0;
418 adv = PHY_AN_CSMA;
2eaba1a2 419 reg = 0;
cd28ab6a 420
0ea065e5 421 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 422 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 423 if (sky2->advertising & ADVERTISED_1000baseT_Full)
424 ct1000 |= PHY_M_1000C_AFD;
425 if (sky2->advertising & ADVERTISED_1000baseT_Half)
426 ct1000 |= PHY_M_1000C_AHD;
427 if (sky2->advertising & ADVERTISED_100baseT_Full)
428 adv |= PHY_M_AN_100_FD;
429 if (sky2->advertising & ADVERTISED_100baseT_Half)
430 adv |= PHY_M_AN_100_HD;
431 if (sky2->advertising & ADVERTISED_10baseT_Full)
432 adv |= PHY_M_AN_10_FD;
433 if (sky2->advertising & ADVERTISED_10baseT_Half)
434 adv |= PHY_M_AN_10_HD;
709c6e7b 435
b89165f2
SH		 436 } else { /* special defines for FIBER (88E1040S only) */
437 if (sky2->advertising & ADVERTISED_1000baseT_Full)
438 adv |= PHY_M_AN_1000X_AFD;
439 if (sky2->advertising & ADVERTISED_1000baseT_Half)
440 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 441 }
cd28ab6a
SH		 442
443 /* Restart Auto-negotiation */
444 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
445 } else {
446 /* forced speed/duplex settings */
447 ct1000 = PHY_M_1000C_MSE;
448
0ea065e5
SH		 449 /* Disable auto update for duplex flow control and duplex */
450 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 451
452 switch (sky2->speed) {
453 case SPEED_1000:
454 ctrl |= PHY_CT_SP1000;
2eaba1a2 455 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 456 break;
457 case SPEED_100:
458 ctrl |= PHY_CT_SP100;
2eaba1a2 459 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 460 break;
461 }
462
2eaba1a2
SH		 463 if (sky2->duplex == DUPLEX_FULL) {
464 reg |= GM_GPCR_DUP_FULL;
465 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 466 } else if (sky2->speed < SPEED_1000)
467 sky2->flow_mode = FC_NONE;
0ea065e5 468 }
2eaba1a2 469
0ea065e5
SH		 470 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
471 if (sky2_is_copper(hw))
472 adv |= copper_fc_adv[sky2->flow_mode];
473 else
474 adv |= fiber_fc_adv[sky2->flow_mode];
475 } else {
476 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 477 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 478
479 /* Forward pause packets to GMAC? */
16ad91e1 480 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 481 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
482 else
483 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 484 }
485
2eaba1a2
SH		 486 gma_write16(hw, port, GM_GP_CTRL, reg);
487
05745c4a 488 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 489 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
490
491 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
492 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
493
494 /* Setup Phy LED's */
495 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
496 ledover = 0;
497
498 switch (hw->chip_id) {
499 case CHIP_ID_YUKON_FE:
500 /* on 88E3082 these bits are at 11..9 (shifted left) */
501 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
502
503 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
504
505 /* delete ACT LED control bits */
506 ctrl &= ~PHY_M_FELP_LED1_MSK;
507 /* change ACT LED control to blink mode */
508 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
509 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
510 break;
511
05745c4a
SH		 512 case CHIP_ID_YUKON_FE_P:
513 /* Enable Link Partner Next Page */
514 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
515 ctrl |= PHY_M_PC_ENA_LIP_NP;
516
517 /* disable Energy Detect and enable scrambler */
518 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
519 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
520
521 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
522 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
523 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
524 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
525
526 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
527 break;
528
cd28ab6a 529 case CHIP_ID_YUKON_XL:
793b883e 530 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 531
532 /* select page 3 to access LED control register */
533 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
534
535 /* set LED Function Control register */
ed6d32c7
SH		 536 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
537 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
538 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
539 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
540 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 541
542 /* set Polarity Control register */
543 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 544 (PHY_M_POLC_LS1_P_MIX(4) |
545 PHY_M_POLC_IS0_P_MIX(4) |
546 PHY_M_POLC_LOS_CTRL(2) |
547 PHY_M_POLC_INIT_CTRL(2) |
548 PHY_M_POLC_STA1_CTRL(2) |
549 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 550
551 /* restore page register */
793b883e 552 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 553 break;
93745494 554
ed6d32c7 555 case CHIP_ID_YUKON_EC_U:
93745494 556 case CHIP_ID_YUKON_EX:
ed4d4161 557 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 558 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
559
560 /* select page 3 to access LED control register */
561 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
562
563 /* set LED Function Control register */
564 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
565 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
566 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
567 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
568 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
569
570 /* set Blink Rate in LED Timer Control Register */
571 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
572 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
573 /* restore page register */
574 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
575 break;
cd28ab6a
SH		 576
577 default:
578 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
579 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 580
cd28ab6a 581 /* turn off the Rx LED (LED_RX) */
a84d0a3d 582 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 583 }
584
0ce8b98d 585 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 586 /* apply fixes in PHY AFE */
ed6d32c7
SH		 587 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
588
977bdf06 589 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 590 gm_phy_write(hw, port, 0x18, 0xaa99);
591 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 592
0ce8b98d
SH		 593 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
594 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
595 gm_phy_write(hw, port, 0x18, 0xa204);
596 gm_phy_write(hw, port, 0x17, 0x2002);
597 }
977bdf06
SH		 598
599 /* set page register to 0 */
9467a8fc 600 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 601 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
602 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
603 /* apply workaround for integrated resistors calibration */
604 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
605 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
e1a74b37
SH		 606 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
607 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 608 /* no effect on Yukon-XL */
977bdf06 609 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 610
0ea065e5
SH		 611 if ( !(sky2->flags & SKY2_FLAG_AUTO_SPEED)
612 || sky2->speed == SPEED_100) {
977bdf06 613 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 614 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 615 }
cd28ab6a 616
977bdf06
SH		 617 if (ledover)
618 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
619
620 }
2eaba1a2 621
d571b694 622 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 623 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 624 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
625 else
626 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
627}
628
b96936da
SH		 629static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
630static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
631
632static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb 633{
634 u32 reg1;
d3bcfbeb 635
82637e80 636 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 637 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 638 reg1 &= ~phy_power[port];
d3bcfbeb 639
b96936da 640 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 641 reg1 |= coma_mode[port];
642
b32f40c4 643 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80
SH		 644 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
645 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 646
647 if (hw->chip_id == CHIP_ID_YUKON_FE)
648 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
649 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
650 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 651}
167f53d0 652
b96936da
SH		 653static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
654{
655 u32 reg1;
db99b988
SH		 656 u16 ctrl;
657
658 /* release GPHY Control reset */
659 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
660
661 /* release GMAC reset */
662 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
663
664 if (hw->flags & SKY2_HW_NEWER_PHY) {
665 /* select page 2 to access MAC control register */
666 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
667
668 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
669 /* allow GMII Power Down */
670 ctrl &= ~PHY_M_MAC_GMIF_PUP;
671 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
672
673 /* set page register back to 0 */
674 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
675 }
676
677 /* setup General Purpose Control Register */
678 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 679 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
680 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
681 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 682
683 if (hw->chip_id != CHIP_ID_YUKON_EC) {
684 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 685 /* select page 2 to access MAC control register */
686 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 687
e484d5f5 688 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 689 /* enable Power Down */
690 ctrl |= PHY_M_PC_POW_D_ENA;
691 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 692
693 /* set page register back to 0 */
694 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 695 }
696
697 /* set IEEE compatible Power Down Mode (dev. #4.99) */
698 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
699 }
b96936da
SH		 700
701 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
702 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 703 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da
SH		 704 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
705 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb 706}
707
1b537565
SH		 708/* Force a renegotiation */
709static void sky2_phy_reinit(struct sky2_port *sky2)
710{
e07b1aa8 711 spin_lock_bh(&sky2->phy_lock);
1b537565 712 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 713 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 714}
715
e3173832
SH		 716/* Put device in state to listen for Wake On Lan */
717static void sky2_wol_init(struct sky2_port *sky2)
718{
719 struct sky2_hw *hw = sky2->hw;
720 unsigned port = sky2->port;
721 enum flow_control save_mode;
722 u16 ctrl;
723 u32 reg1;
724
725 /* Bring hardware out of reset */
726 sky2_write16(hw, B0_CTST, CS_RST_CLR);
727 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
728
729 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
730 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
731
732 /* Force to 10/100
733 * sky2_reset will re-enable on resume
734 */
735 save_mode = sky2->flow_mode;
736 ctrl = sky2->advertising;
737
738 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
739 sky2->flow_mode = FC_NONE;
b96936da
SH		 740
741 spin_lock_bh(&sky2->phy_lock);
742 sky2_phy_power_up(hw, port);
743 sky2_phy_init(hw, port);
744 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 745
746 sky2->flow_mode = save_mode;
747 sky2->advertising = ctrl;
748
749 /* Set GMAC to no flow control and auto update for speed/duplex */
750 gma_write16(hw, port, GM_GP_CTRL,
751 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
752 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
753
754 /* Set WOL address */
755 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
756 sky2->netdev->dev_addr, ETH_ALEN);
757
758 /* Turn on appropriate WOL control bits */
759 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
760 ctrl = 0;
761 if (sky2->wol & WAKE_PHY)
762 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
763 else
764 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
765
766 if (sky2->wol & WAKE_MAGIC)
767 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
768 else
a419aef8 769 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
e3173832
SH		 770
771 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
772 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
773
774 /* Turn on legacy PCI-Express PME mode */
b32f40c4 775 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 776 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 777 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 778
779 /* block receiver */
780 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
781
782}
783
69161611
SH		 784static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
785{
05745c4a
SH		 786 struct net_device *dev = hw->dev[port];
787
ed4d4161
SH		 788 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
789 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
790 hw->chip_id == CHIP_ID_YUKON_FE_P ||
791 hw->chip_id == CHIP_ID_YUKON_SUPR) {
792 /* Yukon-Extreme B0 and further Extreme devices */
793 /* enable Store & Forward mode for TX */
05745c4a 794
ed4d4161
SH		 795 if (dev->mtu <= ETH_DATA_LEN)
796 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
797 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 798
ed4d4161
SH		 799 else
800 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
801 TX_JUMBO_ENA| TX_STFW_ENA);
802 } else {
803 if (dev->mtu <= ETH_DATA_LEN)
804 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
805 else {
806 /* set Tx GMAC FIFO Almost Empty Threshold */
807 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
808 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 809
ed4d4161
SH		 810 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
811
812 /* Can't do offload because of lack of store/forward */
813 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
814 }
69161611
SH		 815 }
816}
817
cd28ab6a
SH		 818static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
819{
820 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
821 u16 reg;
25cccecc 822 u32 rx_reg;
cd28ab6a
SH		 823 int i;
824 const u8 *addr = hw->dev[port]->dev_addr;
825
f350339c
SH		 826 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
827 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 828
829 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
830
793b883e 831 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 832 /* WA DEV_472 -- looks like crossed wires on port 2 */
833 /* clear GMAC 1 Control reset */
834 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
835 do {
836 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
837 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
838 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
839 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
840 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
841 }
842
793b883e 843 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 844
2eaba1a2
SH		 845 /* Enable Transmit FIFO Underrun */
846 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
847
e07b1aa8 848 spin_lock_bh(&sky2->phy_lock);
b96936da 849 sky2_phy_power_up(hw, port);
cd28ab6a 850 sky2_phy_init(hw, port);
e07b1aa8 851 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 852
853 /* MIB clear */
854 reg = gma_read16(hw, port, GM_PHY_ADDR);
855 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
856
43f2f104
SH		 857 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
858 gma_read16(hw, port, i);
cd28ab6a
SH		 859 gma_write16(hw, port, GM_PHY_ADDR, reg);
860
861 /* transmit control */
862 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
863
864 /* receive control reg: unicast + multicast + no FCS */
865 gma_write16(hw, port, GM_RX_CTRL,
793b883e 866 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 867
868 /* transmit flow control */
869 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
870
871 /* transmit parameter */
872 gma_write16(hw, port, GM_TX_PARAM,
873 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
874 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
875 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
876 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
877
878 /* serial mode register */
879 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 880 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 881
6b1a3aef 882 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 883 reg |= GM_SMOD_JUMBO_ENA;
884
885 gma_write16(hw, port, GM_SERIAL_MODE, reg);
886
cd28ab6a
SH		 887 /* virtual address for data */
888 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
889
793b883e
SH		 890 /* physical address: used for pause frames */
891 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
892
893 /* ignore counter overflows */
cd28ab6a
SH		 894 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
895 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
896 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
897
898 /* Configure Rx MAC FIFO */
899 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 900 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 901 if (hw->chip_id == CHIP_ID_YUKON_EX ||
902 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 903 rx_reg |= GMF_RX_OVER_ON;
69161611 904
25cccecc 905 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 906
798fdd07
SH		 907 if (hw->chip_id == CHIP_ID_YUKON_XL) {
908 /* Hardware errata - clear flush mask */
909 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
910 } else {
911 /* Flush Rx MAC FIFO on any flow control or error */
912 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
913 }
cd28ab6a 914
8df9a876 915 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 916 reg = RX_GMF_FL_THR_DEF + 1;
917 /* Another magic mystery workaround from sk98lin */
918 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
919 hw->chip_rev == CHIP_REV_YU_FE2_A0)
920 reg = 0x178;
921 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 922
923 /* Configure Tx MAC FIFO */
924 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
925 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 926
e0c28116 927 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 928 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
d6b54d24
SH		 929 /* Pause threshold is scaled by 8 in bytes */
930 if (hw->chip_id == CHIP_ID_YUKON_FE_P
931 && hw->chip_rev == CHIP_REV_YU_FE2_A0)
932 reg = 1568 / 8;
933 else
934 reg = 1024 / 8;
935 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
936 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
b628ed98 937
69161611 938 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 939 }
940
e970d1f8
SH		 941 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
942 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
943 /* disable dynamic watermark */
944 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
945 reg &= ~TX_DYN_WM_ENA;
946 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
947 }
cd28ab6a
SH		 948}
949
67712901
SH		 950/* Assign Ram Buffer allocation to queue */
951static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 952{
67712901
SH		 953 u32 end;
954
955 /* convert from K bytes to qwords used for hw register */
956 start *= 1024/8;
957 space *= 1024/8;
958 end = start + space - 1;
793b883e 959
cd28ab6a
SH		 960 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
961 sky2_write32(hw, RB_ADDR(q, RB_START), start);
962 sky2_write32(hw, RB_ADDR(q, RB_END), end);
963 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
964 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
965
966 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 967 u32 tp = space - space/4;
793b883e 968
1c28f6ba
SH		 969 /* On receive queue's set the thresholds
970 * give receiver priority when > 3/4 full
971 * send pause when down to 2K
972 */
973 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
974 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 975
1c28f6ba
SH		 976 tp = space - 2048/8;
977 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
978 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 979 } else {
980 /* Enable store & forward on Tx queue's because
981 * Tx FIFO is only 1K on Yukon
982 */
983 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
984 }
985
986 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 987 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 988}
989
cd28ab6a 990/* Setup Bus Memory Interface */
af4ed7e6 991static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 992{
993 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
994 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
995 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 996 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 997}
998
cd28ab6a
SH		 999/* Setup prefetch unit registers. This is the interface between
1000 * hardware and driver list elements
1001 */
8cc048e3 1002static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 1003 dma_addr_t addr, u32 last)
cd28ab6a 1004{
cd28ab6a
SH		 1005 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1006 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 1007 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1008 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 1009 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1010 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1011
1012 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1013}
1014
9b289c33 1015static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1016{
9b289c33 1017 struct sky2_tx_le *le = sky2->tx_le + *slot;
6b84daca 1018 struct tx_ring_info *re = sky2->tx_ring + *slot;
793b883e 1019
ee5f68fe 1020 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
6b84daca
SH		 1021 re->flags = 0;
1022 re->skb = NULL;
291ea614 1023 le->ctrl = 0;
793b883e
SH		 1024 return le;
1025}
cd28ab6a 1026
88f5f0ca
SH		 1027static void tx_init(struct sky2_port *sky2)
1028{
1029 struct sky2_tx_le *le;
1030
1031 sky2->tx_prod = sky2->tx_cons = 0;
1032 sky2->tx_tcpsum = 0;
1033 sky2->tx_last_mss = 0;
1034
9b289c33 1035 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1036 le->addr = 0;
1037 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1038 sky2->tx_last_upper = 0;
88f5f0ca
SH		 1039}
1040
290d4de5
SH		 1041/* Update chip's next pointer */
1042static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1043{
50432cb5 1044 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1045 wmb();
50432cb5
SH		 1046 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1047
1048 /* Synchronize I/O on since next processor may write to tail */
1049 mmiowb();
cd28ab6a
SH		 1050}
1051
793b883e 1052
cd28ab6a
SH		 1053static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1054{
1055 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1056 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1057 le->ctrl = 0;
cd28ab6a
SH		 1058 return le;
1059}
1060
14d0263f
SH		 1061/* Build description to hardware for one receive segment */
1062static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1063 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1064{
1065 struct sky2_rx_le *le;
1066
86c6887e 1067 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1068 le = sky2_next_rx(sky2);
86c6887e 1069 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1070 le->opcode = OP_ADDR64 | HW_OWNER;
1071 }
793b883e 1072
cd28ab6a 1073 le = sky2_next_rx(sky2);
d6e74b6b 1074 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1075 le->length = cpu_to_le16(len);
14d0263f 1076 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1077}
1078
14d0263f
SH		 1079/* Build description to hardware for one possibly fragmented skb */
1080static void sky2_rx_submit(struct sky2_port *sky2,
1081 const struct rx_ring_info *re)
1082{
1083 int i;
1084
1085 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1086
1087 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1088 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1089}
1090
1091
454e6cb6 1092static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1093 unsigned size)
1094{
1095 struct sk_buff *skb = re->skb;
1096 int i;
1097
1098 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
454e6cb6
SH		 1099 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1100 return -EIO;
1101
14d0263f
SH		 1102 pci_unmap_len_set(re, data_size, size);
1103
1104 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1105 re->frag_addr[i] = pci_map_page(pdev,
1106 skb_shinfo(skb)->frags[i].page,
1107 skb_shinfo(skb)->frags[i].page_offset,
1108 skb_shinfo(skb)->frags[i].size,
1109 PCI_DMA_FROMDEVICE);
454e6cb6 1110 return 0;
14d0263f
SH		 1111}
1112
1113static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1114{
1115 struct sk_buff *skb = re->skb;
1116 int i;
1117
1118 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1119 PCI_DMA_FROMDEVICE);
1120
1121 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1122 pci_unmap_page(pdev, re->frag_addr[i],
1123 skb_shinfo(skb)->frags[i].size,
1124 PCI_DMA_FROMDEVICE);
1125}
793b883e 1126
cd28ab6a
SH		 1127/* Tell chip where to start receive checksum.
1128 * Actually has two checksums, but set both same to avoid possible byte
1129 * order problems.
1130 */
793b883e 1131static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1132{
ea76e635 1133 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1134
ea76e635
SH		 1135 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1136 le->ctrl = 0;
1137 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1138
ea76e635
SH		 1139 sky2_write32(sky2->hw,
1140 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
0ea065e5
SH		 1141 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1142 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1143}
1144
6b1a3aef 1145/*
1146 * The RX Stop command will not work for Yukon-2 if the BMU does not
1147 * reach the end of packet and since we can't make sure that we have
1148 * incoming data, we must reset the BMU while it is not doing a DMA
1149 * transfer. Since it is possible that the RX path is still active,
1150 * the RX RAM buffer will be stopped first, so any possible incoming
1151 * data will not trigger a DMA. After the RAM buffer is stopped, the
1152 * BMU is polled until any DMA in progress is ended and only then it
1153 * will be reset.
1154 */
1155static void sky2_rx_stop(struct sky2_port *sky2)
1156{
1157 struct sky2_hw *hw = sky2->hw;
1158 unsigned rxq = rxqaddr[sky2->port];
1159 int i;
1160
1161 /* disable the RAM Buffer receive queue */
1162 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1163
1164 for (i = 0; i < 0xffff; i++)
1165 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1166 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1167 goto stopped;
1168
1169 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1170 sky2->netdev->name);
1171stopped:
1172 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1173
1174 /* reset the Rx prefetch unit */
1175 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1176 mmiowb();
6b1a3aef 1177}
793b883e 1178
d571b694 1179/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1180static void sky2_rx_clean(struct sky2_port *sky2)
1181{
1182 unsigned i;
1183
1184 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1185 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1186 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1187
1188 if (re->skb) {
14d0263f 1189 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1190 kfree_skb(re->skb);
1191 re->skb = NULL;
1192 }
1193 }
1194}
1195
ef743d33 1196/* Basic MII support */
1197static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1198{
1199 struct mii_ioctl_data *data = if_mii(ifr);
1200 struct sky2_port *sky2 = netdev_priv(dev);
1201 struct sky2_hw *hw = sky2->hw;
1202 int err = -EOPNOTSUPP;
1203
1204 if (!netif_running(dev))
1205 return -ENODEV; /* Phy still in reset */
1206
d89e1343 1207 switch (cmd) {
ef743d33 1208 case SIOCGMIIPHY:
1209 data->phy_id = PHY_ADDR_MARV;
1210
1211 /* fallthru */
1212 case SIOCGMIIREG: {
1213 u16 val = 0;
91c86df5 1214
e07b1aa8 1215 spin_lock_bh(&sky2->phy_lock);
ef743d33 1216 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1217 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1218
ef743d33 1219 data->val_out = val;
1220 break;
1221 }
1222
1223 case SIOCSMIIREG:
e07b1aa8 1224 spin_lock_bh(&sky2->phy_lock);
ef743d33 1225 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1226 data->val_in);
e07b1aa8 1227 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1228 break;
1229 }
1230 return err;
1231}
1232
d1f13708 1233#ifdef SKY2_VLAN_TAG_USED
d494eacd 1234static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1235{
d494eacd 1236 if (onoff) {
3d4e66f5
SH		 1237 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1238 RX_VLAN_STRIP_ON);
1239 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1240 TX_VLAN_TAG_ON);
1241 } else {
1242 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1243 RX_VLAN_STRIP_OFF);
1244 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1245 TX_VLAN_TAG_OFF);
1246 }
d494eacd
SH		 1247}
1248
1249static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1250{
1251 struct sky2_port *sky2 = netdev_priv(dev);
1252 struct sky2_hw *hw = sky2->hw;
1253 u16 port = sky2->port;
1254
1255 netif_tx_lock_bh(dev);
1256 napi_disable(&hw->napi);
1257
1258 sky2->vlgrp = grp;
1259 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1260
d1d08d12 1261 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1262 napi_enable(&hw->napi);
2bb8c262 1263 netif_tx_unlock_bh(dev);
d1f13708 1264}
1265#endif
1266
bd1c6869
SH		 1267/* Amount of required worst case padding in rx buffer */
1268static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1269{
1270 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1271}
1272
82788c7a 1273/*
14d0263f
SH		 1274 * Allocate an skb for receiving. If the MTU is large enough
1275 * make the skb non-linear with a fragment list of pages.
82788c7a 1276 */
14d0263f 1277static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1278{
1279 struct sk_buff *skb;
14d0263f 1280 int i;
82788c7a 1281
724b6942
SH		 1282 skb = netdev_alloc_skb(sky2->netdev,
1283 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
bd1c6869
SH		 1284 if (!skb)
1285 goto nomem;
1286
39dbd958 1287 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1288 unsigned char *start;
1289 /*
1290 * Workaround for a bug in FIFO that cause hang
1291 * if the FIFO if the receive buffer is not 64 byte aligned.
1292 * The buffer returned from netdev_alloc_skb is
1293 * aligned except if slab debugging is enabled.
1294 */
f03b8654
SH		 1295 start = PTR_ALIGN(skb->data, 8);
1296 skb_reserve(skb, start - skb->data);
bd1c6869 1297 } else
f03b8654 1298 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1299
1300 for (i = 0; i < sky2->rx_nfrags; i++) {
1301 struct page *page = alloc_page(GFP_ATOMIC);
1302
1303 if (!page)
1304 goto free_partial;
1305 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1306 }
1307
1308 return skb;
14d0263f
SH		 1309free_partial:
1310 kfree_skb(skb);
1311nomem:
1312 return NULL;
82788c7a
SH		 1313}
1314
55c9dd35
SH		 1315static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1316{
1317 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1318}
1319
cd28ab6a
SH		 1320/*
1321 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1322 * Normal case this ends up creating one list element for skb
1323 * in the receive ring. Worst case if using large MTU and each
1324 * allocation falls on a different 64 bit region, that results
1325 * in 6 list elements per ring entry.
1326 * One element is used for checksum enable/disable, and one
1327 * extra to avoid wrap.
cd28ab6a 1328 */
6b1a3aef 1329static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1330{
6b1a3aef 1331 struct sky2_hw *hw = sky2->hw;
14d0263f 1332 struct rx_ring_info *re;
6b1a3aef 1333 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1334 unsigned i, size, thresh;
cd28ab6a 1335
6b1a3aef 1336 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1337 sky2_qset(hw, rxq);
977bdf06 1338
c3905bc4
SH		 1339 /* On PCI express lowering the watermark gives better performance */
1340 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1341 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1342
1343 /* These chips have no ram buffer?
1344 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1345 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1346 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1347 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1348 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1349
6b1a3aef 1350 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1351
ea76e635
SH		 1352 if (!(hw->flags & SKY2_HW_NEW_LE))
1353 rx_set_checksum(sky2);
14d0263f
SH		 1354
1355 /* Space needed for frame data + headers rounded up */
f957da2a 1356 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1357
1358 /* Stopping point for hardware truncation */
1359 thresh = (size - 8) / sizeof(u32);
1360
5f06eba4 1361 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1362 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1363
5f06eba4
SH		 1364 /* Compute residue after pages */
1365 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1366
5f06eba4
SH		 1367 /* Optimize to handle small packets and headers */
1368 if (size < copybreak)
1369 size = copybreak;
1370 if (size < ETH_HLEN)
1371 size = ETH_HLEN;
14d0263f 1372
14d0263f
SH		 1373 sky2->rx_data_size = size;
1374
1375 /* Fill Rx ring */
793b883e 1376 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1377 re = sky2->rx_ring + i;
cd28ab6a 1378
14d0263f 1379 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1380 if (!re->skb)
1381 goto nomem;
1382
454e6cb6
SH		 1383 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1384 dev_kfree_skb(re->skb);
1385 re->skb = NULL;
1386 goto nomem;
1387 }
1388
14d0263f 1389 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1390 }
1391
a1433ac4
SH		 1392 /*
1393 * The receiver hangs if it receives frames larger than the
1394 * packet buffer. As a workaround, truncate oversize frames, but
1395 * the register is limited to 9 bits, so if you do frames > 2052
1396 * you better get the MTU right!
1397 */
a1433ac4
SH		 1398 if (thresh > 0x1ff)
1399 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1400 else {
1401 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1402 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1403 }
1404
6b1a3aef 1405 /* Tell chip about available buffers */
55c9dd35 1406 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1407 return 0;
1408nomem:
1409 sky2_rx_clean(sky2);
1410 return -ENOMEM;
1411}
1412
90bbebb4
MM		 1413static int sky2_alloc_buffers(struct sky2_port *sky2)
1414{
1415 struct sky2_hw *hw = sky2->hw;
1416
1417 /* must be power of 2 */
1418 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1419 sky2->tx_ring_size *
1420 sizeof(struct sky2_tx_le),
1421 &sky2->tx_le_map);
1422 if (!sky2->tx_le)
1423 goto nomem;
1424
1425 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1426 GFP_KERNEL);
1427 if (!sky2->tx_ring)
1428 goto nomem;
1429
1430 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1431 &sky2->rx_le_map);
1432 if (!sky2->rx_le)
1433 goto nomem;
1434 memset(sky2->rx_le, 0, RX_LE_BYTES);
1435
1436 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1437 GFP_KERNEL);
1438 if (!sky2->rx_ring)
1439 goto nomem;
1440
1441 return 0;
1442nomem:
1443 return -ENOMEM;
1444}
1445
1446static void sky2_free_buffers(struct sky2_port *sky2)
1447{
1448 struct sky2_hw *hw = sky2->hw;
1449
1450 if (sky2->rx_le) {
1451 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1452 sky2->rx_le, sky2->rx_le_map);
1453 sky2->rx_le = NULL;
1454 }
1455 if (sky2->tx_le) {
1456 pci_free_consistent(hw->pdev,
1457 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1458 sky2->tx_le, sky2->tx_le_map);
1459 sky2->tx_le = NULL;
1460 }
1461 kfree(sky2->tx_ring);
1462 kfree(sky2->rx_ring);
1463
1464 sky2->tx_ring = NULL;
1465 sky2->rx_ring = NULL;
1466}
1467
cd28ab6a
SH		 1468/* Bring up network interface. */
1469static int sky2_up(struct net_device *dev)
1470{
1471 struct sky2_port *sky2 = netdev_priv(dev);
1472 struct sky2_hw *hw = sky2->hw;
1473 unsigned port = sky2->port;
e0c28116 1474 u32 imask, ramsize;
90bbebb4 1475 int cap, err;
843a46f4 1476 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1477
ee7abb04
SH		 1478 /*
1479 * On dual port PCI-X card, there is an problem where status
1480 * can be received out of order due to split transactions
843a46f4 1481 */
ee7abb04
SH		 1482 if (otherdev && netif_running(otherdev) &&
1483 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1484 u16 cmd;
1485
b32f40c4 1486 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1487 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1488 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1489
ee7abb04 1490 }
843a46f4 1491
55d7b4e6
SH		 1492 netif_carrier_off(dev);
1493
90bbebb4
MM		 1494 err = sky2_alloc_buffers(sky2);
1495 if (err)
cd28ab6a 1496 goto err_out;
88f5f0ca
SH		 1497
1498 tx_init(sky2);
cd28ab6a 1499
cd28ab6a
SH		 1500 sky2_mac_init(hw, port);
1501
e0c28116
SH		 1502 /* Register is number of 4K blocks on internal RAM buffer. */
1503 ramsize = sky2_read8(hw, B2_E_0) * 4;
1504 if (ramsize > 0) {
67712901 1505 u32 rxspace;
cd28ab6a 1506
e0c28116 1507 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1508 if (ramsize < 16)
1509 rxspace = ramsize / 2;
1510 else
1511 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1512
67712901
SH		 1513 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1514 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1515
1516 /* Make sure SyncQ is disabled */
1517 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1518 RB_RST_SET);
1519 }
793b883e 1520
af4ed7e6 1521 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1522
69161611
SH		 1523 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1524 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1525 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1526
977bdf06 1527 /* Set almost empty threshold */
c2716fb4
SH		 1528 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1529 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1530 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1531
6b1a3aef 1532 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
ee5f68fe 1533 sky2->tx_ring_size - 1);
cd28ab6a 1534
d494eacd
SH		 1535#ifdef SKY2_VLAN_TAG_USED
1536 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1537#endif
1538
6b1a3aef 1539 err = sky2_rx_start(sky2);
6de16237 1540 if (err)
cd28ab6a
SH		 1541 goto err_out;
1542
cd28ab6a 1543 /* Enable interrupts from phy/mac for port */
e07b1aa8 1544 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1545 imask |= portirq_msk[port];
e07b1aa8 1546 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1547 sky2_read32(hw, B0_IMSK);
e07b1aa8 1548
a11da890
AD		 1549 if (netif_msg_ifup(sky2))
1550 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
af18d8b8 1551
cd28ab6a
SH		 1552 return 0;
1553
1554err_out:
90bbebb4 1555 sky2_free_buffers(sky2);
cd28ab6a
SH		 1556 return err;
1557}
1558
793b883e 1559/* Modular subtraction in ring */
ee5f68fe 1560static inline int tx_inuse(const struct sky2_port *sky2)
793b883e 1561{
ee5f68fe 1562 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
793b883e 1563}
cd28ab6a 1564
793b883e
SH		 1565/* Number of list elements available for next tx */
1566static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1567{
ee5f68fe 1568 return sky2->tx_pending - tx_inuse(sky2);
cd28ab6a
SH		 1569}
1570
793b883e 1571/* Estimate of number of transmit list elements required */
28bd181a 1572static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1573{
793b883e
SH		 1574 unsigned count;
1575
07e31637
SH		 1576 count = (skb_shinfo(skb)->nr_frags + 1)
1577 * (sizeof(dma_addr_t) / sizeof(u32));
793b883e 1578
89114afd 1579 if (skb_is_gso(skb))
793b883e 1580 ++count;
07e31637
SH		 1581 else if (sizeof(dma_addr_t) == sizeof(u32))
1582 ++count; /* possible vlan */
793b883e 1583
84fa7933 1584 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1585 ++count;
1586
1587 return count;
cd28ab6a
SH		 1588}
1589
6b84daca
SH		 1590static void sky2_tx_unmap(struct pci_dev *pdev,
1591 const struct tx_ring_info *re)
1592{
1593 if (re->flags & TX_MAP_SINGLE)
1594 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1595 pci_unmap_len(re, maplen),
1596 PCI_DMA_TODEVICE);
1597 else if (re->flags & TX_MAP_PAGE)
1598 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1599 pci_unmap_len(re, maplen),
1600 PCI_DMA_TODEVICE);
1601}
1602
793b883e
SH		 1603/*
1604 * Put one packet in ring for transmit.
1605 * A single packet can generate multiple list elements, and
1606 * the number of ring elements will probably be less than the number
1607 * of list elements used.
1608 */
61357325
SH		 1609static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1610 struct net_device *dev)
cd28ab6a
SH		 1611{
1612 struct sky2_port *sky2 = netdev_priv(dev);
1613 struct sky2_hw *hw = sky2->hw;
d1f13708 1614 struct sky2_tx_le *le = NULL;
6cdbbdf3 1615 struct tx_ring_info *re;
9b289c33 1616 unsigned i, len;
cd28ab6a 1617 dma_addr_t mapping;
5dce95e5
SH		 1618 u32 upper;
1619 u16 slot;
cd28ab6a
SH		 1620 u16 mss;
1621 u8 ctrl;
1622
2bb8c262
SH		 1623 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1624 return NETDEV_TX_BUSY;
cd28ab6a 1625
cd28ab6a
SH		 1626 len = skb_headlen(skb);
1627 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1628
454e6cb6
SH		 1629 if (pci_dma_mapping_error(hw->pdev, mapping))
1630 goto mapping_error;
1631
9b289c33 1632 slot = sky2->tx_prod;
454e6cb6
SH		 1633 if (unlikely(netif_msg_tx_queued(sky2)))
1634 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
9b289c33 1635 dev->name, slot, skb->len);
454e6cb6 1636
86c6887e 1637 /* Send high bits if needed */
5dce95e5
SH		 1638 upper = upper_32_bits(mapping);
1639 if (upper != sky2->tx_last_upper) {
9b289c33 1640 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1641 le->addr = cpu_to_le32(upper);
1642 sky2->tx_last_upper = upper;
793b883e 1643 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1644 }
cd28ab6a
SH		 1645
1646 /* Check for TCP Segmentation Offload */
7967168c 1647 mss = skb_shinfo(skb)->gso_size;
793b883e 1648 if (mss != 0) {
ea76e635
SH		 1649
1650 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1651 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1652
1653 if (mss != sky2->tx_last_mss) {
9b289c33 1654 le = get_tx_le(sky2, &slot);
69161611 1655 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1656
1657 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1658 le->opcode = OP_MSS | HW_OWNER;
1659 else
1660 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1661 sky2->tx_last_mss = mss;
1662 }
cd28ab6a
SH		 1663 }
1664
cd28ab6a 1665 ctrl = 0;
d1f13708 1666#ifdef SKY2_VLAN_TAG_USED
1667 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1668 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1669 if (!le) {
9b289c33 1670 le = get_tx_le(sky2, &slot);
f65b138c 1671 le->addr = 0;
d1f13708 1672 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1673 } else
1674 le->opcode |= OP_VLAN;
1675 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1676 ctrl |= INS_VLAN;
1677 }
1678#endif
1679
1680 /* Handle TCP checksum offload */
84fa7933 1681 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1682 /* On Yukon EX (some versions) encoding change. */
ea76e635 1683 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1684 ctrl |= CALSUM; /* auto checksum */
1685 else {
1686 const unsigned offset = skb_transport_offset(skb);
1687 u32 tcpsum;
1688
1689 tcpsum = offset << 16; /* sum start */
1690 tcpsum |= offset + skb->csum_offset; /* sum write */
1691
1692 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1693 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1694 ctrl |= UDPTCP;
1695
1696 if (tcpsum != sky2->tx_tcpsum) {
1697 sky2->tx_tcpsum = tcpsum;
1698
9b289c33 1699 le = get_tx_le(sky2, &slot);
69161611
SH		 1700 le->addr = cpu_to_le32(tcpsum);
1701 le->length = 0; /* initial checksum value */
1702 le->ctrl = 1; /* one packet */
1703 le->opcode = OP_TCPLISW | HW_OWNER;
1704 }
1d179332 1705 }
cd28ab6a
SH		 1706 }
1707
6b84daca
SH		 1708 re = sky2->tx_ring + slot;
1709 re->flags = TX_MAP_SINGLE;
1710 pci_unmap_addr_set(re, mapaddr, mapping);
1711 pci_unmap_len_set(re, maplen, len);
1712
9b289c33 1713 le = get_tx_le(sky2, &slot);
d6e74b6b 1714 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1715 le->length = cpu_to_le16(len);
1716 le->ctrl = ctrl;
793b883e 1717 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1718
cd28ab6a
SH		 1719
1720 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1721 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1722
1723 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1724 frag->size, PCI_DMA_TODEVICE);
86c6887e 1725
454e6cb6
SH		 1726 if (pci_dma_mapping_error(hw->pdev, mapping))
1727 goto mapping_unwind;
1728
5dce95e5
SH		 1729 upper = upper_32_bits(mapping);
1730 if (upper != sky2->tx_last_upper) {
9b289c33 1731 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1732 le->addr = cpu_to_le32(upper);
1733 sky2->tx_last_upper = upper;
793b883e 1734 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1735 }
1736
6b84daca
SH		 1737 re = sky2->tx_ring + slot;
1738 re->flags = TX_MAP_PAGE;
1739 pci_unmap_addr_set(re, mapaddr, mapping);
1740 pci_unmap_len_set(re, maplen, frag->size);
1741
9b289c33 1742 le = get_tx_le(sky2, &slot);
d6e74b6b 1743 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1744 le->length = cpu_to_le16(frag->size);
1745 le->ctrl = ctrl;
793b883e 1746 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1747 }
6cdbbdf3 1748
6b84daca 1749 re->skb = skb;
cd28ab6a
SH		 1750 le->ctrl |= EOP;
1751
9b289c33
MM		 1752 sky2->tx_prod = slot;
1753
97bda706 1754 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1755 netif_stop_queue(dev);
b19666d9 1756
290d4de5 1757 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1758
cd28ab6a 1759 return NETDEV_TX_OK;
454e6cb6
SH		 1760
1761mapping_unwind:
ee5f68fe 1762 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
454e6cb6
SH		 1763 re = sky2->tx_ring + i;
1764
6b84daca 1765 sky2_tx_unmap(hw->pdev, re);
454e6cb6
SH		 1766 }
1767
454e6cb6
SH		 1768mapping_error:
1769 if (net_ratelimit())
1770 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1771 dev_kfree_skb(skb);
1772 return NETDEV_TX_OK;
cd28ab6a
SH		 1773}
1774
cd28ab6a 1775/*
793b883e
SH		 1776 * Free ring elements from starting at tx_cons until "done"
1777 *
481cea4a
SH		 1778 * NB:
1779 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1780 * buffers so make sure not to free skb to early.
481cea4a
SH		 1781 * 2. This may run in parallel start_xmit because the it only
1782 * looks at the tail of the queue of FIFO (tx_cons), not
1783 * the head (tx_prod)
cd28ab6a 1784 */
d11c13e7 1785static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1786{
d11c13e7 1787 struct net_device *dev = sky2->netdev;
291ea614 1788 unsigned idx;
cd28ab6a 1789
ee5f68fe 1790 BUG_ON(done >= sky2->tx_ring_size);
2224795d 1791
291ea614 1792 for (idx = sky2->tx_cons; idx != done;
ee5f68fe 1793 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
291ea614 1794 struct tx_ring_info *re = sky2->tx_ring + idx;
6b84daca 1795 struct sk_buff *skb = re->skb;
291ea614 1796
6b84daca 1797 sky2_tx_unmap(sky2->hw->pdev, re);
bd1c6869 1798
6b84daca 1799 if (skb) {
291ea614
SH		 1800 if (unlikely(netif_msg_tx_done(sky2)))
1801 printk(KERN_DEBUG "%s: tx done %u\n",
1802 dev->name, idx);
3cf26753 1803
7138a0f5 1804 dev->stats.tx_packets++;
bd1c6869
SH		 1805 dev->stats.tx_bytes += skb->len;
1806
724b6942 1807 dev_kfree_skb_any(skb);
2bf56fe2 1808
ee5f68fe 1809 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
cd28ab6a 1810 }
793b883e 1811 }
793b883e 1812
291ea614 1813 sky2->tx_cons = idx;
50432cb5
SH		 1814 smp_mb();
1815
22e11703 1816 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1817 netif_wake_queue(dev);
cd28ab6a
SH		 1818}
1819
264bb4fa 1820static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 1821{
a510996b
MM		 1822 /* Disable Force Sync bit and Enable Alloc bit */
1823 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1824 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1825
1826 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1827 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1828 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1829
1830 /* Reset the PCI FIFO of the async Tx queue */
1831 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1832 BMU_RST_SET | BMU_FIFO_RST);
1833
1834 /* Reset the Tx prefetch units */
1835 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1836 PREF_UNIT_RST_SET);
1837
1838 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1839 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1840}
1841
cd28ab6a
SH		 1842/* Network shutdown */
1843static int sky2_down(struct net_device *dev)
1844{
1845 struct sky2_port *sky2 = netdev_priv(dev);
1846 struct sky2_hw *hw = sky2->hw;
1847 unsigned port = sky2->port;
1848 u16 ctrl;
e07b1aa8 1849 u32 imask;
cd28ab6a 1850
1b537565
SH		 1851 /* Never really got started! */
1852 if (!sky2->tx_le)
1853 return 0;
1854
cd28ab6a
SH		 1855 if (netif_msg_ifdown(sky2))
1856 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1857
d104acaf
SH		 1858 /* Force flow control off */
1859 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1860
cd28ab6a
SH		 1861 /* Stop transmitter */
1862 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1863 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1864
1865 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1866 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1867
1868 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1869 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1870 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1871
1872 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1873
1874 /* Workaround shared GMAC reset */
793b883e
SH		 1875 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1876 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1877 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1878
cd28ab6a 1879 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 1880
6c83504f
SH		 1881 /* Force any delayed status interrrupt and NAPI */
1882 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1883 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1884 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1885 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1886
a947a39d
MM		 1887 sky2_rx_stop(sky2);
1888
1889 /* Disable port IRQ */
1890 imask = sky2_read32(hw, B0_IMSK);
1891 imask &= ~portirq_msk[port];
1892 sky2_write32(hw, B0_IMSK, imask);
1893 sky2_read32(hw, B0_IMSK);
1894
6c83504f
SH		 1895 synchronize_irq(hw->pdev->irq);
1896 napi_synchronize(&hw->napi);
1897
0da6d7b3 1898 spin_lock_bh(&sky2->phy_lock);
b96936da 1899 sky2_phy_power_down(hw, port);
0da6d7b3 1900 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 1901
264bb4fa
MM		 1902 sky2_tx_reset(hw, port);
1903
481cea4a
SH		 1904 /* Free any pending frames stuck in HW queue */
1905 sky2_tx_complete(sky2, sky2->tx_prod);
1906
cd28ab6a
SH		 1907 sky2_rx_clean(sky2);
1908
90bbebb4 1909 sky2_free_buffers(sky2);
1b537565 1910
cd28ab6a
SH		 1911 return 0;
1912}
1913
1914static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1915{
ea76e635 1916 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1917 return SPEED_1000;
1918
05745c4a
SH		 1919 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1920 if (aux & PHY_M_PS_SPEED_100)
1921 return SPEED_100;
1922 else
1923 return SPEED_10;
1924 }
cd28ab6a
SH		 1925
1926 switch (aux & PHY_M_PS_SPEED_MSK) {
1927 case PHY_M_PS_SPEED_1000:
1928 return SPEED_1000;
1929 case PHY_M_PS_SPEED_100:
1930 return SPEED_100;
1931 default:
1932 return SPEED_10;
1933 }
1934}
1935
1936static void sky2_link_up(struct sky2_port *sky2)
1937{
1938 struct sky2_hw *hw = sky2->hw;
1939 unsigned port = sky2->port;
1940 u16 reg;
16ad91e1
SH		 1941 static const char *fc_name[] = {
1942 [FC_NONE] = "none",
1943 [FC_TX] = "tx",
1944 [FC_RX] = "rx",
1945 [FC_BOTH] = "both",
1946 };
cd28ab6a 1947
cd28ab6a 1948 /* enable Rx/Tx */
2eaba1a2 1949 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1950 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1951 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1952
1953 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1954
1955 netif_carrier_on(sky2->netdev);
cd28ab6a 1956
75e80683 1957 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1958
cd28ab6a 1959 /* Turn on link LED */
793b883e 1960 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1961 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1962
1963 if (netif_msg_link(sky2))
1964 printk(KERN_INFO PFX
d571b694 1965 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1966 sky2->netdev->name, sky2->speed,
1967 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1968 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1969}
1970
1971static void sky2_link_down(struct sky2_port *sky2)
1972{
1973 struct sky2_hw *hw = sky2->hw;
1974 unsigned port = sky2->port;
1975 u16 reg;
1976
1977 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1978
1979 reg = gma_read16(hw, port, GM_GP_CTRL);
1980 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1981 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1982
cd28ab6a 1983 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1984
1985 /* Turn on link LED */
1986 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1987
1988 if (netif_msg_link(sky2))
1989 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1990
cd28ab6a
SH		 1991 sky2_phy_init(hw, port);
1992}
1993
16ad91e1
SH		 1994static enum flow_control sky2_flow(int rx, int tx)
1995{
1996 if (rx)
1997 return tx ? FC_BOTH : FC_RX;
1998 else
1999 return tx ? FC_TX : FC_NONE;
2000}
2001
793b883e
SH		 2002static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2003{
2004 struct sky2_hw *hw = sky2->hw;
2005 unsigned port = sky2->port;
da4c1ff4 2006 u16 advert, lpa;
793b883e 2007
da4c1ff4 2008 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2009 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 2010 if (lpa & PHY_M_AN_RF) {
2011 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2012 return -1;
2013 }
2014
793b883e
SH		 2015 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2016 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2017 sky2->netdev->name);
2018 return -1;
2019 }
2020
793b883e 2021 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2022 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2023
da4c1ff4
SH		 2024 /* Since the pause result bits seem to in different positions on
2025 * different chips. look at registers.
2026 */
ea76e635 2027 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2028 /* Shift for bits in fiber PHY */
2029 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2030 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2031
2032 if (advert & ADVERTISE_1000XPAUSE)
2033 advert |= ADVERTISE_PAUSE_CAP;
2034 if (advert & ADVERTISE_1000XPSE_ASYM)
2035 advert |= ADVERTISE_PAUSE_ASYM;
2036 if (lpa & LPA_1000XPAUSE)
2037 lpa |= LPA_PAUSE_CAP;
2038 if (lpa & LPA_1000XPAUSE_ASYM)
2039 lpa |= LPA_PAUSE_ASYM;
2040 }
793b883e 2041
da4c1ff4
SH		 2042 sky2->flow_status = FC_NONE;
2043 if (advert & ADVERTISE_PAUSE_CAP) {
2044 if (lpa & LPA_PAUSE_CAP)
2045 sky2->flow_status = FC_BOTH;
2046 else if (advert & ADVERTISE_PAUSE_ASYM)
2047 sky2->flow_status = FC_RX;
2048 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2049 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2050 sky2->flow_status = FC_TX;
2051 }
793b883e 2052
16ad91e1 2053 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 2054 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2055 sky2->flow_status = FC_NONE;
2eaba1a2 2056
da4c1ff4 2057 if (sky2->flow_status & FC_TX)
793b883e
SH		 2058 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2059 else
2060 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2061
2062 return 0;
2063}
cd28ab6a 2064
e07b1aa8
SH		 2065/* Interrupt from PHY */
2066static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2067{
e07b1aa8
SH		 2068 struct net_device *dev = hw->dev[port];
2069 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2070 u16 istatus, phystat;
2071
ebc646f6
SH		 2072 if (!netif_running(dev))
2073 return;
2074
e07b1aa8
SH		 2075 spin_lock(&sky2->phy_lock);
2076 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2077 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2078
cd28ab6a
SH		 2079 if (netif_msg_intr(sky2))
2080 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2081 sky2->netdev->name, istatus, phystat);
2082
0ea065e5 2083 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 2084 if (sky2_autoneg_done(sky2, phystat) == 0)
2085 sky2_link_up(sky2);
2086 goto out;
2087 }
cd28ab6a 2088
793b883e
SH		 2089 if (istatus & PHY_M_IS_LSP_CHANGE)
2090 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2091
793b883e
SH		 2092 if (istatus & PHY_M_IS_DUP_CHANGE)
2093 sky2->duplex =
2094 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2095
793b883e
SH		 2096 if (istatus & PHY_M_IS_LST_CHANGE) {
2097 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2098 sky2_link_up(sky2);
793b883e
SH		 2099 else
2100 sky2_link_down(sky2);
cd28ab6a 2101 }
793b883e 2102out:
e07b1aa8 2103 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2104}
2105
62335ab0 2106/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2107 * and tx queue is full (stopped).
2108 */
cd28ab6a
SH		 2109static void sky2_tx_timeout(struct net_device *dev)
2110{
2111 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2112 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2113
2114 if (netif_msg_timer(sky2))
2115 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2116
8f24664d 2117 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2118 dev->name, sky2->tx_cons, sky2->tx_prod,
2119 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2120 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2121
81906791
SH		 2122 /* can't restart safely under softirq */
2123 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2124}
2125
2126static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2127{
6b1a3aef 2128 struct sky2_port *sky2 = netdev_priv(dev);
2129 struct sky2_hw *hw = sky2->hw;
b628ed98 2130 unsigned port = sky2->port;
6b1a3aef 2131 int err;
2132 u16 ctl, mode;
e07b1aa8 2133 u32 imask;
cd28ab6a
SH		 2134
2135 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2136 return -EINVAL;
2137
05745c4a
SH		 2138 if (new_mtu > ETH_DATA_LEN &&
2139 (hw->chip_id == CHIP_ID_YUKON_FE ||
2140 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2141 return -EINVAL;
2142
6b1a3aef 2143 if (!netif_running(dev)) {
2144 dev->mtu = new_mtu;
2145 return 0;
2146 }
2147
e07b1aa8 2148 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 2149 sky2_write32(hw, B0_IMSK, 0);
2150
018d1c66 2151 dev->trans_start = jiffies; /* prevent tx timeout */
2152 netif_stop_queue(dev);
bea3348e 2153 napi_disable(&hw->napi);
018d1c66 2154
e07b1aa8
SH		 2155 synchronize_irq(hw->pdev->irq);
2156
39dbd958 2157 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2158 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2159
2160 ctl = gma_read16(hw, port, GM_GP_CTRL);
2161 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 2162 sky2_rx_stop(sky2);
2163 sky2_rx_clean(sky2);
cd28ab6a
SH		 2164
2165 dev->mtu = new_mtu;
14d0263f 2166
6b1a3aef 2167 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2168 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2169
2170 if (dev->mtu > ETH_DATA_LEN)
2171 mode |= GM_SMOD_JUMBO_ENA;
2172
b628ed98 2173 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2174
b628ed98 2175 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2176
6b1a3aef 2177 err = sky2_rx_start(sky2);
e07b1aa8 2178 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2179
d1d08d12 2180 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2181 napi_enable(&hw->napi);
2182
1b537565
SH		 2183 if (err)
2184 dev_close(dev);
2185 else {
b628ed98 2186 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2187
1b537565
SH		 2188 netif_wake_queue(dev);
2189 }
2190
cd28ab6a
SH		 2191 return err;
2192}
2193
14d0263f
SH		 2194/* For small just reuse existing skb for next receive */
2195static struct sk_buff *receive_copy(struct sky2_port *sky2,
2196 const struct rx_ring_info *re,
2197 unsigned length)
2198{
2199 struct sk_buff *skb;
2200
89d71a66 2201 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
14d0263f 2202 if (likely(skb)) {
14d0263f
SH		 2203 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2204 length, PCI_DMA_FROMDEVICE);
d626f62b 2205 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2206 skb->ip_summed = re->skb->ip_summed;
2207 skb->csum = re->skb->csum;
2208 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2209 length, PCI_DMA_FROMDEVICE);
2210 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2211 skb_put(skb, length);
14d0263f
SH		 2212 }
2213 return skb;
2214}
2215
2216/* Adjust length of skb with fragments to match received data */
2217static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2218 unsigned int length)
2219{
2220 int i, num_frags;
2221 unsigned int size;
2222
2223 /* put header into skb */
2224 size = min(length, hdr_space);
2225 skb->tail += size;
2226 skb->len += size;
2227 length -= size;
2228
2229 num_frags = skb_shinfo(skb)->nr_frags;
2230 for (i = 0; i < num_frags; i++) {
2231 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2232
2233 if (length == 0) {
2234 /* don't need this page */
2235 __free_page(frag->page);
2236 --skb_shinfo(skb)->nr_frags;
2237 } else {
2238 size = min(length, (unsigned) PAGE_SIZE);
2239
2240 frag->size = size;
2241 skb->data_len += size;
2242 skb->truesize += size;
2243 skb->len += size;
2244 length -= size;
2245 }
2246 }
2247}
2248
2249/* Normal packet - take skb from ring element and put in a new one */
2250static struct sk_buff *receive_new(struct sky2_port *sky2,
2251 struct rx_ring_info *re,
2252 unsigned int length)
2253{
2254 struct sk_buff *skb, *nskb;
2255 unsigned hdr_space = sky2->rx_data_size;
2256
14d0263f
SH		 2257 /* Don't be tricky about reusing pages (yet) */
2258 nskb = sky2_rx_alloc(sky2);
2259 if (unlikely(!nskb))
2260 return NULL;
2261
2262 skb = re->skb;
2263 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2264
2265 prefetch(skb->data);
2266 re->skb = nskb;
454e6cb6
SH		 2267 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2268 dev_kfree_skb(nskb);
2269 re->skb = skb;
2270 return NULL;
2271 }
14d0263f
SH		 2272
2273 if (skb_shinfo(skb)->nr_frags)
2274 skb_put_frags(skb, hdr_space, length);
2275 else
489b10c1 2276 skb_put(skb, length);
14d0263f
SH		 2277 return skb;
2278}
2279
cd28ab6a
SH		 2280/*
2281 * Receive one packet.
d571b694 2282 * For larger packets, get new buffer.
cd28ab6a 2283 */
497d7c86 2284static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2285 u16 length, u32 status)
2286{
497d7c86 2287 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2288 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2289 struct sk_buff *skb = NULL;
d6532232
SH		 2290 u16 count = (status & GMR_FS_LEN) >> 16;
2291
2292#ifdef SKY2_VLAN_TAG_USED
2293 /* Account for vlan tag */
2294 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2295 count -= VLAN_HLEN;
2296#endif
cd28ab6a
SH		 2297
2298 if (unlikely(netif_msg_rx_status(sky2)))
2299 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2300 dev->name, sky2->rx_next, status, length);
cd28ab6a 2301
793b883e 2302 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2303 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2304
3b12e014
SH		 2305 /* This chip has hardware problems that generates bogus status.
2306 * So do only marginal checking and expect higher level protocols
2307 * to handle crap frames.
2308 */
2309 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2310 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2311 length != count)
2312 goto okay;
2313
42eeea01 2314 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2315 goto error;
2316
42eeea01 2317 if (!(status & GMR_FS_RX_OK))
2318 goto resubmit;
2319
d6532232
SH		 2320 /* if length reported by DMA does not match PHY, packet was truncated */
2321 if (length != count)
3b12e014 2322 goto len_error;
71749531 2323
3b12e014 2324okay:
14d0263f
SH		 2325 if (length < copybreak)
2326 skb = receive_copy(sky2, re, length);
2327 else
2328 skb = receive_new(sky2, re, length);
793b883e 2329resubmit:
14d0263f 2330 sky2_rx_submit(sky2, re);
79e57d32 2331
cd28ab6a
SH		 2332 return skb;
2333
3b12e014 2334len_error:
71749531
SH		 2335 /* Truncation of overlength packets
2336 causes PHY length to not match MAC length */
7138a0f5 2337 ++dev->stats.rx_length_errors;
d6532232 2338 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2339 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2340 dev->name, status, length);
d6532232 2341 goto resubmit;
71749531 2342
cd28ab6a 2343error:
7138a0f5 2344 ++dev->stats.rx_errors;
b6d77734 2345 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2346 dev->stats.rx_over_errors++;
b6d77734
SH		 2347 goto resubmit;
2348 }
6e15b712 2349
3be92a70 2350 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2351 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2352 dev->name, status, length);
793b883e
SH		 2353
2354 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2355 dev->stats.rx_length_errors++;
cd28ab6a 2356 if (status & GMR_FS_FRAGMENT)
7138a0f5 2357 dev->stats.rx_frame_errors++;
cd28ab6a 2358 if (status & GMR_FS_CRC_ERR)
7138a0f5 2359 dev->stats.rx_crc_errors++;
79e57d32 2360
793b883e 2361 goto resubmit;
cd28ab6a
SH		 2362}
2363
e07b1aa8
SH		 2364/* Transmit complete */
2365static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2366{
e07b1aa8 2367 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2368
49d4b8ba 2369 if (netif_running(dev))
e07b1aa8 2370 sky2_tx_complete(sky2, last);
cd28ab6a
SH		 2371}
2372
37e5a243
SH		 2373static inline void sky2_skb_rx(const struct sky2_port *sky2,
2374 u32 status, struct sk_buff *skb)
2375{
2376#ifdef SKY2_VLAN_TAG_USED
2377 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2378 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2379 if (skb->ip_summed == CHECKSUM_NONE)
2380 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2381 else
2382 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2383 vlan_tag, skb);
2384 return;
2385 }
2386#endif
2387 if (skb->ip_summed == CHECKSUM_NONE)
2388 netif_receive_skb(skb);
2389 else
2390 napi_gro_receive(&sky2->hw->napi, skb);
2391}
2392
bf15fe99
SH		 2393static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2394 unsigned packets, unsigned bytes)
2395{
2396 if (packets) {
2397 struct net_device *dev = hw->dev[port];
2398
2399 dev->stats.rx_packets += packets;
2400 dev->stats.rx_bytes += bytes;
2401 dev->last_rx = jiffies;
2402 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2403 }
2404}
2405
e07b1aa8 2406/* Process status response ring */
26691830 2407static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2408{
e07b1aa8 2409 int work_done = 0;
bf15fe99
SH		 2410 unsigned int total_bytes[2] = { 0 };
2411 unsigned int total_packets[2] = { 0 };
a8fd6266 2412
af2a58ac 2413 rmb();
26691830 2414 do {
55c9dd35 2415 struct sky2_port *sky2;
13210ce5 2416 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2417 unsigned port;
13210ce5 2418 struct net_device *dev;
cd28ab6a 2419 struct sk_buff *skb;
cd28ab6a
SH		 2420 u32 status;
2421 u16 length;
ab5adecb
SH		 2422 u8 opcode = le->opcode;
2423
2424 if (!(opcode & HW_OWNER))
2425 break;
cd28ab6a 2426
cb5d9547 2427 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2428
ab5adecb 2429 port = le->css & CSS_LINK_BIT;
69161611 2430 dev = hw->dev[port];
13210ce5 2431 sky2 = netdev_priv(dev);
f65b138c
SH		 2432 length = le16_to_cpu(le->length);
2433 status = le32_to_cpu(le->status);
cd28ab6a 2434
ab5adecb
SH		 2435 le->opcode = 0;
2436 switch (opcode & ~HW_OWNER) {
cd28ab6a 2437 case OP_RXSTAT:
bf15fe99
SH		 2438 total_packets[port]++;
2439 total_bytes[port] += length;
497d7c86 2440 skb = sky2_receive(dev, length, status);
3225b919 2441 if (unlikely(!skb)) {
7138a0f5 2442 dev->stats.rx_dropped++;
55c9dd35 2443 break;
3225b919 2444 }
13210ce5 2445
69161611 2446 /* This chip reports checksum status differently */
05745c4a 2447 if (hw->flags & SKY2_HW_NEW_LE) {
0ea065e5 2448 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
69161611
SH		 2449 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2450 (le->css & CSS_TCPUDPCSOK))
2451 skb->ip_summed = CHECKSUM_UNNECESSARY;
2452 else
2453 skb->ip_summed = CHECKSUM_NONE;
2454 }
2455
13210ce5 2456 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2457
37e5a243 2458 sky2_skb_rx(sky2, status, skb);
13210ce5 2459
22e11703 2460 /* Stop after net poll weight */
13210ce5 2461 if (++work_done >= to_do)
2462 goto exit_loop;
cd28ab6a
SH		 2463 break;
2464
d1f13708 2465#ifdef SKY2_VLAN_TAG_USED
2466 case OP_RXVLAN:
2467 sky2->rx_tag = length;
2468 break;
2469
2470 case OP_RXCHKSVLAN:
2471 sky2->rx_tag = length;
2472 /* fall through */
2473#endif
cd28ab6a 2474 case OP_RXCHKS:
0ea065e5 2475 if (!(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
87418307
SH		 2476 break;
2477
05745c4a
SH		 2478 /* If this happens then driver assuming wrong format */
2479 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2480 if (net_ratelimit())
2481 printk(KERN_NOTICE "%s: unexpected"
2482 " checksum status\n",
2483 dev->name);
69161611 2484 break;
05745c4a 2485 }
69161611 2486
87418307
SH		 2487 /* Both checksum counters are programmed to start at
2488 * the same offset, so unless there is a problem they
2489 * should match. This failure is an early indication that
2490 * hardware receive checksumming won't work.
2491 */
2492 if (likely(status >> 16 == (status & 0xffff))) {
2493 skb = sky2->rx_ring[sky2->rx_next].skb;
2494 skb->ip_summed = CHECKSUM_COMPLETE;
b9389796 2495 skb->csum = le16_to_cpu(status);
87418307
SH		 2496 } else {
2497 printk(KERN_NOTICE PFX "%s: hardware receive "
2498 "checksum problem (status = %#x)\n",
2499 dev->name, status);
0ea065e5
SH		 2500 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2501
87418307 2502 sky2_write32(sky2->hw,
69161611 2503 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2504 BMU_DIS_RX_CHKSUM);
2505 }
cd28ab6a
SH		 2506 break;
2507
2508 case OP_TXINDEXLE:
13b97b74 2509 /* TX index reports status for both ports */
f55925d7 2510 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2511 if (hw->dev[1])
2512 sky2_tx_done(hw->dev[1],
2513 ((status >> 24) & 0xff)
2514 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2515 break;
2516
cd28ab6a
SH		 2517 default:
2518 if (net_ratelimit())
793b883e 2519 printk(KERN_WARNING PFX
ab5adecb 2520 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2521 }
26691830 2522 } while (hw->st_idx != idx);
cd28ab6a 2523
fe2a24df
SH		 2524 /* Fully processed status ring so clear irq */
2525 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2526
13210ce5 2527exit_loop:
bf15fe99
SH		 2528 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2529 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2530
e07b1aa8 2531 return work_done;
cd28ab6a
SH		 2532}
2533
2534static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2535{
2536 struct net_device *dev = hw->dev[port];
2537
3be92a70
SH		 2538 if (net_ratelimit())
2539 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2540 dev->name, status);
cd28ab6a
SH		 2541
2542 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2543 if (net_ratelimit())
2544 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2545 dev->name);
cd28ab6a
SH		 2546 /* Clear IRQ */
2547 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2548 }
2549
2550 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2551 if (net_ratelimit())
2552 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2553 dev->name);
cd28ab6a
SH		 2554
2555 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2556 }
2557
2558 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2559 if (net_ratelimit())
2560 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2561 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2562 }
2563
2564 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2565 if (net_ratelimit())
2566 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2567 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2568 }
2569
2570 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2571 if (net_ratelimit())
2572 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2573 dev->name);
cd28ab6a
SH		 2574 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2575 }
2576}
2577
2578static void sky2_hw_intr(struct sky2_hw *hw)
2579{
555382cb 2580 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2581 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2582 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2583
2584 status &= hwmsk;
cd28ab6a 2585
793b883e 2586 if (status & Y2_IS_TIST_OV)
cd28ab6a 2587 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2588
2589 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2590 u16 pci_err;
2591
82637e80 2592 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2593 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2594 if (net_ratelimit())
555382cb 2595 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2596 pci_err);
cd28ab6a 2597
b32f40c4 2598 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2599 pci_err | PCI_STATUS_ERROR_BITS);
82637e80 2600 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2601 }
2602
2603 if (status & Y2_IS_PCI_EXP) {
d571b694 2604 /* PCI-Express uncorrectable Error occurred */
555382cb 2605 u32 err;
cd28ab6a 2606
82637e80 2607 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2608 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2609 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2610 0xfffffffful);
3be92a70 2611 if (net_ratelimit())
555382cb 2612 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2613
7782c8c4 2614 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
82637e80 2615 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2616 }
2617
2618 if (status & Y2_HWE_L1_MASK)
2619 sky2_hw_error(hw, 0, status);
2620 status >>= 8;
2621 if (status & Y2_HWE_L1_MASK)
2622 sky2_hw_error(hw, 1, status);
2623}
2624
2625static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2626{
2627 struct net_device *dev = hw->dev[port];
2628 struct sky2_port *sky2 = netdev_priv(dev);
2629 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2630
2631 if (netif_msg_intr(sky2))
2632 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2633 dev->name, status);
2634
a3caeada
SH		 2635 if (status & GM_IS_RX_CO_OV)
2636 gma_read16(hw, port, GM_RX_IRQ_SRC);
2637
2638 if (status & GM_IS_TX_CO_OV)
2639 gma_read16(hw, port, GM_TX_IRQ_SRC);
2640
cd28ab6a 2641 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2642 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2643 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2644 }
2645
2646 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2647 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2648 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2649 }
cd28ab6a
SH		 2650}
2651
40b01727 2652/* This should never happen it is a bug. */
c119731d 2653static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH		 2654{
2655 struct net_device *dev = hw->dev[port];
c119731d 2656 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2657
c119731d
SH		 2658 dev_err(&hw->pdev->dev, PFX
2659 "%s: descriptor error q=%#x get=%u put=%u\n",
2660 dev->name, (unsigned) q, (unsigned) idx,
2661 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2662
40b01727 2663 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2664}
cd28ab6a 2665
75e80683
SH		 2666static int sky2_rx_hung(struct net_device *dev)
2667{
2668 struct sky2_port *sky2 = netdev_priv(dev);
2669 struct sky2_hw *hw = sky2->hw;
2670 unsigned port = sky2->port;
2671 unsigned rxq = rxqaddr[port];
2672 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2673 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2674 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2675 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2676
2677 /* If idle and MAC or PCI is stuck */
2678 if (sky2->check.last == dev->last_rx &&
2679 ((mac_rp == sky2->check.mac_rp &&
2680 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2681 /* Check if the PCI RX hang */
2682 (fifo_rp == sky2->check.fifo_rp &&
2683 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2684 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2685 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2686 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2687 return 1;
2688 } else {
2689 sky2->check.last = dev->last_rx;
2690 sky2->check.mac_rp = mac_rp;
2691 sky2->check.mac_lev = mac_lev;
2692 sky2->check.fifo_rp = fifo_rp;
2693 sky2->check.fifo_lev = fifo_lev;
2694 return 0;
2695 }
2696}
2697
32c2c300 2698static void sky2_watchdog(unsigned long arg)
d27ed387 2699{
01bd7564 2700 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2701
75e80683 2702 /* Check for lost IRQ once a second */
32c2c300 2703 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2704 napi_schedule(&hw->napi);
75e80683
SH		 2705 } else {
2706 int i, active = 0;
2707
2708 for (i = 0; i < hw->ports; i++) {
bea3348e 2709 struct net_device *dev = hw->dev[i];
75e80683
SH		 2710 if (!netif_running(dev))
2711 continue;
2712 ++active;
2713
2714 /* For chips with Rx FIFO, check if stuck */
39dbd958 2715 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2716 sky2_rx_hung(dev)) {
2717 pr_info(PFX "%s: receiver hang detected\n",
2718 dev->name);
2719 schedule_work(&hw->restart_work);
2720 return;
2721 }
2722 }
2723
2724 if (active == 0)
2725 return;
32c2c300 2726 }
01bd7564 2727
75e80683 2728 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2729}
2730
40b01727
SH		 2731/* Hardware/software error handling */
2732static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2733{
40b01727
SH		 2734 if (net_ratelimit())
2735 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2736
1e5f1283
SH		 2737 if (status & Y2_IS_HW_ERR)
2738 sky2_hw_intr(hw);
d257924e 2739
1e5f1283
SH		 2740 if (status & Y2_IS_IRQ_MAC1)
2741 sky2_mac_intr(hw, 0);
cd28ab6a 2742
1e5f1283
SH		 2743 if (status & Y2_IS_IRQ_MAC2)
2744 sky2_mac_intr(hw, 1);
cd28ab6a 2745
1e5f1283 2746 if (status & Y2_IS_CHK_RX1)
c119731d 2747 sky2_le_error(hw, 0, Q_R1);
d257924e 2748
1e5f1283 2749 if (status & Y2_IS_CHK_RX2)
c119731d 2750 sky2_le_error(hw, 1, Q_R2);
d257924e 2751
1e5f1283 2752 if (status & Y2_IS_CHK_TXA1)
c119731d 2753 sky2_le_error(hw, 0, Q_XA1);
d257924e 2754
1e5f1283 2755 if (status & Y2_IS_CHK_TXA2)
c119731d 2756 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH		 2757}
2758
bea3348e 2759static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2760{
bea3348e 2761 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2762 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2763 int work_done = 0;
26691830 2764 u16 idx;
40b01727
SH		 2765
2766 if (unlikely(status & Y2_IS_ERROR))
2767 sky2_err_intr(hw, status);
2768
2769 if (status & Y2_IS_IRQ_PHY1)
2770 sky2_phy_intr(hw, 0);
2771
2772 if (status & Y2_IS_IRQ_PHY2)
2773 sky2_phy_intr(hw, 1);
cd28ab6a 2774
26691830
SH		 2775 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2776 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2777
2778 if (work_done >= work_limit)
26691830
SH		 2779 goto done;
2780 }
6f535763 2781
26691830
SH		 2782 napi_complete(napi);
2783 sky2_read32(hw, B0_Y2_SP_LISR);
2784done:
6f535763 2785
bea3348e 2786 return work_done;
e07b1aa8
SH		 2787}
2788
7d12e780 2789static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2790{
2791 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2792 u32 status;
2793
2794 /* Reading this mask interrupts as side effect */
2795 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2796 if (status == 0 || status == ~0)
2797 return IRQ_NONE;
793b883e 2798
e07b1aa8 2799 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2800
2801 napi_schedule(&hw->napi);
793b883e 2802
cd28ab6a
SH		 2803 return IRQ_HANDLED;
2804}
2805
2806#ifdef CONFIG_NET_POLL_CONTROLLER
2807static void sky2_netpoll(struct net_device *dev)
2808{
2809 struct sky2_port *sky2 = netdev_priv(dev);
2810
bea3348e 2811 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2812}
2813#endif
2814
2815/* Chip internal frequency for clock calculations */
05745c4a 2816static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2817{
793b883e 2818 switch (hw->chip_id) {
cd28ab6a 2819 case CHIP_ID_YUKON_EC:
5a5b1ea0 2820 case CHIP_ID_YUKON_EC_U:
93745494 2821 case CHIP_ID_YUKON_EX:
ed4d4161 2822 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2823 case CHIP_ID_YUKON_UL_2:
05745c4a
SH		 2824 return 125;
2825
cd28ab6a 2826 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2827 return 100;
2828
2829 case CHIP_ID_YUKON_FE_P:
2830 return 50;
2831
2832 case CHIP_ID_YUKON_XL:
2833 return 156;
2834
2835 default:
2836 BUG();
cd28ab6a
SH		 2837 }
2838}
2839
fb17358f 2840static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2841{
fb17358f 2842 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2843}
2844
fb17358f 2845static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2846{
fb17358f 2847 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2848}
2849
fb17358f 2850
e3173832 2851static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2852{
b89165f2 2853 u8 t8;
cd28ab6a 2854
167f53d0 2855 /* Enable all clocks and check for bad PCI access */
b32f40c4 2856 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2857
cd28ab6a 2858 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2859
cd28ab6a 2860 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2861 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2862
2863 switch(hw->chip_id) {
2864 case CHIP_ID_YUKON_XL:
39dbd958 2865 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2866 break;
2867
2868 case CHIP_ID_YUKON_EC_U:
2869 hw->flags = SKY2_HW_GIGABIT
2870 | SKY2_HW_NEWER_PHY
2871 | SKY2_HW_ADV_POWER_CTL;
2872 break;
2873
2874 case CHIP_ID_YUKON_EX:
2875 hw->flags = SKY2_HW_GIGABIT
2876 | SKY2_HW_NEWER_PHY
2877 | SKY2_HW_NEW_LE
2878 | SKY2_HW_ADV_POWER_CTL;
2879
2880 /* New transmit checksum */
2881 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2882 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2883 break;
2884
2885 case CHIP_ID_YUKON_EC:
2886 /* This rev is really old, and requires untested workarounds */
2887 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2888 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2889 return -EOPNOTSUPP;
2890 }
39dbd958 2891 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2892 break;
2893
2894 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2895 break;
2896
05745c4a
SH		 2897 case CHIP_ID_YUKON_FE_P:
2898 hw->flags = SKY2_HW_NEWER_PHY
2899 | SKY2_HW_NEW_LE
2900 | SKY2_HW_AUTO_TX_SUM
2901 | SKY2_HW_ADV_POWER_CTL;
2902 break;
ed4d4161
SH		 2903
2904 case CHIP_ID_YUKON_SUPR:
2905 hw->flags = SKY2_HW_GIGABIT
2906 | SKY2_HW_NEWER_PHY
2907 | SKY2_HW_NEW_LE
2908 | SKY2_HW_AUTO_TX_SUM
2909 | SKY2_HW_ADV_POWER_CTL;
2910 break;
2911
0ce8b98d
SH		 2912 case CHIP_ID_YUKON_UL_2:
2913 hw->flags = SKY2_HW_GIGABIT
2914 | SKY2_HW_ADV_POWER_CTL;
2915 break;
2916
ea76e635 2917 default:
b02a9258
SH		 2918 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2919 hw->chip_id);
cd28ab6a
SH		 2920 return -EOPNOTSUPP;
2921 }
2922
ea76e635
SH		 2923 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2924 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2925 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2926
e3173832
SH		 2927 hw->ports = 1;
2928 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2929 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2930 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2931 ++hw->ports;
2932 }
2933
74a61ebf
MM		 2934 if (sky2_read8(hw, B2_E_0))
2935 hw->flags |= SKY2_HW_RAM_BUFFER;
2936
e3173832
SH		 2937 return 0;
2938}
2939
2940static void sky2_reset(struct sky2_hw *hw)
2941{
555382cb 2942 struct pci_dev *pdev = hw->pdev;
e3173832 2943 u16 status;
555382cb
SH		 2944 int i, cap;
2945 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2946
cd28ab6a 2947 /* disable ASF */
4f44d8ba
SH		 2948 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2949 status = sky2_read16(hw, HCU_CCSR);
2950 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2951 HCU_CCSR_UC_STATE_MSK);
2952 sky2_write16(hw, HCU_CCSR, status);
2953 } else
2954 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2955 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2956
2957 /* do a SW reset */
2958 sky2_write8(hw, B0_CTST, CS_RST_SET);
2959 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2960
ac93a394
SH		 2961 /* allow writes to PCI config */
2962 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2963
cd28ab6a 2964 /* clear PCI errors, if any */
b32f40c4 2965 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2966 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2967 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2968
2969 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2970
555382cb
SH		 2971 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2972 if (cap) {
7782c8c4
SH		 2973 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2974 0xfffffffful);
555382cb
SH		 2975
2976 /* If error bit is stuck on ignore it */
2977 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2978 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2979 else
555382cb
SH		 2980 hwe_mask |= Y2_IS_PCI_EXP;
2981 }
cd28ab6a 2982
ae306cca 2983 sky2_power_on(hw);
82637e80 2984 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2985
2986 for (i = 0; i < hw->ports; i++) {
2987 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2988 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 2989
ed4d4161
SH		 2990 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2991 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 2992 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2993 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2994 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2995 }
2996
793b883e
SH		 2997 /* Clear I2C IRQ noise */
2998 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2999
3000 /* turn off hardware timer (unused) */
3001 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3002 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3003
69634ee7
SH		 3004 /* Turn off descriptor polling */
3005 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3006
3007 /* Turn off receive timestamp */
3008 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3009 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3010
3011 /* enable the Tx Arbiters */
3012 for (i = 0; i < hw->ports; i++)
3013 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3014
3015 /* Initialize ram interface */
3016 for (i = 0; i < hw->ports; i++) {
793b883e 3017 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3018
3019 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3020 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3021 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3022 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3023 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3024 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3025 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3026 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3027 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3028 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3029 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3030 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3031 }
3032
555382cb 3033 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3034
cd28ab6a 3035 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3036 sky2_gmac_reset(hw, i);
cd28ab6a 3037
cd28ab6a
SH		 3038 memset(hw->st_le, 0, STATUS_LE_BYTES);
3039 hw->st_idx = 0;
3040
3041 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3042 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3043
3044 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3045 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3046
3047 /* Set the list last index */
793b883e 3048 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3049
290d4de5
SH		 3050 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3051 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3052
290d4de5
SH		 3053 /* set Status-FIFO ISR watermark */
3054 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3055 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3056 else
3057 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3058
290d4de5 3059 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3060 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3061 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3062
793b883e 3063 /* enable status unit */
cd28ab6a
SH		 3064 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3065
3066 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3067 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3068 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3069}
3070
af18d8b8
SH		 3071/* Take device down (offline).
3072 * Equivalent to doing dev_stop() but this does not
3073 * inform upper layers of the transistion.
3074 */
3075static void sky2_detach(struct net_device *dev)
3076{
3077 if (netif_running(dev)) {
3078 netif_device_detach(dev); /* stop txq */
3079 sky2_down(dev);
3080 }
3081}
3082
3083/* Bring device back after doing sky2_detach */
3084static int sky2_reattach(struct net_device *dev)
3085{
3086 int err = 0;
3087
3088 if (netif_running(dev)) {
3089 err = sky2_up(dev);
3090 if (err) {
3091 printk(KERN_INFO PFX "%s: could not restart %d\n",
3092 dev->name, err);
3093 dev_close(dev);
3094 } else {
3095 netif_device_attach(dev);
3096 sky2_set_multicast(dev);
3097 }
3098 }
3099
3100 return err;
3101}
3102
81906791
SH		 3103static void sky2_restart(struct work_struct *work)
3104{
3105 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
af18d8b8 3106 int i;
81906791 3107
81906791 3108 rtnl_lock();
af18d8b8
SH		 3109 for (i = 0; i < hw->ports; i++)
3110 sky2_detach(hw->dev[i]);
81906791 3111
8cfcbe99
SH		 3112 napi_disable(&hw->napi);
3113 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 3114 sky2_reset(hw);
3115 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 3116 napi_enable(&hw->napi);
81906791 3117
af18d8b8
SH		 3118 for (i = 0; i < hw->ports; i++)
3119 sky2_reattach(hw->dev[i]);
81906791 3120
81906791
SH		 3121 rtnl_unlock();
3122}
3123
e3173832
SH		 3124static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3125{
3126 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3127}
3128
3129static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3130{
3131 const struct sky2_port *sky2 = netdev_priv(dev);
3132
3133 wol->supported = sky2_wol_supported(sky2->hw);
3134 wol->wolopts = sky2->wol;
3135}
3136
3137static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3138{
3139 struct sky2_port *sky2 = netdev_priv(dev);
3140 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3141
9d731d77
RW		 3142 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3143 || !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3144 return -EOPNOTSUPP;
3145
3146 sky2->wol = wol->wolopts;
3147
05745c4a
SH		 3148 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3149 hw->chip_id == CHIP_ID_YUKON_EX ||
3150 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 3151 sky2_write32(hw, B0_CTST, sky2->wol
3152 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3153
9d731d77
RW		 3154 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3155
e3173832
SH		 3156 if (!netif_running(dev))
3157 sky2_wol_init(sky2);
cd28ab6a
SH		 3158 return 0;
3159}
3160
28bd181a 3161static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3162{
b89165f2
SH		 3163 if (sky2_is_copper(hw)) {
3164 u32 modes = SUPPORTED_10baseT_Half
3165 | SUPPORTED_10baseT_Full
3166 | SUPPORTED_100baseT_Half
3167 | SUPPORTED_100baseT_Full
3168 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3169
ea76e635 3170 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3171 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3172 | SUPPORTED_1000baseT_Full;
3173 return modes;
cd28ab6a 3174 } else
b89165f2
SH		 3175 return SUPPORTED_1000baseT_Half
3176 | SUPPORTED_1000baseT_Full
3177 | SUPPORTED_Autoneg
3178 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3179}
3180
793b883e 3181static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3182{
3183 struct sky2_port *sky2 = netdev_priv(dev);
3184 struct sky2_hw *hw = sky2->hw;
3185
3186 ecmd->transceiver = XCVR_INTERNAL;
3187 ecmd->supported = sky2_supported_modes(hw);
3188 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3189 if (sky2_is_copper(hw)) {
cd28ab6a 3190 ecmd->port = PORT_TP;
b89165f2
SH		 3191 ecmd->speed = sky2->speed;
3192 } else {
3193 ecmd->speed = SPEED_1000;
cd28ab6a 3194 ecmd->port = PORT_FIBRE;
b89165f2 3195 }
cd28ab6a
SH		 3196
3197 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3198 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3199 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3200 ecmd->duplex = sky2->duplex;
3201 return 0;
3202}
3203
3204static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3205{
3206 struct sky2_port *sky2 = netdev_priv(dev);
3207 const struct sky2_hw *hw = sky2->hw;
3208 u32 supported = sky2_supported_modes(hw);
3209
3210 if (ecmd->autoneg == AUTONEG_ENABLE) {
0ea065e5 3211 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3212 ecmd->advertising = supported;
3213 sky2->duplex = -1;
3214 sky2->speed = -1;
3215 } else {
3216 u32 setting;
3217
793b883e 3218 switch (ecmd->speed) {
cd28ab6a
SH		 3219 case SPEED_1000:
3220 if (ecmd->duplex == DUPLEX_FULL)
3221 setting = SUPPORTED_1000baseT_Full;
3222 else if (ecmd->duplex == DUPLEX_HALF)
3223 setting = SUPPORTED_1000baseT_Half;
3224 else
3225 return -EINVAL;
3226 break;
3227 case SPEED_100:
3228 if (ecmd->duplex == DUPLEX_FULL)
3229 setting = SUPPORTED_100baseT_Full;
3230 else if (ecmd->duplex == DUPLEX_HALF)
3231 setting = SUPPORTED_100baseT_Half;
3232 else
3233 return -EINVAL;
3234 break;
3235
3236 case SPEED_10:
3237 if (ecmd->duplex == DUPLEX_FULL)
3238 setting = SUPPORTED_10baseT_Full;
3239 else if (ecmd->duplex == DUPLEX_HALF)
3240 setting = SUPPORTED_10baseT_Half;
3241 else
3242 return -EINVAL;
3243 break;
3244 default:
3245 return -EINVAL;
3246 }
3247
3248 if ((setting & supported) == 0)
3249 return -EINVAL;
3250
3251 sky2->speed = ecmd->speed;
3252 sky2->duplex = ecmd->duplex;
0ea065e5 3253 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3254 }
3255
cd28ab6a
SH		 3256 sky2->advertising = ecmd->advertising;
3257
d1b139c0 3258 if (netif_running(dev)) {
1b537565 3259 sky2_phy_reinit(sky2);
d1b139c0
SH		 3260 sky2_set_multicast(dev);
3261 }
cd28ab6a
SH		 3262
3263 return 0;
3264}
3265
3266static void sky2_get_drvinfo(struct net_device *dev,
3267 struct ethtool_drvinfo *info)
3268{
3269 struct sky2_port *sky2 = netdev_priv(dev);
3270
3271 strcpy(info->driver, DRV_NAME);
3272 strcpy(info->version, DRV_VERSION);
3273 strcpy(info->fw_version, "N/A");
3274 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3275}
3276
3277static const struct sky2_stat {
793b883e
SH		 3278 char name[ETH_GSTRING_LEN];
3279 u16 offset;
cd28ab6a
SH		 3280} sky2_stats[] = {
3281 { "tx_bytes", GM_TXO_OK_HI },
3282 { "rx_bytes", GM_RXO_OK_HI },
3283 { "tx_broadcast", GM_TXF_BC_OK },
3284 { "rx_broadcast", GM_RXF_BC_OK },
3285 { "tx_multicast", GM_TXF_MC_OK },
3286 { "rx_multicast", GM_RXF_MC_OK },
3287 { "tx_unicast", GM_TXF_UC_OK },
3288 { "rx_unicast", GM_RXF_UC_OK },
3289 { "tx_mac_pause", GM_TXF_MPAUSE },
3290 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3291 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3292 { "late_collision",GM_TXF_LAT_COL },
3293 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3294 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3295 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3296
d2604540 3297 { "rx_short", GM_RXF_SHT },
cd28ab6a 3298 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3299 { "rx_64_byte_packets", GM_RXF_64B },
3300 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3301 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3302 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3303 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3304 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3305 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3306 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3307 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3308 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3309 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3310
3311 { "tx_64_byte_packets", GM_TXF_64B },
3312 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3313 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3314 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3315 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3316 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3317 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3318 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3319};
3320
cd28ab6a
SH		 3321static u32 sky2_get_rx_csum(struct net_device *dev)
3322{
3323 struct sky2_port *sky2 = netdev_priv(dev);
3324
0ea065e5 3325 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
cd28ab6a
SH		 3326}
3327
3328static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3329{
3330 struct sky2_port *sky2 = netdev_priv(dev);
3331
0ea065e5
SH		 3332 if (data)
3333 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3334 else
3335 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
793b883e 3336
cd28ab6a
SH		 3337 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3338 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3339
3340 return 0;
3341}
3342
3343static u32 sky2_get_msglevel(struct net_device *netdev)
3344{
3345 struct sky2_port *sky2 = netdev_priv(netdev);
3346 return sky2->msg_enable;
3347}
3348
9a7ae0a9
SH		 3349static int sky2_nway_reset(struct net_device *dev)
3350{
3351 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3352
0ea065e5 3353 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3354 return -EINVAL;
3355
1b537565 3356 sky2_phy_reinit(sky2);
d1b139c0 3357 sky2_set_multicast(dev);
9a7ae0a9
SH		 3358
3359 return 0;
3360}
3361
793b883e 3362static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3363{
3364 struct sky2_hw *hw = sky2->hw;
3365 unsigned port = sky2->port;
3366 int i;
3367
3368 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3369 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3370 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3371 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3372
793b883e 3373 for (i = 2; i < count; i++)
cd28ab6a
SH		 3374 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3375}
3376
cd28ab6a
SH		 3377static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3378{
3379 struct sky2_port *sky2 = netdev_priv(netdev);
3380 sky2->msg_enable = value;
3381}
3382
b9f2c044 3383static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3384{
b9f2c044
JG		 3385 switch (sset) {
3386 case ETH_SS_STATS:
3387 return ARRAY_SIZE(sky2_stats);
3388 default:
3389 return -EOPNOTSUPP;
3390 }
cd28ab6a
SH		 3391}
3392
3393static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3394 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3395{
3396 struct sky2_port *sky2 = netdev_priv(dev);
3397
793b883e 3398 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3399}
3400
793b883e 3401static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3402{
3403 int i;
3404
3405 switch (stringset) {
3406 case ETH_SS_STATS:
3407 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3408 memcpy(data + i * ETH_GSTRING_LEN,
3409 sky2_stats[i].name, ETH_GSTRING_LEN);
3410 break;
3411 }
3412}
3413
cd28ab6a
SH		 3414static int sky2_set_mac_address(struct net_device *dev, void *p)
3415{
3416 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3417 struct sky2_hw *hw = sky2->hw;
3418 unsigned port = sky2->port;
3419 const struct sockaddr *addr = p;
cd28ab6a
SH		 3420
3421 if (!is_valid_ether_addr(addr->sa_data))
3422 return -EADDRNOTAVAIL;
3423
cd28ab6a 3424 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3425 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3426 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3427 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3428 dev->dev_addr, ETH_ALEN);
1b537565 3429
a8ab1ec0
SH		 3430 /* virtual address for data */
3431 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3432
3433 /* physical address: used for pause frames */
3434 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3435
3436 return 0;
cd28ab6a
SH		 3437}
3438
a052b52f
SH		 3439static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3440{
3441 u32 bit;
3442
3443 bit = ether_crc(ETH_ALEN, addr) & 63;
3444 filter[bit >> 3] |= 1 << (bit & 7);
3445}
3446
cd28ab6a
SH		 3447static void sky2_set_multicast(struct net_device *dev)
3448{
3449 struct sky2_port *sky2 = netdev_priv(dev);
3450 struct sky2_hw *hw = sky2->hw;
3451 unsigned port = sky2->port;
3452 struct dev_mc_list *list = dev->mc_list;
3453 u16 reg;
3454 u8 filter[8];
a052b52f
SH		 3455 int rx_pause;
3456 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3457
a052b52f 3458 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3459 memset(filter, 0, sizeof(filter));
3460
3461 reg = gma_read16(hw, port, GM_RX_CTRL);
3462 reg |= GM_RXCR_UCF_ENA;
3463
d571b694 3464 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3465 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3466 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3467 memset(filter, 0xff, sizeof(filter));
a052b52f 3468 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3469 reg &= ~GM_RXCR_MCF_ENA;
3470 else {
3471 int i;
3472 reg |= GM_RXCR_MCF_ENA;
3473
a052b52f
SH		 3474 if (rx_pause)
3475 sky2_add_filter(filter, pause_mc_addr);
3476
3477 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3478 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3479 }
3480
cd28ab6a 3481 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3482 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3483 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3484 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3485 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3486 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3487 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3488 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3489
3490 gma_write16(hw, port, GM_RX_CTRL, reg);
3491}
3492
3493/* Can have one global because blinking is controlled by
3494 * ethtool and that is always under RTNL mutex
3495 */
a84d0a3d 3496static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3497{
a84d0a3d
SH		 3498 struct sky2_hw *hw = sky2->hw;
3499 unsigned port = sky2->port;
793b883e 3500
a84d0a3d
SH		 3501 spin_lock_bh(&sky2->phy_lock);
3502 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3503 hw->chip_id == CHIP_ID_YUKON_EX ||
3504 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3505 u16 pg;
793b883e
SH		 3506 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3507 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3508
a84d0a3d
SH		 3509 switch (mode) {
3510 case MO_LED_OFF:
3511 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3512 PHY_M_LEDC_LOS_CTRL(8) |
3513 PHY_M_LEDC_INIT_CTRL(8) |
3514 PHY_M_LEDC_STA1_CTRL(8) |
3515 PHY_M_LEDC_STA0_CTRL(8));
3516 break;
3517 case MO_LED_ON:
3518 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3519 PHY_M_LEDC_LOS_CTRL(9) |
3520 PHY_M_LEDC_INIT_CTRL(9) |
3521 PHY_M_LEDC_STA1_CTRL(9) |
3522 PHY_M_LEDC_STA0_CTRL(9));
3523 break;
3524 case MO_LED_BLINK:
3525 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3526 PHY_M_LEDC_LOS_CTRL(0xa) |
3527 PHY_M_LEDC_INIT_CTRL(0xa) |
3528 PHY_M_LEDC_STA1_CTRL(0xa) |
3529 PHY_M_LEDC_STA0_CTRL(0xa));
3530 break;
3531 case MO_LED_NORM:
3532 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3533 PHY_M_LEDC_LOS_CTRL(1) |
3534 PHY_M_LEDC_INIT_CTRL(8) |
3535 PHY_M_LEDC_STA1_CTRL(7) |
3536 PHY_M_LEDC_STA0_CTRL(7));
3537 }
793b883e 3538
a84d0a3d
SH		 3539 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3540 } else
7d2e3cb7 3541 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3542 PHY_M_LED_MO_DUP(mode) |
3543 PHY_M_LED_MO_10(mode) |
3544 PHY_M_LED_MO_100(mode) |
3545 PHY_M_LED_MO_1000(mode) |
3546 PHY_M_LED_MO_RX(mode) |
3547 PHY_M_LED_MO_TX(mode));
3548
3549 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3550}
3551
3552/* blink LED's for finding board */
3553static int sky2_phys_id(struct net_device *dev, u32 data)
3554{
3555 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3556 unsigned int i;
cd28ab6a 3557
a84d0a3d
SH		 3558 if (data == 0)
3559 data = UINT_MAX;
cd28ab6a 3560
a84d0a3d
SH		 3561 for (i = 0; i < data; i++) {
3562 sky2_led(sky2, MO_LED_ON);
3563 if (msleep_interruptible(500))
3564 break;
3565 sky2_led(sky2, MO_LED_OFF);
3566 if (msleep_interruptible(500))
3567 break;
793b883e 3568 }
a84d0a3d 3569 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3570
3571 return 0;
3572}
3573
3574static void sky2_get_pauseparam(struct net_device *dev,
3575 struct ethtool_pauseparam *ecmd)
3576{
3577 struct sky2_port *sky2 = netdev_priv(dev);
3578
16ad91e1
SH		 3579 switch (sky2->flow_mode) {
3580 case FC_NONE:
3581 ecmd->tx_pause = ecmd->rx_pause = 0;
3582 break;
3583 case FC_TX:
3584 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3585 break;
3586 case FC_RX:
3587 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3588 break;
3589 case FC_BOTH:
3590 ecmd->tx_pause = ecmd->rx_pause = 1;
3591 }
3592
0ea065e5
SH		 3593 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3594 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3595}
3596
3597static int sky2_set_pauseparam(struct net_device *dev,
3598 struct ethtool_pauseparam *ecmd)
3599{
3600 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3601
0ea065e5
SH		 3602 if (ecmd->autoneg == AUTONEG_ENABLE)
3603 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3604 else
3605 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3606
16ad91e1 3607 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3608
16ad91e1
SH		 3609 if (netif_running(dev))
3610 sky2_phy_reinit(sky2);
cd28ab6a 3611
2eaba1a2 3612 return 0;
cd28ab6a
SH		 3613}
3614
fb17358f
SH		 3615static int sky2_get_coalesce(struct net_device *dev,
3616 struct ethtool_coalesce *ecmd)
3617{
3618 struct sky2_port *sky2 = netdev_priv(dev);
3619 struct sky2_hw *hw = sky2->hw;
3620
3621 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3622 ecmd->tx_coalesce_usecs = 0;
3623 else {
3624 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3625 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3626 }
3627 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3628
3629 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3630 ecmd->rx_coalesce_usecs = 0;
3631 else {
3632 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3633 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3634 }
3635 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3636
3637 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3638 ecmd->rx_coalesce_usecs_irq = 0;
3639 else {
3640 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3641 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3642 }
3643
3644 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3645
3646 return 0;
3647}
3648
3649/* Note: this affect both ports */
3650static int sky2_set_coalesce(struct net_device *dev,
3651 struct ethtool_coalesce *ecmd)
3652{
3653 struct sky2_port *sky2 = netdev_priv(dev);
3654 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3655 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3656
77b3d6a2
SH		 3657 if (ecmd->tx_coalesce_usecs > tmax ||
3658 ecmd->rx_coalesce_usecs > tmax ||
3659 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3660 return -EINVAL;
3661
ee5f68fe 3662 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
fb17358f 3663 return -EINVAL;
ff81fbbe 3664 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3665 return -EINVAL;
ff81fbbe 3666 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3667 return -EINVAL;
3668
3669 if (ecmd->tx_coalesce_usecs == 0)
3670 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3671 else {
3672 sky2_write32(hw, STAT_TX_TIMER_INI,
3673 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3674 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3675 }
3676 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3677
3678 if (ecmd->rx_coalesce_usecs == 0)
3679 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3680 else {
3681 sky2_write32(hw, STAT_LEV_TIMER_INI,
3682 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3683 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3684 }
3685 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3686
3687 if (ecmd->rx_coalesce_usecs_irq == 0)
3688 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3689 else {
d28d4870 3690 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3691 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3692 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3693 }
3694 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3695 return 0;
3696}
3697
793b883e
SH		 3698static void sky2_get_ringparam(struct net_device *dev,
3699 struct ethtool_ringparam *ering)
3700{
3701 struct sky2_port *sky2 = netdev_priv(dev);
3702
3703 ering->rx_max_pending = RX_MAX_PENDING;
3704 ering->rx_mini_max_pending = 0;
3705 ering->rx_jumbo_max_pending = 0;
ee5f68fe 3706 ering->tx_max_pending = TX_MAX_PENDING;
793b883e
SH		 3707
3708 ering->rx_pending = sky2->rx_pending;
3709 ering->rx_mini_pending = 0;
3710 ering->rx_jumbo_pending = 0;
3711 ering->tx_pending = sky2->tx_pending;
3712}
3713
3714static int sky2_set_ringparam(struct net_device *dev,
3715 struct ethtool_ringparam *ering)
3716{
3717 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 3718
3719 if (ering->rx_pending > RX_MAX_PENDING ||
3720 ering->rx_pending < 8 ||
ee5f68fe
SH		 3721 ering->tx_pending < TX_MIN_PENDING ||
3722 ering->tx_pending > TX_MAX_PENDING)
793b883e
SH		 3723 return -EINVAL;
3724
af18d8b8 3725 sky2_detach(dev);
793b883e
SH		 3726
3727 sky2->rx_pending = ering->rx_pending;
3728 sky2->tx_pending = ering->tx_pending;
ee5f68fe 3729 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
793b883e 3730
af18d8b8 3731 return sky2_reattach(dev);
793b883e
SH		 3732}
3733
793b883e
SH		 3734static int sky2_get_regs_len(struct net_device *dev)
3735{
6e4cbb34 3736 return 0x4000;
793b883e
SH		 3737}
3738
3739/*
3740 * Returns copy of control register region
3ead5db7 3741 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3742 */
3743static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3744 void *p)
3745{
3746 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3747 const void __iomem *io = sky2->hw->regs;
295b54c4 3748 unsigned int b;
793b883e
SH		 3749
3750 regs->version = 1;
793b883e 3751
295b54c4
SH		 3752 for (b = 0; b < 128; b++) {
3753 /* This complicated switch statement is to make sure and
3754 * only access regions that are unreserved.
3755 * Some blocks are only valid on dual port cards.
3756 * and block 3 has some special diagnostic registers that
3757 * are poison.
3758 */
3759 switch (b) {
3760 case 3:
3761 /* skip diagnostic ram region */
3762 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3763 break;
3ead5db7 3764
295b54c4
SH		 3765 /* dual port cards only */
3766 case 5: /* Tx Arbiter 2 */
3767 case 9: /* RX2 */
3768 case 14 ... 15: /* TX2 */
3769 case 17: case 19: /* Ram Buffer 2 */
3770 case 22 ... 23: /* Tx Ram Buffer 2 */
3771 case 25: /* Rx MAC Fifo 1 */
3772 case 27: /* Tx MAC Fifo 2 */
3773 case 31: /* GPHY 2 */
3774 case 40 ... 47: /* Pattern Ram 2 */
3775 case 52: case 54: /* TCP Segmentation 2 */
3776 case 112 ... 116: /* GMAC 2 */
3777 if (sky2->hw->ports == 1)
3778 goto reserved;
3779 /* fall through */
3780 case 0: /* Control */
3781 case 2: /* Mac address */
3782 case 4: /* Tx Arbiter 1 */
3783 case 7: /* PCI express reg */
3784 case 8: /* RX1 */
3785 case 12 ... 13: /* TX1 */
3786 case 16: case 18:/* Rx Ram Buffer 1 */
3787 case 20 ... 21: /* Tx Ram Buffer 1 */
3788 case 24: /* Rx MAC Fifo 1 */
3789 case 26: /* Tx MAC Fifo 1 */
3790 case 28 ... 29: /* Descriptor and status unit */
3791 case 30: /* GPHY 1*/
3792 case 32 ... 39: /* Pattern Ram 1 */
3793 case 48: case 50: /* TCP Segmentation 1 */
3794 case 56 ... 60: /* PCI space */
3795 case 80 ... 84: /* GMAC 1 */
3796 memcpy_fromio(p, io, 128);
3797 break;
3798 default:
3799reserved:
3800 memset(p, 0, 128);
3801 }
3ead5db7 3802
295b54c4
SH		 3803 p += 128;
3804 io += 128;
3805 }
793b883e 3806}
cd28ab6a 3807
b628ed98
SH		 3808/* In order to do Jumbo packets on these chips, need to turn off the
3809 * transmit store/forward. Therefore checksum offload won't work.
3810 */
3811static int no_tx_offload(struct net_device *dev)
3812{
3813 const struct sky2_port *sky2 = netdev_priv(dev);
3814 const struct sky2_hw *hw = sky2->hw;
3815
69161611 3816 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3817}
3818
3819static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3820{
3821 if (data && no_tx_offload(dev))
3822 return -EINVAL;
3823
3824 return ethtool_op_set_tx_csum(dev, data);
3825}
3826
3827
3828static int sky2_set_tso(struct net_device *dev, u32 data)
3829{
3830 if (data && no_tx_offload(dev))
3831 return -EINVAL;
3832
3833 return ethtool_op_set_tso(dev, data);
3834}
3835
f4331a6d
SH		 3836static int sky2_get_eeprom_len(struct net_device *dev)
3837{
3838 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3839 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3840 u16 reg2;
3841
b32f40c4 3842 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3843 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3844}
3845
1413235c 3846static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 3847{
1413235c 3848 unsigned long start = jiffies;
f4331a6d 3849
1413235c
SH		 3850 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3851 /* Can take up to 10.6 ms for write */
3852 if (time_after(jiffies, start + HZ/4)) {
3853 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3854 return -ETIMEDOUT;
3855 }
3856 mdelay(1);
3857 }
167f53d0 3858
1413235c
SH		 3859 return 0;
3860}
167f53d0 3861
1413235c
SH		 3862static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3863 u16 offset, size_t length)
3864{
3865 int rc = 0;
3866
3867 while (length > 0) {
3868 u32 val;
3869
3870 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3871 rc = sky2_vpd_wait(hw, cap, 0);
3872 if (rc)
3873 break;
3874
3875 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3876
3877 memcpy(data, &val, min(sizeof(val), length));
3878 offset += sizeof(u32);
3879 data += sizeof(u32);
3880 length -= sizeof(u32);
3881 }
3882
3883 return rc;
f4331a6d
SH		 3884}
3885
1413235c
SH		 3886static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3887 u16 offset, unsigned int length)
f4331a6d 3888{
1413235c
SH		 3889 unsigned int i;
3890 int rc = 0;
3891
3892 for (i = 0; i < length; i += sizeof(u32)) {
3893 u32 val = *(u32 *)(data + i);
3894
3895 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3896 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3897
3898 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3899 if (rc)
3900 break;
3901 }
3902 return rc;
f4331a6d
SH		 3903}
3904
3905static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3906 u8 *data)
3907{
3908 struct sky2_port *sky2 = netdev_priv(dev);
3909 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3910
3911 if (!cap)
3912 return -EINVAL;
3913
3914 eeprom->magic = SKY2_EEPROM_MAGIC;
3915
1413235c 3916 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3917}
3918
3919static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3920 u8 *data)
3921{
3922 struct sky2_port *sky2 = netdev_priv(dev);
3923 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3924
3925 if (!cap)
3926 return -EINVAL;
3927
3928 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3929 return -EINVAL;
3930
1413235c
SH		 3931 /* Partial writes not supported */
3932 if ((eeprom->offset & 3) || (eeprom->len & 3))
3933 return -EINVAL;
f4331a6d 3934
1413235c 3935 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3936}
3937
3938
7282d491 3939static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3940 .get_settings = sky2_get_settings,
3941 .set_settings = sky2_set_settings,
3942 .get_drvinfo = sky2_get_drvinfo,
3943 .get_wol = sky2_get_wol,
3944 .set_wol = sky2_set_wol,
3945 .get_msglevel = sky2_get_msglevel,
3946 .set_msglevel = sky2_set_msglevel,
3947 .nway_reset = sky2_nway_reset,
3948 .get_regs_len = sky2_get_regs_len,
3949 .get_regs = sky2_get_regs,
3950 .get_link = ethtool_op_get_link,
3951 .get_eeprom_len = sky2_get_eeprom_len,
3952 .get_eeprom = sky2_get_eeprom,
3953 .set_eeprom = sky2_set_eeprom,
f4331a6d 3954 .set_sg = ethtool_op_set_sg,
f4331a6d 3955 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3956 .set_tso = sky2_set_tso,
3957 .get_rx_csum = sky2_get_rx_csum,
3958 .set_rx_csum = sky2_set_rx_csum,
3959 .get_strings = sky2_get_strings,
3960 .get_coalesce = sky2_get_coalesce,
3961 .set_coalesce = sky2_set_coalesce,
3962 .get_ringparam = sky2_get_ringparam,
3963 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3964 .get_pauseparam = sky2_get_pauseparam,
3965 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3966 .phys_id = sky2_phys_id,
b9f2c044 3967 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3968 .get_ethtool_stats = sky2_get_ethtool_stats,
3969};
3970
3cf26753
SH		 3971#ifdef CONFIG_SKY2_DEBUG
3972
3973static struct dentry *sky2_debug;
3974
e4c2abe2
SH		 3975
3976/*
3977 * Read and parse the first part of Vital Product Data
3978 */
3979#define VPD_SIZE 128
3980#define VPD_MAGIC 0x82
3981
3982static const struct vpd_tag {
3983 char tag[2];
3984 char *label;
3985} vpd_tags[] = {
3986 { "PN", "Part Number" },
3987 { "EC", "Engineering Level" },
3988 { "MN", "Manufacturer" },
3989 { "SN", "Serial Number" },
3990 { "YA", "Asset Tag" },
3991 { "VL", "First Error Log Message" },
3992 { "VF", "Second Error Log Message" },
3993 { "VB", "Boot Agent ROM Configuration" },
3994 { "VE", "EFI UNDI Configuration" },
3995};
3996
3997static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
3998{
3999 size_t vpd_size;
4000 loff_t offs;
4001 u8 len;
4002 unsigned char *buf;
4003 u16 reg2;
4004
4005 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4006 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4007
4008 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4009 buf = kmalloc(vpd_size, GFP_KERNEL);
4010 if (!buf) {
4011 seq_puts(seq, "no memory!\n");
4012 return;
4013 }
4014
4015 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4016 seq_puts(seq, "VPD read failed\n");
4017 goto out;
4018 }
4019
4020 if (buf[0] != VPD_MAGIC) {
4021 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4022 goto out;
4023 }
4024 len = buf[1];
4025 if (len == 0 || len > vpd_size - 4) {
4026 seq_printf(seq, "Invalid id length: %d\n", len);
4027 goto out;
4028 }
4029
4030 seq_printf(seq, "%.*s\n", len, buf + 3);
4031 offs = len + 3;
4032
4033 while (offs < vpd_size - 4) {
4034 int i;
4035
4036 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4037 break;
4038 len = buf[offs + 2];
4039 if (offs + len + 3 >= vpd_size)
4040 break;
4041
4042 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4043 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4044 seq_printf(seq, " %s: %.*s\n",
4045 vpd_tags[i].label, len, buf + offs + 3);
4046 break;
4047 }
4048 }
4049 offs += len + 3;
4050 }
4051out:
4052 kfree(buf);
4053}
4054
3cf26753
SH		 4055static int sky2_debug_show(struct seq_file *seq, void *v)
4056{
4057 struct net_device *dev = seq->private;
4058 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4059 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4060 unsigned port = sky2->port;
4061 unsigned idx, last;
4062 int sop;
4063
e4c2abe2 4064 sky2_show_vpd(seq, hw);
3cf26753 4065
e4c2abe2 4066 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4067 sky2_read32(hw, B0_ISRC),
4068 sky2_read32(hw, B0_IMSK),
4069 sky2_read32(hw, B0_Y2_SP_ICR));
4070
e4c2abe2
SH		 4071 if (!netif_running(dev)) {
4072 seq_printf(seq, "network not running\n");
4073 return 0;
4074 }
4075
bea3348e 4076 napi_disable(&hw->napi);
3cf26753
SH		 4077 last = sky2_read16(hw, STAT_PUT_IDX);
4078
4079 if (hw->st_idx == last)
4080 seq_puts(seq, "Status ring (empty)\n");
4081 else {
4082 seq_puts(seq, "Status ring\n");
4083 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4084 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4085 const struct sky2_status_le *le = hw->st_le + idx;
4086 seq_printf(seq, "[%d] %#x %d %#x\n",
4087 idx, le->opcode, le->length, le->status);
4088 }
4089 seq_puts(seq, "\n");
4090 }
4091
4092 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4093 sky2->tx_cons, sky2->tx_prod,
4094 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4095 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4096
4097 /* Dump contents of tx ring */
4098 sop = 1;
ee5f68fe
SH		 4099 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4100 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
3cf26753
SH		 4101 const struct sky2_tx_le *le = sky2->tx_le + idx;
4102 u32 a = le32_to_cpu(le->addr);
4103
4104 if (sop)
4105 seq_printf(seq, "%u:", idx);
4106 sop = 0;
4107
4108 switch(le->opcode & ~HW_OWNER) {
4109 case OP_ADDR64:
4110 seq_printf(seq, " %#x:", a);
4111 break;
4112 case OP_LRGLEN:
4113 seq_printf(seq, " mtu=%d", a);
4114 break;
4115 case OP_VLAN:
4116 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4117 break;
4118 case OP_TCPLISW:
4119 seq_printf(seq, " csum=%#x", a);
4120 break;
4121 case OP_LARGESEND:
4122 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4123 break;
4124 case OP_PACKET:
4125 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4126 break;
4127 case OP_BUFFER:
4128 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4129 break;
4130 default:
4131 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4132 a, le16_to_cpu(le->length));
4133 }
4134
4135 if (le->ctrl & EOP) {
4136 seq_putc(seq, '\n');
4137 sop = 1;
4138 }
4139 }
4140
4141 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4142 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4143 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4144 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4145
d1d08d12 4146 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4147 napi_enable(&hw->napi);
3cf26753
SH		 4148 return 0;
4149}
4150
4151static int sky2_debug_open(struct inode *inode, struct file *file)
4152{
4153 return single_open(file, sky2_debug_show, inode->i_private);
4154}
4155
4156static const struct file_operations sky2_debug_fops = {
4157 .owner = THIS_MODULE,
4158 .open = sky2_debug_open,
4159 .read = seq_read,
4160 .llseek = seq_lseek,
4161 .release = single_release,
4162};
4163
4164/*
4165 * Use network device events to create/remove/rename
4166 * debugfs file entries
4167 */
4168static int sky2_device_event(struct notifier_block *unused,
4169 unsigned long event, void *ptr)
4170{
4171 struct net_device *dev = ptr;
5b296bc9 4172 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4173
1436b301 4174 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4175 return NOTIFY_DONE;
3cf26753 4176
5b296bc9
SH		 4177 switch(event) {
4178 case NETDEV_CHANGENAME:
4179 if (sky2->debugfs) {
4180 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4181 sky2_debug, dev->name);
4182 }
4183 break;
3cf26753 4184
5b296bc9
SH		 4185 case NETDEV_GOING_DOWN:
4186 if (sky2->debugfs) {
4187 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4188 dev->name);
4189 debugfs_remove(sky2->debugfs);
4190 sky2->debugfs = NULL;
3cf26753 4191 }
5b296bc9
SH		 4192 break;
4193
4194 case NETDEV_UP:
4195 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4196 sky2_debug, dev,
4197 &sky2_debug_fops);
4198 if (IS_ERR(sky2->debugfs))
4199 sky2->debugfs = NULL;
3cf26753
SH		 4200 }
4201
4202 return NOTIFY_DONE;
4203}
4204
4205static struct notifier_block sky2_notifier = {
4206 .notifier_call = sky2_device_event,
4207};
4208
4209
4210static __init void sky2_debug_init(void)
4211{
4212 struct dentry *ent;
4213
4214 ent = debugfs_create_dir("sky2", NULL);
4215 if (!ent || IS_ERR(ent))
4216 return;
4217
4218 sky2_debug = ent;
4219 register_netdevice_notifier(&sky2_notifier);
4220}
4221
4222static __exit void sky2_debug_cleanup(void)
4223{
4224 if (sky2_debug) {
4225 unregister_netdevice_notifier(&sky2_notifier);
4226 debugfs_remove(sky2_debug);
4227 sky2_debug = NULL;
4228 }
4229}
4230
4231#else
4232#define sky2_debug_init()
4233#define sky2_debug_cleanup()
4234#endif
4235
1436b301
SH		 4236/* Two copies of network device operations to handle special case of
4237 not allowing netpoll on second port */
4238static const struct net_device_ops sky2_netdev_ops[2] = {
4239 {
4240 .ndo_open = sky2_up,
4241 .ndo_stop = sky2_down,
00829823 4242 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4243 .ndo_do_ioctl = sky2_ioctl,
4244 .ndo_validate_addr = eth_validate_addr,
4245 .ndo_set_mac_address = sky2_set_mac_address,
4246 .ndo_set_multicast_list = sky2_set_multicast,
4247 .ndo_change_mtu = sky2_change_mtu,
4248 .ndo_tx_timeout = sky2_tx_timeout,
4249#ifdef SKY2_VLAN_TAG_USED
4250 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4251#endif
4252#ifdef CONFIG_NET_POLL_CONTROLLER
4253 .ndo_poll_controller = sky2_netpoll,
4254#endif
4255 },
4256 {
4257 .ndo_open = sky2_up,
4258 .ndo_stop = sky2_down,
00829823 4259 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4260 .ndo_do_ioctl = sky2_ioctl,
4261 .ndo_validate_addr = eth_validate_addr,
4262 .ndo_set_mac_address = sky2_set_mac_address,
4263 .ndo_set_multicast_list = sky2_set_multicast,
4264 .ndo_change_mtu = sky2_change_mtu,
4265 .ndo_tx_timeout = sky2_tx_timeout,
4266#ifdef SKY2_VLAN_TAG_USED
4267 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4268#endif
4269 },
4270};
3cf26753 4271
cd28ab6a
SH		 4272/* Initialize network device */
4273static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4274 unsigned port,
be63a21c 4275 int highmem, int wol)
cd28ab6a
SH		 4276{
4277 struct sky2_port *sky2;
4278 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4279
4280 if (!dev) {
898eb71c 4281 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4282 return NULL;
4283 }
4284
cd28ab6a 4285 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4286 dev->irq = hw->pdev->irq;
cd28ab6a 4287 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4288 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4289 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4290
4291 sky2 = netdev_priv(dev);
4292 sky2->netdev = dev;
4293 sky2->hw = hw;
4294 sky2->msg_enable = netif_msg_init(debug, default_msg);
4295
cd28ab6a 4296 /* Auto speed and flow control */
0ea065e5
SH		 4297 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4298 if (hw->chip_id != CHIP_ID_YUKON_XL)
4299 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4300
16ad91e1
SH		 4301 sky2->flow_mode = FC_BOTH;
4302
cd28ab6a
SH		 4303 sky2->duplex = -1;
4304 sky2->speed = -1;
4305 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4306 sky2->wol = wol;
75d070c5 4307
e07b1aa8 4308 spin_lock_init(&sky2->phy_lock);
ee5f68fe 4309
793b883e 4310 sky2->tx_pending = TX_DEF_PENDING;
ee5f68fe 4311 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
290d4de5 4312 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4313
4314 hw->dev[port] = dev;
4315
4316 sky2->port = port;
4317
4a50a876 4318 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4319 if (highmem)
4320 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4321
d1f13708 4322#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4323 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4324 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4325 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4326 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4327 }
d1f13708 4328#endif
4329
cd28ab6a 4330 /* read the mac address */
793b883e 4331 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4332 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4333
cd28ab6a
SH		 4334 return dev;
4335}
4336
28bd181a 4337static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4338{
4339 const struct sky2_port *sky2 = netdev_priv(dev);
4340
4341 if (netif_msg_probe(sky2))
e174961c
JB		 4342 printk(KERN_INFO PFX "%s: addr %pM\n",
4343 dev->name, dev->dev_addr);
cd28ab6a
SH		 4344}
4345
fb2690a9 4346/* Handle software interrupt used during MSI test */
7d12e780 4347static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4348{
4349 struct sky2_hw *hw = dev_id;
4350 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4351
4352 if (status == 0)
4353 return IRQ_NONE;
4354
4355 if (status & Y2_IS_IRQ_SW) {
ea76e635 4356 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4357 wake_up(&hw->msi_wait);
4358 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4359 }
4360 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4361
4362 return IRQ_HANDLED;
4363}
4364
4365/* Test interrupt path by forcing a a software IRQ */
4366static int __devinit sky2_test_msi(struct sky2_hw *hw)
4367{
4368 struct pci_dev *pdev = hw->pdev;
4369 int err;
4370
bb507fe1 4371 init_waitqueue_head (&hw->msi_wait);
4372
fb2690a9
SH		 4373 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4374
b0a20ded 4375 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4376 if (err) {
b02a9258 4377 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4378 return err;
4379 }
4380
fb2690a9 4381 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4382 sky2_read8(hw, B0_CTST);
fb2690a9 4383
ea76e635 4384 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4385
ea76e635 4386 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4387 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4388 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4389 "switching to INTx mode.\n");
fb2690a9
SH		 4390
4391 err = -EOPNOTSUPP;
4392 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4393 }
4394
4395 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4396 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4397
4398 free_irq(pdev->irq, hw);
4399
4400 return err;
4401}
4402
c7127a34
SH		 4403/* This driver supports yukon2 chipset only */
4404static const char *sky2_name(u8 chipid, char *buf, int sz)
4405{
4406 const char *name[] = {
4407 "XL", /* 0xb3 */
4408 "EC Ultra", /* 0xb4 */
4409 "Extreme", /* 0xb5 */
4410 "EC", /* 0xb6 */
4411 "FE", /* 0xb7 */
4412 "FE+", /* 0xb8 */
4413 "Supreme", /* 0xb9 */
0ce8b98d 4414 "UL 2", /* 0xba */
c7127a34
SH		 4415 };
4416
0ce8b98d 4417 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
c7127a34
SH		 4418 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4419 else
4420 snprintf(buf, sz, "(chip %#x)", chipid);
4421 return buf;
4422}
4423
cd28ab6a
SH		 4424static int __devinit sky2_probe(struct pci_dev *pdev,
4425 const struct pci_device_id *ent)
4426{
7f60c64b 4427 struct net_device *dev;
cd28ab6a 4428 struct sky2_hw *hw;
be63a21c 4429 int err, using_dac = 0, wol_default;
3834507d 4430 u32 reg;
c7127a34 4431 char buf1[16];
cd28ab6a 4432
793b883e
SH		 4433 err = pci_enable_device(pdev);
4434 if (err) {
b02a9258 4435 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4436 goto err_out;
4437 }
4438
6cc90a5a
SH		 4439 /* Get configuration information
4440 * Note: only regular PCI config access once to test for HW issues
4441 * other PCI access through shared memory for speed and to
4442 * avoid MMCONFIG problems.
4443 */
4444 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4445 if (err) {
4446 dev_err(&pdev->dev, "PCI read config failed\n");
4447 goto err_out;
4448 }
4449
4450 if (~reg == 0) {
4451 dev_err(&pdev->dev, "PCI configuration read error\n");
4452 goto err_out;
4453 }
4454
793b883e
SH		 4455 err = pci_request_regions(pdev, DRV_NAME);
4456 if (err) {
b02a9258 4457 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4458 goto err_out_disable;
cd28ab6a
SH		 4459 }
4460
4461 pci_set_master(pdev);
4462
d1f3d4dd 4463 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4464 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4465 using_dac = 1;
6a35528a 4466 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4467 if (err < 0) {
b02a9258
SH		 4468 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4469 "for consistent allocations\n");
d1f3d4dd
SH		 4470 goto err_out_free_regions;
4471 }
d1f3d4dd 4472 } else {
284901a9 4473 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4474 if (err) {
b02a9258 4475 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4476 goto err_out_free_regions;
4477 }
4478 }
d1f3d4dd 4479
3834507d
SH		 4480
4481#ifdef __BIG_ENDIAN
4482 /* The sk98lin vendor driver uses hardware byte swapping but
4483 * this driver uses software swapping.
4484 */
4485 reg &= ~PCI_REV_DESC;
4486 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4487 if (err) {
4488 dev_err(&pdev->dev, "PCI write config failed\n");
4489 goto err_out_free_regions;
4490 }
4491#endif
4492
9d731d77 4493 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4494
cd28ab6a 4495 err = -ENOMEM;
66466797
SH		 4496
4497 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4498 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
cd28ab6a 4499 if (!hw) {
b02a9258 4500 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4501 goto err_out_free_regions;
4502 }
4503
cd28ab6a 4504 hw->pdev = pdev;
66466797 4505 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
cd28ab6a
SH		 4506
4507 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4508 if (!hw->regs) {
b02a9258 4509 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4510 goto err_out_free_hw;
4511 }
4512
08c06d8a 4513 /* ring for status responses */
167f53d0 4514 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4515 if (!hw->st_le)
4516 goto err_out_iounmap;
4517
e3173832 4518 err = sky2_init(hw);
cd28ab6a 4519 if (err)
793b883e 4520 goto err_out_iounmap;
cd28ab6a 4521
c844d483
SH		 4522 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4523 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4524
e3173832
SH		 4525 sky2_reset(hw);
4526
be63a21c 4527 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4528 if (!dev) {
4529 err = -ENOMEM;
cd28ab6a 4530 goto err_out_free_pci;
7f60c64b 4531 }
cd28ab6a 4532
9fa1b1f3
SH		 4533 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4534 err = sky2_test_msi(hw);
4535 if (err == -EOPNOTSUPP)
4536 pci_disable_msi(pdev);
4537 else if (err)
4538 goto err_out_free_netdev;
4539 }
4540
793b883e
SH		 4541 err = register_netdev(dev);
4542 if (err) {
b02a9258 4543 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4544 goto err_out_free_netdev;
4545 }
4546
6de16237
SH		 4547 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4548
ea76e635
SH		 4549 err = request_irq(pdev->irq, sky2_intr,
4550 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
66466797 4551 hw->irq_name, hw);
9fa1b1f3 4552 if (err) {
b02a9258 4553 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4554 goto err_out_unregister;
4555 }
4556 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4557 napi_enable(&hw->napi);
9fa1b1f3 4558
cd28ab6a
SH		 4559 sky2_show_addr(dev);
4560
7f60c64b 4561 if (hw->ports > 1) {
4562 struct net_device *dev1;
4563
ca519274 4564 err = -ENOMEM;
be63a21c 4565 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
ca519274
SH		 4566 if (dev1 && (err = register_netdev(dev1)) == 0)
4567 sky2_show_addr(dev1);
4568 else {
b02a9258
SH		 4569 dev_warn(&pdev->dev,
4570 "register of second port failed (%d)\n", err);
cd28ab6a 4571 hw->dev[1] = NULL;
ca519274
SH		 4572 hw->ports = 1;
4573 if (dev1)
4574 free_netdev(dev1);
4575 }
cd28ab6a
SH		 4576 }
4577
32c2c300 4578 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4579 INIT_WORK(&hw->restart_work, sky2_restart);
4580
793b883e
SH		 4581 pci_set_drvdata(pdev, hw);
4582
cd28ab6a
SH		 4583 return 0;
4584
793b883e 4585err_out_unregister:
ea76e635 4586 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4587 pci_disable_msi(pdev);
793b883e 4588 unregister_netdev(dev);
cd28ab6a
SH		 4589err_out_free_netdev:
4590 free_netdev(dev);
cd28ab6a 4591err_out_free_pci:
793b883e 4592 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4593 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4594err_out_iounmap:
4595 iounmap(hw->regs);
4596err_out_free_hw:
4597 kfree(hw);
4598err_out_free_regions:
4599 pci_release_regions(pdev);
44a1d2e5 4600err_out_disable:
cd28ab6a 4601 pci_disable_device(pdev);
cd28ab6a 4602err_out:
549a68c3 4603 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4604 return err;
4605}
4606
4607static void __devexit sky2_remove(struct pci_dev *pdev)
4608{
793b883e 4609 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4610 int i;
cd28ab6a 4611
793b883e 4612 if (!hw)
cd28ab6a
SH		 4613 return;
4614
32c2c300 4615 del_timer_sync(&hw->watchdog_timer);
6de16237 4616 cancel_work_sync(&hw->restart_work);
d27ed387 4617
b877fe28 4618 for (i = hw->ports-1; i >= 0; --i)
6de16237 4619 unregister_netdev(hw->dev[i]);
81906791 4620
d27ed387 4621 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4622
ae306cca
SH		 4623 sky2_power_aux(hw);
4624
793b883e 4625 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4626 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4627
4628 free_irq(pdev->irq, hw);
ea76e635 4629 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4630 pci_disable_msi(pdev);
793b883e 4631 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4632 pci_release_regions(pdev);
4633 pci_disable_device(pdev);
793b883e 4634
b877fe28 4635 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4636 free_netdev(hw->dev[i]);
4637
cd28ab6a
SH		 4638 iounmap(hw->regs);
4639 kfree(hw);
5afa0a9c 4640
cd28ab6a
SH		 4641 pci_set_drvdata(pdev, NULL);
4642}
4643
4644#ifdef CONFIG_PM
4645static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4646{
793b883e 4647 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4648 int i, wol = 0;
cd28ab6a 4649
549a68c3
SH		 4650 if (!hw)
4651 return 0;
4652
063a0b38
SH		 4653 del_timer_sync(&hw->watchdog_timer);
4654 cancel_work_sync(&hw->restart_work);
4655
19720737 4656 rtnl_lock();
f05267e7 4657 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4658 struct net_device *dev = hw->dev[i];
e3173832 4659 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4660
af18d8b8 4661 sky2_detach(dev);
e3173832
SH		 4662
4663 if (sky2->wol)
4664 sky2_wol_init(sky2);
4665
4666 wol |= sky2->wol;
cd28ab6a
SH		 4667 }
4668
8ab8fca2 4669 sky2_write32(hw, B0_IMSK, 0);
6de16237 4670 napi_disable(&hw->napi);
ae306cca 4671 sky2_power_aux(hw);
19720737 4672 rtnl_unlock();
e3173832 4673
d374c1c1 4674 pci_save_state(pdev);
e3173832 4675 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4676 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4677
2ccc99b7 4678 return 0;
cd28ab6a
SH		 4679}
4680
4681static int sky2_resume(struct pci_dev *pdev)
4682{
793b883e 4683 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4684 int i, err;
cd28ab6a 4685
549a68c3
SH		 4686 if (!hw)
4687 return 0;
4688
f71eb1a2
SH		 4689 err = pci_set_power_state(pdev, PCI_D0);
4690 if (err)
4691 goto out;
ae306cca
SH		 4692
4693 err = pci_restore_state(pdev);
4694 if (err)
4695 goto out;
4696
cd28ab6a 4697 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4698
4699 /* Re-enable all clocks */
05745c4a
SH		 4700 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4701 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4702 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4703 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4704
e3173832 4705 sky2_reset(hw);
8ab8fca2 4706 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4707 napi_enable(&hw->napi);
8ab8fca2 4708
af18d8b8 4709 rtnl_lock();
f05267e7 4710 for (i = 0; i < hw->ports; i++) {
af18d8b8
SH		 4711 err = sky2_reattach(hw->dev[i]);
4712 if (err)
4713 goto out;
cd28ab6a 4714 }
af18d8b8 4715 rtnl_unlock();
eb35cf60 4716
ae306cca 4717 return 0;
08c06d8a 4718out:
af18d8b8
SH		 4719 rtnl_unlock();
4720
b02a9258 4721 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4722 pci_disable_device(pdev);
08c06d8a 4723 return err;
cd28ab6a
SH		 4724}
4725#endif
4726
e3173832
SH		 4727static void sky2_shutdown(struct pci_dev *pdev)
4728{
4729 struct sky2_hw *hw = pci_get_drvdata(pdev);
4730 int i, wol = 0;
4731
549a68c3
SH		 4732 if (!hw)
4733 return;
4734
19720737 4735 rtnl_lock();
5c0d6b34 4736 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4737
4738 for (i = 0; i < hw->ports; i++) {
4739 struct net_device *dev = hw->dev[i];
4740 struct sky2_port *sky2 = netdev_priv(dev);
4741
4742 if (sky2->wol) {
4743 wol = 1;
4744 sky2_wol_init(sky2);
4745 }
4746 }
4747
4748 if (wol)
4749 sky2_power_aux(hw);
19720737 4750 rtnl_unlock();
e3173832
SH		 4751
4752 pci_enable_wake(pdev, PCI_D3hot, wol);
4753 pci_enable_wake(pdev, PCI_D3cold, wol);
4754
4755 pci_disable_device(pdev);
f71eb1a2 4756 pci_set_power_state(pdev, PCI_D3hot);
e3173832
SH		 4757}
4758
cd28ab6a 4759static struct pci_driver sky2_driver = {
793b883e
SH		 4760 .name = DRV_NAME,
4761 .id_table = sky2_id_table,
4762 .probe = sky2_probe,
4763 .remove = __devexit_p(sky2_remove),
cd28ab6a 4764#ifdef CONFIG_PM
793b883e
SH		 4765 .suspend = sky2_suspend,
4766 .resume = sky2_resume,
cd28ab6a 4767#endif
e3173832 4768 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4769};
4770
4771static int __init sky2_init_module(void)
4772{
c844d483
SH		 4773 pr_info(PFX "driver version " DRV_VERSION "\n");
4774
3cf26753 4775 sky2_debug_init();
50241c4c 4776 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4777}
4778
4779static void __exit sky2_cleanup_module(void)
4780{
4781 pci_unregister_driver(&sky2_driver);
3cf26753 4782 sky2_debug_cleanup();
cd28ab6a
SH		 4783}
4784
4785module_init(sky2_init_module);
4786module_exit(sky2_cleanup_module);
4787
4788MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4789MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4790MODULE_LICENSE("GPL");
5f4f9dc1 4791MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
This page took 1.263508 seconds and 5 git commands to generate.