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[WIRELESS] radiotap parser: accept all other fields
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
3cf26753 42#include <linux/debugfs.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
faf60e72 54#define DRV_VERSION "1.18"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 67#define RX_SKB_ALIGN 8
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
cd28ab6a 102static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
e5b74c7d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
cd28ab6a
SH		 136 { 0 }
137};
793b883e 138
cd28ab6a
SH		 139MODULE_DEVICE_TABLE(pci, sky2_id_table);
140
141/* Avoid conditionals by using array */
142static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
143static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 144static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 145
92f965e8
SH		 146/* This driver supports yukon2 chipset only */
147static const char *yukon2_name[] = {
148 "XL", /* 0xb3 */
149 "EC Ultra", /* 0xb4 */
93745494 150 "Extreme", /* 0xb5 */
92f965e8
SH		 151 "EC", /* 0xb6 */
152 "FE", /* 0xb7 */
05745c4a 153 "FE+", /* 0xb8 */
793b883e
SH		 154};
155
d1b139c0
SH		 156static void sky2_set_multicast(struct net_device *dev);
157
793b883e 158/* Access to external PHY */
ef743d33 159static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 160{
161 int i;
162
163 gma_write16(hw, port, GM_SMI_DATA, val);
164 gma_write16(hw, port, GM_SMI_CTRL,
165 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
166
167 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 168 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 169 return 0;
793b883e 170 udelay(1);
cd28ab6a 171 }
ef743d33 172
793b883e 173 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 174 return -ETIMEDOUT;
cd28ab6a
SH		 175}
176
ef743d33 177static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 178{
179 int i;
180
793b883e 181 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 182 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
183
184 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33 185 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
186 *val = gma_read16(hw, port, GM_SMI_DATA);
187 return 0;
188 }
189
793b883e 190 udelay(1);
cd28ab6a
SH		 191 }
192
ef743d33 193 return -ETIMEDOUT;
194}
195
196static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
197{
198 u16 v;
199
200 if (__gm_phy_read(hw, port, reg, &v) != 0)
201 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
202 return v;
cd28ab6a
SH		 203}
204
5afa0a9c 205
ae306cca
SH		 206static void sky2_power_on(struct sky2_hw *hw)
207{
208 /* switch power to VCC (WA for VAUX problem) */
209 sky2_write8(hw, B0_POWER_CTRL,
210 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 211
ae306cca
SH		 212 /* disable Core Clock Division, */
213 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 214
ae306cca
SH		 215 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
216 /* enable bits are inverted */
217 sky2_write8(hw, B2_Y2_CLK_GATE,
218 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
219 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
220 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
221 else
222 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 223
ea76e635 224 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 225 u32 reg;
5afa0a9c 226
b2345773
SH		 227 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
228
fc99fe06
SH		 229 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
230 /* set all bits to 0 except bits 15..12 and 8 */
231 reg &= P_ASPM_CONTROL_MSK;
232 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
233
234 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
235 /* set all bits to 0 except bits 28 & 27 */
236 reg &= P_CTL_TIM_VMAIN_AV_MSK;
237 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
238
239 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 240
241 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
242 reg = sky2_read32(hw, B2_GP_IO);
243 reg |= GLB_GPIO_STAT_RACE_DIS;
244 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 245
246 sky2_read32(hw, B2_GP_IO);
5afa0a9c 247 }
ae306cca 248}
5afa0a9c 249
ae306cca
SH		 250static void sky2_power_aux(struct sky2_hw *hw)
251{
252 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
253 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
254 else
255 /* enable bits are inverted */
256 sky2_write8(hw, B2_Y2_CLK_GATE,
257 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
258 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
259 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
260
261 /* switch power to VAUX */
262 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
263 sky2_write8(hw, B0_POWER_CTRL,
264 (PC_VAUX_ENA | PC_VCC_ENA |
265 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c 266}
267
d3bcfbeb 268static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 269{
270 u16 reg;
271
272 /* disable all GMAC IRQ's */
273 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
274 /* disable PHY IRQs */
275 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 276
cd28ab6a
SH		 277 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
278 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
279 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
280 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
281
282 reg = gma_read16(hw, port, GM_RX_CTRL);
283 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
284 gma_write16(hw, port, GM_RX_CTRL, reg);
285}
286
16ad91e1
SH		 287/* flow control to advertise bits */
288static const u16 copper_fc_adv[] = {
289 [FC_NONE] = 0,
290 [FC_TX] = PHY_M_AN_ASP,
291 [FC_RX] = PHY_M_AN_PC,
292 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
293};
294
295/* flow control to advertise bits when using 1000BaseX */
296static const u16 fiber_fc_adv[] = {
297 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
298 [FC_TX] = PHY_M_P_ASYM_MD_X,
299 [FC_RX] = PHY_M_P_SYM_MD_X,
300 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
301};
302
303/* flow control to GMA disable bits */
304static const u16 gm_fc_disable[] = {
305 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
306 [FC_TX] = GM_GPCR_FC_RX_DIS,
307 [FC_RX] = GM_GPCR_FC_TX_DIS,
308 [FC_BOTH] = 0,
309};
310
311
cd28ab6a
SH		 312static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
313{
314 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 315 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 316
ea76e635
SH		 317 if (sky2->autoneg == AUTONEG_ENABLE &&
318 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 319 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
320
321 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 322 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 323 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
324
53419c68 325 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 326 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 327 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 328 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
329 else
53419c68
SH		 330 /* set master & slave downshift counter to 1x */
331 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 332
333 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
334 }
335
336 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 337 if (sky2_is_copper(hw)) {
05745c4a 338 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 339 /* enable automatic crossover */
340 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 341
342 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
343 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
344 u16 spec;
345
346 /* Enable Class A driver for FE+ A0 */
347 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
348 spec |= PHY_M_FESC_SEL_CL_A;
349 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
350 }
cd28ab6a
SH		 351 } else {
352 /* disable energy detect */
353 ctrl &= ~PHY_M_PC_EN_DET_MSK;
354
355 /* enable automatic crossover */
356 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
357
53419c68 358 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 359 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 360 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 361 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 362 ctrl &= ~PHY_M_PC_DSC_MSK;
363 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
364 }
365 }
cd28ab6a
SH		 366 } else {
367 /* workaround for deviation #4.88 (CRC errors) */
368 /* disable Automatic Crossover */
369
370 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 371 }
cd28ab6a 372
b89165f2
SH		 373 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
374
375 /* special setup for PHY 88E1112 Fiber */
ea76e635 376 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 377 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 378
b89165f2
SH		 379 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
380 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
381 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
382 ctrl &= ~PHY_M_MAC_MD_MSK;
383 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
384 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
385
386 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 387 /* select page 1 to access Fiber registers */
388 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 389
390 /* for SFP-module set SIGDET polarity to low */
391 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
392 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 393 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 394 }
b89165f2
SH		 395
396 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 397 }
398
7800fddc 399 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 400 ct1000 = 0;
401 adv = PHY_AN_CSMA;
2eaba1a2 402 reg = 0;
cd28ab6a
SH		 403
404 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 405 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 406 if (sky2->advertising & ADVERTISED_1000baseT_Full)
407 ct1000 |= PHY_M_1000C_AFD;
408 if (sky2->advertising & ADVERTISED_1000baseT_Half)
409 ct1000 |= PHY_M_1000C_AHD;
410 if (sky2->advertising & ADVERTISED_100baseT_Full)
411 adv |= PHY_M_AN_100_FD;
412 if (sky2->advertising & ADVERTISED_100baseT_Half)
413 adv |= PHY_M_AN_100_HD;
414 if (sky2->advertising & ADVERTISED_10baseT_Full)
415 adv |= PHY_M_AN_10_FD;
416 if (sky2->advertising & ADVERTISED_10baseT_Half)
417 adv |= PHY_M_AN_10_HD;
709c6e7b 418
16ad91e1 419 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 420 } else { /* special defines for FIBER (88E1040S only) */
421 if (sky2->advertising & ADVERTISED_1000baseT_Full)
422 adv |= PHY_M_AN_1000X_AFD;
423 if (sky2->advertising & ADVERTISED_1000baseT_Half)
424 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 425
16ad91e1 426 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 427 }
cd28ab6a
SH		 428
429 /* Restart Auto-negotiation */
430 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
431 } else {
432 /* forced speed/duplex settings */
433 ct1000 = PHY_M_1000C_MSE;
434
2eaba1a2
SH		 435 /* Disable auto update for duplex flow control and speed */
436 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 437
438 switch (sky2->speed) {
439 case SPEED_1000:
440 ctrl |= PHY_CT_SP1000;
2eaba1a2 441 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 442 break;
443 case SPEED_100:
444 ctrl |= PHY_CT_SP100;
2eaba1a2 445 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 446 break;
447 }
448
2eaba1a2
SH		 449 if (sky2->duplex == DUPLEX_FULL) {
450 reg |= GM_GPCR_DUP_FULL;
451 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 452 } else if (sky2->speed < SPEED_1000)
453 sky2->flow_mode = FC_NONE;
2eaba1a2 454
2eaba1a2 455
16ad91e1 456 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 457
458 /* Forward pause packets to GMAC? */
16ad91e1 459 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 460 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
461 else
462 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 463 }
464
2eaba1a2
SH		 465 gma_write16(hw, port, GM_GP_CTRL, reg);
466
05745c4a 467 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 468 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
469
470 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
471 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
472
473 /* Setup Phy LED's */
474 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
475 ledover = 0;
476
477 switch (hw->chip_id) {
478 case CHIP_ID_YUKON_FE:
479 /* on 88E3082 these bits are at 11..9 (shifted left) */
480 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
481
482 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
483
484 /* delete ACT LED control bits */
485 ctrl &= ~PHY_M_FELP_LED1_MSK;
486 /* change ACT LED control to blink mode */
487 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
488 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
489 break;
490
05745c4a
SH		 491 case CHIP_ID_YUKON_FE_P:
492 /* Enable Link Partner Next Page */
493 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
494 ctrl |= PHY_M_PC_ENA_LIP_NP;
495
496 /* disable Energy Detect and enable scrambler */
497 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
498 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
499
500 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
501 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
502 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
503 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
504
505 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
506 break;
507
cd28ab6a 508 case CHIP_ID_YUKON_XL:
793b883e 509 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 510
511 /* select page 3 to access LED control register */
512 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
513
514 /* set LED Function Control register */
ed6d32c7
SH		 515 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
516 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
517 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
518 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
519 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 520
521 /* set Polarity Control register */
522 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 523 (PHY_M_POLC_LS1_P_MIX(4) |
524 PHY_M_POLC_IS0_P_MIX(4) |
525 PHY_M_POLC_LOS_CTRL(2) |
526 PHY_M_POLC_INIT_CTRL(2) |
527 PHY_M_POLC_STA1_CTRL(2) |
528 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 529
530 /* restore page register */
793b883e 531 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 532 break;
93745494 533
ed6d32c7 534 case CHIP_ID_YUKON_EC_U:
93745494 535 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 536 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
537
538 /* select page 3 to access LED control register */
539 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
540
541 /* set LED Function Control register */
542 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
543 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
544 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
545 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
546 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
547
548 /* set Blink Rate in LED Timer Control Register */
549 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
550 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
551 /* restore page register */
552 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
553 break;
cd28ab6a
SH		 554
555 default:
556 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
557 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
558 /* turn off the Rx LED (LED_RX) */
0efdf262 559 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 560 }
561
9467a8fc
SH		 562 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
563 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 564 /* apply fixes in PHY AFE */
ed6d32c7
SH		 565 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
566
977bdf06 567 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 568 gm_phy_write(hw, port, 0x18, 0xaa99);
569 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 570
977bdf06 571 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 572 gm_phy_write(hw, port, 0x18, 0xa204);
573 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 574
575 /* set page register to 0 */
9467a8fc 576 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 577 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
578 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
579 /* apply workaround for integrated resistors calibration */
580 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
581 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
93745494 582 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
05745c4a 583 /* no effect on Yukon-XL */
977bdf06 584 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 585
977bdf06
SH		 586 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
587 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 588 ledover |= PHY_M_LED_MO_100;
977bdf06 589 }
cd28ab6a 590
977bdf06
SH		 591 if (ledover)
592 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
593
594 }
2eaba1a2 595
d571b694 596 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 597 if (sky2->autoneg == AUTONEG_ENABLE)
598 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
599 else
600 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
601}
602
d3bcfbeb 603static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
604{
605 u32 reg1;
606 static const u32 phy_power[]
607 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
608
609 /* looks like this XL is back asswards .. */
610 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
611 onoff = !onoff;
612
aed2cec4 613 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 614 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb 615 if (onoff)
616 /* Turn off phy power saving */
617 reg1 &= ~phy_power[port];
618 else
619 reg1 |= phy_power[port];
620
621 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 622 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 623 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb 624 udelay(100);
625}
626
1b537565
SH		 627/* Force a renegotiation */
628static void sky2_phy_reinit(struct sky2_port *sky2)
629{
e07b1aa8 630 spin_lock_bh(&sky2->phy_lock);
1b537565 631 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 632 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 633}
634
e3173832
SH		 635/* Put device in state to listen for Wake On Lan */
636static void sky2_wol_init(struct sky2_port *sky2)
637{
638 struct sky2_hw *hw = sky2->hw;
639 unsigned port = sky2->port;
640 enum flow_control save_mode;
641 u16 ctrl;
642 u32 reg1;
643
644 /* Bring hardware out of reset */
645 sky2_write16(hw, B0_CTST, CS_RST_CLR);
646 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
647
648 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
649 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
650
651 /* Force to 10/100
652 * sky2_reset will re-enable on resume
653 */
654 save_mode = sky2->flow_mode;
655 ctrl = sky2->advertising;
656
657 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
658 sky2->flow_mode = FC_NONE;
659 sky2_phy_power(hw, port, 1);
660 sky2_phy_reinit(sky2);
661
662 sky2->flow_mode = save_mode;
663 sky2->advertising = ctrl;
664
665 /* Set GMAC to no flow control and auto update for speed/duplex */
666 gma_write16(hw, port, GM_GP_CTRL,
667 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
668 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
669
670 /* Set WOL address */
671 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
672 sky2->netdev->dev_addr, ETH_ALEN);
673
674 /* Turn on appropriate WOL control bits */
675 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
676 ctrl = 0;
677 if (sky2->wol & WAKE_PHY)
678 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
679 else
680 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
681
682 if (sky2->wol & WAKE_MAGIC)
683 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
684 else
685 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
686
687 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
688 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
689
690 /* Turn on legacy PCI-Express PME mode */
691 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
692 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
693 reg1 |= PCI_Y2_PME_LEGACY;
694 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
695 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
696
697 /* block receiver */
698 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
699
700}
701
69161611
SH		 702static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
703{
05745c4a
SH		 704 struct net_device *dev = hw->dev[port];
705
706 if (dev->mtu <= ETH_DATA_LEN)
69161611 707 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
05745c4a
SH		 708 TX_JUMBO_DIS | TX_STFW_ENA);
709
710 else if (hw->chip_id != CHIP_ID_YUKON_EC_U)
711 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
712 TX_STFW_ENA | TX_JUMBO_ENA);
713 else {
714 /* set Tx GMAC FIFO Almost Empty Threshold */
715 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
716 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 717
05745c4a
SH		 718 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
719 TX_JUMBO_ENA | TX_STFW_DIS);
69161611 720
05745c4a
SH		 721 /* Can't do offload because of lack of store/forward */
722 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
69161611
SH		 723 }
724}
725
cd28ab6a
SH		 726static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
727{
728 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
729 u16 reg;
25cccecc 730 u32 rx_reg;
cd28ab6a
SH		 731 int i;
732 const u8 *addr = hw->dev[port]->dev_addr;
733
f350339c
SH		 734 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
735 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 736
737 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
738
793b883e 739 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 740 /* WA DEV_472 -- looks like crossed wires on port 2 */
741 /* clear GMAC 1 Control reset */
742 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
743 do {
744 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
745 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
746 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
747 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
748 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
749 }
750
793b883e 751 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 752
2eaba1a2
SH		 753 /* Enable Transmit FIFO Underrun */
754 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
755
e07b1aa8 756 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 757 sky2_phy_init(hw, port);
e07b1aa8 758 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 759
760 /* MIB clear */
761 reg = gma_read16(hw, port, GM_PHY_ADDR);
762 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
763
43f2f104
SH		 764 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
765 gma_read16(hw, port, i);
cd28ab6a
SH		 766 gma_write16(hw, port, GM_PHY_ADDR, reg);
767
768 /* transmit control */
769 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
770
771 /* receive control reg: unicast + multicast + no FCS */
772 gma_write16(hw, port, GM_RX_CTRL,
793b883e 773 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 774
775 /* transmit flow control */
776 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
777
778 /* transmit parameter */
779 gma_write16(hw, port, GM_TX_PARAM,
780 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
781 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
782 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
783 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
784
785 /* serial mode register */
786 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 787 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 788
6b1a3aef 789 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 790 reg |= GM_SMOD_JUMBO_ENA;
791
792 gma_write16(hw, port, GM_SERIAL_MODE, reg);
793
cd28ab6a
SH		 794 /* virtual address for data */
795 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
796
793b883e
SH		 797 /* physical address: used for pause frames */
798 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
799
800 /* ignore counter overflows */
cd28ab6a
SH		 801 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
802 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
803 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
804
805 /* Configure Rx MAC FIFO */
806 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 807 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 808 if (hw->chip_id == CHIP_ID_YUKON_EX ||
809 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 810 rx_reg |= GMF_RX_OVER_ON;
69161611 811
25cccecc 812 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 813
d571b694 814 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 815 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 816
8df9a876 817 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 818 reg = RX_GMF_FL_THR_DEF + 1;
819 /* Another magic mystery workaround from sk98lin */
820 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
821 hw->chip_rev == CHIP_REV_YU_FE2_A0)
822 reg = 0x178;
823 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 824
825 /* Configure Tx MAC FIFO */
826 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
827 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 828
e0c28116
SH		 829 /* On chips without ram buffer, pause is controled by MAC level */
830 if (sky2_read8(hw, B2_E_0) == 0) {
8df9a876 831 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 832 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 833
69161611 834 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 835 }
836
cd28ab6a
SH		 837}
838
67712901
SH		 839/* Assign Ram Buffer allocation to queue */
840static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 841{
67712901
SH		 842 u32 end;
843
844 /* convert from K bytes to qwords used for hw register */
845 start *= 1024/8;
846 space *= 1024/8;
847 end = start + space - 1;
793b883e 848
cd28ab6a
SH		 849 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
850 sky2_write32(hw, RB_ADDR(q, RB_START), start);
851 sky2_write32(hw, RB_ADDR(q, RB_END), end);
852 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
853 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
854
855 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 856 u32 tp = space - space/4;
793b883e 857
1c28f6ba
SH		 858 /* On receive queue's set the thresholds
859 * give receiver priority when > 3/4 full
860 * send pause when down to 2K
861 */
862 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
863 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 864
1c28f6ba
SH		 865 tp = space - 2048/8;
866 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
867 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 868 } else {
869 /* Enable store & forward on Tx queue's because
870 * Tx FIFO is only 1K on Yukon
871 */
872 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
873 }
874
875 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 876 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 877}
878
cd28ab6a 879/* Setup Bus Memory Interface */
af4ed7e6 880static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 881{
882 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
883 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
884 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 885 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 886}
887
cd28ab6a
SH		 888/* Setup prefetch unit registers. This is the interface between
889 * hardware and driver list elements
890 */
8cc048e3 891static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 892 u64 addr, u32 last)
893{
cd28ab6a
SH		 894 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
895 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
896 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
897 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
898 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
899 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 900
901 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 902}
903
793b883e
SH		 904static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
905{
906 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
907
cb5d9547 908 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 909 le->ctrl = 0;
793b883e
SH		 910 return le;
911}
cd28ab6a 912
88f5f0ca
SH		 913static void tx_init(struct sky2_port *sky2)
914{
915 struct sky2_tx_le *le;
916
917 sky2->tx_prod = sky2->tx_cons = 0;
918 sky2->tx_tcpsum = 0;
919 sky2->tx_last_mss = 0;
920
921 le = get_tx_le(sky2);
922 le->addr = 0;
923 le->opcode = OP_ADDR64 | HW_OWNER;
924 sky2->tx_addr64 = 0;
925}
926
291ea614
SH		 927static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
928 struct sky2_tx_le *le)
929{
930 return sky2->tx_ring + (le - sky2->tx_le);
931}
932
290d4de5
SH		 933/* Update chip's next pointer */
934static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 935{
50432cb5 936 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 937 wmb();
50432cb5
SH		 938 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
939
940 /* Synchronize I/O on since next processor may write to tail */
941 mmiowb();
cd28ab6a
SH		 942}
943
793b883e 944
cd28ab6a
SH		 945static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
946{
947 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 948 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 949 le->ctrl = 0;
cd28ab6a
SH		 950 return le;
951}
952
14d0263f
SH		 953/* Build description to hardware for one receive segment */
954static void sky2_rx_add(struct sky2_port *sky2, u8 op,
955 dma_addr_t map, unsigned len)
cd28ab6a
SH		 956{
957 struct sky2_rx_le *le;
36eb0c71 958 u32 hi = upper_32_bits(map);
cd28ab6a 959
793b883e 960 if (sky2->rx_addr64 != hi) {
cd28ab6a 961 le = sky2_next_rx(sky2);
793b883e 962 le->addr = cpu_to_le32(hi);
cd28ab6a 963 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 964 sky2->rx_addr64 = upper_32_bits(map + len);
cd28ab6a 965 }
793b883e 966
cd28ab6a 967 le = sky2_next_rx(sky2);
734d1868
SH		 968 le->addr = cpu_to_le32((u32) map);
969 le->length = cpu_to_le16(len);
14d0263f 970 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 971}
972
14d0263f
SH		 973/* Build description to hardware for one possibly fragmented skb */
974static void sky2_rx_submit(struct sky2_port *sky2,
975 const struct rx_ring_info *re)
976{
977 int i;
978
979 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
980
981 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
982 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
983}
984
985
986static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
987 unsigned size)
988{
989 struct sk_buff *skb = re->skb;
990 int i;
991
992 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
993 pci_unmap_len_set(re, data_size, size);
994
995 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
996 re->frag_addr[i] = pci_map_page(pdev,
997 skb_shinfo(skb)->frags[i].page,
998 skb_shinfo(skb)->frags[i].page_offset,
999 skb_shinfo(skb)->frags[i].size,
1000 PCI_DMA_FROMDEVICE);
1001}
1002
1003static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1004{
1005 struct sk_buff *skb = re->skb;
1006 int i;
1007
1008 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1009 PCI_DMA_FROMDEVICE);
1010
1011 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1012 pci_unmap_page(pdev, re->frag_addr[i],
1013 skb_shinfo(skb)->frags[i].size,
1014 PCI_DMA_FROMDEVICE);
1015}
793b883e 1016
cd28ab6a
SH		 1017/* Tell chip where to start receive checksum.
1018 * Actually has two checksums, but set both same to avoid possible byte
1019 * order problems.
1020 */
793b883e 1021static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1022{
ea76e635 1023 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1024
ea76e635
SH		 1025 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1026 le->ctrl = 0;
1027 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1028
ea76e635
SH		 1029 sky2_write32(sky2->hw,
1030 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1031 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1032}
1033
6b1a3aef 1034/*
1035 * The RX Stop command will not work for Yukon-2 if the BMU does not
1036 * reach the end of packet and since we can't make sure that we have
1037 * incoming data, we must reset the BMU while it is not doing a DMA
1038 * transfer. Since it is possible that the RX path is still active,
1039 * the RX RAM buffer will be stopped first, so any possible incoming
1040 * data will not trigger a DMA. After the RAM buffer is stopped, the
1041 * BMU is polled until any DMA in progress is ended and only then it
1042 * will be reset.
1043 */
1044static void sky2_rx_stop(struct sky2_port *sky2)
1045{
1046 struct sky2_hw *hw = sky2->hw;
1047 unsigned rxq = rxqaddr[sky2->port];
1048 int i;
1049
1050 /* disable the RAM Buffer receive queue */
1051 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1052
1053 for (i = 0; i < 0xffff; i++)
1054 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1055 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1056 goto stopped;
1057
1058 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1059 sky2->netdev->name);
1060stopped:
1061 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1062
1063 /* reset the Rx prefetch unit */
1064 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1065 mmiowb();
6b1a3aef 1066}
793b883e 1067
d571b694 1068/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1069static void sky2_rx_clean(struct sky2_port *sky2)
1070{
1071 unsigned i;
1072
1073 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1074 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1075 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1076
1077 if (re->skb) {
14d0263f 1078 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1079 kfree_skb(re->skb);
1080 re->skb = NULL;
1081 }
1082 }
1083}
1084
ef743d33 1085/* Basic MII support */
1086static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1087{
1088 struct mii_ioctl_data *data = if_mii(ifr);
1089 struct sky2_port *sky2 = netdev_priv(dev);
1090 struct sky2_hw *hw = sky2->hw;
1091 int err = -EOPNOTSUPP;
1092
1093 if (!netif_running(dev))
1094 return -ENODEV; /* Phy still in reset */
1095
d89e1343 1096 switch (cmd) {
ef743d33 1097 case SIOCGMIIPHY:
1098 data->phy_id = PHY_ADDR_MARV;
1099
1100 /* fallthru */
1101 case SIOCGMIIREG: {
1102 u16 val = 0;
91c86df5 1103
e07b1aa8 1104 spin_lock_bh(&sky2->phy_lock);
ef743d33 1105 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1106 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1107
ef743d33 1108 data->val_out = val;
1109 break;
1110 }
1111
1112 case SIOCSMIIREG:
1113 if (!capable(CAP_NET_ADMIN))
1114 return -EPERM;
1115
e07b1aa8 1116 spin_lock_bh(&sky2->phy_lock);
ef743d33 1117 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1118 data->val_in);
e07b1aa8 1119 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1120 break;
1121 }
1122 return err;
1123}
1124
d1f13708 1125#ifdef SKY2_VLAN_TAG_USED
1126static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1127{
1128 struct sky2_port *sky2 = netdev_priv(dev);
1129 struct sky2_hw *hw = sky2->hw;
1130 u16 port = sky2->port;
d1f13708 1131
2bb8c262 1132 netif_tx_lock_bh(dev);
3d4e66f5 1133 netif_poll_disable(sky2->hw->dev[0]);
d1f13708 1134
d1f13708 1135 sky2->vlgrp = grp;
3d4e66f5
SH		 1136 if (grp) {
1137 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1138 RX_VLAN_STRIP_ON);
1139 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1140 TX_VLAN_TAG_ON);
1141 } else {
1142 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1143 RX_VLAN_STRIP_OFF);
1144 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1145 TX_VLAN_TAG_OFF);
1146 }
d1f13708 1147
3d4e66f5 1148 netif_poll_enable(sky2->hw->dev[0]);
2bb8c262 1149 netif_tx_unlock_bh(dev);
d1f13708 1150}
1151#endif
1152
82788c7a 1153/*
14d0263f
SH		 1154 * Allocate an skb for receiving. If the MTU is large enough
1155 * make the skb non-linear with a fragment list of pages.
1156 *
82788c7a
SH		 1157 * It appears the hardware has a bug in the FIFO logic that
1158 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86 1159 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1160 * aligned except if slab debugging is enabled.
82788c7a 1161 */
14d0263f 1162static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1163{
1164 struct sk_buff *skb;
14d0263f
SH		 1165 unsigned long p;
1166 int i;
82788c7a 1167
14d0263f
SH		 1168 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1169 if (!skb)
1170 goto nomem;
1171
1172 p = (unsigned long) skb->data;
1173 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1174
1175 for (i = 0; i < sky2->rx_nfrags; i++) {
1176 struct page *page = alloc_page(GFP_ATOMIC);
1177
1178 if (!page)
1179 goto free_partial;
1180 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1181 }
1182
1183 return skb;
14d0263f
SH		 1184free_partial:
1185 kfree_skb(skb);
1186nomem:
1187 return NULL;
82788c7a
SH		 1188}
1189
55c9dd35
SH		 1190static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1191{
1192 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1193}
1194
cd28ab6a
SH		 1195/*
1196 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1197 * Normal case this ends up creating one list element for skb
1198 * in the receive ring. Worst case if using large MTU and each
1199 * allocation falls on a different 64 bit region, that results
1200 * in 6 list elements per ring entry.
1201 * One element is used for checksum enable/disable, and one
1202 * extra to avoid wrap.
cd28ab6a 1203 */
6b1a3aef 1204static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1205{
6b1a3aef 1206 struct sky2_hw *hw = sky2->hw;
14d0263f 1207 struct rx_ring_info *re;
6b1a3aef 1208 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1209 unsigned i, size, space, thresh;
cd28ab6a 1210
6b1a3aef 1211 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1212 sky2_qset(hw, rxq);
977bdf06 1213
c3905bc4
SH		 1214 /* On PCI express lowering the watermark gives better performance */
1215 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1216 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1217
1218 /* These chips have no ram buffer?
1219 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1220 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1221 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1222 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1223 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1224
6b1a3aef 1225 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1226
ea76e635
SH		 1227 if (!(hw->flags & SKY2_HW_NEW_LE))
1228 rx_set_checksum(sky2);
14d0263f
SH		 1229
1230 /* Space needed for frame data + headers rounded up */
f957da2a 1231 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1232
1233 /* Stopping point for hardware truncation */
1234 thresh = (size - 8) / sizeof(u32);
1235
1236 /* Account for overhead of skb - to avoid order > 0 allocation */
1237 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1238 + sizeof(struct skb_shared_info);
1239
1240 sky2->rx_nfrags = space >> PAGE_SHIFT;
1241 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1242
1243 if (sky2->rx_nfrags != 0) {
1244 /* Compute residue after pages */
1245 space = sky2->rx_nfrags << PAGE_SHIFT;
1246
1247 if (space < size)
1248 size -= space;
1249 else
1250 size = 0;
1251
1252 /* Optimize to handle small packets and headers */
1253 if (size < copybreak)
1254 size = copybreak;
1255 if (size < ETH_HLEN)
1256 size = ETH_HLEN;
1257 }
1258 sky2->rx_data_size = size;
1259
1260 /* Fill Rx ring */
793b883e 1261 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1262 re = sky2->rx_ring + i;
cd28ab6a 1263
14d0263f 1264 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1265 if (!re->skb)
1266 goto nomem;
1267
14d0263f
SH		 1268 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1269 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1270 }
1271
a1433ac4
SH		 1272 /*
1273 * The receiver hangs if it receives frames larger than the
1274 * packet buffer. As a workaround, truncate oversize frames, but
1275 * the register is limited to 9 bits, so if you do frames > 2052
1276 * you better get the MTU right!
1277 */
a1433ac4
SH		 1278 if (thresh > 0x1ff)
1279 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1280 else {
1281 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1282 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1283 }
1284
6b1a3aef 1285 /* Tell chip about available buffers */
55c9dd35 1286 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1287 return 0;
1288nomem:
1289 sky2_rx_clean(sky2);
1290 return -ENOMEM;
1291}
1292
1293/* Bring up network interface. */
1294static int sky2_up(struct net_device *dev)
1295{
1296 struct sky2_port *sky2 = netdev_priv(dev);
1297 struct sky2_hw *hw = sky2->hw;
1298 unsigned port = sky2->port;
e0c28116 1299 u32 imask, ramsize;
ee7abb04 1300 int cap, err = -ENOMEM;
843a46f4 1301 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1302
ee7abb04
SH		 1303 /*
1304 * On dual port PCI-X card, there is an problem where status
1305 * can be received out of order due to split transactions
843a46f4 1306 */
ee7abb04
SH		 1307 if (otherdev && netif_running(otherdev) &&
1308 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1309 struct sky2_port *osky2 = netdev_priv(otherdev);
1310 u16 cmd;
1311
1312 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1313 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1314 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1315
1316 sky2->rx_csum = 0;
1317 osky2->rx_csum = 0;
1318 }
843a46f4 1319
cd28ab6a
SH		 1320 if (netif_msg_ifup(sky2))
1321 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1322
55d7b4e6
SH		 1323 netif_carrier_off(dev);
1324
cd28ab6a
SH		 1325 /* must be power of 2 */
1326 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1327 TX_RING_SIZE *
1328 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1329 &sky2->tx_le_map);
1330 if (!sky2->tx_le)
1331 goto err_out;
1332
6cdbbdf3 1333 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1334 GFP_KERNEL);
1335 if (!sky2->tx_ring)
1336 goto err_out;
88f5f0ca
SH		 1337
1338 tx_init(sky2);
cd28ab6a
SH		 1339
1340 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1341 &sky2->rx_le_map);
1342 if (!sky2->rx_le)
1343 goto err_out;
1344 memset(sky2->rx_le, 0, RX_LE_BYTES);
1345
291ea614 1346 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1347 GFP_KERNEL);
1348 if (!sky2->rx_ring)
1349 goto err_out;
1350
d3bcfbeb 1351 sky2_phy_power(hw, port, 1);
1352
cd28ab6a
SH		 1353 sky2_mac_init(hw, port);
1354
e0c28116
SH		 1355 /* Register is number of 4K blocks on internal RAM buffer. */
1356 ramsize = sky2_read8(hw, B2_E_0) * 4;
1357 if (ramsize > 0) {
67712901 1358 u32 rxspace;
cd28ab6a 1359
e0c28116 1360 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1361 if (ramsize < 16)
1362 rxspace = ramsize / 2;
1363 else
1364 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1365
67712901
SH		 1366 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1367 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1368
1369 /* Make sure SyncQ is disabled */
1370 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1371 RB_RST_SET);
1372 }
793b883e 1373
af4ed7e6 1374 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1375
69161611
SH		 1376 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1377 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1378 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1379
977bdf06 1380 /* Set almost empty threshold */
c2716fb4
SH		 1381 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1382 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1383 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1384
6b1a3aef 1385 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1386 TX_RING_SIZE - 1);
cd28ab6a 1387
6b1a3aef 1388 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1389 if (err)
1390 goto err_out;
1391
cd28ab6a 1392 /* Enable interrupts from phy/mac for port */
e07b1aa8 1393 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1394 imask |= portirq_msk[port];
e07b1aa8
SH		 1395 sky2_write32(hw, B0_IMSK, imask);
1396
cd28ab6a
SH		 1397 return 0;
1398
1399err_out:
1b537565 1400 if (sky2->rx_le) {
cd28ab6a
SH		 1401 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1402 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1403 sky2->rx_le = NULL;
1404 }
1405 if (sky2->tx_le) {
cd28ab6a
SH		 1406 pci_free_consistent(hw->pdev,
1407 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1408 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1409 sky2->tx_le = NULL;
1410 }
1411 kfree(sky2->tx_ring);
1412 kfree(sky2->rx_ring);
cd28ab6a 1413
1b537565
SH		 1414 sky2->tx_ring = NULL;
1415 sky2->rx_ring = NULL;
cd28ab6a
SH		 1416 return err;
1417}
1418
793b883e
SH		 1419/* Modular subtraction in ring */
1420static inline int tx_dist(unsigned tail, unsigned head)
1421{
cb5d9547 1422 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1423}
cd28ab6a 1424
793b883e
SH		 1425/* Number of list elements available for next tx */
1426static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1427{
793b883e 1428 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1429}
1430
793b883e 1431/* Estimate of number of transmit list elements required */
28bd181a 1432static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1433{
793b883e
SH		 1434 unsigned count;
1435
1436 count = sizeof(dma_addr_t) / sizeof(u32);
1437 count += skb_shinfo(skb)->nr_frags * count;
1438
89114afd 1439 if (skb_is_gso(skb))
793b883e
SH		 1440 ++count;
1441
84fa7933 1442 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1443 ++count;
1444
1445 return count;
cd28ab6a
SH		 1446}
1447
793b883e
SH		 1448/*
1449 * Put one packet in ring for transmit.
1450 * A single packet can generate multiple list elements, and
1451 * the number of ring elements will probably be less than the number
1452 * of list elements used.
1453 */
cd28ab6a
SH		 1454static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1455{
1456 struct sky2_port *sky2 = netdev_priv(dev);
1457 struct sky2_hw *hw = sky2->hw;
d1f13708 1458 struct sky2_tx_le *le = NULL;
6cdbbdf3 1459 struct tx_ring_info *re;
cd28ab6a
SH		 1460 unsigned i, len;
1461 dma_addr_t mapping;
1462 u32 addr64;
1463 u16 mss;
1464 u8 ctrl;
1465
2bb8c262
SH		 1466 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1467 return NETDEV_TX_BUSY;
cd28ab6a 1468
793b883e 1469 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1470 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1471 dev->name, sky2->tx_prod, skb->len);
1472
cd28ab6a
SH		 1473 len = skb_headlen(skb);
1474 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
36eb0c71 1475 addr64 = upper_32_bits(mapping);
793b883e 1476
a018e330 1477 /* Send high bits if changed or crosses boundary */
36eb0c71
SH		 1478 if (addr64 != sky2->tx_addr64 ||
1479 upper_32_bits(mapping + len) != sky2->tx_addr64) {
793b883e 1480 le = get_tx_le(sky2);
f65b138c 1481 le->addr = cpu_to_le32(addr64);
793b883e 1482 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 1483 sky2->tx_addr64 = upper_32_bits(mapping + len);
793b883e 1484 }
cd28ab6a
SH		 1485
1486 /* Check for TCP Segmentation Offload */
7967168c 1487 mss = skb_shinfo(skb)->gso_size;
793b883e 1488 if (mss != 0) {
ea76e635
SH		 1489
1490 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1491 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1492
1493 if (mss != sky2->tx_last_mss) {
1494 le = get_tx_le(sky2);
1495 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1496
1497 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1498 le->opcode = OP_MSS | HW_OWNER;
1499 else
1500 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1501 sky2->tx_last_mss = mss;
1502 }
cd28ab6a
SH		 1503 }
1504
cd28ab6a 1505 ctrl = 0;
d1f13708 1506#ifdef SKY2_VLAN_TAG_USED
1507 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1508 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1509 if (!le) {
1510 le = get_tx_le(sky2);
f65b138c 1511 le->addr = 0;
d1f13708 1512 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1513 } else
1514 le->opcode |= OP_VLAN;
1515 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1516 ctrl |= INS_VLAN;
1517 }
1518#endif
1519
1520 /* Handle TCP checksum offload */
84fa7933 1521 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1522 /* On Yukon EX (some versions) encoding change. */
ea76e635 1523 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1524 ctrl |= CALSUM; /* auto checksum */
1525 else {
1526 const unsigned offset = skb_transport_offset(skb);
1527 u32 tcpsum;
1528
1529 tcpsum = offset << 16; /* sum start */
1530 tcpsum |= offset + skb->csum_offset; /* sum write */
1531
1532 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1533 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1534 ctrl |= UDPTCP;
1535
1536 if (tcpsum != sky2->tx_tcpsum) {
1537 sky2->tx_tcpsum = tcpsum;
1538
1539 le = get_tx_le(sky2);
1540 le->addr = cpu_to_le32(tcpsum);
1541 le->length = 0; /* initial checksum value */
1542 le->ctrl = 1; /* one packet */
1543 le->opcode = OP_TCPLISW | HW_OWNER;
1544 }
1d179332 1545 }
cd28ab6a
SH		 1546 }
1547
1548 le = get_tx_le(sky2);
f65b138c 1549 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1550 le->length = cpu_to_le16(len);
1551 le->ctrl = ctrl;
793b883e 1552 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1553
291ea614 1554 re = tx_le_re(sky2, le);
cd28ab6a 1555 re->skb = skb;
6cdbbdf3 1556 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1557 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1558
1559 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1560 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1561
1562 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1563 frag->size, PCI_DMA_TODEVICE);
36eb0c71 1564 addr64 = upper_32_bits(mapping);
793b883e
SH		 1565 if (addr64 != sky2->tx_addr64) {
1566 le = get_tx_le(sky2);
f65b138c 1567 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1568 le->ctrl = 0;
1569 le->opcode = OP_ADDR64 | HW_OWNER;
1570 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1571 }
1572
1573 le = get_tx_le(sky2);
f65b138c 1574 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1575 le->length = cpu_to_le16(frag->size);
1576 le->ctrl = ctrl;
793b883e 1577 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1578
291ea614
SH		 1579 re = tx_le_re(sky2, le);
1580 re->skb = skb;
1581 pci_unmap_addr_set(re, mapaddr, mapping);
1582 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1583 }
6cdbbdf3 1584
cd28ab6a
SH		 1585 le->ctrl |= EOP;
1586
97bda706 1587 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1588 netif_stop_queue(dev);
b19666d9 1589
290d4de5 1590 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1591
cd28ab6a
SH		 1592 dev->trans_start = jiffies;
1593 return NETDEV_TX_OK;
1594}
1595
cd28ab6a 1596/*
793b883e
SH		 1597 * Free ring elements from starting at tx_cons until "done"
1598 *
1599 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1600 * buffers so make sure not to free skb to early.
cd28ab6a 1601 */
d11c13e7 1602static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1603{
d11c13e7 1604 struct net_device *dev = sky2->netdev;
af2a58ac 1605 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1606 unsigned idx;
cd28ab6a 1607
0e3ff6aa 1608 BUG_ON(done >= TX_RING_SIZE);
2224795d 1609
291ea614
SH		 1610 for (idx = sky2->tx_cons; idx != done;
1611 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1612 struct sky2_tx_le *le = sky2->tx_le + idx;
1613 struct tx_ring_info *re = sky2->tx_ring + idx;
1614
1615 switch(le->opcode & ~HW_OWNER) {
1616 case OP_LARGESEND:
1617 case OP_PACKET:
1618 pci_unmap_single(pdev,
1619 pci_unmap_addr(re, mapaddr),
1620 pci_unmap_len(re, maplen),
1621 PCI_DMA_TODEVICE);
af2a58ac 1622 break;
291ea614
SH		 1623 case OP_BUFFER:
1624 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1625 pci_unmap_len(re, maplen),
734d1868 1626 PCI_DMA_TODEVICE);
291ea614
SH		 1627 break;
1628 }
1629
1630 if (le->ctrl & EOP) {
1631 if (unlikely(netif_msg_tx_done(sky2)))
1632 printk(KERN_DEBUG "%s: tx done %u\n",
1633 dev->name, idx);
3cf26753 1634
2bf56fe2 1635 sky2->net_stats.tx_packets++;
1636 sky2->net_stats.tx_bytes += re->skb->len;
1637
794b2bd2 1638 dev_kfree_skb_any(re->skb);
3cf26753 1639 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1640 }
793b883e 1641 }
793b883e 1642
291ea614 1643 sky2->tx_cons = idx;
50432cb5
SH		 1644 smp_mb();
1645
22e11703 1646 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1647 netif_wake_queue(dev);
cd28ab6a
SH		 1648}
1649
1650/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1651static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1652{
2bb8c262
SH		 1653 struct sky2_port *sky2 = netdev_priv(dev);
1654
1655 netif_tx_lock_bh(dev);
d11c13e7 1656 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1657 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1658}
1659
1660/* Network shutdown */
1661static int sky2_down(struct net_device *dev)
1662{
1663 struct sky2_port *sky2 = netdev_priv(dev);
1664 struct sky2_hw *hw = sky2->hw;
1665 unsigned port = sky2->port;
1666 u16 ctrl;
e07b1aa8 1667 u32 imask;
cd28ab6a 1668
1b537565
SH		 1669 /* Never really got started! */
1670 if (!sky2->tx_le)
1671 return 0;
1672
cd28ab6a
SH		 1673 if (netif_msg_ifdown(sky2))
1674 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1675
018d1c66 1676 /* Stop more packets from being queued */
cd28ab6a
SH		 1677 netif_stop_queue(dev);
1678
ebc646f6
SH		 1679 /* Disable port IRQ */
1680 imask = sky2_read32(hw, B0_IMSK);
1681 imask &= ~portirq_msk[port];
1682 sky2_write32(hw, B0_IMSK, imask);
1683
d3bcfbeb 1684 sky2_gmac_reset(hw, port);
793b883e 1685
cd28ab6a
SH		 1686 /* Stop transmitter */
1687 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1688 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1689
1690 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1691 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1692
1693 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1694 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1695 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1696
1697 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1698
1699 /* Workaround shared GMAC reset */
793b883e
SH		 1700 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1701 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1702 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1703
1704 /* Disable Force Sync bit and Enable Alloc bit */
1705 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1706 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1707
1708 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1709 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1710 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1711
1712 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1713 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1714 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1715
1716 /* Reset the Tx prefetch units */
1717 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1718 PREF_UNIT_RST_SET);
1719
1720 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1721
6b1a3aef 1722 sky2_rx_stop(sky2);
cd28ab6a
SH		 1723
1724 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1725 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1726
d3bcfbeb 1727 sky2_phy_power(hw, port, 0);
1728
55d7b4e6
SH		 1729 netif_carrier_off(dev);
1730
d571b694 1731 /* turn off LED's */
cd28ab6a
SH		 1732 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1733
018d1c66 1734 synchronize_irq(hw->pdev->irq);
1735
2bb8c262 1736 sky2_tx_clean(dev);
cd28ab6a
SH		 1737 sky2_rx_clean(sky2);
1738
1739 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1740 sky2->rx_le, sky2->rx_le_map);
1741 kfree(sky2->rx_ring);
1742
1743 pci_free_consistent(hw->pdev,
1744 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1745 sky2->tx_le, sky2->tx_le_map);
1746 kfree(sky2->tx_ring);
1747
1b537565
SH		 1748 sky2->tx_le = NULL;
1749 sky2->rx_le = NULL;
1750
1751 sky2->rx_ring = NULL;
1752 sky2->tx_ring = NULL;
1753
cd28ab6a
SH		 1754 return 0;
1755}
1756
1757static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1758{
ea76e635 1759 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1760 return SPEED_1000;
1761
05745c4a
SH		 1762 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1763 if (aux & PHY_M_PS_SPEED_100)
1764 return SPEED_100;
1765 else
1766 return SPEED_10;
1767 }
cd28ab6a
SH		 1768
1769 switch (aux & PHY_M_PS_SPEED_MSK) {
1770 case PHY_M_PS_SPEED_1000:
1771 return SPEED_1000;
1772 case PHY_M_PS_SPEED_100:
1773 return SPEED_100;
1774 default:
1775 return SPEED_10;
1776 }
1777}
1778
1779static void sky2_link_up(struct sky2_port *sky2)
1780{
1781 struct sky2_hw *hw = sky2->hw;
1782 unsigned port = sky2->port;
1783 u16 reg;
16ad91e1
SH		 1784 static const char *fc_name[] = {
1785 [FC_NONE] = "none",
1786 [FC_TX] = "tx",
1787 [FC_RX] = "rx",
1788 [FC_BOTH] = "both",
1789 };
cd28ab6a 1790
cd28ab6a 1791 /* enable Rx/Tx */
2eaba1a2 1792 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1793 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1794 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1795
1796 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1797
1798 netif_carrier_on(sky2->netdev);
cd28ab6a 1799
75e80683 1800 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1801
cd28ab6a 1802 /* Turn on link LED */
793b883e 1803 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1804 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1805
ea76e635 1806 if (hw->flags & SKY2_HW_NEWER_PHY) {
793b883e 1807 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1808 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1809
1810 switch(sky2->speed) {
1811 case SPEED_10:
1812 led |= PHY_M_LEDC_INIT_CTRL(7);
1813 break;
1814
1815 case SPEED_100:
1816 led |= PHY_M_LEDC_STA1_CTRL(7);
1817 break;
1818
1819 case SPEED_1000:
1820 led |= PHY_M_LEDC_STA0_CTRL(7);
1821 break;
1822 }
793b883e
SH		 1823
1824 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1825 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1826 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1827 }
1828
cd28ab6a
SH		 1829 if (netif_msg_link(sky2))
1830 printk(KERN_INFO PFX
d571b694 1831 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1832 sky2->netdev->name, sky2->speed,
1833 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1834 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1835}
1836
1837static void sky2_link_down(struct sky2_port *sky2)
1838{
1839 struct sky2_hw *hw = sky2->hw;
1840 unsigned port = sky2->port;
1841 u16 reg;
1842
1843 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1844
1845 reg = gma_read16(hw, port, GM_GP_CTRL);
1846 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1847 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1848
cd28ab6a 1849 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1850
1851 /* Turn on link LED */
1852 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1853
1854 if (netif_msg_link(sky2))
1855 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1856
cd28ab6a
SH		 1857 sky2_phy_init(hw, port);
1858}
1859
16ad91e1
SH		 1860static enum flow_control sky2_flow(int rx, int tx)
1861{
1862 if (rx)
1863 return tx ? FC_BOTH : FC_RX;
1864 else
1865 return tx ? FC_TX : FC_NONE;
1866}
1867
793b883e
SH		 1868static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1869{
1870 struct sky2_hw *hw = sky2->hw;
1871 unsigned port = sky2->port;
da4c1ff4 1872 u16 advert, lpa;
793b883e 1873
da4c1ff4 1874 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1875 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1876 if (lpa & PHY_M_AN_RF) {
1877 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1878 return -1;
1879 }
1880
793b883e
SH		 1881 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1882 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1883 sky2->netdev->name);
1884 return -1;
1885 }
1886
793b883e 1887 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1888 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1889
da4c1ff4
SH		 1890 /* Since the pause result bits seem to in different positions on
1891 * different chips. look at registers.
1892 */
ea76e635 1893 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 1894 /* Shift for bits in fiber PHY */
1895 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1896 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1897
1898 if (advert & ADVERTISE_1000XPAUSE)
1899 advert |= ADVERTISE_PAUSE_CAP;
1900 if (advert & ADVERTISE_1000XPSE_ASYM)
1901 advert |= ADVERTISE_PAUSE_ASYM;
1902 if (lpa & LPA_1000XPAUSE)
1903 lpa |= LPA_PAUSE_CAP;
1904 if (lpa & LPA_1000XPAUSE_ASYM)
1905 lpa |= LPA_PAUSE_ASYM;
1906 }
793b883e 1907
da4c1ff4
SH		 1908 sky2->flow_status = FC_NONE;
1909 if (advert & ADVERTISE_PAUSE_CAP) {
1910 if (lpa & LPA_PAUSE_CAP)
1911 sky2->flow_status = FC_BOTH;
1912 else if (advert & ADVERTISE_PAUSE_ASYM)
1913 sky2->flow_status = FC_RX;
1914 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1915 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1916 sky2->flow_status = FC_TX;
1917 }
793b883e 1918
16ad91e1 1919 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1920 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1921 sky2->flow_status = FC_NONE;
2eaba1a2 1922
da4c1ff4 1923 if (sky2->flow_status & FC_TX)
793b883e
SH		 1924 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1925 else
1926 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1927
1928 return 0;
1929}
cd28ab6a 1930
e07b1aa8
SH		 1931/* Interrupt from PHY */
1932static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1933{
e07b1aa8
SH		 1934 struct net_device *dev = hw->dev[port];
1935 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1936 u16 istatus, phystat;
1937
ebc646f6
SH		 1938 if (!netif_running(dev))
1939 return;
1940
e07b1aa8
SH		 1941 spin_lock(&sky2->phy_lock);
1942 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1943 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1944
cd28ab6a
SH		 1945 if (netif_msg_intr(sky2))
1946 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1947 sky2->netdev->name, istatus, phystat);
1948
2eaba1a2 1949 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1950 if (sky2_autoneg_done(sky2, phystat) == 0)
1951 sky2_link_up(sky2);
1952 goto out;
1953 }
cd28ab6a 1954
793b883e
SH		 1955 if (istatus & PHY_M_IS_LSP_CHANGE)
1956 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1957
793b883e
SH		 1958 if (istatus & PHY_M_IS_DUP_CHANGE)
1959 sky2->duplex =
1960 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1961
793b883e
SH		 1962 if (istatus & PHY_M_IS_LST_CHANGE) {
1963 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1964 sky2_link_up(sky2);
793b883e
SH		 1965 else
1966 sky2_link_down(sky2);
cd28ab6a 1967 }
793b883e 1968out:
e07b1aa8 1969 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1970}
1971
62335ab0 1972/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1973 * and tx queue is full (stopped).
1974 */
cd28ab6a
SH		 1975static void sky2_tx_timeout(struct net_device *dev)
1976{
1977 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1978 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1979
1980 if (netif_msg_timer(sky2))
1981 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1982
8f24664d 1983 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1984 dev->name, sky2->tx_cons, sky2->tx_prod,
1985 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1986 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1987
81906791
SH		 1988 /* can't restart safely under softirq */
1989 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1990}
1991
1992static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1993{
6b1a3aef 1994 struct sky2_port *sky2 = netdev_priv(dev);
1995 struct sky2_hw *hw = sky2->hw;
b628ed98 1996 unsigned port = sky2->port;
6b1a3aef 1997 int err;
1998 u16 ctl, mode;
e07b1aa8 1999 u32 imask;
cd28ab6a
SH		 2000
2001 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2002 return -EINVAL;
2003
05745c4a
SH		 2004 if (new_mtu > ETH_DATA_LEN &&
2005 (hw->chip_id == CHIP_ID_YUKON_FE ||
2006 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2007 return -EINVAL;
2008
6b1a3aef 2009 if (!netif_running(dev)) {
2010 dev->mtu = new_mtu;
2011 return 0;
2012 }
2013
e07b1aa8 2014 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 2015 sky2_write32(hw, B0_IMSK, 0);
2016
018d1c66 2017 dev->trans_start = jiffies; /* prevent tx timeout */
2018 netif_stop_queue(dev);
2019 netif_poll_disable(hw->dev[0]);
2020
e07b1aa8
SH		 2021 synchronize_irq(hw->pdev->irq);
2022
e0c28116 2023 if (sky2_read8(hw, B2_E_0) == 0)
69161611 2024 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2025
2026 ctl = gma_read16(hw, port, GM_GP_CTRL);
2027 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 2028 sky2_rx_stop(sky2);
2029 sky2_rx_clean(sky2);
cd28ab6a
SH		 2030
2031 dev->mtu = new_mtu;
14d0263f 2032
6b1a3aef 2033 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2034 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2035
2036 if (dev->mtu > ETH_DATA_LEN)
2037 mode |= GM_SMOD_JUMBO_ENA;
2038
b628ed98 2039 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2040
b628ed98 2041 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2042
6b1a3aef 2043 err = sky2_rx_start(sky2);
e07b1aa8 2044 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2045
1b537565
SH		 2046 if (err)
2047 dev_close(dev);
2048 else {
b628ed98 2049 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565
SH		 2050
2051 netif_poll_enable(hw->dev[0]);
2052 netif_wake_queue(dev);
2053 }
2054
cd28ab6a
SH		 2055 return err;
2056}
2057
14d0263f
SH		 2058/* For small just reuse existing skb for next receive */
2059static struct sk_buff *receive_copy(struct sky2_port *sky2,
2060 const struct rx_ring_info *re,
2061 unsigned length)
2062{
2063 struct sk_buff *skb;
2064
2065 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2066 if (likely(skb)) {
2067 skb_reserve(skb, 2);
2068 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2069 length, PCI_DMA_FROMDEVICE);
d626f62b 2070 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2071 skb->ip_summed = re->skb->ip_summed;
2072 skb->csum = re->skb->csum;
2073 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2074 length, PCI_DMA_FROMDEVICE);
2075 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2076 skb_put(skb, length);
14d0263f
SH		 2077 }
2078 return skb;
2079}
2080
2081/* Adjust length of skb with fragments to match received data */
2082static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2083 unsigned int length)
2084{
2085 int i, num_frags;
2086 unsigned int size;
2087
2088 /* put header into skb */
2089 size = min(length, hdr_space);
2090 skb->tail += size;
2091 skb->len += size;
2092 length -= size;
2093
2094 num_frags = skb_shinfo(skb)->nr_frags;
2095 for (i = 0; i < num_frags; i++) {
2096 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2097
2098 if (length == 0) {
2099 /* don't need this page */
2100 __free_page(frag->page);
2101 --skb_shinfo(skb)->nr_frags;
2102 } else {
2103 size = min(length, (unsigned) PAGE_SIZE);
2104
2105 frag->size = size;
2106 skb->data_len += size;
2107 skb->truesize += size;
2108 skb->len += size;
2109 length -= size;
2110 }
2111 }
2112}
2113
2114/* Normal packet - take skb from ring element and put in a new one */
2115static struct sk_buff *receive_new(struct sky2_port *sky2,
2116 struct rx_ring_info *re,
2117 unsigned int length)
2118{
2119 struct sk_buff *skb, *nskb;
2120 unsigned hdr_space = sky2->rx_data_size;
2121
14d0263f
SH		 2122 /* Don't be tricky about reusing pages (yet) */
2123 nskb = sky2_rx_alloc(sky2);
2124 if (unlikely(!nskb))
2125 return NULL;
2126
2127 skb = re->skb;
2128 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2129
2130 prefetch(skb->data);
2131 re->skb = nskb;
2132 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2133
2134 if (skb_shinfo(skb)->nr_frags)
2135 skb_put_frags(skb, hdr_space, length);
2136 else
489b10c1 2137 skb_put(skb, length);
14d0263f
SH		 2138 return skb;
2139}
2140
cd28ab6a
SH		 2141/*
2142 * Receive one packet.
d571b694 2143 * For larger packets, get new buffer.
cd28ab6a 2144 */
497d7c86 2145static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2146 u16 length, u32 status)
2147{
497d7c86 2148 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2149 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2150 struct sk_buff *skb = NULL;
d6532232
SH		 2151 u16 count = (status & GMR_FS_LEN) >> 16;
2152
2153#ifdef SKY2_VLAN_TAG_USED
2154 /* Account for vlan tag */
2155 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2156 count -= VLAN_HLEN;
2157#endif
cd28ab6a
SH		 2158
2159 if (unlikely(netif_msg_rx_status(sky2)))
2160 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2161 dev->name, sky2->rx_next, status, length);
cd28ab6a 2162
793b883e 2163 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2164 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2165
3b12e014
SH		 2166 /* This chip has hardware problems that generates bogus status.
2167 * So do only marginal checking and expect higher level protocols
2168 * to handle crap frames.
2169 */
2170 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2171 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2172 length != count)
2173 goto okay;
2174
42eeea01 2175 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2176 goto error;
2177
42eeea01 2178 if (!(status & GMR_FS_RX_OK))
2179 goto resubmit;
2180
d6532232
SH		 2181 /* if length reported by DMA does not match PHY, packet was truncated */
2182 if (length != count)
3b12e014 2183 goto len_error;
71749531 2184
3b12e014 2185okay:
14d0263f
SH		 2186 if (length < copybreak)
2187 skb = receive_copy(sky2, re, length);
2188 else
2189 skb = receive_new(sky2, re, length);
793b883e 2190resubmit:
14d0263f 2191 sky2_rx_submit(sky2, re);
79e57d32 2192
cd28ab6a
SH		 2193 return skb;
2194
3b12e014 2195len_error:
71749531
SH		 2196 /* Truncation of overlength packets
2197 causes PHY length to not match MAC length */
2198 ++sky2->net_stats.rx_length_errors;
d6532232 2199 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2200 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2201 dev->name, status, length);
d6532232 2202 goto resubmit;
71749531 2203
cd28ab6a 2204error:
6e15b712 2205 ++sky2->net_stats.rx_errors;
b6d77734 2206 if (status & GMR_FS_RX_FF_OV) {
a79abdc6 2207 sky2->net_stats.rx_over_errors++;
b6d77734
SH		 2208 goto resubmit;
2209 }
6e15b712 2210
3be92a70 2211 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2212 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2213 dev->name, status, length);
793b883e
SH		 2214
2215 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2216 sky2->net_stats.rx_length_errors++;
2217 if (status & GMR_FS_FRAGMENT)
2218 sky2->net_stats.rx_frame_errors++;
2219 if (status & GMR_FS_CRC_ERR)
2220 sky2->net_stats.rx_crc_errors++;
79e57d32 2221
793b883e 2222 goto resubmit;
cd28ab6a
SH		 2223}
2224
e07b1aa8
SH		 2225/* Transmit complete */
2226static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2227{
e07b1aa8 2228 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2229
e07b1aa8 2230 if (netif_running(dev)) {
2bb8c262 2231 netif_tx_lock(dev);
e07b1aa8 2232 sky2_tx_complete(sky2, last);
2bb8c262 2233 netif_tx_unlock(dev);
2224795d 2234 }
cd28ab6a
SH		 2235}
2236
e07b1aa8
SH		 2237/* Process status response ring */
2238static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2239{
e07b1aa8 2240 int work_done = 0;
55c9dd35 2241 unsigned rx[2] = { 0, 0 };
e71ebd73 2242 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2243
af2a58ac 2244 rmb();
bea86103 2245
e71ebd73 2246 while (hw->st_idx != hwidx) {
55c9dd35 2247 struct sky2_port *sky2;
13210ce5 2248 struct sky2_status_le *le = hw->st_le + hw->st_idx;
69161611 2249 unsigned port = le->css & CSS_LINK_BIT;
13210ce5 2250 struct net_device *dev;
cd28ab6a 2251 struct sk_buff *skb;
cd28ab6a
SH		 2252 u32 status;
2253 u16 length;
2254
cb5d9547 2255 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2256
69161611 2257 dev = hw->dev[port];
13210ce5 2258 sky2 = netdev_priv(dev);
f65b138c
SH		 2259 length = le16_to_cpu(le->length);
2260 status = le32_to_cpu(le->status);
cd28ab6a 2261
e71ebd73 2262 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2263 case OP_RXSTAT:
55c9dd35 2264 ++rx[port];
497d7c86 2265 skb = sky2_receive(dev, length, status);
3225b919
SH		 2266 if (unlikely(!skb)) {
2267 sky2->net_stats.rx_dropped++;
55c9dd35 2268 break;
3225b919 2269 }
13210ce5 2270
69161611 2271 /* This chip reports checksum status differently */
05745c4a 2272 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2273 if (sky2->rx_csum &&
2274 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2275 (le->css & CSS_TCPUDPCSOK))
2276 skb->ip_summed = CHECKSUM_UNNECESSARY;
2277 else
2278 skb->ip_summed = CHECKSUM_NONE;
2279 }
2280
13210ce5 2281 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2282 sky2->net_stats.rx_packets++;
2283 sky2->net_stats.rx_bytes += skb->len;
13210ce5 2284 dev->last_rx = jiffies;
2285
d1f13708 2286#ifdef SKY2_VLAN_TAG_USED
2287 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2288 vlan_hwaccel_receive_skb(skb,
2289 sky2->vlgrp,
2290 be16_to_cpu(sky2->rx_tag));
2291 } else
2292#endif
cd28ab6a 2293 netif_receive_skb(skb);
13210ce5 2294
22e11703 2295 /* Stop after net poll weight */
13210ce5 2296 if (++work_done >= to_do)
2297 goto exit_loop;
cd28ab6a
SH		 2298 break;
2299
d1f13708 2300#ifdef SKY2_VLAN_TAG_USED
2301 case OP_RXVLAN:
2302 sky2->rx_tag = length;
2303 break;
2304
2305 case OP_RXCHKSVLAN:
2306 sky2->rx_tag = length;
2307 /* fall through */
2308#endif
cd28ab6a 2309 case OP_RXCHKS:
87418307
SH		 2310 if (!sky2->rx_csum)
2311 break;
2312
05745c4a
SH		 2313 /* If this happens then driver assuming wrong format */
2314 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2315 if (net_ratelimit())
2316 printk(KERN_NOTICE "%s: unexpected"
2317 " checksum status\n",
2318 dev->name);
69161611 2319 break;
05745c4a 2320 }
69161611 2321
87418307
SH		 2322 /* Both checksum counters are programmed to start at
2323 * the same offset, so unless there is a problem they
2324 * should match. This failure is an early indication that
2325 * hardware receive checksumming won't work.
2326 */
2327 if (likely(status >> 16 == (status & 0xffff))) {
2328 skb = sky2->rx_ring[sky2->rx_next].skb;
2329 skb->ip_summed = CHECKSUM_COMPLETE;
2330 skb->csum = status & 0xffff;
2331 } else {
2332 printk(KERN_NOTICE PFX "%s: hardware receive "
2333 "checksum problem (status = %#x)\n",
2334 dev->name, status);
2335 sky2->rx_csum = 0;
2336 sky2_write32(sky2->hw,
69161611 2337 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2338 BMU_DIS_RX_CHKSUM);
2339 }
cd28ab6a
SH		 2340 break;
2341
2342 case OP_TXINDEXLE:
13b97b74 2343 /* TX index reports status for both ports */
f55925d7
SH		 2344 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2345 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2346 if (hw->dev[1])
2347 sky2_tx_done(hw->dev[1],
2348 ((status >> 24) & 0xff)
2349 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2350 break;
2351
cd28ab6a
SH		 2352 default:
2353 if (net_ratelimit())
793b883e 2354 printk(KERN_WARNING PFX
e71ebd73 2355 "unknown status opcode 0x%x\n", le->opcode);
cd28ab6a 2356 }
13210ce5 2357 }
cd28ab6a 2358
fe2a24df
SH		 2359 /* Fully processed status ring so clear irq */
2360 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2361
13210ce5 2362exit_loop:
55c9dd35
SH		 2363 if (rx[0])
2364 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2365
55c9dd35
SH		 2366 if (rx[1])
2367 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2368
e07b1aa8 2369 return work_done;
cd28ab6a
SH		 2370}
2371
2372static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2373{
2374 struct net_device *dev = hw->dev[port];
2375
3be92a70
SH		 2376 if (net_ratelimit())
2377 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2378 dev->name, status);
cd28ab6a
SH		 2379
2380 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2381 if (net_ratelimit())
2382 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2383 dev->name);
cd28ab6a
SH		 2384 /* Clear IRQ */
2385 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2386 }
2387
2388 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2389 if (net_ratelimit())
2390 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2391 dev->name);
cd28ab6a
SH		 2392
2393 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2394 }
2395
2396 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2397 if (net_ratelimit())
2398 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2399 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2400 }
2401
2402 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2403 if (net_ratelimit())
2404 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2405 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2406 }
2407
2408 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2409 if (net_ratelimit())
2410 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2411 dev->name);
cd28ab6a
SH		 2412 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2413 }
2414}
2415
2416static void sky2_hw_intr(struct sky2_hw *hw)
2417{
2418 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2419
793b883e 2420 if (status & Y2_IS_TIST_OV)
cd28ab6a 2421 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2422
2423 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2424 u16 pci_err;
2425
56a645cc 2426 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2427 if (net_ratelimit())
b02a9258
SH		 2428 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2429 pci_err);
cd28ab6a
SH		 2430
2431 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2432 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2433 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2434 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2435 }
2436
2437 if (status & Y2_IS_PCI_EXP) {
d571b694 2438 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2439 u32 pex_err;
2440
7bd656d1 2441 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2442
3be92a70 2443 if (net_ratelimit())
b02a9258
SH		 2444 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2445 pex_err);
cd28ab6a
SH		 2446
2447 /* clear the interrupt */
2448 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2449 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2450 0xffffffffUL);
cd28ab6a
SH		 2451 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2452
7bd656d1 2453 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2454 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2455 hwmsk &= ~Y2_IS_PCI_EXP;
2456 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2457 }
2458 }
2459
2460 if (status & Y2_HWE_L1_MASK)
2461 sky2_hw_error(hw, 0, status);
2462 status >>= 8;
2463 if (status & Y2_HWE_L1_MASK)
2464 sky2_hw_error(hw, 1, status);
2465}
2466
2467static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2468{
2469 struct net_device *dev = hw->dev[port];
2470 struct sky2_port *sky2 = netdev_priv(dev);
2471 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2472
2473 if (netif_msg_intr(sky2))
2474 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2475 dev->name, status);
2476
a3caeada
SH		 2477 if (status & GM_IS_RX_CO_OV)
2478 gma_read16(hw, port, GM_RX_IRQ_SRC);
2479
2480 if (status & GM_IS_TX_CO_OV)
2481 gma_read16(hw, port, GM_TX_IRQ_SRC);
2482
cd28ab6a
SH		 2483 if (status & GM_IS_RX_FF_OR) {
2484 ++sky2->net_stats.rx_fifo_errors;
2485 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2486 }
2487
2488 if (status & GM_IS_TX_FF_UR) {
2489 ++sky2->net_stats.tx_fifo_errors;
2490 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2491 }
cd28ab6a
SH		 2492}
2493
40b01727
SH		 2494/* This should never happen it is a bug. */
2495static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2496 u16 q, unsigned ring_size)
d257924e
SH		 2497{
2498 struct net_device *dev = hw->dev[port];
2499 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2500 unsigned idx;
2501 const u64 *le = (q == Q_R1 || q == Q_R2)
2502 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2503
40b01727
SH		 2504 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2505 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2506 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2507 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2508
40b01727 2509 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2510}
cd28ab6a 2511
75e80683
SH		 2512static int sky2_rx_hung(struct net_device *dev)
2513{
2514 struct sky2_port *sky2 = netdev_priv(dev);
2515 struct sky2_hw *hw = sky2->hw;
2516 unsigned port = sky2->port;
2517 unsigned rxq = rxqaddr[port];
2518 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2519 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2520 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2521 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2522
2523 /* If idle and MAC or PCI is stuck */
2524 if (sky2->check.last == dev->last_rx &&
2525 ((mac_rp == sky2->check.mac_rp &&
2526 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2527 /* Check if the PCI RX hang */
2528 (fifo_rp == sky2->check.fifo_rp &&
2529 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2530 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2531 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2532 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2533 return 1;
2534 } else {
2535 sky2->check.last = dev->last_rx;
2536 sky2->check.mac_rp = mac_rp;
2537 sky2->check.mac_lev = mac_lev;
2538 sky2->check.fifo_rp = fifo_rp;
2539 sky2->check.fifo_lev = fifo_lev;
2540 return 0;
2541 }
2542}
2543
32c2c300 2544static void sky2_watchdog(unsigned long arg)
d27ed387 2545{
01bd7564 2546 struct sky2_hw *hw = (struct sky2_hw *) arg;
75e80683 2547 struct net_device *dev;
d27ed387 2548
75e80683 2549 /* Check for lost IRQ once a second */
32c2c300 2550 if (sky2_read32(hw, B0_ISRC)) {
75e80683 2551 dev = hw->dev[0];
32c2c300
SH		 2552 if (__netif_rx_schedule_prep(dev))
2553 __netif_rx_schedule(dev);
75e80683
SH		 2554 } else {
2555 int i, active = 0;
2556
2557 for (i = 0; i < hw->ports; i++) {
2558 dev = hw->dev[i];
2559 if (!netif_running(dev))
2560 continue;
2561 ++active;
2562
2563 /* For chips with Rx FIFO, check if stuck */
e0c28116 2564 if ((hw->flags & SKY2_HW_FIFO_HANG_CHECK) &&
75e80683
SH		 2565 sky2_rx_hung(dev)) {
2566 pr_info(PFX "%s: receiver hang detected\n",
2567 dev->name);
2568 schedule_work(&hw->restart_work);
2569 return;
2570 }
2571 }
2572
2573 if (active == 0)
2574 return;
32c2c300 2575 }
01bd7564 2576
75e80683 2577 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2578}
2579
40b01727
SH		 2580/* Hardware/software error handling */
2581static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2582{
40b01727
SH		 2583 if (net_ratelimit())
2584 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2585
1e5f1283
SH		 2586 if (status & Y2_IS_HW_ERR)
2587 sky2_hw_intr(hw);
d257924e 2588
1e5f1283
SH		 2589 if (status & Y2_IS_IRQ_MAC1)
2590 sky2_mac_intr(hw, 0);
cd28ab6a 2591
1e5f1283
SH		 2592 if (status & Y2_IS_IRQ_MAC2)
2593 sky2_mac_intr(hw, 1);
cd28ab6a 2594
1e5f1283 2595 if (status & Y2_IS_CHK_RX1)
40b01727 2596 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2597
1e5f1283 2598 if (status & Y2_IS_CHK_RX2)
40b01727 2599 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2600
1e5f1283 2601 if (status & Y2_IS_CHK_TXA1)
40b01727 2602 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2603
1e5f1283 2604 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2605 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2606}
2607
2608static int sky2_poll(struct net_device *dev0, int *budget)
2609{
2610 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
5c11ce70 2611 int work_done;
40b01727
SH		 2612 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2613
2614 if (unlikely(status & Y2_IS_ERROR))
2615 sky2_err_intr(hw, status);
2616
2617 if (status & Y2_IS_IRQ_PHY1)
2618 sky2_phy_intr(hw, 0);
2619
2620 if (status & Y2_IS_IRQ_PHY2)
2621 sky2_phy_intr(hw, 1);
cd28ab6a 2622
5c11ce70
SH		 2623 work_done = sky2_status_intr(hw, min(dev0->quota, *budget));
2624 *budget -= work_done;
2625 dev0->quota -= work_done;
86fba634 2626
5c11ce70
SH		 2627 /* More work? */
2628 if (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX))
1e5f1283 2629 return 1;
5c11ce70
SH		 2630
2631 /* Bug/Errata workaround?
2632 * Need to kick the TX irq moderation timer.
2633 */
2634 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2635 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2636 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2637 }
5c11ce70
SH		 2638 netif_rx_complete(dev0);
2639
2640 sky2_read32(hw, B0_Y2_SP_LISR);
2641 return 0;
e07b1aa8
SH		 2642}
2643
7d12e780 2644static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2645{
2646 struct sky2_hw *hw = dev_id;
2647 struct net_device *dev0 = hw->dev[0];
2648 u32 status;
2649
2650 /* Reading this mask interrupts as side effect */
2651 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2652 if (status == 0 || status == ~0)
2653 return IRQ_NONE;
793b883e 2654
e07b1aa8
SH		 2655 prefetch(&hw->st_le[hw->st_idx]);
2656 if (likely(__netif_rx_schedule_prep(dev0)))
2657 __netif_rx_schedule(dev0);
793b883e 2658
cd28ab6a
SH		 2659 return IRQ_HANDLED;
2660}
2661
2662#ifdef CONFIG_NET_POLL_CONTROLLER
2663static void sky2_netpoll(struct net_device *dev)
2664{
2665 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2666 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2667
88d11360
SH		 2668 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2669 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2670}
2671#endif
2672
2673/* Chip internal frequency for clock calculations */
05745c4a 2674static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2675{
793b883e 2676 switch (hw->chip_id) {
cd28ab6a 2677 case CHIP_ID_YUKON_EC:
5a5b1ea0 2678 case CHIP_ID_YUKON_EC_U:
93745494 2679 case CHIP_ID_YUKON_EX:
05745c4a
SH		 2680 return 125;
2681
cd28ab6a 2682 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2683 return 100;
2684
2685 case CHIP_ID_YUKON_FE_P:
2686 return 50;
2687
2688 case CHIP_ID_YUKON_XL:
2689 return 156;
2690
2691 default:
2692 BUG();
cd28ab6a
SH		 2693 }
2694}
2695
fb17358f 2696static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2697{
fb17358f 2698 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2699}
2700
fb17358f 2701static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2702{
fb17358f 2703 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2704}
2705
fb17358f 2706
e3173832 2707static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2708{
b89165f2 2709 u8 t8;
cd28ab6a 2710
451af335
SH		 2711 /* Enable all clocks */
2712 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2713
cd28ab6a 2714 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2715
cd28ab6a 2716 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2717 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2718
2719 switch(hw->chip_id) {
2720 case CHIP_ID_YUKON_XL:
2721 hw->flags = SKY2_HW_GIGABIT
e0c28116
SH		 2722 | SKY2_HW_NEWER_PHY;
2723 if (hw->chip_rev < 3)
2724 hw->flags |= SKY2_HW_FIFO_HANG_CHECK;
2725
ea76e635
SH		 2726 break;
2727
2728 case CHIP_ID_YUKON_EC_U:
2729 hw->flags = SKY2_HW_GIGABIT
2730 | SKY2_HW_NEWER_PHY
2731 | SKY2_HW_ADV_POWER_CTL;
2732 break;
2733
2734 case CHIP_ID_YUKON_EX:
2735 hw->flags = SKY2_HW_GIGABIT
2736 | SKY2_HW_NEWER_PHY
2737 | SKY2_HW_NEW_LE
2738 | SKY2_HW_ADV_POWER_CTL;
2739
2740 /* New transmit checksum */
2741 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2742 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2743 break;
2744
2745 case CHIP_ID_YUKON_EC:
2746 /* This rev is really old, and requires untested workarounds */
2747 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2748 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2749 return -EOPNOTSUPP;
2750 }
e0c28116 2751 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_FIFO_HANG_CHECK;
ea76e635
SH		 2752 break;
2753
2754 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2755 break;
2756
05745c4a
SH		 2757 case CHIP_ID_YUKON_FE_P:
2758 hw->flags = SKY2_HW_NEWER_PHY
2759 | SKY2_HW_NEW_LE
2760 | SKY2_HW_AUTO_TX_SUM
2761 | SKY2_HW_ADV_POWER_CTL;
2762 break;
ea76e635 2763 default:
b02a9258
SH		 2764 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2765 hw->chip_id);
cd28ab6a
SH		 2766 return -EOPNOTSUPP;
2767 }
2768
ea76e635
SH		 2769 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2770 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2771 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2772
290d4de5 2773
e3173832
SH		 2774 hw->ports = 1;
2775 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2776 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2777 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2778 ++hw->ports;
2779 }
2780
2781 return 0;
2782}
2783
2784static void sky2_reset(struct sky2_hw *hw)
2785{
2786 u16 status;
2787 int i;
2788
cd28ab6a 2789 /* disable ASF */
4f44d8ba
SH		 2790 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2791 status = sky2_read16(hw, HCU_CCSR);
2792 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2793 HCU_CCSR_UC_STATE_MSK);
2794 sky2_write16(hw, HCU_CCSR, status);
2795 } else
2796 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2797 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2798
2799 /* do a SW reset */
2800 sky2_write8(hw, B0_CTST, CS_RST_SET);
2801 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2802
2803 /* clear PCI errors, if any */
56a645cc 2804 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2805
cd28ab6a 2806 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2807 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2808
cd28ab6a
SH		 2809
2810 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2811
2812 /* clear any PEX errors */
7bd656d1
SH		 2813 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2814 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2815
cd28ab6a 2816
ae306cca 2817 sky2_power_on(hw);
cd28ab6a
SH		 2818
2819 for (i = 0; i < hw->ports; i++) {
2820 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2821 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611
SH		 2822
2823 if (hw->chip_id == CHIP_ID_YUKON_EX)
2824 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2825 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2826 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2827 }
2828
2829 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2830
793b883e
SH		 2831 /* Clear I2C IRQ noise */
2832 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2833
2834 /* turn off hardware timer (unused) */
2835 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2836 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2837
cd28ab6a
SH		 2838 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2839
69634ee7
SH		 2840 /* Turn off descriptor polling */
2841 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2842
2843 /* Turn off receive timestamp */
2844 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2845 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2846
2847 /* enable the Tx Arbiters */
2848 for (i = 0; i < hw->ports; i++)
2849 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2850
2851 /* Initialize ram interface */
2852 for (i = 0; i < hw->ports; i++) {
793b883e 2853 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2854
2855 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2856 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2857 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2858 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2859 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2860 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2861 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2862 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2863 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2864 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2865 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2866 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2867 }
2868
7bd656d1 2869 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2870
cd28ab6a 2871 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2872 sky2_gmac_reset(hw, i);
cd28ab6a 2873
cd28ab6a
SH		 2874 memset(hw->st_le, 0, STATUS_LE_BYTES);
2875 hw->st_idx = 0;
2876
2877 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2878 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2879
2880 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2881 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2882
2883 /* Set the list last index */
793b883e 2884 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2885
290d4de5
SH		 2886 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2887 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2888
290d4de5
SH		 2889 /* set Status-FIFO ISR watermark */
2890 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2891 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2892 else
2893 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2894
290d4de5 2895 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2896 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2897 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2898
793b883e 2899 /* enable status unit */
cd28ab6a
SH		 2900 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2901
2902 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2903 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2904 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2905}
2906
81906791
SH		 2907static void sky2_restart(struct work_struct *work)
2908{
2909 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2910 struct net_device *dev;
2911 int i, err;
2912
81906791
SH		 2913 rtnl_lock();
2914 sky2_write32(hw, B0_IMSK, 0);
2915 sky2_read32(hw, B0_IMSK);
2916
2917 netif_poll_disable(hw->dev[0]);
2918
2919 for (i = 0; i < hw->ports; i++) {
2920 dev = hw->dev[i];
2921 if (netif_running(dev))
2922 sky2_down(dev);
2923 }
2924
2925 sky2_reset(hw);
2926 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2927 netif_poll_enable(hw->dev[0]);
2928
2929 for (i = 0; i < hw->ports; i++) {
2930 dev = hw->dev[i];
2931 if (netif_running(dev)) {
2932 err = sky2_up(dev);
2933 if (err) {
2934 printk(KERN_INFO PFX "%s: could not restart %d\n",
2935 dev->name, err);
2936 dev_close(dev);
2937 }
2938 }
2939 }
2940
81906791
SH		 2941 rtnl_unlock();
2942}
2943
e3173832
SH		 2944static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2945{
2946 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2947}
2948
2949static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2950{
2951 const struct sky2_port *sky2 = netdev_priv(dev);
2952
2953 wol->supported = sky2_wol_supported(sky2->hw);
2954 wol->wolopts = sky2->wol;
2955}
2956
2957static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2958{
2959 struct sky2_port *sky2 = netdev_priv(dev);
2960 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2961
e3173832
SH		 2962 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2963 return -EOPNOTSUPP;
2964
2965 sky2->wol = wol->wolopts;
2966
05745c4a
SH		 2967 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2968 hw->chip_id == CHIP_ID_YUKON_EX ||
2969 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 2970 sky2_write32(hw, B0_CTST, sky2->wol
2971 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2972
2973 if (!netif_running(dev))
2974 sky2_wol_init(sky2);
cd28ab6a
SH		 2975 return 0;
2976}
2977
28bd181a 2978static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2979{
b89165f2
SH		 2980 if (sky2_is_copper(hw)) {
2981 u32 modes = SUPPORTED_10baseT_Half
2982 | SUPPORTED_10baseT_Full
2983 | SUPPORTED_100baseT_Half
2984 | SUPPORTED_100baseT_Full
2985 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2986
ea76e635 2987 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 2988 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2989 | SUPPORTED_1000baseT_Full;
2990 return modes;
cd28ab6a 2991 } else
b89165f2
SH		 2992 return SUPPORTED_1000baseT_Half
2993 | SUPPORTED_1000baseT_Full
2994 | SUPPORTED_Autoneg
2995 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2996}
2997
793b883e 2998static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2999{
3000 struct sky2_port *sky2 = netdev_priv(dev);
3001 struct sky2_hw *hw = sky2->hw;
3002
3003 ecmd->transceiver = XCVR_INTERNAL;
3004 ecmd->supported = sky2_supported_modes(hw);
3005 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3006 if (sky2_is_copper(hw)) {
cd28ab6a 3007 ecmd->port = PORT_TP;
b89165f2
SH		 3008 ecmd->speed = sky2->speed;
3009 } else {
3010 ecmd->speed = SPEED_1000;
cd28ab6a 3011 ecmd->port = PORT_FIBRE;
b89165f2 3012 }
cd28ab6a
SH		 3013
3014 ecmd->advertising = sky2->advertising;
3015 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3016 ecmd->duplex = sky2->duplex;
3017 return 0;
3018}
3019
3020static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3021{
3022 struct sky2_port *sky2 = netdev_priv(dev);
3023 const struct sky2_hw *hw = sky2->hw;
3024 u32 supported = sky2_supported_modes(hw);
3025
3026 if (ecmd->autoneg == AUTONEG_ENABLE) {
3027 ecmd->advertising = supported;
3028 sky2->duplex = -1;
3029 sky2->speed = -1;
3030 } else {
3031 u32 setting;
3032
793b883e 3033 switch (ecmd->speed) {
cd28ab6a
SH		 3034 case SPEED_1000:
3035 if (ecmd->duplex == DUPLEX_FULL)
3036 setting = SUPPORTED_1000baseT_Full;
3037 else if (ecmd->duplex == DUPLEX_HALF)
3038 setting = SUPPORTED_1000baseT_Half;
3039 else
3040 return -EINVAL;
3041 break;
3042 case SPEED_100:
3043 if (ecmd->duplex == DUPLEX_FULL)
3044 setting = SUPPORTED_100baseT_Full;
3045 else if (ecmd->duplex == DUPLEX_HALF)
3046 setting = SUPPORTED_100baseT_Half;
3047 else
3048 return -EINVAL;
3049 break;
3050
3051 case SPEED_10:
3052 if (ecmd->duplex == DUPLEX_FULL)
3053 setting = SUPPORTED_10baseT_Full;
3054 else if (ecmd->duplex == DUPLEX_HALF)
3055 setting = SUPPORTED_10baseT_Half;
3056 else
3057 return -EINVAL;
3058 break;
3059 default:
3060 return -EINVAL;
3061 }
3062
3063 if ((setting & supported) == 0)
3064 return -EINVAL;
3065
3066 sky2->speed = ecmd->speed;
3067 sky2->duplex = ecmd->duplex;
3068 }
3069
3070 sky2->autoneg = ecmd->autoneg;
3071 sky2->advertising = ecmd->advertising;
3072
d1b139c0 3073 if (netif_running(dev)) {
1b537565 3074 sky2_phy_reinit(sky2);
d1b139c0
SH		 3075 sky2_set_multicast(dev);
3076 }
cd28ab6a
SH		 3077
3078 return 0;
3079}
3080
3081static void sky2_get_drvinfo(struct net_device *dev,
3082 struct ethtool_drvinfo *info)
3083{
3084 struct sky2_port *sky2 = netdev_priv(dev);
3085
3086 strcpy(info->driver, DRV_NAME);
3087 strcpy(info->version, DRV_VERSION);
3088 strcpy(info->fw_version, "N/A");
3089 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3090}
3091
3092static const struct sky2_stat {
793b883e
SH		 3093 char name[ETH_GSTRING_LEN];
3094 u16 offset;
cd28ab6a
SH		 3095} sky2_stats[] = {
3096 { "tx_bytes", GM_TXO_OK_HI },
3097 { "rx_bytes", GM_RXO_OK_HI },
3098 { "tx_broadcast", GM_TXF_BC_OK },
3099 { "rx_broadcast", GM_RXF_BC_OK },
3100 { "tx_multicast", GM_TXF_MC_OK },
3101 { "rx_multicast", GM_RXF_MC_OK },
3102 { "tx_unicast", GM_TXF_UC_OK },
3103 { "rx_unicast", GM_RXF_UC_OK },
3104 { "tx_mac_pause", GM_TXF_MPAUSE },
3105 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3106 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3107 { "late_collision",GM_TXF_LAT_COL },
3108 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3109 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3110 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3111
d2604540 3112 { "rx_short", GM_RXF_SHT },
cd28ab6a 3113 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3114 { "rx_64_byte_packets", GM_RXF_64B },
3115 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3116 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3117 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3118 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3119 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3120 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3121 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3122 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3123 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3124 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3125
3126 { "tx_64_byte_packets", GM_TXF_64B },
3127 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3128 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3129 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3130 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3131 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3132 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3133 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3134};
3135
cd28ab6a
SH		 3136static u32 sky2_get_rx_csum(struct net_device *dev)
3137{
3138 struct sky2_port *sky2 = netdev_priv(dev);
3139
3140 return sky2->rx_csum;
3141}
3142
3143static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3144{
3145 struct sky2_port *sky2 = netdev_priv(dev);
3146
3147 sky2->rx_csum = data;
793b883e 3148
cd28ab6a
SH		 3149 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3150 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3151
3152 return 0;
3153}
3154
3155static u32 sky2_get_msglevel(struct net_device *netdev)
3156{
3157 struct sky2_port *sky2 = netdev_priv(netdev);
3158 return sky2->msg_enable;
3159}
3160
9a7ae0a9
SH		 3161static int sky2_nway_reset(struct net_device *dev)
3162{
3163 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3164
16ad91e1 3165 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3166 return -EINVAL;
3167
1b537565 3168 sky2_phy_reinit(sky2);
d1b139c0 3169 sky2_set_multicast(dev);
9a7ae0a9
SH		 3170
3171 return 0;
3172}
3173
793b883e 3174static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3175{
3176 struct sky2_hw *hw = sky2->hw;
3177 unsigned port = sky2->port;
3178 int i;
3179
3180 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3181 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3182 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3183 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3184
793b883e 3185 for (i = 2; i < count; i++)
cd28ab6a
SH		 3186 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3187}
3188
cd28ab6a
SH		 3189static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3190{
3191 struct sky2_port *sky2 = netdev_priv(netdev);
3192 sky2->msg_enable = value;
3193}
3194
3195static int sky2_get_stats_count(struct net_device *dev)
3196{
3197 return ARRAY_SIZE(sky2_stats);
3198}
3199
3200static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3201 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3202{
3203 struct sky2_port *sky2 = netdev_priv(dev);
3204
793b883e 3205 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3206}
3207
793b883e 3208static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3209{
3210 int i;
3211
3212 switch (stringset) {
3213 case ETH_SS_STATS:
3214 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3215 memcpy(data + i * ETH_GSTRING_LEN,
3216 sky2_stats[i].name, ETH_GSTRING_LEN);
3217 break;
3218 }
3219}
3220
cd28ab6a
SH		 3221static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3222{
3223 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3224 return &sky2->net_stats;
3225}
3226
3227static int sky2_set_mac_address(struct net_device *dev, void *p)
3228{
3229 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3230 struct sky2_hw *hw = sky2->hw;
3231 unsigned port = sky2->port;
3232 const struct sockaddr *addr = p;
cd28ab6a
SH		 3233
3234 if (!is_valid_ether_addr(addr->sa_data))
3235 return -EADDRNOTAVAIL;
3236
cd28ab6a 3237 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3238 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3239 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3240 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3241 dev->dev_addr, ETH_ALEN);
1b537565 3242
a8ab1ec0
SH		 3243 /* virtual address for data */
3244 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3245
3246 /* physical address: used for pause frames */
3247 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3248
3249 return 0;
cd28ab6a
SH		 3250}
3251
a052b52f
SH		 3252static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3253{
3254 u32 bit;
3255
3256 bit = ether_crc(ETH_ALEN, addr) & 63;
3257 filter[bit >> 3] |= 1 << (bit & 7);
3258}
3259
cd28ab6a
SH		 3260static void sky2_set_multicast(struct net_device *dev)
3261{
3262 struct sky2_port *sky2 = netdev_priv(dev);
3263 struct sky2_hw *hw = sky2->hw;
3264 unsigned port = sky2->port;
3265 struct dev_mc_list *list = dev->mc_list;
3266 u16 reg;
3267 u8 filter[8];
a052b52f
SH		 3268 int rx_pause;
3269 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3270
a052b52f 3271 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3272 memset(filter, 0, sizeof(filter));
3273
3274 reg = gma_read16(hw, port, GM_RX_CTRL);
3275 reg |= GM_RXCR_UCF_ENA;
3276
d571b694 3277 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3278 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3279 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3280 memset(filter, 0xff, sizeof(filter));
a052b52f 3281 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3282 reg &= ~GM_RXCR_MCF_ENA;
3283 else {
3284 int i;
3285 reg |= GM_RXCR_MCF_ENA;
3286
a052b52f
SH		 3287 if (rx_pause)
3288 sky2_add_filter(filter, pause_mc_addr);
3289
3290 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3291 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3292 }
3293
cd28ab6a 3294 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3295 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3296 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3297 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3298 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3299 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3300 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3301 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3302
3303 gma_write16(hw, port, GM_RX_CTRL, reg);
3304}
3305
3306/* Can have one global because blinking is controlled by
3307 * ethtool and that is always under RTNL mutex
3308 */
91c86df5 3309static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3310{
793b883e
SH		 3311 u16 pg;
3312
793b883e
SH		 3313 switch (hw->chip_id) {
3314 case CHIP_ID_YUKON_XL:
3315 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3316 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3317 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3318 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3319 PHY_M_LEDC_INIT_CTRL(7) |
3320 PHY_M_LEDC_STA1_CTRL(7) |
3321 PHY_M_LEDC_STA0_CTRL(7))
3322 : 0);
3323
3324 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3325 break;
3326
3327 default:
3328 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3329 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3330 on ? PHY_M_LED_ALL : 0);
793b883e 3331 }
cd28ab6a
SH		 3332}
3333
3334/* blink LED's for finding board */
3335static int sky2_phys_id(struct net_device *dev, u32 data)
3336{
3337 struct sky2_port *sky2 = netdev_priv(dev);
3338 struct sky2_hw *hw = sky2->hw;
3339 unsigned port = sky2->port;
793b883e 3340 u16 ledctrl, ledover = 0;
cd28ab6a 3341 long ms;
91c86df5 3342 int interrupted;
cd28ab6a
SH		 3343 int onoff = 1;
3344
793b883e 3345 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3346 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3347 else
3348 ms = data * 1000;
3349
3350 /* save initial values */
e07b1aa8 3351 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3352 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3353 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3354 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3355 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3356 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3357 } else {
3358 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3359 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3360 }
cd28ab6a 3361
91c86df5
SH		 3362 interrupted = 0;
3363 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3364 sky2_led(hw, port, onoff);
3365 onoff = !onoff;
3366
e07b1aa8 3367 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3368 interrupted = msleep_interruptible(250);
e07b1aa8 3369 spin_lock_bh(&sky2->phy_lock);
91c86df5 3370
cd28ab6a
SH		 3371 ms -= 250;
3372 }
3373
3374 /* resume regularly scheduled programming */
793b883e
SH		 3375 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3376 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3377 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3378 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3379 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3380 } else {
3381 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3382 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3383 }
e07b1aa8 3384 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3385
3386 return 0;
3387}
3388
3389static void sky2_get_pauseparam(struct net_device *dev,
3390 struct ethtool_pauseparam *ecmd)
3391{
3392 struct sky2_port *sky2 = netdev_priv(dev);
3393
16ad91e1
SH		 3394 switch (sky2->flow_mode) {
3395 case FC_NONE:
3396 ecmd->tx_pause = ecmd->rx_pause = 0;
3397 break;
3398 case FC_TX:
3399 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3400 break;
3401 case FC_RX:
3402 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3403 break;
3404 case FC_BOTH:
3405 ecmd->tx_pause = ecmd->rx_pause = 1;
3406 }
3407
cd28ab6a
SH		 3408 ecmd->autoneg = sky2->autoneg;
3409}
3410
3411static int sky2_set_pauseparam(struct net_device *dev,
3412 struct ethtool_pauseparam *ecmd)
3413{
3414 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3415
3416 sky2->autoneg = ecmd->autoneg;
16ad91e1 3417 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3418
16ad91e1
SH		 3419 if (netif_running(dev))
3420 sky2_phy_reinit(sky2);
cd28ab6a 3421
2eaba1a2 3422 return 0;
cd28ab6a
SH		 3423}
3424
fb17358f
SH		 3425static int sky2_get_coalesce(struct net_device *dev,
3426 struct ethtool_coalesce *ecmd)
3427{
3428 struct sky2_port *sky2 = netdev_priv(dev);
3429 struct sky2_hw *hw = sky2->hw;
3430
3431 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3432 ecmd->tx_coalesce_usecs = 0;
3433 else {
3434 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3435 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3436 }
3437 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3438
3439 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3440 ecmd->rx_coalesce_usecs = 0;
3441 else {
3442 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3443 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3444 }
3445 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3446
3447 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3448 ecmd->rx_coalesce_usecs_irq = 0;
3449 else {
3450 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3451 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3452 }
3453
3454 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3455
3456 return 0;
3457}
3458
3459/* Note: this affect both ports */
3460static int sky2_set_coalesce(struct net_device *dev,
3461 struct ethtool_coalesce *ecmd)
3462{
3463 struct sky2_port *sky2 = netdev_priv(dev);
3464 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3465 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3466
77b3d6a2
SH		 3467 if (ecmd->tx_coalesce_usecs > tmax ||
3468 ecmd->rx_coalesce_usecs > tmax ||
3469 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3470 return -EINVAL;
3471
ff81fbbe 3472 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3473 return -EINVAL;
ff81fbbe 3474 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3475 return -EINVAL;
ff81fbbe 3476 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3477 return -EINVAL;
3478
3479 if (ecmd->tx_coalesce_usecs == 0)
3480 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3481 else {
3482 sky2_write32(hw, STAT_TX_TIMER_INI,
3483 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3484 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3485 }
3486 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3487
3488 if (ecmd->rx_coalesce_usecs == 0)
3489 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3490 else {
3491 sky2_write32(hw, STAT_LEV_TIMER_INI,
3492 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3493 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3494 }
3495 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3496
3497 if (ecmd->rx_coalesce_usecs_irq == 0)
3498 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3499 else {
d28d4870 3500 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3501 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3502 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3503 }
3504 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3505 return 0;
3506}
3507
793b883e
SH		 3508static void sky2_get_ringparam(struct net_device *dev,
3509 struct ethtool_ringparam *ering)
3510{
3511 struct sky2_port *sky2 = netdev_priv(dev);
3512
3513 ering->rx_max_pending = RX_MAX_PENDING;
3514 ering->rx_mini_max_pending = 0;
3515 ering->rx_jumbo_max_pending = 0;
3516 ering->tx_max_pending = TX_RING_SIZE - 1;
3517
3518 ering->rx_pending = sky2->rx_pending;
3519 ering->rx_mini_pending = 0;
3520 ering->rx_jumbo_pending = 0;
3521 ering->tx_pending = sky2->tx_pending;
3522}
3523
3524static int sky2_set_ringparam(struct net_device *dev,
3525 struct ethtool_ringparam *ering)
3526{
3527 struct sky2_port *sky2 = netdev_priv(dev);
3528 int err = 0;
3529
3530 if (ering->rx_pending > RX_MAX_PENDING ||
3531 ering->rx_pending < 8 ||
3532 ering->tx_pending < MAX_SKB_TX_LE ||
3533 ering->tx_pending > TX_RING_SIZE - 1)
3534 return -EINVAL;
3535
3536 if (netif_running(dev))
3537 sky2_down(dev);
3538
3539 sky2->rx_pending = ering->rx_pending;
3540 sky2->tx_pending = ering->tx_pending;
3541
1b537565 3542 if (netif_running(dev)) {
793b883e 3543 err = sky2_up(dev);
1b537565
SH		 3544 if (err)
3545 dev_close(dev);
6ed995bb
SH		 3546 else
3547 sky2_set_multicast(dev);
1b537565 3548 }
793b883e
SH		 3549
3550 return err;
3551}
3552
793b883e
SH		 3553static int sky2_get_regs_len(struct net_device *dev)
3554{
6e4cbb34 3555 return 0x4000;
793b883e
SH		 3556}
3557
3558/*
3559 * Returns copy of control register region
3ead5db7 3560 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3561 */
3562static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3563 void *p)
3564{
3565 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3566 const void __iomem *io = sky2->hw->regs;
793b883e
SH		 3567
3568 regs->version = 1;
6e4cbb34 3569 memset(p, 0, regs->len);
793b883e 3570
6e4cbb34
SH		 3571 memcpy_fromio(p, io, B3_RAM_ADDR);
3572
3ead5db7
SH		 3573 /* skip diagnostic ram region */
3574 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 0x2000 - B3_RI_WTO_R1);
3575
3576 /* copy GMAC registers */
3577 memcpy_fromio(p + BASE_GMAC_1, io + BASE_GMAC_1, 0x1000);
3578 if (sky2->hw->ports > 1)
3579 memcpy_fromio(p + BASE_GMAC_2, io + BASE_GMAC_2, 0x1000);
3580
793b883e 3581}
cd28ab6a 3582
b628ed98
SH		 3583/* In order to do Jumbo packets on these chips, need to turn off the
3584 * transmit store/forward. Therefore checksum offload won't work.
3585 */
3586static int no_tx_offload(struct net_device *dev)
3587{
3588 const struct sky2_port *sky2 = netdev_priv(dev);
3589 const struct sky2_hw *hw = sky2->hw;
3590
69161611 3591 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3592}
3593
3594static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3595{
3596 if (data && no_tx_offload(dev))
3597 return -EINVAL;
3598
3599 return ethtool_op_set_tx_csum(dev, data);
3600}
3601
3602
3603static int sky2_set_tso(struct net_device *dev, u32 data)
3604{
3605 if (data && no_tx_offload(dev))
3606 return -EINVAL;
3607
3608 return ethtool_op_set_tso(dev, data);
3609}
3610
f4331a6d
SH		 3611static int sky2_get_eeprom_len(struct net_device *dev)
3612{
3613 struct sky2_port *sky2 = netdev_priv(dev);
3614 u16 reg2;
3615
3616 reg2 = sky2_pci_read32(sky2->hw, PCI_DEV_REG2);
3617 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3618}
3619
3620static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3621{
3622 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3623
3624 while (!(sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F))
3625 cpu_relax();
3626 return sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3627}
3628
3629static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3630{
3631 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3632 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3633 do {
3634 cpu_relax();
3635 } while (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F);
3636}
3637
3638static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3639 u8 *data)
3640{
3641 struct sky2_port *sky2 = netdev_priv(dev);
3642 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3643 int length = eeprom->len;
3644 u16 offset = eeprom->offset;
3645
3646 if (!cap)
3647 return -EINVAL;
3648
3649 eeprom->magic = SKY2_EEPROM_MAGIC;
3650
3651 while (length > 0) {
3652 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3653 int n = min_t(int, length, sizeof(val));
3654
3655 memcpy(data, &val, n);
3656 length -= n;
3657 data += n;
3658 offset += n;
3659 }
3660 return 0;
3661}
3662
3663static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3664 u8 *data)
3665{
3666 struct sky2_port *sky2 = netdev_priv(dev);
3667 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3668 int length = eeprom->len;
3669 u16 offset = eeprom->offset;
3670
3671 if (!cap)
3672 return -EINVAL;
3673
3674 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3675 return -EINVAL;
3676
3677 while (length > 0) {
3678 u32 val;
3679 int n = min_t(int, length, sizeof(val));
3680
3681 if (n < sizeof(val))
3682 val = sky2_vpd_read(sky2->hw, cap, offset);
3683 memcpy(&val, data, n);
3684
3685 sky2_vpd_write(sky2->hw, cap, offset, val);
3686
3687 length -= n;
3688 data += n;
3689 offset += n;
3690 }
3691 return 0;
3692}
3693
3694
7282d491 3695static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3696 .get_settings = sky2_get_settings,
3697 .set_settings = sky2_set_settings,
3698 .get_drvinfo = sky2_get_drvinfo,
3699 .get_wol = sky2_get_wol,
3700 .set_wol = sky2_set_wol,
3701 .get_msglevel = sky2_get_msglevel,
3702 .set_msglevel = sky2_set_msglevel,
3703 .nway_reset = sky2_nway_reset,
3704 .get_regs_len = sky2_get_regs_len,
3705 .get_regs = sky2_get_regs,
3706 .get_link = ethtool_op_get_link,
3707 .get_eeprom_len = sky2_get_eeprom_len,
3708 .get_eeprom = sky2_get_eeprom,
3709 .set_eeprom = sky2_set_eeprom,
3710 .get_sg = ethtool_op_get_sg,
3711 .set_sg = ethtool_op_set_sg,
3712 .get_tx_csum = ethtool_op_get_tx_csum,
3713 .set_tx_csum = sky2_set_tx_csum,
3714 .get_tso = ethtool_op_get_tso,
3715 .set_tso = sky2_set_tso,
3716 .get_rx_csum = sky2_get_rx_csum,
3717 .set_rx_csum = sky2_set_rx_csum,
3718 .get_strings = sky2_get_strings,
3719 .get_coalesce = sky2_get_coalesce,
3720 .set_coalesce = sky2_set_coalesce,
3721 .get_ringparam = sky2_get_ringparam,
3722 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3723 .get_pauseparam = sky2_get_pauseparam,
3724 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3725 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3726 .get_stats_count = sky2_get_stats_count,
3727 .get_ethtool_stats = sky2_get_ethtool_stats,
3728};
3729
3cf26753
SH		 3730#ifdef CONFIG_SKY2_DEBUG
3731
3732static struct dentry *sky2_debug;
3733
3734static int sky2_debug_show(struct seq_file *seq, void *v)
3735{
3736 struct net_device *dev = seq->private;
3737 const struct sky2_port *sky2 = netdev_priv(dev);
3738 const struct sky2_hw *hw = sky2->hw;
3739 unsigned port = sky2->port;
3740 unsigned idx, last;
3741 int sop;
3742
3743 if (!netif_running(dev))
3744 return -ENETDOWN;
3745
3746 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3747 sky2_read32(hw, B0_ISRC),
3748 sky2_read32(hw, B0_IMSK),
3749 sky2_read32(hw, B0_Y2_SP_ICR));
3750
3751 netif_poll_disable(hw->dev[0]);
3752 last = sky2_read16(hw, STAT_PUT_IDX);
3753
3754 if (hw->st_idx == last)
3755 seq_puts(seq, "Status ring (empty)\n");
3756 else {
3757 seq_puts(seq, "Status ring\n");
3758 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3759 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3760 const struct sky2_status_le *le = hw->st_le + idx;
3761 seq_printf(seq, "[%d] %#x %d %#x\n",
3762 idx, le->opcode, le->length, le->status);
3763 }
3764 seq_puts(seq, "\n");
3765 }
3766
3767 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3768 sky2->tx_cons, sky2->tx_prod,
3769 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3770 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3771
3772 /* Dump contents of tx ring */
3773 sop = 1;
3774 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3775 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3776 const struct sky2_tx_le *le = sky2->tx_le + idx;
3777 u32 a = le32_to_cpu(le->addr);
3778
3779 if (sop)
3780 seq_printf(seq, "%u:", idx);
3781 sop = 0;
3782
3783 switch(le->opcode & ~HW_OWNER) {
3784 case OP_ADDR64:
3785 seq_printf(seq, " %#x:", a);
3786 break;
3787 case OP_LRGLEN:
3788 seq_printf(seq, " mtu=%d", a);
3789 break;
3790 case OP_VLAN:
3791 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3792 break;
3793 case OP_TCPLISW:
3794 seq_printf(seq, " csum=%#x", a);
3795 break;
3796 case OP_LARGESEND:
3797 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3798 break;
3799 case OP_PACKET:
3800 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3801 break;
3802 case OP_BUFFER:
3803 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3804 break;
3805 default:
3806 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3807 a, le16_to_cpu(le->length));
3808 }
3809
3810 if (le->ctrl & EOP) {
3811 seq_putc(seq, '\n');
3812 sop = 1;
3813 }
3814 }
3815
3816 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3817 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3818 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3819 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3820
3821 netif_poll_enable(hw->dev[0]);
3822 return 0;
3823}
3824
3825static int sky2_debug_open(struct inode *inode, struct file *file)
3826{
3827 return single_open(file, sky2_debug_show, inode->i_private);
3828}
3829
3830static const struct file_operations sky2_debug_fops = {
3831 .owner = THIS_MODULE,
3832 .open = sky2_debug_open,
3833 .read = seq_read,
3834 .llseek = seq_lseek,
3835 .release = single_release,
3836};
3837
3838/*
3839 * Use network device events to create/remove/rename
3840 * debugfs file entries
3841 */
3842static int sky2_device_event(struct notifier_block *unused,
3843 unsigned long event, void *ptr)
3844{
3845 struct net_device *dev = ptr;
3846
3847 if (dev->open == sky2_up) {
3848 struct sky2_port *sky2 = netdev_priv(dev);
3849
3850 switch(event) {
3851 case NETDEV_CHANGENAME:
3852 if (!netif_running(dev))
3853 break;
3854 /* fallthrough */
3855 case NETDEV_DOWN:
3856 case NETDEV_GOING_DOWN:
3857 if (sky2->debugfs) {
3858 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3859 dev->name);
3860 debugfs_remove(sky2->debugfs);
3861 sky2->debugfs = NULL;
3862 }
3863
3864 if (event != NETDEV_CHANGENAME)
3865 break;
3866 /* fallthrough for changename */
3867 case NETDEV_UP:
3868 if (sky2_debug) {
3869 struct dentry *d;
3870 d = debugfs_create_file(dev->name, S_IRUGO,
3871 sky2_debug, dev,
3872 &sky2_debug_fops);
3873 if (d == NULL || IS_ERR(d))
3874 printk(KERN_INFO PFX
3875 "%s: debugfs create failed\n",
3876 dev->name);
3877 else
3878 sky2->debugfs = d;
3879 }
3880 break;
3881 }
3882 }
3883
3884 return NOTIFY_DONE;
3885}
3886
3887static struct notifier_block sky2_notifier = {
3888 .notifier_call = sky2_device_event,
3889};
3890
3891
3892static __init void sky2_debug_init(void)
3893{
3894 struct dentry *ent;
3895
3896 ent = debugfs_create_dir("sky2", NULL);
3897 if (!ent || IS_ERR(ent))
3898 return;
3899
3900 sky2_debug = ent;
3901 register_netdevice_notifier(&sky2_notifier);
3902}
3903
3904static __exit void sky2_debug_cleanup(void)
3905{
3906 if (sky2_debug) {
3907 unregister_netdevice_notifier(&sky2_notifier);
3908 debugfs_remove(sky2_debug);
3909 sky2_debug = NULL;
3910 }
3911}
3912
3913#else
3914#define sky2_debug_init()
3915#define sky2_debug_cleanup()
3916#endif
3917
3918
cd28ab6a
SH		 3919/* Initialize network device */
3920static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3921 unsigned port,
3922 int highmem, int wol)
cd28ab6a
SH		 3923{
3924 struct sky2_port *sky2;
3925 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3926
3927 if (!dev) {
b02a9258 3928 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3929 return NULL;
3930 }
3931
3932 SET_MODULE_OWNER(dev);
3933 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3934 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3935 dev->open = sky2_up;
3936 dev->stop = sky2_down;
ef743d33 3937 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3938 dev->hard_start_xmit = sky2_xmit_frame;
3939 dev->get_stats = sky2_get_stats;
3940 dev->set_multicast_list = sky2_set_multicast;
3941 dev->set_mac_address = sky2_set_mac_address;
3942 dev->change_mtu = sky2_change_mtu;
3943 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3944 dev->tx_timeout = sky2_tx_timeout;
3945 dev->watchdog_timeo = TX_WATCHDOG;
3946 if (port == 0)
3947 dev->poll = sky2_poll;
3948 dev->weight = NAPI_WEIGHT;
3949#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3950 /* Network console (only works on port 0)
3951 * because netpoll makes assumptions about NAPI
3952 */
3953 if (port == 0)
3954 dev->poll_controller = sky2_netpoll;
cd28ab6a 3955#endif
cd28ab6a
SH		 3956
3957 sky2 = netdev_priv(dev);
3958 sky2->netdev = dev;
3959 sky2->hw = hw;
3960 sky2->msg_enable = netif_msg_init(debug, default_msg);
3961
cd28ab6a
SH		 3962 /* Auto speed and flow control */
3963 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3964 sky2->flow_mode = FC_BOTH;
3965
cd28ab6a
SH		 3966 sky2->duplex = -1;
3967 sky2->speed = -1;
3968 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3969 sky2->rx_csum = 1;
e3173832 3970 sky2->wol = wol;
75d070c5 3971
e07b1aa8 3972 spin_lock_init(&sky2->phy_lock);
793b883e 3973 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3974 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3975
3976 hw->dev[port] = dev;
3977
3978 sky2->port = port;
3979
4a50a876 3980 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3981 if (highmem)
3982 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3983
d1f13708 3984#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 3985 /* The workaround for FE+ status conflicts with VLAN tag detection. */
3986 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
3987 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
3988 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3989 dev->vlan_rx_register = sky2_vlan_rx_register;
3990 }
d1f13708 3991#endif
3992
cd28ab6a 3993 /* read the mac address */
793b883e 3994 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3995 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 3996
cd28ab6a
SH		 3997 return dev;
3998}
3999
28bd181a 4000static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4001{
4002 const struct sky2_port *sky2 = netdev_priv(dev);
4003
4004 if (netif_msg_probe(sky2))
4005 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
4006 dev->name,
4007 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4008 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4009}
4010
fb2690a9 4011/* Handle software interrupt used during MSI test */
7d12e780 4012static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4013{
4014 struct sky2_hw *hw = dev_id;
4015 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4016
4017 if (status == 0)
4018 return IRQ_NONE;
4019
4020 if (status & Y2_IS_IRQ_SW) {
ea76e635 4021 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4022 wake_up(&hw->msi_wait);
4023 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4024 }
4025 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4026
4027 return IRQ_HANDLED;
4028}
4029
4030/* Test interrupt path by forcing a a software IRQ */
4031static int __devinit sky2_test_msi(struct sky2_hw *hw)
4032{
4033 struct pci_dev *pdev = hw->pdev;
4034 int err;
4035
bb507fe1 4036 init_waitqueue_head (&hw->msi_wait);
4037
fb2690a9
SH		 4038 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4039
b0a20ded 4040 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4041 if (err) {
b02a9258 4042 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4043 return err;
4044 }
4045
fb2690a9 4046 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4047 sky2_read8(hw, B0_CTST);
fb2690a9 4048
ea76e635 4049 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4050
ea76e635 4051 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4052 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4053 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4054 "switching to INTx mode.\n");
fb2690a9
SH		 4055
4056 err = -EOPNOTSUPP;
4057 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4058 }
4059
4060 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4061 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4062
4063 free_irq(pdev->irq, hw);
4064
4065 return err;
4066}
4067
e3173832
SH		 4068static int __devinit pci_wake_enabled(struct pci_dev *dev)
4069{
4070 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4071 u16 value;
4072
4073 if (!pm)
4074 return 0;
4075 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4076 return 0;
4077 return value & PCI_PM_CTRL_PME_ENABLE;
4078}
4079
cd28ab6a
SH		 4080static int __devinit sky2_probe(struct pci_dev *pdev,
4081 const struct pci_device_id *ent)
4082{
7f60c64b 4083 struct net_device *dev;
cd28ab6a 4084 struct sky2_hw *hw;
e3173832 4085 int err, using_dac = 0, wol_default;
cd28ab6a 4086
793b883e
SH		 4087 err = pci_enable_device(pdev);
4088 if (err) {
b02a9258 4089 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4090 goto err_out;
4091 }
4092
793b883e
SH		 4093 err = pci_request_regions(pdev, DRV_NAME);
4094 if (err) {
b02a9258 4095 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4096 goto err_out_disable;
cd28ab6a
SH		 4097 }
4098
4099 pci_set_master(pdev);
4100
d1f3d4dd
SH		 4101 if (sizeof(dma_addr_t) > sizeof(u32) &&
4102 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4103 using_dac = 1;
4104 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4105 if (err < 0) {
b02a9258
SH		 4106 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4107 "for consistent allocations\n");
d1f3d4dd
SH		 4108 goto err_out_free_regions;
4109 }
d1f3d4dd 4110 } else {
cd28ab6a
SH		 4111 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4112 if (err) {
b02a9258 4113 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4114 goto err_out_free_regions;
4115 }
4116 }
d1f3d4dd 4117
e3173832
SH		 4118 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4119
cd28ab6a 4120 err = -ENOMEM;
6aad85d6 4121 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4122 if (!hw) {
b02a9258 4123 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4124 goto err_out_free_regions;
4125 }
4126
cd28ab6a 4127 hw->pdev = pdev;
cd28ab6a
SH		 4128
4129 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4130 if (!hw->regs) {
b02a9258 4131 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4132 goto err_out_free_hw;
4133 }
4134
56a645cc 4135#ifdef __BIG_ENDIAN
f65b138c
SH		 4136 /* The sk98lin vendor driver uses hardware byte swapping but
4137 * this driver uses software swapping.
4138 */
56a645cc
SH		 4139 {
4140 u32 reg;
56a645cc 4141 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 4142 reg &= ~PCI_REV_DESC;
56a645cc
SH		 4143 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
4144 }
4145#endif
4146
08c06d8a
SH		 4147 /* ring for status responses */
4148 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
4149 &hw->st_dma);
4150 if (!hw->st_le)
4151 goto err_out_iounmap;
4152
e3173832 4153 err = sky2_init(hw);
cd28ab6a 4154 if (err)
793b883e 4155 goto err_out_iounmap;
cd28ab6a 4156
b02a9258 4157 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 4158 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4159 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 4160 hw->chip_id, hw->chip_rev);
cd28ab6a 4161
e3173832
SH		 4162 sky2_reset(hw);
4163
4164 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4165 if (!dev) {
4166 err = -ENOMEM;
cd28ab6a 4167 goto err_out_free_pci;
7f60c64b 4168 }
cd28ab6a 4169
9fa1b1f3
SH		 4170 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4171 err = sky2_test_msi(hw);
4172 if (err == -EOPNOTSUPP)
4173 pci_disable_msi(pdev);
4174 else if (err)
4175 goto err_out_free_netdev;
4176 }
4177
793b883e
SH		 4178 err = register_netdev(dev);
4179 if (err) {
b02a9258 4180 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4181 goto err_out_free_netdev;
4182 }
4183
ea76e635
SH		 4184 err = request_irq(pdev->irq, sky2_intr,
4185 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4186 dev->name, hw);
9fa1b1f3 4187 if (err) {
b02a9258 4188 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4189 goto err_out_unregister;
4190 }
4191 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4192
cd28ab6a
SH		 4193 sky2_show_addr(dev);
4194
7f60c64b 4195 if (hw->ports > 1) {
4196 struct net_device *dev1;
4197
e3173832 4198 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4199 if (!dev1)
4200 dev_warn(&pdev->dev, "allocation for second device failed\n");
4201 else if ((err = register_netdev(dev1))) {
4202 dev_warn(&pdev->dev,
4203 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4204 hw->dev[1] = NULL;
4205 free_netdev(dev1);
b02a9258
SH		 4206 } else
4207 sky2_show_addr(dev1);
cd28ab6a
SH		 4208 }
4209
32c2c300 4210 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4211 INIT_WORK(&hw->restart_work, sky2_restart);
4212
793b883e
SH		 4213 pci_set_drvdata(pdev, hw);
4214
cd28ab6a
SH		 4215 return 0;
4216
793b883e 4217err_out_unregister:
ea76e635 4218 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4219 pci_disable_msi(pdev);
793b883e 4220 unregister_netdev(dev);
cd28ab6a
SH		 4221err_out_free_netdev:
4222 free_netdev(dev);
cd28ab6a 4223err_out_free_pci:
793b883e 4224 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 4225 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4226err_out_iounmap:
4227 iounmap(hw->regs);
4228err_out_free_hw:
4229 kfree(hw);
4230err_out_free_regions:
4231 pci_release_regions(pdev);
44a1d2e5 4232err_out_disable:
cd28ab6a 4233 pci_disable_device(pdev);
cd28ab6a 4234err_out:
549a68c3 4235 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4236 return err;
4237}
4238
4239static void __devexit sky2_remove(struct pci_dev *pdev)
4240{
793b883e 4241 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 4242 struct net_device *dev0, *dev1;
4243
793b883e 4244 if (!hw)
cd28ab6a
SH		 4245 return;
4246
32c2c300 4247 del_timer_sync(&hw->watchdog_timer);
d27ed387 4248
81906791
SH		 4249 flush_scheduled_work();
4250
d27ed387 4251 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 4252 synchronize_irq(hw->pdev->irq);
4253
cd28ab6a 4254 dev0 = hw->dev[0];
793b883e
SH		 4255 dev1 = hw->dev[1];
4256 if (dev1)
4257 unregister_netdev(dev1);
cd28ab6a
SH		 4258 unregister_netdev(dev0);
4259
ae306cca
SH		 4260 sky2_power_aux(hw);
4261
cd28ab6a 4262 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4263 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4264 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4265
4266 free_irq(pdev->irq, hw);
ea76e635 4267 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4268 pci_disable_msi(pdev);
793b883e 4269 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4270 pci_release_regions(pdev);
4271 pci_disable_device(pdev);
793b883e 4272
cd28ab6a
SH		 4273 if (dev1)
4274 free_netdev(dev1);
4275 free_netdev(dev0);
4276 iounmap(hw->regs);
4277 kfree(hw);
5afa0a9c 4278
cd28ab6a
SH		 4279 pci_set_drvdata(pdev, NULL);
4280}
4281
4282#ifdef CONFIG_PM
4283static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4284{
793b883e 4285 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4286 int i, wol = 0;
cd28ab6a 4287
549a68c3
SH		 4288 if (!hw)
4289 return 0;
4290
6a5706b9 4291 netif_poll_disable(hw->dev[0]);
eb35cf60 4292
f05267e7 4293 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4294 struct net_device *dev = hw->dev[i];
e3173832 4295 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4296
e3173832 4297 if (netif_running(dev))
5afa0a9c 4298 sky2_down(dev);
e3173832
SH		 4299
4300 if (sky2->wol)
4301 sky2_wol_init(sky2);
4302
4303 wol |= sky2->wol;
cd28ab6a
SH		 4304 }
4305
8ab8fca2 4306 sky2_write32(hw, B0_IMSK, 0);
ae306cca 4307 sky2_power_aux(hw);
e3173832 4308
d374c1c1 4309 pci_save_state(pdev);
e3173832 4310 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 4311 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4312
2ccc99b7 4313 return 0;
cd28ab6a
SH		 4314}
4315
4316static int sky2_resume(struct pci_dev *pdev)
4317{
793b883e 4318 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4319 int i, err;
cd28ab6a 4320
549a68c3
SH		 4321 if (!hw)
4322 return 0;
4323
ae306cca
SH		 4324 err = pci_set_power_state(pdev, PCI_D0);
4325 if (err)
4326 goto out;
4327
4328 err = pci_restore_state(pdev);
4329 if (err)
4330 goto out;
4331
cd28ab6a 4332 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4333
4334 /* Re-enable all clocks */
05745c4a
SH		 4335 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4336 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4337 hw->chip_id == CHIP_ID_YUKON_FE_P)
1ad5b4a5
SH		 4338 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4339
e3173832 4340 sky2_reset(hw);
cd28ab6a 4341
8ab8fca2
SH		 4342 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4343
f05267e7 4344 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4345 struct net_device *dev = hw->dev[i];
6a5706b9 4346 if (netif_running(dev)) {
08c06d8a
SH		 4347 err = sky2_up(dev);
4348 if (err) {
4349 printk(KERN_ERR PFX "%s: could not up: %d\n",
4350 dev->name, err);
4351 dev_close(dev);
eb35cf60 4352 goto out;
5afa0a9c 4353 }
d1b139c0
SH		 4354
4355 sky2_set_multicast(dev);
cd28ab6a
SH		 4356 }
4357 }
eb35cf60 4358
6a5706b9 4359 netif_poll_enable(hw->dev[0]);
32c2c300 4360
ae306cca 4361 return 0;
08c06d8a 4362out:
b02a9258 4363 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4364 pci_disable_device(pdev);
08c06d8a 4365 return err;
cd28ab6a
SH		 4366}
4367#endif
4368
e3173832
SH		 4369static void sky2_shutdown(struct pci_dev *pdev)
4370{
4371 struct sky2_hw *hw = pci_get_drvdata(pdev);
4372 int i, wol = 0;
4373
549a68c3
SH		 4374 if (!hw)
4375 return;
4376
e3173832
SH		 4377 netif_poll_disable(hw->dev[0]);
4378
4379 for (i = 0; i < hw->ports; i++) {
4380 struct net_device *dev = hw->dev[i];
4381 struct sky2_port *sky2 = netdev_priv(dev);
4382
4383 if (sky2->wol) {
4384 wol = 1;
4385 sky2_wol_init(sky2);
4386 }
4387 }
4388
4389 if (wol)
4390 sky2_power_aux(hw);
4391
4392 pci_enable_wake(pdev, PCI_D3hot, wol);
4393 pci_enable_wake(pdev, PCI_D3cold, wol);
4394
4395 pci_disable_device(pdev);
4396 pci_set_power_state(pdev, PCI_D3hot);
4397
4398}
4399
cd28ab6a 4400static struct pci_driver sky2_driver = {
793b883e
SH		 4401 .name = DRV_NAME,
4402 .id_table = sky2_id_table,
4403 .probe = sky2_probe,
4404 .remove = __devexit_p(sky2_remove),
cd28ab6a 4405#ifdef CONFIG_PM
793b883e
SH		 4406 .suspend = sky2_suspend,
4407 .resume = sky2_resume,
cd28ab6a 4408#endif
e3173832 4409 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4410};
4411
4412static int __init sky2_init_module(void)
4413{
3cf26753 4414 sky2_debug_init();
50241c4c 4415 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4416}
4417
4418static void __exit sky2_cleanup_module(void)
4419{
4420 pci_unregister_driver(&sky2_driver);
3cf26753 4421 sky2_debug_cleanup();
cd28ab6a
SH		 4422}
4423
4424module_init(sky2_init_module);
4425module_exit(sky2_cleanup_module);
4426
4427MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4428MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4429MODULE_LICENSE("GPL");
5f4f9dc1 4430MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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