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fix unaligned exception in /drivers/net/wireless/orinoco.c
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
ef743d33 41#include <linux/mii.h>
cd28ab6a
SH		 42
43#include <asm/irq.h>
44
d1f13708 45#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
46#define SKY2_VLAN_TAG_USED 1
47#endif
48
cd28ab6a
SH		 49#include "sky2.h"
50
51#define DRV_NAME "sky2"
285e6ddd 52#define DRV_VERSION "1.11.1"
cd28ab6a
SH		 53#define PFX DRV_NAME " "
54
55/*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
14d0263f 58 * similar to Tigon3.
cd28ab6a
SH		 59 */
60
14d0263f 61#define RX_LE_SIZE 1024
cd28ab6a 62#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 63#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 64#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 65#define RX_SKB_ALIGN 8
22e11703 66#define RX_BUF_WRITE 16
793b883e
SH		 67
68#define TX_RING_SIZE 512
69#define TX_DEF_PENDING (TX_RING_SIZE - 1)
70#define TX_MIN_PENDING 64
b19666d9 71#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 72
793b883e 73#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 74#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 75#define TX_WATCHDOG (5 * HZ)
76#define NAPI_WEIGHT 64
77#define PHY_RETRIES 1000
78
cb5d9547
SH		 79#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
80
cd28ab6a 81static const u32 default_msg =
793b883e
SH		 82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 85
793b883e 86static int debug = -1; /* defaults above */
cd28ab6a
SH		 87module_param(debug, int, 0);
88MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
14d0263f 90static int copybreak __read_mostly = 128;
bdb5c58e
SH		 91module_param(copybreak, int, 0);
92MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
fb2690a9
SH		 94static int disable_msi = 0;
95module_param(disable_msi, int, 0);
96MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
e561a83b 98static int idle_timeout = 0;
01bd7564 99module_param(idle_timeout, int, 0);
e561a83b 100MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 101
cd28ab6a 102static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
e5b74c7d
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
cd28ab6a
SH		 129 { 0 }
130};
793b883e 131
cd28ab6a
SH		 132MODULE_DEVICE_TABLE(pci, sky2_id_table);
133
134/* Avoid conditionals by using array */
135static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
136static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 137static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 138
92f965e8
SH		 139/* This driver supports yukon2 chipset only */
140static const char *yukon2_name[] = {
141 "XL", /* 0xb3 */
142 "EC Ultra", /* 0xb4 */
143 "UNKNOWN", /* 0xb5 */
144 "EC", /* 0xb6 */
145 "FE", /* 0xb7 */
793b883e
SH		 146};
147
793b883e 148/* Access to external PHY */
ef743d33 149static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 150{
151 int i;
152
153 gma_write16(hw, port, GM_SMI_DATA, val);
154 gma_write16(hw, port, GM_SMI_CTRL,
155 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
156
157 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 158 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 159 return 0;
793b883e 160 udelay(1);
cd28ab6a 161 }
ef743d33 162
793b883e 163 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 164 return -ETIMEDOUT;
cd28ab6a
SH		 165}
166
ef743d33 167static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 168{
169 int i;
170
793b883e 171 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 172 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
173
174 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33 175 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
176 *val = gma_read16(hw, port, GM_SMI_DATA);
177 return 0;
178 }
179
793b883e 180 udelay(1);
cd28ab6a
SH		 181 }
182
ef743d33 183 return -ETIMEDOUT;
184}
185
186static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
187{
188 u16 v;
189
190 if (__gm_phy_read(hw, port, reg, &v) != 0)
191 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
192 return v;
cd28ab6a
SH		 193}
194
5afa0a9c 195
ae306cca
SH		 196static void sky2_power_on(struct sky2_hw *hw)
197{
198 /* switch power to VCC (WA for VAUX problem) */
199 sky2_write8(hw, B0_POWER_CTRL,
200 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 201
ae306cca
SH		 202 /* disable Core Clock Division, */
203 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 204
ae306cca
SH		 205 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
206 /* enable bits are inverted */
207 sky2_write8(hw, B2_Y2_CLK_GATE,
208 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
209 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
210 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
211 else
212 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 213
ae306cca
SH		 214 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
215 u32 reg1;
5afa0a9c 216
ae306cca
SH		 217 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
218 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
219 reg1 &= P_ASPM_CONTROL_MSK;
220 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
221 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
5afa0a9c 222 }
ae306cca 223}
5afa0a9c 224
ae306cca
SH		 225static void sky2_power_aux(struct sky2_hw *hw)
226{
227 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
228 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
229 else
230 /* enable bits are inverted */
231 sky2_write8(hw, B2_Y2_CLK_GATE,
232 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
233 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
234 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
235
236 /* switch power to VAUX */
237 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
238 sky2_write8(hw, B0_POWER_CTRL,
239 (PC_VAUX_ENA | PC_VCC_ENA |
240 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c 241}
242
d3bcfbeb 243static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 244{
245 u16 reg;
246
247 /* disable all GMAC IRQ's */
248 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
249 /* disable PHY IRQs */
250 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 251
cd28ab6a
SH		 252 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
253 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
254 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
255 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
256
257 reg = gma_read16(hw, port, GM_RX_CTRL);
258 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
259 gma_write16(hw, port, GM_RX_CTRL, reg);
260}
261
16ad91e1
SH		 262/* flow control to advertise bits */
263static const u16 copper_fc_adv[] = {
264 [FC_NONE] = 0,
265 [FC_TX] = PHY_M_AN_ASP,
266 [FC_RX] = PHY_M_AN_PC,
267 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
268};
269
270/* flow control to advertise bits when using 1000BaseX */
271static const u16 fiber_fc_adv[] = {
272 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
273 [FC_TX] = PHY_M_P_ASYM_MD_X,
274 [FC_RX] = PHY_M_P_SYM_MD_X,
275 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
276};
277
278/* flow control to GMA disable bits */
279static const u16 gm_fc_disable[] = {
280 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
281 [FC_TX] = GM_GPCR_FC_RX_DIS,
282 [FC_RX] = GM_GPCR_FC_TX_DIS,
283 [FC_BOTH] = 0,
284};
285
286
cd28ab6a
SH		 287static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
288{
289 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 290 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 291
ed6d32c7 292 if (sky2->autoneg == AUTONEG_ENABLE &&
86a31a75 293 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 294 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
295
296 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 297 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 298 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
299
300 if (hw->chip_id == CHIP_ID_YUKON_EC)
301 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
302 else
303 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
304
305 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
306 }
307
308 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 309 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 310 if (hw->chip_id == CHIP_ID_YUKON_FE) {
311 /* enable automatic crossover */
312 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
313 } else {
314 /* disable energy detect */
315 ctrl &= ~PHY_M_PC_EN_DET_MSK;
316
317 /* enable automatic crossover */
318 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
319
320 if (sky2->autoneg == AUTONEG_ENABLE &&
ed6d32c7 321 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 322 ctrl &= ~PHY_M_PC_DSC_MSK;
323 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
324 }
325 }
cd28ab6a
SH		 326 } else {
327 /* workaround for deviation #4.88 (CRC errors) */
328 /* disable Automatic Crossover */
329
330 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 331 }
cd28ab6a 332
b89165f2
SH		 333 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
334
335 /* special setup for PHY 88E1112 Fiber */
336 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
337 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 338
b89165f2
SH		 339 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
340 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
341 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
342 ctrl &= ~PHY_M_MAC_MD_MSK;
343 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
344 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
345
346 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 347 /* select page 1 to access Fiber registers */
348 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 349
350 /* for SFP-module set SIGDET polarity to low */
351 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
352 ctrl |= PHY_M_FIB_SIGD_POL;
353 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
cd28ab6a 354 }
b89165f2
SH		 355
356 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 357 }
358
7800fddc 359 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 360 ct1000 = 0;
361 adv = PHY_AN_CSMA;
2eaba1a2 362 reg = 0;
cd28ab6a
SH		 363
364 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 365 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 366 if (sky2->advertising & ADVERTISED_1000baseT_Full)
367 ct1000 |= PHY_M_1000C_AFD;
368 if (sky2->advertising & ADVERTISED_1000baseT_Half)
369 ct1000 |= PHY_M_1000C_AHD;
370 if (sky2->advertising & ADVERTISED_100baseT_Full)
371 adv |= PHY_M_AN_100_FD;
372 if (sky2->advertising & ADVERTISED_100baseT_Half)
373 adv |= PHY_M_AN_100_HD;
374 if (sky2->advertising & ADVERTISED_10baseT_Full)
375 adv |= PHY_M_AN_10_FD;
376 if (sky2->advertising & ADVERTISED_10baseT_Half)
377 adv |= PHY_M_AN_10_HD;
709c6e7b 378
16ad91e1 379 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 380 } else { /* special defines for FIBER (88E1040S only) */
381 if (sky2->advertising & ADVERTISED_1000baseT_Full)
382 adv |= PHY_M_AN_1000X_AFD;
383 if (sky2->advertising & ADVERTISED_1000baseT_Half)
384 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 385
16ad91e1 386 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 387 }
cd28ab6a
SH		 388
389 /* Restart Auto-negotiation */
390 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
391 } else {
392 /* forced speed/duplex settings */
393 ct1000 = PHY_M_1000C_MSE;
394
2eaba1a2
SH		 395 /* Disable auto update for duplex flow control and speed */
396 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 397
398 switch (sky2->speed) {
399 case SPEED_1000:
400 ctrl |= PHY_CT_SP1000;
2eaba1a2 401 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 402 break;
403 case SPEED_100:
404 ctrl |= PHY_CT_SP100;
2eaba1a2 405 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 406 break;
407 }
408
2eaba1a2
SH		 409 if (sky2->duplex == DUPLEX_FULL) {
410 reg |= GM_GPCR_DUP_FULL;
411 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 412 } else if (sky2->speed < SPEED_1000)
413 sky2->flow_mode = FC_NONE;
2eaba1a2 414
2eaba1a2 415
16ad91e1 416 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 417
418 /* Forward pause packets to GMAC? */
16ad91e1 419 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 420 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
421 else
422 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 423 }
424
2eaba1a2
SH		 425 gma_write16(hw, port, GM_GP_CTRL, reg);
426
cd28ab6a
SH		 427 if (hw->chip_id != CHIP_ID_YUKON_FE)
428 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
429
430 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
431 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
432
433 /* Setup Phy LED's */
434 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
435 ledover = 0;
436
437 switch (hw->chip_id) {
438 case CHIP_ID_YUKON_FE:
439 /* on 88E3082 these bits are at 11..9 (shifted left) */
440 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
441
442 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
443
444 /* delete ACT LED control bits */
445 ctrl &= ~PHY_M_FELP_LED1_MSK;
446 /* change ACT LED control to blink mode */
447 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
448 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
449 break;
450
451 case CHIP_ID_YUKON_XL:
793b883e 452 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 453
454 /* select page 3 to access LED control register */
455 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
456
457 /* set LED Function Control register */
ed6d32c7
SH		 458 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
459 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
460 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
461 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
462 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 463
464 /* set Polarity Control register */
465 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 466 (PHY_M_POLC_LS1_P_MIX(4) |
467 PHY_M_POLC_IS0_P_MIX(4) |
468 PHY_M_POLC_LOS_CTRL(2) |
469 PHY_M_POLC_INIT_CTRL(2) |
470 PHY_M_POLC_STA1_CTRL(2) |
471 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 472
473 /* restore page register */
793b883e 474 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 475 break;
ed6d32c7
SH		 476 case CHIP_ID_YUKON_EC_U:
477 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
478
479 /* select page 3 to access LED control register */
480 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
481
482 /* set LED Function Control register */
483 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
484 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
485 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
486 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
487 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
488
489 /* set Blink Rate in LED Timer Control Register */
490 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
491 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
492 /* restore page register */
493 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
494 break;
cd28ab6a
SH		 495
496 default:
497 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
498 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
499 /* turn off the Rx LED (LED_RX) */
0efdf262 500 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 501 }
502
ed6d32c7 503 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 504 /* apply fixes in PHY AFE */
ed6d32c7
SH		 505 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
506 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
507
977bdf06 508 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 509 gm_phy_write(hw, port, 0x18, 0xaa99);
510 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 511
977bdf06 512 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 513 gm_phy_write(hw, port, 0x18, 0xa204);
514 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 515
516 /* set page register to 0 */
ed6d32c7 517 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
977bdf06
SH		 518 } else {
519 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 520
977bdf06
SH		 521 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
522 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 523 ledover |= PHY_M_LED_MO_100;
977bdf06 524 }
cd28ab6a 525
977bdf06
SH		 526 if (ledover)
527 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
528
529 }
2eaba1a2 530
d571b694 531 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 532 if (sky2->autoneg == AUTONEG_ENABLE)
533 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
534 else
535 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
536}
537
d3bcfbeb 538static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
539{
540 u32 reg1;
541 static const u32 phy_power[]
542 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
543
544 /* looks like this XL is back asswards .. */
545 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
546 onoff = !onoff;
547
aed2cec4 548 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 549 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb 550 if (onoff)
551 /* Turn off phy power saving */
552 reg1 &= ~phy_power[port];
553 else
554 reg1 |= phy_power[port];
555
556 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 557 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 558 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb 559 udelay(100);
560}
561
1b537565
SH		 562/* Force a renegotiation */
563static void sky2_phy_reinit(struct sky2_port *sky2)
564{
e07b1aa8 565 spin_lock_bh(&sky2->phy_lock);
1b537565 566 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 567 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 568}
569
cd28ab6a
SH		 570static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
571{
572 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
573 u16 reg;
574 int i;
575 const u8 *addr = hw->dev[port]->dev_addr;
576
42eeea01 577 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
578 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 579
580 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
581
793b883e 582 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 583 /* WA DEV_472 -- looks like crossed wires on port 2 */
584 /* clear GMAC 1 Control reset */
585 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
586 do {
587 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
588 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
589 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
590 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
591 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
592 }
593
793b883e 594 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 595
2eaba1a2
SH		 596 /* Enable Transmit FIFO Underrun */
597 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
598
e07b1aa8 599 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 600 sky2_phy_init(hw, port);
e07b1aa8 601 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 602
603 /* MIB clear */
604 reg = gma_read16(hw, port, GM_PHY_ADDR);
605 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
606
43f2f104
SH		 607 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
608 gma_read16(hw, port, i);
cd28ab6a
SH		 609 gma_write16(hw, port, GM_PHY_ADDR, reg);
610
611 /* transmit control */
612 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
613
614 /* receive control reg: unicast + multicast + no FCS */
615 gma_write16(hw, port, GM_RX_CTRL,
793b883e 616 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 617
618 /* transmit flow control */
619 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
620
621 /* transmit parameter */
622 gma_write16(hw, port, GM_TX_PARAM,
623 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
624 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
625 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
626 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
627
628 /* serial mode register */
629 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 630 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 631
6b1a3aef 632 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 633 reg |= GM_SMOD_JUMBO_ENA;
634
635 gma_write16(hw, port, GM_SERIAL_MODE, reg);
636
cd28ab6a
SH		 637 /* virtual address for data */
638 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
639
793b883e
SH		 640 /* physical address: used for pause frames */
641 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
642
643 /* ignore counter overflows */
cd28ab6a
SH		 644 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
645 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
646 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
647
648 /* Configure Rx MAC FIFO */
649 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 650 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
651 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 652
d571b694 653 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 654 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 655
8df9a876
SH		 656 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
657 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 658
659 /* Configure Tx MAC FIFO */
660 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
661 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 662
663 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
8df9a876 664 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 665 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
666 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
667 /* set Tx GMAC FIFO Almost Empty Threshold */
668 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
669 /* Disable Store & Forward mode for TX */
670 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
671 }
672 }
673
cd28ab6a
SH		 674}
675
67712901
SH		 676/* Assign Ram Buffer allocation to queue */
677static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 678{
67712901
SH		 679 u32 end;
680
681 /* convert from K bytes to qwords used for hw register */
682 start *= 1024/8;
683 space *= 1024/8;
684 end = start + space - 1;
793b883e 685
cd28ab6a
SH		 686 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
687 sky2_write32(hw, RB_ADDR(q, RB_START), start);
688 sky2_write32(hw, RB_ADDR(q, RB_END), end);
689 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
690 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
691
692 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 693 u32 tp = space - space/4;
793b883e 694
1c28f6ba
SH		 695 /* On receive queue's set the thresholds
696 * give receiver priority when > 3/4 full
697 * send pause when down to 2K
698 */
699 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
700 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 701
1c28f6ba
SH		 702 tp = space - 2048/8;
703 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
704 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 705 } else {
706 /* Enable store & forward on Tx queue's because
707 * Tx FIFO is only 1K on Yukon
708 */
709 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
710 }
711
712 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 713 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 714}
715
cd28ab6a 716/* Setup Bus Memory Interface */
af4ed7e6 717static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 718{
719 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
720 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
721 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 722 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 723}
724
cd28ab6a
SH		 725/* Setup prefetch unit registers. This is the interface between
726 * hardware and driver list elements
727 */
8cc048e3 728static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 729 u64 addr, u32 last)
730{
cd28ab6a
SH		 731 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
732 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
733 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
734 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
735 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
736 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 737
738 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 739}
740
793b883e
SH		 741static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
742{
743 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
744
cb5d9547 745 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 746 le->ctrl = 0;
793b883e
SH		 747 return le;
748}
cd28ab6a 749
291ea614
SH		 750static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
751 struct sky2_tx_le *le)
752{
753 return sky2->tx_ring + (le - sky2->tx_le);
754}
755
290d4de5
SH		 756/* Update chip's next pointer */
757static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 758{
98232f85 759 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
762c2de2 760 wmb();
98232f85 761 sky2_write16(hw, q, idx);
762 sky2_read16(hw, q);
cd28ab6a
SH		 763}
764
793b883e 765
cd28ab6a
SH		 766static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
767{
768 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 769 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 770 le->ctrl = 0;
cd28ab6a
SH		 771 return le;
772}
773
a018e330 774/* Return high part of DMA address (could be 32 or 64 bit) */
775static inline u32 high32(dma_addr_t a)
776{
a036119f 777 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330 778}
779
14d0263f
SH		 780/* Build description to hardware for one receive segment */
781static void sky2_rx_add(struct sky2_port *sky2, u8 op,
782 dma_addr_t map, unsigned len)
cd28ab6a
SH		 783{
784 struct sky2_rx_le *le;
734d1868 785 u32 hi = high32(map);
cd28ab6a 786
793b883e 787 if (sky2->rx_addr64 != hi) {
cd28ab6a 788 le = sky2_next_rx(sky2);
793b883e 789 le->addr = cpu_to_le32(hi);
cd28ab6a 790 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 791 sky2->rx_addr64 = high32(map + len);
cd28ab6a 792 }
793b883e 793
cd28ab6a 794 le = sky2_next_rx(sky2);
734d1868
SH		 795 le->addr = cpu_to_le32((u32) map);
796 le->length = cpu_to_le16(len);
14d0263f 797 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 798}
799
14d0263f
SH		 800/* Build description to hardware for one possibly fragmented skb */
801static void sky2_rx_submit(struct sky2_port *sky2,
802 const struct rx_ring_info *re)
803{
804 int i;
805
806 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
807
808 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
809 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
810}
811
812
813static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
814 unsigned size)
815{
816 struct sk_buff *skb = re->skb;
817 int i;
818
819 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
820 pci_unmap_len_set(re, data_size, size);
821
822 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
823 re->frag_addr[i] = pci_map_page(pdev,
824 skb_shinfo(skb)->frags[i].page,
825 skb_shinfo(skb)->frags[i].page_offset,
826 skb_shinfo(skb)->frags[i].size,
827 PCI_DMA_FROMDEVICE);
828}
829
830static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
831{
832 struct sk_buff *skb = re->skb;
833 int i;
834
835 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
836 PCI_DMA_FROMDEVICE);
837
838 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
839 pci_unmap_page(pdev, re->frag_addr[i],
840 skb_shinfo(skb)->frags[i].size,
841 PCI_DMA_FROMDEVICE);
842}
793b883e 843
cd28ab6a
SH		 844/* Tell chip where to start receive checksum.
845 * Actually has two checksums, but set both same to avoid possible byte
846 * order problems.
847 */
793b883e 848static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 849{
850 struct sky2_rx_le *le;
851
cd28ab6a 852 le = sky2_next_rx(sky2);
f65b138c 853 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
cd28ab6a
SH		 854 le->ctrl = 0;
855 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 856
793b883e
SH		 857 sky2_write32(sky2->hw,
858 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
859 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 860
861}
862
6b1a3aef 863/*
864 * The RX Stop command will not work for Yukon-2 if the BMU does not
865 * reach the end of packet and since we can't make sure that we have
866 * incoming data, we must reset the BMU while it is not doing a DMA
867 * transfer. Since it is possible that the RX path is still active,
868 * the RX RAM buffer will be stopped first, so any possible incoming
869 * data will not trigger a DMA. After the RAM buffer is stopped, the
870 * BMU is polled until any DMA in progress is ended and only then it
871 * will be reset.
872 */
873static void sky2_rx_stop(struct sky2_port *sky2)
874{
875 struct sky2_hw *hw = sky2->hw;
876 unsigned rxq = rxqaddr[sky2->port];
877 int i;
878
879 /* disable the RAM Buffer receive queue */
880 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
881
882 for (i = 0; i < 0xffff; i++)
883 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
884 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
885 goto stopped;
886
887 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
888 sky2->netdev->name);
889stopped:
890 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
891
892 /* reset the Rx prefetch unit */
893 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
894}
793b883e 895
d571b694 896/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 897static void sky2_rx_clean(struct sky2_port *sky2)
898{
899 unsigned i;
900
901 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 902 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 903 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 904
905 if (re->skb) {
14d0263f 906 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 907 kfree_skb(re->skb);
908 re->skb = NULL;
909 }
910 }
911}
912
ef743d33 913/* Basic MII support */
914static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
915{
916 struct mii_ioctl_data *data = if_mii(ifr);
917 struct sky2_port *sky2 = netdev_priv(dev);
918 struct sky2_hw *hw = sky2->hw;
919 int err = -EOPNOTSUPP;
920
921 if (!netif_running(dev))
922 return -ENODEV; /* Phy still in reset */
923
d89e1343 924 switch (cmd) {
ef743d33 925 case SIOCGMIIPHY:
926 data->phy_id = PHY_ADDR_MARV;
927
928 /* fallthru */
929 case SIOCGMIIREG: {
930 u16 val = 0;
91c86df5 931
e07b1aa8 932 spin_lock_bh(&sky2->phy_lock);
ef743d33 933 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 934 spin_unlock_bh(&sky2->phy_lock);
91c86df5 935
ef743d33 936 data->val_out = val;
937 break;
938 }
939
940 case SIOCSMIIREG:
941 if (!capable(CAP_NET_ADMIN))
942 return -EPERM;
943
e07b1aa8 944 spin_lock_bh(&sky2->phy_lock);
ef743d33 945 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
946 data->val_in);
e07b1aa8 947 spin_unlock_bh(&sky2->phy_lock);
ef743d33 948 break;
949 }
950 return err;
951}
952
d1f13708 953#ifdef SKY2_VLAN_TAG_USED
954static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
955{
956 struct sky2_port *sky2 = netdev_priv(dev);
957 struct sky2_hw *hw = sky2->hw;
958 u16 port = sky2->port;
d1f13708 959
2bb8c262 960 netif_tx_lock_bh(dev);
d1f13708 961
962 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
963 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
964 sky2->vlgrp = grp;
965
2bb8c262 966 netif_tx_unlock_bh(dev);
d1f13708 967}
968
969static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
970{
971 struct sky2_port *sky2 = netdev_priv(dev);
972 struct sky2_hw *hw = sky2->hw;
973 u16 port = sky2->port;
d1f13708 974
2bb8c262 975 netif_tx_lock_bh(dev);
d1f13708 976
977 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
978 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
979 if (sky2->vlgrp)
980 sky2->vlgrp->vlan_devices[vid] = NULL;
981
2bb8c262 982 netif_tx_unlock_bh(dev);
d1f13708 983}
984#endif
985
82788c7a 986/*
14d0263f
SH		 987 * Allocate an skb for receiving. If the MTU is large enough
988 * make the skb non-linear with a fragment list of pages.
989 *
82788c7a
SH		 990 * It appears the hardware has a bug in the FIFO logic that
991 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86 992 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
993 * aligned except if slab debugging is enabled.
82788c7a 994 */
14d0263f 995static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 996{
997 struct sk_buff *skb;
14d0263f
SH		 998 unsigned long p;
999 int i;
82788c7a 1000
14d0263f
SH		 1001 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1002 if (!skb)
1003 goto nomem;
1004
1005 p = (unsigned long) skb->data;
1006 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1007
1008 for (i = 0; i < sky2->rx_nfrags; i++) {
1009 struct page *page = alloc_page(GFP_ATOMIC);
1010
1011 if (!page)
1012 goto free_partial;
1013 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1014 }
1015
1016 return skb;
14d0263f
SH		 1017free_partial:
1018 kfree_skb(skb);
1019nomem:
1020 return NULL;
82788c7a
SH		 1021}
1022
cd28ab6a
SH		 1023/*
1024 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1025 * Normal case this ends up creating one list element for skb
1026 * in the receive ring. Worst case if using large MTU and each
1027 * allocation falls on a different 64 bit region, that results
1028 * in 6 list elements per ring entry.
1029 * One element is used for checksum enable/disable, and one
1030 * extra to avoid wrap.
cd28ab6a 1031 */
6b1a3aef 1032static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1033{
6b1a3aef 1034 struct sky2_hw *hw = sky2->hw;
14d0263f 1035 struct rx_ring_info *re;
6b1a3aef 1036 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1037 unsigned i, size, space, thresh;
cd28ab6a 1038
6b1a3aef 1039 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1040 sky2_qset(hw, rxq);
977bdf06 1041
c3905bc4
SH		 1042 /* On PCI express lowering the watermark gives better performance */
1043 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1044 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1045
1046 /* These chips have no ram buffer?
1047 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1048 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1049 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1050 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
977bdf06 1051 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
977bdf06 1052
6b1a3aef 1053 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1054
1055 rx_set_checksum(sky2);
14d0263f
SH		 1056
1057 /* Space needed for frame data + headers rounded up */
1058 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1059 + 8;
1060
1061 /* Stopping point for hardware truncation */
1062 thresh = (size - 8) / sizeof(u32);
1063
1064 /* Account for overhead of skb - to avoid order > 0 allocation */
1065 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1066 + sizeof(struct skb_shared_info);
1067
1068 sky2->rx_nfrags = space >> PAGE_SHIFT;
1069 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1070
1071 if (sky2->rx_nfrags != 0) {
1072 /* Compute residue after pages */
1073 space = sky2->rx_nfrags << PAGE_SHIFT;
1074
1075 if (space < size)
1076 size -= space;
1077 else
1078 size = 0;
1079
1080 /* Optimize to handle small packets and headers */
1081 if (size < copybreak)
1082 size = copybreak;
1083 if (size < ETH_HLEN)
1084 size = ETH_HLEN;
1085 }
1086 sky2->rx_data_size = size;
1087
1088 /* Fill Rx ring */
793b883e 1089 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1090 re = sky2->rx_ring + i;
cd28ab6a 1091
14d0263f 1092 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1093 if (!re->skb)
1094 goto nomem;
1095
14d0263f
SH		 1096 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1097 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1098 }
1099
a1433ac4
SH		 1100 /*
1101 * The receiver hangs if it receives frames larger than the
1102 * packet buffer. As a workaround, truncate oversize frames, but
1103 * the register is limited to 9 bits, so if you do frames > 2052
1104 * you better get the MTU right!
1105 */
a1433ac4
SH		 1106 if (thresh > 0x1ff)
1107 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1108 else {
1109 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1110 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1111 }
1112
6b1a3aef 1113 /* Tell chip about available buffers */
1114 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1115 return 0;
1116nomem:
1117 sky2_rx_clean(sky2);
1118 return -ENOMEM;
1119}
1120
1121/* Bring up network interface. */
1122static int sky2_up(struct net_device *dev)
1123{
1124 struct sky2_port *sky2 = netdev_priv(dev);
1125 struct sky2_hw *hw = sky2->hw;
1126 unsigned port = sky2->port;
67712901 1127 u32 ramsize, imask;
ee7abb04 1128 int cap, err = -ENOMEM;
843a46f4 1129 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1130
ee7abb04
SH		 1131 /*
1132 * On dual port PCI-X card, there is an problem where status
1133 * can be received out of order due to split transactions
843a46f4 1134 */
ee7abb04
SH		 1135 if (otherdev && netif_running(otherdev) &&
1136 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1137 struct sky2_port *osky2 = netdev_priv(otherdev);
1138 u16 cmd;
1139
1140 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1141 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1142 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1143
1144 sky2->rx_csum = 0;
1145 osky2->rx_csum = 0;
1146 }
843a46f4 1147
cd28ab6a
SH		 1148 if (netif_msg_ifup(sky2))
1149 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1150
1151 /* must be power of 2 */
1152 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1153 TX_RING_SIZE *
1154 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1155 &sky2->tx_le_map);
1156 if (!sky2->tx_le)
1157 goto err_out;
1158
6cdbbdf3 1159 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1160 GFP_KERNEL);
1161 if (!sky2->tx_ring)
1162 goto err_out;
1163 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1164
1165 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1166 &sky2->rx_le_map);
1167 if (!sky2->rx_le)
1168 goto err_out;
1169 memset(sky2->rx_le, 0, RX_LE_BYTES);
1170
291ea614 1171 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1172 GFP_KERNEL);
1173 if (!sky2->rx_ring)
1174 goto err_out;
1175
d3bcfbeb 1176 sky2_phy_power(hw, port, 1);
1177
cd28ab6a
SH		 1178 sky2_mac_init(hw, port);
1179
67712901
SH		 1180 /* Register is number of 4K blocks on internal RAM buffer. */
1181 ramsize = sky2_read8(hw, B2_E_0) * 4;
1182 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1c28f6ba 1183
67712901
SH		 1184 if (ramsize > 0) {
1185 u32 rxspace;
cd28ab6a 1186
67712901
SH		 1187 if (ramsize < 16)
1188 rxspace = ramsize / 2;
1189 else
1190 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1191
67712901
SH		 1192 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1193 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1194
1195 /* Make sure SyncQ is disabled */
1196 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1197 RB_RST_SET);
1198 }
793b883e 1199
af4ed7e6 1200 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1201
977bdf06 1202 /* Set almost empty threshold */
c2716fb4
SH		 1203 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1204 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
977bdf06 1205 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1206
6b1a3aef 1207 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1208 TX_RING_SIZE - 1);
cd28ab6a 1209
6b1a3aef 1210 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1211 if (err)
1212 goto err_out;
1213
cd28ab6a 1214 /* Enable interrupts from phy/mac for port */
e07b1aa8 1215 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1216 imask |= portirq_msk[port];
e07b1aa8
SH		 1217 sky2_write32(hw, B0_IMSK, imask);
1218
cd28ab6a
SH		 1219 return 0;
1220
1221err_out:
1b537565 1222 if (sky2->rx_le) {
cd28ab6a
SH		 1223 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1224 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1225 sky2->rx_le = NULL;
1226 }
1227 if (sky2->tx_le) {
cd28ab6a
SH		 1228 pci_free_consistent(hw->pdev,
1229 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1230 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1231 sky2->tx_le = NULL;
1232 }
1233 kfree(sky2->tx_ring);
1234 kfree(sky2->rx_ring);
cd28ab6a 1235
1b537565
SH		 1236 sky2->tx_ring = NULL;
1237 sky2->rx_ring = NULL;
cd28ab6a
SH		 1238 return err;
1239}
1240
793b883e
SH		 1241/* Modular subtraction in ring */
1242static inline int tx_dist(unsigned tail, unsigned head)
1243{
cb5d9547 1244 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1245}
cd28ab6a 1246
793b883e
SH		 1247/* Number of list elements available for next tx */
1248static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1249{
793b883e 1250 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1251}
1252
793b883e 1253/* Estimate of number of transmit list elements required */
28bd181a 1254static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1255{
793b883e
SH		 1256 unsigned count;
1257
1258 count = sizeof(dma_addr_t) / sizeof(u32);
1259 count += skb_shinfo(skb)->nr_frags * count;
1260
89114afd 1261 if (skb_is_gso(skb))
793b883e
SH		 1262 ++count;
1263
84fa7933 1264 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1265 ++count;
1266
1267 return count;
cd28ab6a
SH		 1268}
1269
793b883e
SH		 1270/*
1271 * Put one packet in ring for transmit.
1272 * A single packet can generate multiple list elements, and
1273 * the number of ring elements will probably be less than the number
1274 * of list elements used.
1275 */
cd28ab6a
SH		 1276static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1277{
1278 struct sky2_port *sky2 = netdev_priv(dev);
1279 struct sky2_hw *hw = sky2->hw;
d1f13708 1280 struct sky2_tx_le *le = NULL;
6cdbbdf3 1281 struct tx_ring_info *re;
cd28ab6a
SH		 1282 unsigned i, len;
1283 dma_addr_t mapping;
1284 u32 addr64;
1285 u16 mss;
1286 u8 ctrl;
1287
2bb8c262
SH		 1288 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1289 return NETDEV_TX_BUSY;
cd28ab6a 1290
793b883e 1291 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1292 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1293 dev->name, sky2->tx_prod, skb->len);
1294
cd28ab6a
SH		 1295 len = skb_headlen(skb);
1296 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1297 addr64 = high32(mapping);
793b883e 1298
a018e330 1299 /* Send high bits if changed or crosses boundary */
1300 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1301 le = get_tx_le(sky2);
f65b138c 1302 le->addr = cpu_to_le32(addr64);
793b883e 1303 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1304 sky2->tx_addr64 = high32(mapping + len);
793b883e 1305 }
cd28ab6a
SH		 1306
1307 /* Check for TCP Segmentation Offload */
7967168c 1308 mss = skb_shinfo(skb)->gso_size;
793b883e 1309 if (mss != 0) {
cd28ab6a
SH		 1310 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1311 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1312 mss += ETH_HLEN;
1313
e07560cd 1314 if (mss != sky2->tx_last_mss) {
1315 le = get_tx_le(sky2);
f65b138c 1316 le->addr = cpu_to_le32(mss);
e07560cd 1317 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1318 sky2->tx_last_mss = mss;
1319 }
cd28ab6a
SH		 1320 }
1321
cd28ab6a 1322 ctrl = 0;
d1f13708 1323#ifdef SKY2_VLAN_TAG_USED
1324 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1325 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1326 if (!le) {
1327 le = get_tx_le(sky2);
f65b138c 1328 le->addr = 0;
d1f13708 1329 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1330 } else
1331 le->opcode |= OP_VLAN;
1332 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1333 ctrl |= INS_VLAN;
1334 }
1335#endif
1336
1337 /* Handle TCP checksum offload */
84fa7933 1338 if (skb->ip_summed == CHECKSUM_PARTIAL) {
f65b138c
SH		 1339 unsigned offset = skb->h.raw - skb->data;
1340 u32 tcpsum;
1341
1342 tcpsum = offset << 16; /* sum start */
ff1dcadb 1343 tcpsum |= offset + skb->csum_offset; /* sum write */
cd28ab6a
SH		 1344
1345 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1346 if (skb->nh.iph->protocol == IPPROTO_UDP)
1347 ctrl |= UDPTCP;
1348
f65b138c
SH		 1349 if (tcpsum != sky2->tx_tcpsum) {
1350 sky2->tx_tcpsum = tcpsum;
1d179332 1351
1352 le = get_tx_le(sky2);
f65b138c 1353 le->addr = cpu_to_le32(tcpsum);
1d179332 1354 le->length = 0; /* initial checksum value */
1355 le->ctrl = 1; /* one packet */
1356 le->opcode = OP_TCPLISW | HW_OWNER;
1357 }
cd28ab6a
SH		 1358 }
1359
1360 le = get_tx_le(sky2);
f65b138c 1361 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1362 le->length = cpu_to_le16(len);
1363 le->ctrl = ctrl;
793b883e 1364 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1365
291ea614 1366 re = tx_le_re(sky2, le);
cd28ab6a 1367 re->skb = skb;
6cdbbdf3 1368 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1369 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1370
1371 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1372 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1373
1374 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1375 frag->size, PCI_DMA_TODEVICE);
a036119f 1376 addr64 = high32(mapping);
793b883e
SH		 1377 if (addr64 != sky2->tx_addr64) {
1378 le = get_tx_le(sky2);
f65b138c 1379 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1380 le->ctrl = 0;
1381 le->opcode = OP_ADDR64 | HW_OWNER;
1382 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1383 }
1384
1385 le = get_tx_le(sky2);
f65b138c 1386 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1387 le->length = cpu_to_le16(frag->size);
1388 le->ctrl = ctrl;
793b883e 1389 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1390
291ea614
SH		 1391 re = tx_le_re(sky2, le);
1392 re->skb = skb;
1393 pci_unmap_addr_set(re, mapaddr, mapping);
1394 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1395 }
6cdbbdf3 1396
cd28ab6a
SH		 1397 le->ctrl |= EOP;
1398
97bda706 1399 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1400 netif_stop_queue(dev);
b19666d9 1401
290d4de5 1402 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1403
cd28ab6a
SH		 1404 dev->trans_start = jiffies;
1405 return NETDEV_TX_OK;
1406}
1407
cd28ab6a 1408/*
793b883e
SH		 1409 * Free ring elements from starting at tx_cons until "done"
1410 *
1411 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1412 * buffers so make sure not to free skb to early.
cd28ab6a 1413 */
d11c13e7 1414static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1415{
d11c13e7 1416 struct net_device *dev = sky2->netdev;
af2a58ac 1417 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1418 unsigned idx;
cd28ab6a 1419
0e3ff6aa 1420 BUG_ON(done >= TX_RING_SIZE);
2224795d 1421
291ea614
SH		 1422 for (idx = sky2->tx_cons; idx != done;
1423 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1424 struct sky2_tx_le *le = sky2->tx_le + idx;
1425 struct tx_ring_info *re = sky2->tx_ring + idx;
1426
1427 switch(le->opcode & ~HW_OWNER) {
1428 case OP_LARGESEND:
1429 case OP_PACKET:
1430 pci_unmap_single(pdev,
1431 pci_unmap_addr(re, mapaddr),
1432 pci_unmap_len(re, maplen),
1433 PCI_DMA_TODEVICE);
af2a58ac 1434 break;
291ea614
SH		 1435 case OP_BUFFER:
1436 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1437 pci_unmap_len(re, maplen),
734d1868 1438 PCI_DMA_TODEVICE);
291ea614
SH		 1439 break;
1440 }
1441
1442 if (le->ctrl & EOP) {
1443 if (unlikely(netif_msg_tx_done(sky2)))
1444 printk(KERN_DEBUG "%s: tx done %u\n",
1445 dev->name, idx);
2bf56fe2 1446 sky2->net_stats.tx_packets++;
1447 sky2->net_stats.tx_bytes += re->skb->len;
1448
794b2bd2 1449 dev_kfree_skb_any(re->skb);
cd28ab6a
SH		 1450 }
1451
291ea614 1452 le->opcode = 0; /* paranoia */
793b883e 1453 }
793b883e 1454
291ea614 1455 sky2->tx_cons = idx;
22e11703 1456 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1457 netif_wake_queue(dev);
cd28ab6a
SH		 1458}
1459
1460/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1461static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1462{
2bb8c262
SH		 1463 struct sky2_port *sky2 = netdev_priv(dev);
1464
1465 netif_tx_lock_bh(dev);
d11c13e7 1466 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1467 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1468}
1469
1470/* Network shutdown */
1471static int sky2_down(struct net_device *dev)
1472{
1473 struct sky2_port *sky2 = netdev_priv(dev);
1474 struct sky2_hw *hw = sky2->hw;
1475 unsigned port = sky2->port;
1476 u16 ctrl;
e07b1aa8 1477 u32 imask;
cd28ab6a 1478
1b537565
SH		 1479 /* Never really got started! */
1480 if (!sky2->tx_le)
1481 return 0;
1482
cd28ab6a
SH		 1483 if (netif_msg_ifdown(sky2))
1484 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1485
018d1c66 1486 /* Stop more packets from being queued */
cd28ab6a
SH		 1487 netif_stop_queue(dev);
1488
ebc646f6
SH		 1489 /* Disable port IRQ */
1490 imask = sky2_read32(hw, B0_IMSK);
1491 imask &= ~portirq_msk[port];
1492 sky2_write32(hw, B0_IMSK, imask);
1493
25d82d7a
SH		 1494 /*
1495 * Both ports share the NAPI poll on port 0, so if necessary undo the
1496 * the disable that is done in dev_close.
1497 */
1498 if (sky2->port == 0 && hw->ports > 1)
1499 netif_poll_enable(dev);
1500
d3bcfbeb 1501 sky2_gmac_reset(hw, port);
793b883e 1502
cd28ab6a
SH		 1503 /* Stop transmitter */
1504 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1505 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1506
1507 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1508 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a 1509
c2716fb4
SH		 1510 /* WA for dev. #4.209 */
1511 if (hw->chip_id == CHIP_ID_YUKON_EC_U
8df9a876 1512 && (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
c2716fb4
SH		 1513 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1514 sky2->speed != SPEED_1000 ?
1515 TX_STFW_ENA : TX_STFW_DIS);
1516
cd28ab6a 1517 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1518 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1519 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1520
1521 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1522
1523 /* Workaround shared GMAC reset */
793b883e
SH		 1524 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1525 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1526 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1527
1528 /* Disable Force Sync bit and Enable Alloc bit */
1529 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1530 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1531
1532 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1533 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1534 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1535
1536 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1537 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1538 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1539
1540 /* Reset the Tx prefetch units */
1541 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1542 PREF_UNIT_RST_SET);
1543
1544 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1545
6b1a3aef 1546 sky2_rx_stop(sky2);
cd28ab6a
SH		 1547
1548 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1549 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1550
d3bcfbeb 1551 sky2_phy_power(hw, port, 0);
1552
d571b694 1553 /* turn off LED's */
cd28ab6a
SH		 1554 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1555
018d1c66 1556 synchronize_irq(hw->pdev->irq);
1557
2bb8c262 1558 sky2_tx_clean(dev);
cd28ab6a
SH		 1559 sky2_rx_clean(sky2);
1560
1561 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1562 sky2->rx_le, sky2->rx_le_map);
1563 kfree(sky2->rx_ring);
1564
1565 pci_free_consistent(hw->pdev,
1566 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1567 sky2->tx_le, sky2->tx_le_map);
1568 kfree(sky2->tx_ring);
1569
1b537565
SH		 1570 sky2->tx_le = NULL;
1571 sky2->rx_le = NULL;
1572
1573 sky2->rx_ring = NULL;
1574 sky2->tx_ring = NULL;
1575
cd28ab6a
SH		 1576 return 0;
1577}
1578
1579static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1580{
b89165f2 1581 if (!sky2_is_copper(hw))
793b883e
SH		 1582 return SPEED_1000;
1583
cd28ab6a
SH		 1584 if (hw->chip_id == CHIP_ID_YUKON_FE)
1585 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1586
1587 switch (aux & PHY_M_PS_SPEED_MSK) {
1588 case PHY_M_PS_SPEED_1000:
1589 return SPEED_1000;
1590 case PHY_M_PS_SPEED_100:
1591 return SPEED_100;
1592 default:
1593 return SPEED_10;
1594 }
1595}
1596
1597static void sky2_link_up(struct sky2_port *sky2)
1598{
1599 struct sky2_hw *hw = sky2->hw;
1600 unsigned port = sky2->port;
1601 u16 reg;
16ad91e1
SH		 1602 static const char *fc_name[] = {
1603 [FC_NONE] = "none",
1604 [FC_TX] = "tx",
1605 [FC_RX] = "rx",
1606 [FC_BOTH] = "both",
1607 };
cd28ab6a 1608
cd28ab6a 1609 /* enable Rx/Tx */
2eaba1a2 1610 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1611 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1612 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1613
1614 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1615
1616 netif_carrier_on(sky2->netdev);
1617 netif_wake_queue(sky2->netdev);
1618
1619 /* Turn on link LED */
793b883e 1620 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1621 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1622
ed6d32c7 1623 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
793b883e 1624 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1625 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1626
1627 switch(sky2->speed) {
1628 case SPEED_10:
1629 led |= PHY_M_LEDC_INIT_CTRL(7);
1630 break;
1631
1632 case SPEED_100:
1633 led |= PHY_M_LEDC_STA1_CTRL(7);
1634 break;
1635
1636 case SPEED_1000:
1637 led |= PHY_M_LEDC_STA0_CTRL(7);
1638 break;
1639 }
793b883e
SH		 1640
1641 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1642 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1643 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1644 }
1645
cd28ab6a
SH		 1646 if (netif_msg_link(sky2))
1647 printk(KERN_INFO PFX
d571b694 1648 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1649 sky2->netdev->name, sky2->speed,
1650 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1651 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1652}
1653
1654static void sky2_link_down(struct sky2_port *sky2)
1655{
1656 struct sky2_hw *hw = sky2->hw;
1657 unsigned port = sky2->port;
1658 u16 reg;
1659
1660 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1661
1662 reg = gma_read16(hw, port, GM_GP_CTRL);
1663 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1664 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1665
16ad91e1 1666 if (sky2->flow_status == FC_RX) {
cd28ab6a
SH		 1667 /* restore Asymmetric Pause bit */
1668 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1669 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1670 | PHY_M_AN_ASP);
cd28ab6a
SH		 1671 }
1672
cd28ab6a
SH		 1673 netif_carrier_off(sky2->netdev);
1674 netif_stop_queue(sky2->netdev);
1675
1676 /* Turn on link LED */
1677 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1678
1679 if (netif_msg_link(sky2))
1680 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1681
cd28ab6a
SH		 1682 sky2_phy_init(hw, port);
1683}
1684
16ad91e1
SH		 1685static enum flow_control sky2_flow(int rx, int tx)
1686{
1687 if (rx)
1688 return tx ? FC_BOTH : FC_RX;
1689 else
1690 return tx ? FC_TX : FC_NONE;
1691}
1692
793b883e
SH		 1693static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1694{
1695 struct sky2_hw *hw = sky2->hw;
1696 unsigned port = sky2->port;
1697 u16 lpa;
1698
1699 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1700
1701 if (lpa & PHY_M_AN_RF) {
1702 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1703 return -1;
1704 }
1705
793b883e
SH		 1706 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1707 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1708 sky2->netdev->name);
1709 return -1;
1710 }
1711
793b883e 1712 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1713 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e
SH		 1714
1715 /* Pause bits are offset (9..8) */
ed6d32c7 1716 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
793b883e
SH		 1717 aux >>= 6;
1718
16ad91e1
SH		 1719 sky2->flow_status = sky2_flow(aux & PHY_M_PS_RX_P_EN,
1720 aux & PHY_M_PS_TX_P_EN);
793b883e 1721
16ad91e1 1722 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
2eaba1a2 1723 && hw->chip_id != CHIP_ID_YUKON_EC_U)
16ad91e1 1724 sky2->flow_status = FC_NONE;
2eaba1a2 1725
16ad91e1 1726 if (aux & PHY_M_PS_RX_P_EN)
793b883e
SH		 1727 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1728 else
1729 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1730
1731 return 0;
1732}
cd28ab6a 1733
e07b1aa8
SH		 1734/* Interrupt from PHY */
1735static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1736{
e07b1aa8
SH		 1737 struct net_device *dev = hw->dev[port];
1738 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1739 u16 istatus, phystat;
1740
ebc646f6
SH		 1741 if (!netif_running(dev))
1742 return;
1743
e07b1aa8
SH		 1744 spin_lock(&sky2->phy_lock);
1745 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1746 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1747
cd28ab6a
SH		 1748 if (netif_msg_intr(sky2))
1749 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1750 sky2->netdev->name, istatus, phystat);
1751
2eaba1a2 1752 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1753 if (sky2_autoneg_done(sky2, phystat) == 0)
1754 sky2_link_up(sky2);
1755 goto out;
1756 }
cd28ab6a 1757
793b883e
SH		 1758 if (istatus & PHY_M_IS_LSP_CHANGE)
1759 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1760
793b883e
SH		 1761 if (istatus & PHY_M_IS_DUP_CHANGE)
1762 sky2->duplex =
1763 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1764
793b883e
SH		 1765 if (istatus & PHY_M_IS_LST_CHANGE) {
1766 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1767 sky2_link_up(sky2);
793b883e
SH		 1768 else
1769 sky2_link_down(sky2);
cd28ab6a 1770 }
793b883e 1771out:
e07b1aa8 1772 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1773}
1774
302d1252
SH		 1775
1776/* Transmit timeout is only called if we are running, carries is up
1777 * and tx queue is full (stopped).
1778 */
cd28ab6a
SH		 1779static void sky2_tx_timeout(struct net_device *dev)
1780{
1781 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1782 struct sky2_hw *hw = sky2->hw;
1783 unsigned txq = txqaddr[sky2->port];
8f24664d 1784 u16 report, done;
cd28ab6a
SH		 1785
1786 if (netif_msg_timer(sky2))
1787 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1788
8f24664d
SH		 1789 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1790 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1791
8f24664d
SH		 1792 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1793 dev->name,
1794 sky2->tx_cons, sky2->tx_prod, report, done);
1795
1796 if (report != done) {
1797 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1798
1799 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1800 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1801 } else if (report != sky2->tx_cons) {
1802 printk(KERN_INFO PFX "status report lost?\n");
1803
2bb8c262 1804 netif_tx_lock_bh(dev);
8f24664d 1805 sky2_tx_complete(sky2, report);
2bb8c262 1806 netif_tx_unlock_bh(dev);
8f24664d
SH		 1807 } else {
1808 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1809
8f24664d
SH		 1810 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1811 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1812
2bb8c262 1813 sky2_tx_clean(dev);
8f24664d
SH		 1814
1815 sky2_qset(hw, txq);
1816 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1817 }
cd28ab6a
SH		 1818}
1819
1820static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1821{
6b1a3aef 1822 struct sky2_port *sky2 = netdev_priv(dev);
1823 struct sky2_hw *hw = sky2->hw;
1824 int err;
1825 u16 ctl, mode;
e07b1aa8 1826 u32 imask;
cd28ab6a
SH		 1827
1828 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1829 return -EINVAL;
1830
5a5b1ea0 1831 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1832 return -EINVAL;
1833
6b1a3aef 1834 if (!netif_running(dev)) {
1835 dev->mtu = new_mtu;
1836 return 0;
1837 }
1838
e07b1aa8 1839 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 1840 sky2_write32(hw, B0_IMSK, 0);
1841
018d1c66 1842 dev->trans_start = jiffies; /* prevent tx timeout */
1843 netif_stop_queue(dev);
1844 netif_poll_disable(hw->dev[0]);
1845
e07b1aa8
SH		 1846 synchronize_irq(hw->pdev->irq);
1847
6b1a3aef 1848 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1849 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1850 sky2_rx_stop(sky2);
1851 sky2_rx_clean(sky2);
cd28ab6a
SH		 1852
1853 dev->mtu = new_mtu;
14d0263f 1854
6b1a3aef 1855 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1856 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1857
1858 if (dev->mtu > ETH_DATA_LEN)
1859 mode |= GM_SMOD_JUMBO_ENA;
1860
1861 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1862
6b1a3aef 1863 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1864
6b1a3aef 1865 err = sky2_rx_start(sky2);
e07b1aa8 1866 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1867
1b537565
SH		 1868 if (err)
1869 dev_close(dev);
1870 else {
1871 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1872
1873 netif_poll_enable(hw->dev[0]);
1874 netif_wake_queue(dev);
1875 }
1876
cd28ab6a
SH		 1877 return err;
1878}
1879
14d0263f
SH		 1880/* For small just reuse existing skb for next receive */
1881static struct sk_buff *receive_copy(struct sky2_port *sky2,
1882 const struct rx_ring_info *re,
1883 unsigned length)
1884{
1885 struct sk_buff *skb;
1886
1887 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1888 if (likely(skb)) {
1889 skb_reserve(skb, 2);
1890 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1891 length, PCI_DMA_FROMDEVICE);
1892 memcpy(skb->data, re->skb->data, length);
1893 skb->ip_summed = re->skb->ip_summed;
1894 skb->csum = re->skb->csum;
1895 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1896 length, PCI_DMA_FROMDEVICE);
1897 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 1898 skb_put(skb, length);
14d0263f
SH		 1899 }
1900 return skb;
1901}
1902
1903/* Adjust length of skb with fragments to match received data */
1904static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1905 unsigned int length)
1906{
1907 int i, num_frags;
1908 unsigned int size;
1909
1910 /* put header into skb */
1911 size = min(length, hdr_space);
1912 skb->tail += size;
1913 skb->len += size;
1914 length -= size;
1915
1916 num_frags = skb_shinfo(skb)->nr_frags;
1917 for (i = 0; i < num_frags; i++) {
1918 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1919
1920 if (length == 0) {
1921 /* don't need this page */
1922 __free_page(frag->page);
1923 --skb_shinfo(skb)->nr_frags;
1924 } else {
1925 size = min(length, (unsigned) PAGE_SIZE);
1926
1927 frag->size = size;
1928 skb->data_len += size;
1929 skb->truesize += size;
1930 skb->len += size;
1931 length -= size;
1932 }
1933 }
1934}
1935
1936/* Normal packet - take skb from ring element and put in a new one */
1937static struct sk_buff *receive_new(struct sky2_port *sky2,
1938 struct rx_ring_info *re,
1939 unsigned int length)
1940{
1941 struct sk_buff *skb, *nskb;
1942 unsigned hdr_space = sky2->rx_data_size;
1943
1944 pr_debug(PFX "receive new length=%d\n", length);
1945
1946 /* Don't be tricky about reusing pages (yet) */
1947 nskb = sky2_rx_alloc(sky2);
1948 if (unlikely(!nskb))
1949 return NULL;
1950
1951 skb = re->skb;
1952 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1953
1954 prefetch(skb->data);
1955 re->skb = nskb;
1956 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
1957
1958 if (skb_shinfo(skb)->nr_frags)
1959 skb_put_frags(skb, hdr_space, length);
1960 else
489b10c1 1961 skb_put(skb, length);
14d0263f
SH		 1962 return skb;
1963}
1964
cd28ab6a
SH		 1965/*
1966 * Receive one packet.
d571b694 1967 * For larger packets, get new buffer.
cd28ab6a 1968 */
497d7c86 1969static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 1970 u16 length, u32 status)
1971{
497d7c86 1972 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 1973 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1974 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1975
1976 if (unlikely(netif_msg_rx_status(sky2)))
1977 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 1978 dev->name, sky2->rx_next, status, length);
cd28ab6a 1979
793b883e 1980 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1981 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1982
42eeea01 1983 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1984 goto error;
1985
42eeea01 1986 if (!(status & GMR_FS_RX_OK))
1987 goto resubmit;
1988
497d7c86 1989 if (length > dev->mtu + ETH_HLEN)
6e15b712
SH		 1990 goto oversize;
1991
14d0263f
SH		 1992 if (length < copybreak)
1993 skb = receive_copy(sky2, re, length);
1994 else
1995 skb = receive_new(sky2, re, length);
793b883e 1996resubmit:
14d0263f 1997 sky2_rx_submit(sky2, re);
79e57d32 1998
cd28ab6a
SH		 1999 return skb;
2000
6e15b712
SH		 2001oversize:
2002 ++sky2->net_stats.rx_over_errors;
2003 goto resubmit;
2004
cd28ab6a 2005error:
6e15b712 2006 ++sky2->net_stats.rx_errors;
b6d77734
SH		 2007 if (status & GMR_FS_RX_FF_OV) {
2008 sky2->net_stats.rx_fifo_errors++;
2009 goto resubmit;
2010 }
6e15b712 2011
3be92a70 2012 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2013 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2014 dev->name, status, length);
793b883e
SH		 2015
2016 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2017 sky2->net_stats.rx_length_errors++;
2018 if (status & GMR_FS_FRAGMENT)
2019 sky2->net_stats.rx_frame_errors++;
2020 if (status & GMR_FS_CRC_ERR)
2021 sky2->net_stats.rx_crc_errors++;
79e57d32 2022
793b883e 2023 goto resubmit;
cd28ab6a
SH		 2024}
2025
e07b1aa8
SH		 2026/* Transmit complete */
2027static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2028{
e07b1aa8 2029 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2030
e07b1aa8 2031 if (netif_running(dev)) {
2bb8c262 2032 netif_tx_lock(dev);
e07b1aa8 2033 sky2_tx_complete(sky2, last);
2bb8c262 2034 netif_tx_unlock(dev);
2224795d 2035 }
cd28ab6a
SH		 2036}
2037
e07b1aa8
SH		 2038/* Process status response ring */
2039static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2040{
22e11703 2041 struct sky2_port *sky2;
e07b1aa8 2042 int work_done = 0;
22e11703 2043 unsigned buf_write[2] = { 0, 0 };
e71ebd73 2044 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2045
af2a58ac 2046 rmb();
bea86103 2047
e71ebd73 2048 while (hw->st_idx != hwidx) {
13210ce5 2049 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2050 struct net_device *dev;
cd28ab6a 2051 struct sk_buff *skb;
cd28ab6a
SH		 2052 u32 status;
2053 u16 length;
2054
cb5d9547 2055 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2056
e71ebd73
SH		 2057 BUG_ON(le->link >= 2);
2058 dev = hw->dev[le->link];
13210ce5 2059
2060 sky2 = netdev_priv(dev);
f65b138c
SH		 2061 length = le16_to_cpu(le->length);
2062 status = le32_to_cpu(le->status);
cd28ab6a 2063
e71ebd73 2064 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2065 case OP_RXSTAT:
497d7c86 2066 skb = sky2_receive(dev, length, status);
d1f13708 2067 if (!skb)
5df79111 2068 goto force_update;
13210ce5 2069
13210ce5 2070 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2071 sky2->net_stats.rx_packets++;
2072 sky2->net_stats.rx_bytes += skb->len;
13210ce5 2073 dev->last_rx = jiffies;
2074
d1f13708 2075#ifdef SKY2_VLAN_TAG_USED
2076 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2077 vlan_hwaccel_receive_skb(skb,
2078 sky2->vlgrp,
2079 be16_to_cpu(sky2->rx_tag));
2080 } else
2081#endif
cd28ab6a 2082 netif_receive_skb(skb);
13210ce5 2083
22e11703
SH		 2084 /* Update receiver after 16 frames */
2085 if (++buf_write[le->link] == RX_BUF_WRITE) {
5df79111
SH		 2086force_update:
2087 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
22e11703
SH		 2088 buf_write[le->link] = 0;
2089 }
2090
2091 /* Stop after net poll weight */
13210ce5 2092 if (++work_done >= to_do)
2093 goto exit_loop;
cd28ab6a
SH		 2094 break;
2095
d1f13708 2096#ifdef SKY2_VLAN_TAG_USED
2097 case OP_RXVLAN:
2098 sky2->rx_tag = length;
2099 break;
2100
2101 case OP_RXCHKSVLAN:
2102 sky2->rx_tag = length;
2103 /* fall through */
2104#endif
cd28ab6a 2105 case OP_RXCHKS:
d11c13e7 2106 skb = sky2->rx_ring[sky2->rx_next].skb;
84fa7933 2107 skb->ip_summed = CHECKSUM_COMPLETE;
f65b138c 2108 skb->csum = status & 0xffff;
cd28ab6a
SH		 2109 break;
2110
2111 case OP_TXINDEXLE:
13b97b74 2112 /* TX index reports status for both ports */
f55925d7
SH		 2113 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2114 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2115 if (hw->dev[1])
2116 sky2_tx_done(hw->dev[1],
2117 ((status >> 24) & 0xff)
2118 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2119 break;
2120
cd28ab6a
SH		 2121 default:
2122 if (net_ratelimit())
793b883e 2123 printk(KERN_WARNING PFX
e71ebd73
SH		 2124 "unknown status opcode 0x%x\n", le->opcode);
2125 goto exit_loop;
cd28ab6a 2126 }
13210ce5 2127 }
cd28ab6a 2128
fe2a24df
SH		 2129 /* Fully processed status ring so clear irq */
2130 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2131
13210ce5 2132exit_loop:
22e11703
SH		 2133 if (buf_write[0]) {
2134 sky2 = netdev_priv(hw->dev[0]);
2135 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2136 }
2137
2138 if (buf_write[1]) {
2139 sky2 = netdev_priv(hw->dev[1]);
2140 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2141 }
2142
e07b1aa8 2143 return work_done;
cd28ab6a
SH		 2144}
2145
2146static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2147{
2148 struct net_device *dev = hw->dev[port];
2149
3be92a70
SH		 2150 if (net_ratelimit())
2151 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2152 dev->name, status);
cd28ab6a
SH		 2153
2154 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2155 if (net_ratelimit())
2156 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2157 dev->name);
cd28ab6a
SH		 2158 /* Clear IRQ */
2159 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2160 }
2161
2162 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2163 if (net_ratelimit())
2164 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2165 dev->name);
cd28ab6a
SH		 2166
2167 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2168 }
2169
2170 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2171 if (net_ratelimit())
2172 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2173 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2174 }
2175
2176 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2177 if (net_ratelimit())
2178 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2179 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2180 }
2181
2182 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2183 if (net_ratelimit())
2184 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2185 dev->name);
cd28ab6a
SH		 2186 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2187 }
2188}
2189
2190static void sky2_hw_intr(struct sky2_hw *hw)
2191{
2192 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2193
793b883e 2194 if (status & Y2_IS_TIST_OV)
cd28ab6a 2195 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2196
2197 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2198 u16 pci_err;
2199
56a645cc 2200 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2201 if (net_ratelimit())
2202 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2203 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2204
2205 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2206 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2207 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2208 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2209 }
2210
2211 if (status & Y2_IS_PCI_EXP) {
d571b694 2212 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2213 u32 pex_err;
2214
7bd656d1 2215 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2216
3be92a70
SH		 2217 if (net_ratelimit())
2218 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2219 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2220
2221 /* clear the interrupt */
2222 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2223 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2224 0xffffffffUL);
cd28ab6a
SH		 2225 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2226
7bd656d1 2227 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2228 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2229 hwmsk &= ~Y2_IS_PCI_EXP;
2230 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2231 }
2232 }
2233
2234 if (status & Y2_HWE_L1_MASK)
2235 sky2_hw_error(hw, 0, status);
2236 status >>= 8;
2237 if (status & Y2_HWE_L1_MASK)
2238 sky2_hw_error(hw, 1, status);
2239}
2240
2241static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2242{
2243 struct net_device *dev = hw->dev[port];
2244 struct sky2_port *sky2 = netdev_priv(dev);
2245 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2246
2247 if (netif_msg_intr(sky2))
2248 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2249 dev->name, status);
2250
2251 if (status & GM_IS_RX_FF_OR) {
2252 ++sky2->net_stats.rx_fifo_errors;
2253 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2254 }
2255
2256 if (status & GM_IS_TX_FF_UR) {
2257 ++sky2->net_stats.tx_fifo_errors;
2258 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2259 }
cd28ab6a
SH		 2260}
2261
d257924e
SH		 2262/* This should never happen it is a fatal situation */
2263static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2264 const char *rxtx, u32 mask)
2265{
2266 struct net_device *dev = hw->dev[port];
2267 struct sky2_port *sky2 = netdev_priv(dev);
2268 u32 imask;
2269
2270 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2271 dev ? dev->name : "<not registered>", rxtx);
2272
2273 imask = sky2_read32(hw, B0_IMSK);
2274 imask &= ~mask;
2275 sky2_write32(hw, B0_IMSK, imask);
2276
2277 if (dev) {
2278 spin_lock(&sky2->phy_lock);
2279 sky2_link_down(sky2);
2280 spin_unlock(&sky2->phy_lock);
2281 }
2282}
cd28ab6a 2283
d27ed387
SH		 2284/* If idle then force a fake soft NAPI poll once a second
2285 * to work around cases where sharing an edge triggered interrupt.
2286 */
eb35cf60
SH		 2287static inline void sky2_idle_start(struct sky2_hw *hw)
2288{
2289 if (idle_timeout > 0)
2290 mod_timer(&hw->idle_timer,
2291 jiffies + msecs_to_jiffies(idle_timeout));
2292}
2293
d27ed387
SH		 2294static void sky2_idle(unsigned long arg)
2295{
01bd7564
SH		 2296 struct sky2_hw *hw = (struct sky2_hw *) arg;
2297 struct net_device *dev = hw->dev[0];
d27ed387 2298
d27ed387
SH		 2299 if (__netif_rx_schedule_prep(dev))
2300 __netif_rx_schedule(dev);
01bd7564
SH		 2301
2302 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2303}
2304
2305
e07b1aa8 2306static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2307{
e07b1aa8
SH		 2308 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2309 int work_limit = min(dev0->quota, *budget);
2310 int work_done = 0;
fb2690a9 2311 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2312
1e5f1283
SH		 2313 if (status & Y2_IS_HW_ERR)
2314 sky2_hw_intr(hw);
d257924e 2315
1e5f1283
SH		 2316 if (status & Y2_IS_IRQ_PHY1)
2317 sky2_phy_intr(hw, 0);
cd28ab6a 2318
1e5f1283
SH		 2319 if (status & Y2_IS_IRQ_PHY2)
2320 sky2_phy_intr(hw, 1);
cd28ab6a 2321
1e5f1283
SH		 2322 if (status & Y2_IS_IRQ_MAC1)
2323 sky2_mac_intr(hw, 0);
cd28ab6a 2324
1e5f1283
SH		 2325 if (status & Y2_IS_IRQ_MAC2)
2326 sky2_mac_intr(hw, 1);
cd28ab6a 2327
1e5f1283
SH		 2328 if (status & Y2_IS_CHK_RX1)
2329 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2330
1e5f1283
SH		 2331 if (status & Y2_IS_CHK_RX2)
2332 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2333
1e5f1283
SH		 2334 if (status & Y2_IS_CHK_TXA1)
2335 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2336
1e5f1283
SH		 2337 if (status & Y2_IS_CHK_TXA2)
2338 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2339
1e5f1283 2340 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2341 if (work_done < work_limit) {
2342 netif_rx_complete(dev0);
86fba634 2343
fe2a24df
SH		 2344 sky2_read32(hw, B0_Y2_SP_LISR);
2345 return 0;
2346 } else {
2347 *budget -= work_done;
2348 dev0->quota -= work_done;
1e5f1283 2349 return 1;
fe2a24df 2350 }
e07b1aa8
SH		 2351}
2352
7d12e780 2353static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2354{
2355 struct sky2_hw *hw = dev_id;
2356 struct net_device *dev0 = hw->dev[0];
2357 u32 status;
2358
2359 /* Reading this mask interrupts as side effect */
2360 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2361 if (status == 0 || status == ~0)
2362 return IRQ_NONE;
793b883e 2363
e07b1aa8
SH		 2364 prefetch(&hw->st_le[hw->st_idx]);
2365 if (likely(__netif_rx_schedule_prep(dev0)))
2366 __netif_rx_schedule(dev0);
793b883e 2367
cd28ab6a
SH		 2368 return IRQ_HANDLED;
2369}
2370
2371#ifdef CONFIG_NET_POLL_CONTROLLER
2372static void sky2_netpoll(struct net_device *dev)
2373{
2374 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2375 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2376
88d11360
SH		 2377 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2378 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2379}
2380#endif
2381
2382/* Chip internal frequency for clock calculations */
fb17358f 2383static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2384{
793b883e 2385 switch (hw->chip_id) {
cd28ab6a 2386 case CHIP_ID_YUKON_EC:
5a5b1ea0 2387 case CHIP_ID_YUKON_EC_U:
fb17358f 2388 return 125; /* 125 Mhz */
cd28ab6a 2389 case CHIP_ID_YUKON_FE:
fb17358f 2390 return 100; /* 100 Mhz */
793b883e 2391 default: /* YUKON_XL */
fb17358f 2392 return 156; /* 156 Mhz */
cd28ab6a
SH		 2393 }
2394}
2395
fb17358f 2396static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2397{
fb17358f 2398 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2399}
2400
fb17358f 2401static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2402{
fb17358f 2403 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2404}
2405
fb17358f 2406
59139528 2407static int sky2_reset(struct sky2_hw *hw)
cd28ab6a 2408{
cd28ab6a 2409 u16 status;
b89165f2 2410 u8 t8;
56a645cc 2411 int i;
cd28ab6a 2412
cd28ab6a 2413 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2414
cd28ab6a
SH		 2415 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2416 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2417 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2418 pci_name(hw->pdev), hw->chip_id);
2419 return -EOPNOTSUPP;
2420 }
2421
290d4de5
SH		 2422 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2423
2424 /* This rev is really old, and requires untested workarounds */
2425 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2426 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2427 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2428 hw->chip_id, hw->chip_rev);
2429 return -EOPNOTSUPP;
2430 }
2431
cd28ab6a
SH		 2432 /* disable ASF */
2433 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2434 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2435 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2436 }
2437
2438 /* do a SW reset */
2439 sky2_write8(hw, B0_CTST, CS_RST_SET);
2440 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2441
2442 /* clear PCI errors, if any */
56a645cc 2443 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2444
cd28ab6a 2445 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2446 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2447
cd28ab6a
SH		 2448
2449 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2450
2451 /* clear any PEX errors */
7bd656d1
SH		 2452 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2453 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2454
cd28ab6a 2455
b89165f2 2456 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
cd28ab6a
SH		 2457 hw->ports = 1;
2458 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2459 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2460 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2461 ++hw->ports;
2462 }
cd28ab6a 2463
ae306cca 2464 sky2_power_on(hw);
cd28ab6a
SH		 2465
2466 for (i = 0; i < hw->ports; i++) {
2467 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2468 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2469 }
2470
2471 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2472
793b883e
SH		 2473 /* Clear I2C IRQ noise */
2474 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2475
2476 /* turn off hardware timer (unused) */
2477 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2478 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2479
cd28ab6a
SH		 2480 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2481
69634ee7
SH		 2482 /* Turn off descriptor polling */
2483 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2484
2485 /* Turn off receive timestamp */
2486 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2487 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2488
2489 /* enable the Tx Arbiters */
2490 for (i = 0; i < hw->ports; i++)
2491 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2492
2493 /* Initialize ram interface */
2494 for (i = 0; i < hw->ports; i++) {
793b883e 2495 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2496
2497 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2498 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2499 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2500 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2501 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2502 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2503 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2504 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2505 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2506 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2507 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2508 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2509 }
2510
7bd656d1 2511 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2512
cd28ab6a 2513 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2514 sky2_gmac_reset(hw, i);
cd28ab6a 2515
cd28ab6a
SH		 2516 memset(hw->st_le, 0, STATUS_LE_BYTES);
2517 hw->st_idx = 0;
2518
2519 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2520 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2521
2522 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2523 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2524
2525 /* Set the list last index */
793b883e 2526 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2527
290d4de5
SH		 2528 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2529 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2530
290d4de5
SH		 2531 /* set Status-FIFO ISR watermark */
2532 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2533 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2534 else
2535 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2536
290d4de5 2537 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2538 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2539 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2540
793b883e 2541 /* enable status unit */
cd28ab6a
SH		 2542 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2543
2544 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2545 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2546 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2547
2548 return 0;
2549}
2550
28bd181a 2551static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2552{
b89165f2
SH		 2553 if (sky2_is_copper(hw)) {
2554 u32 modes = SUPPORTED_10baseT_Half
2555 | SUPPORTED_10baseT_Full
2556 | SUPPORTED_100baseT_Half
2557 | SUPPORTED_100baseT_Full
2558 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2559
2560 if (hw->chip_id != CHIP_ID_YUKON_FE)
2561 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2562 | SUPPORTED_1000baseT_Full;
2563 return modes;
cd28ab6a 2564 } else
b89165f2
SH		 2565 return SUPPORTED_1000baseT_Half
2566 | SUPPORTED_1000baseT_Full
2567 | SUPPORTED_Autoneg
2568 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2569}
2570
793b883e 2571static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2572{
2573 struct sky2_port *sky2 = netdev_priv(dev);
2574 struct sky2_hw *hw = sky2->hw;
2575
2576 ecmd->transceiver = XCVR_INTERNAL;
2577 ecmd->supported = sky2_supported_modes(hw);
2578 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2579 if (sky2_is_copper(hw)) {
cd28ab6a 2580 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2581 | SUPPORTED_10baseT_Full
2582 | SUPPORTED_100baseT_Half
2583 | SUPPORTED_100baseT_Full
2584 | SUPPORTED_1000baseT_Half
2585 | SUPPORTED_1000baseT_Full
2586 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2587 ecmd->port = PORT_TP;
b89165f2
SH		 2588 ecmd->speed = sky2->speed;
2589 } else {
2590 ecmd->speed = SPEED_1000;
cd28ab6a 2591 ecmd->port = PORT_FIBRE;
b89165f2 2592 }
cd28ab6a
SH		 2593
2594 ecmd->advertising = sky2->advertising;
2595 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2596 ecmd->duplex = sky2->duplex;
2597 return 0;
2598}
2599
2600static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2601{
2602 struct sky2_port *sky2 = netdev_priv(dev);
2603 const struct sky2_hw *hw = sky2->hw;
2604 u32 supported = sky2_supported_modes(hw);
2605
2606 if (ecmd->autoneg == AUTONEG_ENABLE) {
2607 ecmd->advertising = supported;
2608 sky2->duplex = -1;
2609 sky2->speed = -1;
2610 } else {
2611 u32 setting;
2612
793b883e 2613 switch (ecmd->speed) {
cd28ab6a
SH		 2614 case SPEED_1000:
2615 if (ecmd->duplex == DUPLEX_FULL)
2616 setting = SUPPORTED_1000baseT_Full;
2617 else if (ecmd->duplex == DUPLEX_HALF)
2618 setting = SUPPORTED_1000baseT_Half;
2619 else
2620 return -EINVAL;
2621 break;
2622 case SPEED_100:
2623 if (ecmd->duplex == DUPLEX_FULL)
2624 setting = SUPPORTED_100baseT_Full;
2625 else if (ecmd->duplex == DUPLEX_HALF)
2626 setting = SUPPORTED_100baseT_Half;
2627 else
2628 return -EINVAL;
2629 break;
2630
2631 case SPEED_10:
2632 if (ecmd->duplex == DUPLEX_FULL)
2633 setting = SUPPORTED_10baseT_Full;
2634 else if (ecmd->duplex == DUPLEX_HALF)
2635 setting = SUPPORTED_10baseT_Half;
2636 else
2637 return -EINVAL;
2638 break;
2639 default:
2640 return -EINVAL;
2641 }
2642
2643 if ((setting & supported) == 0)
2644 return -EINVAL;
2645
2646 sky2->speed = ecmd->speed;
2647 sky2->duplex = ecmd->duplex;
2648 }
2649
2650 sky2->autoneg = ecmd->autoneg;
2651 sky2->advertising = ecmd->advertising;
2652
1b537565
SH		 2653 if (netif_running(dev))
2654 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2655
2656 return 0;
2657}
2658
2659static void sky2_get_drvinfo(struct net_device *dev,
2660 struct ethtool_drvinfo *info)
2661{
2662 struct sky2_port *sky2 = netdev_priv(dev);
2663
2664 strcpy(info->driver, DRV_NAME);
2665 strcpy(info->version, DRV_VERSION);
2666 strcpy(info->fw_version, "N/A");
2667 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2668}
2669
2670static const struct sky2_stat {
793b883e
SH		 2671 char name[ETH_GSTRING_LEN];
2672 u16 offset;
cd28ab6a
SH		 2673} sky2_stats[] = {
2674 { "tx_bytes", GM_TXO_OK_HI },
2675 { "rx_bytes", GM_RXO_OK_HI },
2676 { "tx_broadcast", GM_TXF_BC_OK },
2677 { "rx_broadcast", GM_RXF_BC_OK },
2678 { "tx_multicast", GM_TXF_MC_OK },
2679 { "rx_multicast", GM_RXF_MC_OK },
2680 { "tx_unicast", GM_TXF_UC_OK },
2681 { "rx_unicast", GM_RXF_UC_OK },
2682 { "tx_mac_pause", GM_TXF_MPAUSE },
2683 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2684 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2685 { "late_collision",GM_TXF_LAT_COL },
2686 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2687 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2688 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2689
d2604540 2690 { "rx_short", GM_RXF_SHT },
cd28ab6a 2691 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2692 { "rx_64_byte_packets", GM_RXF_64B },
2693 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2694 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2695 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2696 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2697 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2698 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2699 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2700 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2701 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2702 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2703
2704 { "tx_64_byte_packets", GM_TXF_64B },
2705 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2706 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2707 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2708 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2709 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2710 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2711 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2712};
2713
cd28ab6a
SH		 2714static u32 sky2_get_rx_csum(struct net_device *dev)
2715{
2716 struct sky2_port *sky2 = netdev_priv(dev);
2717
2718 return sky2->rx_csum;
2719}
2720
2721static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2722{
2723 struct sky2_port *sky2 = netdev_priv(dev);
2724
2725 sky2->rx_csum = data;
793b883e 2726
cd28ab6a
SH		 2727 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2728 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2729
2730 return 0;
2731}
2732
2733static u32 sky2_get_msglevel(struct net_device *netdev)
2734{
2735 struct sky2_port *sky2 = netdev_priv(netdev);
2736 return sky2->msg_enable;
2737}
2738
9a7ae0a9
SH		 2739static int sky2_nway_reset(struct net_device *dev)
2740{
2741 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2742
16ad91e1 2743 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2744 return -EINVAL;
2745
1b537565 2746 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2747
2748 return 0;
2749}
2750
793b883e 2751static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2752{
2753 struct sky2_hw *hw = sky2->hw;
2754 unsigned port = sky2->port;
2755 int i;
2756
2757 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2758 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2759 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2760 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2761
793b883e 2762 for (i = 2; i < count; i++)
cd28ab6a
SH		 2763 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2764}
2765
cd28ab6a
SH		 2766static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2767{
2768 struct sky2_port *sky2 = netdev_priv(netdev);
2769 sky2->msg_enable = value;
2770}
2771
2772static int sky2_get_stats_count(struct net_device *dev)
2773{
2774 return ARRAY_SIZE(sky2_stats);
2775}
2776
2777static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2778 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2779{
2780 struct sky2_port *sky2 = netdev_priv(dev);
2781
793b883e 2782 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2783}
2784
793b883e 2785static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2786{
2787 int i;
2788
2789 switch (stringset) {
2790 case ETH_SS_STATS:
2791 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2792 memcpy(data + i * ETH_GSTRING_LEN,
2793 sky2_stats[i].name, ETH_GSTRING_LEN);
2794 break;
2795 }
2796}
2797
cd28ab6a
SH		 2798static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2799{
2800 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2801 return &sky2->net_stats;
2802}
2803
2804static int sky2_set_mac_address(struct net_device *dev, void *p)
2805{
2806 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2807 struct sky2_hw *hw = sky2->hw;
2808 unsigned port = sky2->port;
2809 const struct sockaddr *addr = p;
cd28ab6a
SH		 2810
2811 if (!is_valid_ether_addr(addr->sa_data))
2812 return -EADDRNOTAVAIL;
2813
cd28ab6a 2814 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2815 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2816 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2817 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2818 dev->dev_addr, ETH_ALEN);
1b537565 2819
a8ab1ec0
SH		 2820 /* virtual address for data */
2821 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2822
2823 /* physical address: used for pause frames */
2824 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2825
2826 return 0;
cd28ab6a
SH		 2827}
2828
a052b52f
SH		 2829static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
2830{
2831 u32 bit;
2832
2833 bit = ether_crc(ETH_ALEN, addr) & 63;
2834 filter[bit >> 3] |= 1 << (bit & 7);
2835}
2836
cd28ab6a
SH		 2837static void sky2_set_multicast(struct net_device *dev)
2838{
2839 struct sky2_port *sky2 = netdev_priv(dev);
2840 struct sky2_hw *hw = sky2->hw;
2841 unsigned port = sky2->port;
2842 struct dev_mc_list *list = dev->mc_list;
2843 u16 reg;
2844 u8 filter[8];
a052b52f
SH		 2845 int rx_pause;
2846 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 2847
a052b52f 2848 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 2849 memset(filter, 0, sizeof(filter));
2850
2851 reg = gma_read16(hw, port, GM_RX_CTRL);
2852 reg |= GM_RXCR_UCF_ENA;
2853
d571b694 2854 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2855 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 2856 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 2857 memset(filter, 0xff, sizeof(filter));
a052b52f 2858 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 2859 reg &= ~GM_RXCR_MCF_ENA;
2860 else {
2861 int i;
2862 reg |= GM_RXCR_MCF_ENA;
2863
a052b52f
SH		 2864 if (rx_pause)
2865 sky2_add_filter(filter, pause_mc_addr);
2866
2867 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2868 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 2869 }
2870
cd28ab6a 2871 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2872 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2873 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2874 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2875 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2876 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2877 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2878 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2879
2880 gma_write16(hw, port, GM_RX_CTRL, reg);
2881}
2882
2883/* Can have one global because blinking is controlled by
2884 * ethtool and that is always under RTNL mutex
2885 */
91c86df5 2886static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2887{
793b883e
SH		 2888 u16 pg;
2889
793b883e
SH		 2890 switch (hw->chip_id) {
2891 case CHIP_ID_YUKON_XL:
2892 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2893 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2894 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2895 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2896 PHY_M_LEDC_INIT_CTRL(7) |
2897 PHY_M_LEDC_STA1_CTRL(7) |
2898 PHY_M_LEDC_STA0_CTRL(7))
2899 : 0);
2900
2901 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2902 break;
2903
2904 default:
2905 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 2906 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2907 on ? PHY_M_LED_ALL : 0);
793b883e 2908 }
cd28ab6a
SH		 2909}
2910
2911/* blink LED's for finding board */
2912static int sky2_phys_id(struct net_device *dev, u32 data)
2913{
2914 struct sky2_port *sky2 = netdev_priv(dev);
2915 struct sky2_hw *hw = sky2->hw;
2916 unsigned port = sky2->port;
793b883e 2917 u16 ledctrl, ledover = 0;
cd28ab6a 2918 long ms;
91c86df5 2919 int interrupted;
cd28ab6a
SH		 2920 int onoff = 1;
2921
793b883e 2922 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2923 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2924 else
2925 ms = data * 1000;
2926
2927 /* save initial values */
e07b1aa8 2928 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2929 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2930 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2931 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2932 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2933 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2934 } else {
2935 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2936 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2937 }
cd28ab6a 2938
91c86df5
SH		 2939 interrupted = 0;
2940 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2941 sky2_led(hw, port, onoff);
2942 onoff = !onoff;
2943
e07b1aa8 2944 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2945 interrupted = msleep_interruptible(250);
e07b1aa8 2946 spin_lock_bh(&sky2->phy_lock);
91c86df5 2947
cd28ab6a
SH		 2948 ms -= 250;
2949 }
2950
2951 /* resume regularly scheduled programming */
793b883e
SH		 2952 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2953 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2954 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2955 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2956 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2957 } else {
2958 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2959 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2960 }
e07b1aa8 2961 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2962
2963 return 0;
2964}
2965
2966static void sky2_get_pauseparam(struct net_device *dev,
2967 struct ethtool_pauseparam *ecmd)
2968{
2969 struct sky2_port *sky2 = netdev_priv(dev);
2970
16ad91e1
SH		 2971 switch (sky2->flow_mode) {
2972 case FC_NONE:
2973 ecmd->tx_pause = ecmd->rx_pause = 0;
2974 break;
2975 case FC_TX:
2976 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
2977 break;
2978 case FC_RX:
2979 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
2980 break;
2981 case FC_BOTH:
2982 ecmd->tx_pause = ecmd->rx_pause = 1;
2983 }
2984
cd28ab6a
SH		 2985 ecmd->autoneg = sky2->autoneg;
2986}
2987
2988static int sky2_set_pauseparam(struct net_device *dev,
2989 struct ethtool_pauseparam *ecmd)
2990{
2991 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2992
2993 sky2->autoneg = ecmd->autoneg;
16ad91e1 2994 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 2995
16ad91e1
SH		 2996 if (netif_running(dev))
2997 sky2_phy_reinit(sky2);
cd28ab6a 2998
2eaba1a2 2999 return 0;
cd28ab6a
SH		 3000}
3001
fb17358f
SH		 3002static int sky2_get_coalesce(struct net_device *dev,
3003 struct ethtool_coalesce *ecmd)
3004{
3005 struct sky2_port *sky2 = netdev_priv(dev);
3006 struct sky2_hw *hw = sky2->hw;
3007
3008 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3009 ecmd->tx_coalesce_usecs = 0;
3010 else {
3011 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3012 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3013 }
3014 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3015
3016 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3017 ecmd->rx_coalesce_usecs = 0;
3018 else {
3019 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3020 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3021 }
3022 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3023
3024 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3025 ecmd->rx_coalesce_usecs_irq = 0;
3026 else {
3027 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3028 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3029 }
3030
3031 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3032
3033 return 0;
3034}
3035
3036/* Note: this affect both ports */
3037static int sky2_set_coalesce(struct net_device *dev,
3038 struct ethtool_coalesce *ecmd)
3039{
3040 struct sky2_port *sky2 = netdev_priv(dev);
3041 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3042 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3043
77b3d6a2
SH		 3044 if (ecmd->tx_coalesce_usecs > tmax ||
3045 ecmd->rx_coalesce_usecs > tmax ||
3046 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3047 return -EINVAL;
3048
ff81fbbe 3049 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3050 return -EINVAL;
ff81fbbe 3051 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3052 return -EINVAL;
ff81fbbe 3053 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3054 return -EINVAL;
3055
3056 if (ecmd->tx_coalesce_usecs == 0)
3057 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3058 else {
3059 sky2_write32(hw, STAT_TX_TIMER_INI,
3060 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3061 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3062 }
3063 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3064
3065 if (ecmd->rx_coalesce_usecs == 0)
3066 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3067 else {
3068 sky2_write32(hw, STAT_LEV_TIMER_INI,
3069 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3070 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3071 }
3072 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3073
3074 if (ecmd->rx_coalesce_usecs_irq == 0)
3075 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3076 else {
d28d4870 3077 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3078 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3079 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3080 }
3081 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3082 return 0;
3083}
3084
793b883e
SH		 3085static void sky2_get_ringparam(struct net_device *dev,
3086 struct ethtool_ringparam *ering)
3087{
3088 struct sky2_port *sky2 = netdev_priv(dev);
3089
3090 ering->rx_max_pending = RX_MAX_PENDING;
3091 ering->rx_mini_max_pending = 0;
3092 ering->rx_jumbo_max_pending = 0;
3093 ering->tx_max_pending = TX_RING_SIZE - 1;
3094
3095 ering->rx_pending = sky2->rx_pending;
3096 ering->rx_mini_pending = 0;
3097 ering->rx_jumbo_pending = 0;
3098 ering->tx_pending = sky2->tx_pending;
3099}
3100
3101static int sky2_set_ringparam(struct net_device *dev,
3102 struct ethtool_ringparam *ering)
3103{
3104 struct sky2_port *sky2 = netdev_priv(dev);
3105 int err = 0;
3106
3107 if (ering->rx_pending > RX_MAX_PENDING ||
3108 ering->rx_pending < 8 ||
3109 ering->tx_pending < MAX_SKB_TX_LE ||
3110 ering->tx_pending > TX_RING_SIZE - 1)
3111 return -EINVAL;
3112
3113 if (netif_running(dev))
3114 sky2_down(dev);
3115
3116 sky2->rx_pending = ering->rx_pending;
3117 sky2->tx_pending = ering->tx_pending;
3118
1b537565 3119 if (netif_running(dev)) {
793b883e 3120 err = sky2_up(dev);
1b537565
SH		 3121 if (err)
3122 dev_close(dev);
6ed995bb
SH		 3123 else
3124 sky2_set_multicast(dev);
1b537565 3125 }
793b883e
SH		 3126
3127 return err;
3128}
3129
793b883e
SH		 3130static int sky2_get_regs_len(struct net_device *dev)
3131{
6e4cbb34 3132 return 0x4000;
793b883e
SH		 3133}
3134
3135/*
3136 * Returns copy of control register region
6e4cbb34 3137 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3138 */
3139static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3140 void *p)
3141{
3142 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3143 const void __iomem *io = sky2->hw->regs;
793b883e 3144
6e4cbb34 3145 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3146 regs->version = 1;
6e4cbb34 3147 memset(p, 0, regs->len);
793b883e 3148
6e4cbb34
SH		 3149 memcpy_fromio(p, io, B3_RAM_ADDR);
3150
3151 memcpy_fromio(p + B3_RI_WTO_R1,
3152 io + B3_RI_WTO_R1,
3153 regs->len - B3_RI_WTO_R1);
793b883e 3154}
cd28ab6a 3155
7282d491 3156static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3157 .get_settings = sky2_get_settings,
3158 .set_settings = sky2_set_settings,
3159 .get_drvinfo = sky2_get_drvinfo,
3160 .get_msglevel = sky2_get_msglevel,
3161 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3162 .nway_reset = sky2_nway_reset,
793b883e
SH		 3163 .get_regs_len = sky2_get_regs_len,
3164 .get_regs = sky2_get_regs,
3165 .get_link = ethtool_op_get_link,
3166 .get_sg = ethtool_op_get_sg,
3167 .set_sg = ethtool_op_set_sg,
3168 .get_tx_csum = ethtool_op_get_tx_csum,
3169 .set_tx_csum = ethtool_op_set_tx_csum,
3170 .get_tso = ethtool_op_get_tso,
3171 .set_tso = ethtool_op_set_tso,
3172 .get_rx_csum = sky2_get_rx_csum,
3173 .set_rx_csum = sky2_set_rx_csum,
3174 .get_strings = sky2_get_strings,
fb17358f
SH		 3175 .get_coalesce = sky2_get_coalesce,
3176 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3177 .get_ringparam = sky2_get_ringparam,
3178 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3179 .get_pauseparam = sky2_get_pauseparam,
3180 .set_pauseparam = sky2_set_pauseparam,
793b883e 3181 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3182 .get_stats_count = sky2_get_stats_count,
3183 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3184 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3185};
3186
3187/* Initialize network device */
3188static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3189 unsigned port, int highmem)
3190{
3191 struct sky2_port *sky2;
3192 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3193
3194 if (!dev) {
3195 printk(KERN_ERR "sky2 etherdev alloc failed");
3196 return NULL;
3197 }
3198
3199 SET_MODULE_OWNER(dev);
3200 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3201 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3202 dev->open = sky2_up;
3203 dev->stop = sky2_down;
ef743d33 3204 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3205 dev->hard_start_xmit = sky2_xmit_frame;
3206 dev->get_stats = sky2_get_stats;
3207 dev->set_multicast_list = sky2_set_multicast;
3208 dev->set_mac_address = sky2_set_mac_address;
3209 dev->change_mtu = sky2_change_mtu;
3210 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3211 dev->tx_timeout = sky2_tx_timeout;
3212 dev->watchdog_timeo = TX_WATCHDOG;
3213 if (port == 0)
3214 dev->poll = sky2_poll;
3215 dev->weight = NAPI_WEIGHT;
3216#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3217 /* Network console (only works on port 0)
3218 * because netpoll makes assumptions about NAPI
3219 */
3220 if (port == 0)
3221 dev->poll_controller = sky2_netpoll;
cd28ab6a 3222#endif
cd28ab6a
SH		 3223
3224 sky2 = netdev_priv(dev);
3225 sky2->netdev = dev;
3226 sky2->hw = hw;
3227 sky2->msg_enable = netif_msg_init(debug, default_msg);
3228
cd28ab6a
SH		 3229 /* Auto speed and flow control */
3230 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3231 sky2->flow_mode = FC_BOTH;
3232
cd28ab6a
SH		 3233 sky2->duplex = -1;
3234 sky2->speed = -1;
3235 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3236 sky2->rx_csum = 1;
75d070c5 3237
e07b1aa8 3238 spin_lock_init(&sky2->phy_lock);
793b883e 3239 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3240 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3241
3242 hw->dev[port] = dev;
3243
3244 sky2->port = port;
3245
5a5b1ea0 3246 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3247 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3248 if (highmem)
3249 dev->features |= NETIF_F_HIGHDMA;
793b883e 3250 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3251
d1f13708 3252#ifdef SKY2_VLAN_TAG_USED
3253 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3254 dev->vlan_rx_register = sky2_vlan_rx_register;
3255 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3256#endif
3257
cd28ab6a 3258 /* read the mac address */
793b883e 3259 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3260 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3261
3262 /* device is off until link detection */
3263 netif_carrier_off(dev);
3264 netif_stop_queue(dev);
3265
3266 return dev;
3267}
3268
28bd181a 3269static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3270{
3271 const struct sky2_port *sky2 = netdev_priv(dev);
3272
3273 if (netif_msg_probe(sky2))
3274 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3275 dev->name,
3276 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3277 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3278}
3279
fb2690a9 3280/* Handle software interrupt used during MSI test */
7d12e780 3281static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3282{
3283 struct sky2_hw *hw = dev_id;
3284 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3285
3286 if (status == 0)
3287 return IRQ_NONE;
3288
3289 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3290 hw->msi = 1;
fb2690a9
SH		 3291 wake_up(&hw->msi_wait);
3292 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3293 }
3294 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3295
3296 return IRQ_HANDLED;
3297}
3298
3299/* Test interrupt path by forcing a a software IRQ */
3300static int __devinit sky2_test_msi(struct sky2_hw *hw)
3301{
3302 struct pci_dev *pdev = hw->pdev;
3303 int err;
3304
bb507fe1 3305 init_waitqueue_head (&hw->msi_wait);
3306
fb2690a9
SH		 3307 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3308
b0a20ded 3309 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9
SH		 3310 if (err) {
3311 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3312 pci_name(pdev), pdev->irq);
3313 return err;
3314 }
3315
fb2690a9 3316 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3317 sky2_read8(hw, B0_CTST);
fb2690a9 3318
b0a20ded 3319 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3320
b0a20ded 3321 if (!hw->msi) {
fb2690a9 3322 /* MSI test failed, go back to INTx mode */
2bffc23a
SH		 3323 printk(KERN_INFO PFX "%s: No interrupt generated using MSI, "
3324 "switching to INTx mode.\n",
fb2690a9
SH		 3325 pci_name(pdev));
3326
3327 err = -EOPNOTSUPP;
3328 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3329 }
3330
3331 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3332 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3333
3334 free_irq(pdev->irq, hw);
3335
3336 return err;
3337}
3338
cd28ab6a
SH		 3339static int __devinit sky2_probe(struct pci_dev *pdev,
3340 const struct pci_device_id *ent)
3341{
7f60c64b 3342 struct net_device *dev;
cd28ab6a 3343 struct sky2_hw *hw;
ae306cca 3344 int err, using_dac = 0;
cd28ab6a 3345
793b883e
SH		 3346 err = pci_enable_device(pdev);
3347 if (err) {
cd28ab6a
SH		 3348 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3349 pci_name(pdev));
3350 goto err_out;
3351 }
3352
793b883e
SH		 3353 err = pci_request_regions(pdev, DRV_NAME);
3354 if (err) {
cd28ab6a
SH		 3355 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3356 pci_name(pdev));
793b883e 3357 goto err_out;
cd28ab6a
SH		 3358 }
3359
3360 pci_set_master(pdev);
3361
d1f3d4dd
SH		 3362 if (sizeof(dma_addr_t) > sizeof(u32) &&
3363 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3364 using_dac = 1;
3365 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3366 if (err < 0) {
3367 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3368 "for consistent allocations\n", pci_name(pdev));
3369 goto err_out_free_regions;
3370 }
cd28ab6a 3371
d1f3d4dd 3372 } else {
cd28ab6a
SH		 3373 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3374 if (err) {
3375 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3376 pci_name(pdev));
3377 goto err_out_free_regions;
3378 }
3379 }
d1f3d4dd 3380
cd28ab6a 3381 err = -ENOMEM;
6aad85d6 3382 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3383 if (!hw) {
3384 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3385 pci_name(pdev));
3386 goto err_out_free_regions;
3387 }
3388
cd28ab6a 3389 hw->pdev = pdev;
cd28ab6a
SH		 3390
3391 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3392 if (!hw->regs) {
3393 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3394 pci_name(pdev));
3395 goto err_out_free_hw;
3396 }
3397
56a645cc 3398#ifdef __BIG_ENDIAN
f65b138c
SH		 3399 /* The sk98lin vendor driver uses hardware byte swapping but
3400 * this driver uses software swapping.
3401 */
56a645cc
SH		 3402 {
3403 u32 reg;
56a645cc 3404 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3405 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3406 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3407 }
3408#endif
3409
08c06d8a
SH		 3410 /* ring for status responses */
3411 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3412 &hw->st_dma);
3413 if (!hw->st_le)
3414 goto err_out_iounmap;
3415
cd28ab6a
SH		 3416 err = sky2_reset(hw);
3417 if (err)
793b883e 3418 goto err_out_iounmap;
cd28ab6a 3419
7c7459d1
GKH		 3420 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3421 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3422 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3423 hw->chip_id, hw->chip_rev);
cd28ab6a 3424
793b883e 3425 dev = sky2_init_netdev(hw, 0, using_dac);
7f60c64b 3426 if (!dev) {
3427 err = -ENOMEM;
cd28ab6a 3428 goto err_out_free_pci;
7f60c64b 3429 }
cd28ab6a 3430
9fa1b1f3
SH		 3431 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3432 err = sky2_test_msi(hw);
3433 if (err == -EOPNOTSUPP)
3434 pci_disable_msi(pdev);
3435 else if (err)
3436 goto err_out_free_netdev;
3437 }
3438
793b883e
SH		 3439 err = register_netdev(dev);
3440 if (err) {
cd28ab6a
SH		 3441 printk(KERN_ERR PFX "%s: cannot register net device\n",
3442 pci_name(pdev));
3443 goto err_out_free_netdev;
3444 }
3445
b0a20ded
SH		 3446 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3447 dev->name, hw);
9fa1b1f3
SH		 3448 if (err) {
3449 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3450 pci_name(pdev), pdev->irq);
3451 goto err_out_unregister;
3452 }
3453 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3454
cd28ab6a
SH		 3455 sky2_show_addr(dev);
3456
7f60c64b 3457 if (hw->ports > 1) {
3458 struct net_device *dev1;
3459
3460 dev1 = sky2_init_netdev(hw, 1, using_dac);
3461 if (!dev1) {
3462 printk(KERN_WARNING PFX
3463 "allocation of second port failed\n");
3464 }
3465 else if (!(err = register_netdev(dev1)))
cd28ab6a
SH		 3466 sky2_show_addr(dev1);
3467 else {
793b883e 3468 printk(KERN_WARNING PFX
7f60c64b 3469 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 3470 hw->dev[1] = NULL;
3471 free_netdev(dev1);
3472 }
3473 }
3474
01bd7564 3475 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
eb35cf60 3476 sky2_idle_start(hw);
d27ed387 3477
793b883e
SH		 3478 pci_set_drvdata(pdev, hw);
3479
cd28ab6a
SH		 3480 return 0;
3481
793b883e 3482err_out_unregister:
b0a20ded
SH		 3483 if (hw->msi)
3484 pci_disable_msi(pdev);
793b883e 3485 unregister_netdev(dev);
cd28ab6a
SH		 3486err_out_free_netdev:
3487 free_netdev(dev);
cd28ab6a 3488err_out_free_pci:
793b883e 3489 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3490 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3491err_out_iounmap:
3492 iounmap(hw->regs);
3493err_out_free_hw:
3494 kfree(hw);
3495err_out_free_regions:
3496 pci_release_regions(pdev);
cd28ab6a 3497 pci_disable_device(pdev);
cd28ab6a
SH		 3498err_out:
3499 return err;
3500}
3501
3502static void __devexit sky2_remove(struct pci_dev *pdev)
3503{
793b883e 3504 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3505 struct net_device *dev0, *dev1;
3506
793b883e 3507 if (!hw)
cd28ab6a
SH		 3508 return;
3509
d27ed387
SH		 3510 del_timer_sync(&hw->idle_timer);
3511
3512 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3513 synchronize_irq(hw->pdev->irq);
3514
cd28ab6a 3515 dev0 = hw->dev[0];
793b883e
SH		 3516 dev1 = hw->dev[1];
3517 if (dev1)
3518 unregister_netdev(dev1);
cd28ab6a
SH		 3519 unregister_netdev(dev0);
3520
ae306cca
SH		 3521 sky2_power_aux(hw);
3522
cd28ab6a 3523 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3524 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3525 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3526
3527 free_irq(pdev->irq, hw);
b0a20ded
SH		 3528 if (hw->msi)
3529 pci_disable_msi(pdev);
793b883e 3530 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3531 pci_release_regions(pdev);
3532 pci_disable_device(pdev);
793b883e 3533
cd28ab6a
SH		 3534 if (dev1)
3535 free_netdev(dev1);
3536 free_netdev(dev0);
3537 iounmap(hw->regs);
3538 kfree(hw);
5afa0a9c 3539
cd28ab6a
SH		 3540 pci_set_drvdata(pdev, NULL);
3541}
3542
3543#ifdef CONFIG_PM
3544static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3545{
793b883e 3546 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3547 int i;
cd28ab6a 3548
eb35cf60 3549 del_timer_sync(&hw->idle_timer);
6a5706b9 3550 netif_poll_disable(hw->dev[0]);
eb35cf60 3551
f05267e7 3552 for (i = 0; i < hw->ports; i++) {
cd28ab6a
SH		 3553 struct net_device *dev = hw->dev[i];
3554
6a5706b9 3555 if (netif_running(dev)) {
5afa0a9c 3556 sky2_down(dev);
cd28ab6a 3557 netif_device_detach(dev);
cd28ab6a
SH		 3558 }
3559 }
3560
8ab8fca2 3561 sky2_write32(hw, B0_IMSK, 0);
ae306cca 3562 sky2_power_aux(hw);
d374c1c1 3563 pci_save_state(pdev);
ae306cca
SH		 3564 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3565
2ccc99b7 3566 return 0;
cd28ab6a
SH		 3567}
3568
3569static int sky2_resume(struct pci_dev *pdev)
3570{
793b883e 3571 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3572 int i, err;
cd28ab6a 3573
ae306cca
SH		 3574 err = pci_set_power_state(pdev, PCI_D0);
3575 if (err)
3576 goto out;
3577
3578 err = pci_restore_state(pdev);
3579 if (err)
3580 goto out;
3581
cd28ab6a
SH		 3582 pci_enable_wake(pdev, PCI_D0, 0);
3583
08c06d8a
SH		 3584 err = sky2_reset(hw);
3585 if (err)
3586 goto out;
cd28ab6a 3587
8ab8fca2
SH		 3588 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3589
f05267e7 3590 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3591 struct net_device *dev = hw->dev[i];
6a5706b9 3592 if (netif_running(dev)) {
08c06d8a 3593 netif_device_attach(dev);
88d11360 3594
08c06d8a
SH		 3595 err = sky2_up(dev);
3596 if (err) {
3597 printk(KERN_ERR PFX "%s: could not up: %d\n",
3598 dev->name, err);
3599 dev_close(dev);
eb35cf60 3600 goto out;
5afa0a9c 3601 }
cd28ab6a
SH		 3602 }
3603 }
eb35cf60 3604
6a5706b9 3605 netif_poll_enable(hw->dev[0]);
eb35cf60 3606 sky2_idle_start(hw);
ae306cca 3607 return 0;
08c06d8a 3608out:
ae306cca
SH		 3609 printk(KERN_ERR PFX "%s: resume failed (%d)\n", pci_name(pdev), err);
3610 pci_disable_device(pdev);
08c06d8a 3611 return err;
cd28ab6a
SH		 3612}
3613#endif
3614
3615static struct pci_driver sky2_driver = {
793b883e
SH		 3616 .name = DRV_NAME,
3617 .id_table = sky2_id_table,
3618 .probe = sky2_probe,
3619 .remove = __devexit_p(sky2_remove),
cd28ab6a 3620#ifdef CONFIG_PM
793b883e
SH		 3621 .suspend = sky2_suspend,
3622 .resume = sky2_resume,
cd28ab6a
SH		 3623#endif
3624};
3625
3626static int __init sky2_init_module(void)
3627{
50241c4c 3628 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3629}
3630
3631static void __exit sky2_cleanup_module(void)
3632{
3633 pci_unregister_driver(&sky2_driver);
3634}
3635
3636module_init(sky2_init_module);
3637module_exit(sky2_cleanup_module);
3638
3639MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 3640MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 3641MODULE_LICENSE("GPL");
5f4f9dc1 3642MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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