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[PATCH] sky2: add comments to PCI ids
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
ef743d33 41#include <linux/mii.h>
cd28ab6a
SH		 42
43#include <asm/irq.h>
44
d1f13708 45#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
46#define SKY2_VLAN_TAG_USED 1
47#endif
48
cd28ab6a
SH		 49#include "sky2.h"
50
51#define DRV_NAME "sky2"
52c89cac 52#define DRV_VERSION "1.10"
cd28ab6a
SH		 53#define PFX DRV_NAME " "
54
55/*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
14d0263f 58 * similar to Tigon3.
cd28ab6a
SH		 59 */
60
14d0263f 61#define RX_LE_SIZE 1024
cd28ab6a 62#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 63#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 64#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 65#define RX_SKB_ALIGN 8
22e11703 66#define RX_BUF_WRITE 16
793b883e
SH		 67
68#define TX_RING_SIZE 512
69#define TX_DEF_PENDING (TX_RING_SIZE - 1)
70#define TX_MIN_PENDING 64
b19666d9 71#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 72
793b883e 73#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 74#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 75#define TX_WATCHDOG (5 * HZ)
76#define NAPI_WEIGHT 64
77#define PHY_RETRIES 1000
78
cb5d9547
SH		 79#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
80
cd28ab6a 81static const u32 default_msg =
793b883e
SH		 82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 85
793b883e 86static int debug = -1; /* defaults above */
cd28ab6a
SH		 87module_param(debug, int, 0);
88MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
14d0263f 90static int copybreak __read_mostly = 128;
bdb5c58e
SH		 91module_param(copybreak, int, 0);
92MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
fb2690a9
SH		 94static int disable_msi = 0;
95module_param(disable_msi, int, 0);
96MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
e561a83b 98static int idle_timeout = 0;
01bd7564 99module_param(idle_timeout, int, 0);
e561a83b 100MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 101
cd28ab6a 102static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
e5b74c7d
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
cd28ab6a
SH		 129 { 0 }
130};
793b883e 131
cd28ab6a
SH		 132MODULE_DEVICE_TABLE(pci, sky2_id_table);
133
134/* Avoid conditionals by using array */
135static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
136static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 137static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 138
92f965e8
SH		 139/* This driver supports yukon2 chipset only */
140static const char *yukon2_name[] = {
141 "XL", /* 0xb3 */
142 "EC Ultra", /* 0xb4 */
143 "UNKNOWN", /* 0xb5 */
144 "EC", /* 0xb6 */
145 "FE", /* 0xb7 */
793b883e
SH		 146};
147
793b883e 148/* Access to external PHY */
ef743d33 149static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 150{
151 int i;
152
153 gma_write16(hw, port, GM_SMI_DATA, val);
154 gma_write16(hw, port, GM_SMI_CTRL,
155 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
156
157 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 158 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 159 return 0;
793b883e 160 udelay(1);
cd28ab6a 161 }
ef743d33 162
793b883e 163 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 164 return -ETIMEDOUT;
cd28ab6a
SH		 165}
166
ef743d33 167static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 168{
169 int i;
170
793b883e 171 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 172 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
173
174 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33 175 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
176 *val = gma_read16(hw, port, GM_SMI_DATA);
177 return 0;
178 }
179
793b883e 180 udelay(1);
cd28ab6a
SH		 181 }
182
ef743d33 183 return -ETIMEDOUT;
184}
185
186static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
187{
188 u16 v;
189
190 if (__gm_phy_read(hw, port, reg, &v) != 0)
191 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
192 return v;
cd28ab6a
SH		 193}
194
2ccc99b7 195static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
5afa0a9c 196{
197 u16 power_control;
5afa0a9c 198 int vaux;
5afa0a9c 199
200 pr_debug("sky2_set_power_state %d\n", state);
201 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
202
56a645cc 203 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 204 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c 205 (power_control & PCI_PM_CAP_PME_D3cold);
206
56a645cc 207 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c 208
209 power_control |= PCI_PM_CTRL_PME_STATUS;
210 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
211
212 switch (state) {
213 case PCI_D0:
214 /* switch power to VCC (WA for VAUX problem) */
215 sky2_write8(hw, B0_POWER_CTRL,
216 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
217
218 /* disable Core Clock Division, */
219 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
220
221 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
222 /* enable bits are inverted */
223 sky2_write8(hw, B2_Y2_CLK_GATE,
224 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
225 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
226 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
227 else
228 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
229
977bdf06 230 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
d3bcfbeb 231 u32 reg1;
232
56a645cc
SH		 233 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
234 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 235 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 236 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
237 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 238 }
239
5afa0a9c 240 break;
241
242 case PCI_D3hot:
243 case PCI_D3cold:
5afa0a9c 244 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
245 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
246 else
247 /* enable bits are inverted */
248 sky2_write8(hw, B2_Y2_CLK_GATE,
249 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
250 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
251 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
252
253 /* switch power to VAUX */
254 if (vaux && state != PCI_D3cold)
255 sky2_write8(hw, B0_POWER_CTRL,
256 (PC_VAUX_ENA | PC_VCC_ENA |
257 PC_VAUX_ON | PC_VCC_OFF));
258 break;
259 default:
260 printk(KERN_ERR PFX "Unknown power state %d\n", state);
5afa0a9c 261 }
262
56a645cc 263 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c 264 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
5afa0a9c 265}
266
d3bcfbeb 267static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 268{
269 u16 reg;
270
271 /* disable all GMAC IRQ's */
272 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
273 /* disable PHY IRQs */
274 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 275
cd28ab6a
SH		 276 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
277 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
278 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
279 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
280
281 reg = gma_read16(hw, port, GM_RX_CTRL);
282 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
283 gma_write16(hw, port, GM_RX_CTRL, reg);
284}
285
16ad91e1
SH		 286/* flow control to advertise bits */
287static const u16 copper_fc_adv[] = {
288 [FC_NONE] = 0,
289 [FC_TX] = PHY_M_AN_ASP,
290 [FC_RX] = PHY_M_AN_PC,
291 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
292};
293
294/* flow control to advertise bits when using 1000BaseX */
295static const u16 fiber_fc_adv[] = {
296 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
297 [FC_TX] = PHY_M_P_ASYM_MD_X,
298 [FC_RX] = PHY_M_P_SYM_MD_X,
299 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
300};
301
302/* flow control to GMA disable bits */
303static const u16 gm_fc_disable[] = {
304 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
305 [FC_TX] = GM_GPCR_FC_RX_DIS,
306 [FC_RX] = GM_GPCR_FC_TX_DIS,
307 [FC_BOTH] = 0,
308};
309
310
cd28ab6a
SH		 311static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
312{
313 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 314 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 315
ed6d32c7 316 if (sky2->autoneg == AUTONEG_ENABLE &&
86a31a75 317 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 318 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
319
320 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 321 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 322 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
323
324 if (hw->chip_id == CHIP_ID_YUKON_EC)
325 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
326 else
327 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
328
329 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
330 }
331
332 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 333 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 334 if (hw->chip_id == CHIP_ID_YUKON_FE) {
335 /* enable automatic crossover */
336 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
337 } else {
338 /* disable energy detect */
339 ctrl &= ~PHY_M_PC_EN_DET_MSK;
340
341 /* enable automatic crossover */
342 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
343
344 if (sky2->autoneg == AUTONEG_ENABLE &&
ed6d32c7 345 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 346 ctrl &= ~PHY_M_PC_DSC_MSK;
347 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
348 }
349 }
cd28ab6a
SH		 350 } else {
351 /* workaround for deviation #4.88 (CRC errors) */
352 /* disable Automatic Crossover */
353
354 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 355 }
cd28ab6a 356
b89165f2
SH		 357 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
358
359 /* special setup for PHY 88E1112 Fiber */
360 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
361 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 362
b89165f2
SH		 363 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
364 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
365 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
366 ctrl &= ~PHY_M_MAC_MD_MSK;
367 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
368 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
369
370 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 371 /* select page 1 to access Fiber registers */
372 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 373
374 /* for SFP-module set SIGDET polarity to low */
375 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
376 ctrl |= PHY_M_FIB_SIGD_POL;
377 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
cd28ab6a 378 }
b89165f2
SH		 379
380 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 381 }
382
7800fddc 383 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 384 ct1000 = 0;
385 adv = PHY_AN_CSMA;
2eaba1a2 386 reg = 0;
cd28ab6a
SH		 387
388 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 389 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 390 if (sky2->advertising & ADVERTISED_1000baseT_Full)
391 ct1000 |= PHY_M_1000C_AFD;
392 if (sky2->advertising & ADVERTISED_1000baseT_Half)
393 ct1000 |= PHY_M_1000C_AHD;
394 if (sky2->advertising & ADVERTISED_100baseT_Full)
395 adv |= PHY_M_AN_100_FD;
396 if (sky2->advertising & ADVERTISED_100baseT_Half)
397 adv |= PHY_M_AN_100_HD;
398 if (sky2->advertising & ADVERTISED_10baseT_Full)
399 adv |= PHY_M_AN_10_FD;
400 if (sky2->advertising & ADVERTISED_10baseT_Half)
401 adv |= PHY_M_AN_10_HD;
709c6e7b 402
16ad91e1 403 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 404 } else { /* special defines for FIBER (88E1040S only) */
405 if (sky2->advertising & ADVERTISED_1000baseT_Full)
406 adv |= PHY_M_AN_1000X_AFD;
407 if (sky2->advertising & ADVERTISED_1000baseT_Half)
408 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 409
16ad91e1 410 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 411 }
cd28ab6a
SH		 412
413 /* Restart Auto-negotiation */
414 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
415 } else {
416 /* forced speed/duplex settings */
417 ct1000 = PHY_M_1000C_MSE;
418
2eaba1a2
SH		 419 /* Disable auto update for duplex flow control and speed */
420 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 421
422 switch (sky2->speed) {
423 case SPEED_1000:
424 ctrl |= PHY_CT_SP1000;
2eaba1a2 425 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 426 break;
427 case SPEED_100:
428 ctrl |= PHY_CT_SP100;
2eaba1a2 429 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 430 break;
431 }
432
2eaba1a2
SH		 433 if (sky2->duplex == DUPLEX_FULL) {
434 reg |= GM_GPCR_DUP_FULL;
435 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 436 } else if (sky2->speed < SPEED_1000)
437 sky2->flow_mode = FC_NONE;
2eaba1a2 438
2eaba1a2 439
16ad91e1 440 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 441
442 /* Forward pause packets to GMAC? */
16ad91e1 443 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 444 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
445 else
446 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 447 }
448
2eaba1a2
SH		 449 gma_write16(hw, port, GM_GP_CTRL, reg);
450
cd28ab6a
SH		 451 if (hw->chip_id != CHIP_ID_YUKON_FE)
452 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
453
454 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
455 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
456
457 /* Setup Phy LED's */
458 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
459 ledover = 0;
460
461 switch (hw->chip_id) {
462 case CHIP_ID_YUKON_FE:
463 /* on 88E3082 these bits are at 11..9 (shifted left) */
464 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
465
466 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
467
468 /* delete ACT LED control bits */
469 ctrl &= ~PHY_M_FELP_LED1_MSK;
470 /* change ACT LED control to blink mode */
471 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
472 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
473 break;
474
475 case CHIP_ID_YUKON_XL:
793b883e 476 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 477
478 /* select page 3 to access LED control register */
479 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
480
481 /* set LED Function Control register */
ed6d32c7
SH		 482 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
483 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
484 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
485 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
486 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 487
488 /* set Polarity Control register */
489 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 490 (PHY_M_POLC_LS1_P_MIX(4) |
491 PHY_M_POLC_IS0_P_MIX(4) |
492 PHY_M_POLC_LOS_CTRL(2) |
493 PHY_M_POLC_INIT_CTRL(2) |
494 PHY_M_POLC_STA1_CTRL(2) |
495 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 496
497 /* restore page register */
793b883e 498 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 499 break;
ed6d32c7
SH		 500 case CHIP_ID_YUKON_EC_U:
501 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
502
503 /* select page 3 to access LED control register */
504 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
505
506 /* set LED Function Control register */
507 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
508 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
509 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
510 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
511 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
512
513 /* set Blink Rate in LED Timer Control Register */
514 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
515 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
516 /* restore page register */
517 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
518 break;
cd28ab6a
SH		 519
520 default:
521 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
522 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
523 /* turn off the Rx LED (LED_RX) */
524 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
525 }
526
ed6d32c7 527 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 528 /* apply fixes in PHY AFE */
ed6d32c7
SH		 529 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
530 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
531
977bdf06 532 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 533 gm_phy_write(hw, port, 0x18, 0xaa99);
534 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 535
977bdf06 536 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 537 gm_phy_write(hw, port, 0x18, 0xa204);
538 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 539
540 /* set page register to 0 */
ed6d32c7 541 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
977bdf06
SH		 542 } else {
543 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 544
977bdf06
SH		 545 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
546 /* turn on 100 Mbps LED (LED_LINK100) */
547 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
548 }
cd28ab6a 549
977bdf06
SH		 550 if (ledover)
551 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
552
553 }
2eaba1a2 554
d571b694 555 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 556 if (sky2->autoneg == AUTONEG_ENABLE)
557 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
558 else
559 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
560}
561
d3bcfbeb 562static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
563{
564 u32 reg1;
565 static const u32 phy_power[]
566 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
567
568 /* looks like this XL is back asswards .. */
569 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
570 onoff = !onoff;
571
572 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
573
574 if (onoff)
575 /* Turn off phy power saving */
576 reg1 &= ~phy_power[port];
577 else
578 reg1 |= phy_power[port];
579
580 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 581 sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb 582 udelay(100);
583}
584
1b537565
SH		 585/* Force a renegotiation */
586static void sky2_phy_reinit(struct sky2_port *sky2)
587{
e07b1aa8 588 spin_lock_bh(&sky2->phy_lock);
1b537565 589 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 590 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 591}
592
cd28ab6a
SH		 593static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
594{
595 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
596 u16 reg;
597 int i;
598 const u8 *addr = hw->dev[port]->dev_addr;
599
42eeea01 600 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
601 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 602
603 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
604
793b883e 605 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 606 /* WA DEV_472 -- looks like crossed wires on port 2 */
607 /* clear GMAC 1 Control reset */
608 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
609 do {
610 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
611 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
612 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
613 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
614 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
615 }
616
793b883e 617 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 618
2eaba1a2
SH		 619 /* Enable Transmit FIFO Underrun */
620 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
621
e07b1aa8 622 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 623 sky2_phy_init(hw, port);
e07b1aa8 624 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 625
626 /* MIB clear */
627 reg = gma_read16(hw, port, GM_PHY_ADDR);
628 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
629
43f2f104
SH		 630 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
631 gma_read16(hw, port, i);
cd28ab6a
SH		 632 gma_write16(hw, port, GM_PHY_ADDR, reg);
633
634 /* transmit control */
635 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
636
637 /* receive control reg: unicast + multicast + no FCS */
638 gma_write16(hw, port, GM_RX_CTRL,
793b883e 639 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 640
641 /* transmit flow control */
642 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
643
644 /* transmit parameter */
645 gma_write16(hw, port, GM_TX_PARAM,
646 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
647 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
648 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
649 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
650
651 /* serial mode register */
652 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 653 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 654
6b1a3aef 655 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 656 reg |= GM_SMOD_JUMBO_ENA;
657
658 gma_write16(hw, port, GM_SERIAL_MODE, reg);
659
cd28ab6a
SH		 660 /* virtual address for data */
661 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
662
793b883e
SH		 663 /* physical address: used for pause frames */
664 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
665
666 /* ignore counter overflows */
cd28ab6a
SH		 667 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
668 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
669 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
670
671 /* Configure Rx MAC FIFO */
672 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 673 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
674 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 675
d571b694 676 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 677 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 678
8df9a876
SH		 679 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
680 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 681
682 /* Configure Tx MAC FIFO */
683 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
684 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 685
686 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
8df9a876 687 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 688 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
689 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
690 /* set Tx GMAC FIFO Almost Empty Threshold */
691 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
692 /* Disable Store & Forward mode for TX */
693 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
694 }
695 }
696
cd28ab6a
SH		 697}
698
470ea7eb
SH		 699/* Assign Ram Buffer allocation in units of 64bit (8 bytes) */
700static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 end)
cd28ab6a 701{
470ea7eb 702 pr_debug(PFX "q %d %#x %#x\n", q, start, end);
793b883e 703
cd28ab6a
SH		 704 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
705 sky2_write32(hw, RB_ADDR(q, RB_START), start);
706 sky2_write32(hw, RB_ADDR(q, RB_END), end);
707 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
708 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
709
710 if (q == Q_R1 || q == Q_R2) {
470ea7eb 711 u32 space = end - start + 1;
1c28f6ba 712 u32 tp = space - space/4;
793b883e 713
1c28f6ba
SH		 714 /* On receive queue's set the thresholds
715 * give receiver priority when > 3/4 full
716 * send pause when down to 2K
717 */
718 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
719 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 720
1c28f6ba
SH		 721 tp = space - 2048/8;
722 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
723 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 724 } else {
725 /* Enable store & forward on Tx queue's because
726 * Tx FIFO is only 1K on Yukon
727 */
728 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
729 }
730
731 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 732 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 733}
734
cd28ab6a 735/* Setup Bus Memory Interface */
af4ed7e6 736static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 737{
738 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
739 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
740 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 741 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 742}
743
cd28ab6a
SH		 744/* Setup prefetch unit registers. This is the interface between
745 * hardware and driver list elements
746 */
8cc048e3 747static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 748 u64 addr, u32 last)
749{
cd28ab6a
SH		 750 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
751 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
752 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
753 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
754 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
755 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 756
757 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 758}
759
793b883e
SH		 760static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
761{
762 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
763
cb5d9547 764 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 765 le->ctrl = 0;
793b883e
SH		 766 return le;
767}
cd28ab6a 768
291ea614
SH		 769static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
770 struct sky2_tx_le *le)
771{
772 return sky2->tx_ring + (le - sky2->tx_le);
773}
774
290d4de5
SH		 775/* Update chip's next pointer */
776static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 777{
98232f85 778 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
762c2de2 779 wmb();
98232f85 780 sky2_write16(hw, q, idx);
781 sky2_read16(hw, q);
cd28ab6a
SH		 782}
783
793b883e 784
cd28ab6a
SH		 785static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
786{
787 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 788 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 789 le->ctrl = 0;
cd28ab6a
SH		 790 return le;
791}
792
a018e330 793/* Return high part of DMA address (could be 32 or 64 bit) */
794static inline u32 high32(dma_addr_t a)
795{
a036119f 796 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330 797}
798
14d0263f
SH		 799/* Build description to hardware for one receive segment */
800static void sky2_rx_add(struct sky2_port *sky2, u8 op,
801 dma_addr_t map, unsigned len)
cd28ab6a
SH		 802{
803 struct sky2_rx_le *le;
734d1868 804 u32 hi = high32(map);
cd28ab6a 805
793b883e 806 if (sky2->rx_addr64 != hi) {
cd28ab6a 807 le = sky2_next_rx(sky2);
793b883e 808 le->addr = cpu_to_le32(hi);
cd28ab6a 809 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 810 sky2->rx_addr64 = high32(map + len);
cd28ab6a 811 }
793b883e 812
cd28ab6a 813 le = sky2_next_rx(sky2);
734d1868
SH		 814 le->addr = cpu_to_le32((u32) map);
815 le->length = cpu_to_le16(len);
14d0263f 816 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 817}
818
14d0263f
SH		 819/* Build description to hardware for one possibly fragmented skb */
820static void sky2_rx_submit(struct sky2_port *sky2,
821 const struct rx_ring_info *re)
822{
823 int i;
824
825 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
826
827 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
828 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
829}
830
831
832static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
833 unsigned size)
834{
835 struct sk_buff *skb = re->skb;
836 int i;
837
838 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
839 pci_unmap_len_set(re, data_size, size);
840
841 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
842 re->frag_addr[i] = pci_map_page(pdev,
843 skb_shinfo(skb)->frags[i].page,
844 skb_shinfo(skb)->frags[i].page_offset,
845 skb_shinfo(skb)->frags[i].size,
846 PCI_DMA_FROMDEVICE);
847}
848
849static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
850{
851 struct sk_buff *skb = re->skb;
852 int i;
853
854 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
855 PCI_DMA_FROMDEVICE);
856
857 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
858 pci_unmap_page(pdev, re->frag_addr[i],
859 skb_shinfo(skb)->frags[i].size,
860 PCI_DMA_FROMDEVICE);
861}
793b883e 862
cd28ab6a
SH		 863/* Tell chip where to start receive checksum.
864 * Actually has two checksums, but set both same to avoid possible byte
865 * order problems.
866 */
793b883e 867static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 868{
869 struct sky2_rx_le *le;
870
cd28ab6a 871 le = sky2_next_rx(sky2);
f65b138c 872 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
cd28ab6a
SH		 873 le->ctrl = 0;
874 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 875
793b883e
SH		 876 sky2_write32(sky2->hw,
877 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
878 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 879
880}
881
6b1a3aef 882/*
883 * The RX Stop command will not work for Yukon-2 if the BMU does not
884 * reach the end of packet and since we can't make sure that we have
885 * incoming data, we must reset the BMU while it is not doing a DMA
886 * transfer. Since it is possible that the RX path is still active,
887 * the RX RAM buffer will be stopped first, so any possible incoming
888 * data will not trigger a DMA. After the RAM buffer is stopped, the
889 * BMU is polled until any DMA in progress is ended and only then it
890 * will be reset.
891 */
892static void sky2_rx_stop(struct sky2_port *sky2)
893{
894 struct sky2_hw *hw = sky2->hw;
895 unsigned rxq = rxqaddr[sky2->port];
896 int i;
897
898 /* disable the RAM Buffer receive queue */
899 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
900
901 for (i = 0; i < 0xffff; i++)
902 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
903 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
904 goto stopped;
905
906 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
907 sky2->netdev->name);
908stopped:
909 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
910
911 /* reset the Rx prefetch unit */
912 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
913}
793b883e 914
d571b694 915/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 916static void sky2_rx_clean(struct sky2_port *sky2)
917{
918 unsigned i;
919
920 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 921 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 922 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 923
924 if (re->skb) {
14d0263f 925 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 926 kfree_skb(re->skb);
927 re->skb = NULL;
928 }
929 }
930}
931
ef743d33 932/* Basic MII support */
933static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
934{
935 struct mii_ioctl_data *data = if_mii(ifr);
936 struct sky2_port *sky2 = netdev_priv(dev);
937 struct sky2_hw *hw = sky2->hw;
938 int err = -EOPNOTSUPP;
939
940 if (!netif_running(dev))
941 return -ENODEV; /* Phy still in reset */
942
d89e1343 943 switch (cmd) {
ef743d33 944 case SIOCGMIIPHY:
945 data->phy_id = PHY_ADDR_MARV;
946
947 /* fallthru */
948 case SIOCGMIIREG: {
949 u16 val = 0;
91c86df5 950
e07b1aa8 951 spin_lock_bh(&sky2->phy_lock);
ef743d33 952 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 953 spin_unlock_bh(&sky2->phy_lock);
91c86df5 954
ef743d33 955 data->val_out = val;
956 break;
957 }
958
959 case SIOCSMIIREG:
960 if (!capable(CAP_NET_ADMIN))
961 return -EPERM;
962
e07b1aa8 963 spin_lock_bh(&sky2->phy_lock);
ef743d33 964 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
965 data->val_in);
e07b1aa8 966 spin_unlock_bh(&sky2->phy_lock);
ef743d33 967 break;
968 }
969 return err;
970}
971
d1f13708 972#ifdef SKY2_VLAN_TAG_USED
973static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
974{
975 struct sky2_port *sky2 = netdev_priv(dev);
976 struct sky2_hw *hw = sky2->hw;
977 u16 port = sky2->port;
d1f13708 978
2bb8c262 979 netif_tx_lock_bh(dev);
d1f13708 980
981 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
982 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
983 sky2->vlgrp = grp;
984
2bb8c262 985 netif_tx_unlock_bh(dev);
d1f13708 986}
987
988static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
989{
990 struct sky2_port *sky2 = netdev_priv(dev);
991 struct sky2_hw *hw = sky2->hw;
992 u16 port = sky2->port;
d1f13708 993
2bb8c262 994 netif_tx_lock_bh(dev);
d1f13708 995
996 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
997 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
998 if (sky2->vlgrp)
999 sky2->vlgrp->vlan_devices[vid] = NULL;
1000
2bb8c262 1001 netif_tx_unlock_bh(dev);
d1f13708 1002}
1003#endif
1004
82788c7a 1005/*
14d0263f
SH		 1006 * Allocate an skb for receiving. If the MTU is large enough
1007 * make the skb non-linear with a fragment list of pages.
1008 *
82788c7a
SH		 1009 * It appears the hardware has a bug in the FIFO logic that
1010 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86 1011 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1012 * aligned except if slab debugging is enabled.
82788c7a 1013 */
14d0263f 1014static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1015{
1016 struct sk_buff *skb;
14d0263f
SH		 1017 unsigned long p;
1018 int i;
82788c7a 1019
14d0263f
SH		 1020 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1021 if (!skb)
1022 goto nomem;
1023
1024 p = (unsigned long) skb->data;
1025 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1026
1027 for (i = 0; i < sky2->rx_nfrags; i++) {
1028 struct page *page = alloc_page(GFP_ATOMIC);
1029
1030 if (!page)
1031 goto free_partial;
1032 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1033 }
1034
1035 return skb;
14d0263f
SH		 1036free_partial:
1037 kfree_skb(skb);
1038nomem:
1039 return NULL;
82788c7a
SH		 1040}
1041
cd28ab6a
SH		 1042/*
1043 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1044 * Normal case this ends up creating one list element for skb
1045 * in the receive ring. Worst case if using large MTU and each
1046 * allocation falls on a different 64 bit region, that results
1047 * in 6 list elements per ring entry.
1048 * One element is used for checksum enable/disable, and one
1049 * extra to avoid wrap.
cd28ab6a 1050 */
6b1a3aef 1051static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1052{
6b1a3aef 1053 struct sky2_hw *hw = sky2->hw;
14d0263f 1054 struct rx_ring_info *re;
6b1a3aef 1055 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1056 unsigned i, size, space, thresh;
cd28ab6a 1057
6b1a3aef 1058 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1059 sky2_qset(hw, rxq);
977bdf06 1060
8df9a876
SH		 1061 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1062 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0)) {
977bdf06
SH		 1063 /* MAC Rx RAM Read is controlled by hardware */
1064 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1065 }
1066
6b1a3aef 1067 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1068
1069 rx_set_checksum(sky2);
14d0263f
SH		 1070
1071 /* Space needed for frame data + headers rounded up */
1072 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1073 + 8;
1074
1075 /* Stopping point for hardware truncation */
1076 thresh = (size - 8) / sizeof(u32);
1077
1078 /* Account for overhead of skb - to avoid order > 0 allocation */
1079 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1080 + sizeof(struct skb_shared_info);
1081
1082 sky2->rx_nfrags = space >> PAGE_SHIFT;
1083 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1084
1085 if (sky2->rx_nfrags != 0) {
1086 /* Compute residue after pages */
1087 space = sky2->rx_nfrags << PAGE_SHIFT;
1088
1089 if (space < size)
1090 size -= space;
1091 else
1092 size = 0;
1093
1094 /* Optimize to handle small packets and headers */
1095 if (size < copybreak)
1096 size = copybreak;
1097 if (size < ETH_HLEN)
1098 size = ETH_HLEN;
1099 }
1100 sky2->rx_data_size = size;
1101
1102 /* Fill Rx ring */
793b883e 1103 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1104 re = sky2->rx_ring + i;
cd28ab6a 1105
14d0263f 1106 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1107 if (!re->skb)
1108 goto nomem;
1109
14d0263f
SH		 1110 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1111 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1112 }
1113
a1433ac4
SH		 1114 /*
1115 * The receiver hangs if it receives frames larger than the
1116 * packet buffer. As a workaround, truncate oversize frames, but
1117 * the register is limited to 9 bits, so if you do frames > 2052
1118 * you better get the MTU right!
1119 */
a1433ac4
SH		 1120 if (thresh > 0x1ff)
1121 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1122 else {
1123 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1124 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1125 }
1126
6b1a3aef 1127 /* Tell chip about available buffers */
1128 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1129 return 0;
1130nomem:
1131 sky2_rx_clean(sky2);
1132 return -ENOMEM;
1133}
1134
1135/* Bring up network interface. */
1136static int sky2_up(struct net_device *dev)
1137{
1138 struct sky2_port *sky2 = netdev_priv(dev);
1139 struct sky2_hw *hw = sky2->hw;
1140 unsigned port = sky2->port;
e07b1aa8 1141 u32 ramsize, rxspace, imask;
ee7abb04 1142 int cap, err = -ENOMEM;
843a46f4 1143 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1144
ee7abb04
SH		 1145 /*
1146 * On dual port PCI-X card, there is an problem where status
1147 * can be received out of order due to split transactions
843a46f4 1148 */
ee7abb04
SH		 1149 if (otherdev && netif_running(otherdev) &&
1150 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1151 struct sky2_port *osky2 = netdev_priv(otherdev);
1152 u16 cmd;
1153
1154 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1155 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1156 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1157
1158 sky2->rx_csum = 0;
1159 osky2->rx_csum = 0;
1160 }
843a46f4 1161
cd28ab6a
SH		 1162 if (netif_msg_ifup(sky2))
1163 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1164
1165 /* must be power of 2 */
1166 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1167 TX_RING_SIZE *
1168 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1169 &sky2->tx_le_map);
1170 if (!sky2->tx_le)
1171 goto err_out;
1172
6cdbbdf3 1173 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1174 GFP_KERNEL);
1175 if (!sky2->tx_ring)
1176 goto err_out;
1177 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1178
1179 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1180 &sky2->rx_le_map);
1181 if (!sky2->rx_le)
1182 goto err_out;
1183 memset(sky2->rx_le, 0, RX_LE_BYTES);
1184
291ea614 1185 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1186 GFP_KERNEL);
1187 if (!sky2->rx_ring)
1188 goto err_out;
1189
d3bcfbeb 1190 sky2_phy_power(hw, port, 1);
1191
cd28ab6a
SH		 1192 sky2_mac_init(hw, port);
1193
470ea7eb
SH		 1194 /* Determine available ram buffer space in qwords. */
1195 ramsize = sky2_read8(hw, B2_E_0) * 4096/8;
1c28f6ba 1196
470ea7eb
SH		 1197 if (ramsize > 6*1024/8)
1198 rxspace = ramsize - (ramsize + 2) / 3;
1199 else
1200 rxspace = ramsize / 2;
cd28ab6a 1201
470ea7eb
SH		 1202 sky2_ramset(hw, rxqaddr[port], 0, rxspace-1);
1203 sky2_ramset(hw, txqaddr[port], rxspace, ramsize-1);
cd28ab6a 1204
793b883e
SH		 1205 /* Make sure SyncQ is disabled */
1206 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1207 RB_RST_SET);
1208
af4ed7e6 1209 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1210
977bdf06 1211 /* Set almost empty threshold */
c2716fb4
SH		 1212 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1213 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
977bdf06 1214 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1215
6b1a3aef 1216 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1217 TX_RING_SIZE - 1);
cd28ab6a 1218
6b1a3aef 1219 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1220 if (err)
1221 goto err_out;
1222
cd28ab6a 1223 /* Enable interrupts from phy/mac for port */
e07b1aa8 1224 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1225 imask |= portirq_msk[port];
e07b1aa8
SH		 1226 sky2_write32(hw, B0_IMSK, imask);
1227
cd28ab6a
SH		 1228 return 0;
1229
1230err_out:
1b537565 1231 if (sky2->rx_le) {
cd28ab6a
SH		 1232 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1233 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1234 sky2->rx_le = NULL;
1235 }
1236 if (sky2->tx_le) {
cd28ab6a
SH		 1237 pci_free_consistent(hw->pdev,
1238 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1239 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1240 sky2->tx_le = NULL;
1241 }
1242 kfree(sky2->tx_ring);
1243 kfree(sky2->rx_ring);
cd28ab6a 1244
1b537565
SH		 1245 sky2->tx_ring = NULL;
1246 sky2->rx_ring = NULL;
cd28ab6a
SH		 1247 return err;
1248}
1249
793b883e
SH		 1250/* Modular subtraction in ring */
1251static inline int tx_dist(unsigned tail, unsigned head)
1252{
cb5d9547 1253 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1254}
cd28ab6a 1255
793b883e
SH		 1256/* Number of list elements available for next tx */
1257static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1258{
793b883e 1259 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1260}
1261
793b883e 1262/* Estimate of number of transmit list elements required */
28bd181a 1263static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1264{
793b883e
SH		 1265 unsigned count;
1266
1267 count = sizeof(dma_addr_t) / sizeof(u32);
1268 count += skb_shinfo(skb)->nr_frags * count;
1269
89114afd 1270 if (skb_is_gso(skb))
793b883e
SH		 1271 ++count;
1272
84fa7933 1273 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1274 ++count;
1275
1276 return count;
cd28ab6a
SH		 1277}
1278
793b883e
SH		 1279/*
1280 * Put one packet in ring for transmit.
1281 * A single packet can generate multiple list elements, and
1282 * the number of ring elements will probably be less than the number
1283 * of list elements used.
1284 */
cd28ab6a
SH		 1285static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1286{
1287 struct sky2_port *sky2 = netdev_priv(dev);
1288 struct sky2_hw *hw = sky2->hw;
d1f13708 1289 struct sky2_tx_le *le = NULL;
6cdbbdf3 1290 struct tx_ring_info *re;
cd28ab6a
SH		 1291 unsigned i, len;
1292 dma_addr_t mapping;
1293 u32 addr64;
1294 u16 mss;
1295 u8 ctrl;
1296
2bb8c262
SH		 1297 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1298 return NETDEV_TX_BUSY;
cd28ab6a 1299
793b883e 1300 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1301 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1302 dev->name, sky2->tx_prod, skb->len);
1303
cd28ab6a
SH		 1304 len = skb_headlen(skb);
1305 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1306 addr64 = high32(mapping);
793b883e 1307
a018e330 1308 /* Send high bits if changed or crosses boundary */
1309 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1310 le = get_tx_le(sky2);
f65b138c 1311 le->addr = cpu_to_le32(addr64);
793b883e 1312 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1313 sky2->tx_addr64 = high32(mapping + len);
793b883e 1314 }
cd28ab6a
SH		 1315
1316 /* Check for TCP Segmentation Offload */
7967168c 1317 mss = skb_shinfo(skb)->gso_size;
793b883e 1318 if (mss != 0) {
cd28ab6a
SH		 1319 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1320 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1321 mss += ETH_HLEN;
1322
e07560cd 1323 if (mss != sky2->tx_last_mss) {
1324 le = get_tx_le(sky2);
f65b138c 1325 le->addr = cpu_to_le32(mss);
e07560cd 1326 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1327 sky2->tx_last_mss = mss;
1328 }
cd28ab6a
SH		 1329 }
1330
cd28ab6a 1331 ctrl = 0;
d1f13708 1332#ifdef SKY2_VLAN_TAG_USED
1333 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1334 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1335 if (!le) {
1336 le = get_tx_le(sky2);
f65b138c 1337 le->addr = 0;
d1f13708 1338 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1339 } else
1340 le->opcode |= OP_VLAN;
1341 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1342 ctrl |= INS_VLAN;
1343 }
1344#endif
1345
1346 /* Handle TCP checksum offload */
84fa7933 1347 if (skb->ip_summed == CHECKSUM_PARTIAL) {
f65b138c
SH		 1348 unsigned offset = skb->h.raw - skb->data;
1349 u32 tcpsum;
1350
1351 tcpsum = offset << 16; /* sum start */
ff1dcadb 1352 tcpsum |= offset + skb->csum_offset; /* sum write */
cd28ab6a
SH		 1353
1354 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1355 if (skb->nh.iph->protocol == IPPROTO_UDP)
1356 ctrl |= UDPTCP;
1357
f65b138c
SH		 1358 if (tcpsum != sky2->tx_tcpsum) {
1359 sky2->tx_tcpsum = tcpsum;
1d179332 1360
1361 le = get_tx_le(sky2);
f65b138c 1362 le->addr = cpu_to_le32(tcpsum);
1d179332 1363 le->length = 0; /* initial checksum value */
1364 le->ctrl = 1; /* one packet */
1365 le->opcode = OP_TCPLISW | HW_OWNER;
1366 }
cd28ab6a
SH		 1367 }
1368
1369 le = get_tx_le(sky2);
f65b138c 1370 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1371 le->length = cpu_to_le16(len);
1372 le->ctrl = ctrl;
793b883e 1373 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1374
291ea614 1375 re = tx_le_re(sky2, le);
cd28ab6a 1376 re->skb = skb;
6cdbbdf3 1377 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1378 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1379
1380 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1381 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1382
1383 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1384 frag->size, PCI_DMA_TODEVICE);
a036119f 1385 addr64 = high32(mapping);
793b883e
SH		 1386 if (addr64 != sky2->tx_addr64) {
1387 le = get_tx_le(sky2);
f65b138c 1388 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1389 le->ctrl = 0;
1390 le->opcode = OP_ADDR64 | HW_OWNER;
1391 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1392 }
1393
1394 le = get_tx_le(sky2);
f65b138c 1395 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1396 le->length = cpu_to_le16(frag->size);
1397 le->ctrl = ctrl;
793b883e 1398 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1399
291ea614
SH		 1400 re = tx_le_re(sky2, le);
1401 re->skb = skb;
1402 pci_unmap_addr_set(re, mapaddr, mapping);
1403 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1404 }
6cdbbdf3 1405
cd28ab6a
SH		 1406 le->ctrl |= EOP;
1407
97bda706 1408 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1409 netif_stop_queue(dev);
b19666d9 1410
290d4de5 1411 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1412
cd28ab6a
SH		 1413 dev->trans_start = jiffies;
1414 return NETDEV_TX_OK;
1415}
1416
cd28ab6a 1417/*
793b883e
SH		 1418 * Free ring elements from starting at tx_cons until "done"
1419 *
1420 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1421 * buffers so make sure not to free skb to early.
cd28ab6a 1422 */
d11c13e7 1423static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1424{
d11c13e7 1425 struct net_device *dev = sky2->netdev;
af2a58ac 1426 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1427 unsigned idx;
cd28ab6a 1428
0e3ff6aa 1429 BUG_ON(done >= TX_RING_SIZE);
2224795d 1430
291ea614
SH		 1431 for (idx = sky2->tx_cons; idx != done;
1432 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1433 struct sky2_tx_le *le = sky2->tx_le + idx;
1434 struct tx_ring_info *re = sky2->tx_ring + idx;
1435
1436 switch(le->opcode & ~HW_OWNER) {
1437 case OP_LARGESEND:
1438 case OP_PACKET:
1439 pci_unmap_single(pdev,
1440 pci_unmap_addr(re, mapaddr),
1441 pci_unmap_len(re, maplen),
1442 PCI_DMA_TODEVICE);
af2a58ac 1443 break;
291ea614
SH		 1444 case OP_BUFFER:
1445 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1446 pci_unmap_len(re, maplen),
734d1868 1447 PCI_DMA_TODEVICE);
291ea614
SH		 1448 break;
1449 }
1450
1451 if (le->ctrl & EOP) {
1452 if (unlikely(netif_msg_tx_done(sky2)))
1453 printk(KERN_DEBUG "%s: tx done %u\n",
1454 dev->name, idx);
794b2bd2 1455 dev_kfree_skb_any(re->skb);
cd28ab6a
SH		 1456 }
1457
291ea614 1458 le->opcode = 0; /* paranoia */
793b883e 1459 }
793b883e 1460
291ea614 1461 sky2->tx_cons = idx;
22e11703 1462 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1463 netif_wake_queue(dev);
cd28ab6a
SH		 1464}
1465
1466/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1467static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1468{
2bb8c262
SH		 1469 struct sky2_port *sky2 = netdev_priv(dev);
1470
1471 netif_tx_lock_bh(dev);
d11c13e7 1472 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1473 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1474}
1475
1476/* Network shutdown */
1477static int sky2_down(struct net_device *dev)
1478{
1479 struct sky2_port *sky2 = netdev_priv(dev);
1480 struct sky2_hw *hw = sky2->hw;
1481 unsigned port = sky2->port;
1482 u16 ctrl;
e07b1aa8 1483 u32 imask;
cd28ab6a 1484
1b537565
SH		 1485 /* Never really got started! */
1486 if (!sky2->tx_le)
1487 return 0;
1488
cd28ab6a
SH		 1489 if (netif_msg_ifdown(sky2))
1490 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1491
018d1c66 1492 /* Stop more packets from being queued */
cd28ab6a
SH		 1493 netif_stop_queue(dev);
1494
ebc646f6
SH		 1495 /* Disable port IRQ */
1496 imask = sky2_read32(hw, B0_IMSK);
1497 imask &= ~portirq_msk[port];
1498 sky2_write32(hw, B0_IMSK, imask);
1499
d3bcfbeb 1500 sky2_gmac_reset(hw, port);
793b883e 1501
cd28ab6a
SH		 1502 /* Stop transmitter */
1503 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1504 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1505
1506 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1507 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a 1508
c2716fb4
SH		 1509 /* WA for dev. #4.209 */
1510 if (hw->chip_id == CHIP_ID_YUKON_EC_U
8df9a876 1511 && (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
c2716fb4
SH		 1512 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1513 sky2->speed != SPEED_1000 ?
1514 TX_STFW_ENA : TX_STFW_DIS);
1515
cd28ab6a 1516 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1517 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1518 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1519
1520 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1521
1522 /* Workaround shared GMAC reset */
793b883e
SH		 1523 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1524 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1525 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1526
1527 /* Disable Force Sync bit and Enable Alloc bit */
1528 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1529 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1530
1531 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1532 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1533 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1534
1535 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1536 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1537 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1538
1539 /* Reset the Tx prefetch units */
1540 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1541 PREF_UNIT_RST_SET);
1542
1543 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1544
6b1a3aef 1545 sky2_rx_stop(sky2);
cd28ab6a
SH		 1546
1547 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1548 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1549
d3bcfbeb 1550 sky2_phy_power(hw, port, 0);
1551
d571b694 1552 /* turn off LED's */
cd28ab6a
SH		 1553 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1554
018d1c66 1555 synchronize_irq(hw->pdev->irq);
1556
2bb8c262 1557 sky2_tx_clean(dev);
cd28ab6a
SH		 1558 sky2_rx_clean(sky2);
1559
1560 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1561 sky2->rx_le, sky2->rx_le_map);
1562 kfree(sky2->rx_ring);
1563
1564 pci_free_consistent(hw->pdev,
1565 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1566 sky2->tx_le, sky2->tx_le_map);
1567 kfree(sky2->tx_ring);
1568
1b537565
SH		 1569 sky2->tx_le = NULL;
1570 sky2->rx_le = NULL;
1571
1572 sky2->rx_ring = NULL;
1573 sky2->tx_ring = NULL;
1574
cd28ab6a
SH		 1575 return 0;
1576}
1577
1578static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1579{
b89165f2 1580 if (!sky2_is_copper(hw))
793b883e
SH		 1581 return SPEED_1000;
1582
cd28ab6a
SH		 1583 if (hw->chip_id == CHIP_ID_YUKON_FE)
1584 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1585
1586 switch (aux & PHY_M_PS_SPEED_MSK) {
1587 case PHY_M_PS_SPEED_1000:
1588 return SPEED_1000;
1589 case PHY_M_PS_SPEED_100:
1590 return SPEED_100;
1591 default:
1592 return SPEED_10;
1593 }
1594}
1595
1596static void sky2_link_up(struct sky2_port *sky2)
1597{
1598 struct sky2_hw *hw = sky2->hw;
1599 unsigned port = sky2->port;
1600 u16 reg;
16ad91e1
SH		 1601 static const char *fc_name[] = {
1602 [FC_NONE] = "none",
1603 [FC_TX] = "tx",
1604 [FC_RX] = "rx",
1605 [FC_BOTH] = "both",
1606 };
cd28ab6a 1607
cd28ab6a 1608 /* enable Rx/Tx */
2eaba1a2 1609 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1610 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1611 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1612
1613 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1614
1615 netif_carrier_on(sky2->netdev);
1616 netif_wake_queue(sky2->netdev);
1617
1618 /* Turn on link LED */
793b883e 1619 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1620 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1621
ed6d32c7 1622 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
793b883e 1623 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1624 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1625
1626 switch(sky2->speed) {
1627 case SPEED_10:
1628 led |= PHY_M_LEDC_INIT_CTRL(7);
1629 break;
1630
1631 case SPEED_100:
1632 led |= PHY_M_LEDC_STA1_CTRL(7);
1633 break;
1634
1635 case SPEED_1000:
1636 led |= PHY_M_LEDC_STA0_CTRL(7);
1637 break;
1638 }
793b883e
SH		 1639
1640 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1641 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1642 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1643 }
1644
cd28ab6a
SH		 1645 if (netif_msg_link(sky2))
1646 printk(KERN_INFO PFX
d571b694 1647 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1648 sky2->netdev->name, sky2->speed,
1649 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1650 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1651}
1652
1653static void sky2_link_down(struct sky2_port *sky2)
1654{
1655 struct sky2_hw *hw = sky2->hw;
1656 unsigned port = sky2->port;
1657 u16 reg;
1658
1659 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1660
1661 reg = gma_read16(hw, port, GM_GP_CTRL);
1662 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1663 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1664
16ad91e1 1665 if (sky2->flow_status == FC_RX) {
cd28ab6a
SH		 1666 /* restore Asymmetric Pause bit */
1667 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1668 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1669 | PHY_M_AN_ASP);
cd28ab6a
SH		 1670 }
1671
cd28ab6a
SH		 1672 netif_carrier_off(sky2->netdev);
1673 netif_stop_queue(sky2->netdev);
1674
1675 /* Turn on link LED */
1676 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1677
1678 if (netif_msg_link(sky2))
1679 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1680
cd28ab6a
SH		 1681 sky2_phy_init(hw, port);
1682}
1683
16ad91e1
SH		 1684static enum flow_control sky2_flow(int rx, int tx)
1685{
1686 if (rx)
1687 return tx ? FC_BOTH : FC_RX;
1688 else
1689 return tx ? FC_TX : FC_NONE;
1690}
1691
793b883e
SH		 1692static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1693{
1694 struct sky2_hw *hw = sky2->hw;
1695 unsigned port = sky2->port;
1696 u16 lpa;
1697
1698 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1699
1700 if (lpa & PHY_M_AN_RF) {
1701 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1702 return -1;
1703 }
1704
793b883e
SH		 1705 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1706 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1707 sky2->netdev->name);
1708 return -1;
1709 }
1710
793b883e 1711 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1712 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e
SH		 1713
1714 /* Pause bits are offset (9..8) */
ed6d32c7 1715 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
793b883e
SH		 1716 aux >>= 6;
1717
16ad91e1
SH		 1718 sky2->flow_status = sky2_flow(aux & PHY_M_PS_RX_P_EN,
1719 aux & PHY_M_PS_TX_P_EN);
793b883e 1720
16ad91e1 1721 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
2eaba1a2 1722 && hw->chip_id != CHIP_ID_YUKON_EC_U)
16ad91e1 1723 sky2->flow_status = FC_NONE;
2eaba1a2 1724
16ad91e1 1725 if (aux & PHY_M_PS_RX_P_EN)
793b883e
SH		 1726 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1727 else
1728 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1729
1730 return 0;
1731}
cd28ab6a 1732
e07b1aa8
SH		 1733/* Interrupt from PHY */
1734static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1735{
e07b1aa8
SH		 1736 struct net_device *dev = hw->dev[port];
1737 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1738 u16 istatus, phystat;
1739
ebc646f6
SH		 1740 if (!netif_running(dev))
1741 return;
1742
e07b1aa8
SH		 1743 spin_lock(&sky2->phy_lock);
1744 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1745 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1746
cd28ab6a
SH		 1747 if (netif_msg_intr(sky2))
1748 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1749 sky2->netdev->name, istatus, phystat);
1750
2eaba1a2 1751 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1752 if (sky2_autoneg_done(sky2, phystat) == 0)
1753 sky2_link_up(sky2);
1754 goto out;
1755 }
cd28ab6a 1756
793b883e
SH		 1757 if (istatus & PHY_M_IS_LSP_CHANGE)
1758 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1759
793b883e
SH		 1760 if (istatus & PHY_M_IS_DUP_CHANGE)
1761 sky2->duplex =
1762 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1763
793b883e
SH		 1764 if (istatus & PHY_M_IS_LST_CHANGE) {
1765 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1766 sky2_link_up(sky2);
793b883e
SH		 1767 else
1768 sky2_link_down(sky2);
cd28ab6a 1769 }
793b883e 1770out:
e07b1aa8 1771 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1772}
1773
302d1252
SH		 1774
1775/* Transmit timeout is only called if we are running, carries is up
1776 * and tx queue is full (stopped).
1777 */
cd28ab6a
SH		 1778static void sky2_tx_timeout(struct net_device *dev)
1779{
1780 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1781 struct sky2_hw *hw = sky2->hw;
1782 unsigned txq = txqaddr[sky2->port];
8f24664d 1783 u16 report, done;
cd28ab6a
SH		 1784
1785 if (netif_msg_timer(sky2))
1786 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1787
8f24664d
SH		 1788 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1789 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1790
8f24664d
SH		 1791 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1792 dev->name,
1793 sky2->tx_cons, sky2->tx_prod, report, done);
1794
1795 if (report != done) {
1796 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1797
1798 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1799 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1800 } else if (report != sky2->tx_cons) {
1801 printk(KERN_INFO PFX "status report lost?\n");
1802
2bb8c262 1803 netif_tx_lock_bh(dev);
8f24664d 1804 sky2_tx_complete(sky2, report);
2bb8c262 1805 netif_tx_unlock_bh(dev);
8f24664d
SH		 1806 } else {
1807 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1808
8f24664d
SH		 1809 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1810 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1811
2bb8c262 1812 sky2_tx_clean(dev);
8f24664d
SH		 1813
1814 sky2_qset(hw, txq);
1815 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1816 }
cd28ab6a
SH		 1817}
1818
1819static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1820{
6b1a3aef 1821 struct sky2_port *sky2 = netdev_priv(dev);
1822 struct sky2_hw *hw = sky2->hw;
1823 int err;
1824 u16 ctl, mode;
e07b1aa8 1825 u32 imask;
cd28ab6a
SH		 1826
1827 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1828 return -EINVAL;
1829
5a5b1ea0 1830 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1831 return -EINVAL;
1832
6b1a3aef 1833 if (!netif_running(dev)) {
1834 dev->mtu = new_mtu;
1835 return 0;
1836 }
1837
e07b1aa8 1838 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 1839 sky2_write32(hw, B0_IMSK, 0);
1840
018d1c66 1841 dev->trans_start = jiffies; /* prevent tx timeout */
1842 netif_stop_queue(dev);
1843 netif_poll_disable(hw->dev[0]);
1844
e07b1aa8
SH		 1845 synchronize_irq(hw->pdev->irq);
1846
6b1a3aef 1847 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1848 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1849 sky2_rx_stop(sky2);
1850 sky2_rx_clean(sky2);
cd28ab6a
SH		 1851
1852 dev->mtu = new_mtu;
14d0263f 1853
6b1a3aef 1854 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1855 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1856
1857 if (dev->mtu > ETH_DATA_LEN)
1858 mode |= GM_SMOD_JUMBO_ENA;
1859
1860 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1861
6b1a3aef 1862 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1863
6b1a3aef 1864 err = sky2_rx_start(sky2);
e07b1aa8 1865 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1866
1b537565
SH		 1867 if (err)
1868 dev_close(dev);
1869 else {
1870 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1871
1872 netif_poll_enable(hw->dev[0]);
1873 netif_wake_queue(dev);
1874 }
1875
cd28ab6a
SH		 1876 return err;
1877}
1878
14d0263f
SH		 1879/* For small just reuse existing skb for next receive */
1880static struct sk_buff *receive_copy(struct sky2_port *sky2,
1881 const struct rx_ring_info *re,
1882 unsigned length)
1883{
1884 struct sk_buff *skb;
1885
1886 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1887 if (likely(skb)) {
1888 skb_reserve(skb, 2);
1889 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1890 length, PCI_DMA_FROMDEVICE);
1891 memcpy(skb->data, re->skb->data, length);
1892 skb->ip_summed = re->skb->ip_summed;
1893 skb->csum = re->skb->csum;
1894 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1895 length, PCI_DMA_FROMDEVICE);
1896 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 1897 skb_put(skb, length);
14d0263f
SH		 1898 }
1899 return skb;
1900}
1901
1902/* Adjust length of skb with fragments to match received data */
1903static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1904 unsigned int length)
1905{
1906 int i, num_frags;
1907 unsigned int size;
1908
1909 /* put header into skb */
1910 size = min(length, hdr_space);
1911 skb->tail += size;
1912 skb->len += size;
1913 length -= size;
1914
1915 num_frags = skb_shinfo(skb)->nr_frags;
1916 for (i = 0; i < num_frags; i++) {
1917 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1918
1919 if (length == 0) {
1920 /* don't need this page */
1921 __free_page(frag->page);
1922 --skb_shinfo(skb)->nr_frags;
1923 } else {
1924 size = min(length, (unsigned) PAGE_SIZE);
1925
1926 frag->size = size;
1927 skb->data_len += size;
1928 skb->truesize += size;
1929 skb->len += size;
1930 length -= size;
1931 }
1932 }
1933}
1934
1935/* Normal packet - take skb from ring element and put in a new one */
1936static struct sk_buff *receive_new(struct sky2_port *sky2,
1937 struct rx_ring_info *re,
1938 unsigned int length)
1939{
1940 struct sk_buff *skb, *nskb;
1941 unsigned hdr_space = sky2->rx_data_size;
1942
1943 pr_debug(PFX "receive new length=%d\n", length);
1944
1945 /* Don't be tricky about reusing pages (yet) */
1946 nskb = sky2_rx_alloc(sky2);
1947 if (unlikely(!nskb))
1948 return NULL;
1949
1950 skb = re->skb;
1951 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1952
1953 prefetch(skb->data);
1954 re->skb = nskb;
1955 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
1956
1957 if (skb_shinfo(skb)->nr_frags)
1958 skb_put_frags(skb, hdr_space, length);
1959 else
489b10c1 1960 skb_put(skb, length);
14d0263f
SH		 1961 return skb;
1962}
1963
cd28ab6a
SH		 1964/*
1965 * Receive one packet.
d571b694 1966 * For larger packets, get new buffer.
cd28ab6a 1967 */
497d7c86 1968static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 1969 u16 length, u32 status)
1970{
497d7c86 1971 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 1972 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1973 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1974
1975 if (unlikely(netif_msg_rx_status(sky2)))
1976 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 1977 dev->name, sky2->rx_next, status, length);
cd28ab6a 1978
793b883e 1979 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1980 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1981
42eeea01 1982 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1983 goto error;
1984
42eeea01 1985 if (!(status & GMR_FS_RX_OK))
1986 goto resubmit;
1987
497d7c86 1988 if (length > dev->mtu + ETH_HLEN)
6e15b712
SH		 1989 goto oversize;
1990
14d0263f
SH		 1991 if (length < copybreak)
1992 skb = receive_copy(sky2, re, length);
1993 else
1994 skb = receive_new(sky2, re, length);
793b883e 1995resubmit:
14d0263f 1996 sky2_rx_submit(sky2, re);
79e57d32 1997
cd28ab6a
SH		 1998 return skb;
1999
6e15b712
SH		 2000oversize:
2001 ++sky2->net_stats.rx_over_errors;
2002 goto resubmit;
2003
cd28ab6a 2004error:
6e15b712 2005 ++sky2->net_stats.rx_errors;
b6d77734
SH		 2006 if (status & GMR_FS_RX_FF_OV) {
2007 sky2->net_stats.rx_fifo_errors++;
2008 goto resubmit;
2009 }
6e15b712 2010
3be92a70 2011 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2012 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2013 dev->name, status, length);
793b883e
SH		 2014
2015 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2016 sky2->net_stats.rx_length_errors++;
2017 if (status & GMR_FS_FRAGMENT)
2018 sky2->net_stats.rx_frame_errors++;
2019 if (status & GMR_FS_CRC_ERR)
2020 sky2->net_stats.rx_crc_errors++;
79e57d32 2021
793b883e 2022 goto resubmit;
cd28ab6a
SH		 2023}
2024
e07b1aa8
SH		 2025/* Transmit complete */
2026static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2027{
e07b1aa8 2028 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2029
e07b1aa8 2030 if (netif_running(dev)) {
2bb8c262 2031 netif_tx_lock(dev);
e07b1aa8 2032 sky2_tx_complete(sky2, last);
2bb8c262 2033 netif_tx_unlock(dev);
2224795d 2034 }
cd28ab6a
SH		 2035}
2036
e07b1aa8
SH		 2037/* Process status response ring */
2038static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2039{
22e11703 2040 struct sky2_port *sky2;
e07b1aa8 2041 int work_done = 0;
22e11703 2042 unsigned buf_write[2] = { 0, 0 };
e71ebd73 2043 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2044
af2a58ac 2045 rmb();
bea86103 2046
e71ebd73 2047 while (hw->st_idx != hwidx) {
13210ce5 2048 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2049 struct net_device *dev;
cd28ab6a 2050 struct sk_buff *skb;
cd28ab6a
SH		 2051 u32 status;
2052 u16 length;
2053
cb5d9547 2054 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2055
e71ebd73
SH		 2056 BUG_ON(le->link >= 2);
2057 dev = hw->dev[le->link];
13210ce5 2058
2059 sky2 = netdev_priv(dev);
f65b138c
SH		 2060 length = le16_to_cpu(le->length);
2061 status = le32_to_cpu(le->status);
cd28ab6a 2062
e71ebd73 2063 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2064 case OP_RXSTAT:
497d7c86 2065 skb = sky2_receive(dev, length, status);
d1f13708 2066 if (!skb)
5df79111 2067 goto force_update;
13210ce5 2068
13210ce5 2069 skb->protocol = eth_type_trans(skb, dev);
2070 dev->last_rx = jiffies;
2071
d1f13708 2072#ifdef SKY2_VLAN_TAG_USED
2073 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2074 vlan_hwaccel_receive_skb(skb,
2075 sky2->vlgrp,
2076 be16_to_cpu(sky2->rx_tag));
2077 } else
2078#endif
cd28ab6a 2079 netif_receive_skb(skb);
13210ce5 2080
22e11703
SH		 2081 /* Update receiver after 16 frames */
2082 if (++buf_write[le->link] == RX_BUF_WRITE) {
5df79111
SH		 2083force_update:
2084 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
22e11703
SH		 2085 buf_write[le->link] = 0;
2086 }
2087
2088 /* Stop after net poll weight */
13210ce5 2089 if (++work_done >= to_do)
2090 goto exit_loop;
cd28ab6a
SH		 2091 break;
2092
d1f13708 2093#ifdef SKY2_VLAN_TAG_USED
2094 case OP_RXVLAN:
2095 sky2->rx_tag = length;
2096 break;
2097
2098 case OP_RXCHKSVLAN:
2099 sky2->rx_tag = length;
2100 /* fall through */
2101#endif
cd28ab6a 2102 case OP_RXCHKS:
d11c13e7 2103 skb = sky2->rx_ring[sky2->rx_next].skb;
84fa7933 2104 skb->ip_summed = CHECKSUM_COMPLETE;
f65b138c 2105 skb->csum = status & 0xffff;
cd28ab6a
SH		 2106 break;
2107
2108 case OP_TXINDEXLE:
13b97b74 2109 /* TX index reports status for both ports */
f55925d7
SH		 2110 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2111 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2112 if (hw->dev[1])
2113 sky2_tx_done(hw->dev[1],
2114 ((status >> 24) & 0xff)
2115 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2116 break;
2117
cd28ab6a
SH		 2118 default:
2119 if (net_ratelimit())
793b883e 2120 printk(KERN_WARNING PFX
e71ebd73
SH		 2121 "unknown status opcode 0x%x\n", le->opcode);
2122 goto exit_loop;
cd28ab6a 2123 }
13210ce5 2124 }
cd28ab6a 2125
fe2a24df
SH		 2126 /* Fully processed status ring so clear irq */
2127 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2128
13210ce5 2129exit_loop:
22e11703
SH		 2130 if (buf_write[0]) {
2131 sky2 = netdev_priv(hw->dev[0]);
2132 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2133 }
2134
2135 if (buf_write[1]) {
2136 sky2 = netdev_priv(hw->dev[1]);
2137 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2138 }
2139
e07b1aa8 2140 return work_done;
cd28ab6a
SH		 2141}
2142
2143static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2144{
2145 struct net_device *dev = hw->dev[port];
2146
3be92a70
SH		 2147 if (net_ratelimit())
2148 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2149 dev->name, status);
cd28ab6a
SH		 2150
2151 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2152 if (net_ratelimit())
2153 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2154 dev->name);
cd28ab6a
SH		 2155 /* Clear IRQ */
2156 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2157 }
2158
2159 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2160 if (net_ratelimit())
2161 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2162 dev->name);
cd28ab6a
SH		 2163
2164 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2165 }
2166
2167 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2168 if (net_ratelimit())
2169 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2170 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2171 }
2172
2173 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2174 if (net_ratelimit())
2175 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2176 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2177 }
2178
2179 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2180 if (net_ratelimit())
2181 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2182 dev->name);
cd28ab6a
SH		 2183 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2184 }
2185}
2186
2187static void sky2_hw_intr(struct sky2_hw *hw)
2188{
2189 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2190
793b883e 2191 if (status & Y2_IS_TIST_OV)
cd28ab6a 2192 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2193
2194 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2195 u16 pci_err;
2196
56a645cc 2197 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2198 if (net_ratelimit())
2199 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2200 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2201
2202 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2203 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2204 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2205 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2206 }
2207
2208 if (status & Y2_IS_PCI_EXP) {
d571b694 2209 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2210 u32 pex_err;
2211
7bd656d1 2212 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2213
3be92a70
SH		 2214 if (net_ratelimit())
2215 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2216 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2217
2218 /* clear the interrupt */
2219 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2220 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2221 0xffffffffUL);
cd28ab6a
SH		 2222 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2223
7bd656d1 2224 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2225 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2226 hwmsk &= ~Y2_IS_PCI_EXP;
2227 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2228 }
2229 }
2230
2231 if (status & Y2_HWE_L1_MASK)
2232 sky2_hw_error(hw, 0, status);
2233 status >>= 8;
2234 if (status & Y2_HWE_L1_MASK)
2235 sky2_hw_error(hw, 1, status);
2236}
2237
2238static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2239{
2240 struct net_device *dev = hw->dev[port];
2241 struct sky2_port *sky2 = netdev_priv(dev);
2242 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2243
2244 if (netif_msg_intr(sky2))
2245 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2246 dev->name, status);
2247
2248 if (status & GM_IS_RX_FF_OR) {
2249 ++sky2->net_stats.rx_fifo_errors;
2250 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2251 }
2252
2253 if (status & GM_IS_TX_FF_UR) {
2254 ++sky2->net_stats.tx_fifo_errors;
2255 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2256 }
cd28ab6a
SH		 2257}
2258
d257924e
SH		 2259/* This should never happen it is a fatal situation */
2260static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2261 const char *rxtx, u32 mask)
2262{
2263 struct net_device *dev = hw->dev[port];
2264 struct sky2_port *sky2 = netdev_priv(dev);
2265 u32 imask;
2266
2267 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2268 dev ? dev->name : "<not registered>", rxtx);
2269
2270 imask = sky2_read32(hw, B0_IMSK);
2271 imask &= ~mask;
2272 sky2_write32(hw, B0_IMSK, imask);
2273
2274 if (dev) {
2275 spin_lock(&sky2->phy_lock);
2276 sky2_link_down(sky2);
2277 spin_unlock(&sky2->phy_lock);
2278 }
2279}
cd28ab6a 2280
d27ed387
SH		 2281/* If idle then force a fake soft NAPI poll once a second
2282 * to work around cases where sharing an edge triggered interrupt.
2283 */
eb35cf60
SH		 2284static inline void sky2_idle_start(struct sky2_hw *hw)
2285{
2286 if (idle_timeout > 0)
2287 mod_timer(&hw->idle_timer,
2288 jiffies + msecs_to_jiffies(idle_timeout));
2289}
2290
d27ed387
SH		 2291static void sky2_idle(unsigned long arg)
2292{
01bd7564
SH		 2293 struct sky2_hw *hw = (struct sky2_hw *) arg;
2294 struct net_device *dev = hw->dev[0];
d27ed387 2295
d27ed387
SH		 2296 if (__netif_rx_schedule_prep(dev))
2297 __netif_rx_schedule(dev);
01bd7564
SH		 2298
2299 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2300}
2301
2302
e07b1aa8 2303static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2304{
e07b1aa8
SH		 2305 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2306 int work_limit = min(dev0->quota, *budget);
2307 int work_done = 0;
fb2690a9 2308 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2309
1e5f1283
SH		 2310 if (status & Y2_IS_HW_ERR)
2311 sky2_hw_intr(hw);
d257924e 2312
1e5f1283
SH		 2313 if (status & Y2_IS_IRQ_PHY1)
2314 sky2_phy_intr(hw, 0);
cd28ab6a 2315
1e5f1283
SH		 2316 if (status & Y2_IS_IRQ_PHY2)
2317 sky2_phy_intr(hw, 1);
cd28ab6a 2318
1e5f1283
SH		 2319 if (status & Y2_IS_IRQ_MAC1)
2320 sky2_mac_intr(hw, 0);
cd28ab6a 2321
1e5f1283
SH		 2322 if (status & Y2_IS_IRQ_MAC2)
2323 sky2_mac_intr(hw, 1);
cd28ab6a 2324
1e5f1283
SH		 2325 if (status & Y2_IS_CHK_RX1)
2326 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2327
1e5f1283
SH		 2328 if (status & Y2_IS_CHK_RX2)
2329 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2330
1e5f1283
SH		 2331 if (status & Y2_IS_CHK_TXA1)
2332 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2333
1e5f1283
SH		 2334 if (status & Y2_IS_CHK_TXA2)
2335 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2336
1e5f1283 2337 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2338 if (work_done < work_limit) {
2339 netif_rx_complete(dev0);
86fba634 2340
fe2a24df
SH		 2341 sky2_read32(hw, B0_Y2_SP_LISR);
2342 return 0;
2343 } else {
2344 *budget -= work_done;
2345 dev0->quota -= work_done;
1e5f1283 2346 return 1;
fe2a24df 2347 }
e07b1aa8
SH		 2348}
2349
7d12e780 2350static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2351{
2352 struct sky2_hw *hw = dev_id;
2353 struct net_device *dev0 = hw->dev[0];
2354 u32 status;
2355
2356 /* Reading this mask interrupts as side effect */
2357 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2358 if (status == 0 || status == ~0)
2359 return IRQ_NONE;
793b883e 2360
e07b1aa8
SH		 2361 prefetch(&hw->st_le[hw->st_idx]);
2362 if (likely(__netif_rx_schedule_prep(dev0)))
2363 __netif_rx_schedule(dev0);
793b883e 2364
cd28ab6a
SH		 2365 return IRQ_HANDLED;
2366}
2367
2368#ifdef CONFIG_NET_POLL_CONTROLLER
2369static void sky2_netpoll(struct net_device *dev)
2370{
2371 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2372 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2373
88d11360
SH		 2374 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2375 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2376}
2377#endif
2378
2379/* Chip internal frequency for clock calculations */
fb17358f 2380static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2381{
793b883e 2382 switch (hw->chip_id) {
cd28ab6a 2383 case CHIP_ID_YUKON_EC:
5a5b1ea0 2384 case CHIP_ID_YUKON_EC_U:
fb17358f 2385 return 125; /* 125 Mhz */
cd28ab6a 2386 case CHIP_ID_YUKON_FE:
fb17358f 2387 return 100; /* 100 Mhz */
793b883e 2388 default: /* YUKON_XL */
fb17358f 2389 return 156; /* 156 Mhz */
cd28ab6a
SH		 2390 }
2391}
2392
fb17358f 2393static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2394{
fb17358f 2395 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2396}
2397
fb17358f 2398static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2399{
fb17358f 2400 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2401}
2402
fb17358f 2403
59139528 2404static int sky2_reset(struct sky2_hw *hw)
cd28ab6a 2405{
cd28ab6a 2406 u16 status;
b89165f2 2407 u8 t8;
56a645cc 2408 int i;
cd28ab6a 2409
cd28ab6a 2410 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2411
cd28ab6a
SH		 2412 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2413 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2414 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2415 pci_name(hw->pdev), hw->chip_id);
2416 return -EOPNOTSUPP;
2417 }
2418
290d4de5
SH		 2419 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2420
2421 /* This rev is really old, and requires untested workarounds */
2422 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2423 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2424 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2425 hw->chip_id, hw->chip_rev);
2426 return -EOPNOTSUPP;
2427 }
2428
cd28ab6a
SH		 2429 /* disable ASF */
2430 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2431 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2432 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2433 }
2434
2435 /* do a SW reset */
2436 sky2_write8(hw, B0_CTST, CS_RST_SET);
2437 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2438
2439 /* clear PCI errors, if any */
56a645cc 2440 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2441
cd28ab6a 2442 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2443 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2444
cd28ab6a
SH		 2445
2446 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2447
2448 /* clear any PEX errors */
7bd656d1
SH		 2449 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2450 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2451
cd28ab6a 2452
b89165f2 2453 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
cd28ab6a
SH		 2454 hw->ports = 1;
2455 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2456 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2457 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2458 ++hw->ports;
2459 }
cd28ab6a 2460
5afa0a9c 2461 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2462
2463 for (i = 0; i < hw->ports; i++) {
2464 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2465 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2466 }
2467
2468 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2469
793b883e
SH		 2470 /* Clear I2C IRQ noise */
2471 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2472
2473 /* turn off hardware timer (unused) */
2474 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2475 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2476
cd28ab6a
SH		 2477 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2478
69634ee7
SH		 2479 /* Turn off descriptor polling */
2480 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2481
2482 /* Turn off receive timestamp */
2483 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2484 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2485
2486 /* enable the Tx Arbiters */
2487 for (i = 0; i < hw->ports; i++)
2488 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2489
2490 /* Initialize ram interface */
2491 for (i = 0; i < hw->ports; i++) {
793b883e 2492 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2493
2494 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2495 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2496 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2497 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2498 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2499 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2500 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2501 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2502 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2503 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2504 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2505 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2506 }
2507
7bd656d1 2508 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2509
cd28ab6a 2510 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2511 sky2_gmac_reset(hw, i);
cd28ab6a 2512
cd28ab6a
SH		 2513 memset(hw->st_le, 0, STATUS_LE_BYTES);
2514 hw->st_idx = 0;
2515
2516 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2517 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2518
2519 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2520 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2521
2522 /* Set the list last index */
793b883e 2523 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2524
290d4de5
SH		 2525 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2526 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2527
290d4de5
SH		 2528 /* set Status-FIFO ISR watermark */
2529 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2530 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2531 else
2532 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2533
290d4de5 2534 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2535 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2536 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2537
793b883e 2538 /* enable status unit */
cd28ab6a
SH		 2539 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2540
2541 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2542 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2543 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2544
2545 return 0;
2546}
2547
28bd181a 2548static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2549{
b89165f2
SH		 2550 if (sky2_is_copper(hw)) {
2551 u32 modes = SUPPORTED_10baseT_Half
2552 | SUPPORTED_10baseT_Full
2553 | SUPPORTED_100baseT_Half
2554 | SUPPORTED_100baseT_Full
2555 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2556
2557 if (hw->chip_id != CHIP_ID_YUKON_FE)
2558 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2559 | SUPPORTED_1000baseT_Full;
2560 return modes;
cd28ab6a 2561 } else
b89165f2
SH		 2562 return SUPPORTED_1000baseT_Half
2563 | SUPPORTED_1000baseT_Full
2564 | SUPPORTED_Autoneg
2565 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2566}
2567
793b883e 2568static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2569{
2570 struct sky2_port *sky2 = netdev_priv(dev);
2571 struct sky2_hw *hw = sky2->hw;
2572
2573 ecmd->transceiver = XCVR_INTERNAL;
2574 ecmd->supported = sky2_supported_modes(hw);
2575 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2576 if (sky2_is_copper(hw)) {
cd28ab6a 2577 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2578 | SUPPORTED_10baseT_Full
2579 | SUPPORTED_100baseT_Half
2580 | SUPPORTED_100baseT_Full
2581 | SUPPORTED_1000baseT_Half
2582 | SUPPORTED_1000baseT_Full
2583 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2584 ecmd->port = PORT_TP;
b89165f2
SH		 2585 ecmd->speed = sky2->speed;
2586 } else {
2587 ecmd->speed = SPEED_1000;
cd28ab6a 2588 ecmd->port = PORT_FIBRE;
b89165f2 2589 }
cd28ab6a
SH		 2590
2591 ecmd->advertising = sky2->advertising;
2592 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2593 ecmd->duplex = sky2->duplex;
2594 return 0;
2595}
2596
2597static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2598{
2599 struct sky2_port *sky2 = netdev_priv(dev);
2600 const struct sky2_hw *hw = sky2->hw;
2601 u32 supported = sky2_supported_modes(hw);
2602
2603 if (ecmd->autoneg == AUTONEG_ENABLE) {
2604 ecmd->advertising = supported;
2605 sky2->duplex = -1;
2606 sky2->speed = -1;
2607 } else {
2608 u32 setting;
2609
793b883e 2610 switch (ecmd->speed) {
cd28ab6a
SH		 2611 case SPEED_1000:
2612 if (ecmd->duplex == DUPLEX_FULL)
2613 setting = SUPPORTED_1000baseT_Full;
2614 else if (ecmd->duplex == DUPLEX_HALF)
2615 setting = SUPPORTED_1000baseT_Half;
2616 else
2617 return -EINVAL;
2618 break;
2619 case SPEED_100:
2620 if (ecmd->duplex == DUPLEX_FULL)
2621 setting = SUPPORTED_100baseT_Full;
2622 else if (ecmd->duplex == DUPLEX_HALF)
2623 setting = SUPPORTED_100baseT_Half;
2624 else
2625 return -EINVAL;
2626 break;
2627
2628 case SPEED_10:
2629 if (ecmd->duplex == DUPLEX_FULL)
2630 setting = SUPPORTED_10baseT_Full;
2631 else if (ecmd->duplex == DUPLEX_HALF)
2632 setting = SUPPORTED_10baseT_Half;
2633 else
2634 return -EINVAL;
2635 break;
2636 default:
2637 return -EINVAL;
2638 }
2639
2640 if ((setting & supported) == 0)
2641 return -EINVAL;
2642
2643 sky2->speed = ecmd->speed;
2644 sky2->duplex = ecmd->duplex;
2645 }
2646
2647 sky2->autoneg = ecmd->autoneg;
2648 sky2->advertising = ecmd->advertising;
2649
1b537565
SH		 2650 if (netif_running(dev))
2651 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2652
2653 return 0;
2654}
2655
2656static void sky2_get_drvinfo(struct net_device *dev,
2657 struct ethtool_drvinfo *info)
2658{
2659 struct sky2_port *sky2 = netdev_priv(dev);
2660
2661 strcpy(info->driver, DRV_NAME);
2662 strcpy(info->version, DRV_VERSION);
2663 strcpy(info->fw_version, "N/A");
2664 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2665}
2666
2667static const struct sky2_stat {
793b883e
SH		 2668 char name[ETH_GSTRING_LEN];
2669 u16 offset;
cd28ab6a
SH		 2670} sky2_stats[] = {
2671 { "tx_bytes", GM_TXO_OK_HI },
2672 { "rx_bytes", GM_RXO_OK_HI },
2673 { "tx_broadcast", GM_TXF_BC_OK },
2674 { "rx_broadcast", GM_RXF_BC_OK },
2675 { "tx_multicast", GM_TXF_MC_OK },
2676 { "rx_multicast", GM_RXF_MC_OK },
2677 { "tx_unicast", GM_TXF_UC_OK },
2678 { "rx_unicast", GM_RXF_UC_OK },
2679 { "tx_mac_pause", GM_TXF_MPAUSE },
2680 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2681 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2682 { "late_collision",GM_TXF_LAT_COL },
2683 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2684 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2685 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2686
d2604540 2687 { "rx_short", GM_RXF_SHT },
cd28ab6a 2688 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2689 { "rx_64_byte_packets", GM_RXF_64B },
2690 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2691 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2692 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2693 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2694 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2695 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2696 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2697 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2698 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2699 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2700
2701 { "tx_64_byte_packets", GM_TXF_64B },
2702 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2703 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2704 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2705 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2706 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2707 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2708 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2709};
2710
cd28ab6a
SH		 2711static u32 sky2_get_rx_csum(struct net_device *dev)
2712{
2713 struct sky2_port *sky2 = netdev_priv(dev);
2714
2715 return sky2->rx_csum;
2716}
2717
2718static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2719{
2720 struct sky2_port *sky2 = netdev_priv(dev);
2721
2722 sky2->rx_csum = data;
793b883e 2723
cd28ab6a
SH		 2724 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2725 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2726
2727 return 0;
2728}
2729
2730static u32 sky2_get_msglevel(struct net_device *netdev)
2731{
2732 struct sky2_port *sky2 = netdev_priv(netdev);
2733 return sky2->msg_enable;
2734}
2735
9a7ae0a9
SH		 2736static int sky2_nway_reset(struct net_device *dev)
2737{
2738 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2739
16ad91e1 2740 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2741 return -EINVAL;
2742
1b537565 2743 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2744
2745 return 0;
2746}
2747
793b883e 2748static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2749{
2750 struct sky2_hw *hw = sky2->hw;
2751 unsigned port = sky2->port;
2752 int i;
2753
2754 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2755 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2756 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2757 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2758
793b883e 2759 for (i = 2; i < count; i++)
cd28ab6a
SH		 2760 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2761}
2762
cd28ab6a
SH		 2763static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2764{
2765 struct sky2_port *sky2 = netdev_priv(netdev);
2766 sky2->msg_enable = value;
2767}
2768
2769static int sky2_get_stats_count(struct net_device *dev)
2770{
2771 return ARRAY_SIZE(sky2_stats);
2772}
2773
2774static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2775 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2776{
2777 struct sky2_port *sky2 = netdev_priv(dev);
2778
793b883e 2779 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2780}
2781
793b883e 2782static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2783{
2784 int i;
2785
2786 switch (stringset) {
2787 case ETH_SS_STATS:
2788 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2789 memcpy(data + i * ETH_GSTRING_LEN,
2790 sky2_stats[i].name, ETH_GSTRING_LEN);
2791 break;
2792 }
2793}
2794
2795/* Use hardware MIB variables for critical path statistics and
2796 * transmit feedback not reported at interrupt.
2797 * Other errors are accounted for in interrupt handler.
2798 */
2799static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2800{
2801 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2802 u64 data[13];
cd28ab6a 2803
793b883e 2804 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2805
2806 sky2->net_stats.tx_bytes = data[0];
2807 sky2->net_stats.rx_bytes = data[1];
2808 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2809 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
050ff180 2810 sky2->net_stats.multicast = data[3] + data[5];
cd28ab6a
SH		 2811 sky2->net_stats.collisions = data[10];
2812 sky2->net_stats.tx_aborted_errors = data[12];
2813
2814 return &sky2->net_stats;
2815}
2816
2817static int sky2_set_mac_address(struct net_device *dev, void *p)
2818{
2819 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2820 struct sky2_hw *hw = sky2->hw;
2821 unsigned port = sky2->port;
2822 const struct sockaddr *addr = p;
cd28ab6a
SH		 2823
2824 if (!is_valid_ether_addr(addr->sa_data))
2825 return -EADDRNOTAVAIL;
2826
cd28ab6a 2827 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2828 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2829 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2830 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2831 dev->dev_addr, ETH_ALEN);
1b537565 2832
a8ab1ec0
SH		 2833 /* virtual address for data */
2834 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2835
2836 /* physical address: used for pause frames */
2837 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2838
2839 return 0;
cd28ab6a
SH		 2840}
2841
a052b52f
SH		 2842static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
2843{
2844 u32 bit;
2845
2846 bit = ether_crc(ETH_ALEN, addr) & 63;
2847 filter[bit >> 3] |= 1 << (bit & 7);
2848}
2849
cd28ab6a
SH		 2850static void sky2_set_multicast(struct net_device *dev)
2851{
2852 struct sky2_port *sky2 = netdev_priv(dev);
2853 struct sky2_hw *hw = sky2->hw;
2854 unsigned port = sky2->port;
2855 struct dev_mc_list *list = dev->mc_list;
2856 u16 reg;
2857 u8 filter[8];
a052b52f
SH		 2858 int rx_pause;
2859 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 2860
a052b52f 2861 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 2862 memset(filter, 0, sizeof(filter));
2863
2864 reg = gma_read16(hw, port, GM_RX_CTRL);
2865 reg |= GM_RXCR_UCF_ENA;
2866
d571b694 2867 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2868 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 2869 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 2870 memset(filter, 0xff, sizeof(filter));
a052b52f 2871 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 2872 reg &= ~GM_RXCR_MCF_ENA;
2873 else {
2874 int i;
2875 reg |= GM_RXCR_MCF_ENA;
2876
a052b52f
SH		 2877 if (rx_pause)
2878 sky2_add_filter(filter, pause_mc_addr);
2879
2880 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2881 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 2882 }
2883
cd28ab6a 2884 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2885 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2886 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2887 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2888 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2889 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2890 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2891 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2892
2893 gma_write16(hw, port, GM_RX_CTRL, reg);
2894}
2895
2896/* Can have one global because blinking is controlled by
2897 * ethtool and that is always under RTNL mutex
2898 */
91c86df5 2899static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2900{
793b883e
SH		 2901 u16 pg;
2902
793b883e
SH		 2903 switch (hw->chip_id) {
2904 case CHIP_ID_YUKON_XL:
2905 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2906 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2907 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2908 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2909 PHY_M_LEDC_INIT_CTRL(7) |
2910 PHY_M_LEDC_STA1_CTRL(7) |
2911 PHY_M_LEDC_STA0_CTRL(7))
2912 : 0);
2913
2914 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2915 break;
2916
2917 default:
2918 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2919 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2920 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2921 PHY_M_LED_MO_10(MO_LED_ON) |
2922 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2923 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2924 PHY_M_LED_MO_RX(MO_LED_ON)
2925 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2926 PHY_M_LED_MO_10(MO_LED_OFF) |
2927 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2928 PHY_M_LED_MO_1000(MO_LED_OFF) |
2929 PHY_M_LED_MO_RX(MO_LED_OFF));
2930
793b883e 2931 }
cd28ab6a
SH		 2932}
2933
2934/* blink LED's for finding board */
2935static int sky2_phys_id(struct net_device *dev, u32 data)
2936{
2937 struct sky2_port *sky2 = netdev_priv(dev);
2938 struct sky2_hw *hw = sky2->hw;
2939 unsigned port = sky2->port;
793b883e 2940 u16 ledctrl, ledover = 0;
cd28ab6a 2941 long ms;
91c86df5 2942 int interrupted;
cd28ab6a
SH		 2943 int onoff = 1;
2944
793b883e 2945 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2946 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2947 else
2948 ms = data * 1000;
2949
2950 /* save initial values */
e07b1aa8 2951 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2952 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2953 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2954 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2955 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2956 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2957 } else {
2958 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2959 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2960 }
cd28ab6a 2961
91c86df5
SH		 2962 interrupted = 0;
2963 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2964 sky2_led(hw, port, onoff);
2965 onoff = !onoff;
2966
e07b1aa8 2967 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2968 interrupted = msleep_interruptible(250);
e07b1aa8 2969 spin_lock_bh(&sky2->phy_lock);
91c86df5 2970
cd28ab6a
SH		 2971 ms -= 250;
2972 }
2973
2974 /* resume regularly scheduled programming */
793b883e
SH		 2975 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2976 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2977 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2978 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2979 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2980 } else {
2981 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2982 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2983 }
e07b1aa8 2984 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2985
2986 return 0;
2987}
2988
2989static void sky2_get_pauseparam(struct net_device *dev,
2990 struct ethtool_pauseparam *ecmd)
2991{
2992 struct sky2_port *sky2 = netdev_priv(dev);
2993
16ad91e1
SH		 2994 switch (sky2->flow_mode) {
2995 case FC_NONE:
2996 ecmd->tx_pause = ecmd->rx_pause = 0;
2997 break;
2998 case FC_TX:
2999 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3000 break;
3001 case FC_RX:
3002 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3003 break;
3004 case FC_BOTH:
3005 ecmd->tx_pause = ecmd->rx_pause = 1;
3006 }
3007
cd28ab6a
SH		 3008 ecmd->autoneg = sky2->autoneg;
3009}
3010
3011static int sky2_set_pauseparam(struct net_device *dev,
3012 struct ethtool_pauseparam *ecmd)
3013{
3014 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3015
3016 sky2->autoneg = ecmd->autoneg;
16ad91e1 3017 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3018
16ad91e1
SH		 3019 if (netif_running(dev))
3020 sky2_phy_reinit(sky2);
cd28ab6a 3021
2eaba1a2 3022 return 0;
cd28ab6a
SH		 3023}
3024
fb17358f
SH		 3025static int sky2_get_coalesce(struct net_device *dev,
3026 struct ethtool_coalesce *ecmd)
3027{
3028 struct sky2_port *sky2 = netdev_priv(dev);
3029 struct sky2_hw *hw = sky2->hw;
3030
3031 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3032 ecmd->tx_coalesce_usecs = 0;
3033 else {
3034 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3035 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3036 }
3037 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3038
3039 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3040 ecmd->rx_coalesce_usecs = 0;
3041 else {
3042 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3043 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3044 }
3045 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3046
3047 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3048 ecmd->rx_coalesce_usecs_irq = 0;
3049 else {
3050 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3051 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3052 }
3053
3054 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3055
3056 return 0;
3057}
3058
3059/* Note: this affect both ports */
3060static int sky2_set_coalesce(struct net_device *dev,
3061 struct ethtool_coalesce *ecmd)
3062{
3063 struct sky2_port *sky2 = netdev_priv(dev);
3064 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3065 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3066
77b3d6a2
SH		 3067 if (ecmd->tx_coalesce_usecs > tmax ||
3068 ecmd->rx_coalesce_usecs > tmax ||
3069 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3070 return -EINVAL;
3071
ff81fbbe 3072 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3073 return -EINVAL;
ff81fbbe 3074 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3075 return -EINVAL;
ff81fbbe 3076 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3077 return -EINVAL;
3078
3079 if (ecmd->tx_coalesce_usecs == 0)
3080 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3081 else {
3082 sky2_write32(hw, STAT_TX_TIMER_INI,
3083 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3084 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3085 }
3086 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3087
3088 if (ecmd->rx_coalesce_usecs == 0)
3089 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3090 else {
3091 sky2_write32(hw, STAT_LEV_TIMER_INI,
3092 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3093 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3094 }
3095 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3096
3097 if (ecmd->rx_coalesce_usecs_irq == 0)
3098 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3099 else {
d28d4870 3100 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3101 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3102 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3103 }
3104 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3105 return 0;
3106}
3107
793b883e
SH		 3108static void sky2_get_ringparam(struct net_device *dev,
3109 struct ethtool_ringparam *ering)
3110{
3111 struct sky2_port *sky2 = netdev_priv(dev);
3112
3113 ering->rx_max_pending = RX_MAX_PENDING;
3114 ering->rx_mini_max_pending = 0;
3115 ering->rx_jumbo_max_pending = 0;
3116 ering->tx_max_pending = TX_RING_SIZE - 1;
3117
3118 ering->rx_pending = sky2->rx_pending;
3119 ering->rx_mini_pending = 0;
3120 ering->rx_jumbo_pending = 0;
3121 ering->tx_pending = sky2->tx_pending;
3122}
3123
3124static int sky2_set_ringparam(struct net_device *dev,
3125 struct ethtool_ringparam *ering)
3126{
3127 struct sky2_port *sky2 = netdev_priv(dev);
3128 int err = 0;
3129
3130 if (ering->rx_pending > RX_MAX_PENDING ||
3131 ering->rx_pending < 8 ||
3132 ering->tx_pending < MAX_SKB_TX_LE ||
3133 ering->tx_pending > TX_RING_SIZE - 1)
3134 return -EINVAL;
3135
3136 if (netif_running(dev))
3137 sky2_down(dev);
3138
3139 sky2->rx_pending = ering->rx_pending;
3140 sky2->tx_pending = ering->tx_pending;
3141
1b537565 3142 if (netif_running(dev)) {
793b883e 3143 err = sky2_up(dev);
1b537565
SH		 3144 if (err)
3145 dev_close(dev);
6ed995bb
SH		 3146 else
3147 sky2_set_multicast(dev);
1b537565 3148 }
793b883e
SH		 3149
3150 return err;
3151}
3152
793b883e
SH		 3153static int sky2_get_regs_len(struct net_device *dev)
3154{
6e4cbb34 3155 return 0x4000;
793b883e
SH		 3156}
3157
3158/*
3159 * Returns copy of control register region
6e4cbb34 3160 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3161 */
3162static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3163 void *p)
3164{
3165 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3166 const void __iomem *io = sky2->hw->regs;
793b883e 3167
6e4cbb34 3168 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3169 regs->version = 1;
6e4cbb34 3170 memset(p, 0, regs->len);
793b883e 3171
6e4cbb34
SH		 3172 memcpy_fromio(p, io, B3_RAM_ADDR);
3173
3174 memcpy_fromio(p + B3_RI_WTO_R1,
3175 io + B3_RI_WTO_R1,
3176 regs->len - B3_RI_WTO_R1);
793b883e 3177}
cd28ab6a 3178
7282d491 3179static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3180 .get_settings = sky2_get_settings,
3181 .set_settings = sky2_set_settings,
3182 .get_drvinfo = sky2_get_drvinfo,
3183 .get_msglevel = sky2_get_msglevel,
3184 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3185 .nway_reset = sky2_nway_reset,
793b883e
SH		 3186 .get_regs_len = sky2_get_regs_len,
3187 .get_regs = sky2_get_regs,
3188 .get_link = ethtool_op_get_link,
3189 .get_sg = ethtool_op_get_sg,
3190 .set_sg = ethtool_op_set_sg,
3191 .get_tx_csum = ethtool_op_get_tx_csum,
3192 .set_tx_csum = ethtool_op_set_tx_csum,
3193 .get_tso = ethtool_op_get_tso,
3194 .set_tso = ethtool_op_set_tso,
3195 .get_rx_csum = sky2_get_rx_csum,
3196 .set_rx_csum = sky2_set_rx_csum,
3197 .get_strings = sky2_get_strings,
fb17358f
SH		 3198 .get_coalesce = sky2_get_coalesce,
3199 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3200 .get_ringparam = sky2_get_ringparam,
3201 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3202 .get_pauseparam = sky2_get_pauseparam,
3203 .set_pauseparam = sky2_set_pauseparam,
793b883e 3204 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3205 .get_stats_count = sky2_get_stats_count,
3206 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3207 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3208};
3209
3210/* Initialize network device */
3211static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3212 unsigned port, int highmem)
3213{
3214 struct sky2_port *sky2;
3215 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3216
3217 if (!dev) {
3218 printk(KERN_ERR "sky2 etherdev alloc failed");
3219 return NULL;
3220 }
3221
3222 SET_MODULE_OWNER(dev);
3223 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3224 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3225 dev->open = sky2_up;
3226 dev->stop = sky2_down;
ef743d33 3227 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3228 dev->hard_start_xmit = sky2_xmit_frame;
3229 dev->get_stats = sky2_get_stats;
3230 dev->set_multicast_list = sky2_set_multicast;
3231 dev->set_mac_address = sky2_set_mac_address;
3232 dev->change_mtu = sky2_change_mtu;
3233 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3234 dev->tx_timeout = sky2_tx_timeout;
3235 dev->watchdog_timeo = TX_WATCHDOG;
3236 if (port == 0)
3237 dev->poll = sky2_poll;
3238 dev->weight = NAPI_WEIGHT;
3239#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3240 /* Network console (only works on port 0)
3241 * because netpoll makes assumptions about NAPI
3242 */
3243 if (port == 0)
3244 dev->poll_controller = sky2_netpoll;
cd28ab6a 3245#endif
cd28ab6a
SH		 3246
3247 sky2 = netdev_priv(dev);
3248 sky2->netdev = dev;
3249 sky2->hw = hw;
3250 sky2->msg_enable = netif_msg_init(debug, default_msg);
3251
cd28ab6a
SH		 3252 /* Auto speed and flow control */
3253 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3254 sky2->flow_mode = FC_BOTH;
3255
cd28ab6a
SH		 3256 sky2->duplex = -1;
3257 sky2->speed = -1;
3258 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3259 sky2->rx_csum = 1;
75d070c5 3260
e07b1aa8 3261 spin_lock_init(&sky2->phy_lock);
793b883e 3262 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3263 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3264
3265 hw->dev[port] = dev;
3266
3267 sky2->port = port;
3268
5a5b1ea0 3269 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3270 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3271 if (highmem)
3272 dev->features |= NETIF_F_HIGHDMA;
793b883e 3273 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3274
d1f13708 3275#ifdef SKY2_VLAN_TAG_USED
3276 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3277 dev->vlan_rx_register = sky2_vlan_rx_register;
3278 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3279#endif
3280
cd28ab6a 3281 /* read the mac address */
793b883e 3282 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3283 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3284
3285 /* device is off until link detection */
3286 netif_carrier_off(dev);
3287 netif_stop_queue(dev);
3288
3289 return dev;
3290}
3291
28bd181a 3292static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3293{
3294 const struct sky2_port *sky2 = netdev_priv(dev);
3295
3296 if (netif_msg_probe(sky2))
3297 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3298 dev->name,
3299 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3300 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3301}
3302
fb2690a9 3303/* Handle software interrupt used during MSI test */
7d12e780 3304static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3305{
3306 struct sky2_hw *hw = dev_id;
3307 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3308
3309 if (status == 0)
3310 return IRQ_NONE;
3311
3312 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3313 hw->msi = 1;
fb2690a9
SH		 3314 wake_up(&hw->msi_wait);
3315 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3316 }
3317 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3318
3319 return IRQ_HANDLED;
3320}
3321
3322/* Test interrupt path by forcing a a software IRQ */
3323static int __devinit sky2_test_msi(struct sky2_hw *hw)
3324{
3325 struct pci_dev *pdev = hw->pdev;
3326 int err;
3327
bb507fe1 3328 init_waitqueue_head (&hw->msi_wait);
3329
fb2690a9
SH		 3330 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3331
b0a20ded 3332 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9
SH		 3333 if (err) {
3334 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3335 pci_name(pdev), pdev->irq);
3336 return err;
3337 }
3338
fb2690a9 3339 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3340 sky2_read8(hw, B0_CTST);
fb2690a9 3341
b0a20ded 3342 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3343
b0a20ded 3344 if (!hw->msi) {
fb2690a9 3345 /* MSI test failed, go back to INTx mode */
2bffc23a
SH		 3346 printk(KERN_INFO PFX "%s: No interrupt generated using MSI, "
3347 "switching to INTx mode.\n",
fb2690a9
SH		 3348 pci_name(pdev));
3349
3350 err = -EOPNOTSUPP;
3351 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3352 }
3353
3354 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3355 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3356
3357 free_irq(pdev->irq, hw);
3358
3359 return err;
3360}
3361
cd28ab6a
SH		 3362static int __devinit sky2_probe(struct pci_dev *pdev,
3363 const struct pci_device_id *ent)
3364{
793b883e 3365 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3366 struct sky2_hw *hw;
5afa0a9c 3367 int err, pm_cap, using_dac = 0;
cd28ab6a 3368
793b883e
SH		 3369 err = pci_enable_device(pdev);
3370 if (err) {
cd28ab6a
SH		 3371 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3372 pci_name(pdev));
3373 goto err_out;
3374 }
3375
793b883e
SH		 3376 err = pci_request_regions(pdev, DRV_NAME);
3377 if (err) {
cd28ab6a
SH		 3378 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3379 pci_name(pdev));
793b883e 3380 goto err_out;
cd28ab6a
SH		 3381 }
3382
3383 pci_set_master(pdev);
3384
5afa0a9c 3385 /* Find power-management capability. */
3386 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3387 if (pm_cap == 0) {
3388 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3389 "aborting.\n");
3390 err = -EIO;
3391 goto err_out_free_regions;
3392 }
3393
d1f3d4dd
SH		 3394 if (sizeof(dma_addr_t) > sizeof(u32) &&
3395 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3396 using_dac = 1;
3397 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3398 if (err < 0) {
3399 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3400 "for consistent allocations\n", pci_name(pdev));
3401 goto err_out_free_regions;
3402 }
cd28ab6a 3403
d1f3d4dd 3404 } else {
cd28ab6a
SH		 3405 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3406 if (err) {
3407 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3408 pci_name(pdev));
3409 goto err_out_free_regions;
3410 }
3411 }
d1f3d4dd 3412
cd28ab6a 3413 err = -ENOMEM;
6aad85d6 3414 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3415 if (!hw) {
3416 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3417 pci_name(pdev));
3418 goto err_out_free_regions;
3419 }
3420
cd28ab6a 3421 hw->pdev = pdev;
cd28ab6a
SH		 3422
3423 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3424 if (!hw->regs) {
3425 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3426 pci_name(pdev));
3427 goto err_out_free_hw;
3428 }
5afa0a9c 3429 hw->pm_cap = pm_cap;
cd28ab6a 3430
56a645cc 3431#ifdef __BIG_ENDIAN
f65b138c
SH		 3432 /* The sk98lin vendor driver uses hardware byte swapping but
3433 * this driver uses software swapping.
3434 */
56a645cc
SH		 3435 {
3436 u32 reg;
56a645cc 3437 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3438 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3439 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3440 }
3441#endif
3442
08c06d8a
SH		 3443 /* ring for status responses */
3444 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3445 &hw->st_dma);
3446 if (!hw->st_le)
3447 goto err_out_iounmap;
3448
cd28ab6a
SH		 3449 err = sky2_reset(hw);
3450 if (err)
793b883e 3451 goto err_out_iounmap;
cd28ab6a 3452
7c7459d1
GKH		 3453 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3454 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3455 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3456 hw->chip_id, hw->chip_rev);
cd28ab6a 3457
793b883e
SH		 3458 dev = sky2_init_netdev(hw, 0, using_dac);
3459 if (!dev)
cd28ab6a
SH		 3460 goto err_out_free_pci;
3461
9fa1b1f3
SH		 3462 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3463 err = sky2_test_msi(hw);
3464 if (err == -EOPNOTSUPP)
3465 pci_disable_msi(pdev);
3466 else if (err)
3467 goto err_out_free_netdev;
3468 }
3469
793b883e
SH		 3470 err = register_netdev(dev);
3471 if (err) {
cd28ab6a
SH		 3472 printk(KERN_ERR PFX "%s: cannot register net device\n",
3473 pci_name(pdev));
3474 goto err_out_free_netdev;
3475 }
3476
b0a20ded
SH		 3477 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3478 dev->name, hw);
9fa1b1f3
SH		 3479 if (err) {
3480 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3481 pci_name(pdev), pdev->irq);
3482 goto err_out_unregister;
3483 }
3484 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3485
cd28ab6a
SH		 3486 sky2_show_addr(dev);
3487
3488 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3489 if (register_netdev(dev1) == 0)
3490 sky2_show_addr(dev1);
3491 else {
3492 /* Failure to register second port need not be fatal */
793b883e
SH		 3493 printk(KERN_WARNING PFX
3494 "register of second port failed\n");
cd28ab6a
SH		 3495 hw->dev[1] = NULL;
3496 free_netdev(dev1);
3497 }
3498 }
3499
01bd7564 3500 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
eb35cf60 3501 sky2_idle_start(hw);
d27ed387 3502
793b883e
SH		 3503 pci_set_drvdata(pdev, hw);
3504
cd28ab6a
SH		 3505 return 0;
3506
793b883e 3507err_out_unregister:
b0a20ded
SH		 3508 if (hw->msi)
3509 pci_disable_msi(pdev);
793b883e 3510 unregister_netdev(dev);
cd28ab6a
SH		 3511err_out_free_netdev:
3512 free_netdev(dev);
cd28ab6a 3513err_out_free_pci:
793b883e 3514 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3515 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3516err_out_iounmap:
3517 iounmap(hw->regs);
3518err_out_free_hw:
3519 kfree(hw);
3520err_out_free_regions:
3521 pci_release_regions(pdev);
cd28ab6a 3522 pci_disable_device(pdev);
cd28ab6a
SH		 3523err_out:
3524 return err;
3525}
3526
3527static void __devexit sky2_remove(struct pci_dev *pdev)
3528{
793b883e 3529 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3530 struct net_device *dev0, *dev1;
3531
793b883e 3532 if (!hw)
cd28ab6a
SH		 3533 return;
3534
d27ed387
SH		 3535 del_timer_sync(&hw->idle_timer);
3536
3537 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3538 synchronize_irq(hw->pdev->irq);
3539
cd28ab6a 3540 dev0 = hw->dev[0];
793b883e
SH		 3541 dev1 = hw->dev[1];
3542 if (dev1)
3543 unregister_netdev(dev1);
cd28ab6a
SH		 3544 unregister_netdev(dev0);
3545
5afa0a9c 3546 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3547 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3548 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3549 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3550
3551 free_irq(pdev->irq, hw);
b0a20ded
SH		 3552 if (hw->msi)
3553 pci_disable_msi(pdev);
793b883e 3554 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3555 pci_release_regions(pdev);
3556 pci_disable_device(pdev);
793b883e 3557
cd28ab6a
SH		 3558 if (dev1)
3559 free_netdev(dev1);
3560 free_netdev(dev0);
3561 iounmap(hw->regs);
3562 kfree(hw);
5afa0a9c 3563
cd28ab6a
SH		 3564 pci_set_drvdata(pdev, NULL);
3565}
3566
3567#ifdef CONFIG_PM
3568static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3569{
793b883e 3570 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3571 int i;
2ccc99b7
SH		 3572 pci_power_t pstate = pci_choose_state(pdev, state);
3573
3574 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3575 return -EINVAL;
cd28ab6a 3576
eb35cf60 3577 del_timer_sync(&hw->idle_timer);
6a5706b9 3578 netif_poll_disable(hw->dev[0]);
eb35cf60 3579
f05267e7 3580 for (i = 0; i < hw->ports; i++) {
cd28ab6a
SH		 3581 struct net_device *dev = hw->dev[i];
3582
6a5706b9 3583 if (netif_running(dev)) {
5afa0a9c 3584 sky2_down(dev);
cd28ab6a 3585 netif_device_detach(dev);
cd28ab6a
SH		 3586 }
3587 }
3588
8ab8fca2 3589 sky2_write32(hw, B0_IMSK, 0);
d374c1c1 3590 pci_save_state(pdev);
2ccc99b7
SH		 3591 sky2_set_power_state(hw, pstate);
3592 return 0;
cd28ab6a
SH		 3593}
3594
3595static int sky2_resume(struct pci_dev *pdev)
3596{
793b883e 3597 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3598 int i, err;
cd28ab6a 3599
cd28ab6a
SH		 3600 pci_restore_state(pdev);
3601 pci_enable_wake(pdev, PCI_D0, 0);
2ccc99b7 3602 sky2_set_power_state(hw, PCI_D0);
cd28ab6a 3603
08c06d8a
SH		 3604 err = sky2_reset(hw);
3605 if (err)
3606 goto out;
cd28ab6a 3607
8ab8fca2
SH		 3608 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3609
f05267e7 3610 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3611 struct net_device *dev = hw->dev[i];
6a5706b9 3612 if (netif_running(dev)) {
08c06d8a 3613 netif_device_attach(dev);
88d11360 3614
08c06d8a
SH		 3615 err = sky2_up(dev);
3616 if (err) {
3617 printk(KERN_ERR PFX "%s: could not up: %d\n",
3618 dev->name, err);
3619 dev_close(dev);
eb35cf60 3620 goto out;
5afa0a9c 3621 }
cd28ab6a
SH		 3622 }
3623 }
eb35cf60 3624
6a5706b9 3625 netif_poll_enable(hw->dev[0]);
eb35cf60 3626 sky2_idle_start(hw);
08c06d8a
SH		 3627out:
3628 return err;
cd28ab6a
SH		 3629}
3630#endif
3631
3632static struct pci_driver sky2_driver = {
793b883e
SH		 3633 .name = DRV_NAME,
3634 .id_table = sky2_id_table,
3635 .probe = sky2_probe,
3636 .remove = __devexit_p(sky2_remove),
cd28ab6a 3637#ifdef CONFIG_PM
793b883e
SH		 3638 .suspend = sky2_suspend,
3639 .resume = sky2_resume,
cd28ab6a
SH		 3640#endif
3641};
3642
3643static int __init sky2_init_module(void)
3644{
50241c4c 3645 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3646}
3647
3648static void __exit sky2_cleanup_module(void)
3649{
3650 pci_unregister_driver(&sky2_driver);
3651}
3652
3653module_init(sky2_init_module);
3654module_exit(sky2_cleanup_module);
3655
3656MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3657MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3658MODULE_LICENSE("GPL");
5f4f9dc1 3659MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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