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[PATCH] sky2: add MII support
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26/*
27 * TODO
28 * - coalescing setting?
cd28ab6a
SH		 29 *
30 * TOTEST
31 * - speed setting
724bca3c 32 * - suspend/resume
cd28ab6a
SH		 33 */
34
35#include <linux/config.h>
793b883e 36#include <linux/crc32.h>
cd28ab6a
SH		 37#include <linux/kernel.h>
38#include <linux/version.h>
39#include <linux/module.h>
40#include <linux/netdevice.h>
d0bbccfa 41#include <linux/dma-mapping.h>
cd28ab6a
SH		 42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/pci.h>
45#include <linux/ip.h>
46#include <linux/tcp.h>
47#include <linux/in.h>
48#include <linux/delay.h>
d1f13708 49#include <linux/if_vlan.h>
ef743d33 50#include <linux/mii.h>
cd28ab6a
SH		 51
52#include <asm/irq.h>
53
d1f13708 54#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
55#define SKY2_VLAN_TAG_USED 1
56#endif
57
cd28ab6a
SH		 58#include "sky2.h"
59
60#define DRV_NAME "sky2"
f1e691a2 61#define DRV_VERSION "0.7"
cd28ab6a
SH		 62#define PFX DRV_NAME " "
63
64/*
65 * The Yukon II chipset takes 64 bit command blocks (called list elements)
66 * that are organized into three (receive, transmit, status) different rings
67 * similar to Tigon3. A transmit can require several elements;
68 * a receive requires one (or two if using 64 bit dma).
69 */
70
cd28ab6a 71#define is_ec_a1(hw) \
21437643 72 unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
73 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
cd28ab6a 74
793b883e 75#define RX_LE_SIZE 256
cd28ab6a 76#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
bea86103 77#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
793b883e 78#define RX_DEF_PENDING 128
79e57d32 79#define RX_COPY_THRESHOLD 256
793b883e
SH		 80
81#define TX_RING_SIZE 512
82#define TX_DEF_PENDING (TX_RING_SIZE - 1)
83#define TX_MIN_PENDING 64
84#define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
cd28ab6a 85
793b883e 86#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 87#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
88#define ETH_JUMBO_MTU 9000
89#define TX_WATCHDOG (5 * HZ)
90#define NAPI_WEIGHT 64
91#define PHY_RETRIES 1000
92
93static const u32 default_msg =
793b883e
SH		 94 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
95 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
96 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
cd28ab6a 97
793b883e 98static int debug = -1; /* defaults above */
cd28ab6a
SH		 99module_param(debug, int, 0);
100MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
101
102static const struct pci_device_id sky2_id_table[] = {
793b883e 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a
SH		 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
120 { 0 }
121};
793b883e 122
cd28ab6a
SH		 123MODULE_DEVICE_TABLE(pci, sky2_id_table);
124
125/* Avoid conditionals by using array */
126static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
127static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
128
793b883e
SH		 129static const char *yukon_name[] = {
130 [CHIP_ID_YUKON_LITE - CHIP_ID_YUKON] = "Lite", /* 0xb0 */
131 [CHIP_ID_YUKON_LP - CHIP_ID_YUKON] = "LP", /* 0xb2 */
132 [CHIP_ID_YUKON_XL - CHIP_ID_YUKON] = "XL", /* 0xb3 */
cd28ab6a 133
793b883e
SH		 134 [CHIP_ID_YUKON_EC - CHIP_ID_YUKON] = "EC", /* 0xb6 */
135 [CHIP_ID_YUKON_FE - CHIP_ID_YUKON] = "FE", /* 0xb7 */
136};
137
138
139/* Access to external PHY */
ef743d33 140static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 141{
142 int i;
143
144 gma_write16(hw, port, GM_SMI_DATA, val);
145 gma_write16(hw, port, GM_SMI_CTRL,
146 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
147
148 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 149 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 150 return 0;
793b883e 151 udelay(1);
cd28ab6a 152 }
ef743d33 153
793b883e 154 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 155 return -ETIMEDOUT;
cd28ab6a
SH		 156}
157
ef743d33 158static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 159{
160 int i;
161
793b883e 162 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 163 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
164
165 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33 166 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
167 *val = gma_read16(hw, port, GM_SMI_DATA);
168 return 0;
169 }
170
793b883e 171 udelay(1);
cd28ab6a
SH		 172 }
173
ef743d33 174 return -ETIMEDOUT;
175}
176
177static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
178{
179 u16 v;
180
181 if (__gm_phy_read(hw, port, reg, &v) != 0)
182 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
183 return v;
cd28ab6a
SH		 184}
185
5afa0a9c 186static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
187{
188 u16 power_control;
189 u32 reg1;
190 int vaux;
191 int ret = 0;
192
193 pr_debug("sky2_set_power_state %d\n", state);
194 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
195
196 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
197 vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
198 (power_control & PCI_PM_CAP_PME_D3cold);
199
200 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
201
202 power_control |= PCI_PM_CTRL_PME_STATUS;
203 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
204
205 switch (state) {
206 case PCI_D0:
207 /* switch power to VCC (WA for VAUX problem) */
208 sky2_write8(hw, B0_POWER_CTRL,
209 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
210
211 /* disable Core Clock Division, */
212 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
213
214 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
215 /* enable bits are inverted */
216 sky2_write8(hw, B2_Y2_CLK_GATE,
217 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
218 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
219 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
220 else
221 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
222
223 /* Turn off phy power saving */
224 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
225 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
226
d571b694 227 /* looks like this XL is back asswards .. */
5afa0a9c 228 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
229 reg1 |= PCI_Y2_PHY1_COMA;
230 if (hw->ports > 1)
231 reg1 |= PCI_Y2_PHY2_COMA;
232 }
233 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
234 break;
235
236 case PCI_D3hot:
237 case PCI_D3cold:
238 /* Turn on phy power saving */
239 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
240 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
241 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
242 else
243 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
244 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
245
246 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
247 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
248 else
249 /* enable bits are inverted */
250 sky2_write8(hw, B2_Y2_CLK_GATE,
251 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
252 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
253 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
254
255 /* switch power to VAUX */
256 if (vaux && state != PCI_D3cold)
257 sky2_write8(hw, B0_POWER_CTRL,
258 (PC_VAUX_ENA | PC_VCC_ENA |
259 PC_VAUX_ON | PC_VCC_OFF));
260 break;
261 default:
262 printk(KERN_ERR PFX "Unknown power state %d\n", state);
263 ret = -1;
264 }
265
266 pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
267 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
268 return ret;
269}
270
cd28ab6a
SH		 271static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
272{
273 u16 reg;
274
275 /* disable all GMAC IRQ's */
276 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
277 /* disable PHY IRQs */
278 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 279
cd28ab6a
SH		 280 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
281 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
282 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
283 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
284
285 reg = gma_read16(hw, port, GM_RX_CTRL);
286 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
287 gma_write16(hw, port, GM_RX_CTRL, reg);
288}
289
290static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
291{
292 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
793b883e 293 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
cd28ab6a 294
793b883e 295 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
cd28ab6a
SH		 296 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
297
298 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 299 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 300 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
301
302 if (hw->chip_id == CHIP_ID_YUKON_EC)
303 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
304 else
305 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
306
307 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
308 }
309
310 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
311 if (hw->copper) {
312 if (hw->chip_id == CHIP_ID_YUKON_FE) {
313 /* enable automatic crossover */
314 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
315 } else {
316 /* disable energy detect */
317 ctrl &= ~PHY_M_PC_EN_DET_MSK;
318
319 /* enable automatic crossover */
320 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
321
322 if (sky2->autoneg == AUTONEG_ENABLE &&
323 hw->chip_id == CHIP_ID_YUKON_XL) {
324 ctrl &= ~PHY_M_PC_DSC_MSK;
325 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
326 }
327 }
328 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
329 } else {
330 /* workaround for deviation #4.88 (CRC errors) */
331 /* disable Automatic Crossover */
332
333 ctrl &= ~PHY_M_PC_MDIX_MSK;
334 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
335
336 if (hw->chip_id == CHIP_ID_YUKON_XL) {
337 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
338 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
339 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
340 ctrl &= ~PHY_M_MAC_MD_MSK;
341 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
342 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
343
344 /* select page 1 to access Fiber registers */
345 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
346 }
cd28ab6a
SH		 347 }
348
349 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
350 if (sky2->autoneg == AUTONEG_DISABLE)
351 ctrl &= ~PHY_CT_ANE;
352 else
353 ctrl |= PHY_CT_ANE;
354
355 ctrl |= PHY_CT_RESET;
356 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
357
358 ctrl = 0;
359 ct1000 = 0;
360 adv = PHY_AN_CSMA;
361
362 if (sky2->autoneg == AUTONEG_ENABLE) {
363 if (hw->copper) {
364 if (sky2->advertising & ADVERTISED_1000baseT_Full)
365 ct1000 |= PHY_M_1000C_AFD;
366 if (sky2->advertising & ADVERTISED_1000baseT_Half)
367 ct1000 |= PHY_M_1000C_AHD;
368 if (sky2->advertising & ADVERTISED_100baseT_Full)
369 adv |= PHY_M_AN_100_FD;
370 if (sky2->advertising & ADVERTISED_100baseT_Half)
371 adv |= PHY_M_AN_100_HD;
372 if (sky2->advertising & ADVERTISED_10baseT_Full)
373 adv |= PHY_M_AN_10_FD;
374 if (sky2->advertising & ADVERTISED_10baseT_Half)
375 adv |= PHY_M_AN_10_HD;
793b883e 376 } else /* special defines for FIBER (88E1011S only) */
cd28ab6a
SH		 377 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
378
379 /* Set Flow-control capabilities */
380 if (sky2->tx_pause && sky2->rx_pause)
793b883e 381 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 382 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 383 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 384 else if (!sky2->rx_pause && sky2->tx_pause)
385 adv |= PHY_AN_PAUSE_ASYM; /* local */
386
387 /* Restart Auto-negotiation */
388 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
389 } else {
390 /* forced speed/duplex settings */
391 ct1000 = PHY_M_1000C_MSE;
392
393 if (sky2->duplex == DUPLEX_FULL)
394 ctrl |= PHY_CT_DUP_MD;
395
396 switch (sky2->speed) {
397 case SPEED_1000:
398 ctrl |= PHY_CT_SP1000;
399 break;
400 case SPEED_100:
401 ctrl |= PHY_CT_SP100;
402 break;
403 }
404
405 ctrl |= PHY_CT_RESET;
406 }
407
408 if (hw->chip_id != CHIP_ID_YUKON_FE)
409 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
410
411 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
412 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
413
414 /* Setup Phy LED's */
415 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
416 ledover = 0;
417
418 switch (hw->chip_id) {
419 case CHIP_ID_YUKON_FE:
420 /* on 88E3082 these bits are at 11..9 (shifted left) */
421 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
422
423 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
424
425 /* delete ACT LED control bits */
426 ctrl &= ~PHY_M_FELP_LED1_MSK;
427 /* change ACT LED control to blink mode */
428 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
429 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
430 break;
431
432 case CHIP_ID_YUKON_XL:
793b883e 433 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 434
435 /* select page 3 to access LED control register */
436 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
437
438 /* set LED Function Control register */
793b883e
SH		 439 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
440 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
441 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
442 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 443
444 /* set Polarity Control register */
445 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 446 (PHY_M_POLC_LS1_P_MIX(4) |
447 PHY_M_POLC_IS0_P_MIX(4) |
448 PHY_M_POLC_LOS_CTRL(2) |
449 PHY_M_POLC_INIT_CTRL(2) |
450 PHY_M_POLC_STA1_CTRL(2) |
451 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 452
453 /* restore page register */
793b883e 454 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 455 break;
456
457 default:
458 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
459 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
460 /* turn off the Rx LED (LED_RX) */
461 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
462 }
463
464 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
465
466 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
467 /* turn on 100 Mbps LED (LED_LINK100) */
468 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
469 }
470
471 if (ledover)
472 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
473
d571b694 474 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 475 if (sky2->autoneg == AUTONEG_ENABLE)
476 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
477 else
478 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
479}
480
481static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
482{
483 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
484 u16 reg;
485 int i;
486 const u8 *addr = hw->dev[port]->dev_addr;
487
488 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
489 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
490
491 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
492
793b883e 493 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 494 /* WA DEV_472 -- looks like crossed wires on port 2 */
495 /* clear GMAC 1 Control reset */
496 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
497 do {
498 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
499 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
500 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
501 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
502 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
503 }
504
cd28ab6a
SH		 505 if (sky2->autoneg == AUTONEG_DISABLE) {
506 reg = gma_read16(hw, port, GM_GP_CTRL);
507 reg |= GM_GPCR_AU_ALL_DIS;
508 gma_write16(hw, port, GM_GP_CTRL, reg);
509 gma_read16(hw, port, GM_GP_CTRL);
510
cd28ab6a
SH		 511 switch (sky2->speed) {
512 case SPEED_1000:
513 reg |= GM_GPCR_SPEED_1000;
514 /* fallthru */
515 case SPEED_100:
516 reg |= GM_GPCR_SPEED_100;
517 }
518
519 if (sky2->duplex == DUPLEX_FULL)
520 reg |= GM_GPCR_DUP_FULL;
521 } else
522 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
523
524 if (!sky2->tx_pause && !sky2->rx_pause) {
525 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e
SH		 526 reg |=
527 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
528 } else if (sky2->tx_pause && !sky2->rx_pause) {
cd28ab6a
SH		 529 /* disable Rx flow-control */
530 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
531 }
532
533 gma_write16(hw, port, GM_GP_CTRL, reg);
534
793b883e 535 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a
SH		 536
537 spin_lock_bh(&hw->phy_lock);
538 sky2_phy_init(hw, port);
539 spin_unlock_bh(&hw->phy_lock);
540
541 /* MIB clear */
542 reg = gma_read16(hw, port, GM_PHY_ADDR);
543 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
544
545 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
793b883e 546 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
cd28ab6a
SH		 547 gma_write16(hw, port, GM_PHY_ADDR, reg);
548
549 /* transmit control */
550 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
551
552 /* receive control reg: unicast + multicast + no FCS */
553 gma_write16(hw, port, GM_RX_CTRL,
793b883e 554 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 555
556 /* transmit flow control */
557 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
558
559 /* transmit parameter */
560 gma_write16(hw, port, GM_TX_PARAM,
561 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
562 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
563 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
564 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
565
566 /* serial mode register */
567 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 568 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 569
6b1a3aef 570 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 571 reg |= GM_SMOD_JUMBO_ENA;
572
573 gma_write16(hw, port, GM_SERIAL_MODE, reg);
574
cd28ab6a
SH		 575 /* virtual address for data */
576 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
577
793b883e
SH		 578 /* physical address: used for pause frames */
579 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
580
581 /* ignore counter overflows */
cd28ab6a
SH		 582 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
583 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
584 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
585
586 /* Configure Rx MAC FIFO */
587 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
793b883e 588 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
d1f13708 589 GMF_RX_CTRL_DEF);
cd28ab6a 590
d571b694 591 /* Flush Rx MAC FIFO on any flow control or error */
793b883e 592 reg = GMR_FS_ANY_ERR;
cd28ab6a 593 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev <= 1)
d571b694 594 reg = 0; /* WA dev #4.115 */
cd28ab6a
SH		 595
596 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), reg);
793b883e
SH		 597 /* Set threshold to 0xa (64 bytes)
598 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 599 */
600 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
601
602 /* Configure Tx MAC FIFO */
603 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
604 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
cd28ab6a
SH		 605}
606
607static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
608{
609 u32 end;
610
611 start /= 8;
612 len /= 8;
613 end = start + len - 1;
793b883e 614
cd28ab6a
SH		 615 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
616 sky2_write32(hw, RB_ADDR(q, RB_START), start);
617 sky2_write32(hw, RB_ADDR(q, RB_END), end);
618 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
619 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
620
621 if (q == Q_R1 || q == Q_R2) {
793b883e
SH		 622 u32 rxup, rxlo;
623
624 rxlo = len/2;
625 rxup = rxlo + len/4;
793b883e 626
cd28ab6a 627 /* Set thresholds on receive queue's */
793b883e
SH		 628 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup);
629 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo);
cd28ab6a
SH		 630 } else {
631 /* Enable store & forward on Tx queue's because
632 * Tx FIFO is only 1K on Yukon
633 */
634 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
635 }
636
637 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 638 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 639}
640
cd28ab6a
SH		 641/* Setup Bus Memory Interface */
642static void sky2_qset(struct sky2_hw *hw, u16 q, u32 wm)
643{
644 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
645 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
646 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
647 sky2_write32(hw, Q_ADDR(q, Q_WM), wm);
648}
649
cd28ab6a
SH		 650/* Setup prefetch unit registers. This is the interface between
651 * hardware and driver list elements
652 */
653static inline void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
654 u64 addr, u32 last)
655{
cd28ab6a
SH		 656 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
657 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
658 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
659 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
660 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
661 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 662
663 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 664}
665
793b883e
SH		 666static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
667{
668 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
669
670 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
671 return le;
672}
cd28ab6a
SH		 673
674/*
d571b694 675 * This is a workaround code taken from SysKonnect sk98lin driver
793b883e 676 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
cd28ab6a
SH		 677 */
678static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
679 u16 idx, u16 *last, u16 size)
cd28ab6a 680{
cd28ab6a
SH		 681 if (is_ec_a1(hw) && idx < *last) {
682 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
683
684 if (hwget == 0) {
685 /* Start prefetching again */
793b883e 686 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
cd28ab6a
SH		 687 goto setnew;
688 }
689
793b883e 690 if (hwget == size - 1) {
cd28ab6a
SH		 691 /* set watermark to one list element */
692 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
693
694 /* set put index to first list element */
695 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
793b883e
SH		 696 } else /* have hardware go to end of list */
697 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
698 size - 1);
cd28ab6a 699 } else {
793b883e 700setnew:
cd28ab6a 701 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
cd28ab6a 702 }
bea86103 703 *last = idx;
cd28ab6a
SH		 704}
705
793b883e 706
cd28ab6a
SH		 707static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
708{
709 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
710 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
711 return le;
712}
713
793b883e
SH		 714/* Build description to hardware about buffer */
715static inline void sky2_rx_add(struct sky2_port *sky2, struct ring_info *re)
cd28ab6a
SH		 716{
717 struct sky2_rx_le *le;
793b883e 718 u32 hi = (re->mapaddr >> 16) >> 16;
cd28ab6a 719
793b883e
SH		 720 re->idx = sky2->rx_put;
721 if (sky2->rx_addr64 != hi) {
cd28ab6a 722 le = sky2_next_rx(sky2);
793b883e 723 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 724 le->ctrl = 0;
725 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 726 sky2->rx_addr64 = hi;
cd28ab6a 727 }
793b883e 728
cd28ab6a 729 le = sky2_next_rx(sky2);
793b883e
SH		 730 le->addr = cpu_to_le32((u32) re->mapaddr);
731 le->length = cpu_to_le16(re->maplen);
cd28ab6a
SH		 732 le->ctrl = 0;
733 le->opcode = OP_PACKET | HW_OWNER;
734}
735
793b883e 736
cd28ab6a
SH		 737/* Tell chip where to start receive checksum.
738 * Actually has two checksums, but set both same to avoid possible byte
739 * order problems.
740 */
793b883e 741static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 742{
743 struct sky2_rx_le *le;
744
cd28ab6a 745 le = sky2_next_rx(sky2);
793b883e 746 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
cd28ab6a
SH		 747 le->ctrl = 0;
748 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 749
793b883e
SH		 750 sky2_write32(sky2->hw,
751 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
752 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 753
754}
755
6b1a3aef 756/*
757 * The RX Stop command will not work for Yukon-2 if the BMU does not
758 * reach the end of packet and since we can't make sure that we have
759 * incoming data, we must reset the BMU while it is not doing a DMA
760 * transfer. Since it is possible that the RX path is still active,
761 * the RX RAM buffer will be stopped first, so any possible incoming
762 * data will not trigger a DMA. After the RAM buffer is stopped, the
763 * BMU is polled until any DMA in progress is ended and only then it
764 * will be reset.
765 */
766static void sky2_rx_stop(struct sky2_port *sky2)
767{
768 struct sky2_hw *hw = sky2->hw;
769 unsigned rxq = rxqaddr[sky2->port];
770 int i;
771
772 /* disable the RAM Buffer receive queue */
773 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
774
775 for (i = 0; i < 0xffff; i++)
776 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
777 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
778 goto stopped;
779
780 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
781 sky2->netdev->name);
782stopped:
783 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
784
785 /* reset the Rx prefetch unit */
786 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
787}
793b883e 788
d571b694 789/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 790static void sky2_rx_clean(struct sky2_port *sky2)
791{
792 unsigned i;
793
794 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 795 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 796 struct ring_info *re = sky2->rx_ring + i;
797
798 if (re->skb) {
793b883e
SH		 799 pci_unmap_single(sky2->hw->pdev,
800 re->mapaddr, re->maplen,
cd28ab6a
SH		 801 PCI_DMA_FROMDEVICE);
802 kfree_skb(re->skb);
803 re->skb = NULL;
804 }
805 }
806}
807
ef743d33 808/* Basic MII support */
809static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
810{
811 struct mii_ioctl_data *data = if_mii(ifr);
812 struct sky2_port *sky2 = netdev_priv(dev);
813 struct sky2_hw *hw = sky2->hw;
814 int err = -EOPNOTSUPP;
815
816 if (!netif_running(dev))
817 return -ENODEV; /* Phy still in reset */
818
819 switch(cmd) {
820 case SIOCGMIIPHY:
821 data->phy_id = PHY_ADDR_MARV;
822
823 /* fallthru */
824 case SIOCGMIIREG: {
825 u16 val = 0;
826 spin_lock_bh(&hw->phy_lock);
827 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
828 spin_unlock_bh(&hw->phy_lock);
829 data->val_out = val;
830 break;
831 }
832
833 case SIOCSMIIREG:
834 if (!capable(CAP_NET_ADMIN))
835 return -EPERM;
836
837 spin_lock_bh(&hw->phy_lock);
838 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
839 data->val_in);
840 spin_unlock_bh(&hw->phy_lock);
841 break;
842 }
843 return err;
844}
845
d1f13708 846#ifdef SKY2_VLAN_TAG_USED
847static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
848{
849 struct sky2_port *sky2 = netdev_priv(dev);
850 struct sky2_hw *hw = sky2->hw;
851 u16 port = sky2->port;
852 unsigned long flags;
853
854 spin_lock_irqsave(&sky2->tx_lock, flags);
855
856 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
857 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
858 sky2->vlgrp = grp;
859
860 spin_unlock_irqrestore(&sky2->tx_lock, flags);
861}
862
863static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
864{
865 struct sky2_port *sky2 = netdev_priv(dev);
866 struct sky2_hw *hw = sky2->hw;
867 u16 port = sky2->port;
868 unsigned long flags;
869
870 spin_lock_irqsave(&sky2->tx_lock, flags);
871
872 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
873 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
874 if (sky2->vlgrp)
875 sky2->vlgrp->vlan_devices[vid] = NULL;
876
877 spin_unlock_irqrestore(&sky2->tx_lock, flags);
878}
879#endif
880
79e57d32 881#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
6b1a3aef 882static inline unsigned rx_size(const struct sky2_port *sky2)
cd28ab6a 883{
79e57d32 884 return roundup(sky2->netdev->mtu + ETH_HLEN + 4, 8);
cd28ab6a
SH		 885}
886
887/*
888 * Allocate and setup receiver buffer pool.
889 * In case of 64 bit dma, there are 2X as many list elements
890 * available as ring entries
891 * and need to reserve one list element so we don't wrap around.
79e57d32
SH		 892 *
893 * It appears the hardware has a bug in the FIFO logic that
894 * cause it to hang if the FIFO gets overrun and the receive buffer
895 * is not aligned. This means we can't use skb_reserve to align
896 * the IP header.
cd28ab6a 897 */
6b1a3aef 898static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 899{
6b1a3aef 900 struct sky2_hw *hw = sky2->hw;
901 unsigned size = rx_size(sky2);
902 unsigned rxq = rxqaddr[sky2->port];
903 int i;
cd28ab6a 904
6b1a3aef 905 sky2->rx_put = sky2->rx_next = 0;
906 sky2_qset(hw, rxq, is_pciex(hw) ? 0x80 : 0x600);
907 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
908
909 rx_set_checksum(sky2);
793b883e 910 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 911 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 912
79e57d32 913 re->skb = dev_alloc_skb(size);
cd28ab6a
SH		 914 if (!re->skb)
915 goto nomem;
916
6b1a3aef 917 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
79e57d32
SH		 918 size, PCI_DMA_FROMDEVICE);
919 re->maplen = size;
793b883e 920 sky2_rx_add(sky2, re);
cd28ab6a
SH		 921 }
922
6b1a3aef 923 /* Tell chip about available buffers */
924 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
925 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
cd28ab6a
SH		 926 return 0;
927nomem:
928 sky2_rx_clean(sky2);
929 return -ENOMEM;
930}
931
932/* Bring up network interface. */
933static int sky2_up(struct net_device *dev)
934{
935 struct sky2_port *sky2 = netdev_priv(dev);
936 struct sky2_hw *hw = sky2->hw;
937 unsigned port = sky2->port;
938 u32 ramsize, rxspace;
939 int err = -ENOMEM;
940
941 if (netif_msg_ifup(sky2))
942 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
943
944 /* must be power of 2 */
945 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 946 TX_RING_SIZE *
947 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 948 &sky2->tx_le_map);
949 if (!sky2->tx_le)
950 goto err_out;
951
b2f5ad4f 952 sky2->tx_ring = kzalloc(TX_RING_SIZE * sizeof(struct ring_info),
cd28ab6a
SH		 953 GFP_KERNEL);
954 if (!sky2->tx_ring)
955 goto err_out;
956 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 957
958 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
959 &sky2->rx_le_map);
960 if (!sky2->rx_le)
961 goto err_out;
962 memset(sky2->rx_le, 0, RX_LE_BYTES);
963
b2f5ad4f 964 sky2->rx_ring = kzalloc(sky2->rx_pending * sizeof(struct ring_info),
cd28ab6a
SH		 965 GFP_KERNEL);
966 if (!sky2->rx_ring)
967 goto err_out;
968
969 sky2_mac_init(hw, port);
970
971 /* Configure RAM buffers */
972 if (hw->chip_id == CHIP_ID_YUKON_FE ||
973 (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2))
974 ramsize = 4096;
975 else {
793b883e
SH		 976 u8 e0 = sky2_read8(hw, B2_E_0);
977 ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096);
cd28ab6a
SH		 978 }
979
980 /* 2/3 for Rx */
981 rxspace = (2 * ramsize) / 3;
982 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
983 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
984
793b883e
SH		 985 /* Make sure SyncQ is disabled */
986 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
987 RB_RST_SET);
988
cd28ab6a 989 sky2_qset(hw, txqaddr[port], 0x600);
6b1a3aef 990 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
991 TX_RING_SIZE - 1);
cd28ab6a 992
6b1a3aef 993 err = sky2_rx_start(sky2);
cd28ab6a
SH		 994 if (err)
995 goto err_out;
996
cd28ab6a
SH		 997 /* Enable interrupts from phy/mac for port */
998 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
999 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1000 return 0;
1001
1002err_out:
1003 if (sky2->rx_le)
1004 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1005 sky2->rx_le, sky2->rx_le_map);
1006 if (sky2->tx_le)
1007 pci_free_consistent(hw->pdev,
1008 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1009 sky2->tx_le, sky2->tx_le_map);
1010 if (sky2->tx_ring)
1011 kfree(sky2->tx_ring);
1012 if (sky2->rx_ring)
1013 kfree(sky2->rx_ring);
1014
1015 return err;
1016}
1017
793b883e
SH		 1018/* Modular subtraction in ring */
1019static inline int tx_dist(unsigned tail, unsigned head)
1020{
1021 return (head >= tail ? head : head + TX_RING_SIZE) - tail;
1022}
cd28ab6a 1023
793b883e
SH		 1024/* Number of list elements available for next tx */
1025static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1026{
793b883e 1027 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1028}
1029
793b883e
SH		 1030/* Estimate of number of transmit list elements required */
1031static inline unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1032{
793b883e
SH		 1033 unsigned count;
1034
1035 count = sizeof(dma_addr_t) / sizeof(u32);
1036 count += skb_shinfo(skb)->nr_frags * count;
1037
1038 if (skb_shinfo(skb)->tso_size)
1039 ++count;
1040
1041 if (skb->ip_summed)
1042 ++count;
1043
1044 return count;
cd28ab6a
SH		 1045}
1046
793b883e
SH		 1047/*
1048 * Put one packet in ring for transmit.
1049 * A single packet can generate multiple list elements, and
1050 * the number of ring elements will probably be less than the number
1051 * of list elements used.
1052 */
cd28ab6a
SH		 1053static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1054{
1055 struct sky2_port *sky2 = netdev_priv(dev);
1056 struct sky2_hw *hw = sky2->hw;
d1f13708 1057 struct sky2_tx_le *le = NULL;
cd28ab6a 1058 struct ring_info *re;
793b883e 1059 unsigned long flags;
cd28ab6a
SH		 1060 unsigned i, len;
1061 dma_addr_t mapping;
1062 u32 addr64;
1063 u16 mss;
1064 u8 ctrl;
1065
793b883e
SH		 1066 local_irq_save(flags);
1067 if (!spin_trylock(&sky2->tx_lock)) {
1068 local_irq_restore(flags);
cd28ab6a 1069 return NETDEV_TX_LOCKED;
793b883e 1070 }
cd28ab6a 1071
793b883e 1072 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
cd28ab6a 1073 netif_stop_queue(dev);
793b883e 1074 spin_unlock_irqrestore(&sky2->tx_lock, flags);
cd28ab6a
SH		 1075
1076 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1077 dev->name);
1078 return NETDEV_TX_BUSY;
1079 }
1080
793b883e 1081 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1082 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1083 dev->name, sky2->tx_prod, skb->len);
1084
cd28ab6a
SH		 1085 len = skb_headlen(skb);
1086 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e
SH		 1087 addr64 = (mapping >> 16) >> 16;
1088
1089 re = sky2->tx_ring + sky2->tx_prod;
1090
1091 /* Send high bits if changed */
1092 if (addr64 != sky2->tx_addr64) {
1093 le = get_tx_le(sky2);
1094 le->tx.addr = cpu_to_le32(addr64);
1095 le->ctrl = 0;
1096 le->opcode = OP_ADDR64 | HW_OWNER;
1097 sky2->tx_addr64 = addr64;
1098 }
cd28ab6a
SH		 1099
1100 /* Check for TCP Segmentation Offload */
1101 mss = skb_shinfo(skb)->tso_size;
793b883e 1102 if (mss != 0) {
cd28ab6a
SH		 1103 /* just drop the packet if non-linear expansion fails */
1104 if (skb_header_cloned(skb) &&
1105 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
793b883e
SH		 1106 dev_kfree_skb_any(skb);
1107 goto out_unlock;
cd28ab6a
SH		 1108 }
1109
1110 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1111 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1112 mss += ETH_HLEN;
793b883e 1113 }
cd28ab6a 1114
793b883e 1115 if (mss != sky2->tx_last_mss) {
cd28ab6a
SH		 1116 le = get_tx_le(sky2);
1117 le->tx.tso.size = cpu_to_le16(mss);
793b883e 1118 le->tx.tso.rsvd = 0;
cd28ab6a 1119 le->opcode = OP_LRGLEN | HW_OWNER;
cd28ab6a 1120 le->ctrl = 0;
793b883e 1121 sky2->tx_last_mss = mss;
cd28ab6a
SH		 1122 }
1123
cd28ab6a 1124 ctrl = 0;
d1f13708 1125#ifdef SKY2_VLAN_TAG_USED
1126 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1127 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1128 if (!le) {
1129 le = get_tx_le(sky2);
1130 le->tx.addr = 0;
1131 le->opcode = OP_VLAN|HW_OWNER;
1132 le->ctrl = 0;
1133 } else
1134 le->opcode |= OP_VLAN;
1135 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1136 ctrl |= INS_VLAN;
1137 }
1138#endif
1139
1140 /* Handle TCP checksum offload */
cd28ab6a 1141 if (skb->ip_summed == CHECKSUM_HW) {
793b883e
SH		 1142 u16 hdr = skb->h.raw - skb->data;
1143 u16 offset = hdr + skb->csum;
cd28ab6a
SH		 1144
1145 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1146 if (skb->nh.iph->protocol == IPPROTO_UDP)
1147 ctrl |= UDPTCP;
1148
1149 le = get_tx_le(sky2);
1150 le->tx.csum.start = cpu_to_le16(hdr);
793b883e
SH		 1151 le->tx.csum.offset = cpu_to_le16(offset);
1152 le->length = 0; /* initial checksum value */
cd28ab6a 1153 le->ctrl = 1; /* one packet */
793b883e 1154 le->opcode = OP_TCPLISW | HW_OWNER;
cd28ab6a
SH		 1155 }
1156
1157 le = get_tx_le(sky2);
1158 le->tx.addr = cpu_to_le32((u32) mapping);
1159 le->length = cpu_to_le16(len);
1160 le->ctrl = ctrl;
793b883e 1161 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1162
793b883e 1163 /* Record the transmit mapping info */
cd28ab6a 1164 re->skb = skb;
793b883e
SH		 1165 re->mapaddr = mapping;
1166 re->maplen = len;
cd28ab6a
SH		 1167
1168 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1169 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
793b883e 1170 struct ring_info *fre;
cd28ab6a
SH		 1171
1172 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1173 frag->size, PCI_DMA_TODEVICE);
793b883e
SH		 1174 addr64 = (mapping >> 16) >> 16;
1175 if (addr64 != sky2->tx_addr64) {
1176 le = get_tx_le(sky2);
1177 le->tx.addr = cpu_to_le32(addr64);
1178 le->ctrl = 0;
1179 le->opcode = OP_ADDR64 | HW_OWNER;
1180 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1181 }
1182
1183 le = get_tx_le(sky2);
1184 le->tx.addr = cpu_to_le32((u32) mapping);
1185 le->length = cpu_to_le16(frag->size);
1186 le->ctrl = ctrl;
793b883e 1187 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1188
793b883e
SH		 1189 fre = sky2->tx_ring
1190 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1191 fre->skb = NULL;
1192 fre->mapaddr = mapping;
1193 fre->maplen = frag->size;
cd28ab6a 1194 }
793b883e 1195 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1196 le->ctrl |= EOP;
1197
724bca3c 1198 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
cd28ab6a
SH		 1199 &sky2->tx_last_put, TX_RING_SIZE);
1200
793b883e 1201 if (tx_avail(sky2) < MAX_SKB_TX_LE + 1)
cd28ab6a 1202 netif_stop_queue(dev);
793b883e
SH		 1203
1204out_unlock:
1205 mmiowb();
1206 spin_unlock_irqrestore(&sky2->tx_lock, flags);
cd28ab6a
SH		 1207
1208 dev->trans_start = jiffies;
1209 return NETDEV_TX_OK;
1210}
1211
cd28ab6a 1212/*
793b883e
SH		 1213 * Free ring elements from starting at tx_cons until "done"
1214 *
1215 * NB: the hardware will tell us about partial completion of multi-part
d571b694 1216 * buffers; these are deferred until completion.
cd28ab6a 1217 */
d11c13e7 1218static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1219{
d11c13e7 1220 struct net_device *dev = sky2->netdev;
793b883e 1221 unsigned i;
cd28ab6a 1222
d11c13e7 1223 if (unlikely(netif_msg_tx_done(sky2)))
d571b694 1224 printk(KERN_DEBUG "%s: tx done, up to %u\n",
d11c13e7 1225 dev->name, done);
cd28ab6a
SH		 1226
1227 spin_lock(&sky2->tx_lock);
cd28ab6a 1228
793b883e
SH		 1229 while (sky2->tx_cons != done) {
1230 struct ring_info *re = sky2->tx_ring + sky2->tx_cons;
1231 struct sk_buff *skb;
cd28ab6a 1232
793b883e
SH		 1233 /* Check for partial status */
1234 if (tx_dist(sky2->tx_cons, done)
1235 < tx_dist(sky2->tx_cons, re->idx))
1236 goto out;
1237
1238 skb = re->skb;
1239 pci_unmap_single(sky2->hw->pdev,
1240 re->mapaddr, re->maplen, PCI_DMA_TODEVICE);
1241
1242 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1243 struct ring_info *fre;
1244 fre =
1245 sky2->tx_ring + (sky2->tx_cons + i +
1246 1) % TX_RING_SIZE;
1247 pci_unmap_page(sky2->hw->pdev, fre->mapaddr,
1248 fre->maplen, PCI_DMA_TODEVICE);
cd28ab6a
SH		 1249 }
1250
cd28ab6a 1251 dev_kfree_skb_any(skb);
cd28ab6a 1252
793b883e
SH		 1253 sky2->tx_cons = re->idx;
1254 }
1255out:
1256
1257 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
cd28ab6a
SH		 1258 netif_wake_queue(dev);
1259 spin_unlock(&sky2->tx_lock);
1260}
1261
1262/* Cleanup all untransmitted buffers, assume transmitter not running */
1263static inline void sky2_tx_clean(struct sky2_port *sky2)
1264{
d11c13e7 1265 sky2_tx_complete(sky2, sky2->tx_prod);
cd28ab6a
SH		 1266}
1267
1268/* Network shutdown */
1269static int sky2_down(struct net_device *dev)
1270{
1271 struct sky2_port *sky2 = netdev_priv(dev);
1272 struct sky2_hw *hw = sky2->hw;
1273 unsigned port = sky2->port;
1274 u16 ctrl;
cd28ab6a
SH		 1275
1276 if (netif_msg_ifdown(sky2))
1277 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1278
1279 netif_stop_queue(dev);
1280
793b883e
SH		 1281 sky2_phy_reset(hw, port);
1282
cd28ab6a
SH		 1283 /* Stop transmitter */
1284 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1285 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1286
1287 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1288 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1289
1290 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1291 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1292 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1293
1294 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1295
1296 /* Workaround shared GMAC reset */
793b883e
SH		 1297 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1298 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1299 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1300
1301 /* Disable Force Sync bit and Enable Alloc bit */
1302 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1303 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1304
1305 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1306 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1307 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1308
1309 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1310 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1311 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1312
1313 /* Reset the Tx prefetch units */
1314 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1315 PREF_UNIT_RST_SET);
1316
1317 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1318
6b1a3aef 1319 sky2_rx_stop(sky2);
cd28ab6a
SH		 1320
1321 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1322 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1323
d571b694 1324 /* turn off LED's */
cd28ab6a
SH		 1325 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1326
1327 sky2_tx_clean(sky2);
1328 sky2_rx_clean(sky2);
1329
1330 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1331 sky2->rx_le, sky2->rx_le_map);
1332 kfree(sky2->rx_ring);
1333
1334 pci_free_consistent(hw->pdev,
1335 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1336 sky2->tx_le, sky2->tx_le_map);
1337 kfree(sky2->tx_ring);
1338
1339 return 0;
1340}
1341
1342static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1343{
793b883e
SH		 1344 if (!hw->copper)
1345 return SPEED_1000;
1346
cd28ab6a
SH		 1347 if (hw->chip_id == CHIP_ID_YUKON_FE)
1348 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1349
1350 switch (aux & PHY_M_PS_SPEED_MSK) {
1351 case PHY_M_PS_SPEED_1000:
1352 return SPEED_1000;
1353 case PHY_M_PS_SPEED_100:
1354 return SPEED_100;
1355 default:
1356 return SPEED_10;
1357 }
1358}
1359
1360static void sky2_link_up(struct sky2_port *sky2)
1361{
1362 struct sky2_hw *hw = sky2->hw;
1363 unsigned port = sky2->port;
1364 u16 reg;
1365
793b883e
SH		 1366 /* disable Rx GMAC FIFO flush mode */
1367 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RX_F_FL_OFF);
1368
cd28ab6a 1369 /* Enable Transmit FIFO Underrun */
793b883e 1370 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
cd28ab6a
SH		 1371
1372 reg = gma_read16(hw, port, GM_GP_CTRL);
1373 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1374 reg |= GM_GPCR_DUP_FULL;
1375
cd28ab6a
SH		 1376 /* enable Rx/Tx */
1377 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1378 gma_write16(hw, port, GM_GP_CTRL, reg);
1379 gma_read16(hw, port, GM_GP_CTRL);
1380
1381 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1382
1383 netif_carrier_on(sky2->netdev);
1384 netif_wake_queue(sky2->netdev);
1385
1386 /* Turn on link LED */
793b883e 1387 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1388 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1389
793b883e
SH		 1390 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1391 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1392
1393 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1394 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1395 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1396 SPEED_10 ? 7 : 0) |
1397 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1398 SPEED_100 ? 7 : 0) |
1399 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1400 SPEED_1000 ? 7 : 0));
1401 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1402 }
1403
cd28ab6a
SH		 1404 if (netif_msg_link(sky2))
1405 printk(KERN_INFO PFX
d571b694 1406 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1407 sky2->netdev->name, sky2->speed,
1408 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1409 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1410 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1411}
1412
1413static void sky2_link_down(struct sky2_port *sky2)
1414{
1415 struct sky2_hw *hw = sky2->hw;
1416 unsigned port = sky2->port;
1417 u16 reg;
1418
1419 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1420
1421 reg = gma_read16(hw, port, GM_GP_CTRL);
1422 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1423 gma_write16(hw, port, GM_GP_CTRL, reg);
1424 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1425
1426 if (sky2->rx_pause && !sky2->tx_pause) {
1427 /* restore Asymmetric Pause bit */
1428 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1429 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1430 | PHY_M_AN_ASP);
cd28ab6a
SH		 1431 }
1432
1433 sky2_phy_reset(hw, port);
1434
1435 netif_carrier_off(sky2->netdev);
1436 netif_stop_queue(sky2->netdev);
1437
1438 /* Turn on link LED */
1439 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1440
1441 if (netif_msg_link(sky2))
1442 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1443 sky2_phy_init(hw, port);
1444}
1445
793b883e
SH		 1446static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1447{
1448 struct sky2_hw *hw = sky2->hw;
1449 unsigned port = sky2->port;
1450 u16 lpa;
1451
1452 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1453
1454 if (lpa & PHY_M_AN_RF) {
1455 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1456 return -1;
1457 }
1458
1459 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1460 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1461 printk(KERN_ERR PFX "%s: master/slave fault",
1462 sky2->netdev->name);
1463 return -1;
1464 }
1465
1466 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1467 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1468 sky2->netdev->name);
1469 return -1;
1470 }
1471
1472 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1473
1474 sky2->speed = sky2_phy_speed(hw, aux);
1475
1476 /* Pause bits are offset (9..8) */
1477 if (hw->chip_id == CHIP_ID_YUKON_XL)
1478 aux >>= 6;
1479
1480 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1481 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1482
1483 if ((sky2->tx_pause || sky2->rx_pause)
1484 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1485 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1486 else
1487 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1488
1489 return 0;
1490}
cd28ab6a
SH		 1491
1492/*
d571b694 1493 * Interrupt from PHY are handled in tasklet (soft irq)
cd28ab6a
SH		 1494 * because accessing phy registers requires spin wait which might
1495 * cause excess interrupt latency.
1496 */
1497static void sky2_phy_task(unsigned long data)
1498{
793b883e 1499 struct sky2_port *sky2 = (struct sky2_port *)data;
cd28ab6a 1500 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1501 u16 istatus, phystat;
1502
793b883e
SH		 1503 spin_lock(&hw->phy_lock);
1504 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1505 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
cd28ab6a
SH		 1506
1507 if (netif_msg_intr(sky2))
1508 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1509 sky2->netdev->name, istatus, phystat);
1510
1511 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 1512 if (sky2_autoneg_done(sky2, phystat) == 0)
1513 sky2_link_up(sky2);
1514 goto out;
1515 }
cd28ab6a 1516
793b883e
SH		 1517 if (istatus & PHY_M_IS_LSP_CHANGE)
1518 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1519
793b883e
SH		 1520 if (istatus & PHY_M_IS_DUP_CHANGE)
1521 sky2->duplex =
1522 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1523
793b883e
SH		 1524 if (istatus & PHY_M_IS_LST_CHANGE) {
1525 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1526 sky2_link_up(sky2);
793b883e
SH		 1527 else
1528 sky2_link_down(sky2);
cd28ab6a 1529 }
793b883e
SH		 1530out:
1531 spin_unlock(&hw->phy_lock);
cd28ab6a
SH		 1532
1533 local_irq_disable();
793b883e 1534 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
cd28ab6a
SH		 1535 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1536 local_irq_enable();
1537}
1538
1539static void sky2_tx_timeout(struct net_device *dev)
1540{
1541 struct sky2_port *sky2 = netdev_priv(dev);
1542
1543 if (netif_msg_timer(sky2))
1544 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1545
1546 sky2_write32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR), BMU_STOP);
1547 sky2_read32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR));
1548
1549 sky2_tx_clean(sky2);
1550}
1551
1552static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1553{
6b1a3aef 1554 struct sky2_port *sky2 = netdev_priv(dev);
1555 struct sky2_hw *hw = sky2->hw;
1556 int err;
1557 u16 ctl, mode;
cd28ab6a
SH		 1558
1559 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1560 return -EINVAL;
1561
6b1a3aef 1562 if (!netif_running(dev)) {
1563 dev->mtu = new_mtu;
1564 return 0;
1565 }
1566
1567 local_irq_disable();
1568 sky2_write32(hw, B0_IMSK, 0);
1569
1570 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1571 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1572 sky2_rx_stop(sky2);
1573 sky2_rx_clean(sky2);
cd28ab6a
SH		 1574
1575 dev->mtu = new_mtu;
6b1a3aef 1576 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1577 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1578
1579 if (dev->mtu > ETH_DATA_LEN)
1580 mode |= GM_SMOD_JUMBO_ENA;
1581
1582 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1583
6b1a3aef 1584 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1585
6b1a3aef 1586 err = sky2_rx_start(sky2);
1587 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1588
1589 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1590 sky2_read32(hw, B0_IMSK);
1591 local_irq_enable();
cd28ab6a
SH		 1592 return err;
1593}
1594
1595/*
1596 * Receive one packet.
1597 * For small packets or errors, just reuse existing skb.
d571b694 1598 * For larger packets, get new buffer.
cd28ab6a 1599 */
d11c13e7 1600static struct sk_buff *sky2_receive(struct sky2_port *sky2,
cd28ab6a
SH		 1601 u16 length, u32 status)
1602{
cd28ab6a 1603 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1604 struct sk_buff *skb = NULL;
d11c13e7 1605 struct net_device *dev;
6b1a3aef 1606 const unsigned int bufsize = rx_size(sky2);
cd28ab6a
SH		 1607
1608 if (unlikely(netif_msg_rx_status(sky2)))
1609 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
d11c13e7 1610 sky2->netdev->name, sky2->rx_next, status, length);
cd28ab6a 1611
793b883e 1612 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
cd28ab6a 1613
d1f13708 1614 if (!(status & GMR_FS_RX_OK) || (status & GMR_FS_ANY_ERR))
cd28ab6a
SH		 1615 goto error;
1616
793b883e 1617 if (length < RX_COPY_THRESHOLD) {
79e57d32
SH		 1618 skb = alloc_skb(length + 2, GFP_ATOMIC);
1619 if (!skb)
793b883e
SH		 1620 goto resubmit;
1621
79e57d32 1622 skb_reserve(skb, 2);
793b883e
SH		 1623 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1624 length, PCI_DMA_FROMDEVICE);
79e57d32 1625 memcpy(skb->data, re->skb->data, length);
d11c13e7 1626 skb->ip_summed = re->skb->ip_summed;
1627 skb->csum = re->skb->csum;
793b883e
SH		 1628 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1629 length, PCI_DMA_FROMDEVICE);
793b883e 1630 } else {
79e57d32
SH		 1631 struct sk_buff *nskb;
1632
1633 nskb = dev_alloc_skb(bufsize);
793b883e
SH		 1634 if (!nskb)
1635 goto resubmit;
cd28ab6a 1636
793b883e 1637 skb = re->skb;
79e57d32 1638 re->skb = nskb;
793b883e
SH		 1639 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1640 re->maplen, PCI_DMA_FROMDEVICE);
1641 prefetch(skb->data);
cd28ab6a 1642
793b883e 1643 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
79e57d32
SH		 1644 bufsize, PCI_DMA_FROMDEVICE);
1645 re->maplen = bufsize;
793b883e 1646 }
cd28ab6a 1647
79e57d32 1648 skb_put(skb, length);
d11c13e7 1649 dev = sky2->netdev;
1650 skb->dev = dev;
79e57d32
SH		 1651 skb->protocol = eth_type_trans(skb, dev);
1652 dev->last_rx = jiffies;
1653
793b883e 1654resubmit:
d11c13e7 1655 re->skb->ip_summed = CHECKSUM_NONE;
793b883e 1656 sky2_rx_add(sky2, re);
79e57d32 1657
bea86103 1658 /* Tell receiver about new buffers. */
1659 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1660 &sky2->rx_last_put, RX_LE_SIZE);
1661
cd28ab6a
SH		 1662 return skb;
1663
1664error:
793b883e
SH		 1665 if (status & GMR_FS_GOOD_FC)
1666 goto resubmit;
1667
cd28ab6a
SH		 1668 if (netif_msg_rx_err(sky2))
1669 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1670 sky2->netdev->name, status, length);
793b883e
SH		 1671
1672 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1673 sky2->net_stats.rx_length_errors++;
1674 if (status & GMR_FS_FRAGMENT)
1675 sky2->net_stats.rx_frame_errors++;
1676 if (status & GMR_FS_CRC_ERR)
1677 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1678 if (status & GMR_FS_RX_FF_OV)
1679 sky2->net_stats.rx_fifo_errors++;
79e57d32 1680
793b883e 1681 goto resubmit;
cd28ab6a
SH		 1682}
1683
793b883e
SH		 1684/* Transmit ring index in reported status block is encoded as:
1685 *
1686 * | TXS2 | TXA2 | TXS1 | TXA1
1687 */
1688static inline u16 tx_index(u8 port, u32 status, u16 len)
cd28ab6a
SH		 1689{
1690 if (port == 0)
1691 return status & 0xfff;
1692 else
1693 return ((status >> 24) & 0xff) | (len & 0xf) << 8;
1694}
1695
1696/*
cd28ab6a
SH		 1697 * Both ports share the same status interrupt, therefore there is only
1698 * one poll routine.
cd28ab6a 1699 */
d11c13e7 1700static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 1701{
d11c13e7 1702 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1703 unsigned int to_do = min(dev0->quota, *budget);
cd28ab6a 1704 unsigned int work_done = 0;
793b883e 1705 u16 hwidx;
cd28ab6a 1706
793b883e 1707 hwidx = sky2_read16(hw, STAT_PUT_IDX);
79e57d32 1708 BUG_ON(hwidx >= STATUS_RING_SIZE);
793b883e 1709 rmb();
bea86103 1710
1711 do {
cd28ab6a 1712 struct sky2_status_le *le = hw->st_le + hw->st_idx;
d11c13e7 1713 struct sky2_port *sky2;
cd28ab6a 1714 struct sk_buff *skb;
cd28ab6a
SH		 1715 u32 status;
1716 u16 length;
1717
bea86103 1718 /* Are we done yet? */
1719 if (hw->st_idx == hwidx) {
1720 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1721 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1722 if (hwidx == hw->st_idx)
1723 break;
1724 }
1725
1726 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1727 prefetch(&hw->st_le[hw->st_idx]);
1728
1729 BUG_ON(le->link >= hw->ports || !hw->dev[le->link]);
d1f13708 1730
d11c13e7 1731 sky2 = netdev_priv(hw->dev[le->link]);
cd28ab6a
SH		 1732 status = le32_to_cpu(le->status);
1733 length = le16_to_cpu(le->length);
cd28ab6a 1734
793b883e 1735 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 1736 case OP_RXSTAT:
d11c13e7 1737 skb = sky2_receive(sky2, length, status);
d1f13708 1738 if (!skb)
1739 break;
1740#ifdef SKY2_VLAN_TAG_USED
1741 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1742 vlan_hwaccel_receive_skb(skb,
1743 sky2->vlgrp,
1744 be16_to_cpu(sky2->rx_tag));
1745 } else
1746#endif
cd28ab6a 1747 netif_receive_skb(skb);
bea86103 1748 ++work_done;
cd28ab6a
SH		 1749 break;
1750
d1f13708 1751#ifdef SKY2_VLAN_TAG_USED
1752 case OP_RXVLAN:
1753 sky2->rx_tag = length;
1754 break;
1755
1756 case OP_RXCHKSVLAN:
1757 sky2->rx_tag = length;
1758 /* fall through */
1759#endif
cd28ab6a 1760 case OP_RXCHKS:
d11c13e7 1761 skb = sky2->rx_ring[sky2->rx_next].skb;
1762 skb->ip_summed = CHECKSUM_HW;
1763 skb->csum = le16_to_cpu(status);
cd28ab6a
SH		 1764 break;
1765
1766 case OP_TXINDEXLE:
d11c13e7 1767 sky2_tx_complete(sky2,
1768 tx_index(sky2->port, status, length));
cd28ab6a
SH		 1769 break;
1770
cd28ab6a
SH		 1771 default:
1772 if (net_ratelimit())
793b883e
SH		 1773 printk(KERN_WARNING PFX
1774 "unknown status opcode 0x%x\n",
cd28ab6a
SH		 1775 le->opcode);
1776 break;
1777 }
1778
bea86103 1779 le->opcode = 0; /* paranoia */
1780 } while (work_done < to_do);
cd28ab6a 1781
793b883e
SH		 1782 mmiowb();
1783
cd28ab6a 1784 *budget -= work_done;
d11c13e7 1785 dev0->quota -= work_done;
cd28ab6a
SH		 1786 if (work_done < to_do) {
1787 /*
1788 * Another chip workaround, need to restart TX timer if status
1789 * LE was handled. WA_DEV_43_418
1790 */
1791 if (is_ec_a1(hw)) {
1792 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1793 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1794 }
1795
bea86103 1796 netif_rx_complete(dev0);
cd28ab6a
SH		 1797 hw->intr_mask |= Y2_IS_STAT_BMU;
1798 sky2_write32(hw, B0_IMSK, hw->intr_mask);
793b883e 1799 sky2_read32(hw, B0_IMSK);
cd28ab6a
SH		 1800 }
1801
1802 return work_done >= to_do;
1803
1804}
1805
1806static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1807{
1808 struct net_device *dev = hw->dev[port];
1809
1810 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1811 dev->name, status);
1812
1813 if (status & Y2_IS_PAR_RD1) {
1814 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1815 dev->name);
1816 /* Clear IRQ */
1817 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1818 }
1819
1820 if (status & Y2_IS_PAR_WR1) {
1821 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1822 dev->name);
1823
1824 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1825 }
1826
1827 if (status & Y2_IS_PAR_MAC1) {
1828 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1829 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1830 }
1831
1832 if (status & Y2_IS_PAR_RX1) {
1833 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1834 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1835 }
1836
1837 if (status & Y2_IS_TCP_TXA1) {
1838 printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
1839 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1840 }
1841}
1842
1843static void sky2_hw_intr(struct sky2_hw *hw)
1844{
1845 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1846
793b883e 1847 if (status & Y2_IS_TIST_OV)
cd28ab6a 1848 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 1849
1850 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 1851 u16 pci_err;
1852
1853 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
cd28ab6a
SH		 1854 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1855 pci_name(hw->pdev), pci_err);
1856
1857 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 1858 pci_write_config_word(hw->pdev, PCI_STATUS,
1859 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 1860 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1861 }
1862
1863 if (status & Y2_IS_PCI_EXP) {
d571b694 1864 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 1865 u32 pex_err;
1866
1867 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
cd28ab6a 1868
cd28ab6a
SH		 1869 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
1870 pci_name(hw->pdev), pex_err);
1871
1872 /* clear the interrupt */
1873 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 1874 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1875 0xffffffffUL);
cd28ab6a
SH		 1876 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1877
1878 if (pex_err & PEX_FATAL_ERRORS) {
1879 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
1880 hwmsk &= ~Y2_IS_PCI_EXP;
1881 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
1882 }
1883 }
1884
1885 if (status & Y2_HWE_L1_MASK)
1886 sky2_hw_error(hw, 0, status);
1887 status >>= 8;
1888 if (status & Y2_HWE_L1_MASK)
1889 sky2_hw_error(hw, 1, status);
1890}
1891
1892static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
1893{
1894 struct net_device *dev = hw->dev[port];
1895 struct sky2_port *sky2 = netdev_priv(dev);
1896 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1897
1898 if (netif_msg_intr(sky2))
1899 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
1900 dev->name, status);
1901
1902 if (status & GM_IS_RX_FF_OR) {
1903 ++sky2->net_stats.rx_fifo_errors;
1904 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1905 }
1906
1907 if (status & GM_IS_TX_FF_UR) {
1908 ++sky2->net_stats.tx_fifo_errors;
1909 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1910 }
cd28ab6a
SH		 1911}
1912
1913static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1914{
1915 struct net_device *dev = hw->dev[port];
1916 struct sky2_port *sky2 = netdev_priv(dev);
1917
1918 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1919 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1920 tasklet_schedule(&sky2->phy_task);
1921}
1922
1923static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
1924{
1925 struct sky2_hw *hw = dev_id;
bea86103 1926 struct net_device *dev0 = hw->dev[0];
cd28ab6a
SH		 1927 u32 status;
1928
1929 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
793b883e 1930 if (status == 0 || status == ~0)
cd28ab6a
SH		 1931 return IRQ_NONE;
1932
1933 if (status & Y2_IS_HW_ERR)
1934 sky2_hw_intr(hw);
1935
793b883e 1936 /* Do NAPI for Rx and Tx status */
bea86103 1937 if (status & Y2_IS_STAT_BMU) {
cd28ab6a
SH		 1938 hw->intr_mask &= ~Y2_IS_STAT_BMU;
1939 sky2_write32(hw, B0_IMSK, hw->intr_mask);
bea86103 1940 prefetch(&hw->st_le[hw->st_idx]);
1941
1942 if (netif_rx_schedule_test(dev0))
1943 __netif_rx_schedule(dev0);
cd28ab6a
SH		 1944 }
1945
793b883e 1946 if (status & Y2_IS_IRQ_PHY1)
cd28ab6a
SH		 1947 sky2_phy_intr(hw, 0);
1948
1949 if (status & Y2_IS_IRQ_PHY2)
1950 sky2_phy_intr(hw, 1);
1951
1952 if (status & Y2_IS_IRQ_MAC1)
1953 sky2_mac_intr(hw, 0);
1954
1955 if (status & Y2_IS_IRQ_MAC2)
1956 sky2_mac_intr(hw, 1);
1957
cd28ab6a 1958 sky2_write32(hw, B0_Y2_SP_ICR, 2);
793b883e
SH		 1959
1960 sky2_read32(hw, B0_IMSK);
1961
cd28ab6a
SH		 1962 return IRQ_HANDLED;
1963}
1964
1965#ifdef CONFIG_NET_POLL_CONTROLLER
1966static void sky2_netpoll(struct net_device *dev)
1967{
1968 struct sky2_port *sky2 = netdev_priv(dev);
1969
793b883e 1970 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
cd28ab6a
SH		 1971}
1972#endif
1973
1974/* Chip internal frequency for clock calculations */
1975static inline u32 sky2_khz(const struct sky2_hw *hw)
1976{
793b883e 1977 switch (hw->chip_id) {
cd28ab6a
SH		 1978 case CHIP_ID_YUKON_EC:
1979 return 125000; /* 125 Mhz */
1980 case CHIP_ID_YUKON_FE:
1981 return 100000; /* 100 Mhz */
793b883e 1982 default: /* YUKON_XL */
cd28ab6a
SH		 1983 return 156000; /* 156 Mhz */
1984 }
1985}
1986
1987static inline u32 sky2_ms2clk(const struct sky2_hw *hw, u32 ms)
1988{
1989 return sky2_khz(hw) * ms;
1990}
1991
1992static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
1993{
793b883e 1994 return (sky2_khz(hw) * us) / 1000;
cd28ab6a
SH		 1995}
1996
1997static int sky2_reset(struct sky2_hw *hw)
1998{
5afa0a9c 1999 u32 ctst;
cd28ab6a
SH		 2000 u16 status;
2001 u8 t8, pmd_type;
2002 int i;
2003
2004 ctst = sky2_read32(hw, B0_CTST);
2005
2006 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2007 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2008 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2009 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2010 pci_name(hw->pdev), hw->chip_id);
2011 return -EOPNOTSUPP;
2012 }
2013
793b883e
SH		 2014 /* ring for status responses */
2015 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
2016 &hw->st_dma);
2017 if (!hw->st_le)
2018 return -ENOMEM;
2019
cd28ab6a
SH		 2020 /* disable ASF */
2021 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2022 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2023 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2024 }
2025
2026 /* do a SW reset */
2027 sky2_write8(hw, B0_CTST, CS_RST_SET);
2028 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2029
2030 /* clear PCI errors, if any */
793b883e 2031 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
cd28ab6a 2032 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 2033 pci_write_config_word(hw->pdev, PCI_STATUS,
2034 status | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2035
2036 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2037
2038 /* clear any PEX errors */
2039 if (is_pciex(hw)) {
793b883e
SH		 2040 u16 lstat;
2041 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2042 0xffffffffUL);
2043 pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
cd28ab6a
SH		 2044 }
2045
2046 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2047 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2048
2049 hw->ports = 1;
2050 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2051 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2052 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2053 ++hw->ports;
2054 }
2055 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2056
5afa0a9c 2057 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2058
2059 for (i = 0; i < hw->ports; i++) {
2060 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2061 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2062 }
2063
2064 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2065
793b883e
SH		 2066 /* Clear I2C IRQ noise */
2067 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2068
2069 /* turn off hardware timer (unused) */
2070 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2071 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2072
cd28ab6a
SH		 2073 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2074
793b883e 2075 /* Turn on descriptor polling (every 75us) */
cd28ab6a
SH		 2076 sky2_write32(hw, B28_DPT_INI, sky2_us2clk(hw, 75));
2077 sky2_write8(hw, B28_DPT_CTRL, DPT_START);
2078
2079 /* Turn off receive timestamp */
2080 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2081 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2082
2083 /* enable the Tx Arbiters */
2084 for (i = 0; i < hw->ports; i++)
2085 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2086
2087 /* Initialize ram interface */
2088 for (i = 0; i < hw->ports; i++) {
793b883e 2089 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2090
2091 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2092 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2093 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2094 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2095 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2096 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2097 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2098 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2099 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2100 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2101 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2102 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2103 }
2104
cd28ab6a 2105 if (is_pciex(hw)) {
793b883e
SH		 2106 u16 pctrl;
2107
2108 /* change Max. Read Request Size to 2048 bytes */
2109 pci_read_config_word(hw->pdev, PEX_DEV_CTRL, &pctrl);
2110 pctrl &= ~PEX_DC_MAX_RRS_MSK;
2111 pctrl |= PEX_DC_MAX_RD_RQ_SIZE(4);
2112
2113
cd28ab6a 2114 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e 2115 pci_write_config_word(hw->pdev, PEX_DEV_CTRL, pctrl);
cd28ab6a
SH		 2116 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2117 }
2118
2119 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2120
cd28ab6a
SH		 2121 spin_lock_bh(&hw->phy_lock);
2122 for (i = 0; i < hw->ports; i++)
2123 sky2_phy_reset(hw, i);
2124 spin_unlock_bh(&hw->phy_lock);
2125
cd28ab6a
SH		 2126 memset(hw->st_le, 0, STATUS_LE_BYTES);
2127 hw->st_idx = 0;
2128
2129 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2130 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2131
2132 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2133 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2134
2135 /* Set the list last index */
793b883e 2136 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2137
793b883e
SH		 2138 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_ms2clk(hw, 10));
2139
2140 /* These status setup values are copied from SysKonnect's driver */
cd28ab6a
SH		 2141 if (is_ec_a1(hw)) {
2142 /* WA for dev. #4.3 */
793b883e 2143 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
cd28ab6a
SH		 2144
2145 /* set Status-FIFO watermark */
2146 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2147
2148 /* set Status-FIFO ISR watermark */
793b883e 2149 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
cd28ab6a 2150
cd28ab6a 2151 } else {
cd28ab6a
SH		 2152 sky2_write16(hw, STAT_TX_IDX_TH, 0x000a);
2153
2154 /* set Status-FIFO watermark */
2155 sky2_write8(hw, STAT_FIFO_WM, 0x10);
2156
2157 /* set Status-FIFO ISR watermark */
2158 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2159 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10);
2160
d571b694 2161 else /* WA dev 4.109 */
cd28ab6a
SH		 2162 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04);
2163
2164 sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190);
2165 }
2166
793b883e 2167 /* enable status unit */
cd28ab6a
SH		 2168 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2169
2170 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2171 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2172 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2173
2174 return 0;
2175}
2176
2177static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
2178{
2179 u32 modes;
2180 if (hw->copper) {
793b883e
SH		 2181 modes = SUPPORTED_10baseT_Half
2182 | SUPPORTED_10baseT_Full
2183 | SUPPORTED_100baseT_Half
2184 | SUPPORTED_100baseT_Full
2185 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2186
2187 if (hw->chip_id != CHIP_ID_YUKON_FE)
2188 modes |= SUPPORTED_1000baseT_Half
793b883e 2189 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 2190 } else
2191 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
793b883e 2192 | SUPPORTED_Autoneg;
cd28ab6a
SH		 2193 return modes;
2194}
2195
793b883e 2196static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2197{
2198 struct sky2_port *sky2 = netdev_priv(dev);
2199 struct sky2_hw *hw = sky2->hw;
2200
2201 ecmd->transceiver = XCVR_INTERNAL;
2202 ecmd->supported = sky2_supported_modes(hw);
2203 ecmd->phy_address = PHY_ADDR_MARV;
2204 if (hw->copper) {
2205 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2206 | SUPPORTED_10baseT_Full
2207 | SUPPORTED_100baseT_Half
2208 | SUPPORTED_100baseT_Full
2209 | SUPPORTED_1000baseT_Half
2210 | SUPPORTED_1000baseT_Full
2211 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2212 ecmd->port = PORT_TP;
2213 } else
2214 ecmd->port = PORT_FIBRE;
2215
2216 ecmd->advertising = sky2->advertising;
2217 ecmd->autoneg = sky2->autoneg;
2218 ecmd->speed = sky2->speed;
2219 ecmd->duplex = sky2->duplex;
2220 return 0;
2221}
2222
2223static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2224{
2225 struct sky2_port *sky2 = netdev_priv(dev);
2226 const struct sky2_hw *hw = sky2->hw;
2227 u32 supported = sky2_supported_modes(hw);
2228
2229 if (ecmd->autoneg == AUTONEG_ENABLE) {
2230 ecmd->advertising = supported;
2231 sky2->duplex = -1;
2232 sky2->speed = -1;
2233 } else {
2234 u32 setting;
2235
793b883e 2236 switch (ecmd->speed) {
cd28ab6a
SH		 2237 case SPEED_1000:
2238 if (ecmd->duplex == DUPLEX_FULL)
2239 setting = SUPPORTED_1000baseT_Full;
2240 else if (ecmd->duplex == DUPLEX_HALF)
2241 setting = SUPPORTED_1000baseT_Half;
2242 else
2243 return -EINVAL;
2244 break;
2245 case SPEED_100:
2246 if (ecmd->duplex == DUPLEX_FULL)
2247 setting = SUPPORTED_100baseT_Full;
2248 else if (ecmd->duplex == DUPLEX_HALF)
2249 setting = SUPPORTED_100baseT_Half;
2250 else
2251 return -EINVAL;
2252 break;
2253
2254 case SPEED_10:
2255 if (ecmd->duplex == DUPLEX_FULL)
2256 setting = SUPPORTED_10baseT_Full;
2257 else if (ecmd->duplex == DUPLEX_HALF)
2258 setting = SUPPORTED_10baseT_Half;
2259 else
2260 return -EINVAL;
2261 break;
2262 default:
2263 return -EINVAL;
2264 }
2265
2266 if ((setting & supported) == 0)
2267 return -EINVAL;
2268
2269 sky2->speed = ecmd->speed;
2270 sky2->duplex = ecmd->duplex;
2271 }
2272
2273 sky2->autoneg = ecmd->autoneg;
2274 sky2->advertising = ecmd->advertising;
2275
2276 if (netif_running(dev)) {
2277 sky2_down(dev);
2278 sky2_up(dev);
2279 }
2280
2281 return 0;
2282}
2283
2284static void sky2_get_drvinfo(struct net_device *dev,
2285 struct ethtool_drvinfo *info)
2286{
2287 struct sky2_port *sky2 = netdev_priv(dev);
2288
2289 strcpy(info->driver, DRV_NAME);
2290 strcpy(info->version, DRV_VERSION);
2291 strcpy(info->fw_version, "N/A");
2292 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2293}
2294
2295static const struct sky2_stat {
793b883e
SH		 2296 char name[ETH_GSTRING_LEN];
2297 u16 offset;
cd28ab6a
SH		 2298} sky2_stats[] = {
2299 { "tx_bytes", GM_TXO_OK_HI },
2300 { "rx_bytes", GM_RXO_OK_HI },
2301 { "tx_broadcast", GM_TXF_BC_OK },
2302 { "rx_broadcast", GM_RXF_BC_OK },
2303 { "tx_multicast", GM_TXF_MC_OK },
2304 { "rx_multicast", GM_RXF_MC_OK },
2305 { "tx_unicast", GM_TXF_UC_OK },
2306 { "rx_unicast", GM_RXF_UC_OK },
2307 { "tx_mac_pause", GM_TXF_MPAUSE },
2308 { "rx_mac_pause", GM_RXF_MPAUSE },
2309 { "collisions", GM_TXF_SNG_COL },
2310 { "late_collision",GM_TXF_LAT_COL },
2311 { "aborted", GM_TXF_ABO_COL },
2312 { "multi_collisions", GM_TXF_MUL_COL },
2313 { "fifo_underrun", GM_TXE_FIFO_UR },
2314 { "fifo_overflow", GM_RXE_FIFO_OV },
2315 { "rx_toolong", GM_RXF_LNG_ERR },
2316 { "rx_jabber", GM_RXF_JAB_PKT },
2317 { "rx_runt", GM_RXE_FRAG },
2318 { "rx_too_long", GM_RXF_LNG_ERR },
2319 { "rx_fcs_error", GM_RXF_FCS_ERR },
2320};
2321
cd28ab6a
SH		 2322static u32 sky2_get_rx_csum(struct net_device *dev)
2323{
2324 struct sky2_port *sky2 = netdev_priv(dev);
2325
2326 return sky2->rx_csum;
2327}
2328
2329static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2330{
2331 struct sky2_port *sky2 = netdev_priv(dev);
2332
2333 sky2->rx_csum = data;
793b883e 2334
cd28ab6a
SH		 2335 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2336 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2337
2338 return 0;
2339}
2340
2341static u32 sky2_get_msglevel(struct net_device *netdev)
2342{
2343 struct sky2_port *sky2 = netdev_priv(netdev);
2344 return sky2->msg_enable;
2345}
2346
9a7ae0a9
SH		 2347static int sky2_nway_reset(struct net_device *dev)
2348{
2349 struct sky2_port *sky2 = netdev_priv(dev);
2350 struct sky2_hw *hw = sky2->hw;
2351
2352 if (sky2->autoneg != AUTONEG_ENABLE)
2353 return -EINVAL;
2354
2355 netif_stop_queue(dev);
2356
2357 spin_lock_irq(&hw->phy_lock);
2358 sky2_phy_reset(hw, sky2->port);
2359 sky2_phy_init(hw, sky2->port);
2360 spin_unlock_irq(&hw->phy_lock);
2361
2362 return 0;
2363}
2364
793b883e 2365static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2366{
2367 struct sky2_hw *hw = sky2->hw;
2368 unsigned port = sky2->port;
2369 int i;
2370
2371 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2372 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2373 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2374 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2375
793b883e 2376 for (i = 2; i < count; i++)
cd28ab6a
SH		 2377 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2378}
2379
cd28ab6a
SH		 2380static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2381{
2382 struct sky2_port *sky2 = netdev_priv(netdev);
2383 sky2->msg_enable = value;
2384}
2385
2386static int sky2_get_stats_count(struct net_device *dev)
2387{
2388 return ARRAY_SIZE(sky2_stats);
2389}
2390
2391static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2392 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2393{
2394 struct sky2_port *sky2 = netdev_priv(dev);
2395
793b883e 2396 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2397}
2398
793b883e 2399static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2400{
2401 int i;
2402
2403 switch (stringset) {
2404 case ETH_SS_STATS:
2405 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2406 memcpy(data + i * ETH_GSTRING_LEN,
2407 sky2_stats[i].name, ETH_GSTRING_LEN);
2408 break;
2409 }
2410}
2411
2412/* Use hardware MIB variables for critical path statistics and
2413 * transmit feedback not reported at interrupt.
2414 * Other errors are accounted for in interrupt handler.
2415 */
2416static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2417{
2418 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2419 u64 data[13];
cd28ab6a 2420
793b883e 2421 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2422
2423 sky2->net_stats.tx_bytes = data[0];
2424 sky2->net_stats.rx_bytes = data[1];
2425 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2426 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2427 sky2->net_stats.multicast = data[5] + data[7];
2428 sky2->net_stats.collisions = data[10];
2429 sky2->net_stats.tx_aborted_errors = data[12];
2430
2431 return &sky2->net_stats;
2432}
2433
2434static int sky2_set_mac_address(struct net_device *dev, void *p)
2435{
2436 struct sky2_port *sky2 = netdev_priv(dev);
2437 struct sockaddr *addr = p;
2438 int err = 0;
2439
2440 if (!is_valid_ether_addr(addr->sa_data))
2441 return -EADDRNOTAVAIL;
2442
2443 sky2_down(dev);
2444 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
793b883e 2445 memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
cd28ab6a 2446 dev->dev_addr, ETH_ALEN);
793b883e 2447 memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
cd28ab6a
SH		 2448 dev->dev_addr, ETH_ALEN);
2449 if (dev->flags & IFF_UP)
2450 err = sky2_up(dev);
2451 return err;
2452}
2453
2454static void sky2_set_multicast(struct net_device *dev)
2455{
2456 struct sky2_port *sky2 = netdev_priv(dev);
2457 struct sky2_hw *hw = sky2->hw;
2458 unsigned port = sky2->port;
2459 struct dev_mc_list *list = dev->mc_list;
2460 u16 reg;
2461 u8 filter[8];
2462
2463 memset(filter, 0, sizeof(filter));
2464
2465 reg = gma_read16(hw, port, GM_RX_CTRL);
2466 reg |= GM_RXCR_UCF_ENA;
2467
d571b694 2468 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2469 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2470 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2471 memset(filter, 0xff, sizeof(filter));
793b883e 2472 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2473 reg &= ~GM_RXCR_MCF_ENA;
2474 else {
2475 int i;
2476 reg |= GM_RXCR_MCF_ENA;
2477
2478 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2479 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2480 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2481 }
2482 }
2483
cd28ab6a 2484 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2485 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2486 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2487 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2488 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2489 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2490 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2491 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2492
2493 gma_write16(hw, port, GM_RX_CTRL, reg);
2494}
2495
2496/* Can have one global because blinking is controlled by
2497 * ethtool and that is always under RTNL mutex
2498 */
2499static inline void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2500{
793b883e
SH		 2501 u16 pg;
2502
cd28ab6a 2503 spin_lock_bh(&hw->phy_lock);
793b883e
SH		 2504 switch (hw->chip_id) {
2505 case CHIP_ID_YUKON_XL:
2506 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2507 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2508 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2509 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2510 PHY_M_LEDC_INIT_CTRL(7) |
2511 PHY_M_LEDC_STA1_CTRL(7) |
2512 PHY_M_LEDC_STA0_CTRL(7))
2513 : 0);
2514
2515 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2516 break;
2517
2518 default:
2519 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2520 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2521 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2522 PHY_M_LED_MO_10(MO_LED_ON) |
2523 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2524 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2525 PHY_M_LED_MO_RX(MO_LED_ON)
2526 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2527 PHY_M_LED_MO_10(MO_LED_OFF) |
2528 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2529 PHY_M_LED_MO_1000(MO_LED_OFF) |
2530 PHY_M_LED_MO_RX(MO_LED_OFF));
2531
793b883e 2532 }
cd28ab6a
SH		 2533 spin_unlock_bh(&hw->phy_lock);
2534}
2535
2536/* blink LED's for finding board */
2537static int sky2_phys_id(struct net_device *dev, u32 data)
2538{
2539 struct sky2_port *sky2 = netdev_priv(dev);
2540 struct sky2_hw *hw = sky2->hw;
2541 unsigned port = sky2->port;
793b883e 2542 u16 ledctrl, ledover = 0;
cd28ab6a
SH		 2543 long ms;
2544 int onoff = 1;
2545
793b883e 2546 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2547 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2548 else
2549 ms = data * 1000;
2550
2551 /* save initial values */
2552 spin_lock_bh(&hw->phy_lock);
793b883e
SH		 2553 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2554 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2555 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2556 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2557 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2558 } else {
2559 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2560 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2561 }
cd28ab6a
SH		 2562 spin_unlock_bh(&hw->phy_lock);
2563
2564 while (ms > 0) {
2565 sky2_led(hw, port, onoff);
2566 onoff = !onoff;
2567
2568 if (msleep_interruptible(250))
2569 break; /* interrupted */
2570 ms -= 250;
2571 }
2572
2573 /* resume regularly scheduled programming */
2574 spin_lock_bh(&hw->phy_lock);
793b883e
SH		 2575 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2576 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2577 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2578 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2579 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2580 } else {
2581 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2582 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2583 }
cd28ab6a
SH		 2584 spin_unlock_bh(&hw->phy_lock);
2585
2586 return 0;
2587}
2588
2589static void sky2_get_pauseparam(struct net_device *dev,
2590 struct ethtool_pauseparam *ecmd)
2591{
2592 struct sky2_port *sky2 = netdev_priv(dev);
2593
2594 ecmd->tx_pause = sky2->tx_pause;
2595 ecmd->rx_pause = sky2->rx_pause;
2596 ecmd->autoneg = sky2->autoneg;
2597}
2598
2599static int sky2_set_pauseparam(struct net_device *dev,
2600 struct ethtool_pauseparam *ecmd)
2601{
2602 struct sky2_port *sky2 = netdev_priv(dev);
2603 int err = 0;
2604
2605 sky2->autoneg = ecmd->autoneg;
2606 sky2->tx_pause = ecmd->tx_pause != 0;
2607 sky2->rx_pause = ecmd->rx_pause != 0;
2608
2609 if (netif_running(dev)) {
2610 sky2_down(dev);
2611 err = sky2_up(dev);
2612 }
2613
2614 return err;
2615}
2616
2617#ifdef CONFIG_PM
2618static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2619{
2620 struct sky2_port *sky2 = netdev_priv(dev);
2621
2622 wol->supported = WAKE_MAGIC;
2623 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2624}
2625
2626static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2627{
2628 struct sky2_port *sky2 = netdev_priv(dev);
2629 struct sky2_hw *hw = sky2->hw;
2630
2631 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2632 return -EOPNOTSUPP;
2633
2634 sky2->wol = wol->wolopts == WAKE_MAGIC;
2635
2636 if (sky2->wol) {
2637 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2638
2639 sky2_write16(hw, WOL_CTRL_STAT,
2640 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2641 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2642 } else
2643 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2644
2645 return 0;
2646}
2647#endif
2648
793b883e
SH		 2649static void sky2_get_ringparam(struct net_device *dev,
2650 struct ethtool_ringparam *ering)
2651{
2652 struct sky2_port *sky2 = netdev_priv(dev);
2653
2654 ering->rx_max_pending = RX_MAX_PENDING;
2655 ering->rx_mini_max_pending = 0;
2656 ering->rx_jumbo_max_pending = 0;
2657 ering->tx_max_pending = TX_RING_SIZE - 1;
2658
2659 ering->rx_pending = sky2->rx_pending;
2660 ering->rx_mini_pending = 0;
2661 ering->rx_jumbo_pending = 0;
2662 ering->tx_pending = sky2->tx_pending;
2663}
2664
2665static int sky2_set_ringparam(struct net_device *dev,
2666 struct ethtool_ringparam *ering)
2667{
2668 struct sky2_port *sky2 = netdev_priv(dev);
2669 int err = 0;
2670
2671 if (ering->rx_pending > RX_MAX_PENDING ||
2672 ering->rx_pending < 8 ||
2673 ering->tx_pending < MAX_SKB_TX_LE ||
2674 ering->tx_pending > TX_RING_SIZE - 1)
2675 return -EINVAL;
2676
2677 if (netif_running(dev))
2678 sky2_down(dev);
2679
2680 sky2->rx_pending = ering->rx_pending;
2681 sky2->tx_pending = ering->tx_pending;
2682
2683 if (netif_running(dev))
2684 err = sky2_up(dev);
2685
2686 return err;
2687}
2688
793b883e
SH		 2689static int sky2_get_regs_len(struct net_device *dev)
2690{
6e4cbb34 2691 return 0x4000;
793b883e
SH		 2692}
2693
2694/*
2695 * Returns copy of control register region
6e4cbb34 2696 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 2697 */
2698static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2699 void *p)
2700{
2701 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2702 const void __iomem *io = sky2->hw->regs;
793b883e 2703
6e4cbb34 2704 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 2705 regs->version = 1;
6e4cbb34 2706 memset(p, 0, regs->len);
793b883e 2707
6e4cbb34
SH		 2708 memcpy_fromio(p, io, B3_RAM_ADDR);
2709
2710 memcpy_fromio(p + B3_RI_WTO_R1,
2711 io + B3_RI_WTO_R1,
2712 regs->len - B3_RI_WTO_R1);
793b883e 2713}
cd28ab6a
SH		 2714
2715static struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 2716 .get_settings = sky2_get_settings,
2717 .set_settings = sky2_set_settings,
2718 .get_drvinfo = sky2_get_drvinfo,
2719 .get_msglevel = sky2_get_msglevel,
2720 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 2721 .nway_reset = sky2_nway_reset,
793b883e
SH		 2722 .get_regs_len = sky2_get_regs_len,
2723 .get_regs = sky2_get_regs,
2724 .get_link = ethtool_op_get_link,
2725 .get_sg = ethtool_op_get_sg,
2726 .set_sg = ethtool_op_set_sg,
2727 .get_tx_csum = ethtool_op_get_tx_csum,
2728 .set_tx_csum = ethtool_op_set_tx_csum,
2729 .get_tso = ethtool_op_get_tso,
2730 .set_tso = ethtool_op_set_tso,
2731 .get_rx_csum = sky2_get_rx_csum,
2732 .set_rx_csum = sky2_set_rx_csum,
2733 .get_strings = sky2_get_strings,
2734 .get_ringparam = sky2_get_ringparam,
2735 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 2736 .get_pauseparam = sky2_get_pauseparam,
2737 .set_pauseparam = sky2_set_pauseparam,
2738#ifdef CONFIG_PM
793b883e
SH		 2739 .get_wol = sky2_get_wol,
2740 .set_wol = sky2_set_wol,
cd28ab6a 2741#endif
793b883e 2742 .phys_id = sky2_phys_id,
cd28ab6a
SH		 2743 .get_stats_count = sky2_get_stats_count,
2744 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 2745 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 2746};
2747
2748/* Initialize network device */
2749static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2750 unsigned port, int highmem)
2751{
2752 struct sky2_port *sky2;
2753 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2754
2755 if (!dev) {
2756 printk(KERN_ERR "sky2 etherdev alloc failed");
2757 return NULL;
2758 }
2759
2760 SET_MODULE_OWNER(dev);
2761 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 2762 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 2763 dev->open = sky2_up;
2764 dev->stop = sky2_down;
ef743d33 2765 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 2766 dev->hard_start_xmit = sky2_xmit_frame;
2767 dev->get_stats = sky2_get_stats;
2768 dev->set_multicast_list = sky2_set_multicast;
2769 dev->set_mac_address = sky2_set_mac_address;
2770 dev->change_mtu = sky2_change_mtu;
2771 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2772 dev->tx_timeout = sky2_tx_timeout;
2773 dev->watchdog_timeo = TX_WATCHDOG;
2774 if (port == 0)
2775 dev->poll = sky2_poll;
2776 dev->weight = NAPI_WEIGHT;
2777#ifdef CONFIG_NET_POLL_CONTROLLER
2778 dev->poll_controller = sky2_netpoll;
2779#endif
cd28ab6a
SH		 2780
2781 sky2 = netdev_priv(dev);
2782 sky2->netdev = dev;
2783 sky2->hw = hw;
2784 sky2->msg_enable = netif_msg_init(debug, default_msg);
2785
2786 spin_lock_init(&sky2->tx_lock);
2787 /* Auto speed and flow control */
2788 sky2->autoneg = AUTONEG_ENABLE;
2789 sky2->tx_pause = 0;
2790 sky2->rx_pause = 1;
2791 sky2->duplex = -1;
2792 sky2->speed = -1;
2793 sky2->advertising = sky2_supported_modes(hw);
2794 sky2->rx_csum = 1;
793b883e
SH		 2795 tasklet_init(&sky2->phy_task, sky2_phy_task, (unsigned long)sky2);
2796 sky2->tx_pending = TX_DEF_PENDING;
2797 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
cd28ab6a
SH		 2798
2799 hw->dev[port] = dev;
2800
2801 sky2->port = port;
2802
793b883e 2803 dev->features |= NETIF_F_LLTX | NETIF_F_TSO;
cd28ab6a
SH		 2804 if (highmem)
2805 dev->features |= NETIF_F_HIGHDMA;
793b883e 2806 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 2807
d1f13708 2808#ifdef SKY2_VLAN_TAG_USED
2809 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2810 dev->vlan_rx_register = sky2_vlan_rx_register;
2811 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
2812#endif
2813
cd28ab6a 2814 /* read the mac address */
793b883e 2815 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 2816 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 2817
2818 /* device is off until link detection */
2819 netif_carrier_off(dev);
2820 netif_stop_queue(dev);
2821
2822 return dev;
2823}
2824
2825static inline void sky2_show_addr(struct net_device *dev)
2826{
2827 const struct sky2_port *sky2 = netdev_priv(dev);
2828
2829 if (netif_msg_probe(sky2))
2830 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
2831 dev->name,
2832 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2833 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2834}
2835
2836static int __devinit sky2_probe(struct pci_dev *pdev,
2837 const struct pci_device_id *ent)
2838{
793b883e 2839 struct net_device *dev, *dev1 = NULL;
cd28ab6a 2840 struct sky2_hw *hw;
5afa0a9c 2841 int err, pm_cap, using_dac = 0;
cd28ab6a 2842
793b883e
SH		 2843 err = pci_enable_device(pdev);
2844 if (err) {
cd28ab6a
SH		 2845 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
2846 pci_name(pdev));
2847 goto err_out;
2848 }
2849
793b883e
SH		 2850 err = pci_request_regions(pdev, DRV_NAME);
2851 if (err) {
cd28ab6a
SH		 2852 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
2853 pci_name(pdev));
793b883e 2854 goto err_out;
cd28ab6a
SH		 2855 }
2856
2857 pci_set_master(pdev);
2858
5afa0a9c 2859 /* Find power-management capability. */
2860 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
2861 if (pm_cap == 0) {
2862 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
2863 "aborting.\n");
2864 err = -EIO;
2865 goto err_out_free_regions;
2866 }
2867
cd28ab6a
SH		 2868 if (sizeof(dma_addr_t) > sizeof(u32)) {
2869 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2870 if (!err)
2871 using_dac = 1;
2872 }
2873
2874 if (!using_dac) {
2875 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2876 if (err) {
2877 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
2878 pci_name(pdev));
2879 goto err_out_free_regions;
2880 }
2881 }
cd28ab6a 2882#ifdef __BIG_ENDIAN
d571b694 2883 /* byte swap descriptors in hardware */
cd28ab6a
SH		 2884 {
2885 u32 reg;
2886
2887 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
2888 reg |= PCI_REV_DESC;
2889 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
2890 }
2891#endif
2892
2893 err = -ENOMEM;
2894 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
2895 if (!hw) {
2896 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
2897 pci_name(pdev));
2898 goto err_out_free_regions;
2899 }
2900
2901 memset(hw, 0, sizeof(*hw));
2902 hw->pdev = pdev;
2903 spin_lock_init(&hw->phy_lock);
2904
2905 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
2906 if (!hw->regs) {
2907 printk(KERN_ERR PFX "%s: cannot map device registers\n",
2908 pci_name(pdev));
2909 goto err_out_free_hw;
2910 }
5afa0a9c 2911 hw->pm_cap = pm_cap;
cd28ab6a 2912
cd28ab6a
SH		 2913 err = sky2_reset(hw);
2914 if (err)
793b883e 2915 goto err_out_iounmap;
cd28ab6a 2916
793b883e 2917 printk(KERN_INFO PFX "addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
cd28ab6a 2918 pci_resource_start(pdev, 0), pdev->irq,
793b883e
SH		 2919 yukon_name[hw->chip_id - CHIP_ID_YUKON],
2920 hw->chip_id, hw->chip_rev);
cd28ab6a 2921
793b883e
SH		 2922 dev = sky2_init_netdev(hw, 0, using_dac);
2923 if (!dev)
cd28ab6a
SH		 2924 goto err_out_free_pci;
2925
793b883e
SH		 2926 err = register_netdev(dev);
2927 if (err) {
cd28ab6a
SH		 2928 printk(KERN_ERR PFX "%s: cannot register net device\n",
2929 pci_name(pdev));
2930 goto err_out_free_netdev;
2931 }
2932
2933 sky2_show_addr(dev);
2934
2935 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
2936 if (register_netdev(dev1) == 0)
2937 sky2_show_addr(dev1);
2938 else {
2939 /* Failure to register second port need not be fatal */
793b883e
SH		 2940 printk(KERN_WARNING PFX
2941 "register of second port failed\n");
cd28ab6a
SH		 2942 hw->dev[1] = NULL;
2943 free_netdev(dev1);
2944 }
2945 }
2946
793b883e
SH		 2947 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
2948 if (err) {
2949 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
2950 pci_name(pdev), pdev->irq);
2951 goto err_out_unregister;
2952 }
2953
2954 hw->intr_mask = Y2_IS_BASE;
2955 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2956
2957 pci_set_drvdata(pdev, hw);
2958
cd28ab6a
SH		 2959 return 0;
2960
793b883e
SH		 2961err_out_unregister:
2962 if (dev1) {
2963 unregister_netdev(dev1);
2964 free_netdev(dev1);
2965 }
2966 unregister_netdev(dev);
cd28ab6a
SH		 2967err_out_free_netdev:
2968 free_netdev(dev);
cd28ab6a 2969err_out_free_pci:
793b883e 2970 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 2971 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
2972err_out_iounmap:
2973 iounmap(hw->regs);
2974err_out_free_hw:
2975 kfree(hw);
2976err_out_free_regions:
2977 pci_release_regions(pdev);
cd28ab6a 2978 pci_disable_device(pdev);
cd28ab6a
SH		 2979err_out:
2980 return err;
2981}
2982
2983static void __devexit sky2_remove(struct pci_dev *pdev)
2984{
793b883e 2985 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 2986 struct net_device *dev0, *dev1;
2987
793b883e 2988 if (!hw)
cd28ab6a
SH		 2989 return;
2990
cd28ab6a 2991 dev0 = hw->dev[0];
793b883e
SH		 2992 dev1 = hw->dev[1];
2993 if (dev1)
2994 unregister_netdev(dev1);
cd28ab6a
SH		 2995 unregister_netdev(dev0);
2996
793b883e 2997 sky2_write32(hw, B0_IMSK, 0);
5afa0a9c 2998 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 2999 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3000 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3001 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3002
3003 free_irq(pdev->irq, hw);
793b883e 3004 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3005 pci_release_regions(pdev);
3006 pci_disable_device(pdev);
793b883e 3007
cd28ab6a
SH		 3008 if (dev1)
3009 free_netdev(dev1);
3010 free_netdev(dev0);
3011 iounmap(hw->regs);
3012 kfree(hw);
5afa0a9c 3013
cd28ab6a
SH		 3014 pci_set_drvdata(pdev, NULL);
3015}
3016
3017#ifdef CONFIG_PM
3018static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3019{
793b883e 3020 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3021 int i;
cd28ab6a
SH		 3022
3023 for (i = 0; i < 2; i++) {
3024 struct net_device *dev = hw->dev[i];
3025
3026 if (dev) {
5afa0a9c 3027 if (!netif_running(dev))
3028 continue;
3029
3030 sky2_down(dev);
cd28ab6a 3031 netif_device_detach(dev);
cd28ab6a
SH		 3032 }
3033 }
3034
5afa0a9c 3035 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
cd28ab6a
SH		 3036}
3037
3038static int sky2_resume(struct pci_dev *pdev)
3039{
793b883e 3040 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3041 int i;
3042
cd28ab6a
SH		 3043 pci_restore_state(pdev);
3044 pci_enable_wake(pdev, PCI_D0, 0);
5afa0a9c 3045 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 3046
3047 sky2_reset(hw);
3048
3049 for (i = 0; i < 2; i++) {
3050 struct net_device *dev = hw->dev[i];
3051 if (dev) {
5afa0a9c 3052 if (netif_running(dev)) {
3053 netif_device_attach(dev);
cd28ab6a 3054 sky2_up(dev);
5afa0a9c 3055 }
cd28ab6a
SH		 3056 }
3057 }
3058 return 0;
3059}
3060#endif
3061
3062static struct pci_driver sky2_driver = {
793b883e
SH		 3063 .name = DRV_NAME,
3064 .id_table = sky2_id_table,
3065 .probe = sky2_probe,
3066 .remove = __devexit_p(sky2_remove),
cd28ab6a 3067#ifdef CONFIG_PM
793b883e
SH		 3068 .suspend = sky2_suspend,
3069 .resume = sky2_resume,
cd28ab6a
SH		 3070#endif
3071};
3072
3073static int __init sky2_init_module(void)
3074{
cd28ab6a
SH		 3075 return pci_module_init(&sky2_driver);
3076}
3077
3078static void __exit sky2_cleanup_module(void)
3079{
3080 pci_unregister_driver(&sky2_driver);
3081}
3082
3083module_init(sky2_init_module);
3084module_exit(sky2_cleanup_module);
3085
3086MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3087MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3088MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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