projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'r8169-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/romieu...
[deliverable/linux.git] / drivers / net / smc911x.h
CommitLineData
0a0c72c9
DM		 1/*------------------------------------------------------------------------
2 . smc911x.h - macros for SMSC's LAN911{5,6,7,8} single-chip Ethernet device.
3 .
4 . Copyright (C) 2005 Sensoria Corp.
5 . Derived from the unified SMC91x driver by Nicolas Pitre
6 .
7 . This program is free software; you can redistribute it and/or modify
8 . it under the terms of the GNU General Public License as published by
9 . the Free Software Foundation; either version 2 of the License, or
10 . (at your option) any later version.
11 .
12 . This program is distributed in the hope that it will be useful,
13 . but WITHOUT ANY WARRANTY; without even the implied warranty of
14 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 . GNU General Public License for more details.
16 .
17 . You should have received a copy of the GNU General Public License
18 . along with this program; if not, write to the Free Software
19 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 .
21 . Information contained in this file was obtained from the LAN9118
22 . manual from SMC. To get a copy, if you really want one, you can find
23 . information under www.smsc.com.
24 .
25 . Authors
26 . Dustin McIntire <dustin@sensoria.com>
27 .
28 ---------------------------------------------------------------------------*/
29#ifndef _SMC911X_H_
30#define _SMC911X_H_
31
12c03f59 32#include <linux/smc911x.h>
0a0c72c9
DM		 33/*
34 * Use the DMA feature on PXA chips
35 */
36#ifdef CONFIG_ARCH_PXA
37 #define SMC_USE_PXA_DMA 1
38 #define SMC_USE_16BIT 0
39 #define SMC_USE_32BIT 1
726d722e 40 #define SMC_IRQ_SENSE IRQF_TRIGGER_FALLING
d0c4581b 41#elif defined(CONFIG_SH_MAGIC_PANEL_R2)
726d722e
MB		 42 #define SMC_USE_16BIT 0
43 #define SMC_USE_32BIT 1
44 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
12c03f59
MD		 45#else
46/*
47 * Default configuration
48 */
49
50#define SMC_DYNAMIC_BUS_CONFIG
0a0c72c9
DM		 51#endif
52
699559f8
MD		 53/* store this information for the driver.. */
54struct smc911x_local {
55 /*
56 * If I have to wait until the DMA is finished and ready to reload a
57 * packet, I will store the skbuff here. Then, the DMA will send it
58 * out and free it.
59 */
60 struct sk_buff *pending_tx_skb;
61
62 /* version/revision of the SMC911x chip */
63 u16 version;
64 u16 revision;
65
66 /* FIFO sizes */
67 int tx_fifo_kb;
68 int tx_fifo_size;
69 int rx_fifo_size;
70 int afc_cfg;
71
72 /* Contains the current active receive/phy mode */
73 int ctl_rfduplx;
74 int ctl_rspeed;
75
76 u32 msg_enable;
77 u32 phy_type;
78 struct mii_if_info mii;
79
80 /* work queue */
81 struct work_struct phy_configure;
699559f8
MD		 82
83 int tx_throttle;
84 spinlock_t lock;
85
86 struct net_device *netdev;
87
88#ifdef SMC_USE_DMA
89 /* DMA needs the physical address of the chip */
90 u_long physaddr;
91 int rxdma;
92 int txdma;
93 int rxdma_active;
94 int txdma_active;
95 struct sk_buff *current_rx_skb;
96 struct sk_buff *current_tx_skb;
97 struct device *dev;
98#endif
99 void __iomem *base;
12c03f59
MD		 100#ifdef SMC_DYNAMIC_BUS_CONFIG
101 struct smc911x_platdata cfg;
102#endif
699559f8 103};
0a0c72c9
DM		 104
105/*
106 * Define the bus width specific IO macros
107 */
108
12c03f59
MD		 109#ifdef SMC_DYNAMIC_BUS_CONFIG
110static inline unsigned int SMC_inl(struct smc911x_local *lp, int reg)
111{
112 void __iomem *ioaddr = lp->base + reg;
113
114 if (lp->cfg.flags & SMC911X_USE_32BIT)
115 return readl(ioaddr);
116
117 if (lp->cfg.flags & SMC911X_USE_16BIT)
118 return readw(ioaddr) | (readw(ioaddr + 2) << 16);
119
120 BUG();
121}
122
123static inline void SMC_outl(unsigned int value, struct smc911x_local *lp,
124 int reg)
125{
126 void __iomem *ioaddr = lp->base + reg;
127
128 if (lp->cfg.flags & SMC911X_USE_32BIT) {
129 writel(value, ioaddr);
130 return;
131 }
132
133 if (lp->cfg.flags & SMC911X_USE_16BIT) {
134 writew(value & 0xffff, ioaddr);
135 writew(value >> 16, ioaddr + 2);
136 return;
137 }
138
139 BUG();
140}
141
142static inline void SMC_insl(struct smc911x_local *lp, int reg,
143 void *addr, unsigned int count)
144{
145 void __iomem *ioaddr = lp->base + reg;
146
147 if (lp->cfg.flags & SMC911X_USE_32BIT) {
148 readsl(ioaddr, addr, count);
149 return;
150 }
151
152 if (lp->cfg.flags & SMC911X_USE_16BIT) {
153 readsw(ioaddr, addr, count * 2);
154 return;
155 }
156
157 BUG();
158}
159
160static inline void SMC_outsl(struct smc911x_local *lp, int reg,
161 void *addr, unsigned int count)
162{
163 void __iomem *ioaddr = lp->base + reg;
164
165 if (lp->cfg.flags & SMC911X_USE_32BIT) {
166 writesl(ioaddr, addr, count);
167 return;
168 }
169
170 if (lp->cfg.flags & SMC911X_USE_16BIT) {
171 writesw(ioaddr, addr, count * 2);
172 return;
173 }
174
175 BUG();
176}
177#else
0a0c72c9 178#if SMC_USE_16BIT
699559f8
MD		 179#define SMC_inl(lp, r) ((readw((lp)->base + (r)) & 0xFFFF) + (readw((lp)->base + (r) + 2) << 16))
180#define SMC_outl(v, lp, r) \
0a0c72c9 181 do{ \
699559f8
MD		 182 writew(v & 0xFFFF, (lp)->base + (r)); \
183 writew(v >> 16, (lp)->base + (r) + 2); \
0a0c72c9 184 } while (0)
699559f8
MD		 185#define SMC_insl(lp, r, p, l) readsw((short*)((lp)->base + (r)), p, l*2)
186#define SMC_outsl(lp, r, p, l) writesw((short*)((lp)->base + (r)), p, l*2)
0a0c72c9
DM		 187
188#elif SMC_USE_32BIT
699559f8
MD		 189#define SMC_inl(lp, r) readl((lp)->base + (r))
190#define SMC_outl(v, lp, r) writel(v, (lp)->base + (r))
191#define SMC_insl(lp, r, p, l) readsl((int*)((lp)->base + (r)), p, l)
192#define SMC_outsl(lp, r, p, l) writesl((int*)((lp)->base + (r)), p, l)
0a0c72c9
DM		 193
194#endif /* SMC_USE_16BIT */
12c03f59
MD		 195#endif /* SMC_DYNAMIC_BUS_CONFIG */
196
0a0c72c9 197
b173079f 198#ifdef SMC_USE_PXA_DMA
0a0c72c9
DM		 199#define SMC_USE_DMA
200
d5498bef
JG		 201/*
202 * Define the request and free functions
0a0c72c9
DM		 203 * These are unfortunately architecture specific as no generic allocation
204 * mechanism exits
205 */
206#define SMC_DMA_REQUEST(dev, handler) \
d5498bef 207 pxa_request_dma(dev->name, DMA_PRIO_LOW, handler, dev)
0a0c72c9
DM		 208
209#define SMC_DMA_FREE(dev, dma) \
210 pxa_free_dma(dma)
211
212#define SMC_DMA_ACK_IRQ(dev, dma) \
213{ \
214 if (DCSR(dma) & DCSR_BUSERR) { \
215 printk("%s: DMA %d bus error!\n", dev->name, dma); \
216 } \
217 DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; \
218}
219
220/*
221 * Use a DMA for RX and TX packets.
222 */
223#include <linux/dma-mapping.h>
224#include <asm/dma.h>
a09e64fb 225#include <mach/pxa-regs.h>
0a0c72c9
DM		 226
227static dma_addr_t rx_dmabuf, tx_dmabuf;
228static int rx_dmalen, tx_dmalen;
d5498bef 229
0a0c72c9
DM		 230#ifdef SMC_insl
231#undef SMC_insl
699559f8
MD		 232#define SMC_insl(lp, r, p, l) \
233 smc_pxa_dma_insl(lp, lp->physaddr, r, lp->rxdma, p, l)
0a0c72c9
DM		 234
235static inline void
699559f8 236smc_pxa_dma_insl(struct smc911x_local *lp, u_long physaddr,
0a0c72c9
DM		 237 int reg, int dma, u_char *buf, int len)
238{
239 /* 64 bit alignment is required for memory to memory DMA */
240 if ((long)buf & 4) {
699559f8 241 *((u32 *)buf) = SMC_inl(lp, reg);
0a0c72c9
DM		 242 buf += 4;
243 len--;
244 }
245
246 len *= 4;
699559f8 247 rx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_FROM_DEVICE);
0a0c72c9
DM		 248 rx_dmalen = len;
249 DCSR(dma) = DCSR_NODESC;
250 DTADR(dma) = rx_dmabuf;
251 DSADR(dma) = physaddr + reg;
252 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
253 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
254 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
255}
256#endif
257
0a0c72c9
DM		 258#ifdef SMC_outsl
259#undef SMC_outsl
699559f8
MD		 260#define SMC_outsl(lp, r, p, l) \
261 smc_pxa_dma_outsl(lp, lp->physaddr, r, lp->txdma, p, l)
0a0c72c9
DM		 262
263static inline void
699559f8 264smc_pxa_dma_outsl(struct smc911x_local *lp, u_long physaddr,
0a0c72c9
DM		 265 int reg, int dma, u_char *buf, int len)
266{
267 /* 64 bit alignment is required for memory to memory DMA */
268 if ((long)buf & 4) {
699559f8 269 SMC_outl(*((u32 *)buf), lp, reg);
0a0c72c9
DM		 270 buf += 4;
271 len--;
272 }
273
274 len *= 4;
699559f8 275 tx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_TO_DEVICE);
0a0c72c9
DM		 276 tx_dmalen = len;
277 DCSR(dma) = DCSR_NODESC;
278 DSADR(dma) = tx_dmabuf;
279 DTADR(dma) = physaddr + reg;
280 DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
281 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
282 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
283}
284#endif
0a0c72c9
DM		 285#endif /* SMC_USE_PXA_DMA */
286
287
288/* Chip Parameters and Register Definitions */
289
290#define SMC911X_TX_FIFO_LOW_THRESHOLD (1536*2)
291
292#define SMC911X_IO_EXTENT 0x100
293
294#define SMC911X_EEPROM_LEN 7
295
296/* Below are the register offsets and bit definitions
297 * of the Lan911x memory space
298 */
299#define RX_DATA_FIFO (0x00)
300
301#define TX_DATA_FIFO (0x20)
302#define TX_CMD_A_INT_ON_COMP_ (0x80000000)
303#define TX_CMD_A_INT_BUF_END_ALGN_ (0x03000000)
304#define TX_CMD_A_INT_4_BYTE_ALGN_ (0x00000000)
305#define TX_CMD_A_INT_16_BYTE_ALGN_ (0x01000000)
306#define TX_CMD_A_INT_32_BYTE_ALGN_ (0x02000000)
307#define TX_CMD_A_INT_DATA_OFFSET_ (0x001F0000)
308#define TX_CMD_A_INT_FIRST_SEG_ (0x00002000)
309#define TX_CMD_A_INT_LAST_SEG_ (0x00001000)
310#define TX_CMD_A_BUF_SIZE_ (0x000007FF)
311#define TX_CMD_B_PKT_TAG_ (0xFFFF0000)
312#define TX_CMD_B_ADD_CRC_DISABLE_ (0x00002000)
313#define TX_CMD_B_DISABLE_PADDING_ (0x00001000)
314#define TX_CMD_B_PKT_BYTE_LENGTH_ (0x000007FF)
315
316#define RX_STATUS_FIFO (0x40)
317#define RX_STS_PKT_LEN_ (0x3FFF0000)
318#define RX_STS_ES_ (0x00008000)
319#define RX_STS_BCST_ (0x00002000)
320#define RX_STS_LEN_ERR_ (0x00001000)
321#define RX_STS_RUNT_ERR_ (0x00000800)
322#define RX_STS_MCAST_ (0x00000400)
323#define RX_STS_TOO_LONG_ (0x00000080)
324#define RX_STS_COLL_ (0x00000040)
325#define RX_STS_ETH_TYPE_ (0x00000020)
326#define RX_STS_WDOG_TMT_ (0x00000010)
327#define RX_STS_MII_ERR_ (0x00000008)
328#define RX_STS_DRIBBLING_ (0x00000004)
329#define RX_STS_CRC_ERR_ (0x00000002)
330#define RX_STATUS_FIFO_PEEK (0x44)
331#define TX_STATUS_FIFO (0x48)
332#define TX_STS_TAG_ (0xFFFF0000)
333#define TX_STS_ES_ (0x00008000)
334#define TX_STS_LOC_ (0x00000800)
335#define TX_STS_NO_CARR_ (0x00000400)
336#define TX_STS_LATE_COLL_ (0x00000200)
337#define TX_STS_MANY_COLL_ (0x00000100)
338#define TX_STS_COLL_CNT_ (0x00000078)
339#define TX_STS_MANY_DEFER_ (0x00000004)
340#define TX_STS_UNDERRUN_ (0x00000002)
341#define TX_STS_DEFERRED_ (0x00000001)
342#define TX_STATUS_FIFO_PEEK (0x4C)
343#define ID_REV (0x50)
344#define ID_REV_CHIP_ID_ (0xFFFF0000) /* RO */
345#define ID_REV_REV_ID_ (0x0000FFFF) /* RO */
346
347#define INT_CFG (0x54)
348#define INT_CFG_INT_DEAS_ (0xFF000000) /* R/W */
349#define INT_CFG_INT_DEAS_CLR_ (0x00004000)
350#define INT_CFG_INT_DEAS_STS_ (0x00002000)
351#define INT_CFG_IRQ_INT_ (0x00001000) /* RO */
352#define INT_CFG_IRQ_EN_ (0x00000100) /* R/W */
353#define INT_CFG_IRQ_POL_ (0x00000010) /* R/W Not Affected by SW Reset */
354#define INT_CFG_IRQ_TYPE_ (0x00000001) /* R/W Not Affected by SW Reset */
355
356#define INT_STS (0x58)
357#define INT_STS_SW_INT_ (0x80000000) /* R/WC */
358#define INT_STS_TXSTOP_INT_ (0x02000000) /* R/WC */
359#define INT_STS_RXSTOP_INT_ (0x01000000) /* R/WC */
360#define INT_STS_RXDFH_INT_ (0x00800000) /* R/WC */
361#define INT_STS_RXDF_INT_ (0x00400000) /* R/WC */
362#define INT_STS_TX_IOC_ (0x00200000) /* R/WC */
363#define INT_STS_RXD_INT_ (0x00100000) /* R/WC */
364#define INT_STS_GPT_INT_ (0x00080000) /* R/WC */
365#define INT_STS_PHY_INT_ (0x00040000) /* RO */
366#define INT_STS_PME_INT_ (0x00020000) /* R/WC */
367#define INT_STS_TXSO_ (0x00010000) /* R/WC */
368#define INT_STS_RWT_ (0x00008000) /* R/WC */
369#define INT_STS_RXE_ (0x00004000) /* R/WC */
370#define INT_STS_TXE_ (0x00002000) /* R/WC */
371//#define INT_STS_ERX_ (0x00001000) /* R/WC */
372#define INT_STS_TDFU_ (0x00000800) /* R/WC */
373#define INT_STS_TDFO_ (0x00000400) /* R/WC */
374#define INT_STS_TDFA_ (0x00000200) /* R/WC */
375#define INT_STS_TSFF_ (0x00000100) /* R/WC */
376#define INT_STS_TSFL_ (0x00000080) /* R/WC */
377//#define INT_STS_RXDF_ (0x00000040) /* R/WC */
378#define INT_STS_RDFO_ (0x00000040) /* R/WC */
379#define INT_STS_RDFL_ (0x00000020) /* R/WC */
380#define INT_STS_RSFF_ (0x00000010) /* R/WC */
381#define INT_STS_RSFL_ (0x00000008) /* R/WC */
382#define INT_STS_GPIO2_INT_ (0x00000004) /* R/WC */
383#define INT_STS_GPIO1_INT_ (0x00000002) /* R/WC */
384#define INT_STS_GPIO0_INT_ (0x00000001) /* R/WC */
385
386#define INT_EN (0x5C)
387#define INT_EN_SW_INT_EN_ (0x80000000) /* R/W */
388#define INT_EN_TXSTOP_INT_EN_ (0x02000000) /* R/W */
389#define INT_EN_RXSTOP_INT_EN_ (0x01000000) /* R/W */
390#define INT_EN_RXDFH_INT_EN_ (0x00800000) /* R/W */
391//#define INT_EN_RXDF_INT_EN_ (0x00400000) /* R/W */
392#define INT_EN_TIOC_INT_EN_ (0x00200000) /* R/W */
393#define INT_EN_RXD_INT_EN_ (0x00100000) /* R/W */
394#define INT_EN_GPT_INT_EN_ (0x00080000) /* R/W */
395#define INT_EN_PHY_INT_EN_ (0x00040000) /* R/W */
396#define INT_EN_PME_INT_EN_ (0x00020000) /* R/W */
397#define INT_EN_TXSO_EN_ (0x00010000) /* R/W */
398#define INT_EN_RWT_EN_ (0x00008000) /* R/W */
399#define INT_EN_RXE_EN_ (0x00004000) /* R/W */
400#define INT_EN_TXE_EN_ (0x00002000) /* R/W */
401//#define INT_EN_ERX_EN_ (0x00001000) /* R/W */
402#define INT_EN_TDFU_EN_ (0x00000800) /* R/W */
403#define INT_EN_TDFO_EN_ (0x00000400) /* R/W */
404#define INT_EN_TDFA_EN_ (0x00000200) /* R/W */
405#define INT_EN_TSFF_EN_ (0x00000100) /* R/W */
406#define INT_EN_TSFL_EN_ (0x00000080) /* R/W */
407//#define INT_EN_RXDF_EN_ (0x00000040) /* R/W */
408#define INT_EN_RDFO_EN_ (0x00000040) /* R/W */
409#define INT_EN_RDFL_EN_ (0x00000020) /* R/W */
410#define INT_EN_RSFF_EN_ (0x00000010) /* R/W */
411#define INT_EN_RSFL_EN_ (0x00000008) /* R/W */
412#define INT_EN_GPIO2_INT_ (0x00000004) /* R/W */
413#define INT_EN_GPIO1_INT_ (0x00000002) /* R/W */
414#define INT_EN_GPIO0_INT_ (0x00000001) /* R/W */
415
416#define BYTE_TEST (0x64)
417#define FIFO_INT (0x68)
418#define FIFO_INT_TX_AVAIL_LEVEL_ (0xFF000000) /* R/W */
419#define FIFO_INT_TX_STS_LEVEL_ (0x00FF0000) /* R/W */
420#define FIFO_INT_RX_AVAIL_LEVEL_ (0x0000FF00) /* R/W */
421#define FIFO_INT_RX_STS_LEVEL_ (0x000000FF) /* R/W */
422
423#define RX_CFG (0x6C)
424#define RX_CFG_RX_END_ALGN_ (0xC0000000) /* R/W */
425#define RX_CFG_RX_END_ALGN4_ (0x00000000) /* R/W */
426#define RX_CFG_RX_END_ALGN16_ (0x40000000) /* R/W */
427#define RX_CFG_RX_END_ALGN32_ (0x80000000) /* R/W */
428#define RX_CFG_RX_DMA_CNT_ (0x0FFF0000) /* R/W */
429#define RX_CFG_RX_DUMP_ (0x00008000) /* R/W */
430#define RX_CFG_RXDOFF_ (0x00001F00) /* R/W */
431//#define RX_CFG_RXBAD_ (0x00000001) /* R/W */
432
433#define TX_CFG (0x70)
434//#define TX_CFG_TX_DMA_LVL_ (0xE0000000) /* R/W */
435//#define TX_CFG_TX_DMA_CNT_ (0x0FFF0000) /* R/W Self Clearing */
436#define TX_CFG_TXS_DUMP_ (0x00008000) /* Self Clearing */
437#define TX_CFG_TXD_DUMP_ (0x00004000) /* Self Clearing */
438#define TX_CFG_TXSAO_ (0x00000004) /* R/W */
439#define TX_CFG_TX_ON_ (0x00000002) /* R/W */
440#define TX_CFG_STOP_TX_ (0x00000001) /* Self Clearing */
441
442#define HW_CFG (0x74)
443#define HW_CFG_TTM_ (0x00200000) /* R/W */
444#define HW_CFG_SF_ (0x00100000) /* R/W */
445#define HW_CFG_TX_FIF_SZ_ (0x000F0000) /* R/W */
446#define HW_CFG_TR_ (0x00003000) /* R/W */
447#define HW_CFG_PHY_CLK_SEL_ (0x00000060) /* R/W */
448#define HW_CFG_PHY_CLK_SEL_INT_PHY_ (0x00000000) /* R/W */
449#define HW_CFG_PHY_CLK_SEL_EXT_PHY_ (0x00000020) /* R/W */
450#define HW_CFG_PHY_CLK_SEL_CLK_DIS_ (0x00000040) /* R/W */
451#define HW_CFG_SMI_SEL_ (0x00000010) /* R/W */
452#define HW_CFG_EXT_PHY_DET_ (0x00000008) /* RO */
453#define HW_CFG_EXT_PHY_EN_ (0x00000004) /* R/W */
454#define HW_CFG_32_16_BIT_MODE_ (0x00000004) /* RO */
455#define HW_CFG_SRST_TO_ (0x00000002) /* RO */
456#define HW_CFG_SRST_ (0x00000001) /* Self Clearing */
457
458#define RX_DP_CTRL (0x78)
459#define RX_DP_CTRL_RX_FFWD_ (0x80000000) /* R/W */
460#define RX_DP_CTRL_FFWD_BUSY_ (0x80000000) /* RO */
461
462#define RX_FIFO_INF (0x7C)
463#define RX_FIFO_INF_RXSUSED_ (0x00FF0000) /* RO */
464#define RX_FIFO_INF_RXDUSED_ (0x0000FFFF) /* RO */
465
466#define TX_FIFO_INF (0x80)
467#define TX_FIFO_INF_TSUSED_ (0x00FF0000) /* RO */
468#define TX_FIFO_INF_TDFREE_ (0x0000FFFF) /* RO */
469
470#define PMT_CTRL (0x84)
471#define PMT_CTRL_PM_MODE_ (0x00003000) /* Self Clearing */
472#define PMT_CTRL_PHY_RST_ (0x00000400) /* Self Clearing */
473#define PMT_CTRL_WOL_EN_ (0x00000200) /* R/W */
474#define PMT_CTRL_ED_EN_ (0x00000100) /* R/W */
475#define PMT_CTRL_PME_TYPE_ (0x00000040) /* R/W Not Affected by SW Reset */
476#define PMT_CTRL_WUPS_ (0x00000030) /* R/WC */
477#define PMT_CTRL_WUPS_NOWAKE_ (0x00000000) /* R/WC */
478#define PMT_CTRL_WUPS_ED_ (0x00000010) /* R/WC */
479#define PMT_CTRL_WUPS_WOL_ (0x00000020) /* R/WC */
480#define PMT_CTRL_WUPS_MULTI_ (0x00000030) /* R/WC */
481#define PMT_CTRL_PME_IND_ (0x00000008) /* R/W */
482#define PMT_CTRL_PME_POL_ (0x00000004) /* R/W */
483#define PMT_CTRL_PME_EN_ (0x00000002) /* R/W Not Affected by SW Reset */
484#define PMT_CTRL_READY_ (0x00000001) /* RO */
485
486#define GPIO_CFG (0x88)
487#define GPIO_CFG_LED3_EN_ (0x40000000) /* R/W */
488#define GPIO_CFG_LED2_EN_ (0x20000000) /* R/W */
489#define GPIO_CFG_LED1_EN_ (0x10000000) /* R/W */
490#define GPIO_CFG_GPIO2_INT_POL_ (0x04000000) /* R/W */
491#define GPIO_CFG_GPIO1_INT_POL_ (0x02000000) /* R/W */
492#define GPIO_CFG_GPIO0_INT_POL_ (0x01000000) /* R/W */
493#define GPIO_CFG_EEPR_EN_ (0x00700000) /* R/W */
494#define GPIO_CFG_GPIOBUF2_ (0x00040000) /* R/W */
495#define GPIO_CFG_GPIOBUF1_ (0x00020000) /* R/W */
496#define GPIO_CFG_GPIOBUF0_ (0x00010000) /* R/W */
497#define GPIO_CFG_GPIODIR2_ (0x00000400) /* R/W */
498#define GPIO_CFG_GPIODIR1_ (0x00000200) /* R/W */
499#define GPIO_CFG_GPIODIR0_ (0x00000100) /* R/W */
500#define GPIO_CFG_GPIOD4_ (0x00000010) /* R/W */
501#define GPIO_CFG_GPIOD3_ (0x00000008) /* R/W */
502#define GPIO_CFG_GPIOD2_ (0x00000004) /* R/W */
503#define GPIO_CFG_GPIOD1_ (0x00000002) /* R/W */
504#define GPIO_CFG_GPIOD0_ (0x00000001) /* R/W */
505
506#define GPT_CFG (0x8C)
507#define GPT_CFG_TIMER_EN_ (0x20000000) /* R/W */
508#define GPT_CFG_GPT_LOAD_ (0x0000FFFF) /* R/W */
509
510#define GPT_CNT (0x90)
511#define GPT_CNT_GPT_CNT_ (0x0000FFFF) /* RO */
512
513#define ENDIAN (0x98)
514#define FREE_RUN (0x9C)
515#define RX_DROP (0xA0)
516#define MAC_CSR_CMD (0xA4)
517#define MAC_CSR_CMD_CSR_BUSY_ (0x80000000) /* Self Clearing */
518#define MAC_CSR_CMD_R_NOT_W_ (0x40000000) /* R/W */
519#define MAC_CSR_CMD_CSR_ADDR_ (0x000000FF) /* R/W */
520
521#define MAC_CSR_DATA (0xA8)
522#define AFC_CFG (0xAC)
523#define AFC_CFG_AFC_HI_ (0x00FF0000) /* R/W */
524#define AFC_CFG_AFC_LO_ (0x0000FF00) /* R/W */
525#define AFC_CFG_BACK_DUR_ (0x000000F0) /* R/W */
526#define AFC_CFG_FCMULT_ (0x00000008) /* R/W */
527#define AFC_CFG_FCBRD_ (0x00000004) /* R/W */
528#define AFC_CFG_FCADD_ (0x00000002) /* R/W */
529#define AFC_CFG_FCANY_ (0x00000001) /* R/W */
530
531#define E2P_CMD (0xB0)
532#define E2P_CMD_EPC_BUSY_ (0x80000000) /* Self Clearing */
533#define E2P_CMD_EPC_CMD_ (0x70000000) /* R/W */
534#define E2P_CMD_EPC_CMD_READ_ (0x00000000) /* R/W */
535#define E2P_CMD_EPC_CMD_EWDS_ (0x10000000) /* R/W */
536#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) /* R/W */
537#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) /* R/W */
538#define E2P_CMD_EPC_CMD_WRAL_ (0x40000000) /* R/W */
539#define E2P_CMD_EPC_CMD_ERASE_ (0x50000000) /* R/W */
540#define E2P_CMD_EPC_CMD_ERAL_ (0x60000000) /* R/W */
541#define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000) /* R/W */
542#define E2P_CMD_EPC_TIMEOUT_ (0x00000200) /* RO */
543#define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100) /* RO */
544#define E2P_CMD_EPC_ADDR_ (0x000000FF) /* R/W */
545
546#define E2P_DATA (0xB4)
547#define E2P_DATA_EEPROM_DATA_ (0x000000FF) /* R/W */
548/* end of LAN register offsets and bit definitions */
549
550/*
551 ****************************************************************************
552 ****************************************************************************
553 * MAC Control and Status Register (Indirect Address)
554 * Offset (through the MAC_CSR CMD and DATA port)
555 ****************************************************************************
556 ****************************************************************************
557 *
558 */
559#define MAC_CR (0x01) /* R/W */
560
561/* MAC_CR - MAC Control Register */
562#define MAC_CR_RXALL_ (0x80000000)
563// TODO: delete this bit? It is not described in the data sheet.
564#define MAC_CR_HBDIS_ (0x10000000)
565#define MAC_CR_RCVOWN_ (0x00800000)
566#define MAC_CR_LOOPBK_ (0x00200000)
567#define MAC_CR_FDPX_ (0x00100000)
568#define MAC_CR_MCPAS_ (0x00080000)
569#define MAC_CR_PRMS_ (0x00040000)
570#define MAC_CR_INVFILT_ (0x00020000)
571#define MAC_CR_PASSBAD_ (0x00010000)
572#define MAC_CR_HFILT_ (0x00008000)
573#define MAC_CR_HPFILT_ (0x00002000)
574#define MAC_CR_LCOLL_ (0x00001000)
575#define MAC_CR_BCAST_ (0x00000800)
576#define MAC_CR_DISRTY_ (0x00000400)
577#define MAC_CR_PADSTR_ (0x00000100)
578#define MAC_CR_BOLMT_MASK_ (0x000000C0)
579#define MAC_CR_DFCHK_ (0x00000020)
580#define MAC_CR_TXEN_ (0x00000008)
581#define MAC_CR_RXEN_ (0x00000004)
582
583#define ADDRH (0x02) /* R/W mask 0x0000FFFFUL */
584#define ADDRL (0x03) /* R/W mask 0xFFFFFFFFUL */
585#define HASHH (0x04) /* R/W */
586#define HASHL (0x05) /* R/W */
587
588#define MII_ACC (0x06) /* R/W */
589#define MII_ACC_PHY_ADDR_ (0x0000F800)
590#define MII_ACC_MIIRINDA_ (0x000007C0)
591#define MII_ACC_MII_WRITE_ (0x00000002)
592#define MII_ACC_MII_BUSY_ (0x00000001)
593
594#define MII_DATA (0x07) /* R/W mask 0x0000FFFFUL */
595
596#define FLOW (0x08) /* R/W */
597#define FLOW_FCPT_ (0xFFFF0000)
598#define FLOW_FCPASS_ (0x00000004)
599#define FLOW_FCEN_ (0x00000002)
600#define FLOW_FCBSY_ (0x00000001)
601
602#define VLAN1 (0x09) /* R/W mask 0x0000FFFFUL */
603#define VLAN1_VTI1_ (0x0000ffff)
604
605#define VLAN2 (0x0A) /* R/W mask 0x0000FFFFUL */
606#define VLAN2_VTI2_ (0x0000ffff)
607
608#define WUFF (0x0B) /* WO */
609
610#define WUCSR (0x0C) /* R/W */
611#define WUCSR_GUE_ (0x00000200)
612#define WUCSR_WUFR_ (0x00000040)
613#define WUCSR_MPR_ (0x00000020)
614#define WUCSR_WAKE_EN_ (0x00000004)
615#define WUCSR_MPEN_ (0x00000002)
616
617/*
618 ****************************************************************************
619 * Chip Specific MII Defines
620 ****************************************************************************
621 *
622 * Phy register offsets and bit definitions
623 *
624 */
625
626#define PHY_MODE_CTRL_STS ((u32)17) /* Mode Control/Status Register */
627//#define MODE_CTRL_STS_FASTRIP_ ((u16)0x4000)
628#define MODE_CTRL_STS_EDPWRDOWN_ ((u16)0x2000)
629//#define MODE_CTRL_STS_LOWSQEN_ ((u16)0x0800)
630//#define MODE_CTRL_STS_MDPREBP_ ((u16)0x0400)
631//#define MODE_CTRL_STS_FARLOOPBACK_ ((u16)0x0200)
632//#define MODE_CTRL_STS_FASTEST_ ((u16)0x0100)
633//#define MODE_CTRL_STS_REFCLKEN_ ((u16)0x0010)
634//#define MODE_CTRL_STS_PHYADBP_ ((u16)0x0008)
635//#define MODE_CTRL_STS_FORCE_G_LINK_ ((u16)0x0004)
636#define MODE_CTRL_STS_ENERGYON_ ((u16)0x0002)
637
638#define PHY_INT_SRC ((u32)29)
639#define PHY_INT_SRC_ENERGY_ON_ ((u16)0x0080)
640#define PHY_INT_SRC_ANEG_COMP_ ((u16)0x0040)
641#define PHY_INT_SRC_REMOTE_FAULT_ ((u16)0x0020)
642#define PHY_INT_SRC_LINK_DOWN_ ((u16)0x0010)
643#define PHY_INT_SRC_ANEG_LP_ACK_ ((u16)0x0008)
644#define PHY_INT_SRC_PAR_DET_FAULT_ ((u16)0x0004)
645#define PHY_INT_SRC_ANEG_PGRX_ ((u16)0x0002)
646
647#define PHY_INT_MASK ((u32)30)
648#define PHY_INT_MASK_ENERGY_ON_ ((u16)0x0080)
649#define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
650#define PHY_INT_MASK_REMOTE_FAULT_ ((u16)0x0020)
651#define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
652#define PHY_INT_MASK_ANEG_LP_ACK_ ((u16)0x0008)
653#define PHY_INT_MASK_PAR_DET_FAULT_ ((u16)0x0004)
654#define PHY_INT_MASK_ANEG_PGRX_ ((u16)0x0002)
655
656#define PHY_SPECIAL ((u32)31)
657#define PHY_SPECIAL_ANEG_DONE_ ((u16)0x1000)
658#define PHY_SPECIAL_RES_ ((u16)0x0040)
659#define PHY_SPECIAL_RES_MASK_ ((u16)0x0FE1)
660#define PHY_SPECIAL_SPD_ ((u16)0x001C)
661#define PHY_SPECIAL_SPD_10HALF_ ((u16)0x0004)
662#define PHY_SPECIAL_SPD_10FULL_ ((u16)0x0014)
663#define PHY_SPECIAL_SPD_100HALF_ ((u16)0x0008)
664#define PHY_SPECIAL_SPD_100FULL_ ((u16)0x0018)
665
666#define LAN911X_INTERNAL_PHY_ID (0x0007C000)
667
668/* Chip ID values */
669#define CHIP_9115 0x115
670#define CHIP_9116 0x116
671#define CHIP_9117 0x117
672#define CHIP_9118 0x118
673
674struct chip_id {
675 u16 id;
676 char *name;
677};
d5498bef 678
0a0c72c9
DM		 679static const struct chip_id chip_ids[] = {
680 { CHIP_9115, "LAN9115" },
681 { CHIP_9116, "LAN9116" },
682 { CHIP_9117, "LAN9117" },
683 { CHIP_9118, "LAN9118" },
684 { 0, NULL },
685};
686
687#define IS_REV_A(x) ((x & 0xFFFF)==0)
688
689/*
690 * Macros to abstract register access according to the data bus
691 * capabilities. Please use those and not the in/out primitives.
692 */
693/* FIFO read/write macros */
699559f8
MD		 694#define SMC_PUSH_DATA(lp, p, l) SMC_outsl( lp, TX_DATA_FIFO, p, (l) >> 2 )
695#define SMC_PULL_DATA(lp, p, l) SMC_insl ( lp, RX_DATA_FIFO, p, (l) >> 2 )
696#define SMC_SET_TX_FIFO(lp, x) SMC_outl( x, lp, TX_DATA_FIFO )
697#define SMC_GET_RX_FIFO(lp) SMC_inl( lp, RX_DATA_FIFO )
0a0c72c9
DM		 698
699
700/* I/O mapped register read/write macros */
699559f8
MD		 701#define SMC_GET_TX_STS_FIFO(lp) SMC_inl( lp, TX_STATUS_FIFO )
702#define SMC_GET_RX_STS_FIFO(lp) SMC_inl( lp, RX_STATUS_FIFO )
703#define SMC_GET_RX_STS_FIFO_PEEK(lp) SMC_inl( lp, RX_STATUS_FIFO_PEEK )
704#define SMC_GET_PN(lp) (SMC_inl( lp, ID_REV ) >> 16)
705#define SMC_GET_REV(lp) (SMC_inl( lp, ID_REV ) & 0xFFFF)
706#define SMC_GET_IRQ_CFG(lp) SMC_inl( lp, INT_CFG )
707#define SMC_SET_IRQ_CFG(lp, x) SMC_outl( x, lp, INT_CFG )
708#define SMC_GET_INT(lp) SMC_inl( lp, INT_STS )
709#define SMC_ACK_INT(lp, x) SMC_outl( x, lp, INT_STS )
710#define SMC_GET_INT_EN(lp) SMC_inl( lp, INT_EN )
711#define SMC_SET_INT_EN(lp, x) SMC_outl( x, lp, INT_EN )
712#define SMC_GET_BYTE_TEST(lp) SMC_inl( lp, BYTE_TEST )
713#define SMC_SET_BYTE_TEST(lp, x) SMC_outl( x, lp, BYTE_TEST )
714#define SMC_GET_FIFO_INT(lp) SMC_inl( lp, FIFO_INT )
715#define SMC_SET_FIFO_INT(lp, x) SMC_outl( x, lp, FIFO_INT )
716#define SMC_SET_FIFO_TDA(lp, x) \
0a0c72c9
DM		 717 do { \
718 unsigned long __flags; \
719 int __mask; \
720 local_irq_save(__flags); \
699559f8
MD		 721 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<24); \
722 SMC_SET_FIFO_INT( (lp), __mask | (x)<<24 ); \
0a0c72c9
DM		 723 local_irq_restore(__flags); \
724 } while (0)
699559f8 725#define SMC_SET_FIFO_TSL(lp, x) \
0a0c72c9
DM		 726 do { \
727 unsigned long __flags; \
728 int __mask; \
729 local_irq_save(__flags); \
699559f8
MD		 730 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<16); \
731 SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<16)); \
0a0c72c9
DM		 732 local_irq_restore(__flags); \
733 } while (0)
699559f8 734#define SMC_SET_FIFO_RSA(lp, x) \
0a0c72c9
DM		 735 do { \
736 unsigned long __flags; \
737 int __mask; \
738 local_irq_save(__flags); \
699559f8
MD		 739 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<8); \
740 SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<8)); \
0a0c72c9
DM		 741 local_irq_restore(__flags); \
742 } while (0)
699559f8 743#define SMC_SET_FIFO_RSL(lp, x) \
0a0c72c9
DM		 744 do { \
745 unsigned long __flags; \
746 int __mask; \
747 local_irq_save(__flags); \
699559f8
MD		 748 __mask = SMC_GET_FIFO_INT((lp)) & ~0xFF; \
749 SMC_SET_FIFO_INT( (lp),__mask | ((x) & 0xFF)); \
0a0c72c9
DM		 750 local_irq_restore(__flags); \
751 } while (0)
699559f8
MD		 752#define SMC_GET_RX_CFG(lp) SMC_inl( lp, RX_CFG )
753#define SMC_SET_RX_CFG(lp, x) SMC_outl( x, lp, RX_CFG )
754#define SMC_GET_TX_CFG(lp) SMC_inl( lp, TX_CFG )
755#define SMC_SET_TX_CFG(lp, x) SMC_outl( x, lp, TX_CFG )
756#define SMC_GET_HW_CFG(lp) SMC_inl( lp, HW_CFG )
757#define SMC_SET_HW_CFG(lp, x) SMC_outl( x, lp, HW_CFG )
758#define SMC_GET_RX_DP_CTRL(lp) SMC_inl( lp, RX_DP_CTRL )
759#define SMC_SET_RX_DP_CTRL(lp, x) SMC_outl( x, lp, RX_DP_CTRL )
760#define SMC_GET_PMT_CTRL(lp) SMC_inl( lp, PMT_CTRL )
761#define SMC_SET_PMT_CTRL(lp, x) SMC_outl( x, lp, PMT_CTRL )
762#define SMC_GET_GPIO_CFG(lp) SMC_inl( lp, GPIO_CFG )
763#define SMC_SET_GPIO_CFG(lp, x) SMC_outl( x, lp, GPIO_CFG )
764#define SMC_GET_RX_FIFO_INF(lp) SMC_inl( lp, RX_FIFO_INF )
765#define SMC_SET_RX_FIFO_INF(lp, x) SMC_outl( x, lp, RX_FIFO_INF )
766#define SMC_GET_TX_FIFO_INF(lp) SMC_inl( lp, TX_FIFO_INF )
767#define SMC_SET_TX_FIFO_INF(lp, x) SMC_outl( x, lp, TX_FIFO_INF )
768#define SMC_GET_GPT_CFG(lp) SMC_inl( lp, GPT_CFG )
769#define SMC_SET_GPT_CFG(lp, x) SMC_outl( x, lp, GPT_CFG )
770#define SMC_GET_RX_DROP(lp) SMC_inl( lp, RX_DROP )
771#define SMC_SET_RX_DROP(lp, x) SMC_outl( x, lp, RX_DROP )
772#define SMC_GET_MAC_CMD(lp) SMC_inl( lp, MAC_CSR_CMD )
773#define SMC_SET_MAC_CMD(lp, x) SMC_outl( x, lp, MAC_CSR_CMD )
774#define SMC_GET_MAC_DATA(lp) SMC_inl( lp, MAC_CSR_DATA )
775#define SMC_SET_MAC_DATA(lp, x) SMC_outl( x, lp, MAC_CSR_DATA )
776#define SMC_GET_AFC_CFG(lp) SMC_inl( lp, AFC_CFG )
777#define SMC_SET_AFC_CFG(lp, x) SMC_outl( x, lp, AFC_CFG )
778#define SMC_GET_E2P_CMD(lp) SMC_inl( lp, E2P_CMD )
779#define SMC_SET_E2P_CMD(lp, x) SMC_outl( x, lp, E2P_CMD )
780#define SMC_GET_E2P_DATA(lp) SMC_inl( lp, E2P_DATA )
781#define SMC_SET_E2P_DATA(lp, x) SMC_outl( x, lp, E2P_DATA )
0a0c72c9
DM		 782
783/* MAC register read/write macros */
699559f8 784#define SMC_GET_MAC_CSR(lp,a,v) \
0a0c72c9 785 do { \
699559f8
MD		 786 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
787 SMC_SET_MAC_CMD((lp),MAC_CSR_CMD_CSR_BUSY_ | \
0a0c72c9 788 MAC_CSR_CMD_R_NOT_W_ | (a) ); \
699559f8
MD		 789 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
790 v = SMC_GET_MAC_DATA((lp)); \
0a0c72c9 791 } while (0)
699559f8 792#define SMC_SET_MAC_CSR(lp,a,v) \
0a0c72c9 793 do { \
699559f8
MD		 794 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
795 SMC_SET_MAC_DATA((lp), v); \
796 SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_CSR_BUSY_ | (a) ); \
797 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
0a0c72c9 798 } while (0)
699559f8
MD		 799#define SMC_GET_MAC_CR(lp, x) SMC_GET_MAC_CSR( (lp), MAC_CR, x )
800#define SMC_SET_MAC_CR(lp, x) SMC_SET_MAC_CSR( (lp), MAC_CR, x )
801#define SMC_GET_ADDRH(lp, x) SMC_GET_MAC_CSR( (lp), ADDRH, x )
802#define SMC_SET_ADDRH(lp, x) SMC_SET_MAC_CSR( (lp), ADDRH, x )
803#define SMC_GET_ADDRL(lp, x) SMC_GET_MAC_CSR( (lp), ADDRL, x )
804#define SMC_SET_ADDRL(lp, x) SMC_SET_MAC_CSR( (lp), ADDRL, x )
805#define SMC_GET_HASHH(lp, x) SMC_GET_MAC_CSR( (lp), HASHH, x )
806#define SMC_SET_HASHH(lp, x) SMC_SET_MAC_CSR( (lp), HASHH, x )
807#define SMC_GET_HASHL(lp, x) SMC_GET_MAC_CSR( (lp), HASHL, x )
808#define SMC_SET_HASHL(lp, x) SMC_SET_MAC_CSR( (lp), HASHL, x )
809#define SMC_GET_MII_ACC(lp, x) SMC_GET_MAC_CSR( (lp), MII_ACC, x )
810#define SMC_SET_MII_ACC(lp, x) SMC_SET_MAC_CSR( (lp), MII_ACC, x )
811#define SMC_GET_MII_DATA(lp, x) SMC_GET_MAC_CSR( (lp), MII_DATA, x )
812#define SMC_SET_MII_DATA(lp, x) SMC_SET_MAC_CSR( (lp), MII_DATA, x )
813#define SMC_GET_FLOW(lp, x) SMC_GET_MAC_CSR( (lp), FLOW, x )
814#define SMC_SET_FLOW(lp, x) SMC_SET_MAC_CSR( (lp), FLOW, x )
815#define SMC_GET_VLAN1(lp, x) SMC_GET_MAC_CSR( (lp), VLAN1, x )
816#define SMC_SET_VLAN1(lp, x) SMC_SET_MAC_CSR( (lp), VLAN1, x )
817#define SMC_GET_VLAN2(lp, x) SMC_GET_MAC_CSR( (lp), VLAN2, x )
818#define SMC_SET_VLAN2(lp, x) SMC_SET_MAC_CSR( (lp), VLAN2, x )
819#define SMC_SET_WUFF(lp, x) SMC_SET_MAC_CSR( (lp), WUFF, x )
820#define SMC_GET_WUCSR(lp, x) SMC_GET_MAC_CSR( (lp), WUCSR, x )
821#define SMC_SET_WUCSR(lp, x) SMC_SET_MAC_CSR( (lp), WUCSR, x )
0a0c72c9
DM		 822
823/* PHY register read/write macros */
699559f8 824#define SMC_GET_MII(lp,a,phy,v) \
0a0c72c9
DM		 825 do { \
826 u32 __v; \
827 do { \
699559f8 828 SMC_GET_MII_ACC((lp), __v); \
0a0c72c9 829 } while ( __v & MII_ACC_MII_BUSY_ ); \
699559f8 830 SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
0a0c72c9
DM		 831 MII_ACC_MII_BUSY_); \
832 do { \
699559f8 833 SMC_GET_MII_ACC( (lp), __v); \
0a0c72c9 834 } while ( __v & MII_ACC_MII_BUSY_ ); \
699559f8 835 SMC_GET_MII_DATA((lp), v); \
0a0c72c9 836 } while (0)
699559f8 837#define SMC_SET_MII(lp,a,phy,v) \
0a0c72c9
DM		 838 do { \
839 u32 __v; \
840 do { \
699559f8 841 SMC_GET_MII_ACC((lp), __v); \
0a0c72c9 842 } while ( __v & MII_ACC_MII_BUSY_ ); \
699559f8
MD		 843 SMC_SET_MII_DATA((lp), v); \
844 SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
0a0c72c9
DM		 845 MII_ACC_MII_BUSY_ | \
846 MII_ACC_MII_WRITE_ ); \
847 do { \
699559f8 848 SMC_GET_MII_ACC((lp), __v); \
0a0c72c9
DM		 849 } while ( __v & MII_ACC_MII_BUSY_ ); \
850 } while (0)
699559f8
MD		 851#define SMC_GET_PHY_BMCR(lp,phy,x) SMC_GET_MII( (lp), MII_BMCR, phy, x )
852#define SMC_SET_PHY_BMCR(lp,phy,x) SMC_SET_MII( (lp), MII_BMCR, phy, x )
853#define SMC_GET_PHY_BMSR(lp,phy,x) SMC_GET_MII( (lp), MII_BMSR, phy, x )
854#define SMC_GET_PHY_ID1(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID1, phy, x )
855#define SMC_GET_PHY_ID2(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID2, phy, x )
856#define SMC_GET_PHY_MII_ADV(lp,phy,x) SMC_GET_MII( (lp), MII_ADVERTISE, phy, x )
857#define SMC_SET_PHY_MII_ADV(lp,phy,x) SMC_SET_MII( (lp), MII_ADVERTISE, phy, x )
858#define SMC_GET_PHY_MII_LPA(lp,phy,x) SMC_GET_MII( (lp), MII_LPA, phy, x )
859#define SMC_SET_PHY_MII_LPA(lp,phy,x) SMC_SET_MII( (lp), MII_LPA, phy, x )
860#define SMC_GET_PHY_CTRL_STS(lp,phy,x) SMC_GET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
861#define SMC_SET_PHY_CTRL_STS(lp,phy,x) SMC_SET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
862#define SMC_GET_PHY_INT_SRC(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_SRC, phy, x )
863#define SMC_SET_PHY_INT_SRC(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_SRC, phy, x )
864#define SMC_GET_PHY_INT_MASK(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_MASK, phy, x )
865#define SMC_SET_PHY_INT_MASK(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_MASK, phy, x )
866#define SMC_GET_PHY_SPECIAL(lp,phy,x) SMC_GET_MII( (lp), PHY_SPECIAL, phy, x )
0a0c72c9
DM		 867
868
869
870/* Misc read/write macros */
871
872#ifndef SMC_GET_MAC_ADDR
699559f8 873#define SMC_GET_MAC_ADDR(lp, addr) \
0a0c72c9
DM		 874 do { \
875 unsigned int __v; \
876 \
699559f8 877 SMC_GET_MAC_CSR((lp), ADDRL, __v); \
0a0c72c9
DM		 878 addr[0] = __v; addr[1] = __v >> 8; \
879 addr[2] = __v >> 16; addr[3] = __v >> 24; \
699559f8 880 SMC_GET_MAC_CSR((lp), ADDRH, __v); \
0a0c72c9
DM		 881 addr[4] = __v; addr[5] = __v >> 8; \
882 } while (0)
883#endif
884
699559f8 885#define SMC_SET_MAC_ADDR(lp, addr) \
0a0c72c9 886 do { \
699559f8 887 SMC_SET_MAC_CSR((lp), ADDRL, \
0a0c72c9
DM		 888 addr[0] | \
889 (addr[1] << 8) | \
890 (addr[2] << 16) | \
891 (addr[3] << 24)); \
699559f8 892 SMC_SET_MAC_CSR((lp), ADDRH, addr[4]|(addr[5] << 8));\
0a0c72c9
DM		 893 } while (0)
894
895
699559f8 896#define SMC_WRITE_EEPROM_CMD(lp, cmd, addr) \
0a0c72c9 897 do { \
699559f8
MD		 898 while (SMC_GET_E2P_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
899 SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_R_NOT_W_ | a ); \
900 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
0a0c72c9
DM		 901 } while (0)
902
903#endif /* _SMC911X_H_ */
Linux kernel - Deliverables
This page took 0.535027 seconds and 5 git commands to generate.