Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * smc91x.c | |
3 | * This is a driver for SMSC's 91C9x/91C1xx single-chip Ethernet devices. | |
4 | * | |
5 | * Copyright (C) 1996 by Erik Stahlman | |
6 | * Copyright (C) 2001 Standard Microsystems Corporation | |
7 | * Developed by Simple Network Magic Corporation | |
8 | * Copyright (C) 2003 Monta Vista Software, Inc. | |
9 | * Unified SMC91x driver by Nicolas Pitre | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
24 | * | |
25 | * Arguments: | |
26 | * io = for the base address | |
27 | * irq = for the IRQ | |
28 | * nowait = 0 for normal wait states, 1 eliminates additional wait states | |
29 | * | |
30 | * original author: | |
31 | * Erik Stahlman <erik@vt.edu> | |
32 | * | |
33 | * hardware multicast code: | |
34 | * Peter Cammaert <pc@denkart.be> | |
35 | * | |
36 | * contributors: | |
37 | * Daris A Nevil <dnevil@snmc.com> | |
2f82af08 | 38 | * Nicolas Pitre <nico@fluxnic.net> |
1da177e4 LT |
39 | * Russell King <rmk@arm.linux.org.uk> |
40 | * | |
41 | * History: | |
42 | * 08/20/00 Arnaldo Melo fix kfree(skb) in smc_hardware_send_packet | |
43 | * 12/15/00 Christian Jullien fix "Warning: kfree_skb on hard IRQ" | |
44 | * 03/16/01 Daris A Nevil modified smc9194.c for use with LAN91C111 | |
45 | * 08/22/01 Scott Anderson merge changes from smc9194 to smc91111 | |
46 | * 08/21/01 Pramod B Bhardwaj added support for RevB of LAN91C111 | |
47 | * 12/20/01 Jeff Sutherland initial port to Xscale PXA with DMA support | |
48 | * 04/07/03 Nicolas Pitre unified SMC91x driver, killed irq races, | |
49 | * more bus abstraction, big cleanup, etc. | |
50 | * 29/09/03 Russell King - add driver model support | |
51 | * - ethtool support | |
52 | * - convert to use generic MII interface | |
53 | * - add link up/down notification | |
54 | * - don't try to handle full negotiation in | |
55 | * smc_phy_configure | |
56 | * - clean up (and fix stack overrun) in PHY | |
57 | * MII read/write functions | |
58 | * 22/09/04 Nicolas Pitre big update (see commit log for details) | |
59 | */ | |
60 | static const char version[] = | |
2f82af08 | 61 | "smc91x.c: v1.1, sep 22 2004 by Nicolas Pitre <nico@fluxnic.net>\n"; |
1da177e4 LT |
62 | |
63 | /* Debugging level */ | |
64 | #ifndef SMC_DEBUG | |
65 | #define SMC_DEBUG 0 | |
66 | #endif | |
67 | ||
68 | ||
1da177e4 LT |
69 | #include <linux/init.h> |
70 | #include <linux/module.h> | |
71 | #include <linux/kernel.h> | |
72 | #include <linux/sched.h> | |
1da177e4 LT |
73 | #include <linux/delay.h> |
74 | #include <linux/interrupt.h> | |
75 | #include <linux/errno.h> | |
76 | #include <linux/ioport.h> | |
77 | #include <linux/crc32.h> | |
d052d1be | 78 | #include <linux/platform_device.h> |
1da177e4 LT |
79 | #include <linux/spinlock.h> |
80 | #include <linux/ethtool.h> | |
81 | #include <linux/mii.h> | |
82 | #include <linux/workqueue.h> | |
83 | ||
84 | #include <linux/netdevice.h> | |
85 | #include <linux/etherdevice.h> | |
86 | #include <linux/skbuff.h> | |
87 | ||
88 | #include <asm/io.h> | |
1da177e4 LT |
89 | |
90 | #include "smc91x.h" | |
91 | ||
1da177e4 LT |
92 | #ifndef SMC_NOWAIT |
93 | # define SMC_NOWAIT 0 | |
94 | #endif | |
95 | static int nowait = SMC_NOWAIT; | |
96 | module_param(nowait, int, 0400); | |
97 | MODULE_PARM_DESC(nowait, "set to 1 for no wait state"); | |
98 | ||
99 | /* | |
100 | * Transmit timeout, default 5 seconds. | |
101 | */ | |
ea937560 | 102 | static int watchdog = 1000; |
1da177e4 LT |
103 | module_param(watchdog, int, 0400); |
104 | MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); | |
105 | ||
106 | MODULE_LICENSE("GPL"); | |
72abb461 | 107 | MODULE_ALIAS("platform:smc91x"); |
1da177e4 LT |
108 | |
109 | /* | |
110 | * The internal workings of the driver. If you are changing anything | |
111 | * here with the SMC stuff, you should have the datasheet and know | |
112 | * what you are doing. | |
113 | */ | |
114 | #define CARDNAME "smc91x" | |
115 | ||
116 | /* | |
117 | * Use power-down feature of the chip | |
118 | */ | |
119 | #define POWER_DOWN 1 | |
120 | ||
121 | /* | |
122 | * Wait time for memory to be free. This probably shouldn't be | |
123 | * tuned that much, as waiting for this means nothing else happens | |
124 | * in the system | |
125 | */ | |
126 | #define MEMORY_WAIT_TIME 16 | |
127 | ||
5d0571d9 NP |
128 | /* |
129 | * The maximum number of processing loops allowed for each call to the | |
6aa20a22 | 130 | * IRQ handler. |
5d0571d9 NP |
131 | */ |
132 | #define MAX_IRQ_LOOPS 8 | |
133 | ||
1da177e4 LT |
134 | /* |
135 | * This selects whether TX packets are sent one by one to the SMC91x internal | |
136 | * memory and throttled until transmission completes. This may prevent | |
137 | * RX overruns a litle by keeping much of the memory free for RX packets | |
138 | * but to the expense of reduced TX throughput and increased IRQ overhead. | |
139 | * Note this is not a cure for a too slow data bus or too high IRQ latency. | |
140 | */ | |
141 | #define THROTTLE_TX_PKTS 0 | |
142 | ||
143 | /* | |
144 | * The MII clock high/low times. 2x this number gives the MII clock period | |
145 | * in microseconds. (was 50, but this gives 6.4ms for each MII transaction!) | |
146 | */ | |
147 | #define MII_DELAY 1 | |
148 | ||
1da177e4 LT |
149 | #if SMC_DEBUG > 0 |
150 | #define DBG(n, args...) \ | |
151 | do { \ | |
152 | if (SMC_DEBUG >= (n)) \ | |
153 | printk(args); \ | |
154 | } while (0) | |
155 | ||
156 | #define PRINTK(args...) printk(args) | |
157 | #else | |
158 | #define DBG(n, args...) do { } while(0) | |
159 | #define PRINTK(args...) printk(KERN_DEBUG args) | |
160 | #endif | |
161 | ||
162 | #if SMC_DEBUG > 3 | |
163 | static void PRINT_PKT(u_char *buf, int length) | |
164 | { | |
165 | int i; | |
166 | int remainder; | |
167 | int lines; | |
168 | ||
169 | lines = length / 16; | |
170 | remainder = length % 16; | |
171 | ||
172 | for (i = 0; i < lines ; i ++) { | |
173 | int cur; | |
174 | for (cur = 0; cur < 8; cur++) { | |
175 | u_char a, b; | |
176 | a = *buf++; | |
177 | b = *buf++; | |
178 | printk("%02x%02x ", a, b); | |
179 | } | |
180 | printk("\n"); | |
181 | } | |
182 | for (i = 0; i < remainder/2 ; i++) { | |
183 | u_char a, b; | |
184 | a = *buf++; | |
185 | b = *buf++; | |
186 | printk("%02x%02x ", a, b); | |
187 | } | |
188 | printk("\n"); | |
189 | } | |
190 | #else | |
191 | #define PRINT_PKT(x...) do { } while(0) | |
192 | #endif | |
193 | ||
194 | ||
195 | /* this enables an interrupt in the interrupt mask register */ | |
cfdfa865 | 196 | #define SMC_ENABLE_INT(lp, x) do { \ |
1da177e4 | 197 | unsigned char mask; \ |
8ff499e4 DD |
198 | unsigned long smc_enable_flags; \ |
199 | spin_lock_irqsave(&lp->lock, smc_enable_flags); \ | |
cfdfa865 | 200 | mask = SMC_GET_INT_MASK(lp); \ |
1da177e4 | 201 | mask |= (x); \ |
cfdfa865 | 202 | SMC_SET_INT_MASK(lp, mask); \ |
8ff499e4 | 203 | spin_unlock_irqrestore(&lp->lock, smc_enable_flags); \ |
1da177e4 LT |
204 | } while (0) |
205 | ||
206 | /* this disables an interrupt from the interrupt mask register */ | |
cfdfa865 | 207 | #define SMC_DISABLE_INT(lp, x) do { \ |
1da177e4 | 208 | unsigned char mask; \ |
8ff499e4 DD |
209 | unsigned long smc_disable_flags; \ |
210 | spin_lock_irqsave(&lp->lock, smc_disable_flags); \ | |
cfdfa865 | 211 | mask = SMC_GET_INT_MASK(lp); \ |
1da177e4 | 212 | mask &= ~(x); \ |
cfdfa865 | 213 | SMC_SET_INT_MASK(lp, mask); \ |
8ff499e4 | 214 | spin_unlock_irqrestore(&lp->lock, smc_disable_flags); \ |
1da177e4 LT |
215 | } while (0) |
216 | ||
217 | /* | |
218 | * Wait while MMU is busy. This is usually in the order of a few nanosecs | |
219 | * if at all, but let's avoid deadlocking the system if the hardware | |
220 | * decides to go south. | |
221 | */ | |
cfdfa865 MD |
222 | #define SMC_WAIT_MMU_BUSY(lp) do { \ |
223 | if (unlikely(SMC_GET_MMU_CMD(lp) & MC_BUSY)) { \ | |
1da177e4 | 224 | unsigned long timeout = jiffies + 2; \ |
cfdfa865 | 225 | while (SMC_GET_MMU_CMD(lp) & MC_BUSY) { \ |
1da177e4 LT |
226 | if (time_after(jiffies, timeout)) { \ |
227 | printk("%s: timeout %s line %d\n", \ | |
228 | dev->name, __FILE__, __LINE__); \ | |
229 | break; \ | |
230 | } \ | |
231 | cpu_relax(); \ | |
232 | } \ | |
233 | } \ | |
234 | } while (0) | |
235 | ||
236 | ||
237 | /* | |
238 | * this does a soft reset on the device | |
239 | */ | |
240 | static void smc_reset(struct net_device *dev) | |
241 | { | |
242 | struct smc_local *lp = netdev_priv(dev); | |
243 | void __iomem *ioaddr = lp->base; | |
244 | unsigned int ctl, cfg; | |
be83668a | 245 | struct sk_buff *pending_skb; |
1da177e4 | 246 | |
b39d66a8 | 247 | DBG(2, "%s: %s\n", dev->name, __func__); |
1da177e4 | 248 | |
be83668a | 249 | /* Disable all interrupts, block TX tasklet */ |
76cb4fe7 | 250 | spin_lock_irq(&lp->lock); |
cfdfa865 MD |
251 | SMC_SELECT_BANK(lp, 2); |
252 | SMC_SET_INT_MASK(lp, 0); | |
be83668a NP |
253 | pending_skb = lp->pending_tx_skb; |
254 | lp->pending_tx_skb = NULL; | |
76cb4fe7 | 255 | spin_unlock_irq(&lp->lock); |
1da177e4 | 256 | |
be83668a NP |
257 | /* free any pending tx skb */ |
258 | if (pending_skb) { | |
259 | dev_kfree_skb(pending_skb); | |
09f75cd7 JG |
260 | dev->stats.tx_errors++; |
261 | dev->stats.tx_aborted_errors++; | |
be83668a NP |
262 | } |
263 | ||
1da177e4 LT |
264 | /* |
265 | * This resets the registers mostly to defaults, but doesn't | |
266 | * affect EEPROM. That seems unnecessary | |
267 | */ | |
cfdfa865 MD |
268 | SMC_SELECT_BANK(lp, 0); |
269 | SMC_SET_RCR(lp, RCR_SOFTRST); | |
1da177e4 LT |
270 | |
271 | /* | |
272 | * Setup the Configuration Register | |
273 | * This is necessary because the CONFIG_REG is not affected | |
274 | * by a soft reset | |
275 | */ | |
cfdfa865 | 276 | SMC_SELECT_BANK(lp, 1); |
1da177e4 LT |
277 | |
278 | cfg = CONFIG_DEFAULT; | |
279 | ||
280 | /* | |
281 | * Setup for fast accesses if requested. If the card/system | |
282 | * can't handle it then there will be no recovery except for | |
283 | * a hard reset or power cycle | |
284 | */ | |
c4f0e767 | 285 | if (lp->cfg.flags & SMC91X_NOWAIT) |
1da177e4 LT |
286 | cfg |= CONFIG_NO_WAIT; |
287 | ||
288 | /* | |
289 | * Release from possible power-down state | |
290 | * Configuration register is not affected by Soft Reset | |
291 | */ | |
292 | cfg |= CONFIG_EPH_POWER_EN; | |
293 | ||
cfdfa865 | 294 | SMC_SET_CONFIG(lp, cfg); |
1da177e4 LT |
295 | |
296 | /* this should pause enough for the chip to be happy */ | |
297 | /* | |
298 | * elaborate? What does the chip _need_? --jgarzik | |
299 | * | |
300 | * This seems to be undocumented, but something the original | |
301 | * driver(s) have always done. Suspect undocumented timing | |
302 | * info/determined empirically. --rmk | |
303 | */ | |
304 | udelay(1); | |
305 | ||
306 | /* Disable transmit and receive functionality */ | |
cfdfa865 MD |
307 | SMC_SELECT_BANK(lp, 0); |
308 | SMC_SET_RCR(lp, RCR_CLEAR); | |
309 | SMC_SET_TCR(lp, TCR_CLEAR); | |
1da177e4 | 310 | |
cfdfa865 MD |
311 | SMC_SELECT_BANK(lp, 1); |
312 | ctl = SMC_GET_CTL(lp) | CTL_LE_ENABLE; | |
1da177e4 LT |
313 | |
314 | /* | |
315 | * Set the control register to automatically release successfully | |
316 | * transmitted packets, to make the best use out of our limited | |
317 | * memory | |
318 | */ | |
319 | if(!THROTTLE_TX_PKTS) | |
320 | ctl |= CTL_AUTO_RELEASE; | |
321 | else | |
322 | ctl &= ~CTL_AUTO_RELEASE; | |
cfdfa865 | 323 | SMC_SET_CTL(lp, ctl); |
1da177e4 LT |
324 | |
325 | /* Reset the MMU */ | |
cfdfa865 MD |
326 | SMC_SELECT_BANK(lp, 2); |
327 | SMC_SET_MMU_CMD(lp, MC_RESET); | |
328 | SMC_WAIT_MMU_BUSY(lp); | |
1da177e4 LT |
329 | } |
330 | ||
331 | /* | |
332 | * Enable Interrupts, Receive, and Transmit | |
333 | */ | |
334 | static void smc_enable(struct net_device *dev) | |
335 | { | |
336 | struct smc_local *lp = netdev_priv(dev); | |
337 | void __iomem *ioaddr = lp->base; | |
338 | int mask; | |
339 | ||
b39d66a8 | 340 | DBG(2, "%s: %s\n", dev->name, __func__); |
1da177e4 LT |
341 | |
342 | /* see the header file for options in TCR/RCR DEFAULT */ | |
cfdfa865 MD |
343 | SMC_SELECT_BANK(lp, 0); |
344 | SMC_SET_TCR(lp, lp->tcr_cur_mode); | |
345 | SMC_SET_RCR(lp, lp->rcr_cur_mode); | |
1da177e4 | 346 | |
cfdfa865 MD |
347 | SMC_SELECT_BANK(lp, 1); |
348 | SMC_SET_MAC_ADDR(lp, dev->dev_addr); | |
1da177e4 LT |
349 | |
350 | /* now, enable interrupts */ | |
351 | mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT; | |
352 | if (lp->version >= (CHIP_91100 << 4)) | |
353 | mask |= IM_MDINT; | |
cfdfa865 MD |
354 | SMC_SELECT_BANK(lp, 2); |
355 | SMC_SET_INT_MASK(lp, mask); | |
1da177e4 LT |
356 | |
357 | /* | |
358 | * From this point the register bank must _NOT_ be switched away | |
359 | * to something else than bank 2 without proper locking against | |
360 | * races with any tasklet or interrupt handlers until smc_shutdown() | |
361 | * or smc_reset() is called. | |
362 | */ | |
363 | } | |
364 | ||
365 | /* | |
366 | * this puts the device in an inactive state | |
367 | */ | |
368 | static void smc_shutdown(struct net_device *dev) | |
369 | { | |
370 | struct smc_local *lp = netdev_priv(dev); | |
371 | void __iomem *ioaddr = lp->base; | |
be83668a | 372 | struct sk_buff *pending_skb; |
1da177e4 | 373 | |
b39d66a8 | 374 | DBG(2, "%s: %s\n", CARDNAME, __func__); |
1da177e4 LT |
375 | |
376 | /* no more interrupts for me */ | |
76cb4fe7 | 377 | spin_lock_irq(&lp->lock); |
cfdfa865 MD |
378 | SMC_SELECT_BANK(lp, 2); |
379 | SMC_SET_INT_MASK(lp, 0); | |
be83668a NP |
380 | pending_skb = lp->pending_tx_skb; |
381 | lp->pending_tx_skb = NULL; | |
76cb4fe7 | 382 | spin_unlock_irq(&lp->lock); |
be83668a NP |
383 | if (pending_skb) |
384 | dev_kfree_skb(pending_skb); | |
1da177e4 LT |
385 | |
386 | /* and tell the card to stay away from that nasty outside world */ | |
cfdfa865 MD |
387 | SMC_SELECT_BANK(lp, 0); |
388 | SMC_SET_RCR(lp, RCR_CLEAR); | |
389 | SMC_SET_TCR(lp, TCR_CLEAR); | |
1da177e4 LT |
390 | |
391 | #ifdef POWER_DOWN | |
392 | /* finally, shut the chip down */ | |
cfdfa865 MD |
393 | SMC_SELECT_BANK(lp, 1); |
394 | SMC_SET_CONFIG(lp, SMC_GET_CONFIG(lp) & ~CONFIG_EPH_POWER_EN); | |
1da177e4 LT |
395 | #endif |
396 | } | |
397 | ||
398 | /* | |
399 | * This is the procedure to handle the receipt of a packet. | |
400 | */ | |
401 | static inline void smc_rcv(struct net_device *dev) | |
402 | { | |
403 | struct smc_local *lp = netdev_priv(dev); | |
404 | void __iomem *ioaddr = lp->base; | |
405 | unsigned int packet_number, status, packet_len; | |
406 | ||
b39d66a8 | 407 | DBG(3, "%s: %s\n", dev->name, __func__); |
1da177e4 | 408 | |
cfdfa865 | 409 | packet_number = SMC_GET_RXFIFO(lp); |
1da177e4 LT |
410 | if (unlikely(packet_number & RXFIFO_REMPTY)) { |
411 | PRINTK("%s: smc_rcv with nothing on FIFO.\n", dev->name); | |
412 | return; | |
413 | } | |
414 | ||
415 | /* read from start of packet */ | |
cfdfa865 | 416 | SMC_SET_PTR(lp, PTR_READ | PTR_RCV | PTR_AUTOINC); |
1da177e4 LT |
417 | |
418 | /* First two words are status and packet length */ | |
cfdfa865 | 419 | SMC_GET_PKT_HDR(lp, status, packet_len); |
1da177e4 LT |
420 | packet_len &= 0x07ff; /* mask off top bits */ |
421 | DBG(2, "%s: RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n", | |
422 | dev->name, packet_number, status, | |
423 | packet_len, packet_len); | |
424 | ||
425 | back: | |
426 | if (unlikely(packet_len < 6 || status & RS_ERRORS)) { | |
427 | if (status & RS_TOOLONG && packet_len <= (1514 + 4 + 6)) { | |
428 | /* accept VLAN packets */ | |
429 | status &= ~RS_TOOLONG; | |
430 | goto back; | |
431 | } | |
432 | if (packet_len < 6) { | |
433 | /* bloody hardware */ | |
434 | printk(KERN_ERR "%s: fubar (rxlen %u status %x\n", | |
435 | dev->name, packet_len, status); | |
436 | status |= RS_TOOSHORT; | |
437 | } | |
cfdfa865 MD |
438 | SMC_WAIT_MMU_BUSY(lp); |
439 | SMC_SET_MMU_CMD(lp, MC_RELEASE); | |
09f75cd7 | 440 | dev->stats.rx_errors++; |
1da177e4 | 441 | if (status & RS_ALGNERR) |
09f75cd7 | 442 | dev->stats.rx_frame_errors++; |
1da177e4 | 443 | if (status & (RS_TOOSHORT | RS_TOOLONG)) |
09f75cd7 | 444 | dev->stats.rx_length_errors++; |
1da177e4 | 445 | if (status & RS_BADCRC) |
09f75cd7 | 446 | dev->stats.rx_crc_errors++; |
1da177e4 LT |
447 | } else { |
448 | struct sk_buff *skb; | |
449 | unsigned char *data; | |
450 | unsigned int data_len; | |
451 | ||
452 | /* set multicast stats */ | |
453 | if (status & RS_MULTICAST) | |
09f75cd7 | 454 | dev->stats.multicast++; |
1da177e4 LT |
455 | |
456 | /* | |
457 | * Actual payload is packet_len - 6 (or 5 if odd byte). | |
458 | * We want skb_reserve(2) and the final ctrl word | |
459 | * (2 bytes, possibly containing the payload odd byte). | |
460 | * Furthermore, we add 2 bytes to allow rounding up to | |
461 | * multiple of 4 bytes on 32 bit buses. | |
462 | * Hence packet_len - 6 + 2 + 2 + 2. | |
463 | */ | |
464 | skb = dev_alloc_skb(packet_len); | |
465 | if (unlikely(skb == NULL)) { | |
466 | printk(KERN_NOTICE "%s: Low memory, packet dropped.\n", | |
467 | dev->name); | |
cfdfa865 MD |
468 | SMC_WAIT_MMU_BUSY(lp); |
469 | SMC_SET_MMU_CMD(lp, MC_RELEASE); | |
09f75cd7 | 470 | dev->stats.rx_dropped++; |
1da177e4 LT |
471 | return; |
472 | } | |
473 | ||
474 | /* Align IP header to 32 bits */ | |
475 | skb_reserve(skb, 2); | |
476 | ||
477 | /* BUG: the LAN91C111 rev A never sets this bit. Force it. */ | |
478 | if (lp->version == 0x90) | |
479 | status |= RS_ODDFRAME; | |
480 | ||
481 | /* | |
482 | * If odd length: packet_len - 5, | |
483 | * otherwise packet_len - 6. | |
484 | * With the trailing ctrl byte it's packet_len - 4. | |
485 | */ | |
486 | data_len = packet_len - ((status & RS_ODDFRAME) ? 5 : 6); | |
487 | data = skb_put(skb, data_len); | |
cfdfa865 | 488 | SMC_PULL_DATA(lp, data, packet_len - 4); |
1da177e4 | 489 | |
cfdfa865 MD |
490 | SMC_WAIT_MMU_BUSY(lp); |
491 | SMC_SET_MMU_CMD(lp, MC_RELEASE); | |
1da177e4 LT |
492 | |
493 | PRINT_PKT(data, packet_len - 4); | |
494 | ||
1da177e4 LT |
495 | skb->protocol = eth_type_trans(skb, dev); |
496 | netif_rx(skb); | |
09f75cd7 JG |
497 | dev->stats.rx_packets++; |
498 | dev->stats.rx_bytes += data_len; | |
1da177e4 LT |
499 | } |
500 | } | |
501 | ||
502 | #ifdef CONFIG_SMP | |
503 | /* | |
504 | * On SMP we have the following problem: | |
505 | * | |
506 | * A = smc_hardware_send_pkt() | |
507 | * B = smc_hard_start_xmit() | |
508 | * C = smc_interrupt() | |
509 | * | |
510 | * A and B can never be executed simultaneously. However, at least on UP, | |
511 | * it is possible (and even desirable) for C to interrupt execution of | |
512 | * A or B in order to have better RX reliability and avoid overruns. | |
513 | * C, just like A and B, must have exclusive access to the chip and | |
514 | * each of them must lock against any other concurrent access. | |
515 | * Unfortunately this is not possible to have C suspend execution of A or | |
516 | * B taking place on another CPU. On UP this is no an issue since A and B | |
517 | * are run from softirq context and C from hard IRQ context, and there is | |
518 | * no other CPU where concurrent access can happen. | |
519 | * If ever there is a way to force at least B and C to always be executed | |
520 | * on the same CPU then we could use read/write locks to protect against | |
521 | * any other concurrent access and C would always interrupt B. But life | |
522 | * isn't that easy in a SMP world... | |
523 | */ | |
8ff499e4 | 524 | #define smc_special_trylock(lock, flags) \ |
1da177e4 LT |
525 | ({ \ |
526 | int __ret; \ | |
8ff499e4 | 527 | local_irq_save(flags); \ |
1da177e4 LT |
528 | __ret = spin_trylock(lock); \ |
529 | if (!__ret) \ | |
8ff499e4 | 530 | local_irq_restore(flags); \ |
1da177e4 LT |
531 | __ret; \ |
532 | }) | |
0b4f2928 | 533 | #define smc_special_lock(lock, flags) spin_lock_irqsave(lock, flags) |
8ff499e4 | 534 | #define smc_special_unlock(lock, flags) spin_unlock_irqrestore(lock, flags) |
1da177e4 | 535 | #else |
fd0775bf MF |
536 | #define smc_special_trylock(lock, flags) (flags == flags) |
537 | #define smc_special_lock(lock, flags) do { flags = 0; } while (0) | |
538 | #define smc_special_unlock(lock, flags) do { flags = 0; } while (0) | |
1da177e4 LT |
539 | #endif |
540 | ||
541 | /* | |
542 | * This is called to actually send a packet to the chip. | |
543 | */ | |
544 | static void smc_hardware_send_pkt(unsigned long data) | |
545 | { | |
546 | struct net_device *dev = (struct net_device *)data; | |
547 | struct smc_local *lp = netdev_priv(dev); | |
548 | void __iomem *ioaddr = lp->base; | |
549 | struct sk_buff *skb; | |
550 | unsigned int packet_no, len; | |
551 | unsigned char *buf; | |
8ff499e4 | 552 | unsigned long flags; |
1da177e4 | 553 | |
b39d66a8 | 554 | DBG(3, "%s: %s\n", dev->name, __func__); |
1da177e4 | 555 | |
8ff499e4 | 556 | if (!smc_special_trylock(&lp->lock, flags)) { |
1da177e4 LT |
557 | netif_stop_queue(dev); |
558 | tasklet_schedule(&lp->tx_task); | |
559 | return; | |
560 | } | |
561 | ||
562 | skb = lp->pending_tx_skb; | |
be83668a | 563 | if (unlikely(!skb)) { |
8ff499e4 | 564 | smc_special_unlock(&lp->lock, flags); |
be83668a NP |
565 | return; |
566 | } | |
1da177e4 | 567 | lp->pending_tx_skb = NULL; |
be83668a | 568 | |
cfdfa865 | 569 | packet_no = SMC_GET_AR(lp); |
1da177e4 LT |
570 | if (unlikely(packet_no & AR_FAILED)) { |
571 | printk("%s: Memory allocation failed.\n", dev->name); | |
09f75cd7 JG |
572 | dev->stats.tx_errors++; |
573 | dev->stats.tx_fifo_errors++; | |
8ff499e4 | 574 | smc_special_unlock(&lp->lock, flags); |
1da177e4 LT |
575 | goto done; |
576 | } | |
577 | ||
578 | /* point to the beginning of the packet */ | |
cfdfa865 MD |
579 | SMC_SET_PN(lp, packet_no); |
580 | SMC_SET_PTR(lp, PTR_AUTOINC); | |
1da177e4 LT |
581 | |
582 | buf = skb->data; | |
583 | len = skb->len; | |
584 | DBG(2, "%s: TX PNR 0x%x LENGTH 0x%04x (%d) BUF 0x%p\n", | |
585 | dev->name, packet_no, len, len, buf); | |
586 | PRINT_PKT(buf, len); | |
587 | ||
588 | /* | |
589 | * Send the packet length (+6 for status words, length, and ctl. | |
590 | * The card will pad to 64 bytes with zeroes if packet is too small. | |
591 | */ | |
cfdfa865 | 592 | SMC_PUT_PKT_HDR(lp, 0, len + 6); |
1da177e4 LT |
593 | |
594 | /* send the actual data */ | |
cfdfa865 | 595 | SMC_PUSH_DATA(lp, buf, len & ~1); |
1da177e4 LT |
596 | |
597 | /* Send final ctl word with the last byte if there is one */ | |
cfdfa865 | 598 | SMC_outw(((len & 1) ? (0x2000 | buf[len-1]) : 0), ioaddr, DATA_REG(lp)); |
1da177e4 LT |
599 | |
600 | /* | |
ea937560 NP |
601 | * If THROTTLE_TX_PKTS is set, we stop the queue here. This will |
602 | * have the effect of having at most one packet queued for TX | |
603 | * in the chip's memory at all time. | |
604 | * | |
605 | * If THROTTLE_TX_PKTS is not set then the queue is stopped only | |
606 | * when memory allocation (MC_ALLOC) does not succeed right away. | |
1da177e4 | 607 | */ |
ea937560 | 608 | if (THROTTLE_TX_PKTS) |
1da177e4 LT |
609 | netif_stop_queue(dev); |
610 | ||
611 | /* queue the packet for TX */ | |
cfdfa865 | 612 | SMC_SET_MMU_CMD(lp, MC_ENQUEUE); |
8ff499e4 | 613 | smc_special_unlock(&lp->lock, flags); |
1da177e4 LT |
614 | |
615 | dev->trans_start = jiffies; | |
09f75cd7 JG |
616 | dev->stats.tx_packets++; |
617 | dev->stats.tx_bytes += len; | |
1da177e4 | 618 | |
cfdfa865 | 619 | SMC_ENABLE_INT(lp, IM_TX_INT | IM_TX_EMPTY_INT); |
1da177e4 LT |
620 | |
621 | done: if (!THROTTLE_TX_PKTS) | |
622 | netif_wake_queue(dev); | |
623 | ||
624 | dev_kfree_skb(skb); | |
625 | } | |
626 | ||
627 | /* | |
628 | * Since I am not sure if I will have enough room in the chip's ram | |
629 | * to store the packet, I call this routine which either sends it | |
630 | * now, or set the card to generates an interrupt when ready | |
631 | * for the packet. | |
632 | */ | |
633 | static int smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
634 | { | |
635 | struct smc_local *lp = netdev_priv(dev); | |
636 | void __iomem *ioaddr = lp->base; | |
637 | unsigned int numPages, poll_count, status; | |
8ff499e4 | 638 | unsigned long flags; |
1da177e4 | 639 | |
b39d66a8 | 640 | DBG(3, "%s: %s\n", dev->name, __func__); |
1da177e4 LT |
641 | |
642 | BUG_ON(lp->pending_tx_skb != NULL); | |
1da177e4 LT |
643 | |
644 | /* | |
645 | * The MMU wants the number of pages to be the number of 256 bytes | |
646 | * 'pages', minus 1 (since a packet can't ever have 0 pages :)) | |
647 | * | |
648 | * The 91C111 ignores the size bits, but earlier models don't. | |
649 | * | |
650 | * Pkt size for allocating is data length +6 (for additional status | |
651 | * words, length and ctl) | |
652 | * | |
653 | * If odd size then last byte is included in ctl word. | |
654 | */ | |
655 | numPages = ((skb->len & ~1) + (6 - 1)) >> 8; | |
656 | if (unlikely(numPages > 7)) { | |
657 | printk("%s: Far too big packet error.\n", dev->name); | |
09f75cd7 JG |
658 | dev->stats.tx_errors++; |
659 | dev->stats.tx_dropped++; | |
1da177e4 | 660 | dev_kfree_skb(skb); |
6ed10654 | 661 | return NETDEV_TX_OK; |
1da177e4 LT |
662 | } |
663 | ||
8ff499e4 | 664 | smc_special_lock(&lp->lock, flags); |
1da177e4 LT |
665 | |
666 | /* now, try to allocate the memory */ | |
cfdfa865 | 667 | SMC_SET_MMU_CMD(lp, MC_ALLOC | numPages); |
1da177e4 LT |
668 | |
669 | /* | |
670 | * Poll the chip for a short amount of time in case the | |
671 | * allocation succeeds quickly. | |
672 | */ | |
673 | poll_count = MEMORY_WAIT_TIME; | |
674 | do { | |
cfdfa865 | 675 | status = SMC_GET_INT(lp); |
1da177e4 | 676 | if (status & IM_ALLOC_INT) { |
cfdfa865 | 677 | SMC_ACK_INT(lp, IM_ALLOC_INT); |
1da177e4 LT |
678 | break; |
679 | } | |
680 | } while (--poll_count); | |
681 | ||
8ff499e4 | 682 | smc_special_unlock(&lp->lock, flags); |
1da177e4 | 683 | |
be83668a | 684 | lp->pending_tx_skb = skb; |
1da177e4 LT |
685 | if (!poll_count) { |
686 | /* oh well, wait until the chip finds memory later */ | |
687 | netif_stop_queue(dev); | |
688 | DBG(2, "%s: TX memory allocation deferred.\n", dev->name); | |
cfdfa865 | 689 | SMC_ENABLE_INT(lp, IM_ALLOC_INT); |
1da177e4 LT |
690 | } else { |
691 | /* | |
692 | * Allocation succeeded: push packet to the chip's own memory | |
693 | * immediately. | |
6aa20a22 | 694 | */ |
1da177e4 LT |
695 | smc_hardware_send_pkt((unsigned long)dev); |
696 | } | |
697 | ||
6ed10654 | 698 | return NETDEV_TX_OK; |
1da177e4 LT |
699 | } |
700 | ||
701 | /* | |
702 | * This handles a TX interrupt, which is only called when: | |
703 | * - a TX error occurred, or | |
704 | * - CTL_AUTO_RELEASE is not set and TX of a packet completed. | |
705 | */ | |
706 | static void smc_tx(struct net_device *dev) | |
707 | { | |
708 | struct smc_local *lp = netdev_priv(dev); | |
709 | void __iomem *ioaddr = lp->base; | |
710 | unsigned int saved_packet, packet_no, tx_status, pkt_len; | |
711 | ||
b39d66a8 | 712 | DBG(3, "%s: %s\n", dev->name, __func__); |
1da177e4 LT |
713 | |
714 | /* If the TX FIFO is empty then nothing to do */ | |
cfdfa865 | 715 | packet_no = SMC_GET_TXFIFO(lp); |
1da177e4 LT |
716 | if (unlikely(packet_no & TXFIFO_TEMPTY)) { |
717 | PRINTK("%s: smc_tx with nothing on FIFO.\n", dev->name); | |
718 | return; | |
719 | } | |
720 | ||
721 | /* select packet to read from */ | |
cfdfa865 MD |
722 | saved_packet = SMC_GET_PN(lp); |
723 | SMC_SET_PN(lp, packet_no); | |
1da177e4 LT |
724 | |
725 | /* read the first word (status word) from this packet */ | |
cfdfa865 MD |
726 | SMC_SET_PTR(lp, PTR_AUTOINC | PTR_READ); |
727 | SMC_GET_PKT_HDR(lp, tx_status, pkt_len); | |
1da177e4 LT |
728 | DBG(2, "%s: TX STATUS 0x%04x PNR 0x%02x\n", |
729 | dev->name, tx_status, packet_no); | |
730 | ||
8de90115 | 731 | if (!(tx_status & ES_TX_SUC)) |
09f75cd7 | 732 | dev->stats.tx_errors++; |
8de90115 NP |
733 | |
734 | if (tx_status & ES_LOSTCARR) | |
09f75cd7 | 735 | dev->stats.tx_carrier_errors++; |
1da177e4 | 736 | |
8de90115 NP |
737 | if (tx_status & (ES_LATCOL | ES_16COL)) { |
738 | PRINTK("%s: %s occurred on last xmit\n", dev->name, | |
739 | (tx_status & ES_LATCOL) ? | |
740 | "late collision" : "too many collisions"); | |
09f75cd7 JG |
741 | dev->stats.tx_window_errors++; |
742 | if (!(dev->stats.tx_window_errors & 63) && net_ratelimit()) { | |
8de90115 NP |
743 | printk(KERN_INFO "%s: unexpectedly large number of " |
744 | "bad collisions. Please check duplex " | |
1da177e4 LT |
745 | "setting.\n", dev->name); |
746 | } | |
747 | } | |
748 | ||
749 | /* kill the packet */ | |
cfdfa865 MD |
750 | SMC_WAIT_MMU_BUSY(lp); |
751 | SMC_SET_MMU_CMD(lp, MC_FREEPKT); | |
1da177e4 LT |
752 | |
753 | /* Don't restore Packet Number Reg until busy bit is cleared */ | |
cfdfa865 MD |
754 | SMC_WAIT_MMU_BUSY(lp); |
755 | SMC_SET_PN(lp, saved_packet); | |
1da177e4 LT |
756 | |
757 | /* re-enable transmit */ | |
cfdfa865 MD |
758 | SMC_SELECT_BANK(lp, 0); |
759 | SMC_SET_TCR(lp, lp->tcr_cur_mode); | |
760 | SMC_SELECT_BANK(lp, 2); | |
1da177e4 LT |
761 | } |
762 | ||
763 | ||
764 | /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/ | |
765 | ||
766 | static void smc_mii_out(struct net_device *dev, unsigned int val, int bits) | |
767 | { | |
768 | struct smc_local *lp = netdev_priv(dev); | |
769 | void __iomem *ioaddr = lp->base; | |
770 | unsigned int mii_reg, mask; | |
771 | ||
cfdfa865 | 772 | mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO); |
1da177e4 LT |
773 | mii_reg |= MII_MDOE; |
774 | ||
775 | for (mask = 1 << (bits - 1); mask; mask >>= 1) { | |
776 | if (val & mask) | |
777 | mii_reg |= MII_MDO; | |
778 | else | |
779 | mii_reg &= ~MII_MDO; | |
780 | ||
cfdfa865 | 781 | SMC_SET_MII(lp, mii_reg); |
1da177e4 | 782 | udelay(MII_DELAY); |
cfdfa865 | 783 | SMC_SET_MII(lp, mii_reg | MII_MCLK); |
1da177e4 LT |
784 | udelay(MII_DELAY); |
785 | } | |
786 | } | |
787 | ||
788 | static unsigned int smc_mii_in(struct net_device *dev, int bits) | |
789 | { | |
790 | struct smc_local *lp = netdev_priv(dev); | |
791 | void __iomem *ioaddr = lp->base; | |
792 | unsigned int mii_reg, mask, val; | |
793 | ||
cfdfa865 MD |
794 | mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO); |
795 | SMC_SET_MII(lp, mii_reg); | |
1da177e4 LT |
796 | |
797 | for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) { | |
cfdfa865 | 798 | if (SMC_GET_MII(lp) & MII_MDI) |
1da177e4 LT |
799 | val |= mask; |
800 | ||
cfdfa865 | 801 | SMC_SET_MII(lp, mii_reg); |
1da177e4 | 802 | udelay(MII_DELAY); |
cfdfa865 | 803 | SMC_SET_MII(lp, mii_reg | MII_MCLK); |
1da177e4 LT |
804 | udelay(MII_DELAY); |
805 | } | |
806 | ||
807 | return val; | |
808 | } | |
809 | ||
810 | /* | |
811 | * Reads a register from the MII Management serial interface | |
812 | */ | |
813 | static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg) | |
814 | { | |
815 | struct smc_local *lp = netdev_priv(dev); | |
816 | void __iomem *ioaddr = lp->base; | |
817 | unsigned int phydata; | |
818 | ||
cfdfa865 | 819 | SMC_SELECT_BANK(lp, 3); |
1da177e4 LT |
820 | |
821 | /* Idle - 32 ones */ | |
822 | smc_mii_out(dev, 0xffffffff, 32); | |
823 | ||
824 | /* Start code (01) + read (10) + phyaddr + phyreg */ | |
825 | smc_mii_out(dev, 6 << 10 | phyaddr << 5 | phyreg, 14); | |
826 | ||
827 | /* Turnaround (2bits) + phydata */ | |
828 | phydata = smc_mii_in(dev, 18); | |
829 | ||
830 | /* Return to idle state */ | |
cfdfa865 | 831 | SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO)); |
1da177e4 LT |
832 | |
833 | DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", | |
b39d66a8 | 834 | __func__, phyaddr, phyreg, phydata); |
1da177e4 | 835 | |
cfdfa865 | 836 | SMC_SELECT_BANK(lp, 2); |
1da177e4 LT |
837 | return phydata; |
838 | } | |
839 | ||
840 | /* | |
841 | * Writes a register to the MII Management serial interface | |
842 | */ | |
843 | static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg, | |
844 | int phydata) | |
845 | { | |
846 | struct smc_local *lp = netdev_priv(dev); | |
847 | void __iomem *ioaddr = lp->base; | |
848 | ||
cfdfa865 | 849 | SMC_SELECT_BANK(lp, 3); |
1da177e4 LT |
850 | |
851 | /* Idle - 32 ones */ | |
852 | smc_mii_out(dev, 0xffffffff, 32); | |
853 | ||
854 | /* Start code (01) + write (01) + phyaddr + phyreg + turnaround + phydata */ | |
855 | smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32); | |
856 | ||
857 | /* Return to idle state */ | |
cfdfa865 | 858 | SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO)); |
1da177e4 LT |
859 | |
860 | DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", | |
b39d66a8 | 861 | __func__, phyaddr, phyreg, phydata); |
1da177e4 | 862 | |
cfdfa865 | 863 | SMC_SELECT_BANK(lp, 2); |
1da177e4 LT |
864 | } |
865 | ||
866 | /* | |
867 | * Finds and reports the PHY address | |
868 | */ | |
869 | static void smc_phy_detect(struct net_device *dev) | |
870 | { | |
871 | struct smc_local *lp = netdev_priv(dev); | |
872 | int phyaddr; | |
873 | ||
b39d66a8 | 874 | DBG(2, "%s: %s\n", dev->name, __func__); |
1da177e4 LT |
875 | |
876 | lp->phy_type = 0; | |
877 | ||
878 | /* | |
879 | * Scan all 32 PHY addresses if necessary, starting at | |
880 | * PHY#1 to PHY#31, and then PHY#0 last. | |
881 | */ | |
882 | for (phyaddr = 1; phyaddr < 33; ++phyaddr) { | |
883 | unsigned int id1, id2; | |
884 | ||
885 | /* Read the PHY identifiers */ | |
886 | id1 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID1); | |
887 | id2 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID2); | |
888 | ||
889 | DBG(3, "%s: phy_id1=0x%x, phy_id2=0x%x\n", | |
890 | dev->name, id1, id2); | |
891 | ||
892 | /* Make sure it is a valid identifier */ | |
893 | if (id1 != 0x0000 && id1 != 0xffff && id1 != 0x8000 && | |
894 | id2 != 0x0000 && id2 != 0xffff && id2 != 0x8000) { | |
895 | /* Save the PHY's address */ | |
896 | lp->mii.phy_id = phyaddr & 31; | |
897 | lp->phy_type = id1 << 16 | id2; | |
898 | break; | |
899 | } | |
900 | } | |
901 | } | |
902 | ||
903 | /* | |
904 | * Sets the PHY to a configuration as determined by the user | |
905 | */ | |
906 | static int smc_phy_fixed(struct net_device *dev) | |
907 | { | |
908 | struct smc_local *lp = netdev_priv(dev); | |
909 | void __iomem *ioaddr = lp->base; | |
910 | int phyaddr = lp->mii.phy_id; | |
911 | int bmcr, cfg1; | |
912 | ||
b39d66a8 | 913 | DBG(3, "%s: %s\n", dev->name, __func__); |
1da177e4 LT |
914 | |
915 | /* Enter Link Disable state */ | |
916 | cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG); | |
917 | cfg1 |= PHY_CFG1_LNKDIS; | |
918 | smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1); | |
919 | ||
920 | /* | |
921 | * Set our fixed capabilities | |
922 | * Disable auto-negotiation | |
923 | */ | |
924 | bmcr = 0; | |
925 | ||
926 | if (lp->ctl_rfduplx) | |
927 | bmcr |= BMCR_FULLDPLX; | |
928 | ||
929 | if (lp->ctl_rspeed == 100) | |
930 | bmcr |= BMCR_SPEED100; | |
931 | ||
932 | /* Write our capabilities to the phy control register */ | |
933 | smc_phy_write(dev, phyaddr, MII_BMCR, bmcr); | |
934 | ||
935 | /* Re-Configure the Receive/Phy Control register */ | |
cfdfa865 MD |
936 | SMC_SELECT_BANK(lp, 0); |
937 | SMC_SET_RPC(lp, lp->rpc_cur_mode); | |
938 | SMC_SELECT_BANK(lp, 2); | |
1da177e4 LT |
939 | |
940 | return 1; | |
941 | } | |
942 | ||
943 | /* | |
944 | * smc_phy_reset - reset the phy | |
945 | * @dev: net device | |
946 | * @phy: phy address | |
947 | * | |
948 | * Issue a software reset for the specified PHY and | |
949 | * wait up to 100ms for the reset to complete. We should | |
950 | * not access the PHY for 50ms after issuing the reset. | |
951 | * | |
952 | * The time to wait appears to be dependent on the PHY. | |
953 | * | |
954 | * Must be called with lp->lock locked. | |
955 | */ | |
956 | static int smc_phy_reset(struct net_device *dev, int phy) | |
957 | { | |
958 | struct smc_local *lp = netdev_priv(dev); | |
959 | unsigned int bmcr; | |
960 | int timeout; | |
961 | ||
962 | smc_phy_write(dev, phy, MII_BMCR, BMCR_RESET); | |
963 | ||
964 | for (timeout = 2; timeout; timeout--) { | |
965 | spin_unlock_irq(&lp->lock); | |
966 | msleep(50); | |
967 | spin_lock_irq(&lp->lock); | |
968 | ||
969 | bmcr = smc_phy_read(dev, phy, MII_BMCR); | |
970 | if (!(bmcr & BMCR_RESET)) | |
971 | break; | |
972 | } | |
973 | ||
974 | return bmcr & BMCR_RESET; | |
975 | } | |
976 | ||
977 | /* | |
978 | * smc_phy_powerdown - powerdown phy | |
979 | * @dev: net device | |
980 | * | |
981 | * Power down the specified PHY | |
982 | */ | |
983 | static void smc_phy_powerdown(struct net_device *dev) | |
984 | { | |
985 | struct smc_local *lp = netdev_priv(dev); | |
986 | unsigned int bmcr; | |
987 | int phy = lp->mii.phy_id; | |
988 | ||
989 | if (lp->phy_type == 0) | |
990 | return; | |
991 | ||
992 | /* We need to ensure that no calls to smc_phy_configure are | |
993 | pending. | |
1da177e4 | 994 | */ |
4bb073c0 | 995 | cancel_work_sync(&lp->phy_configure); |
1da177e4 LT |
996 | |
997 | bmcr = smc_phy_read(dev, phy, MII_BMCR); | |
998 | smc_phy_write(dev, phy, MII_BMCR, bmcr | BMCR_PDOWN); | |
999 | } | |
1000 | ||
1001 | /* | |
1002 | * smc_phy_check_media - check the media status and adjust TCR | |
1003 | * @dev: net device | |
1004 | * @init: set true for initialisation | |
1005 | * | |
1006 | * Select duplex mode depending on negotiation state. This | |
1007 | * also updates our carrier state. | |
1008 | */ | |
1009 | static void smc_phy_check_media(struct net_device *dev, int init) | |
1010 | { | |
1011 | struct smc_local *lp = netdev_priv(dev); | |
1012 | void __iomem *ioaddr = lp->base; | |
1013 | ||
1014 | if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) { | |
1015 | /* duplex state has changed */ | |
1016 | if (lp->mii.full_duplex) { | |
1017 | lp->tcr_cur_mode |= TCR_SWFDUP; | |
1018 | } else { | |
1019 | lp->tcr_cur_mode &= ~TCR_SWFDUP; | |
1020 | } | |
1021 | ||
cfdfa865 MD |
1022 | SMC_SELECT_BANK(lp, 0); |
1023 | SMC_SET_TCR(lp, lp->tcr_cur_mode); | |
1da177e4 LT |
1024 | } |
1025 | } | |
1026 | ||
1027 | /* | |
1028 | * Configures the specified PHY through the MII management interface | |
1029 | * using Autonegotiation. | |
1030 | * Calls smc_phy_fixed() if the user has requested a certain config. | |
1031 | * If RPC ANEG bit is set, the media selection is dependent purely on | |
1032 | * the selection by the MII (either in the MII BMCR reg or the result | |
1033 | * of autonegotiation.) If the RPC ANEG bit is cleared, the selection | |
1034 | * is controlled by the RPC SPEED and RPC DPLX bits. | |
1035 | */ | |
6d5aefb8 | 1036 | static void smc_phy_configure(struct work_struct *work) |
1da177e4 | 1037 | { |
6d5aefb8 DH |
1038 | struct smc_local *lp = |
1039 | container_of(work, struct smc_local, phy_configure); | |
1040 | struct net_device *dev = lp->dev; | |
1da177e4 LT |
1041 | void __iomem *ioaddr = lp->base; |
1042 | int phyaddr = lp->mii.phy_id; | |
1043 | int my_phy_caps; /* My PHY capabilities */ | |
1044 | int my_ad_caps; /* My Advertised capabilities */ | |
1045 | int status; | |
1046 | ||
1047 | DBG(3, "%s:smc_program_phy()\n", dev->name); | |
1048 | ||
1049 | spin_lock_irq(&lp->lock); | |
1050 | ||
1051 | /* | |
1052 | * We should not be called if phy_type is zero. | |
1053 | */ | |
1054 | if (lp->phy_type == 0) | |
1055 | goto smc_phy_configure_exit; | |
1056 | ||
1057 | if (smc_phy_reset(dev, phyaddr)) { | |
1058 | printk("%s: PHY reset timed out\n", dev->name); | |
1059 | goto smc_phy_configure_exit; | |
1060 | } | |
1061 | ||
1062 | /* | |
1063 | * Enable PHY Interrupts (for register 18) | |
1064 | * Interrupts listed here are disabled | |
1065 | */ | |
1066 | smc_phy_write(dev, phyaddr, PHY_MASK_REG, | |
1067 | PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD | | |
1068 | PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB | | |
1069 | PHY_INT_SPDDET | PHY_INT_DPLXDET); | |
1070 | ||
1071 | /* Configure the Receive/Phy Control register */ | |
cfdfa865 MD |
1072 | SMC_SELECT_BANK(lp, 0); |
1073 | SMC_SET_RPC(lp, lp->rpc_cur_mode); | |
1da177e4 LT |
1074 | |
1075 | /* If the user requested no auto neg, then go set his request */ | |
1076 | if (lp->mii.force_media) { | |
1077 | smc_phy_fixed(dev); | |
1078 | goto smc_phy_configure_exit; | |
1079 | } | |
1080 | ||
1081 | /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */ | |
1082 | my_phy_caps = smc_phy_read(dev, phyaddr, MII_BMSR); | |
1083 | ||
1084 | if (!(my_phy_caps & BMSR_ANEGCAPABLE)) { | |
1085 | printk(KERN_INFO "Auto negotiation NOT supported\n"); | |
1086 | smc_phy_fixed(dev); | |
1087 | goto smc_phy_configure_exit; | |
1088 | } | |
1089 | ||
1090 | my_ad_caps = ADVERTISE_CSMA; /* I am CSMA capable */ | |
1091 | ||
1092 | if (my_phy_caps & BMSR_100BASE4) | |
1093 | my_ad_caps |= ADVERTISE_100BASE4; | |
1094 | if (my_phy_caps & BMSR_100FULL) | |
1095 | my_ad_caps |= ADVERTISE_100FULL; | |
1096 | if (my_phy_caps & BMSR_100HALF) | |
1097 | my_ad_caps |= ADVERTISE_100HALF; | |
1098 | if (my_phy_caps & BMSR_10FULL) | |
1099 | my_ad_caps |= ADVERTISE_10FULL; | |
1100 | if (my_phy_caps & BMSR_10HALF) | |
1101 | my_ad_caps |= ADVERTISE_10HALF; | |
1102 | ||
1103 | /* Disable capabilities not selected by our user */ | |
1104 | if (lp->ctl_rspeed != 100) | |
1105 | my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF); | |
1106 | ||
1107 | if (!lp->ctl_rfduplx) | |
1108 | my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL); | |
1109 | ||
1110 | /* Update our Auto-Neg Advertisement Register */ | |
1111 | smc_phy_write(dev, phyaddr, MII_ADVERTISE, my_ad_caps); | |
1112 | lp->mii.advertising = my_ad_caps; | |
1113 | ||
1114 | /* | |
1115 | * Read the register back. Without this, it appears that when | |
1116 | * auto-negotiation is restarted, sometimes it isn't ready and | |
1117 | * the link does not come up. | |
1118 | */ | |
1119 | status = smc_phy_read(dev, phyaddr, MII_ADVERTISE); | |
1120 | ||
1121 | DBG(2, "%s: phy caps=%x\n", dev->name, my_phy_caps); | |
1122 | DBG(2, "%s: phy advertised caps=%x\n", dev->name, my_ad_caps); | |
1123 | ||
1124 | /* Restart auto-negotiation process in order to advertise my caps */ | |
1125 | smc_phy_write(dev, phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); | |
1126 | ||
1127 | smc_phy_check_media(dev, 1); | |
1128 | ||
1129 | smc_phy_configure_exit: | |
cfdfa865 | 1130 | SMC_SELECT_BANK(lp, 2); |
1da177e4 | 1131 | spin_unlock_irq(&lp->lock); |
1da177e4 LT |
1132 | } |
1133 | ||
1134 | /* | |
1135 | * smc_phy_interrupt | |
1136 | * | |
1137 | * Purpose: Handle interrupts relating to PHY register 18. This is | |
1138 | * called from the "hard" interrupt handler under our private spinlock. | |
1139 | */ | |
1140 | static void smc_phy_interrupt(struct net_device *dev) | |
1141 | { | |
1142 | struct smc_local *lp = netdev_priv(dev); | |
1143 | int phyaddr = lp->mii.phy_id; | |
1144 | int phy18; | |
1145 | ||
b39d66a8 | 1146 | DBG(2, "%s: %s\n", dev->name, __func__); |
1da177e4 LT |
1147 | |
1148 | if (lp->phy_type == 0) | |
1149 | return; | |
1150 | ||
1151 | for(;;) { | |
1152 | smc_phy_check_media(dev, 0); | |
1153 | ||
1154 | /* Read PHY Register 18, Status Output */ | |
1155 | phy18 = smc_phy_read(dev, phyaddr, PHY_INT_REG); | |
1156 | if ((phy18 & PHY_INT_INT) == 0) | |
1157 | break; | |
1158 | } | |
1159 | } | |
1160 | ||
1161 | /*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/ | |
1162 | ||
1163 | static void smc_10bt_check_media(struct net_device *dev, int init) | |
1164 | { | |
1165 | struct smc_local *lp = netdev_priv(dev); | |
1166 | void __iomem *ioaddr = lp->base; | |
1167 | unsigned int old_carrier, new_carrier; | |
1168 | ||
1169 | old_carrier = netif_carrier_ok(dev) ? 1 : 0; | |
1170 | ||
cfdfa865 MD |
1171 | SMC_SELECT_BANK(lp, 0); |
1172 | new_carrier = (SMC_GET_EPH_STATUS(lp) & ES_LINK_OK) ? 1 : 0; | |
1173 | SMC_SELECT_BANK(lp, 2); | |
1da177e4 LT |
1174 | |
1175 | if (init || (old_carrier != new_carrier)) { | |
1176 | if (!new_carrier) { | |
1177 | netif_carrier_off(dev); | |
1178 | } else { | |
1179 | netif_carrier_on(dev); | |
1180 | } | |
1181 | if (netif_msg_link(lp)) | |
1182 | printk(KERN_INFO "%s: link %s\n", dev->name, | |
1183 | new_carrier ? "up" : "down"); | |
1184 | } | |
1185 | } | |
1186 | ||
1187 | static void smc_eph_interrupt(struct net_device *dev) | |
1188 | { | |
1189 | struct smc_local *lp = netdev_priv(dev); | |
1190 | void __iomem *ioaddr = lp->base; | |
1191 | unsigned int ctl; | |
1192 | ||
1193 | smc_10bt_check_media(dev, 0); | |
1194 | ||
cfdfa865 MD |
1195 | SMC_SELECT_BANK(lp, 1); |
1196 | ctl = SMC_GET_CTL(lp); | |
1197 | SMC_SET_CTL(lp, ctl & ~CTL_LE_ENABLE); | |
1198 | SMC_SET_CTL(lp, ctl); | |
1199 | SMC_SELECT_BANK(lp, 2); | |
1da177e4 LT |
1200 | } |
1201 | ||
1202 | /* | |
1203 | * This is the main routine of the driver, to handle the device when | |
1204 | * it needs some attention. | |
1205 | */ | |
7d12e780 | 1206 | static irqreturn_t smc_interrupt(int irq, void *dev_id) |
1da177e4 LT |
1207 | { |
1208 | struct net_device *dev = dev_id; | |
1209 | struct smc_local *lp = netdev_priv(dev); | |
1210 | void __iomem *ioaddr = lp->base; | |
1211 | int status, mask, timeout, card_stats; | |
1212 | int saved_pointer; | |
1213 | ||
b39d66a8 | 1214 | DBG(3, "%s: %s\n", dev->name, __func__); |
1da177e4 LT |
1215 | |
1216 | spin_lock(&lp->lock); | |
1217 | ||
1218 | /* A preamble may be used when there is a potential race | |
1219 | * between the interruptible transmit functions and this | |
1220 | * ISR. */ | |
1221 | SMC_INTERRUPT_PREAMBLE; | |
1222 | ||
cfdfa865 MD |
1223 | saved_pointer = SMC_GET_PTR(lp); |
1224 | mask = SMC_GET_INT_MASK(lp); | |
1225 | SMC_SET_INT_MASK(lp, 0); | |
1da177e4 LT |
1226 | |
1227 | /* set a timeout value, so I don't stay here forever */ | |
5d0571d9 | 1228 | timeout = MAX_IRQ_LOOPS; |
1da177e4 LT |
1229 | |
1230 | do { | |
cfdfa865 | 1231 | status = SMC_GET_INT(lp); |
1da177e4 LT |
1232 | |
1233 | DBG(2, "%s: INT 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n", | |
1234 | dev->name, status, mask, | |
cfdfa865 MD |
1235 | ({ int meminfo; SMC_SELECT_BANK(lp, 0); |
1236 | meminfo = SMC_GET_MIR(lp); | |
1237 | SMC_SELECT_BANK(lp, 2); meminfo; }), | |
1238 | SMC_GET_FIFO(lp)); | |
1da177e4 LT |
1239 | |
1240 | status &= mask; | |
1241 | if (!status) | |
1242 | break; | |
1243 | ||
ea937560 NP |
1244 | if (status & IM_TX_INT) { |
1245 | /* do this before RX as it will free memory quickly */ | |
1da177e4 LT |
1246 | DBG(3, "%s: TX int\n", dev->name); |
1247 | smc_tx(dev); | |
cfdfa865 | 1248 | SMC_ACK_INT(lp, IM_TX_INT); |
1da177e4 LT |
1249 | if (THROTTLE_TX_PKTS) |
1250 | netif_wake_queue(dev); | |
ea937560 NP |
1251 | } else if (status & IM_RCV_INT) { |
1252 | DBG(3, "%s: RX irq\n", dev->name); | |
1253 | smc_rcv(dev); | |
1da177e4 LT |
1254 | } else if (status & IM_ALLOC_INT) { |
1255 | DBG(3, "%s: Allocation irq\n", dev->name); | |
1256 | tasklet_hi_schedule(&lp->tx_task); | |
1257 | mask &= ~IM_ALLOC_INT; | |
1258 | } else if (status & IM_TX_EMPTY_INT) { | |
1259 | DBG(3, "%s: TX empty\n", dev->name); | |
1260 | mask &= ~IM_TX_EMPTY_INT; | |
1261 | ||
1262 | /* update stats */ | |
cfdfa865 MD |
1263 | SMC_SELECT_BANK(lp, 0); |
1264 | card_stats = SMC_GET_COUNTER(lp); | |
1265 | SMC_SELECT_BANK(lp, 2); | |
1da177e4 LT |
1266 | |
1267 | /* single collisions */ | |
09f75cd7 | 1268 | dev->stats.collisions += card_stats & 0xF; |
1da177e4 LT |
1269 | card_stats >>= 4; |
1270 | ||
1271 | /* multiple collisions */ | |
09f75cd7 | 1272 | dev->stats.collisions += card_stats & 0xF; |
1da177e4 | 1273 | } else if (status & IM_RX_OVRN_INT) { |
8de90115 | 1274 | DBG(1, "%s: RX overrun (EPH_ST 0x%04x)\n", dev->name, |
cfdfa865 MD |
1275 | ({ int eph_st; SMC_SELECT_BANK(lp, 0); |
1276 | eph_st = SMC_GET_EPH_STATUS(lp); | |
1277 | SMC_SELECT_BANK(lp, 2); eph_st; })); | |
1278 | SMC_ACK_INT(lp, IM_RX_OVRN_INT); | |
09f75cd7 JG |
1279 | dev->stats.rx_errors++; |
1280 | dev->stats.rx_fifo_errors++; | |
1da177e4 LT |
1281 | } else if (status & IM_EPH_INT) { |
1282 | smc_eph_interrupt(dev); | |
1283 | } else if (status & IM_MDINT) { | |
cfdfa865 | 1284 | SMC_ACK_INT(lp, IM_MDINT); |
1da177e4 LT |
1285 | smc_phy_interrupt(dev); |
1286 | } else if (status & IM_ERCV_INT) { | |
cfdfa865 | 1287 | SMC_ACK_INT(lp, IM_ERCV_INT); |
84d57bd6 | 1288 | PRINTK("%s: UNSUPPORTED: ERCV INTERRUPT\n", dev->name); |
1da177e4 LT |
1289 | } |
1290 | } while (--timeout); | |
1291 | ||
1292 | /* restore register states */ | |
cfdfa865 MD |
1293 | SMC_SET_PTR(lp, saved_pointer); |
1294 | SMC_SET_INT_MASK(lp, mask); | |
1da177e4 LT |
1295 | spin_unlock(&lp->lock); |
1296 | ||
c500cb26 | 1297 | #ifndef CONFIG_NET_POLL_CONTROLLER |
5d0571d9 NP |
1298 | if (timeout == MAX_IRQ_LOOPS) |
1299 | PRINTK("%s: spurious interrupt (mask = 0x%02x)\n", | |
1300 | dev->name, mask); | |
c500cb26 | 1301 | #endif |
5d0571d9 NP |
1302 | DBG(3, "%s: Interrupt done (%d loops)\n", |
1303 | dev->name, MAX_IRQ_LOOPS - timeout); | |
1da177e4 LT |
1304 | |
1305 | /* | |
1306 | * We return IRQ_HANDLED unconditionally here even if there was | |
1307 | * nothing to do. There is a possibility that a packet might | |
1308 | * get enqueued into the chip right after TX_EMPTY_INT is raised | |
1309 | * but just before the CPU acknowledges the IRQ. | |
1310 | * Better take an unneeded IRQ in some occasions than complexifying | |
1311 | * the code for all cases. | |
1312 | */ | |
1313 | return IRQ_HANDLED; | |
1314 | } | |
1315 | ||
1316 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1317 | /* | |
1318 | * Polling receive - used by netconsole and other diagnostic tools | |
1319 | * to allow network i/o with interrupts disabled. | |
1320 | */ | |
1321 | static void smc_poll_controller(struct net_device *dev) | |
1322 | { | |
1323 | disable_irq(dev->irq); | |
9c8e7f5c | 1324 | smc_interrupt(dev->irq, dev); |
1da177e4 LT |
1325 | enable_irq(dev->irq); |
1326 | } | |
1327 | #endif | |
1328 | ||
1329 | /* Our watchdog timed out. Called by the networking layer */ | |
1330 | static void smc_timeout(struct net_device *dev) | |
1331 | { | |
1332 | struct smc_local *lp = netdev_priv(dev); | |
1333 | void __iomem *ioaddr = lp->base; | |
8de90115 | 1334 | int status, mask, eph_st, meminfo, fifo; |
1da177e4 | 1335 | |
b39d66a8 | 1336 | DBG(2, "%s: %s\n", dev->name, __func__); |
1da177e4 LT |
1337 | |
1338 | spin_lock_irq(&lp->lock); | |
cfdfa865 MD |
1339 | status = SMC_GET_INT(lp); |
1340 | mask = SMC_GET_INT_MASK(lp); | |
1341 | fifo = SMC_GET_FIFO(lp); | |
1342 | SMC_SELECT_BANK(lp, 0); | |
1343 | eph_st = SMC_GET_EPH_STATUS(lp); | |
1344 | meminfo = SMC_GET_MIR(lp); | |
1345 | SMC_SELECT_BANK(lp, 2); | |
1da177e4 | 1346 | spin_unlock_irq(&lp->lock); |
8de90115 NP |
1347 | PRINTK( "%s: TX timeout (INT 0x%02x INTMASK 0x%02x " |
1348 | "MEM 0x%04x FIFO 0x%04x EPH_ST 0x%04x)\n", | |
1349 | dev->name, status, mask, meminfo, fifo, eph_st ); | |
1da177e4 LT |
1350 | |
1351 | smc_reset(dev); | |
1352 | smc_enable(dev); | |
1353 | ||
1354 | /* | |
1355 | * Reconfiguring the PHY doesn't seem like a bad idea here, but | |
1356 | * smc_phy_configure() calls msleep() which calls schedule_timeout() | |
1357 | * which calls schedule(). Hence we use a work queue. | |
1358 | */ | |
4bb073c0 DM |
1359 | if (lp->phy_type != 0) |
1360 | schedule_work(&lp->phy_configure); | |
1da177e4 LT |
1361 | |
1362 | /* We can accept TX packets again */ | |
1ae5dc34 | 1363 | dev->trans_start = jiffies; /* prevent tx timeout */ |
1da177e4 LT |
1364 | netif_wake_queue(dev); |
1365 | } | |
1366 | ||
1367 | /* | |
1368 | * This routine will, depending on the values passed to it, | |
1369 | * either make it accept multicast packets, go into | |
1370 | * promiscuous mode (for TCPDUMP and cousins) or accept | |
1371 | * a select set of multicast packets | |
1372 | */ | |
1373 | static void smc_set_multicast_list(struct net_device *dev) | |
1374 | { | |
1375 | struct smc_local *lp = netdev_priv(dev); | |
1376 | void __iomem *ioaddr = lp->base; | |
1377 | unsigned char multicast_table[8]; | |
1378 | int update_multicast = 0; | |
1379 | ||
b39d66a8 | 1380 | DBG(2, "%s: %s\n", dev->name, __func__); |
1da177e4 LT |
1381 | |
1382 | if (dev->flags & IFF_PROMISC) { | |
1383 | DBG(2, "%s: RCR_PRMS\n", dev->name); | |
1384 | lp->rcr_cur_mode |= RCR_PRMS; | |
1385 | } | |
1386 | ||
1387 | /* BUG? I never disable promiscuous mode if multicasting was turned on. | |
1388 | Now, I turn off promiscuous mode, but I don't do anything to multicasting | |
1389 | when promiscuous mode is turned on. | |
1390 | */ | |
1391 | ||
1392 | /* | |
1393 | * Here, I am setting this to accept all multicast packets. | |
1394 | * I don't need to zero the multicast table, because the flag is | |
1395 | * checked before the table is | |
1396 | */ | |
4cd24eaf | 1397 | else if (dev->flags & IFF_ALLMULTI || netdev_mc_count(dev) > 16) { |
1da177e4 LT |
1398 | DBG(2, "%s: RCR_ALMUL\n", dev->name); |
1399 | lp->rcr_cur_mode |= RCR_ALMUL; | |
1400 | } | |
1401 | ||
1402 | /* | |
1403 | * This sets the internal hardware table to filter out unwanted | |
1404 | * multicast packets before they take up memory. | |
1405 | * | |
1406 | * The SMC chip uses a hash table where the high 6 bits of the CRC of | |
1407 | * address are the offset into the table. If that bit is 1, then the | |
1408 | * multicast packet is accepted. Otherwise, it's dropped silently. | |
1409 | * | |
1410 | * To use the 6 bits as an offset into the table, the high 3 bits are | |
1411 | * the number of the 8 bit register, while the low 3 bits are the bit | |
1412 | * within that register. | |
1413 | */ | |
4cd24eaf | 1414 | else if (!netdev_mc_empty(dev)) { |
22bedad3 | 1415 | struct netdev_hw_addr *ha; |
1da177e4 LT |
1416 | |
1417 | /* table for flipping the order of 3 bits */ | |
1418 | static const unsigned char invert3[] = {0, 4, 2, 6, 1, 5, 3, 7}; | |
1419 | ||
1420 | /* start with a table of all zeros: reject all */ | |
1421 | memset(multicast_table, 0, sizeof(multicast_table)); | |
1422 | ||
22bedad3 | 1423 | netdev_for_each_mc_addr(ha, dev) { |
1da177e4 LT |
1424 | int position; |
1425 | ||
1da177e4 LT |
1426 | /* make sure this is a multicast address - |
1427 | shouldn't this be a given if we have it here ? */ | |
22bedad3 | 1428 | if (!(*ha->addr & 1)) |
1da177e4 LT |
1429 | continue; |
1430 | ||
1431 | /* only use the low order bits */ | |
22bedad3 | 1432 | position = crc32_le(~0, ha->addr, 6) & 0x3f; |
1da177e4 LT |
1433 | |
1434 | /* do some messy swapping to put the bit in the right spot */ | |
1435 | multicast_table[invert3[position&7]] |= | |
1436 | (1<<invert3[(position>>3)&7]); | |
1437 | } | |
1438 | ||
1439 | /* be sure I get rid of flags I might have set */ | |
1440 | lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL); | |
1441 | ||
1442 | /* now, the table can be loaded into the chipset */ | |
1443 | update_multicast = 1; | |
1444 | } else { | |
1445 | DBG(2, "%s: ~(RCR_PRMS|RCR_ALMUL)\n", dev->name); | |
1446 | lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL); | |
1447 | ||
1448 | /* | |
1449 | * since I'm disabling all multicast entirely, I need to | |
1450 | * clear the multicast list | |
1451 | */ | |
1452 | memset(multicast_table, 0, sizeof(multicast_table)); | |
1453 | update_multicast = 1; | |
1454 | } | |
1455 | ||
1456 | spin_lock_irq(&lp->lock); | |
cfdfa865 MD |
1457 | SMC_SELECT_BANK(lp, 0); |
1458 | SMC_SET_RCR(lp, lp->rcr_cur_mode); | |
1da177e4 | 1459 | if (update_multicast) { |
cfdfa865 MD |
1460 | SMC_SELECT_BANK(lp, 3); |
1461 | SMC_SET_MCAST(lp, multicast_table); | |
1da177e4 | 1462 | } |
cfdfa865 | 1463 | SMC_SELECT_BANK(lp, 2); |
1da177e4 LT |
1464 | spin_unlock_irq(&lp->lock); |
1465 | } | |
1466 | ||
1467 | ||
1468 | /* | |
1469 | * Open and Initialize the board | |
1470 | * | |
1471 | * Set up everything, reset the card, etc.. | |
1472 | */ | |
1473 | static int | |
1474 | smc_open(struct net_device *dev) | |
1475 | { | |
1476 | struct smc_local *lp = netdev_priv(dev); | |
1477 | ||
b39d66a8 | 1478 | DBG(2, "%s: %s\n", dev->name, __func__); |
1da177e4 LT |
1479 | |
1480 | /* | |
1481 | * Check that the address is valid. If its not, refuse | |
1482 | * to bring the device up. The user must specify an | |
1483 | * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx | |
1484 | */ | |
1485 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
b39d66a8 | 1486 | PRINTK("%s: no valid ethernet hw addr\n", __func__); |
1da177e4 LT |
1487 | return -EINVAL; |
1488 | } | |
1489 | ||
1490 | /* Setup the default Register Modes */ | |
1491 | lp->tcr_cur_mode = TCR_DEFAULT; | |
1492 | lp->rcr_cur_mode = RCR_DEFAULT; | |
b0dbcf51 RK |
1493 | lp->rpc_cur_mode = RPC_DEFAULT | |
1494 | lp->cfg.leda << RPC_LSXA_SHFT | | |
1495 | lp->cfg.ledb << RPC_LSXB_SHFT; | |
1da177e4 LT |
1496 | |
1497 | /* | |
1498 | * If we are not using a MII interface, we need to | |
1499 | * monitor our own carrier signal to detect faults. | |
1500 | */ | |
1501 | if (lp->phy_type == 0) | |
1502 | lp->tcr_cur_mode |= TCR_MON_CSN; | |
1503 | ||
1504 | /* reset the hardware */ | |
1505 | smc_reset(dev); | |
1506 | smc_enable(dev); | |
1507 | ||
1508 | /* Configure the PHY, initialize the link state */ | |
1509 | if (lp->phy_type != 0) | |
6d5aefb8 | 1510 | smc_phy_configure(&lp->phy_configure); |
1da177e4 LT |
1511 | else { |
1512 | spin_lock_irq(&lp->lock); | |
1513 | smc_10bt_check_media(dev, 1); | |
1514 | spin_unlock_irq(&lp->lock); | |
1515 | } | |
1516 | ||
1517 | netif_start_queue(dev); | |
1518 | return 0; | |
1519 | } | |
1520 | ||
1521 | /* | |
1522 | * smc_close | |
1523 | * | |
1524 | * this makes the board clean up everything that it can | |
1525 | * and not talk to the outside world. Caused by | |
1526 | * an 'ifconfig ethX down' | |
1527 | */ | |
1528 | static int smc_close(struct net_device *dev) | |
1529 | { | |
1530 | struct smc_local *lp = netdev_priv(dev); | |
1531 | ||
b39d66a8 | 1532 | DBG(2, "%s: %s\n", dev->name, __func__); |
1da177e4 LT |
1533 | |
1534 | netif_stop_queue(dev); | |
1535 | netif_carrier_off(dev); | |
1536 | ||
1537 | /* clear everything */ | |
1538 | smc_shutdown(dev); | |
be83668a | 1539 | tasklet_kill(&lp->tx_task); |
1da177e4 | 1540 | smc_phy_powerdown(dev); |
1da177e4 LT |
1541 | return 0; |
1542 | } | |
1543 | ||
1da177e4 LT |
1544 | /* |
1545 | * Ethtool support | |
1546 | */ | |
1547 | static int | |
1548 | smc_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1549 | { | |
1550 | struct smc_local *lp = netdev_priv(dev); | |
1551 | int ret; | |
1552 | ||
1553 | cmd->maxtxpkt = 1; | |
1554 | cmd->maxrxpkt = 1; | |
1555 | ||
1556 | if (lp->phy_type != 0) { | |
1557 | spin_lock_irq(&lp->lock); | |
1558 | ret = mii_ethtool_gset(&lp->mii, cmd); | |
1559 | spin_unlock_irq(&lp->lock); | |
1560 | } else { | |
1561 | cmd->supported = SUPPORTED_10baseT_Half | | |
1562 | SUPPORTED_10baseT_Full | | |
1563 | SUPPORTED_TP | SUPPORTED_AUI; | |
1564 | ||
1565 | if (lp->ctl_rspeed == 10) | |
1566 | cmd->speed = SPEED_10; | |
1567 | else if (lp->ctl_rspeed == 100) | |
1568 | cmd->speed = SPEED_100; | |
1569 | ||
1570 | cmd->autoneg = AUTONEG_DISABLE; | |
1571 | cmd->transceiver = XCVR_INTERNAL; | |
1572 | cmd->port = 0; | |
1573 | cmd->duplex = lp->tcr_cur_mode & TCR_SWFDUP ? DUPLEX_FULL : DUPLEX_HALF; | |
1574 | ||
1575 | ret = 0; | |
1576 | } | |
1577 | ||
1578 | return ret; | |
1579 | } | |
1580 | ||
1581 | static int | |
1582 | smc_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1583 | { | |
1584 | struct smc_local *lp = netdev_priv(dev); | |
1585 | int ret; | |
1586 | ||
1587 | if (lp->phy_type != 0) { | |
1588 | spin_lock_irq(&lp->lock); | |
1589 | ret = mii_ethtool_sset(&lp->mii, cmd); | |
1590 | spin_unlock_irq(&lp->lock); | |
1591 | } else { | |
1592 | if (cmd->autoneg != AUTONEG_DISABLE || | |
1593 | cmd->speed != SPEED_10 || | |
1594 | (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL) || | |
1595 | (cmd->port != PORT_TP && cmd->port != PORT_AUI)) | |
1596 | return -EINVAL; | |
1597 | ||
1598 | // lp->port = cmd->port; | |
1599 | lp->ctl_rfduplx = cmd->duplex == DUPLEX_FULL; | |
1600 | ||
1601 | // if (netif_running(dev)) | |
1602 | // smc_set_port(dev); | |
1603 | ||
1604 | ret = 0; | |
1605 | } | |
1606 | ||
1607 | return ret; | |
1608 | } | |
1609 | ||
1610 | static void | |
1611 | smc_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
1612 | { | |
1613 | strncpy(info->driver, CARDNAME, sizeof(info->driver)); | |
1614 | strncpy(info->version, version, sizeof(info->version)); | |
db1d7bf7 | 1615 | strncpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info)); |
1da177e4 LT |
1616 | } |
1617 | ||
1618 | static int smc_ethtool_nwayreset(struct net_device *dev) | |
1619 | { | |
1620 | struct smc_local *lp = netdev_priv(dev); | |
1621 | int ret = -EINVAL; | |
1622 | ||
1623 | if (lp->phy_type != 0) { | |
1624 | spin_lock_irq(&lp->lock); | |
1625 | ret = mii_nway_restart(&lp->mii); | |
1626 | spin_unlock_irq(&lp->lock); | |
1627 | } | |
1628 | ||
1629 | return ret; | |
1630 | } | |
1631 | ||
1632 | static u32 smc_ethtool_getmsglevel(struct net_device *dev) | |
1633 | { | |
1634 | struct smc_local *lp = netdev_priv(dev); | |
1635 | return lp->msg_enable; | |
1636 | } | |
1637 | ||
1638 | static void smc_ethtool_setmsglevel(struct net_device *dev, u32 level) | |
1639 | { | |
1640 | struct smc_local *lp = netdev_priv(dev); | |
1641 | lp->msg_enable = level; | |
1642 | } | |
1643 | ||
357fe2c6 VS |
1644 | static int smc_write_eeprom_word(struct net_device *dev, u16 addr, u16 word) |
1645 | { | |
1646 | u16 ctl; | |
1647 | struct smc_local *lp = netdev_priv(dev); | |
1648 | void __iomem *ioaddr = lp->base; | |
1649 | ||
1650 | spin_lock_irq(&lp->lock); | |
1651 | /* load word into GP register */ | |
1652 | SMC_SELECT_BANK(lp, 1); | |
1653 | SMC_SET_GP(lp, word); | |
1654 | /* set the address to put the data in EEPROM */ | |
1655 | SMC_SELECT_BANK(lp, 2); | |
1656 | SMC_SET_PTR(lp, addr); | |
1657 | /* tell it to write */ | |
1658 | SMC_SELECT_BANK(lp, 1); | |
1659 | ctl = SMC_GET_CTL(lp); | |
1660 | SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_STORE)); | |
1661 | /* wait for it to finish */ | |
1662 | do { | |
1663 | udelay(1); | |
1664 | } while (SMC_GET_CTL(lp) & CTL_STORE); | |
1665 | /* clean up */ | |
1666 | SMC_SET_CTL(lp, ctl); | |
1667 | SMC_SELECT_BANK(lp, 2); | |
1668 | spin_unlock_irq(&lp->lock); | |
1669 | return 0; | |
1670 | } | |
1671 | ||
1672 | static int smc_read_eeprom_word(struct net_device *dev, u16 addr, u16 *word) | |
1673 | { | |
1674 | u16 ctl; | |
1675 | struct smc_local *lp = netdev_priv(dev); | |
1676 | void __iomem *ioaddr = lp->base; | |
1677 | ||
1678 | spin_lock_irq(&lp->lock); | |
1679 | /* set the EEPROM address to get the data from */ | |
1680 | SMC_SELECT_BANK(lp, 2); | |
1681 | SMC_SET_PTR(lp, addr | PTR_READ); | |
1682 | /* tell it to load */ | |
1683 | SMC_SELECT_BANK(lp, 1); | |
1684 | SMC_SET_GP(lp, 0xffff); /* init to known */ | |
1685 | ctl = SMC_GET_CTL(lp); | |
1686 | SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_RELOAD)); | |
1687 | /* wait for it to finish */ | |
1688 | do { | |
1689 | udelay(1); | |
1690 | } while (SMC_GET_CTL(lp) & CTL_RELOAD); | |
1691 | /* read word from GP register */ | |
1692 | *word = SMC_GET_GP(lp); | |
1693 | /* clean up */ | |
1694 | SMC_SET_CTL(lp, ctl); | |
1695 | SMC_SELECT_BANK(lp, 2); | |
1696 | spin_unlock_irq(&lp->lock); | |
1697 | return 0; | |
1698 | } | |
1699 | ||
1700 | static int smc_ethtool_geteeprom_len(struct net_device *dev) | |
1701 | { | |
1702 | return 0x23 * 2; | |
1703 | } | |
1704 | ||
1705 | static int smc_ethtool_geteeprom(struct net_device *dev, | |
1706 | struct ethtool_eeprom *eeprom, u8 *data) | |
1707 | { | |
1708 | int i; | |
1709 | int imax; | |
1710 | ||
1711 | DBG(1, "Reading %d bytes at %d(0x%x)\n", | |
1712 | eeprom->len, eeprom->offset, eeprom->offset); | |
1713 | imax = smc_ethtool_geteeprom_len(dev); | |
1714 | for (i = 0; i < eeprom->len; i += 2) { | |
1715 | int ret; | |
1716 | u16 wbuf; | |
1717 | int offset = i + eeprom->offset; | |
1718 | if (offset > imax) | |
1719 | break; | |
1720 | ret = smc_read_eeprom_word(dev, offset >> 1, &wbuf); | |
1721 | if (ret != 0) | |
1722 | return ret; | |
1723 | DBG(2, "Read 0x%x from 0x%x\n", wbuf, offset >> 1); | |
1724 | data[i] = (wbuf >> 8) & 0xff; | |
1725 | data[i+1] = wbuf & 0xff; | |
1726 | } | |
1727 | return 0; | |
1728 | } | |
1729 | ||
1730 | static int smc_ethtool_seteeprom(struct net_device *dev, | |
1731 | struct ethtool_eeprom *eeprom, u8 *data) | |
1732 | { | |
1733 | int i; | |
1734 | int imax; | |
1735 | ||
1736 | DBG(1, "Writing %d bytes to %d(0x%x)\n", | |
1737 | eeprom->len, eeprom->offset, eeprom->offset); | |
1738 | imax = smc_ethtool_geteeprom_len(dev); | |
1739 | for (i = 0; i < eeprom->len; i += 2) { | |
1740 | int ret; | |
1741 | u16 wbuf; | |
1742 | int offset = i + eeprom->offset; | |
1743 | if (offset > imax) | |
1744 | break; | |
1745 | wbuf = (data[i] << 8) | data[i + 1]; | |
1746 | DBG(2, "Writing 0x%x to 0x%x\n", wbuf, offset >> 1); | |
1747 | ret = smc_write_eeprom_word(dev, offset >> 1, wbuf); | |
1748 | if (ret != 0) | |
1749 | return ret; | |
1750 | } | |
1751 | return 0; | |
1752 | } | |
1753 | ||
1754 | ||
7282d491 | 1755 | static const struct ethtool_ops smc_ethtool_ops = { |
1da177e4 LT |
1756 | .get_settings = smc_ethtool_getsettings, |
1757 | .set_settings = smc_ethtool_setsettings, | |
1758 | .get_drvinfo = smc_ethtool_getdrvinfo, | |
1759 | ||
1760 | .get_msglevel = smc_ethtool_getmsglevel, | |
1761 | .set_msglevel = smc_ethtool_setmsglevel, | |
1762 | .nway_reset = smc_ethtool_nwayreset, | |
1763 | .get_link = ethtool_op_get_link, | |
357fe2c6 VS |
1764 | .get_eeprom_len = smc_ethtool_geteeprom_len, |
1765 | .get_eeprom = smc_ethtool_geteeprom, | |
1766 | .set_eeprom = smc_ethtool_seteeprom, | |
1da177e4 LT |
1767 | }; |
1768 | ||
a528079e MD |
1769 | static const struct net_device_ops smc_netdev_ops = { |
1770 | .ndo_open = smc_open, | |
1771 | .ndo_stop = smc_close, | |
1772 | .ndo_start_xmit = smc_hard_start_xmit, | |
1773 | .ndo_tx_timeout = smc_timeout, | |
1774 | .ndo_set_multicast_list = smc_set_multicast_list, | |
635ecaa7 | 1775 | .ndo_change_mtu = eth_change_mtu, |
a528079e MD |
1776 | .ndo_validate_addr = eth_validate_addr, |
1777 | .ndo_set_mac_address = eth_mac_addr, | |
1778 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1779 | .ndo_poll_controller = smc_poll_controller, | |
1780 | #endif | |
1781 | }; | |
1782 | ||
1da177e4 LT |
1783 | /* |
1784 | * smc_findirq | |
1785 | * | |
1786 | * This routine has a simple purpose -- make the SMC chip generate an | |
1787 | * interrupt, so an auto-detect routine can detect it, and find the IRQ, | |
1788 | */ | |
1789 | /* | |
1790 | * does this still work? | |
1791 | * | |
1792 | * I just deleted auto_irq.c, since it was never built... | |
1793 | * --jgarzik | |
1794 | */ | |
f57628d7 | 1795 | static int __devinit smc_findirq(struct smc_local *lp) |
1da177e4 | 1796 | { |
cfdfa865 | 1797 | void __iomem *ioaddr = lp->base; |
1da177e4 LT |
1798 | int timeout = 20; |
1799 | unsigned long cookie; | |
1800 | ||
b39d66a8 | 1801 | DBG(2, "%s: %s\n", CARDNAME, __func__); |
1da177e4 LT |
1802 | |
1803 | cookie = probe_irq_on(); | |
1804 | ||
1805 | /* | |
1806 | * What I try to do here is trigger an ALLOC_INT. This is done | |
1807 | * by allocating a small chunk of memory, which will give an interrupt | |
1808 | * when done. | |
1809 | */ | |
1810 | /* enable ALLOCation interrupts ONLY */ | |
cfdfa865 MD |
1811 | SMC_SELECT_BANK(lp, 2); |
1812 | SMC_SET_INT_MASK(lp, IM_ALLOC_INT); | |
1da177e4 LT |
1813 | |
1814 | /* | |
1815 | * Allocate 512 bytes of memory. Note that the chip was just | |
1816 | * reset so all the memory is available | |
1817 | */ | |
cfdfa865 | 1818 | SMC_SET_MMU_CMD(lp, MC_ALLOC | 1); |
1da177e4 LT |
1819 | |
1820 | /* | |
1821 | * Wait until positive that the interrupt has been generated | |
1822 | */ | |
1823 | do { | |
1824 | int int_status; | |
1825 | udelay(10); | |
cfdfa865 | 1826 | int_status = SMC_GET_INT(lp); |
1da177e4 LT |
1827 | if (int_status & IM_ALLOC_INT) |
1828 | break; /* got the interrupt */ | |
1829 | } while (--timeout); | |
1830 | ||
1831 | /* | |
1832 | * there is really nothing that I can do here if timeout fails, | |
1833 | * as autoirq_report will return a 0 anyway, which is what I | |
1834 | * want in this case. Plus, the clean up is needed in both | |
1835 | * cases. | |
1836 | */ | |
1837 | ||
1838 | /* and disable all interrupts again */ | |
cfdfa865 | 1839 | SMC_SET_INT_MASK(lp, 0); |
1da177e4 LT |
1840 | |
1841 | /* and return what I found */ | |
1842 | return probe_irq_off(cookie); | |
1843 | } | |
1844 | ||
1845 | /* | |
1846 | * Function: smc_probe(unsigned long ioaddr) | |
1847 | * | |
1848 | * Purpose: | |
1849 | * Tests to see if a given ioaddr points to an SMC91x chip. | |
1850 | * Returns a 0 on success | |
1851 | * | |
1852 | * Algorithm: | |
1853 | * (1) see if the high byte of BANK_SELECT is 0x33 | |
1854 | * (2) compare the ioaddr with the base register's address | |
1855 | * (3) see if I recognize the chip ID in the appropriate register | |
1856 | * | |
1857 | * Here I do typical initialization tasks. | |
1858 | * | |
1859 | * o Initialize the structure if needed | |
1860 | * o print out my vanity message if not done so already | |
1861 | * o print out what type of hardware is detected | |
1862 | * o print out the ethernet address | |
1863 | * o find the IRQ | |
1864 | * o set up my private data | |
1865 | * o configure the dev structure with my subroutines | |
1866 | * o actually GRAB the irq. | |
1867 | * o GRAB the region | |
1868 | */ | |
f57628d7 | 1869 | static int __devinit smc_probe(struct net_device *dev, void __iomem *ioaddr, |
e7b3dc7e | 1870 | unsigned long irq_flags) |
1da177e4 LT |
1871 | { |
1872 | struct smc_local *lp = netdev_priv(dev); | |
1873 | static int version_printed = 0; | |
0795af57 | 1874 | int retval; |
1da177e4 LT |
1875 | unsigned int val, revision_register; |
1876 | const char *version_string; | |
1877 | ||
b39d66a8 | 1878 | DBG(2, "%s: %s\n", CARDNAME, __func__); |
1da177e4 LT |
1879 | |
1880 | /* First, see if the high byte is 0x33 */ | |
cfdfa865 | 1881 | val = SMC_CURRENT_BANK(lp); |
1da177e4 LT |
1882 | DBG(2, "%s: bank signature probe returned 0x%04x\n", CARDNAME, val); |
1883 | if ((val & 0xFF00) != 0x3300) { | |
1884 | if ((val & 0xFF) == 0x33) { | |
1885 | printk(KERN_WARNING | |
1886 | "%s: Detected possible byte-swapped interface" | |
1887 | " at IOADDR %p\n", CARDNAME, ioaddr); | |
1888 | } | |
1889 | retval = -ENODEV; | |
1890 | goto err_out; | |
1891 | } | |
1892 | ||
1893 | /* | |
1894 | * The above MIGHT indicate a device, but I need to write to | |
1895 | * further test this. | |
1896 | */ | |
cfdfa865 MD |
1897 | SMC_SELECT_BANK(lp, 0); |
1898 | val = SMC_CURRENT_BANK(lp); | |
1da177e4 LT |
1899 | if ((val & 0xFF00) != 0x3300) { |
1900 | retval = -ENODEV; | |
1901 | goto err_out; | |
1902 | } | |
1903 | ||
1904 | /* | |
1905 | * well, we've already written once, so hopefully another | |
1906 | * time won't hurt. This time, I need to switch the bank | |
1907 | * register to bank 1, so I can access the base address | |
1908 | * register | |
1909 | */ | |
cfdfa865 MD |
1910 | SMC_SELECT_BANK(lp, 1); |
1911 | val = SMC_GET_BASE(lp); | |
1da177e4 | 1912 | val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT; |
53155109 | 1913 | if (((unsigned int)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) { |
1da177e4 LT |
1914 | printk("%s: IOADDR %p doesn't match configuration (%x).\n", |
1915 | CARDNAME, ioaddr, val); | |
1916 | } | |
1917 | ||
1918 | /* | |
1919 | * check if the revision register is something that I | |
1920 | * recognize. These might need to be added to later, | |
1921 | * as future revisions could be added. | |
1922 | */ | |
cfdfa865 MD |
1923 | SMC_SELECT_BANK(lp, 3); |
1924 | revision_register = SMC_GET_REV(lp); | |
1da177e4 LT |
1925 | DBG(2, "%s: revision = 0x%04x\n", CARDNAME, revision_register); |
1926 | version_string = chip_ids[ (revision_register >> 4) & 0xF]; | |
1927 | if (!version_string || (revision_register & 0xff00) != 0x3300) { | |
1928 | /* I don't recognize this chip, so... */ | |
1929 | printk("%s: IO %p: Unrecognized revision register 0x%04x" | |
1930 | ", Contact author.\n", CARDNAME, | |
1931 | ioaddr, revision_register); | |
1932 | ||
1933 | retval = -ENODEV; | |
1934 | goto err_out; | |
1935 | } | |
1936 | ||
1937 | /* At this point I'll assume that the chip is an SMC91x. */ | |
1938 | if (version_printed++ == 0) | |
1939 | printk("%s", version); | |
1940 | ||
1941 | /* fill in some of the fields */ | |
1942 | dev->base_addr = (unsigned long)ioaddr; | |
1943 | lp->base = ioaddr; | |
1944 | lp->version = revision_register & 0xff; | |
1945 | spin_lock_init(&lp->lock); | |
1946 | ||
1947 | /* Get the MAC address */ | |
cfdfa865 MD |
1948 | SMC_SELECT_BANK(lp, 1); |
1949 | SMC_GET_MAC_ADDR(lp, dev->dev_addr); | |
1da177e4 LT |
1950 | |
1951 | /* now, reset the chip, and put it into a known state */ | |
1952 | smc_reset(dev); | |
1953 | ||
1954 | /* | |
1955 | * If dev->irq is 0, then the device has to be banged on to see | |
1956 | * what the IRQ is. | |
1957 | * | |
1958 | * This banging doesn't always detect the IRQ, for unknown reasons. | |
1959 | * a workaround is to reset the chip and try again. | |
1960 | * | |
1961 | * Interestingly, the DOS packet driver *SETS* the IRQ on the card to | |
1962 | * be what is requested on the command line. I don't do that, mostly | |
1963 | * because the card that I have uses a non-standard method of accessing | |
1964 | * the IRQs, and because this _should_ work in most configurations. | |
1965 | * | |
1966 | * Specifying an IRQ is done with the assumption that the user knows | |
1967 | * what (s)he is doing. No checking is done!!!! | |
1968 | */ | |
1969 | if (dev->irq < 1) { | |
1970 | int trials; | |
1971 | ||
1972 | trials = 3; | |
1973 | while (trials--) { | |
cfdfa865 | 1974 | dev->irq = smc_findirq(lp); |
1da177e4 LT |
1975 | if (dev->irq) |
1976 | break; | |
1977 | /* kick the card and try again */ | |
1978 | smc_reset(dev); | |
1979 | } | |
1980 | } | |
1981 | if (dev->irq == 0) { | |
1982 | printk("%s: Couldn't autodetect your IRQ. Use irq=xx.\n", | |
1983 | dev->name); | |
1984 | retval = -ENODEV; | |
1985 | goto err_out; | |
1986 | } | |
1987 | dev->irq = irq_canonicalize(dev->irq); | |
1988 | ||
1989 | /* Fill in the fields of the device structure with ethernet values. */ | |
1990 | ether_setup(dev); | |
1991 | ||
1da177e4 | 1992 | dev->watchdog_timeo = msecs_to_jiffies(watchdog); |
a528079e | 1993 | dev->netdev_ops = &smc_netdev_ops; |
1da177e4 | 1994 | dev->ethtool_ops = &smc_ethtool_ops; |
1da177e4 LT |
1995 | |
1996 | tasklet_init(&lp->tx_task, smc_hardware_send_pkt, (unsigned long)dev); | |
6d5aefb8 DH |
1997 | INIT_WORK(&lp->phy_configure, smc_phy_configure); |
1998 | lp->dev = dev; | |
1da177e4 LT |
1999 | lp->mii.phy_id_mask = 0x1f; |
2000 | lp->mii.reg_num_mask = 0x1f; | |
2001 | lp->mii.force_media = 0; | |
2002 | lp->mii.full_duplex = 0; | |
2003 | lp->mii.dev = dev; | |
2004 | lp->mii.mdio_read = smc_phy_read; | |
2005 | lp->mii.mdio_write = smc_phy_write; | |
2006 | ||
2007 | /* | |
2008 | * Locate the phy, if any. | |
2009 | */ | |
2010 | if (lp->version >= (CHIP_91100 << 4)) | |
2011 | smc_phy_detect(dev); | |
2012 | ||
99e1baf8 NP |
2013 | /* then shut everything down to save power */ |
2014 | smc_shutdown(dev); | |
2015 | smc_phy_powerdown(dev); | |
2016 | ||
1da177e4 LT |
2017 | /* Set default parameters */ |
2018 | lp->msg_enable = NETIF_MSG_LINK; | |
2019 | lp->ctl_rfduplx = 0; | |
2020 | lp->ctl_rspeed = 10; | |
2021 | ||
2022 | if (lp->version >= (CHIP_91100 << 4)) { | |
2023 | lp->ctl_rfduplx = 1; | |
2024 | lp->ctl_rspeed = 100; | |
2025 | } | |
2026 | ||
2027 | /* Grab the IRQ */ | |
a0607fd3 | 2028 | retval = request_irq(dev->irq, smc_interrupt, irq_flags, dev->name, dev); |
1da177e4 LT |
2029 | if (retval) |
2030 | goto err_out; | |
2031 | ||
52256c0e EM |
2032 | #ifdef CONFIG_ARCH_PXA |
2033 | # ifdef SMC_USE_PXA_DMA | |
2034 | lp->cfg.flags |= SMC91X_USE_DMA; | |
2035 | # endif | |
2036 | if (lp->cfg.flags & SMC91X_USE_DMA) { | |
1da177e4 LT |
2037 | int dma = pxa_request_dma(dev->name, DMA_PRIO_LOW, |
2038 | smc_pxa_dma_irq, NULL); | |
2039 | if (dma >= 0) | |
2040 | dev->dma = dma; | |
2041 | } | |
2042 | #endif | |
2043 | ||
2044 | retval = register_netdev(dev); | |
2045 | if (retval == 0) { | |
2046 | /* now, print out the card info, in a short format.. */ | |
2047 | printk("%s: %s (rev %d) at %p IRQ %d", | |
2048 | dev->name, version_string, revision_register & 0x0f, | |
2049 | lp->base, dev->irq); | |
2050 | ||
2051 | if (dev->dma != (unsigned char)-1) | |
2052 | printk(" DMA %d", dev->dma); | |
2053 | ||
d6bc372e MD |
2054 | printk("%s%s\n", |
2055 | lp->cfg.flags & SMC91X_NOWAIT ? " [nowait]" : "", | |
1da177e4 LT |
2056 | THROTTLE_TX_PKTS ? " [throttle_tx]" : ""); |
2057 | ||
2058 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
2059 | printk("%s: Invalid ethernet MAC address. Please " | |
2060 | "set using ifconfig\n", dev->name); | |
2061 | } else { | |
2062 | /* Print the Ethernet address */ | |
e174961c JB |
2063 | printk("%s: Ethernet addr: %pM\n", |
2064 | dev->name, dev->dev_addr); | |
1da177e4 LT |
2065 | } |
2066 | ||
2067 | if (lp->phy_type == 0) { | |
2068 | PRINTK("%s: No PHY found\n", dev->name); | |
2069 | } else if ((lp->phy_type & 0xfffffff0) == 0x0016f840) { | |
2070 | PRINTK("%s: PHY LAN83C183 (LAN91C111 Internal)\n", dev->name); | |
2071 | } else if ((lp->phy_type & 0xfffffff0) == 0x02821c50) { | |
2072 | PRINTK("%s: PHY LAN83C180\n", dev->name); | |
2073 | } | |
2074 | } | |
2075 | ||
2076 | err_out: | |
52256c0e | 2077 | #ifdef CONFIG_ARCH_PXA |
1da177e4 LT |
2078 | if (retval && dev->dma != (unsigned char)-1) |
2079 | pxa_free_dma(dev->dma); | |
2080 | #endif | |
2081 | return retval; | |
2082 | } | |
2083 | ||
2084 | static int smc_enable_device(struct platform_device *pdev) | |
2085 | { | |
3e947943 MD |
2086 | struct net_device *ndev = platform_get_drvdata(pdev); |
2087 | struct smc_local *lp = netdev_priv(ndev); | |
1da177e4 LT |
2088 | unsigned long flags; |
2089 | unsigned char ecor, ecsr; | |
2090 | void __iomem *addr; | |
2091 | struct resource * res; | |
2092 | ||
2093 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); | |
2094 | if (!res) | |
2095 | return 0; | |
2096 | ||
2097 | /* | |
2098 | * Map the attribute space. This is overkill, but clean. | |
2099 | */ | |
2100 | addr = ioremap(res->start, ATTRIB_SIZE); | |
2101 | if (!addr) | |
2102 | return -ENOMEM; | |
2103 | ||
2104 | /* | |
2105 | * Reset the device. We must disable IRQs around this | |
2106 | * since a reset causes the IRQ line become active. | |
2107 | */ | |
2108 | local_irq_save(flags); | |
2109 | ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET; | |
2110 | writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT)); | |
2111 | readb(addr + (ECOR << SMC_IO_SHIFT)); | |
2112 | ||
2113 | /* | |
2114 | * Wait 100us for the chip to reset. | |
2115 | */ | |
2116 | udelay(100); | |
2117 | ||
2118 | /* | |
2119 | * The device will ignore all writes to the enable bit while | |
2120 | * reset is asserted, even if the reset bit is cleared in the | |
2121 | * same write. Must clear reset first, then enable the device. | |
2122 | */ | |
2123 | writeb(ecor, addr + (ECOR << SMC_IO_SHIFT)); | |
2124 | writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT)); | |
2125 | ||
2126 | /* | |
2127 | * Set the appropriate byte/word mode. | |
2128 | */ | |
2129 | ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8; | |
3e947943 | 2130 | if (!SMC_16BIT(lp)) |
09779c6d | 2131 | ecsr |= ECSR_IOIS8; |
1da177e4 LT |
2132 | writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT)); |
2133 | local_irq_restore(flags); | |
2134 | ||
2135 | iounmap(addr); | |
2136 | ||
2137 | /* | |
2138 | * Wait for the chip to wake up. We could poll the control | |
2139 | * register in the main register space, but that isn't mapped | |
2140 | * yet. We know this is going to take 750us. | |
2141 | */ | |
2142 | msleep(1); | |
2143 | ||
2144 | return 0; | |
2145 | } | |
2146 | ||
15919886 EM |
2147 | static int smc_request_attrib(struct platform_device *pdev, |
2148 | struct net_device *ndev) | |
1da177e4 LT |
2149 | { |
2150 | struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); | |
55c8eb6c | 2151 | struct smc_local *lp __maybe_unused = netdev_priv(ndev); |
1da177e4 LT |
2152 | |
2153 | if (!res) | |
2154 | return 0; | |
2155 | ||
2156 | if (!request_mem_region(res->start, ATTRIB_SIZE, CARDNAME)) | |
2157 | return -EBUSY; | |
2158 | ||
2159 | return 0; | |
2160 | } | |
2161 | ||
15919886 EM |
2162 | static void smc_release_attrib(struct platform_device *pdev, |
2163 | struct net_device *ndev) | |
1da177e4 LT |
2164 | { |
2165 | struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); | |
55c8eb6c | 2166 | struct smc_local *lp __maybe_unused = netdev_priv(ndev); |
1da177e4 LT |
2167 | |
2168 | if (res) | |
2169 | release_mem_region(res->start, ATTRIB_SIZE); | |
2170 | } | |
2171 | ||
09779c6d | 2172 | static inline void smc_request_datacs(struct platform_device *pdev, struct net_device *ndev) |
1da177e4 | 2173 | { |
09779c6d NP |
2174 | if (SMC_CAN_USE_DATACS) { |
2175 | struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32"); | |
2176 | struct smc_local *lp = netdev_priv(ndev); | |
1da177e4 | 2177 | |
09779c6d NP |
2178 | if (!res) |
2179 | return; | |
1da177e4 | 2180 | |
09779c6d NP |
2181 | if(!request_mem_region(res->start, SMC_DATA_EXTENT, CARDNAME)) { |
2182 | printk(KERN_INFO "%s: failed to request datacs memory region.\n", CARDNAME); | |
2183 | return; | |
2184 | } | |
1da177e4 | 2185 | |
09779c6d NP |
2186 | lp->datacs = ioremap(res->start, SMC_DATA_EXTENT); |
2187 | } | |
1da177e4 LT |
2188 | } |
2189 | ||
2190 | static void smc_release_datacs(struct platform_device *pdev, struct net_device *ndev) | |
2191 | { | |
09779c6d NP |
2192 | if (SMC_CAN_USE_DATACS) { |
2193 | struct smc_local *lp = netdev_priv(ndev); | |
2194 | struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32"); | |
1da177e4 | 2195 | |
09779c6d NP |
2196 | if (lp->datacs) |
2197 | iounmap(lp->datacs); | |
1da177e4 | 2198 | |
09779c6d | 2199 | lp->datacs = NULL; |
1da177e4 | 2200 | |
09779c6d NP |
2201 | if (res) |
2202 | release_mem_region(res->start, SMC_DATA_EXTENT); | |
2203 | } | |
1da177e4 | 2204 | } |
1da177e4 LT |
2205 | |
2206 | /* | |
2207 | * smc_init(void) | |
2208 | * Input parameters: | |
2209 | * dev->base_addr == 0, try to find all possible locations | |
2210 | * dev->base_addr > 0x1ff, this is the address to check | |
2211 | * dev->base_addr == <anything else>, return failure code | |
2212 | * | |
2213 | * Output: | |
2214 | * 0 --> there is a device | |
2215 | * anything else, error | |
2216 | */ | |
f57628d7 | 2217 | static int __devinit smc_drv_probe(struct platform_device *pdev) |
1da177e4 | 2218 | { |
3e947943 MD |
2219 | struct smc91x_platdata *pd = pdev->dev.platform_data; |
2220 | struct smc_local *lp; | |
1da177e4 | 2221 | struct net_device *ndev; |
e7b3dc7e | 2222 | struct resource *res, *ires; |
1da177e4 | 2223 | unsigned int __iomem *addr; |
d280eadc | 2224 | unsigned long irq_flags = SMC_IRQ_FLAGS; |
1da177e4 LT |
2225 | int ret; |
2226 | ||
1da177e4 LT |
2227 | ndev = alloc_etherdev(sizeof(struct smc_local)); |
2228 | if (!ndev) { | |
2229 | printk("%s: could not allocate device.\n", CARDNAME); | |
2230 | ret = -ENOMEM; | |
15919886 | 2231 | goto out; |
1da177e4 | 2232 | } |
3ae5eaec | 2233 | SET_NETDEV_DEV(ndev, &pdev->dev); |
1da177e4 | 2234 | |
3e947943 MD |
2235 | /* get configuration from platform data, only allow use of |
2236 | * bus width if both SMC_CAN_USE_xxx and SMC91X_USE_xxx are set. | |
2237 | */ | |
2238 | ||
2239 | lp = netdev_priv(ndev); | |
3e947943 | 2240 | |
15919886 | 2241 | if (pd) { |
3e947943 | 2242 | memcpy(&lp->cfg, pd, sizeof(lp->cfg)); |
15919886 EM |
2243 | lp->io_shift = SMC91X_IO_SHIFT(lp->cfg.flags); |
2244 | } else { | |
fa6d3be0 EM |
2245 | lp->cfg.flags |= (SMC_CAN_USE_8BIT) ? SMC91X_USE_8BIT : 0; |
2246 | lp->cfg.flags |= (SMC_CAN_USE_16BIT) ? SMC91X_USE_16BIT : 0; | |
2247 | lp->cfg.flags |= (SMC_CAN_USE_32BIT) ? SMC91X_USE_32BIT : 0; | |
c4f0e767 | 2248 | lp->cfg.flags |= (nowait) ? SMC91X_NOWAIT : 0; |
3e947943 MD |
2249 | } |
2250 | ||
b0dbcf51 RK |
2251 | if (!lp->cfg.leda && !lp->cfg.ledb) { |
2252 | lp->cfg.leda = RPC_LSA_DEFAULT; | |
2253 | lp->cfg.ledb = RPC_LSB_DEFAULT; | |
2254 | } | |
2255 | ||
1da177e4 | 2256 | ndev->dma = (unsigned char)-1; |
e7b3dc7e | 2257 | |
15919886 EM |
2258 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs"); |
2259 | if (!res) | |
2260 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2261 | if (!res) { | |
2262 | ret = -ENODEV; | |
2263 | goto out_free_netdev; | |
2264 | } | |
2265 | ||
2266 | ||
2267 | if (!request_mem_region(res->start, SMC_IO_EXTENT, CARDNAME)) { | |
2268 | ret = -EBUSY; | |
2269 | goto out_free_netdev; | |
2270 | } | |
2271 | ||
e7b3dc7e RK |
2272 | ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
2273 | if (!ires) { | |
48944738 | 2274 | ret = -ENODEV; |
15919886 | 2275 | goto out_release_io; |
48944738 | 2276 | } |
1da177e4 | 2277 | |
e7b3dc7e | 2278 | ndev->irq = ires->start; |
d280eadc | 2279 | |
d5ccd67b | 2280 | if (irq_flags == -1 || ires->flags & IRQF_TRIGGER_MASK) |
d280eadc | 2281 | irq_flags = ires->flags & IRQF_TRIGGER_MASK; |
e7b3dc7e | 2282 | |
15919886 | 2283 | ret = smc_request_attrib(pdev, ndev); |
1da177e4 | 2284 | if (ret) |
15919886 | 2285 | goto out_release_io; |
1da177e4 LT |
2286 | #if defined(CONFIG_SA1100_ASSABET) |
2287 | NCR_0 |= NCR_ENET_OSC_EN; | |
2288 | #endif | |
3e947943 | 2289 | platform_set_drvdata(pdev, ndev); |
1da177e4 LT |
2290 | ret = smc_enable_device(pdev); |
2291 | if (ret) | |
2292 | goto out_release_attrib; | |
2293 | ||
2294 | addr = ioremap(res->start, SMC_IO_EXTENT); | |
2295 | if (!addr) { | |
2296 | ret = -ENOMEM; | |
2297 | goto out_release_attrib; | |
2298 | } | |
2299 | ||
52256c0e | 2300 | #ifdef CONFIG_ARCH_PXA |
073ac8fd | 2301 | { |
1da177e4 | 2302 | struct smc_local *lp = netdev_priv(ndev); |
073ac8fd | 2303 | lp->device = &pdev->dev; |
1da177e4 LT |
2304 | lp->physaddr = res->start; |
2305 | } | |
2306 | #endif | |
2307 | ||
d280eadc | 2308 | ret = smc_probe(ndev, addr, irq_flags); |
073ac8fd RK |
2309 | if (ret != 0) |
2310 | goto out_iounmap; | |
2311 | ||
1da177e4 LT |
2312 | smc_request_datacs(pdev, ndev); |
2313 | ||
2314 | return 0; | |
2315 | ||
2316 | out_iounmap: | |
3ae5eaec | 2317 | platform_set_drvdata(pdev, NULL); |
1da177e4 LT |
2318 | iounmap(addr); |
2319 | out_release_attrib: | |
15919886 | 2320 | smc_release_attrib(pdev, ndev); |
1da177e4 LT |
2321 | out_release_io: |
2322 | release_mem_region(res->start, SMC_IO_EXTENT); | |
15919886 EM |
2323 | out_free_netdev: |
2324 | free_netdev(ndev); | |
1da177e4 LT |
2325 | out: |
2326 | printk("%s: not found (%d).\n", CARDNAME, ret); | |
2327 | ||
2328 | return ret; | |
2329 | } | |
2330 | ||
f57628d7 | 2331 | static int __devexit smc_drv_remove(struct platform_device *pdev) |
1da177e4 | 2332 | { |
3ae5eaec | 2333 | struct net_device *ndev = platform_get_drvdata(pdev); |
1da177e4 LT |
2334 | struct smc_local *lp = netdev_priv(ndev); |
2335 | struct resource *res; | |
2336 | ||
3ae5eaec | 2337 | platform_set_drvdata(pdev, NULL); |
1da177e4 LT |
2338 | |
2339 | unregister_netdev(ndev); | |
2340 | ||
2341 | free_irq(ndev->irq, ndev); | |
2342 | ||
52256c0e | 2343 | #ifdef CONFIG_ARCH_PXA |
1da177e4 LT |
2344 | if (ndev->dma != (unsigned char)-1) |
2345 | pxa_free_dma(ndev->dma); | |
2346 | #endif | |
2347 | iounmap(lp->base); | |
2348 | ||
2349 | smc_release_datacs(pdev,ndev); | |
15919886 | 2350 | smc_release_attrib(pdev,ndev); |
1da177e4 LT |
2351 | |
2352 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs"); | |
2353 | if (!res) | |
6fc30db5 | 2354 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1da177e4 LT |
2355 | release_mem_region(res->start, SMC_IO_EXTENT); |
2356 | ||
2357 | free_netdev(ndev); | |
2358 | ||
2359 | return 0; | |
2360 | } | |
2361 | ||
9f950f72 | 2362 | static int smc_drv_suspend(struct device *dev) |
1da177e4 | 2363 | { |
9f950f72 KH |
2364 | struct platform_device *pdev = to_platform_device(dev); |
2365 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1da177e4 | 2366 | |
9480e307 | 2367 | if (ndev) { |
1da177e4 LT |
2368 | if (netif_running(ndev)) { |
2369 | netif_device_detach(ndev); | |
2370 | smc_shutdown(ndev); | |
2371 | smc_phy_powerdown(ndev); | |
2372 | } | |
2373 | } | |
2374 | return 0; | |
2375 | } | |
2376 | ||
9f950f72 | 2377 | static int smc_drv_resume(struct device *dev) |
1da177e4 | 2378 | { |
9f950f72 KH |
2379 | struct platform_device *pdev = to_platform_device(dev); |
2380 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1da177e4 | 2381 | |
9480e307 | 2382 | if (ndev) { |
1da177e4 | 2383 | struct smc_local *lp = netdev_priv(ndev); |
5fc34413 | 2384 | smc_enable_device(pdev); |
1da177e4 LT |
2385 | if (netif_running(ndev)) { |
2386 | smc_reset(ndev); | |
2387 | smc_enable(ndev); | |
2388 | if (lp->phy_type != 0) | |
6d5aefb8 | 2389 | smc_phy_configure(&lp->phy_configure); |
1da177e4 LT |
2390 | netif_device_attach(ndev); |
2391 | } | |
2392 | } | |
2393 | return 0; | |
2394 | } | |
2395 | ||
9f950f72 KH |
2396 | static struct dev_pm_ops smc_drv_pm_ops = { |
2397 | .suspend = smc_drv_suspend, | |
2398 | .resume = smc_drv_resume, | |
2399 | }; | |
2400 | ||
3ae5eaec | 2401 | static struct platform_driver smc_driver = { |
1da177e4 | 2402 | .probe = smc_drv_probe, |
f57628d7 | 2403 | .remove = __devexit_p(smc_drv_remove), |
3ae5eaec RK |
2404 | .driver = { |
2405 | .name = CARDNAME, | |
72abb461 | 2406 | .owner = THIS_MODULE, |
9f950f72 | 2407 | .pm = &smc_drv_pm_ops, |
3ae5eaec | 2408 | }, |
1da177e4 LT |
2409 | }; |
2410 | ||
2411 | static int __init smc_init(void) | |
2412 | { | |
3ae5eaec | 2413 | return platform_driver_register(&smc_driver); |
1da177e4 LT |
2414 | } |
2415 | ||
2416 | static void __exit smc_cleanup(void) | |
2417 | { | |
3ae5eaec | 2418 | platform_driver_unregister(&smc_driver); |
1da177e4 LT |
2419 | } |
2420 | ||
2421 | module_init(smc_init); | |
2422 | module_exit(smc_cleanup); |