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2cb37728 SG |
1 | /*************************************************************************** |
2 | * | |
3 | * Copyright (C) 2007,2008 SMSC | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
18 | * | |
19 | *************************************************************************** | |
20 | */ | |
21 | ||
22 | #include <linux/kernel.h> | |
23 | #include <linux/netdevice.h> | |
24 | #include <linux/phy.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/if_vlan.h> | |
27 | #include <linux/dma-mapping.h> | |
28 | #include <linux/crc32.h> | |
29 | #include <asm/unaligned.h> | |
30 | #include "smsc9420.h" | |
31 | ||
32 | #define DRV_NAME "smsc9420" | |
33 | #define PFX DRV_NAME ": " | |
34 | #define DRV_MDIONAME "smsc9420-mdio" | |
35 | #define DRV_DESCRIPTION "SMSC LAN9420 driver" | |
36 | #define DRV_VERSION "1.01" | |
37 | ||
38 | MODULE_LICENSE("GPL"); | |
39 | MODULE_VERSION(DRV_VERSION); | |
40 | ||
41 | struct smsc9420_dma_desc { | |
42 | u32 status; | |
43 | u32 length; | |
44 | u32 buffer1; | |
45 | u32 buffer2; | |
46 | }; | |
47 | ||
48 | struct smsc9420_ring_info { | |
49 | struct sk_buff *skb; | |
50 | dma_addr_t mapping; | |
51 | }; | |
52 | ||
53 | struct smsc9420_pdata { | |
54 | void __iomem *base_addr; | |
55 | struct pci_dev *pdev; | |
56 | struct net_device *dev; | |
57 | ||
58 | struct smsc9420_dma_desc *rx_ring; | |
59 | struct smsc9420_dma_desc *tx_ring; | |
60 | struct smsc9420_ring_info *tx_buffers; | |
61 | struct smsc9420_ring_info *rx_buffers; | |
62 | dma_addr_t rx_dma_addr; | |
63 | dma_addr_t tx_dma_addr; | |
64 | int tx_ring_head, tx_ring_tail; | |
65 | int rx_ring_head, rx_ring_tail; | |
66 | ||
67 | spinlock_t int_lock; | |
68 | spinlock_t phy_lock; | |
69 | ||
70 | struct napi_struct napi; | |
71 | ||
72 | bool software_irq_signal; | |
73 | bool rx_csum; | |
74 | u32 msg_enable; | |
75 | ||
76 | struct phy_device *phy_dev; | |
77 | struct mii_bus *mii_bus; | |
78 | int phy_irq[PHY_MAX_ADDR]; | |
79 | int last_duplex; | |
80 | int last_carrier; | |
81 | }; | |
82 | ||
a3aa1884 | 83 | static DEFINE_PCI_DEVICE_TABLE(smsc9420_id_table) = { |
2cb37728 SG |
84 | { PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, }, |
85 | { 0, } | |
86 | }; | |
87 | ||
88 | MODULE_DEVICE_TABLE(pci, smsc9420_id_table); | |
89 | ||
90 | #define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) | |
91 | ||
92 | static uint smsc_debug; | |
93 | static uint debug = -1; | |
94 | module_param(debug, uint, 0); | |
95 | MODULE_PARM_DESC(debug, "debug level"); | |
96 | ||
97 | #define smsc_dbg(TYPE, f, a...) \ | |
98 | do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \ | |
99 | printk(KERN_DEBUG PFX f "\n", ## a); \ | |
100 | } while (0) | |
101 | ||
102 | #define smsc_info(TYPE, f, a...) \ | |
103 | do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \ | |
104 | printk(KERN_INFO PFX f "\n", ## a); \ | |
105 | } while (0) | |
106 | ||
107 | #define smsc_warn(TYPE, f, a...) \ | |
108 | do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \ | |
109 | printk(KERN_WARNING PFX f "\n", ## a); \ | |
110 | } while (0) | |
111 | ||
112 | static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset) | |
113 | { | |
114 | return ioread32(pd->base_addr + offset); | |
115 | } | |
116 | ||
117 | static inline void | |
118 | smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value) | |
119 | { | |
120 | iowrite32(value, pd->base_addr + offset); | |
121 | } | |
122 | ||
123 | static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd) | |
124 | { | |
125 | /* to ensure PCI write completion, we must perform a PCI read */ | |
126 | smsc9420_reg_read(pd, ID_REV); | |
127 | } | |
128 | ||
129 | static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx) | |
130 | { | |
131 | struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv; | |
132 | unsigned long flags; | |
133 | u32 addr; | |
134 | int i, reg = -EIO; | |
135 | ||
136 | spin_lock_irqsave(&pd->phy_lock, flags); | |
137 | ||
138 | /* confirm MII not busy */ | |
139 | if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) { | |
140 | smsc_warn(DRV, "MII is busy???"); | |
141 | goto out; | |
142 | } | |
143 | ||
144 | /* set the address, index & direction (read from PHY) */ | |
145 | addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) | | |
146 | MII_ACCESS_MII_READ_; | |
147 | smsc9420_reg_write(pd, MII_ACCESS, addr); | |
148 | ||
149 | /* wait for read to complete with 50us timeout */ | |
150 | for (i = 0; i < 5; i++) { | |
151 | if (!(smsc9420_reg_read(pd, MII_ACCESS) & | |
152 | MII_ACCESS_MII_BUSY_)) { | |
153 | reg = (u16)smsc9420_reg_read(pd, MII_DATA); | |
154 | goto out; | |
155 | } | |
156 | udelay(10); | |
157 | } | |
158 | ||
159 | smsc_warn(DRV, "MII busy timeout!"); | |
160 | ||
161 | out: | |
162 | spin_unlock_irqrestore(&pd->phy_lock, flags); | |
163 | return reg; | |
164 | } | |
165 | ||
166 | static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx, | |
167 | u16 val) | |
168 | { | |
169 | struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv; | |
170 | unsigned long flags; | |
171 | u32 addr; | |
172 | int i, reg = -EIO; | |
173 | ||
174 | spin_lock_irqsave(&pd->phy_lock, flags); | |
175 | ||
176 | /* confirm MII not busy */ | |
177 | if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) { | |
178 | smsc_warn(DRV, "MII is busy???"); | |
179 | goto out; | |
180 | } | |
181 | ||
182 | /* put the data to write in the MAC */ | |
183 | smsc9420_reg_write(pd, MII_DATA, (u32)val); | |
184 | ||
185 | /* set the address, index & direction (write to PHY) */ | |
186 | addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) | | |
187 | MII_ACCESS_MII_WRITE_; | |
188 | smsc9420_reg_write(pd, MII_ACCESS, addr); | |
189 | ||
190 | /* wait for write to complete with 50us timeout */ | |
191 | for (i = 0; i < 5; i++) { | |
192 | if (!(smsc9420_reg_read(pd, MII_ACCESS) & | |
193 | MII_ACCESS_MII_BUSY_)) { | |
194 | reg = 0; | |
195 | goto out; | |
196 | } | |
197 | udelay(10); | |
198 | } | |
199 | ||
200 | smsc_warn(DRV, "MII busy timeout!"); | |
201 | ||
202 | out: | |
203 | spin_unlock_irqrestore(&pd->phy_lock, flags); | |
204 | return reg; | |
205 | } | |
206 | ||
207 | /* Returns hash bit number for given MAC address | |
208 | * Example: | |
209 | * 01 00 5E 00 00 01 -> returns bit number 31 */ | |
210 | static u32 smsc9420_hash(u8 addr[ETH_ALEN]) | |
211 | { | |
212 | return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f; | |
213 | } | |
214 | ||
215 | static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd) | |
216 | { | |
217 | int timeout = 100000; | |
218 | ||
219 | BUG_ON(!pd); | |
220 | ||
221 | if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) { | |
222 | smsc_dbg(DRV, "smsc9420_eeprom_reload: Eeprom busy"); | |
223 | return -EIO; | |
224 | } | |
225 | ||
226 | smsc9420_reg_write(pd, E2P_CMD, | |
227 | (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_)); | |
228 | ||
229 | do { | |
230 | udelay(10); | |
231 | if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_)) | |
232 | return 0; | |
233 | } while (timeout--); | |
234 | ||
235 | smsc_warn(DRV, "smsc9420_eeprom_reload: Eeprom timed out"); | |
236 | return -EIO; | |
237 | } | |
238 | ||
239 | /* Standard ioctls for mii-tool */ | |
240 | static int smsc9420_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
241 | { | |
242 | struct smsc9420_pdata *pd = netdev_priv(dev); | |
243 | ||
244 | if (!netif_running(dev) || !pd->phy_dev) | |
245 | return -EINVAL; | |
246 | ||
247 | return phy_mii_ioctl(pd->phy_dev, if_mii(ifr), cmd); | |
248 | } | |
249 | ||
250 | static int smsc9420_ethtool_get_settings(struct net_device *dev, | |
251 | struct ethtool_cmd *cmd) | |
252 | { | |
253 | struct smsc9420_pdata *pd = netdev_priv(dev); | |
254 | ||
6c53b1b1 SG |
255 | if (!pd->phy_dev) |
256 | return -ENODEV; | |
257 | ||
2cb37728 SG |
258 | cmd->maxtxpkt = 1; |
259 | cmd->maxrxpkt = 1; | |
260 | return phy_ethtool_gset(pd->phy_dev, cmd); | |
261 | } | |
262 | ||
263 | static int smsc9420_ethtool_set_settings(struct net_device *dev, | |
264 | struct ethtool_cmd *cmd) | |
265 | { | |
266 | struct smsc9420_pdata *pd = netdev_priv(dev); | |
267 | ||
6c53b1b1 SG |
268 | if (!pd->phy_dev) |
269 | return -ENODEV; | |
270 | ||
2cb37728 SG |
271 | return phy_ethtool_sset(pd->phy_dev, cmd); |
272 | } | |
273 | ||
274 | static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev, | |
275 | struct ethtool_drvinfo *drvinfo) | |
276 | { | |
277 | struct smsc9420_pdata *pd = netdev_priv(netdev); | |
278 | ||
279 | strcpy(drvinfo->driver, DRV_NAME); | |
280 | strcpy(drvinfo->bus_info, pci_name(pd->pdev)); | |
281 | strcpy(drvinfo->version, DRV_VERSION); | |
282 | } | |
283 | ||
284 | static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev) | |
285 | { | |
286 | struct smsc9420_pdata *pd = netdev_priv(netdev); | |
287 | return pd->msg_enable; | |
288 | } | |
289 | ||
290 | static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data) | |
291 | { | |
292 | struct smsc9420_pdata *pd = netdev_priv(netdev); | |
293 | pd->msg_enable = data; | |
294 | } | |
295 | ||
296 | static int smsc9420_ethtool_nway_reset(struct net_device *netdev) | |
297 | { | |
298 | struct smsc9420_pdata *pd = netdev_priv(netdev); | |
6c53b1b1 SG |
299 | |
300 | if (!pd->phy_dev) | |
301 | return -ENODEV; | |
302 | ||
2cb37728 SG |
303 | return phy_start_aneg(pd->phy_dev); |
304 | } | |
305 | ||
a7276db6 SG |
306 | static int smsc9420_ethtool_getregslen(struct net_device *dev) |
307 | { | |
308 | /* all smsc9420 registers plus all phy registers */ | |
309 | return 0x100 + (32 * sizeof(u32)); | |
310 | } | |
311 | ||
312 | static void | |
313 | smsc9420_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs, | |
314 | void *buf) | |
315 | { | |
316 | struct smsc9420_pdata *pd = netdev_priv(dev); | |
317 | struct phy_device *phy_dev = pd->phy_dev; | |
318 | unsigned int i, j = 0; | |
319 | u32 *data = buf; | |
320 | ||
321 | regs->version = smsc9420_reg_read(pd, ID_REV); | |
322 | for (i = 0; i < 0x100; i += (sizeof(u32))) | |
323 | data[j++] = smsc9420_reg_read(pd, i); | |
324 | ||
6c53b1b1 SG |
325 | // cannot read phy registers if the net device is down |
326 | if (!phy_dev) | |
327 | return; | |
328 | ||
a7276db6 SG |
329 | for (i = 0; i <= 31; i++) |
330 | data[j++] = smsc9420_mii_read(phy_dev->bus, phy_dev->addr, i); | |
331 | } | |
332 | ||
012b215c SG |
333 | static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd) |
334 | { | |
335 | unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG); | |
336 | temp &= ~GPIO_CFG_EEPR_EN_; | |
337 | smsc9420_reg_write(pd, GPIO_CFG, temp); | |
338 | msleep(1); | |
339 | } | |
340 | ||
341 | static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op) | |
342 | { | |
343 | int timeout = 100; | |
344 | u32 e2cmd; | |
345 | ||
346 | smsc_dbg(HW, "op 0x%08x", op); | |
347 | if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) { | |
348 | smsc_warn(HW, "Busy at start"); | |
349 | return -EBUSY; | |
350 | } | |
351 | ||
352 | e2cmd = op | E2P_CMD_EPC_BUSY_; | |
353 | smsc9420_reg_write(pd, E2P_CMD, e2cmd); | |
354 | ||
355 | do { | |
356 | msleep(1); | |
357 | e2cmd = smsc9420_reg_read(pd, E2P_CMD); | |
9df8f4e3 | 358 | } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout)); |
012b215c SG |
359 | |
360 | if (!timeout) { | |
361 | smsc_info(HW, "TIMED OUT"); | |
362 | return -EAGAIN; | |
363 | } | |
364 | ||
365 | if (e2cmd & E2P_CMD_EPC_TIMEOUT_) { | |
366 | smsc_info(HW, "Error occured during eeprom operation"); | |
367 | return -EINVAL; | |
368 | } | |
369 | ||
370 | return 0; | |
371 | } | |
372 | ||
373 | static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd, | |
374 | u8 address, u8 *data) | |
375 | { | |
376 | u32 op = E2P_CMD_EPC_CMD_READ_ | address; | |
377 | int ret; | |
378 | ||
379 | smsc_dbg(HW, "address 0x%x", address); | |
380 | ret = smsc9420_eeprom_send_cmd(pd, op); | |
381 | ||
382 | if (!ret) | |
383 | data[address] = smsc9420_reg_read(pd, E2P_DATA); | |
384 | ||
385 | return ret; | |
386 | } | |
387 | ||
388 | static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd, | |
389 | u8 address, u8 data) | |
390 | { | |
391 | u32 op = E2P_CMD_EPC_CMD_ERASE_ | address; | |
392 | int ret; | |
393 | ||
394 | smsc_dbg(HW, "address 0x%x, data 0x%x", address, data); | |
395 | ret = smsc9420_eeprom_send_cmd(pd, op); | |
396 | ||
397 | if (!ret) { | |
398 | op = E2P_CMD_EPC_CMD_WRITE_ | address; | |
399 | smsc9420_reg_write(pd, E2P_DATA, (u32)data); | |
400 | ret = smsc9420_eeprom_send_cmd(pd, op); | |
401 | } | |
402 | ||
403 | return ret; | |
404 | } | |
405 | ||
406 | static int smsc9420_ethtool_get_eeprom_len(struct net_device *dev) | |
407 | { | |
408 | return SMSC9420_EEPROM_SIZE; | |
409 | } | |
410 | ||
411 | static int smsc9420_ethtool_get_eeprom(struct net_device *dev, | |
412 | struct ethtool_eeprom *eeprom, u8 *data) | |
413 | { | |
414 | struct smsc9420_pdata *pd = netdev_priv(dev); | |
415 | u8 eeprom_data[SMSC9420_EEPROM_SIZE]; | |
416 | int len, i; | |
417 | ||
418 | smsc9420_eeprom_enable_access(pd); | |
419 | ||
420 | len = min(eeprom->len, SMSC9420_EEPROM_SIZE); | |
421 | for (i = 0; i < len; i++) { | |
422 | int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data); | |
423 | if (ret < 0) { | |
424 | eeprom->len = 0; | |
425 | return ret; | |
426 | } | |
427 | } | |
428 | ||
429 | memcpy(data, &eeprom_data[eeprom->offset], len); | |
196b7e1b | 430 | eeprom->magic = SMSC9420_EEPROM_MAGIC; |
012b215c SG |
431 | eeprom->len = len; |
432 | return 0; | |
433 | } | |
434 | ||
435 | static int smsc9420_ethtool_set_eeprom(struct net_device *dev, | |
436 | struct ethtool_eeprom *eeprom, u8 *data) | |
437 | { | |
438 | struct smsc9420_pdata *pd = netdev_priv(dev); | |
439 | int ret; | |
440 | ||
196b7e1b SG |
441 | if (eeprom->magic != SMSC9420_EEPROM_MAGIC) |
442 | return -EINVAL; | |
443 | ||
012b215c SG |
444 | smsc9420_eeprom_enable_access(pd); |
445 | smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_); | |
446 | ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data); | |
447 | smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_); | |
448 | ||
449 | /* Single byte write, according to man page */ | |
450 | eeprom->len = 1; | |
451 | ||
452 | return ret; | |
453 | } | |
454 | ||
2cb37728 SG |
455 | static const struct ethtool_ops smsc9420_ethtool_ops = { |
456 | .get_settings = smsc9420_ethtool_get_settings, | |
457 | .set_settings = smsc9420_ethtool_set_settings, | |
458 | .get_drvinfo = smsc9420_ethtool_get_drvinfo, | |
459 | .get_msglevel = smsc9420_ethtool_get_msglevel, | |
460 | .set_msglevel = smsc9420_ethtool_set_msglevel, | |
461 | .nway_reset = smsc9420_ethtool_nway_reset, | |
462 | .get_link = ethtool_op_get_link, | |
012b215c SG |
463 | .get_eeprom_len = smsc9420_ethtool_get_eeprom_len, |
464 | .get_eeprom = smsc9420_ethtool_get_eeprom, | |
465 | .set_eeprom = smsc9420_ethtool_set_eeprom, | |
a7276db6 SG |
466 | .get_regs_len = smsc9420_ethtool_getregslen, |
467 | .get_regs = smsc9420_ethtool_getregs, | |
2cb37728 SG |
468 | }; |
469 | ||
470 | /* Sets the device MAC address to dev_addr */ | |
471 | static void smsc9420_set_mac_address(struct net_device *dev) | |
472 | { | |
473 | struct smsc9420_pdata *pd = netdev_priv(dev); | |
474 | u8 *dev_addr = dev->dev_addr; | |
475 | u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4]; | |
476 | u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | | |
477 | (dev_addr[1] << 8) | dev_addr[0]; | |
478 | ||
479 | smsc9420_reg_write(pd, ADDRH, mac_high16); | |
480 | smsc9420_reg_write(pd, ADDRL, mac_low32); | |
481 | } | |
482 | ||
483 | static void smsc9420_check_mac_address(struct net_device *dev) | |
484 | { | |
485 | struct smsc9420_pdata *pd = netdev_priv(dev); | |
486 | ||
487 | /* Check if mac address has been specified when bringing interface up */ | |
488 | if (is_valid_ether_addr(dev->dev_addr)) { | |
489 | smsc9420_set_mac_address(dev); | |
490 | smsc_dbg(PROBE, "MAC Address is specified by configuration"); | |
491 | } else { | |
492 | /* Try reading mac address from device. if EEPROM is present | |
493 | * it will already have been set */ | |
494 | u32 mac_high16 = smsc9420_reg_read(pd, ADDRH); | |
495 | u32 mac_low32 = smsc9420_reg_read(pd, ADDRL); | |
496 | dev->dev_addr[0] = (u8)(mac_low32); | |
497 | dev->dev_addr[1] = (u8)(mac_low32 >> 8); | |
498 | dev->dev_addr[2] = (u8)(mac_low32 >> 16); | |
499 | dev->dev_addr[3] = (u8)(mac_low32 >> 24); | |
500 | dev->dev_addr[4] = (u8)(mac_high16); | |
501 | dev->dev_addr[5] = (u8)(mac_high16 >> 8); | |
502 | ||
503 | if (is_valid_ether_addr(dev->dev_addr)) { | |
504 | /* eeprom values are valid so use them */ | |
505 | smsc_dbg(PROBE, "Mac Address is read from EEPROM"); | |
506 | } else { | |
507 | /* eeprom values are invalid, generate random MAC */ | |
508 | random_ether_addr(dev->dev_addr); | |
509 | smsc9420_set_mac_address(dev); | |
510 | smsc_dbg(PROBE, | |
511 | "MAC Address is set to random_ether_addr"); | |
512 | } | |
513 | } | |
514 | } | |
515 | ||
516 | static void smsc9420_stop_tx(struct smsc9420_pdata *pd) | |
517 | { | |
518 | u32 dmac_control, mac_cr, dma_intr_ena; | |
46578a69 | 519 | int timeout = 1000; |
2cb37728 SG |
520 | |
521 | /* disable TX DMAC */ | |
522 | dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL); | |
523 | dmac_control &= (~DMAC_CONTROL_ST_); | |
524 | smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control); | |
525 | ||
526 | /* Wait max 10ms for transmit process to stop */ | |
46578a69 | 527 | while (--timeout) { |
2cb37728 SG |
528 | if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_) |
529 | break; | |
530 | udelay(10); | |
531 | } | |
532 | ||
46578a69 | 533 | if (!timeout) |
2cb37728 SG |
534 | smsc_warn(IFDOWN, "TX DMAC failed to stop"); |
535 | ||
536 | /* ACK Tx DMAC stop bit */ | |
537 | smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_); | |
538 | ||
539 | /* mask TX DMAC interrupts */ | |
540 | dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); | |
541 | dma_intr_ena &= ~(DMAC_INTR_ENA_TX_); | |
542 | smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); | |
543 | smsc9420_pci_flush_write(pd); | |
544 | ||
545 | /* stop MAC TX */ | |
546 | mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_); | |
547 | smsc9420_reg_write(pd, MAC_CR, mac_cr); | |
548 | smsc9420_pci_flush_write(pd); | |
549 | } | |
550 | ||
551 | static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd) | |
552 | { | |
553 | int i; | |
554 | ||
555 | BUG_ON(!pd->tx_ring); | |
556 | ||
557 | if (!pd->tx_buffers) | |
558 | return; | |
559 | ||
560 | for (i = 0; i < TX_RING_SIZE; i++) { | |
561 | struct sk_buff *skb = pd->tx_buffers[i].skb; | |
562 | ||
563 | if (skb) { | |
564 | BUG_ON(!pd->tx_buffers[i].mapping); | |
565 | pci_unmap_single(pd->pdev, pd->tx_buffers[i].mapping, | |
566 | skb->len, PCI_DMA_TODEVICE); | |
567 | dev_kfree_skb_any(skb); | |
568 | } | |
569 | ||
570 | pd->tx_ring[i].status = 0; | |
571 | pd->tx_ring[i].length = 0; | |
572 | pd->tx_ring[i].buffer1 = 0; | |
573 | pd->tx_ring[i].buffer2 = 0; | |
574 | } | |
575 | wmb(); | |
576 | ||
577 | kfree(pd->tx_buffers); | |
578 | pd->tx_buffers = NULL; | |
579 | ||
580 | pd->tx_ring_head = 0; | |
581 | pd->tx_ring_tail = 0; | |
582 | } | |
583 | ||
584 | static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd) | |
585 | { | |
586 | int i; | |
587 | ||
588 | BUG_ON(!pd->rx_ring); | |
589 | ||
590 | if (!pd->rx_buffers) | |
591 | return; | |
592 | ||
593 | for (i = 0; i < RX_RING_SIZE; i++) { | |
594 | if (pd->rx_buffers[i].skb) | |
595 | dev_kfree_skb_any(pd->rx_buffers[i].skb); | |
596 | ||
597 | if (pd->rx_buffers[i].mapping) | |
598 | pci_unmap_single(pd->pdev, pd->rx_buffers[i].mapping, | |
599 | PKT_BUF_SZ, PCI_DMA_FROMDEVICE); | |
600 | ||
601 | pd->rx_ring[i].status = 0; | |
602 | pd->rx_ring[i].length = 0; | |
603 | pd->rx_ring[i].buffer1 = 0; | |
604 | pd->rx_ring[i].buffer2 = 0; | |
605 | } | |
606 | wmb(); | |
607 | ||
608 | kfree(pd->rx_buffers); | |
609 | pd->rx_buffers = NULL; | |
610 | ||
611 | pd->rx_ring_head = 0; | |
612 | pd->rx_ring_tail = 0; | |
613 | } | |
614 | ||
615 | static void smsc9420_stop_rx(struct smsc9420_pdata *pd) | |
616 | { | |
46578a69 | 617 | int timeout = 1000; |
2cb37728 SG |
618 | u32 mac_cr, dmac_control, dma_intr_ena; |
619 | ||
620 | /* mask RX DMAC interrupts */ | |
621 | dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); | |
622 | dma_intr_ena &= (~DMAC_INTR_ENA_RX_); | |
623 | smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); | |
624 | smsc9420_pci_flush_write(pd); | |
625 | ||
626 | /* stop RX MAC prior to stoping DMA */ | |
627 | mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_); | |
628 | smsc9420_reg_write(pd, MAC_CR, mac_cr); | |
629 | smsc9420_pci_flush_write(pd); | |
630 | ||
631 | /* stop RX DMAC */ | |
632 | dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL); | |
633 | dmac_control &= (~DMAC_CONTROL_SR_); | |
634 | smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control); | |
635 | smsc9420_pci_flush_write(pd); | |
636 | ||
637 | /* wait up to 10ms for receive to stop */ | |
46578a69 | 638 | while (--timeout) { |
2cb37728 SG |
639 | if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_) |
640 | break; | |
641 | udelay(10); | |
642 | } | |
643 | ||
46578a69 | 644 | if (!timeout) |
2cb37728 SG |
645 | smsc_warn(IFDOWN, "RX DMAC did not stop! timeout."); |
646 | ||
647 | /* ACK the Rx DMAC stop bit */ | |
648 | smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_); | |
649 | } | |
650 | ||
651 | static irqreturn_t smsc9420_isr(int irq, void *dev_id) | |
652 | { | |
653 | struct smsc9420_pdata *pd = dev_id; | |
654 | u32 int_cfg, int_sts, int_ctl; | |
655 | irqreturn_t ret = IRQ_NONE; | |
656 | ulong flags; | |
657 | ||
658 | BUG_ON(!pd); | |
659 | BUG_ON(!pd->base_addr); | |
660 | ||
661 | int_cfg = smsc9420_reg_read(pd, INT_CFG); | |
662 | ||
663 | /* check if it's our interrupt */ | |
664 | if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) != | |
665 | (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) | |
666 | return IRQ_NONE; | |
667 | ||
668 | int_sts = smsc9420_reg_read(pd, INT_STAT); | |
669 | ||
670 | if (likely(INT_STAT_DMAC_INT_ & int_sts)) { | |
671 | u32 status = smsc9420_reg_read(pd, DMAC_STATUS); | |
672 | u32 ints_to_clear = 0; | |
673 | ||
674 | if (status & DMAC_STS_TX_) { | |
675 | ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_); | |
676 | netif_wake_queue(pd->dev); | |
677 | } | |
678 | ||
679 | if (status & DMAC_STS_RX_) { | |
680 | /* mask RX DMAC interrupts */ | |
681 | u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); | |
682 | dma_intr_ena &= (~DMAC_INTR_ENA_RX_); | |
683 | smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); | |
684 | smsc9420_pci_flush_write(pd); | |
685 | ||
686 | ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_); | |
288379f0 | 687 | napi_schedule(&pd->napi); |
2cb37728 SG |
688 | } |
689 | ||
690 | if (ints_to_clear) | |
691 | smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear); | |
692 | ||
693 | ret = IRQ_HANDLED; | |
694 | } | |
695 | ||
696 | if (unlikely(INT_STAT_SW_INT_ & int_sts)) { | |
697 | /* mask software interrupt */ | |
698 | spin_lock_irqsave(&pd->int_lock, flags); | |
699 | int_ctl = smsc9420_reg_read(pd, INT_CTL); | |
700 | int_ctl &= (~INT_CTL_SW_INT_EN_); | |
701 | smsc9420_reg_write(pd, INT_CTL, int_ctl); | |
702 | spin_unlock_irqrestore(&pd->int_lock, flags); | |
703 | ||
704 | smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_); | |
705 | pd->software_irq_signal = true; | |
706 | smp_wmb(); | |
707 | ||
708 | ret = IRQ_HANDLED; | |
709 | } | |
710 | ||
711 | /* to ensure PCI write completion, we must perform a PCI read */ | |
712 | smsc9420_pci_flush_write(pd); | |
713 | ||
714 | return ret; | |
715 | } | |
716 | ||
e312674f SG |
717 | #ifdef CONFIG_NET_POLL_CONTROLLER |
718 | static void smsc9420_poll_controller(struct net_device *dev) | |
719 | { | |
720 | disable_irq(dev->irq); | |
721 | smsc9420_isr(0, dev); | |
722 | enable_irq(dev->irq); | |
723 | } | |
724 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
725 | ||
2cb37728 SG |
726 | static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd) |
727 | { | |
728 | smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_); | |
729 | smsc9420_reg_read(pd, BUS_MODE); | |
730 | udelay(2); | |
731 | if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_) | |
732 | smsc_warn(DRV, "Software reset not cleared"); | |
733 | } | |
734 | ||
735 | static int smsc9420_stop(struct net_device *dev) | |
736 | { | |
737 | struct smsc9420_pdata *pd = netdev_priv(dev); | |
738 | u32 int_cfg; | |
739 | ulong flags; | |
740 | ||
741 | BUG_ON(!pd); | |
742 | BUG_ON(!pd->phy_dev); | |
743 | ||
744 | /* disable master interrupt */ | |
745 | spin_lock_irqsave(&pd->int_lock, flags); | |
746 | int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); | |
747 | smsc9420_reg_write(pd, INT_CFG, int_cfg); | |
748 | spin_unlock_irqrestore(&pd->int_lock, flags); | |
749 | ||
750 | netif_tx_disable(dev); | |
751 | napi_disable(&pd->napi); | |
752 | ||
753 | smsc9420_stop_tx(pd); | |
754 | smsc9420_free_tx_ring(pd); | |
755 | ||
756 | smsc9420_stop_rx(pd); | |
757 | smsc9420_free_rx_ring(pd); | |
758 | ||
759 | free_irq(dev->irq, pd); | |
760 | ||
761 | smsc9420_dmac_soft_reset(pd); | |
762 | ||
763 | phy_stop(pd->phy_dev); | |
764 | ||
765 | phy_disconnect(pd->phy_dev); | |
766 | pd->phy_dev = NULL; | |
767 | mdiobus_unregister(pd->mii_bus); | |
768 | mdiobus_free(pd->mii_bus); | |
769 | ||
770 | return 0; | |
771 | } | |
772 | ||
773 | static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status) | |
774 | { | |
775 | if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) { | |
776 | dev->stats.rx_errors++; | |
777 | if (desc_status & RDES0_DESCRIPTOR_ERROR_) | |
778 | dev->stats.rx_over_errors++; | |
779 | else if (desc_status & (RDES0_FRAME_TOO_LONG_ | | |
780 | RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_)) | |
781 | dev->stats.rx_frame_errors++; | |
782 | else if (desc_status & RDES0_CRC_ERROR_) | |
783 | dev->stats.rx_crc_errors++; | |
784 | } | |
785 | ||
786 | if (unlikely(desc_status & RDES0_LENGTH_ERROR_)) | |
787 | dev->stats.rx_length_errors++; | |
788 | ||
789 | if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) && | |
790 | (desc_status & RDES0_FIRST_DESCRIPTOR_)))) | |
791 | dev->stats.rx_length_errors++; | |
792 | ||
793 | if (desc_status & RDES0_MULTICAST_FRAME_) | |
794 | dev->stats.multicast++; | |
795 | } | |
796 | ||
797 | static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index, | |
798 | const u32 status) | |
799 | { | |
800 | struct net_device *dev = pd->dev; | |
801 | struct sk_buff *skb; | |
802 | u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_) | |
803 | >> RDES0_FRAME_LENGTH_SHFT_; | |
804 | ||
805 | /* remove crc from packet lendth */ | |
806 | packet_length -= 4; | |
807 | ||
808 | if (pd->rx_csum) | |
809 | packet_length -= 2; | |
810 | ||
811 | dev->stats.rx_packets++; | |
812 | dev->stats.rx_bytes += packet_length; | |
813 | ||
814 | pci_unmap_single(pd->pdev, pd->rx_buffers[index].mapping, | |
815 | PKT_BUF_SZ, PCI_DMA_FROMDEVICE); | |
816 | pd->rx_buffers[index].mapping = 0; | |
817 | ||
818 | skb = pd->rx_buffers[index].skb; | |
819 | pd->rx_buffers[index].skb = NULL; | |
820 | ||
821 | if (pd->rx_csum) { | |
822 | u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) + | |
823 | NET_IP_ALIGN + packet_length + 4); | |
cd7a3b75 | 824 | put_unaligned_le16(hw_csum, &skb->csum); |
2cb37728 SG |
825 | skb->ip_summed = CHECKSUM_COMPLETE; |
826 | } | |
827 | ||
828 | skb_reserve(skb, NET_IP_ALIGN); | |
829 | skb_put(skb, packet_length); | |
830 | ||
831 | skb->protocol = eth_type_trans(skb, dev); | |
832 | ||
833 | netif_receive_skb(skb); | |
2cb37728 SG |
834 | } |
835 | ||
836 | static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index) | |
837 | { | |
838 | struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ); | |
839 | dma_addr_t mapping; | |
840 | ||
841 | BUG_ON(pd->rx_buffers[index].skb); | |
842 | BUG_ON(pd->rx_buffers[index].mapping); | |
843 | ||
844 | if (unlikely(!skb)) { | |
845 | smsc_warn(RX_ERR, "Failed to allocate new skb!"); | |
846 | return -ENOMEM; | |
847 | } | |
848 | ||
849 | skb->dev = pd->dev; | |
850 | ||
851 | mapping = pci_map_single(pd->pdev, skb_tail_pointer(skb), | |
852 | PKT_BUF_SZ, PCI_DMA_FROMDEVICE); | |
853 | if (pci_dma_mapping_error(pd->pdev, mapping)) { | |
854 | dev_kfree_skb_any(skb); | |
855 | smsc_warn(RX_ERR, "pci_map_single failed!"); | |
856 | return -ENOMEM; | |
857 | } | |
858 | ||
859 | pd->rx_buffers[index].skb = skb; | |
860 | pd->rx_buffers[index].mapping = mapping; | |
861 | pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN; | |
862 | pd->rx_ring[index].status = RDES0_OWN_; | |
863 | wmb(); | |
864 | ||
865 | return 0; | |
866 | } | |
867 | ||
868 | static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd) | |
869 | { | |
870 | while (pd->rx_ring_tail != pd->rx_ring_head) { | |
871 | if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail)) | |
872 | break; | |
873 | ||
874 | pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE; | |
875 | } | |
876 | } | |
877 | ||
878 | static int smsc9420_rx_poll(struct napi_struct *napi, int budget) | |
879 | { | |
880 | struct smsc9420_pdata *pd = | |
881 | container_of(napi, struct smsc9420_pdata, napi); | |
882 | struct net_device *dev = pd->dev; | |
883 | u32 drop_frame_cnt, dma_intr_ena, status; | |
884 | int work_done; | |
885 | ||
886 | for (work_done = 0; work_done < budget; work_done++) { | |
887 | rmb(); | |
888 | status = pd->rx_ring[pd->rx_ring_head].status; | |
889 | ||
890 | /* stop if DMAC owns this dma descriptor */ | |
891 | if (status & RDES0_OWN_) | |
892 | break; | |
893 | ||
894 | smsc9420_rx_count_stats(dev, status); | |
895 | smsc9420_rx_handoff(pd, pd->rx_ring_head, status); | |
896 | pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE; | |
897 | smsc9420_alloc_new_rx_buffers(pd); | |
898 | } | |
899 | ||
900 | drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR); | |
901 | dev->stats.rx_dropped += | |
902 | (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF); | |
903 | ||
904 | /* Kick RXDMA */ | |
905 | smsc9420_reg_write(pd, RX_POLL_DEMAND, 1); | |
906 | smsc9420_pci_flush_write(pd); | |
907 | ||
908 | if (work_done < budget) { | |
288379f0 | 909 | napi_complete(&pd->napi); |
2cb37728 SG |
910 | |
911 | /* re-enable RX DMA interrupts */ | |
912 | dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); | |
913 | dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_); | |
914 | smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); | |
915 | smsc9420_pci_flush_write(pd); | |
916 | } | |
917 | return work_done; | |
918 | } | |
919 | ||
920 | static void | |
921 | smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length) | |
922 | { | |
923 | if (unlikely(status & TDES0_ERROR_SUMMARY_)) { | |
924 | dev->stats.tx_errors++; | |
925 | if (status & (TDES0_EXCESSIVE_DEFERRAL_ | | |
926 | TDES0_EXCESSIVE_COLLISIONS_)) | |
927 | dev->stats.tx_aborted_errors++; | |
928 | ||
929 | if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_)) | |
930 | dev->stats.tx_carrier_errors++; | |
931 | } else { | |
932 | dev->stats.tx_packets++; | |
933 | dev->stats.tx_bytes += (length & 0x7FF); | |
934 | } | |
935 | ||
936 | if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) { | |
937 | dev->stats.collisions += 16; | |
938 | } else { | |
939 | dev->stats.collisions += | |
940 | (status & TDES0_COLLISION_COUNT_MASK_) >> | |
941 | TDES0_COLLISION_COUNT_SHFT_; | |
942 | } | |
943 | ||
944 | if (unlikely(status & TDES0_HEARTBEAT_FAIL_)) | |
945 | dev->stats.tx_heartbeat_errors++; | |
946 | } | |
947 | ||
948 | /* Check for completed dma transfers, update stats and free skbs */ | |
949 | static void smsc9420_complete_tx(struct net_device *dev) | |
950 | { | |
951 | struct smsc9420_pdata *pd = netdev_priv(dev); | |
952 | ||
953 | while (pd->tx_ring_tail != pd->tx_ring_head) { | |
954 | int index = pd->tx_ring_tail; | |
955 | u32 status, length; | |
956 | ||
957 | rmb(); | |
958 | status = pd->tx_ring[index].status; | |
959 | length = pd->tx_ring[index].length; | |
960 | ||
961 | /* Check if DMA still owns this descriptor */ | |
962 | if (unlikely(TDES0_OWN_ & status)) | |
963 | break; | |
964 | ||
965 | smsc9420_tx_update_stats(dev, status, length); | |
966 | ||
967 | BUG_ON(!pd->tx_buffers[index].skb); | |
968 | BUG_ON(!pd->tx_buffers[index].mapping); | |
969 | ||
970 | pci_unmap_single(pd->pdev, pd->tx_buffers[index].mapping, | |
971 | pd->tx_buffers[index].skb->len, PCI_DMA_TODEVICE); | |
972 | pd->tx_buffers[index].mapping = 0; | |
973 | ||
974 | dev_kfree_skb_any(pd->tx_buffers[index].skb); | |
975 | pd->tx_buffers[index].skb = NULL; | |
976 | ||
977 | pd->tx_ring[index].buffer1 = 0; | |
978 | wmb(); | |
979 | ||
980 | pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE; | |
981 | } | |
982 | } | |
983 | ||
61357325 SH |
984 | static netdev_tx_t smsc9420_hard_start_xmit(struct sk_buff *skb, |
985 | struct net_device *dev) | |
2cb37728 SG |
986 | { |
987 | struct smsc9420_pdata *pd = netdev_priv(dev); | |
988 | dma_addr_t mapping; | |
989 | int index = pd->tx_ring_head; | |
990 | u32 tmp_desc1; | |
991 | bool about_to_take_last_desc = | |
992 | (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail); | |
993 | ||
994 | smsc9420_complete_tx(dev); | |
995 | ||
996 | rmb(); | |
997 | BUG_ON(pd->tx_ring[index].status & TDES0_OWN_); | |
998 | BUG_ON(pd->tx_buffers[index].skb); | |
999 | BUG_ON(pd->tx_buffers[index].mapping); | |
1000 | ||
1001 | mapping = pci_map_single(pd->pdev, skb->data, | |
1002 | skb->len, PCI_DMA_TODEVICE); | |
1003 | if (pci_dma_mapping_error(pd->pdev, mapping)) { | |
1004 | smsc_warn(TX_ERR, "pci_map_single failed, dropping packet"); | |
1005 | return NETDEV_TX_BUSY; | |
1006 | } | |
1007 | ||
1008 | pd->tx_buffers[index].skb = skb; | |
1009 | pd->tx_buffers[index].mapping = mapping; | |
1010 | ||
1011 | tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF)); | |
1012 | if (unlikely(about_to_take_last_desc)) { | |
1013 | tmp_desc1 |= TDES1_IC_; | |
1014 | netif_stop_queue(pd->dev); | |
1015 | } | |
1016 | ||
1017 | /* check if we are at the last descriptor and need to set EOR */ | |
1018 | if (unlikely(index == (TX_RING_SIZE - 1))) | |
1019 | tmp_desc1 |= TDES1_TER_; | |
1020 | ||
1021 | pd->tx_ring[index].buffer1 = mapping; | |
1022 | pd->tx_ring[index].length = tmp_desc1; | |
1023 | wmb(); | |
1024 | ||
1025 | /* increment head */ | |
1026 | pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE; | |
1027 | ||
1028 | /* assign ownership to DMAC */ | |
1029 | pd->tx_ring[index].status = TDES0_OWN_; | |
1030 | wmb(); | |
1031 | ||
1032 | /* kick the DMA */ | |
1033 | smsc9420_reg_write(pd, TX_POLL_DEMAND, 1); | |
1034 | smsc9420_pci_flush_write(pd); | |
1035 | ||
1036 | dev->trans_start = jiffies; | |
1037 | ||
1038 | return NETDEV_TX_OK; | |
1039 | } | |
1040 | ||
1041 | static struct net_device_stats *smsc9420_get_stats(struct net_device *dev) | |
1042 | { | |
1043 | struct smsc9420_pdata *pd = netdev_priv(dev); | |
1044 | u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR); | |
1045 | dev->stats.rx_dropped += | |
1046 | (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF); | |
1047 | return &dev->stats; | |
1048 | } | |
1049 | ||
1050 | static void smsc9420_set_multicast_list(struct net_device *dev) | |
1051 | { | |
1052 | struct smsc9420_pdata *pd = netdev_priv(dev); | |
1053 | u32 mac_cr = smsc9420_reg_read(pd, MAC_CR); | |
1054 | ||
1055 | if (dev->flags & IFF_PROMISC) { | |
1056 | smsc_dbg(HW, "Promiscuous Mode Enabled"); | |
1057 | mac_cr |= MAC_CR_PRMS_; | |
1058 | mac_cr &= (~MAC_CR_MCPAS_); | |
1059 | mac_cr &= (~MAC_CR_HPFILT_); | |
1060 | } else if (dev->flags & IFF_ALLMULTI) { | |
1061 | smsc_dbg(HW, "Receive all Multicast Enabled"); | |
1062 | mac_cr &= (~MAC_CR_PRMS_); | |
1063 | mac_cr |= MAC_CR_MCPAS_; | |
1064 | mac_cr &= (~MAC_CR_HPFILT_); | |
4cd24eaf | 1065 | } else if (!netdev_mc_empty(dev)) { |
22bedad3 | 1066 | struct netdev_hw_addr *ha; |
2cb37728 SG |
1067 | u32 hash_lo = 0, hash_hi = 0; |
1068 | ||
1069 | smsc_dbg(HW, "Multicast filter enabled"); | |
22bedad3 JP |
1070 | netdev_for_each_mc_addr(ha, dev) { |
1071 | u32 bit_num = smsc9420_hash(ha->addr); | |
2cb37728 SG |
1072 | u32 mask = 1 << (bit_num & 0x1F); |
1073 | ||
1074 | if (bit_num & 0x20) | |
1075 | hash_hi |= mask; | |
1076 | else | |
1077 | hash_lo |= mask; | |
1078 | ||
2cb37728 SG |
1079 | } |
1080 | smsc9420_reg_write(pd, HASHH, hash_hi); | |
1081 | smsc9420_reg_write(pd, HASHL, hash_lo); | |
1082 | ||
1083 | mac_cr &= (~MAC_CR_PRMS_); | |
1084 | mac_cr &= (~MAC_CR_MCPAS_); | |
1085 | mac_cr |= MAC_CR_HPFILT_; | |
1086 | } else { | |
1087 | smsc_dbg(HW, "Receive own packets only."); | |
1088 | smsc9420_reg_write(pd, HASHH, 0); | |
1089 | smsc9420_reg_write(pd, HASHL, 0); | |
1090 | ||
1091 | mac_cr &= (~MAC_CR_PRMS_); | |
1092 | mac_cr &= (~MAC_CR_MCPAS_); | |
1093 | mac_cr &= (~MAC_CR_HPFILT_); | |
1094 | } | |
1095 | ||
1096 | smsc9420_reg_write(pd, MAC_CR, mac_cr); | |
1097 | smsc9420_pci_flush_write(pd); | |
1098 | } | |
1099 | ||
2cb37728 SG |
1100 | static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd) |
1101 | { | |
1102 | struct phy_device *phy_dev = pd->phy_dev; | |
1103 | u32 flow; | |
1104 | ||
1105 | if (phy_dev->duplex == DUPLEX_FULL) { | |
1106 | u16 lcladv = phy_read(phy_dev, MII_ADVERTISE); | |
1107 | u16 rmtadv = phy_read(phy_dev, MII_LPA); | |
bc02ff95 | 1108 | u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
2cb37728 SG |
1109 | |
1110 | if (cap & FLOW_CTRL_RX) | |
1111 | flow = 0xFFFF0002; | |
1112 | else | |
1113 | flow = 0; | |
1114 | ||
1115 | smsc_info(LINK, "rx pause %s, tx pause %s", | |
1116 | (cap & FLOW_CTRL_RX ? "enabled" : "disabled"), | |
1117 | (cap & FLOW_CTRL_TX ? "enabled" : "disabled")); | |
1118 | } else { | |
1119 | smsc_info(LINK, "half duplex"); | |
1120 | flow = 0; | |
1121 | } | |
1122 | ||
1123 | smsc9420_reg_write(pd, FLOW, flow); | |
1124 | } | |
1125 | ||
1126 | /* Update link mode if anything has changed. Called periodically when the | |
1127 | * PHY is in polling mode, even if nothing has changed. */ | |
1128 | static void smsc9420_phy_adjust_link(struct net_device *dev) | |
1129 | { | |
1130 | struct smsc9420_pdata *pd = netdev_priv(dev); | |
1131 | struct phy_device *phy_dev = pd->phy_dev; | |
1132 | int carrier; | |
1133 | ||
1134 | if (phy_dev->duplex != pd->last_duplex) { | |
1135 | u32 mac_cr = smsc9420_reg_read(pd, MAC_CR); | |
1136 | if (phy_dev->duplex) { | |
1137 | smsc_dbg(LINK, "full duplex mode"); | |
1138 | mac_cr |= MAC_CR_FDPX_; | |
1139 | } else { | |
1140 | smsc_dbg(LINK, "half duplex mode"); | |
1141 | mac_cr &= ~MAC_CR_FDPX_; | |
1142 | } | |
1143 | smsc9420_reg_write(pd, MAC_CR, mac_cr); | |
1144 | ||
1145 | smsc9420_phy_update_flowcontrol(pd); | |
1146 | pd->last_duplex = phy_dev->duplex; | |
1147 | } | |
1148 | ||
1149 | carrier = netif_carrier_ok(dev); | |
1150 | if (carrier != pd->last_carrier) { | |
1151 | if (carrier) | |
1152 | smsc_dbg(LINK, "carrier OK"); | |
1153 | else | |
1154 | smsc_dbg(LINK, "no carrier"); | |
1155 | pd->last_carrier = carrier; | |
1156 | } | |
1157 | } | |
1158 | ||
1159 | static int smsc9420_mii_probe(struct net_device *dev) | |
1160 | { | |
1161 | struct smsc9420_pdata *pd = netdev_priv(dev); | |
1162 | struct phy_device *phydev = NULL; | |
1163 | ||
1164 | BUG_ON(pd->phy_dev); | |
1165 | ||
1166 | /* Device only supports internal PHY at address 1 */ | |
1167 | if (!pd->mii_bus->phy_map[1]) { | |
1168 | pr_err("%s: no PHY found at address 1\n", dev->name); | |
1169 | return -ENODEV; | |
1170 | } | |
1171 | ||
1172 | phydev = pd->mii_bus->phy_map[1]; | |
1173 | smsc_info(PROBE, "PHY addr %d, phy_id 0x%08X", phydev->addr, | |
1174 | phydev->phy_id); | |
1175 | ||
db1d7bf7 | 1176 | phydev = phy_connect(dev, dev_name(&phydev->dev), |
a974a679 | 1177 | smsc9420_phy_adjust_link, 0, PHY_INTERFACE_MODE_MII); |
2cb37728 SG |
1178 | |
1179 | if (IS_ERR(phydev)) { | |
1180 | pr_err("%s: Could not attach to PHY\n", dev->name); | |
1181 | return PTR_ERR(phydev); | |
1182 | } | |
1183 | ||
1184 | pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", | |
db1d7bf7 | 1185 | dev->name, phydev->drv->name, dev_name(&phydev->dev), phydev->irq); |
2cb37728 SG |
1186 | |
1187 | /* mask with MAC supported features */ | |
1188 | phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause | | |
1189 | SUPPORTED_Asym_Pause); | |
1190 | phydev->advertising = phydev->supported; | |
1191 | ||
1192 | pd->phy_dev = phydev; | |
1193 | pd->last_duplex = -1; | |
1194 | pd->last_carrier = -1; | |
1195 | ||
1196 | return 0; | |
1197 | } | |
1198 | ||
1199 | static int smsc9420_mii_init(struct net_device *dev) | |
1200 | { | |
1201 | struct smsc9420_pdata *pd = netdev_priv(dev); | |
1202 | int err = -ENXIO, i; | |
1203 | ||
1204 | pd->mii_bus = mdiobus_alloc(); | |
1205 | if (!pd->mii_bus) { | |
1206 | err = -ENOMEM; | |
1207 | goto err_out_1; | |
1208 | } | |
1209 | pd->mii_bus->name = DRV_MDIONAME; | |
1210 | snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x", | |
1211 | (pd->pdev->bus->number << 8) | pd->pdev->devfn); | |
1212 | pd->mii_bus->priv = pd; | |
1213 | pd->mii_bus->read = smsc9420_mii_read; | |
1214 | pd->mii_bus->write = smsc9420_mii_write; | |
1215 | pd->mii_bus->irq = pd->phy_irq; | |
1216 | for (i = 0; i < PHY_MAX_ADDR; ++i) | |
1217 | pd->mii_bus->irq[i] = PHY_POLL; | |
1218 | ||
1219 | /* Mask all PHYs except ID 1 (internal) */ | |
1220 | pd->mii_bus->phy_mask = ~(1 << 1); | |
1221 | ||
1222 | if (mdiobus_register(pd->mii_bus)) { | |
1223 | smsc_warn(PROBE, "Error registering mii bus"); | |
1224 | goto err_out_free_bus_2; | |
1225 | } | |
1226 | ||
1227 | if (smsc9420_mii_probe(dev) < 0) { | |
1228 | smsc_warn(PROBE, "Error probing mii bus"); | |
1229 | goto err_out_unregister_bus_3; | |
1230 | } | |
1231 | ||
1232 | return 0; | |
1233 | ||
1234 | err_out_unregister_bus_3: | |
1235 | mdiobus_unregister(pd->mii_bus); | |
1236 | err_out_free_bus_2: | |
1237 | mdiobus_free(pd->mii_bus); | |
1238 | err_out_1: | |
1239 | return err; | |
1240 | } | |
1241 | ||
1242 | static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd) | |
1243 | { | |
1244 | int i; | |
1245 | ||
1246 | BUG_ON(!pd->tx_ring); | |
1247 | ||
1248 | pd->tx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) * | |
1249 | TX_RING_SIZE), GFP_KERNEL); | |
1250 | if (!pd->tx_buffers) { | |
1251 | smsc_warn(IFUP, "Failed to allocated tx_buffers"); | |
1252 | return -ENOMEM; | |
1253 | } | |
1254 | ||
1255 | /* Initialize the TX Ring */ | |
1256 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1257 | pd->tx_buffers[i].skb = NULL; | |
1258 | pd->tx_buffers[i].mapping = 0; | |
1259 | pd->tx_ring[i].status = 0; | |
1260 | pd->tx_ring[i].length = 0; | |
1261 | pd->tx_ring[i].buffer1 = 0; | |
1262 | pd->tx_ring[i].buffer2 = 0; | |
1263 | } | |
1264 | pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_; | |
1265 | wmb(); | |
1266 | ||
1267 | pd->tx_ring_head = 0; | |
1268 | pd->tx_ring_tail = 0; | |
1269 | ||
1270 | smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr); | |
1271 | smsc9420_pci_flush_write(pd); | |
1272 | ||
1273 | return 0; | |
1274 | } | |
1275 | ||
1276 | static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd) | |
1277 | { | |
1278 | int i; | |
1279 | ||
1280 | BUG_ON(!pd->rx_ring); | |
1281 | ||
1282 | pd->rx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) * | |
1283 | RX_RING_SIZE), GFP_KERNEL); | |
1284 | if (pd->rx_buffers == NULL) { | |
1285 | smsc_warn(IFUP, "Failed to allocated rx_buffers"); | |
1286 | goto out; | |
1287 | } | |
1288 | ||
1289 | /* initialize the rx ring */ | |
1290 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1291 | pd->rx_ring[i].status = 0; | |
1292 | pd->rx_ring[i].length = PKT_BUF_SZ; | |
1293 | pd->rx_ring[i].buffer2 = 0; | |
1294 | pd->rx_buffers[i].skb = NULL; | |
1295 | pd->rx_buffers[i].mapping = 0; | |
1296 | } | |
1297 | pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_); | |
1298 | ||
1299 | /* now allocate the entire ring of skbs */ | |
1300 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1301 | if (smsc9420_alloc_rx_buffer(pd, i)) { | |
1302 | smsc_warn(IFUP, "failed to allocate rx skb %d", i); | |
1303 | goto out_free_rx_skbs; | |
1304 | } | |
1305 | } | |
1306 | ||
1307 | pd->rx_ring_head = 0; | |
1308 | pd->rx_ring_tail = 0; | |
1309 | ||
1310 | smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q); | |
1311 | smsc_dbg(IFUP, "VLAN1 = 0x%08x", smsc9420_reg_read(pd, VLAN1)); | |
1312 | ||
1313 | if (pd->rx_csum) { | |
1314 | /* Enable RX COE */ | |
1315 | u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN; | |
1316 | smsc9420_reg_write(pd, COE_CR, coe); | |
1317 | smsc_dbg(IFUP, "COE_CR = 0x%08x", coe); | |
1318 | } | |
1319 | ||
1320 | smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr); | |
1321 | smsc9420_pci_flush_write(pd); | |
1322 | ||
1323 | return 0; | |
1324 | ||
1325 | out_free_rx_skbs: | |
1326 | smsc9420_free_rx_ring(pd); | |
1327 | out: | |
1328 | return -ENOMEM; | |
1329 | } | |
1330 | ||
1331 | static int smsc9420_open(struct net_device *dev) | |
1332 | { | |
1333 | struct smsc9420_pdata *pd; | |
1334 | u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl; | |
1335 | unsigned long flags; | |
1336 | int result = 0, timeout; | |
1337 | ||
1338 | BUG_ON(!dev); | |
1339 | pd = netdev_priv(dev); | |
1340 | BUG_ON(!pd); | |
1341 | ||
1342 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
1343 | smsc_warn(IFUP, "dev_addr is not a valid MAC address"); | |
1344 | result = -EADDRNOTAVAIL; | |
1345 | goto out_0; | |
1346 | } | |
1347 | ||
1348 | netif_carrier_off(dev); | |
1349 | ||
3ad2f3fb | 1350 | /* disable, mask and acknowledge all interrupts */ |
2cb37728 SG |
1351 | spin_lock_irqsave(&pd->int_lock, flags); |
1352 | int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); | |
1353 | smsc9420_reg_write(pd, INT_CFG, int_cfg); | |
1354 | smsc9420_reg_write(pd, INT_CTL, 0); | |
1355 | spin_unlock_irqrestore(&pd->int_lock, flags); | |
1356 | smsc9420_reg_write(pd, DMAC_INTR_ENA, 0); | |
1357 | smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF); | |
1358 | smsc9420_pci_flush_write(pd); | |
1359 | ||
1360 | if (request_irq(dev->irq, smsc9420_isr, IRQF_SHARED | IRQF_DISABLED, | |
1361 | DRV_NAME, pd)) { | |
1362 | smsc_warn(IFUP, "Unable to use IRQ = %d", dev->irq); | |
1363 | result = -ENODEV; | |
1364 | goto out_0; | |
1365 | } | |
1366 | ||
1367 | smsc9420_dmac_soft_reset(pd); | |
1368 | ||
1369 | /* make sure MAC_CR is sane */ | |
1370 | smsc9420_reg_write(pd, MAC_CR, 0); | |
1371 | ||
1372 | smsc9420_set_mac_address(dev); | |
1373 | ||
1374 | /* Configure GPIO pins to drive LEDs */ | |
1375 | smsc9420_reg_write(pd, GPIO_CFG, | |
1376 | (GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_)); | |
1377 | ||
1378 | bus_mode = BUS_MODE_DMA_BURST_LENGTH_16; | |
1379 | ||
1380 | #ifdef __BIG_ENDIAN | |
1381 | bus_mode |= BUS_MODE_DBO_; | |
1382 | #endif | |
1383 | ||
1384 | smsc9420_reg_write(pd, BUS_MODE, bus_mode); | |
1385 | ||
1386 | smsc9420_pci_flush_write(pd); | |
1387 | ||
1388 | /* set bus master bridge arbitration priority for Rx and TX DMA */ | |
1389 | smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1); | |
1390 | ||
1391 | smsc9420_reg_write(pd, DMAC_CONTROL, | |
1392 | (DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_)); | |
1393 | ||
1394 | smsc9420_pci_flush_write(pd); | |
1395 | ||
1396 | /* test the IRQ connection to the ISR */ | |
1397 | smsc_dbg(IFUP, "Testing ISR using IRQ %d", dev->irq); | |
16095595 | 1398 | pd->software_irq_signal = false; |
2cb37728 SG |
1399 | |
1400 | spin_lock_irqsave(&pd->int_lock, flags); | |
1401 | /* configure interrupt deassertion timer and enable interrupts */ | |
1402 | int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_; | |
1403 | int_cfg &= ~(INT_CFG_INT_DEAS_MASK); | |
1404 | int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK); | |
1405 | smsc9420_reg_write(pd, INT_CFG, int_cfg); | |
1406 | ||
1407 | /* unmask software interrupt */ | |
1408 | int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_; | |
1409 | smsc9420_reg_write(pd, INT_CTL, int_ctl); | |
1410 | spin_unlock_irqrestore(&pd->int_lock, flags); | |
1411 | smsc9420_pci_flush_write(pd); | |
1412 | ||
1413 | timeout = 1000; | |
2cb37728 SG |
1414 | while (timeout--) { |
1415 | if (pd->software_irq_signal) | |
1416 | break; | |
1417 | msleep(1); | |
1418 | } | |
1419 | ||
1420 | /* disable interrupts */ | |
1421 | spin_lock_irqsave(&pd->int_lock, flags); | |
1422 | int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); | |
1423 | smsc9420_reg_write(pd, INT_CFG, int_cfg); | |
1424 | spin_unlock_irqrestore(&pd->int_lock, flags); | |
1425 | ||
1426 | if (!pd->software_irq_signal) { | |
1427 | smsc_warn(IFUP, "ISR failed signaling test"); | |
1428 | result = -ENODEV; | |
1429 | goto out_free_irq_1; | |
1430 | } | |
1431 | ||
1432 | smsc_dbg(IFUP, "ISR passed test using IRQ %d", dev->irq); | |
1433 | ||
1434 | result = smsc9420_alloc_tx_ring(pd); | |
1435 | if (result) { | |
1436 | smsc_warn(IFUP, "Failed to Initialize tx dma ring"); | |
1437 | result = -ENOMEM; | |
1438 | goto out_free_irq_1; | |
1439 | } | |
1440 | ||
1441 | result = smsc9420_alloc_rx_ring(pd); | |
1442 | if (result) { | |
1443 | smsc_warn(IFUP, "Failed to Initialize rx dma ring"); | |
1444 | result = -ENOMEM; | |
1445 | goto out_free_tx_ring_2; | |
1446 | } | |
1447 | ||
1448 | result = smsc9420_mii_init(dev); | |
1449 | if (result) { | |
1450 | smsc_warn(IFUP, "Failed to initialize Phy"); | |
1451 | result = -ENODEV; | |
1452 | goto out_free_rx_ring_3; | |
1453 | } | |
1454 | ||
1455 | /* Bring the PHY up */ | |
1456 | phy_start(pd->phy_dev); | |
1457 | ||
1458 | napi_enable(&pd->napi); | |
1459 | ||
1460 | /* start tx and rx */ | |
1461 | mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_; | |
1462 | smsc9420_reg_write(pd, MAC_CR, mac_cr); | |
1463 | ||
1464 | dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL); | |
1465 | dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_; | |
1466 | smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control); | |
1467 | smsc9420_pci_flush_write(pd); | |
1468 | ||
1469 | dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); | |
1470 | dma_intr_ena |= | |
1471 | (DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_); | |
1472 | smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); | |
1473 | smsc9420_pci_flush_write(pd); | |
1474 | ||
1475 | netif_wake_queue(dev); | |
1476 | ||
1477 | smsc9420_reg_write(pd, RX_POLL_DEMAND, 1); | |
1478 | ||
1479 | /* enable interrupts */ | |
1480 | spin_lock_irqsave(&pd->int_lock, flags); | |
1481 | int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_; | |
1482 | smsc9420_reg_write(pd, INT_CFG, int_cfg); | |
1483 | spin_unlock_irqrestore(&pd->int_lock, flags); | |
1484 | ||
1485 | return 0; | |
1486 | ||
1487 | out_free_rx_ring_3: | |
1488 | smsc9420_free_rx_ring(pd); | |
1489 | out_free_tx_ring_2: | |
1490 | smsc9420_free_tx_ring(pd); | |
1491 | out_free_irq_1: | |
1492 | free_irq(dev->irq, pd); | |
1493 | out_0: | |
1494 | return result; | |
1495 | } | |
1496 | ||
1497 | #ifdef CONFIG_PM | |
1498 | ||
1499 | static int smsc9420_suspend(struct pci_dev *pdev, pm_message_t state) | |
1500 | { | |
1501 | struct net_device *dev = pci_get_drvdata(pdev); | |
1502 | struct smsc9420_pdata *pd = netdev_priv(dev); | |
1503 | u32 int_cfg; | |
1504 | ulong flags; | |
1505 | ||
1506 | /* disable interrupts */ | |
1507 | spin_lock_irqsave(&pd->int_lock, flags); | |
1508 | int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); | |
1509 | smsc9420_reg_write(pd, INT_CFG, int_cfg); | |
1510 | spin_unlock_irqrestore(&pd->int_lock, flags); | |
1511 | ||
1512 | if (netif_running(dev)) { | |
1513 | netif_tx_disable(dev); | |
1514 | smsc9420_stop_tx(pd); | |
1515 | smsc9420_free_tx_ring(pd); | |
1516 | ||
1517 | napi_disable(&pd->napi); | |
1518 | smsc9420_stop_rx(pd); | |
1519 | smsc9420_free_rx_ring(pd); | |
1520 | ||
1521 | free_irq(dev->irq, pd); | |
1522 | ||
1523 | netif_device_detach(dev); | |
1524 | } | |
1525 | ||
1526 | pci_save_state(pdev); | |
1527 | pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); | |
1528 | pci_disable_device(pdev); | |
1529 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
1530 | ||
1531 | return 0; | |
1532 | } | |
1533 | ||
1534 | static int smsc9420_resume(struct pci_dev *pdev) | |
1535 | { | |
1536 | struct net_device *dev = pci_get_drvdata(pdev); | |
1537 | struct smsc9420_pdata *pd = netdev_priv(dev); | |
1538 | int err; | |
1539 | ||
1540 | pci_set_power_state(pdev, PCI_D0); | |
1541 | pci_restore_state(pdev); | |
1542 | ||
1543 | err = pci_enable_device(pdev); | |
1544 | if (err) | |
1545 | return err; | |
1546 | ||
1547 | pci_set_master(pdev); | |
1548 | ||
1549 | err = pci_enable_wake(pdev, 0, 0); | |
1550 | if (err) | |
1551 | smsc_warn(IFUP, "pci_enable_wake failed: %d", err); | |
1552 | ||
1553 | if (netif_running(dev)) { | |
1554 | err = smsc9420_open(dev); | |
1555 | netif_device_attach(dev); | |
1556 | } | |
1557 | return err; | |
1558 | } | |
1559 | ||
1560 | #endif /* CONFIG_PM */ | |
1561 | ||
1562 | static const struct net_device_ops smsc9420_netdev_ops = { | |
1563 | .ndo_open = smsc9420_open, | |
1564 | .ndo_stop = smsc9420_stop, | |
1565 | .ndo_start_xmit = smsc9420_hard_start_xmit, | |
1566 | .ndo_get_stats = smsc9420_get_stats, | |
1567 | .ndo_set_multicast_list = smsc9420_set_multicast_list, | |
1568 | .ndo_do_ioctl = smsc9420_do_ioctl, | |
1569 | .ndo_validate_addr = eth_validate_addr, | |
fe96aaa1 | 1570 | .ndo_set_mac_address = eth_mac_addr, |
e312674f SG |
1571 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1572 | .ndo_poll_controller = smsc9420_poll_controller, | |
1573 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
2cb37728 SG |
1574 | }; |
1575 | ||
1576 | static int __devinit | |
1577 | smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |
1578 | { | |
1579 | struct net_device *dev; | |
1580 | struct smsc9420_pdata *pd; | |
1581 | void __iomem *virt_addr; | |
1582 | int result = 0; | |
1583 | u32 id_rev; | |
1584 | ||
1585 | printk(KERN_INFO DRV_DESCRIPTION " version " DRV_VERSION "\n"); | |
1586 | ||
1587 | /* First do the PCI initialisation */ | |
1588 | result = pci_enable_device(pdev); | |
1589 | if (unlikely(result)) { | |
1590 | printk(KERN_ERR "Cannot enable smsc9420\n"); | |
1591 | goto out_0; | |
1592 | } | |
1593 | ||
1594 | pci_set_master(pdev); | |
1595 | ||
1596 | dev = alloc_etherdev(sizeof(*pd)); | |
1597 | if (!dev) { | |
1598 | printk(KERN_ERR "ether device alloc failed\n"); | |
1599 | goto out_disable_pci_device_1; | |
1600 | } | |
1601 | ||
1602 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1603 | ||
1604 | if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) { | |
1605 | printk(KERN_ERR "Cannot find PCI device base address\n"); | |
1606 | goto out_free_netdev_2; | |
1607 | } | |
1608 | ||
1609 | if ((pci_request_regions(pdev, DRV_NAME))) { | |
1610 | printk(KERN_ERR "Cannot obtain PCI resources, aborting.\n"); | |
1611 | goto out_free_netdev_2; | |
1612 | } | |
1613 | ||
284901a9 | 1614 | if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { |
2cb37728 SG |
1615 | printk(KERN_ERR "No usable DMA configuration, aborting.\n"); |
1616 | goto out_free_regions_3; | |
1617 | } | |
1618 | ||
1619 | virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR), | |
1620 | pci_resource_len(pdev, SMSC_BAR)); | |
1621 | if (!virt_addr) { | |
1622 | printk(KERN_ERR "Cannot map device registers, aborting.\n"); | |
1623 | goto out_free_regions_3; | |
1624 | } | |
1625 | ||
1626 | /* registers are double mapped with 0 offset for LE and 0x200 for BE */ | |
1627 | virt_addr += LAN9420_CPSR_ENDIAN_OFFSET; | |
1628 | ||
1629 | dev->base_addr = (ulong)virt_addr; | |
1630 | ||
1631 | pd = netdev_priv(dev); | |
1632 | ||
1633 | /* pci descriptors are created in the PCI consistent area */ | |
1634 | pd->rx_ring = pci_alloc_consistent(pdev, | |
1635 | sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE + | |
1636 | sizeof(struct smsc9420_dma_desc) * TX_RING_SIZE, | |
1637 | &pd->rx_dma_addr); | |
1638 | ||
1639 | if (!pd->rx_ring) | |
1640 | goto out_free_io_4; | |
1641 | ||
1642 | /* descriptors are aligned due to the nature of pci_alloc_consistent */ | |
1643 | pd->tx_ring = (struct smsc9420_dma_desc *) | |
1644 | (pd->rx_ring + RX_RING_SIZE); | |
1645 | pd->tx_dma_addr = pd->rx_dma_addr + | |
1646 | sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE; | |
1647 | ||
1648 | pd->pdev = pdev; | |
1649 | pd->dev = dev; | |
1650 | pd->base_addr = virt_addr; | |
1651 | pd->msg_enable = smsc_debug; | |
1652 | pd->rx_csum = true; | |
1653 | ||
1654 | smsc_dbg(PROBE, "lan_base=0x%08lx", (ulong)virt_addr); | |
1655 | ||
1656 | id_rev = smsc9420_reg_read(pd, ID_REV); | |
1657 | switch (id_rev & 0xFFFF0000) { | |
1658 | case 0x94200000: | |
1659 | smsc_info(PROBE, "LAN9420 identified, ID_REV=0x%08X", id_rev); | |
1660 | break; | |
1661 | default: | |
1662 | smsc_warn(PROBE, "LAN9420 NOT identified"); | |
1663 | smsc_warn(PROBE, "ID_REV=0x%08X", id_rev); | |
1664 | goto out_free_dmadesc_5; | |
1665 | } | |
1666 | ||
1667 | smsc9420_dmac_soft_reset(pd); | |
1668 | smsc9420_eeprom_reload(pd); | |
1669 | smsc9420_check_mac_address(dev); | |
1670 | ||
1671 | dev->netdev_ops = &smsc9420_netdev_ops; | |
1672 | dev->ethtool_ops = &smsc9420_ethtool_ops; | |
1673 | dev->irq = pdev->irq; | |
1674 | ||
1675 | netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_WEIGHT); | |
1676 | ||
1677 | result = register_netdev(dev); | |
1678 | if (result) { | |
1679 | smsc_warn(PROBE, "error %i registering device", result); | |
1680 | goto out_free_dmadesc_5; | |
1681 | } | |
1682 | ||
1683 | pci_set_drvdata(pdev, dev); | |
1684 | ||
1685 | spin_lock_init(&pd->int_lock); | |
1686 | spin_lock_init(&pd->phy_lock); | |
1687 | ||
1688 | dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr); | |
1689 | ||
1690 | return 0; | |
1691 | ||
1692 | out_free_dmadesc_5: | |
1693 | pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) * | |
1694 | (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr); | |
1695 | out_free_io_4: | |
1696 | iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET); | |
1697 | out_free_regions_3: | |
1698 | pci_release_regions(pdev); | |
1699 | out_free_netdev_2: | |
1700 | free_netdev(dev); | |
1701 | out_disable_pci_device_1: | |
1702 | pci_disable_device(pdev); | |
1703 | out_0: | |
1704 | return -ENODEV; | |
1705 | } | |
1706 | ||
1707 | static void __devexit smsc9420_remove(struct pci_dev *pdev) | |
1708 | { | |
1709 | struct net_device *dev; | |
1710 | struct smsc9420_pdata *pd; | |
1711 | ||
1712 | dev = pci_get_drvdata(pdev); | |
1713 | if (!dev) | |
1714 | return; | |
1715 | ||
1716 | pci_set_drvdata(pdev, NULL); | |
1717 | ||
1718 | pd = netdev_priv(dev); | |
1719 | unregister_netdev(dev); | |
1720 | ||
1721 | /* tx_buffers and rx_buffers are freed in stop */ | |
1722 | BUG_ON(pd->tx_buffers); | |
1723 | BUG_ON(pd->rx_buffers); | |
1724 | ||
1725 | BUG_ON(!pd->tx_ring); | |
1726 | BUG_ON(!pd->rx_ring); | |
1727 | ||
1728 | pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) * | |
1729 | (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr); | |
1730 | ||
1731 | iounmap(pd->base_addr - LAN9420_CPSR_ENDIAN_OFFSET); | |
1732 | pci_release_regions(pdev); | |
1733 | free_netdev(dev); | |
1734 | pci_disable_device(pdev); | |
1735 | } | |
1736 | ||
1737 | static struct pci_driver smsc9420_driver = { | |
1738 | .name = DRV_NAME, | |
1739 | .id_table = smsc9420_id_table, | |
1740 | .probe = smsc9420_probe, | |
1741 | .remove = __devexit_p(smsc9420_remove), | |
1742 | #ifdef CONFIG_PM | |
1743 | .suspend = smsc9420_suspend, | |
1744 | .resume = smsc9420_resume, | |
1745 | #endif /* CONFIG_PM */ | |
1746 | }; | |
1747 | ||
1748 | static int __init smsc9420_init_module(void) | |
1749 | { | |
1750 | smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT); | |
1751 | ||
1752 | return pci_register_driver(&smsc9420_driver); | |
1753 | } | |
1754 | ||
1755 | static void __exit smsc9420_exit_module(void) | |
1756 | { | |
1757 | pci_unregister_driver(&smsc9420_driver); | |
1758 | } | |
1759 | ||
1760 | module_init(smsc9420_init_module); | |
1761 | module_exit(smsc9420_exit_module); |