[deliverable/linux.git] / drivers / net / spider_net.h

/*
 * Network device driver for Cell Processor-Based Blade
 *
 * (C) Copyright IBM Corp. 2005
 *
 * Authors : Utz Bacher <utz.bacher@de.ibm.com>
 *           Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef _SPIDER_NET_H
#define _SPIDER_NET_H

#define VERSION "1.1 A"

#include "sungem_phy.h"

extern int spider_net_stop(struct net_device *netdev);
extern int spider_net_open(struct net_device *netdev);

extern const struct ethtool_ops spider_net_ethtool_ops;

extern char spider_net_driver_name[];

#define SPIDER_NET_MAX_FRAME			2312
#define SPIDER_NET_MAX_MTU			2294
#define SPIDER_NET_MIN_MTU			64

#define SPIDER_NET_RXBUF_ALIGN			128

#define SPIDER_NET_RX_DESCRIPTORS_DEFAULT	256
#define SPIDER_NET_RX_DESCRIPTORS_MIN		16
#define SPIDER_NET_RX_DESCRIPTORS_MAX		512

#define SPIDER_NET_TX_DESCRIPTORS_DEFAULT	256
#define SPIDER_NET_TX_DESCRIPTORS_MIN		16
#define SPIDER_NET_TX_DESCRIPTORS_MAX		512

#define SPIDER_NET_TX_TIMER			20

#define SPIDER_NET_RX_CSUM_DEFAULT		1

#define SPIDER_NET_WATCHDOG_TIMEOUT		50*HZ
#define SPIDER_NET_NAPI_WEIGHT			64

#define SPIDER_NET_FIRMWARE_SEQS	6
#define SPIDER_NET_FIRMWARE_SEQWORDS	1024
#define SPIDER_NET_FIRMWARE_LEN		(SPIDER_NET_FIRMWARE_SEQS * \
					 SPIDER_NET_FIRMWARE_SEQWORDS * \
					 sizeof(u32))
#define SPIDER_NET_FIRMWARE_NAME	"spider_fw.bin"

/** spider_net SMMIO registers */
#define SPIDER_NET_GHIINT0STS		0x00000000
#define SPIDER_NET_GHIINT1STS		0x00000004
#define SPIDER_NET_GHIINT2STS		0x00000008
#define SPIDER_NET_GHIINT0MSK		0x00000010
#define SPIDER_NET_GHIINT1MSK		0x00000014
#define SPIDER_NET_GHIINT2MSK		0x00000018

#define SPIDER_NET_GRESUMINTNUM		0x00000020
#define SPIDER_NET_GREINTNUM		0x00000024

#define SPIDER_NET_GFFRMNUM		0x00000028
#define SPIDER_NET_GFAFRMNUM		0x0000002c
#define SPIDER_NET_GFBFRMNUM		0x00000030
#define SPIDER_NET_GFCFRMNUM		0x00000034
#define SPIDER_NET_GFDFRMNUM		0x00000038

/* clear them (don't use it) */
#define SPIDER_NET_GFREECNNUM		0x0000003c
#define SPIDER_NET_GONETIMENUM		0x00000040

#define SPIDER_NET_GTOUTFRMNUM		0x00000044

#define SPIDER_NET_GTXMDSET		0x00000050
#define SPIDER_NET_GPCCTRL		0x00000054
#define SPIDER_NET_GRXMDSET		0x00000058
#define SPIDER_NET_GIPSECINIT		0x0000005c
#define SPIDER_NET_GFTRESTRT		0x00000060
#define SPIDER_NET_GRXDMAEN		0x00000064
#define SPIDER_NET_GMRWOLCTRL		0x00000068
#define SPIDER_NET_GPCWOPCMD		0x0000006c
#define SPIDER_NET_GPCROPCMD		0x00000070
#define SPIDER_NET_GTTFRMCNT		0x00000078
#define SPIDER_NET_GTESTMD		0x0000007c

#define SPIDER_NET_GSINIT		0x00000080
#define SPIDER_NET_GSnPRGADR		0x00000084
#define SPIDER_NET_GSnPRGDAT		0x00000088

#define SPIDER_NET_GMACOPEMD		0x00000100
#define SPIDER_NET_GMACLENLMT		0x00000108
#define SPIDER_NET_GMACINTEN		0x00000118
#define SPIDER_NET_GMACPHYCTRL		0x00000120

#define SPIDER_NET_GMACAPAUSE		0x00000154
#define SPIDER_NET_GMACTXPAUSE		0x00000164

#define SPIDER_NET_GMACMODE		0x000001b0
#define SPIDER_NET_GMACBSTLMT		0x000001b4

#define SPIDER_NET_GMACUNIMACU		0x000001c0
#define SPIDER_NET_GMACUNIMACL		0x000001c8

#define SPIDER_NET_GMRMHFILnR		0x00000400
#define SPIDER_NET_MULTICAST_HASHES	256

#define SPIDER_NET_GMRUAFILnR		0x00000500
#define SPIDER_NET_GMRUA0FIL15R		0x00000578

#define SPIDER_NET_GTTQMSK		0x00000934

/* RX DMA controller registers, all 0x00000a.. are for DMA controller A,
 * 0x00000b.. for DMA controller B, etc. */
#define SPIDER_NET_GDADCHA		0x00000a00
#define SPIDER_NET_GDADMACCNTR		0x00000a04
#define SPIDER_NET_GDACTDPA		0x00000a08
#define SPIDER_NET_GDACTDCNT		0x00000a0c
#define SPIDER_NET_GDACDBADDR		0x00000a20
#define SPIDER_NET_GDACDBSIZE		0x00000a24
#define SPIDER_NET_GDACNEXTDA		0x00000a28
#define SPIDER_NET_GDACCOMST		0x00000a2c
#define SPIDER_NET_GDAWBCOMST		0x00000a30
#define SPIDER_NET_GDAWBRSIZE		0x00000a34
#define SPIDER_NET_GDAWBVSIZE		0x00000a38
#define SPIDER_NET_GDAWBTRST		0x00000a3c
#define SPIDER_NET_GDAWBTRERR		0x00000a40

/* TX DMA controller registers */
#define SPIDER_NET_GDTDCHA		0x00000e00
#define SPIDER_NET_GDTDMACCNTR		0x00000e04
#define SPIDER_NET_GDTCDPA		0x00000e08
#define SPIDER_NET_GDTDMASEL		0x00000e14

#define SPIDER_NET_ECMODE		0x00000f00
/* clock and reset control register */
#define SPIDER_NET_CKRCTRL		0x00000ff0

/** SCONFIG registers */
#define SPIDER_NET_SCONFIG_IOACTE	0x00002810

/** interrupt mask registers */
#define SPIDER_NET_INT0_MASK_VALUE	0x3f7fe2c7
#define SPIDER_NET_INT1_MASK_VALUE	0xffff7ff7
/* no MAC aborts -> auto retransmission */
#define SPIDER_NET_INT2_MASK_VALUE	0xffef7ff1

/* we rely on flagged descriptor interrupts */
#define SPIDER_NET_FRAMENUM_VALUE	0x00000000
/* set this first, then the FRAMENUM_VALUE */
#define SPIDER_NET_GFXFRAMES_VALUE	0x00000000

#define SPIDER_NET_STOP_SEQ_VALUE	0x00000000
#define SPIDER_NET_RUN_SEQ_VALUE	0x0000007e

#define SPIDER_NET_PHY_CTRL_VALUE	0x00040040
/* #define SPIDER_NET_PHY_CTRL_VALUE	0x01070080*/
#define SPIDER_NET_RXMODE_VALUE		0x00000011
/* auto retransmission in case of MAC aborts */
#define SPIDER_NET_TXMODE_VALUE		0x00010000
#define SPIDER_NET_RESTART_VALUE	0x00000000
#define SPIDER_NET_WOL_VALUE		0x00001111
#if 0
#define SPIDER_NET_WOL_VALUE		0x00000000
#endif
#define SPIDER_NET_IPSECINIT_VALUE	0x6f716f71

/* pause frames: automatic, no upper retransmission count */
/* outside loopback mode: ETOMOD signal dont matter, not connected */
#define SPIDER_NET_OPMODE_VALUE		0x00000063
/*#define SPIDER_NET_OPMODE_VALUE		0x001b0062*/
#define SPIDER_NET_LENLMT_VALUE		0x00000908

#define SPIDER_NET_MACAPAUSE_VALUE	0x00000800 /* about 1 ms */
#define SPIDER_NET_TXPAUSE_VALUE	0x00000000

#define SPIDER_NET_MACMODE_VALUE	0x00000001
#define SPIDER_NET_BURSTLMT_VALUE	0x00000200 /* about 16 us */

/* DMAC control register GDMACCNTR
 *
 * 1(0)				enable r/tx dma
 *  0000000				fixed to 0
 *
 *         000000			fixed to 0
 *               0(1)			en/disable descr writeback on force end
 *                0(1)			force end
 *
 *                 000000		fixed to 0
 *                       00		burst alignment: 128 bytes
 *                       11		burst alignment: 1024 bytes
 *
 *                         00000	fixed to 0
 *                              0	descr writeback size 32 bytes
 *                               0(1)	descr chain end interrupt enable
 *                                0(1)	descr status writeback enable */

/* to set RX_DMA_EN */
#define SPIDER_NET_DMA_RX_VALUE		0x80000000
#define SPIDER_NET_DMA_RX_FEND_VALUE	0x00030003
/* to set TX_DMA_EN */
#define SPIDER_NET_TX_DMA_EN           0x80000000
#define SPIDER_NET_GDTBSTA             0x00000300
#define SPIDER_NET_GDTDCEIDIS          0x00000002
#define SPIDER_NET_DMA_TX_VALUE        SPIDER_NET_TX_DMA_EN | \
                                       SPIDER_NET_GDTBSTA | \
                                       SPIDER_NET_GDTDCEIDIS

#define SPIDER_NET_DMA_TX_FEND_VALUE	0x00030003

/* SPIDER_NET_UA_DESCR_VALUE is OR'ed with the unicast address */
#define SPIDER_NET_UA_DESCR_VALUE	0x00080000
#define SPIDER_NET_PROMISC_VALUE	0x00080000
#define SPIDER_NET_NONPROMISC_VALUE	0x00000000

#define SPIDER_NET_DMASEL_VALUE		0x00000001

#define SPIDER_NET_ECMODE_VALUE		0x00000000

#define SPIDER_NET_CKRCTRL_RUN_VALUE	0x1fff010f
#define SPIDER_NET_CKRCTRL_STOP_VALUE	0x0000010f

#define SPIDER_NET_SBIMSTATE_VALUE	0x00000000
#define SPIDER_NET_SBTMSTATE_VALUE	0x00000000

/* SPIDER_NET_GHIINT0STS bits, in reverse order so that they can be used
 * with 1 << SPIDER_NET_... */
enum spider_net_int0_status {
	SPIDER_NET_GPHYINT = 0,
	SPIDER_NET_GMAC2INT,
	SPIDER_NET_GMAC1INT,
	SPIDER_NET_GIPSINT,
	SPIDER_NET_GFIFOINT,
	SPIDER_NET_GDMACINT,
	SPIDER_NET_GSYSINT,
	SPIDER_NET_GPWOPCMPINT,
	SPIDER_NET_GPROPCMPINT,
	SPIDER_NET_GPWFFINT,
	SPIDER_NET_GRMDADRINT,
	SPIDER_NET_GRMARPINT,
	SPIDER_NET_GRMMPINT,
	SPIDER_NET_GDTDEN0INT,
	SPIDER_NET_GDDDEN0INT,
	SPIDER_NET_GDCDEN0INT,
	SPIDER_NET_GDBDEN0INT,
	SPIDER_NET_GDADEN0INT,
	SPIDER_NET_GDTFDCINT,
	SPIDER_NET_GDDFDCINT,
	SPIDER_NET_GDCFDCINT,
	SPIDER_NET_GDBFDCINT,
	SPIDER_NET_GDAFDCINT,
	SPIDER_NET_GTTEDINT,
	SPIDER_NET_GDTDCEINT,
	SPIDER_NET_GRFDNMINT,
	SPIDER_NET_GRFCNMINT,
	SPIDER_NET_GRFBNMINT,
	SPIDER_NET_GRFANMINT,
	SPIDER_NET_GRFNMINT,
	SPIDER_NET_G1TMCNTINT,
	SPIDER_NET_GFREECNTINT
};
/* GHIINT1STS bits */
enum spider_net_int1_status {
	SPIDER_NET_GTMFLLINT = 0,
	SPIDER_NET_GRMFLLINT,
	SPIDER_NET_GTMSHTINT,
	SPIDER_NET_GDTINVDINT,
	SPIDER_NET_GRFDFLLINT,
	SPIDER_NET_GDDDCEINT,
	SPIDER_NET_GDDINVDINT,
	SPIDER_NET_GRFCFLLINT,
	SPIDER_NET_GDCDCEINT,
	SPIDER_NET_GDCINVDINT,
	SPIDER_NET_GRFBFLLINT,
	SPIDER_NET_GDBDCEINT,
	SPIDER_NET_GDBINVDINT,
	SPIDER_NET_GRFAFLLINT,
	SPIDER_NET_GDADCEINT,
	SPIDER_NET_GDAINVDINT,
	SPIDER_NET_GDTRSERINT,
	SPIDER_NET_GDDRSERINT,
	SPIDER_NET_GDCRSERINT,
	SPIDER_NET_GDBRSERINT,
	SPIDER_NET_GDARSERINT,
	SPIDER_NET_GDSERINT,
	SPIDER_NET_GDTPTERINT,
	SPIDER_NET_GDDPTERINT,
	SPIDER_NET_GDCPTERINT,
	SPIDER_NET_GDBPTERINT,
	SPIDER_NET_GDAPTERINT
};
/* GHIINT2STS bits */
enum spider_net_int2_status {
	SPIDER_NET_GPROPERINT = 0,
	SPIDER_NET_GMCTCRSNGINT,
	SPIDER_NET_GMCTLCOLINT,
	SPIDER_NET_GMCTTMOTINT,
	SPIDER_NET_GMCRCAERINT,
	SPIDER_NET_GMCRCALERINT,
	SPIDER_NET_GMCRALNERINT,
	SPIDER_NET_GMCROVRINT,
	SPIDER_NET_GMCRRNTINT,
	SPIDER_NET_GMCRRXERINT,
	SPIDER_NET_GTITCSERINT,
	SPIDER_NET_GTIFMTERINT,
	SPIDER_NET_GTIPKTRVKINT,
	SPIDER_NET_GTISPINGINT,
	SPIDER_NET_GTISADNGINT,
	SPIDER_NET_GTISPDNGINT,
	SPIDER_NET_GRIFMTERINT,
	SPIDER_NET_GRIPKTRVKINT,
	SPIDER_NET_GRISPINGINT,
	SPIDER_NET_GRISADNGINT,
	SPIDER_NET_GRISPDNGINT
};

#define SPIDER_NET_TXINT	( (1 << SPIDER_NET_GTTEDINT) | \
				  (1 << SPIDER_NET_GDTDCEINT) | \
				  (1 << SPIDER_NET_GDTFDCINT) )

/* We rely on flagged descriptor interrupts */
#define SPIDER_NET_RXINT	( (1 << SPIDER_NET_GDAFDCINT) )

#define SPIDER_NET_ERRINT	( 0xffffffff & \
				  (~SPIDER_NET_TXINT) & \
				  (~SPIDER_NET_RXINT) )

#define SPIDER_NET_GPREXEC			0x80000000
#define SPIDER_NET_GPRDAT_MASK			0x0000ffff

#define SPIDER_NET_DMAC_NOINTR_COMPLETE		0x00800000
#define SPIDER_NET_DMAC_NOCS			0x00040000
#define SPIDER_NET_DMAC_TCP			0x00020000
#define SPIDER_NET_DMAC_UDP			0x00030000
#define SPIDER_NET_TXDCEST			0x08000000

#define SPIDER_NET_DESCR_IND_PROC_MASK		0xF0000000
#define SPIDER_NET_DESCR_COMPLETE		0x00000000 /* used in rx and tx */
#define SPIDER_NET_DESCR_RESPONSE_ERROR		0x10000000 /* used in rx and tx */
#define SPIDER_NET_DESCR_PROTECTION_ERROR	0x20000000 /* used in rx and tx */
#define SPIDER_NET_DESCR_FRAME_END		0x40000000 /* used in rx */
#define SPIDER_NET_DESCR_FORCE_END		0x50000000 /* used in rx and tx */
#define SPIDER_NET_DESCR_CARDOWNED		0xA0000000 /* used in rx and tx */
#define SPIDER_NET_DESCR_NOT_IN_USE		0xF0000000

struct spider_net_descr {
	/* as defined by the hardware */
	u32 buf_addr;
	u32 buf_size;
	u32 next_descr_addr;
	u32 dmac_cmd_status;
	u32 result_size;
	u32 valid_size;	/* all zeroes for tx */
	u32 data_status;
	u32 data_error;	/* all zeroes for tx */

	/* used in the driver */
	struct sk_buff *skb;
	u32 bus_addr;
	struct spider_net_descr *next;
	struct spider_net_descr *prev;
} __attribute__((aligned(32)));

struct spider_net_descr_chain {
	spinlock_t lock;
	struct spider_net_descr *head;
	struct spider_net_descr *tail;
};

/* descriptor data_status bits */
#define SPIDER_NET_RX_IPCHK		29
#define SPIDER_NET_RX_TCPCHK		28
#define SPIDER_NET_VLAN_PACKET		21
#define SPIDER_NET_DATA_STATUS_CKSUM_MASK ( (1 << SPIDER_NET_RX_IPCHK) | \
					  (1 << SPIDER_NET_RX_TCPCHK) )

/* descriptor data_error bits */
#define SPIDER_NET_RX_IPCHKERR		27
#define SPIDER_NET_RX_RXTCPCHKERR	28

#define SPIDER_NET_DATA_ERR_CKSUM_MASK	(1 << SPIDER_NET_RX_IPCHKERR)

/* the cases we don't pass the packet to the stack.
 * 701b8000 would be correct, but every packets gets that flag */
#define SPIDER_NET_DESTROY_RX_FLAGS	0x700b8000

#define SPIDER_NET_DESCR_SIZE		32

/* this will be bigger some time */
struct spider_net_options {
	int rx_csum; /* for rx: if 0 ip_summed=NONE,
			if 1 and hw has verified, ip_summed=UNNECESSARY */
};

#define SPIDER_NET_DEFAULT_MSG		( NETIF_MSG_DRV | \
					  NETIF_MSG_PROBE | \
					  NETIF_MSG_LINK | \
					  NETIF_MSG_TIMER | \
					  NETIF_MSG_IFDOWN | \
					  NETIF_MSG_IFUP | \
					  NETIF_MSG_RX_ERR | \
					  NETIF_MSG_TX_ERR | \
					  NETIF_MSG_TX_QUEUED | \
					  NETIF_MSG_INTR | \
					  NETIF_MSG_TX_DONE | \
					  NETIF_MSG_RX_STATUS | \
					  NETIF_MSG_PKTDATA | \
					  NETIF_MSG_HW | \
					  NETIF_MSG_WOL )

struct spider_net_extra_stats {
	unsigned long rx_desc_error;
	unsigned long tx_timeouts;
	unsigned long alloc_rx_skb_error;
	unsigned long rx_iommu_map_error;
	unsigned long tx_iommu_map_error;
	unsigned long rx_desc_unk_state;
};

struct spider_net_card {
	struct net_device *netdev;
	struct pci_dev *pdev;
	struct mii_phy phy;

	void __iomem *regs;

	struct spider_net_descr_chain tx_chain;
	struct spider_net_descr_chain rx_chain;

	struct net_device_stats netdev_stats;

	struct spider_net_options options;

	spinlock_t intmask_lock;
	struct tasklet_struct rxram_full_tl;
	struct timer_list tx_timer;

	struct work_struct tx_timeout_task;
	atomic_t tx_timeout_task_counter;
	wait_queue_head_t waitq;

	/* for ethtool */
	int msg_enable;
	int rx_desc;
	int tx_desc;
	struct spider_net_extra_stats spider_stats;

	struct spider_net_descr descr[0];
};

#define pr_err(fmt,arg...) \
	printk(KERN_ERR fmt ,##arg)

#endif
Commit	Line	Data
aaec0fab JO	1	/*
	2	* Network device driver for Cell Processor-Based Blade
	3	*
	4	* (C) Copyright IBM Corp. 2005
	5	*
	6	* Authors : Utz Bacher <utz.bacher@de.ibm.com>
	7	* Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2, or (at your option)
	12	* any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	22	*/
	23
	24	#ifndef _SPIDER_NET_H
	25	#define _SPIDER_NET_H
	26
90f10841 LV	27	#define VERSION "1.1 A"
90f10841 LV	28
aaec0fab JO	29	#include "sungem_phy.h"
	30
	31	extern int spider_net_stop(struct net_device *netdev);
	32	extern int spider_net_open(struct net_device *netdev);
	33
7282d491	34	extern const struct ethtool_ops spider_net_ethtool_ops;
aaec0fab JO	35
	36	extern char spider_net_driver_name[];
	37
11f1a52b AB	38	#define SPIDER_NET_MAX_FRAME 2312
11f1a52b AB	39	#define SPIDER_NET_MAX_MTU 2294
aaec0fab JO	40	#define SPIDER_NET_MIN_MTU 64
	41
	42	#define SPIDER_NET_RXBUF_ALIGN 128
	43
11f1a52b	44	#define SPIDER_NET_RX_DESCRIPTORS_DEFAULT 256
aaec0fab	45	#define SPIDER_NET_RX_DESCRIPTORS_MIN 16
11f1a52b	46	#define SPIDER_NET_RX_DESCRIPTORS_MAX 512
aaec0fab	47
11f1a52b	48	#define SPIDER_NET_TX_DESCRIPTORS_DEFAULT 256
aaec0fab	49	#define SPIDER_NET_TX_DESCRIPTORS_MIN 16
11f1a52b AB	50	#define SPIDER_NET_TX_DESCRIPTORS_MAX 512
	51
	52	#define SPIDER_NET_TX_TIMER 20
aaec0fab JO	53
	54	#define SPIDER_NET_RX_CSUM_DEFAULT 1
	55
11f1a52b AB	56	#define SPIDER_NET_WATCHDOG_TIMEOUT 50*HZ
11f1a52b AB	57	#define SPIDER_NET_NAPI_WEIGHT 64
aaec0fab	58
11f1a52b AB	59	#define SPIDER_NET_FIRMWARE_SEQS 6
	60	#define SPIDER_NET_FIRMWARE_SEQWORDS 1024
	61	#define SPIDER_NET_FIRMWARE_LEN (SPIDER_NET_FIRMWARE_SEQS * \
	62	SPIDER_NET_FIRMWARE_SEQWORDS * \
	63	sizeof(u32))
aaec0fab JO	64	#define SPIDER_NET_FIRMWARE_NAME "spider_fw.bin"
	65
	66	/** spider_net SMMIO registers */
	67	#define SPIDER_NET_GHIINT0STS 0x00000000
	68	#define SPIDER_NET_GHIINT1STS 0x00000004
	69	#define SPIDER_NET_GHIINT2STS 0x00000008
	70	#define SPIDER_NET_GHIINT0MSK 0x00000010
	71	#define SPIDER_NET_GHIINT1MSK 0x00000014
	72	#define SPIDER_NET_GHIINT2MSK 0x00000018
	73
	74	#define SPIDER_NET_GRESUMINTNUM 0x00000020
	75	#define SPIDER_NET_GREINTNUM 0x00000024
	76
	77	#define SPIDER_NET_GFFRMNUM 0x00000028
	78	#define SPIDER_NET_GFAFRMNUM 0x0000002c
	79	#define SPIDER_NET_GFBFRMNUM 0x00000030
	80	#define SPIDER_NET_GFCFRMNUM 0x00000034
	81	#define SPIDER_NET_GFDFRMNUM 0x00000038
	82
	83	/* clear them (don't use it) */
	84	#define SPIDER_NET_GFREECNNUM 0x0000003c
	85	#define SPIDER_NET_GONETIMENUM 0x00000040
	86
	87	#define SPIDER_NET_GTOUTFRMNUM 0x00000044
	88
	89	#define SPIDER_NET_GTXMDSET 0x00000050
	90	#define SPIDER_NET_GPCCTRL 0x00000054
	91	#define SPIDER_NET_GRXMDSET 0x00000058
	92	#define SPIDER_NET_GIPSECINIT 0x0000005c
	93	#define SPIDER_NET_GFTRESTRT 0x00000060
	94	#define SPIDER_NET_GRXDMAEN 0x00000064
	95	#define SPIDER_NET_GMRWOLCTRL 0x00000068
	96	#define SPIDER_NET_GPCWOPCMD 0x0000006c
	97	#define SPIDER_NET_GPCROPCMD 0x00000070
	98	#define SPIDER_NET_GTTFRMCNT 0x00000078
	99	#define SPIDER_NET_GTESTMD 0x0000007c
	100
	101	#define SPIDER_NET_GSINIT 0x00000080
	102	#define SPIDER_NET_GSnPRGADR 0x00000084
	103	#define SPIDER_NET_GSnPRGDAT 0x00000088
	104
	105	#define SPIDER_NET_GMACOPEMD 0x00000100
	106	#define SPIDER_NET_GMACLENLMT 0x00000108
	107	#define SPIDER_NET_GMACINTEN 0x00000118
	108	#define SPIDER_NET_GMACPHYCTRL 0x00000120
	109
	110	#define SPIDER_NET_GMACAPAUSE 0x00000154
	111	#define SPIDER_NET_GMACTXPAUSE 0x00000164
	112
	113	#define SPIDER_NET_GMACMODE 0x000001b0
	114	#define SPIDER_NET_GMACBSTLMT 0x000001b4
	115
	116	#define SPIDER_NET_GMACUNIMACU 0x000001c0
	117	#define SPIDER_NET_GMACUNIMACL 0x000001c8
	118
	119	#define SPIDER_NET_GMRMHFILnR 0x00000400
	120	#define SPIDER_NET_MULTICAST_HASHES 256
	121
	122	#define SPIDER_NET_GMRUAFILnR 0x00000500
	123	#define SPIDER_NET_GMRUA0FIL15R 0x00000578
	124
b636d17a JO	125	#define SPIDER_NET_GTTQMSK 0x00000934
b636d17a JO	126
aaec0fab JO	127	/* RX DMA controller registers, all 0x00000a.. are for DMA controller A,
	128	* 0x00000b.. for DMA controller B, etc. */
	129	#define SPIDER_NET_GDADCHA 0x00000a00
	130	#define SPIDER_NET_GDADMACCNTR 0x00000a04
	131	#define SPIDER_NET_GDACTDPA 0x00000a08
	132	#define SPIDER_NET_GDACTDCNT 0x00000a0c
	133	#define SPIDER_NET_GDACDBADDR 0x00000a20
	134	#define SPIDER_NET_GDACDBSIZE 0x00000a24
	135	#define SPIDER_NET_GDACNEXTDA 0x00000a28
	136	#define SPIDER_NET_GDACCOMST 0x00000a2c
	137	#define SPIDER_NET_GDAWBCOMST 0x00000a30
	138	#define SPIDER_NET_GDAWBRSIZE 0x00000a34
	139	#define SPIDER_NET_GDAWBVSIZE 0x00000a38
	140	#define SPIDER_NET_GDAWBTRST 0x00000a3c
	141	#define SPIDER_NET_GDAWBTRERR 0x00000a40
	142
	143	/* TX DMA controller registers */
	144	#define SPIDER_NET_GDTDCHA 0x00000e00
	145	#define SPIDER_NET_GDTDMACCNTR 0x00000e04
	146	#define SPIDER_NET_GDTCDPA 0x00000e08
	147	#define SPIDER_NET_GDTDMASEL 0x00000e14
	148
	149	#define SPIDER_NET_ECMODE 0x00000f00
	150	/* clock and reset control register */
	151	#define SPIDER_NET_CKRCTRL 0x00000ff0
	152
	153	/** SCONFIG registers */
	154	#define SPIDER_NET_SCONFIG_IOACTE 0x00002810
	155
11f1a52b AB	156	/** interrupt mask registers */
	157	#define SPIDER_NET_INT0_MASK_VALUE 0x3f7fe2c7
	158	#define SPIDER_NET_INT1_MASK_VALUE 0xffff7ff7
aaec0fab	159	/* no MAC aborts -> auto retransmission */
11f1a52b	160	#define SPIDER_NET_INT2_MASK_VALUE 0xffef7ff1
aaec0fab	161
aaec0fab JO	162	/* we rely on flagged descriptor interrupts */
	163	#define SPIDER_NET_FRAMENUM_VALUE 0x00000000
	164	/* set this first, then the FRAMENUM_VALUE */
	165	#define SPIDER_NET_GFXFRAMES_VALUE 0x00000000
	166
	167	#define SPIDER_NET_STOP_SEQ_VALUE 0x00000000
	168	#define SPIDER_NET_RUN_SEQ_VALUE 0x0000007e
	169
	170	#define SPIDER_NET_PHY_CTRL_VALUE 0x00040040
	171	/* #define SPIDER_NET_PHY_CTRL_VALUE 0x01070080*/
	172	#define SPIDER_NET_RXMODE_VALUE 0x00000011
	173	/* auto retransmission in case of MAC aborts */
	174	#define SPIDER_NET_TXMODE_VALUE 0x00010000
	175	#define SPIDER_NET_RESTART_VALUE 0x00000000
	176	#define SPIDER_NET_WOL_VALUE 0x00001111
	177	#if 0
	178	#define SPIDER_NET_WOL_VALUE 0x00000000
	179	#endif
11f1a52b	180	#define SPIDER_NET_IPSECINIT_VALUE 0x6f716f71
aaec0fab JO	181
	182	/* pause frames: automatic, no upper retransmission count */
	183	/* outside loopback mode: ETOMOD signal dont matter, not connected */
	184	#define SPIDER_NET_OPMODE_VALUE 0x00000063
	185	/#define SPIDER_NET_OPMODE_VALUE 0x001b0062/
	186	#define SPIDER_NET_LENLMT_VALUE 0x00000908
	187
	188	#define SPIDER_NET_MACAPAUSE_VALUE 0x00000800 /* about 1 ms */
	189	#define SPIDER_NET_TXPAUSE_VALUE 0x00000000
	190
	191	#define SPIDER_NET_MACMODE_VALUE 0x00000001
	192	#define SPIDER_NET_BURSTLMT_VALUE 0x00000200 /* about 16 us */
	193
ded8028a LV	194	/* DMAC control register GDMACCNTR
	195	*
	196	* 1(0) enable r/tx dma
aaec0fab JO	197	* 0000000 fixed to 0
	198	*
	199	* 000000 fixed to 0
	200	* 0(1) en/disable descr writeback on force end
	201	* 0(1) force end
	202	*
	203	* 000000 fixed to 0
	204	* 00 burst alignment: 128 bytes
ded8028a	205	* 11 burst alignment: 1024 bytes
aaec0fab JO	206	*
	207	* 00000 fixed to 0
	208	* 0 descr writeback size 32 bytes
	209	* 0(1) descr chain end interrupt enable
	210	* 0(1) descr status writeback enable */
	211
	212	/* to set RX_DMA_EN */
	213	#define SPIDER_NET_DMA_RX_VALUE 0x80000000
	214	#define SPIDER_NET_DMA_RX_FEND_VALUE 0x00030003
	215	/* to set TX_DMA_EN */
ded8028a LV	216	#define SPIDER_NET_TX_DMA_EN 0x80000000
	217	#define SPIDER_NET_GDTBSTA 0x00000300
	218	#define SPIDER_NET_GDTDCEIDIS 0x00000002
	219	#define SPIDER_NET_DMA_TX_VALUE SPIDER_NET_TX_DMA_EN \| \
	220	SPIDER_NET_GDTBSTA \| \
	221	SPIDER_NET_GDTDCEIDIS
	222
aaec0fab JO	223	#define SPIDER_NET_DMA_TX_FEND_VALUE 0x00030003
	224
	225	/* SPIDER_NET_UA_DESCR_VALUE is OR'ed with the unicast address */
	226	#define SPIDER_NET_UA_DESCR_VALUE 0x00080000
	227	#define SPIDER_NET_PROMISC_VALUE 0x00080000
	228	#define SPIDER_NET_NONPROMISC_VALUE 0x00000000
	229
	230	#define SPIDER_NET_DMASEL_VALUE 0x00000001
	231
	232	#define SPIDER_NET_ECMODE_VALUE 0x00000000
	233
	234	#define SPIDER_NET_CKRCTRL_RUN_VALUE 0x1fff010f
	235	#define SPIDER_NET_CKRCTRL_STOP_VALUE 0x0000010f
	236
	237	#define SPIDER_NET_SBIMSTATE_VALUE 0x00000000
	238	#define SPIDER_NET_SBTMSTATE_VALUE 0x00000000
	239
	240	/* SPIDER_NET_GHIINT0STS bits, in reverse order so that they can be used
	241	* with 1 << SPIDER_NET_... */
	242	enum spider_net_int0_status {
	243	SPIDER_NET_GPHYINT = 0,
	244	SPIDER_NET_GMAC2INT,
	245	SPIDER_NET_GMAC1INT,
	246	SPIDER_NET_GIPSINT,
	247	SPIDER_NET_GFIFOINT,
	248	SPIDER_NET_GDMACINT,
	249	SPIDER_NET_GSYSINT,
	250	SPIDER_NET_GPWOPCMPINT,
	251	SPIDER_NET_GPROPCMPINT,
	252	SPIDER_NET_GPWFFINT,
	253	SPIDER_NET_GRMDADRINT,
	254	SPIDER_NET_GRMARPINT,
	255	SPIDER_NET_GRMMPINT,
	256	SPIDER_NET_GDTDEN0INT,
	257	SPIDER_NET_GDDDEN0INT,
	258	SPIDER_NET_GDCDEN0INT,
	259	SPIDER_NET_GDBDEN0INT,
	260	SPIDER_NET_GDADEN0INT,
	261	SPIDER_NET_GDTFDCINT,
	262	SPIDER_NET_GDDFDCINT,
	263	SPIDER_NET_GDCFDCINT,
	264	SPIDER_NET_GDBFDCINT,
	265	SPIDER_NET_GDAFDCINT,
	266	SPIDER_NET_GTTEDINT,
	267	SPIDER_NET_GDTDCEINT,
	268	SPIDER_NET_GRFDNMINT,
	269	SPIDER_NET_GRFCNMINT,
	270	SPIDER_NET_GRFBNMINT,
	271	SPIDER_NET_GRFANMINT,
	272	SPIDER_NET_GRFNMINT,
	273	SPIDER_NET_G1TMCNTINT,
	274	SPIDER_NET_GFREECNTINT
	275	};
	276	/* GHIINT1STS bits */
	277	enum spider_net_int1_status {
	278	SPIDER_NET_GTMFLLINT = 0,
	279	SPIDER_NET_GRMFLLINT,
	280	SPIDER_NET_GTMSHTINT,
	281	SPIDER_NET_GDTINVDINT,
	282	SPIDER_NET_GRFDFLLINT,
	283	SPIDER_NET_GDDDCEINT,
	284	SPIDER_NET_GDDINVDINT,
	285	SPIDER_NET_GRFCFLLINT,
	286	SPIDER_NET_GDCDCEINT,
287	SPIDER_NET_GDCINVDINT,
288	SPIDER_NET_GRFBFLLINT,
289	SPIDER_NET_GDBDCEINT,
290	SPIDER_NET_GDBINVDINT,
291	SPIDER_NET_GRFAFLLINT,
292	SPIDER_NET_GDADCEINT,
293	SPIDER_NET_GDAINVDINT,
294	SPIDER_NET_GDTRSERINT,
295	SPIDER_NET_GDDRSERINT,
296	SPIDER_NET_GDCRSERINT,
297	SPIDER_NET_GDBRSERINT,
298	SPIDER_NET_GDARSERINT,
299	SPIDER_NET_GDSERINT,
300	SPIDER_NET_GDTPTERINT,
301	SPIDER_NET_GDDPTERINT,
302	SPIDER_NET_GDCPTERINT,
303	SPIDER_NET_GDBPTERINT,
304	SPIDER_NET_GDAPTERINT
305	};
306	/* GHIINT2STS bits */
307	enum spider_net_int2_status {
308	SPIDER_NET_GPROPERINT = 0,
309	SPIDER_NET_GMCTCRSNGINT,
310	SPIDER_NET_GMCTLCOLINT,
311	SPIDER_NET_GMCTTMOTINT,
312	SPIDER_NET_GMCRCAERINT,
313	SPIDER_NET_GMCRCALERINT,
314	SPIDER_NET_GMCRALNERINT,
315	SPIDER_NET_GMCROVRINT,
316	SPIDER_NET_GMCRRNTINT,
317	SPIDER_NET_GMCRRXERINT,
318	SPIDER_NET_GTITCSERINT,
319	SPIDER_NET_GTIFMTERINT,
320	SPIDER_NET_GTIPKTRVKINT,
321	SPIDER_NET_GTISPINGINT,
322	SPIDER_NET_GTISADNGINT,
323	SPIDER_NET_GTISPDNGINT,
324	SPIDER_NET_GRIFMTERINT,
325	SPIDER_NET_GRIPKTRVKINT,
326	SPIDER_NET_GRISPINGINT,
327	SPIDER_NET_GRISADNGINT,
328	SPIDER_NET_GRISPDNGINT
329	};
330
331	#define SPIDER_NET_TXINT ( (1 << SPIDER_NET_GTTEDINT) \| \
332	(1 << SPIDER_NET_GDTDCEINT) \| \
333	(1 << SPIDER_NET_GDTFDCINT) )
334
43932d93 LV	335	/* We rely on flagged descriptor interrupts */
43932d93 LV	336	#define SPIDER_NET_RXINT ( (1 << SPIDER_NET_GDAFDCINT) )
aaec0fab	337
11f1a52b AB	338	#define SPIDER_NET_ERRINT ( 0xffffffff & \
	339	(~SPIDER_NET_TXINT) & \
	340	(~SPIDER_NET_RXINT) )
	341
bdd01503 JO	342	#define SPIDER_NET_GPREXEC 0x80000000
bdd01503 JO	343	#define SPIDER_NET_GPRDAT_MASK 0x0000ffff
aaec0fab	344
bdd01503 JO	345	#define SPIDER_NET_DMAC_NOINTR_COMPLETE 0x00800000
	346	#define SPIDER_NET_DMAC_NOCS 0x00040000
	347	#define SPIDER_NET_DMAC_TCP 0x00020000
	348	#define SPIDER_NET_DMAC_UDP 0x00030000
	349	#define SPIDER_NET_TXDCEST 0x08000000
	350
	351	#define SPIDER_NET_DESCR_IND_PROC_MASK 0xF0000000
	352	#define SPIDER_NET_DESCR_COMPLETE 0x00000000 /* used in rx and tx */
	353	#define SPIDER_NET_DESCR_RESPONSE_ERROR 0x10000000 /* used in rx and tx */
	354	#define SPIDER_NET_DESCR_PROTECTION_ERROR 0x20000000 /* used in rx and tx */
	355	#define SPIDER_NET_DESCR_FRAME_END 0x40000000 /* used in rx */
	356	#define SPIDER_NET_DESCR_FORCE_END 0x50000000 /* used in rx and tx */
	357	#define SPIDER_NET_DESCR_CARDOWNED 0xA0000000 /* used in rx and tx */
	358	#define SPIDER_NET_DESCR_NOT_IN_USE 0xF0000000
aaec0fab JO	359
	360	struct spider_net_descr {
	361	/* as defined by the hardware */
8e0a613b	362	u32 buf_addr;
aaec0fab	363	u32 buf_size;
8e0a613b	364	u32 next_descr_addr;
aaec0fab JO	365	u32 dmac_cmd_status;
	366	u32 result_size;
	367	u32 valid_size; /* all zeroes for tx */
	368	u32 data_status;
	369	u32 data_error; /* all zeroes for tx */
	370
	371	/* used in the driver */
	372	struct sk_buff *skb;
11f1a52b	373	u32 bus_addr;
aaec0fab JO	374	struct spider_net_descr *next;
	375	struct spider_net_descr *prev;
	376	} __attribute__((aligned(32)));
	377
	378	struct spider_net_descr_chain {
bdd01503	379	spinlock_t lock;
aaec0fab JO	380	struct spider_net_descr *head;
	381	struct spider_net_descr *tail;
	382	};
	383
	384	/* descriptor data_status bits */
11f1a52b AB	385	#define SPIDER_NET_RX_IPCHK 29
11f1a52b AB	386	#define SPIDER_NET_RX_TCPCHK 28
aaec0fab	387	#define SPIDER_NET_VLAN_PACKET 21
11f1a52b AB	388	#define SPIDER_NET_DATA_STATUS_CKSUM_MASK ( (1 << SPIDER_NET_RX_IPCHK) \| \
11f1a52b AB	389	(1 << SPIDER_NET_RX_TCPCHK) )
aaec0fab JO	390
aaec0fab JO	391	/* descriptor data_error bits */
11f1a52b AB	392	#define SPIDER_NET_RX_IPCHKERR 27
	393	#define SPIDER_NET_RX_RXTCPCHKERR 28
	394
	395	#define SPIDER_NET_DATA_ERR_CKSUM_MASK (1 << SPIDER_NET_RX_IPCHKERR)
aaec0fab	396
11f1a52b AB	397	/* the cases we don't pass the packet to the stack.
	398	* 701b8000 would be correct, but every packets gets that flag */
	399	#define SPIDER_NET_DESTROY_RX_FLAGS 0x700b8000
aaec0fab JO	400
	401	#define SPIDER_NET_DESCR_SIZE 32
	402
	403	/* this will be bigger some time */
	404	struct spider_net_options {
	405	int rx_csum; /* for rx: if 0 ip_summed=NONE,
	406	if 1 and hw has verified, ip_summed=UNNECESSARY */
	407	};
	408
	409	#define SPIDER_NET_DEFAULT_MSG ( NETIF_MSG_DRV \| \
	410	NETIF_MSG_PROBE \| \
	411	NETIF_MSG_LINK \| \
	412	NETIF_MSG_TIMER \| \
	413	NETIF_MSG_IFDOWN \| \
	414	NETIF_MSG_IFUP \| \
	415	NETIF_MSG_RX_ERR \| \
	416	NETIF_MSG_TX_ERR \| \
	417	NETIF_MSG_TX_QUEUED \| \
	418	NETIF_MSG_INTR \| \
	419	NETIF_MSG_TX_DONE \| \
	420	NETIF_MSG_RX_STATUS \| \
	421	NETIF_MSG_PKTDATA \| \
	422	NETIF_MSG_HW \| \
	423	NETIF_MSG_WOL )
	424
9b6b0b81 JL	425	struct spider_net_extra_stats {
	426	unsigned long rx_desc_error;
	427	unsigned long tx_timeouts;
	428	unsigned long alloc_rx_skb_error;
	429	unsigned long rx_iommu_map_error;
	430	unsigned long tx_iommu_map_error;
	431	unsigned long rx_desc_unk_state;
	432	};
	433
aaec0fab JO	434	struct spider_net_card {
	435	struct net_device *netdev;
	436	struct pci_dev *pdev;
	437	struct mii_phy phy;
	438
	439	void __iomem *regs;
	440
	441	struct spider_net_descr_chain tx_chain;
	442	struct spider_net_descr_chain rx_chain;
aaec0fab JO	443
	444	struct net_device_stats netdev_stats;
	445
	446	struct spider_net_options options;
	447
	448	spinlock_t intmask_lock;
11f1a52b AB	449	struct tasklet_struct rxram_full_tl;
11f1a52b AB	450	struct timer_list tx_timer;
aaec0fab JO	451
	452	struct work_struct tx_timeout_task;
	453	atomic_t tx_timeout_task_counter;
	454	wait_queue_head_t waitq;
	455
	456	/* for ethtool */
	457	int msg_enable;
b68a60e5 JL	458	int rx_desc;
b68a60e5 JL	459	int tx_desc;
9b6b0b81	460	struct spider_net_extra_stats spider_stats;
b68a60e5	461
aaec0fab JO	462	struct spider_net_descr descr[0];
	463	};
	464
	465	#define pr_err(fmt,arg...) \
	466	printk(KERN_ERR fmt ,##arg)
	467
	468	#endif