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21d437cc GC |
1 | /******************************************************************************* |
2 | This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. | |
3 | DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for | |
4 | developing this code. | |
5 | ||
6 | This only implements the mac core functions for this chip. | |
7 | ||
8 | Copyright (C) 2007-2009 STMicroelectronics Ltd | |
9 | ||
10 | This program is free software; you can redistribute it and/or modify it | |
11 | under the terms and conditions of the GNU General Public License, | |
12 | version 2, as published by the Free Software Foundation. | |
13 | ||
14 | This program is distributed in the hope it will be useful, but WITHOUT | |
15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License along with | |
20 | this program; if not, write to the Free Software Foundation, Inc., | |
21 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
22 | ||
23 | The full GNU General Public License is included in this distribution in | |
24 | the file called "COPYING". | |
25 | ||
26 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
27 | *******************************************************************************/ | |
28 | ||
29 | #include <linux/crc32.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
21d437cc GC |
31 | #include "dwmac1000.h" |
32 | ||
ad01b7d4 | 33 | static void dwmac1000_core_init(void __iomem *ioaddr) |
21d437cc GC |
34 | { |
35 | u32 value = readl(ioaddr + GMAC_CONTROL); | |
36 | value |= GMAC_CORE_INIT; | |
37 | writel(value, ioaddr + GMAC_CONTROL); | |
38 | ||
39 | /* STBus Bridge Configuration */ | |
40 | /*writel(0xc5608, ioaddr + 0x00007000);*/ | |
41 | ||
42 | /* Freeze MMC counters */ | |
43 | writel(0x8, ioaddr + GMAC_MMC_CTRL); | |
44 | /* Mask GMAC interrupts */ | |
45 | writel(0x207, ioaddr + GMAC_INT_MASK); | |
46 | ||
47 | #ifdef STMMAC_VLAN_TAG_USED | |
48 | /* Tag detection without filtering */ | |
49 | writel(0x0, ioaddr + GMAC_VLAN_TAG); | |
50 | #endif | |
21d437cc GC |
51 | } |
52 | ||
ebbb293f GC |
53 | static int dwmac1000_rx_coe_supported(void __iomem *ioaddr) |
54 | { | |
55 | u32 value = readl(ioaddr + GMAC_CONTROL); | |
56 | ||
57 | value |= GMAC_CONTROL_IPC; | |
58 | writel(value, ioaddr + GMAC_CONTROL); | |
59 | ||
60 | value = readl(ioaddr + GMAC_CONTROL); | |
61 | ||
62 | return !!(value & GMAC_CONTROL_IPC); | |
63 | } | |
64 | ||
ad01b7d4 | 65 | static void dwmac1000_dump_regs(void __iomem *ioaddr) |
21d437cc GC |
66 | { |
67 | int i; | |
1f0f6388 | 68 | pr_info("\tDWMAC1000 regs (base addr = 0x%p)\n", ioaddr); |
21d437cc GC |
69 | |
70 | for (i = 0; i < 55; i++) { | |
71 | int offset = i * 4; | |
72 | pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i, | |
73 | offset, readl(ioaddr + offset)); | |
74 | } | |
21d437cc GC |
75 | } |
76 | ||
ad01b7d4 | 77 | static void dwmac1000_set_umac_addr(void __iomem *ioaddr, unsigned char *addr, |
21d437cc GC |
78 | unsigned int reg_n) |
79 | { | |
80 | stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n), | |
81 | GMAC_ADDR_LOW(reg_n)); | |
82 | } | |
83 | ||
ad01b7d4 | 84 | static void dwmac1000_get_umac_addr(void __iomem *ioaddr, unsigned char *addr, |
21d437cc GC |
85 | unsigned int reg_n) |
86 | { | |
87 | stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n), | |
88 | GMAC_ADDR_LOW(reg_n)); | |
89 | } | |
90 | ||
91 | static void dwmac1000_set_filter(struct net_device *dev) | |
92 | { | |
ad01b7d4 | 93 | void __iomem *ioaddr = (void __iomem *) dev->base_addr; |
21d437cc GC |
94 | unsigned int value = 0; |
95 | ||
56b106ae GC |
96 | CHIP_DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n", |
97 | __func__, netdev_mc_count(dev), netdev_uc_count(dev)); | |
21d437cc GC |
98 | |
99 | if (dev->flags & IFF_PROMISC) | |
100 | value = GMAC_FRAME_FILTER_PR; | |
4cd24eaf | 101 | else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE) |
21d437cc GC |
102 | || (dev->flags & IFF_ALLMULTI)) { |
103 | value = GMAC_FRAME_FILTER_PM; /* pass all multi */ | |
104 | writel(0xffffffff, ioaddr + GMAC_HASH_HIGH); | |
105 | writel(0xffffffff, ioaddr + GMAC_HASH_LOW); | |
4cd24eaf | 106 | } else if (!netdev_mc_empty(dev)) { |
21d437cc | 107 | u32 mc_filter[2]; |
22bedad3 | 108 | struct netdev_hw_addr *ha; |
21d437cc GC |
109 | |
110 | /* Hash filter for multicast */ | |
111 | value = GMAC_FRAME_FILTER_HMC; | |
112 | ||
113 | memset(mc_filter, 0, sizeof(mc_filter)); | |
22bedad3 | 114 | netdev_for_each_mc_addr(ha, dev) { |
21d437cc GC |
115 | /* The upper 6 bits of the calculated CRC are used to |
116 | index the contens of the hash table */ | |
117 | int bit_nr = | |
22bedad3 | 118 | bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26; |
21d437cc GC |
119 | /* The most significant bit determines the register to |
120 | * use (H/L) while the other 5 bits determine the bit | |
121 | * within the register. */ | |
122 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); | |
123 | } | |
124 | writel(mc_filter[0], ioaddr + GMAC_HASH_LOW); | |
125 | writel(mc_filter[1], ioaddr + GMAC_HASH_HIGH); | |
126 | } | |
127 | ||
128 | /* Handle multiple unicast addresses (perfect filtering)*/ | |
32e7bfc4 | 129 | if (netdev_uc_count(dev) > GMAC_MAX_UNICAST_ADDRESSES) |
21d437cc GC |
130 | /* Switch to promiscuous mode is more than 16 addrs |
131 | are required */ | |
132 | value |= GMAC_FRAME_FILTER_PR; | |
133 | else { | |
134 | int reg = 1; | |
135 | struct netdev_hw_addr *ha; | |
136 | ||
32e7bfc4 JP |
137 | netdev_for_each_uc_addr(ha, dev) { |
138 | dwmac1000_set_umac_addr(ioaddr, ha->addr, reg); | |
139 | reg++; | |
21d437cc GC |
140 | } |
141 | } | |
142 | ||
143 | #ifdef FRAME_FILTER_DEBUG | |
144 | /* Enable Receive all mode (to debug filtering_fail errors) */ | |
145 | value |= GMAC_FRAME_FILTER_RA; | |
146 | #endif | |
147 | writel(value, ioaddr + GMAC_FRAME_FILTER); | |
148 | ||
56b106ae | 149 | CHIP_DBG(KERN_INFO "\tFrame Filter reg: 0x%08x\n\tHash regs: " |
21d437cc GC |
150 | "HI 0x%08x, LO 0x%08x\n", readl(ioaddr + GMAC_FRAME_FILTER), |
151 | readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW)); | |
21d437cc GC |
152 | } |
153 | ||
ad01b7d4 | 154 | static void dwmac1000_flow_ctrl(void __iomem *ioaddr, unsigned int duplex, |
21d437cc GC |
155 | unsigned int fc, unsigned int pause_time) |
156 | { | |
157 | unsigned int flow = 0; | |
158 | ||
56b106ae | 159 | CHIP_DBG(KERN_DEBUG "GMAC Flow-Control:\n"); |
21d437cc | 160 | if (fc & FLOW_RX) { |
56b106ae | 161 | CHIP_DBG(KERN_DEBUG "\tReceive Flow-Control ON\n"); |
21d437cc GC |
162 | flow |= GMAC_FLOW_CTRL_RFE; |
163 | } | |
164 | if (fc & FLOW_TX) { | |
56b106ae | 165 | CHIP_DBG(KERN_DEBUG "\tTransmit Flow-Control ON\n"); |
21d437cc GC |
166 | flow |= GMAC_FLOW_CTRL_TFE; |
167 | } | |
168 | ||
169 | if (duplex) { | |
56b106ae | 170 | CHIP_DBG(KERN_DEBUG "\tduplex mode: PAUSE %d\n", pause_time); |
21d437cc GC |
171 | flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT); |
172 | } | |
173 | ||
174 | writel(flow, ioaddr + GMAC_FLOW_CTRL); | |
21d437cc GC |
175 | } |
176 | ||
ad01b7d4 | 177 | static void dwmac1000_pmt(void __iomem *ioaddr, unsigned long mode) |
21d437cc GC |
178 | { |
179 | unsigned int pmt = 0; | |
180 | ||
181 | if (mode == WAKE_MAGIC) { | |
56b106ae | 182 | CHIP_DBG(KERN_DEBUG "GMAC: WOL Magic frame\n"); |
21d437cc GC |
183 | pmt |= power_down | magic_pkt_en; |
184 | } else if (mode == WAKE_UCAST) { | |
56b106ae | 185 | CHIP_DBG(KERN_DEBUG "GMAC: WOL on global unicast\n"); |
21d437cc GC |
186 | pmt |= global_unicast; |
187 | } | |
188 | ||
189 | writel(pmt, ioaddr + GMAC_PMT); | |
21d437cc GC |
190 | } |
191 | ||
192 | ||
ad01b7d4 | 193 | static void dwmac1000_irq_status(void __iomem *ioaddr) |
21d437cc GC |
194 | { |
195 | u32 intr_status = readl(ioaddr + GMAC_INT_STATUS); | |
196 | ||
197 | /* Not used events (e.g. MMC interrupts) are not handled. */ | |
198 | if ((intr_status & mmc_tx_irq)) | |
56b106ae | 199 | CHIP_DBG(KERN_DEBUG "GMAC: MMC tx interrupt: 0x%08x\n", |
21d437cc GC |
200 | readl(ioaddr + GMAC_MMC_TX_INTR)); |
201 | if (unlikely(intr_status & mmc_rx_irq)) | |
56b106ae | 202 | CHIP_DBG(KERN_DEBUG "GMAC: MMC rx interrupt: 0x%08x\n", |
21d437cc GC |
203 | readl(ioaddr + GMAC_MMC_RX_INTR)); |
204 | if (unlikely(intr_status & mmc_rx_csum_offload_irq)) | |
56b106ae | 205 | CHIP_DBG(KERN_DEBUG "GMAC: MMC rx csum offload: 0x%08x\n", |
21d437cc GC |
206 | readl(ioaddr + GMAC_MMC_RX_CSUM_OFFLOAD)); |
207 | if (unlikely(intr_status & pmt_irq)) { | |
56b106ae | 208 | CHIP_DBG(KERN_DEBUG "GMAC: received Magic frame\n"); |
21d437cc GC |
209 | /* clear the PMT bits 5 and 6 by reading the PMT |
210 | * status register. */ | |
211 | readl(ioaddr + GMAC_PMT); | |
212 | } | |
21d437cc GC |
213 | } |
214 | ||
215 | struct stmmac_ops dwmac1000_ops = { | |
216 | .core_init = dwmac1000_core_init, | |
ebbb293f | 217 | .rx_coe = dwmac1000_rx_coe_supported, |
21d437cc GC |
218 | .dump_regs = dwmac1000_dump_regs, |
219 | .host_irq_status = dwmac1000_irq_status, | |
220 | .set_filter = dwmac1000_set_filter, | |
221 | .flow_ctrl = dwmac1000_flow_ctrl, | |
222 | .pmt = dwmac1000_pmt, | |
223 | .set_umac_addr = dwmac1000_set_umac_addr, | |
224 | .get_umac_addr = dwmac1000_get_umac_addr, | |
225 | }; | |
226 | ||
ad01b7d4 | 227 | struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr) |
21d437cc GC |
228 | { |
229 | struct mac_device_info *mac; | |
230 | u32 uid = readl(ioaddr + GMAC_VERSION); | |
231 | ||
232 | pr_info("\tDWMAC1000 - user ID: 0x%x, Synopsys ID: 0x%x\n", | |
233 | ((uid & 0x0000ff00) >> 8), (uid & 0x000000ff)); | |
234 | ||
235 | mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL); | |
1ff21906 DC |
236 | if (!mac) |
237 | return NULL; | |
21d437cc GC |
238 | |
239 | mac->mac = &dwmac1000_ops; | |
21d437cc GC |
240 | mac->dma = &dwmac1000_dma_ops; |
241 | ||
21d437cc GC |
242 | mac->link.port = GMAC_CONTROL_PS; |
243 | mac->link.duplex = GMAC_CONTROL_DM; | |
244 | mac->link.speed = GMAC_CONTROL_FES; | |
245 | mac->mii.addr = GMAC_MII_ADDR; | |
246 | mac->mii.data = GMAC_MII_DATA; | |
247 | ||
248 | return mac; | |
249 | } |