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47dd7a54 GC |
1 | /******************************************************************************* |
2 | This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. | |
3 | ST Ethernet IPs are built around a Synopsys IP Core. | |
4 | ||
5 | Copyright (C) 2007-2009 STMicroelectronics Ltd | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify it | |
8 | under the terms and conditions of the GNU General Public License, | |
9 | version 2, as published by the Free Software Foundation. | |
10 | ||
11 | This program is distributed in the hope it will be useful, but WITHOUT | |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License along with | |
17 | this program; if not, write to the Free Software Foundation, Inc., | |
18 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | ||
20 | The full GNU General Public License is included in this distribution in | |
21 | the file called "COPYING". | |
22 | ||
23 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
24 | ||
25 | Documentation available at: | |
26 | http://www.stlinux.com | |
27 | Support available at: | |
28 | https://bugzilla.stlinux.com/ | |
29 | *******************************************************************************/ | |
30 | ||
31 | #include <linux/module.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/kernel.h> | |
34 | #include <linux/interrupt.h> | |
47dd7a54 GC |
35 | #include <linux/etherdevice.h> |
36 | #include <linux/platform_device.h> | |
37 | #include <linux/ip.h> | |
38 | #include <linux/tcp.h> | |
39 | #include <linux/skbuff.h> | |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/if_ether.h> | |
42 | #include <linux/crc32.h> | |
43 | #include <linux/mii.h> | |
44 | #include <linux/phy.h> | |
45 | #include <linux/if_vlan.h> | |
46 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 47 | #include <linux/slab.h> |
70c71606 | 48 | #include <linux/prefetch.h> |
47dd7a54 GC |
49 | #include "stmmac.h" |
50 | ||
51 | #define STMMAC_RESOURCE_NAME "stmmaceth" | |
52 | #define PHY_RESOURCE_NAME "stmmacphy" | |
53 | ||
54 | #undef STMMAC_DEBUG | |
55 | /*#define STMMAC_DEBUG*/ | |
56 | #ifdef STMMAC_DEBUG | |
57 | #define DBG(nlevel, klevel, fmt, args...) \ | |
58 | ((void)(netif_msg_##nlevel(priv) && \ | |
59 | printk(KERN_##klevel fmt, ## args))) | |
60 | #else | |
61 | #define DBG(nlevel, klevel, fmt, args...) do { } while (0) | |
62 | #endif | |
63 | ||
64 | #undef STMMAC_RX_DEBUG | |
65 | /*#define STMMAC_RX_DEBUG*/ | |
66 | #ifdef STMMAC_RX_DEBUG | |
67 | #define RX_DBG(fmt, args...) printk(fmt, ## args) | |
68 | #else | |
69 | #define RX_DBG(fmt, args...) do { } while (0) | |
70 | #endif | |
71 | ||
72 | #undef STMMAC_XMIT_DEBUG | |
73 | /*#define STMMAC_XMIT_DEBUG*/ | |
74 | #ifdef STMMAC_TX_DEBUG | |
75 | #define TX_DBG(fmt, args...) printk(fmt, ## args) | |
76 | #else | |
77 | #define TX_DBG(fmt, args...) do { } while (0) | |
78 | #endif | |
79 | ||
80 | #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) | |
81 | #define JUMBO_LEN 9000 | |
82 | ||
83 | /* Module parameters */ | |
84 | #define TX_TIMEO 5000 /* default 5 seconds */ | |
85 | static int watchdog = TX_TIMEO; | |
86 | module_param(watchdog, int, S_IRUGO | S_IWUSR); | |
87 | MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds"); | |
88 | ||
89 | static int debug = -1; /* -1: default, 0: no output, 16: all */ | |
90 | module_param(debug, int, S_IRUGO | S_IWUSR); | |
91 | MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)"); | |
92 | ||
93 | static int phyaddr = -1; | |
94 | module_param(phyaddr, int, S_IRUGO); | |
95 | MODULE_PARM_DESC(phyaddr, "Physical device address"); | |
96 | ||
97 | #define DMA_TX_SIZE 256 | |
98 | static int dma_txsize = DMA_TX_SIZE; | |
99 | module_param(dma_txsize, int, S_IRUGO | S_IWUSR); | |
100 | MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list"); | |
101 | ||
102 | #define DMA_RX_SIZE 256 | |
103 | static int dma_rxsize = DMA_RX_SIZE; | |
104 | module_param(dma_rxsize, int, S_IRUGO | S_IWUSR); | |
105 | MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list"); | |
106 | ||
107 | static int flow_ctrl = FLOW_OFF; | |
108 | module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); | |
109 | MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); | |
110 | ||
111 | static int pause = PAUSE_TIME; | |
112 | module_param(pause, int, S_IRUGO | S_IWUSR); | |
113 | MODULE_PARM_DESC(pause, "Flow Control Pause Time"); | |
114 | ||
115 | #define TC_DEFAULT 64 | |
116 | static int tc = TC_DEFAULT; | |
117 | module_param(tc, int, S_IRUGO | S_IWUSR); | |
118 | MODULE_PARM_DESC(tc, "DMA threshold control value"); | |
119 | ||
47dd7a54 GC |
120 | /* Pay attention to tune this parameter; take care of both |
121 | * hardware capability and network stabitily/performance impact. | |
122 | * Many tests showed that ~4ms latency seems to be good enough. */ | |
123 | #ifdef CONFIG_STMMAC_TIMER | |
124 | #define DEFAULT_PERIODIC_RATE 256 | |
125 | static int tmrate = DEFAULT_PERIODIC_RATE; | |
126 | module_param(tmrate, int, S_IRUGO | S_IWUSR); | |
127 | MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)"); | |
128 | #endif | |
129 | ||
130 | #define DMA_BUFFER_SIZE BUF_SIZE_2KiB | |
131 | static int buf_sz = DMA_BUFFER_SIZE; | |
132 | module_param(buf_sz, int, S_IRUGO | S_IWUSR); | |
133 | MODULE_PARM_DESC(buf_sz, "DMA buffer size"); | |
134 | ||
47dd7a54 GC |
135 | static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
136 | NETIF_MSG_LINK | NETIF_MSG_IFUP | | |
137 | NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); | |
138 | ||
139 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id); | |
47dd7a54 GC |
140 | |
141 | /** | |
142 | * stmmac_verify_args - verify the driver parameters. | |
143 | * Description: it verifies if some wrong parameter is passed to the driver. | |
144 | * Note that wrong parameters are replaced with the default values. | |
145 | */ | |
146 | static void stmmac_verify_args(void) | |
147 | { | |
148 | if (unlikely(watchdog < 0)) | |
149 | watchdog = TX_TIMEO; | |
150 | if (unlikely(dma_rxsize < 0)) | |
151 | dma_rxsize = DMA_RX_SIZE; | |
152 | if (unlikely(dma_txsize < 0)) | |
153 | dma_txsize = DMA_TX_SIZE; | |
154 | if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB))) | |
155 | buf_sz = DMA_BUFFER_SIZE; | |
156 | if (unlikely(flow_ctrl > 1)) | |
157 | flow_ctrl = FLOW_AUTO; | |
158 | else if (likely(flow_ctrl < 0)) | |
159 | flow_ctrl = FLOW_OFF; | |
160 | if (unlikely((pause < 0) || (pause > 0xffff))) | |
161 | pause = PAUSE_TIME; | |
47dd7a54 GC |
162 | } |
163 | ||
164 | #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG) | |
165 | static void print_pkt(unsigned char *buf, int len) | |
166 | { | |
167 | int j; | |
168 | pr_info("len = %d byte, buf addr: 0x%p", len, buf); | |
169 | for (j = 0; j < len; j++) { | |
170 | if ((j % 16) == 0) | |
171 | pr_info("\n %03x:", j); | |
172 | pr_info(" %02x", buf[j]); | |
173 | } | |
174 | pr_info("\n"); | |
47dd7a54 GC |
175 | } |
176 | #endif | |
177 | ||
178 | /* minimum number of free TX descriptors required to wake up TX process */ | |
179 | #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4) | |
180 | ||
181 | static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) | |
182 | { | |
183 | return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; | |
184 | } | |
185 | ||
9dfeb4d9 GC |
186 | /* On some ST platforms, some HW system configuraton registers have to be |
187 | * set according to the link speed negotiated. | |
188 | */ | |
189 | static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) | |
190 | { | |
191 | struct phy_device *phydev = priv->phydev; | |
192 | ||
193 | if (likely(priv->plat->fix_mac_speed)) | |
194 | priv->plat->fix_mac_speed(priv->plat->bsp_priv, | |
195 | phydev->speed); | |
196 | } | |
197 | ||
47dd7a54 GC |
198 | /** |
199 | * stmmac_adjust_link | |
200 | * @dev: net device structure | |
201 | * Description: it adjusts the link parameters. | |
202 | */ | |
203 | static void stmmac_adjust_link(struct net_device *dev) | |
204 | { | |
205 | struct stmmac_priv *priv = netdev_priv(dev); | |
206 | struct phy_device *phydev = priv->phydev; | |
47dd7a54 GC |
207 | unsigned long flags; |
208 | int new_state = 0; | |
209 | unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; | |
210 | ||
211 | if (phydev == NULL) | |
212 | return; | |
213 | ||
214 | DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n", | |
215 | phydev->addr, phydev->link); | |
216 | ||
217 | spin_lock_irqsave(&priv->lock, flags); | |
218 | if (phydev->link) { | |
ad01b7d4 | 219 | u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
220 | |
221 | /* Now we make sure that we can be in full duplex mode. | |
222 | * If not, we operate in half-duplex mode. */ | |
223 | if (phydev->duplex != priv->oldduplex) { | |
224 | new_state = 1; | |
225 | if (!(phydev->duplex)) | |
db98a0b0 | 226 | ctrl &= ~priv->hw->link.duplex; |
47dd7a54 | 227 | else |
db98a0b0 | 228 | ctrl |= priv->hw->link.duplex; |
47dd7a54 GC |
229 | priv->oldduplex = phydev->duplex; |
230 | } | |
231 | /* Flow Control operation */ | |
232 | if (phydev->pause) | |
ad01b7d4 | 233 | priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex, |
db98a0b0 | 234 | fc, pause_time); |
47dd7a54 GC |
235 | |
236 | if (phydev->speed != priv->speed) { | |
237 | new_state = 1; | |
238 | switch (phydev->speed) { | |
239 | case 1000: | |
9dfeb4d9 | 240 | if (likely(priv->plat->has_gmac)) |
db98a0b0 | 241 | ctrl &= ~priv->hw->link.port; |
9dfeb4d9 | 242 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
243 | break; |
244 | case 100: | |
245 | case 10: | |
9dfeb4d9 | 246 | if (priv->plat->has_gmac) { |
db98a0b0 | 247 | ctrl |= priv->hw->link.port; |
47dd7a54 | 248 | if (phydev->speed == SPEED_100) { |
db98a0b0 | 249 | ctrl |= priv->hw->link.speed; |
47dd7a54 | 250 | } else { |
db98a0b0 | 251 | ctrl &= ~(priv->hw->link.speed); |
47dd7a54 GC |
252 | } |
253 | } else { | |
db98a0b0 | 254 | ctrl &= ~priv->hw->link.port; |
47dd7a54 | 255 | } |
9dfeb4d9 | 256 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
257 | break; |
258 | default: | |
259 | if (netif_msg_link(priv)) | |
260 | pr_warning("%s: Speed (%d) is not 10" | |
261 | " or 100!\n", dev->name, phydev->speed); | |
262 | break; | |
263 | } | |
264 | ||
265 | priv->speed = phydev->speed; | |
266 | } | |
267 | ||
ad01b7d4 | 268 | writel(ctrl, priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
269 | |
270 | if (!priv->oldlink) { | |
271 | new_state = 1; | |
272 | priv->oldlink = 1; | |
273 | } | |
274 | } else if (priv->oldlink) { | |
275 | new_state = 1; | |
276 | priv->oldlink = 0; | |
277 | priv->speed = 0; | |
278 | priv->oldduplex = -1; | |
279 | } | |
280 | ||
281 | if (new_state && netif_msg_link(priv)) | |
282 | phy_print_status(phydev); | |
283 | ||
284 | spin_unlock_irqrestore(&priv->lock, flags); | |
285 | ||
286 | DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n"); | |
287 | } | |
288 | ||
289 | /** | |
290 | * stmmac_init_phy - PHY initialization | |
291 | * @dev: net device structure | |
292 | * Description: it initializes the driver's PHY state, and attaches the PHY | |
293 | * to the mac driver. | |
294 | * Return value: | |
295 | * 0 on success | |
296 | */ | |
297 | static int stmmac_init_phy(struct net_device *dev) | |
298 | { | |
299 | struct stmmac_priv *priv = netdev_priv(dev); | |
300 | struct phy_device *phydev; | |
109cdd66 GC |
301 | char phy_id[MII_BUS_ID_SIZE + 3]; |
302 | char bus_id[MII_BUS_ID_SIZE]; | |
47dd7a54 GC |
303 | |
304 | priv->oldlink = 0; | |
305 | priv->speed = 0; | |
306 | priv->oldduplex = -1; | |
307 | ||
308 | if (priv->phy_addr == -1) { | |
309 | /* We don't have a PHY, so do nothing */ | |
310 | return 0; | |
311 | } | |
312 | ||
9dfeb4d9 | 313 | snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->plat->bus_id); |
109cdd66 GC |
314 | snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, |
315 | priv->phy_addr); | |
47dd7a54 GC |
316 | pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id); |
317 | ||
318 | phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0, | |
319 | priv->phy_interface); | |
320 | ||
321 | if (IS_ERR(phydev)) { | |
322 | pr_err("%s: Could not attach to PHY\n", dev->name); | |
323 | return PTR_ERR(phydev); | |
324 | } | |
325 | ||
326 | /* | |
327 | * Broken HW is sometimes missing the pull-up resistor on the | |
328 | * MDIO line, which results in reads to non-existent devices returning | |
329 | * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent | |
330 | * device as well. | |
331 | * Note: phydev->phy_id is the result of reading the UID PHY registers. | |
332 | */ | |
333 | if (phydev->phy_id == 0) { | |
334 | phy_disconnect(phydev); | |
335 | return -ENODEV; | |
336 | } | |
337 | pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" | |
338 | " Link = %d\n", dev->name, phydev->phy_id, phydev->link); | |
339 | ||
340 | priv->phydev = phydev; | |
341 | ||
342 | return 0; | |
343 | } | |
344 | ||
19449bfc | 345 | static inline void stmmac_enable_mac(void __iomem *ioaddr) |
47dd7a54 GC |
346 | { |
347 | u32 value = readl(ioaddr + MAC_CTRL_REG); | |
47dd7a54 | 348 | |
19449bfc | 349 | value |= MAC_RNABLE_RX | MAC_ENABLE_TX; |
47dd7a54 GC |
350 | writel(value, ioaddr + MAC_CTRL_REG); |
351 | } | |
352 | ||
19449bfc | 353 | static inline void stmmac_disable_mac(void __iomem *ioaddr) |
47dd7a54 GC |
354 | { |
355 | u32 value = readl(ioaddr + MAC_CTRL_REG); | |
47dd7a54 | 356 | |
19449bfc | 357 | value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX); |
47dd7a54 GC |
358 | writel(value, ioaddr + MAC_CTRL_REG); |
359 | } | |
360 | ||
361 | /** | |
362 | * display_ring | |
363 | * @p: pointer to the ring. | |
364 | * @size: size of the ring. | |
365 | * Description: display all the descriptors within the ring. | |
366 | */ | |
367 | static void display_ring(struct dma_desc *p, int size) | |
368 | { | |
369 | struct tmp_s { | |
370 | u64 a; | |
371 | unsigned int b; | |
372 | unsigned int c; | |
373 | }; | |
374 | int i; | |
375 | for (i = 0; i < size; i++) { | |
376 | struct tmp_s *x = (struct tmp_s *)(p + i); | |
377 | pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", | |
378 | i, (unsigned int)virt_to_phys(&p[i]), | |
379 | (unsigned int)(x->a), (unsigned int)((x->a) >> 32), | |
380 | x->b, x->c); | |
381 | pr_info("\n"); | |
382 | } | |
383 | } | |
384 | ||
385 | /** | |
386 | * init_dma_desc_rings - init the RX/TX descriptor rings | |
387 | * @dev: net device structure | |
388 | * Description: this function initializes the DMA RX/TX descriptors | |
389 | * and allocates the socket buffers. | |
390 | */ | |
391 | static void init_dma_desc_rings(struct net_device *dev) | |
392 | { | |
393 | int i; | |
394 | struct stmmac_priv *priv = netdev_priv(dev); | |
395 | struct sk_buff *skb; | |
396 | unsigned int txsize = priv->dma_tx_size; | |
397 | unsigned int rxsize = priv->dma_rx_size; | |
398 | unsigned int bfsize = priv->dma_buf_sz; | |
73cfe264 | 399 | int buff2_needed = 0, dis_ic = 0; |
47dd7a54 | 400 | |
47dd7a54 GC |
401 | /* Set the Buffer size according to the MTU; |
402 | * indeed, in case of jumbo we need to bump-up the buffer sizes. | |
403 | */ | |
404 | if (unlikely(dev->mtu >= BUF_SIZE_8KiB)) | |
405 | bfsize = BUF_SIZE_16KiB; | |
406 | else if (unlikely(dev->mtu >= BUF_SIZE_4KiB)) | |
407 | bfsize = BUF_SIZE_8KiB; | |
408 | else if (unlikely(dev->mtu >= BUF_SIZE_2KiB)) | |
409 | bfsize = BUF_SIZE_4KiB; | |
410 | else if (unlikely(dev->mtu >= DMA_BUFFER_SIZE)) | |
411 | bfsize = BUF_SIZE_2KiB; | |
412 | else | |
413 | bfsize = DMA_BUFFER_SIZE; | |
414 | ||
73cfe264 GC |
415 | #ifdef CONFIG_STMMAC_TIMER |
416 | /* Disable interrupts on completion for the reception if timer is on */ | |
417 | if (likely(priv->tm->enable)) | |
418 | dis_ic = 1; | |
419 | #endif | |
47dd7a54 GC |
420 | /* If the MTU exceeds 8k so use the second buffer in the chain */ |
421 | if (bfsize >= BUF_SIZE_8KiB) | |
422 | buff2_needed = 1; | |
423 | ||
424 | DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n", | |
425 | txsize, rxsize, bfsize); | |
426 | ||
427 | priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL); | |
428 | priv->rx_skbuff = | |
429 | kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL); | |
430 | priv->dma_rx = | |
431 | (struct dma_desc *)dma_alloc_coherent(priv->device, | |
432 | rxsize * | |
433 | sizeof(struct dma_desc), | |
434 | &priv->dma_rx_phy, | |
435 | GFP_KERNEL); | |
436 | priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize, | |
437 | GFP_KERNEL); | |
438 | priv->dma_tx = | |
439 | (struct dma_desc *)dma_alloc_coherent(priv->device, | |
440 | txsize * | |
441 | sizeof(struct dma_desc), | |
442 | &priv->dma_tx_phy, | |
443 | GFP_KERNEL); | |
444 | ||
445 | if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) { | |
446 | pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__); | |
447 | return; | |
448 | } | |
449 | ||
450 | DBG(probe, INFO, "stmmac (%s) DMA desc rings: virt addr (Rx %p, " | |
451 | "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n", | |
452 | dev->name, priv->dma_rx, priv->dma_tx, | |
453 | (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy); | |
454 | ||
455 | /* RX INITIALIZATION */ | |
456 | DBG(probe, INFO, "stmmac: SKB addresses:\n" | |
457 | "skb\t\tskb data\tdma data\n"); | |
458 | ||
459 | for (i = 0; i < rxsize; i++) { | |
460 | struct dma_desc *p = priv->dma_rx + i; | |
461 | ||
462 | skb = netdev_alloc_skb_ip_align(dev, bfsize); | |
463 | if (unlikely(skb == NULL)) { | |
464 | pr_err("%s: Rx init fails; skb is NULL\n", __func__); | |
465 | break; | |
466 | } | |
467 | priv->rx_skbuff[i] = skb; | |
468 | priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, | |
469 | bfsize, DMA_FROM_DEVICE); | |
470 | ||
471 | p->des2 = priv->rx_skbuff_dma[i]; | |
472 | if (unlikely(buff2_needed)) | |
473 | p->des3 = p->des2 + BUF_SIZE_8KiB; | |
474 | DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], | |
475 | priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]); | |
476 | } | |
477 | priv->cur_rx = 0; | |
478 | priv->dirty_rx = (unsigned int)(i - rxsize); | |
479 | priv->dma_buf_sz = bfsize; | |
480 | buf_sz = bfsize; | |
481 | ||
482 | /* TX INITIALIZATION */ | |
483 | for (i = 0; i < txsize; i++) { | |
484 | priv->tx_skbuff[i] = NULL; | |
485 | priv->dma_tx[i].des2 = 0; | |
486 | } | |
487 | priv->dirty_tx = 0; | |
488 | priv->cur_tx = 0; | |
489 | ||
490 | /* Clear the Rx/Tx descriptors */ | |
db98a0b0 GC |
491 | priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic); |
492 | priv->hw->desc->init_tx_desc(priv->dma_tx, txsize); | |
47dd7a54 GC |
493 | |
494 | if (netif_msg_hw(priv)) { | |
495 | pr_info("RX descriptor ring:\n"); | |
496 | display_ring(priv->dma_rx, rxsize); | |
497 | pr_info("TX descriptor ring:\n"); | |
498 | display_ring(priv->dma_tx, txsize); | |
499 | } | |
47dd7a54 GC |
500 | } |
501 | ||
502 | static void dma_free_rx_skbufs(struct stmmac_priv *priv) | |
503 | { | |
504 | int i; | |
505 | ||
506 | for (i = 0; i < priv->dma_rx_size; i++) { | |
507 | if (priv->rx_skbuff[i]) { | |
508 | dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], | |
509 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
510 | dev_kfree_skb_any(priv->rx_skbuff[i]); | |
511 | } | |
512 | priv->rx_skbuff[i] = NULL; | |
513 | } | |
47dd7a54 GC |
514 | } |
515 | ||
516 | static void dma_free_tx_skbufs(struct stmmac_priv *priv) | |
517 | { | |
518 | int i; | |
519 | ||
520 | for (i = 0; i < priv->dma_tx_size; i++) { | |
521 | if (priv->tx_skbuff[i] != NULL) { | |
522 | struct dma_desc *p = priv->dma_tx + i; | |
523 | if (p->des2) | |
524 | dma_unmap_single(priv->device, p->des2, | |
db98a0b0 GC |
525 | priv->hw->desc->get_tx_len(p), |
526 | DMA_TO_DEVICE); | |
47dd7a54 GC |
527 | dev_kfree_skb_any(priv->tx_skbuff[i]); |
528 | priv->tx_skbuff[i] = NULL; | |
529 | } | |
530 | } | |
47dd7a54 GC |
531 | } |
532 | ||
533 | static void free_dma_desc_resources(struct stmmac_priv *priv) | |
534 | { | |
535 | /* Release the DMA TX/RX socket buffers */ | |
536 | dma_free_rx_skbufs(priv); | |
537 | dma_free_tx_skbufs(priv); | |
538 | ||
539 | /* Free the region of consistent memory previously allocated for | |
540 | * the DMA */ | |
541 | dma_free_coherent(priv->device, | |
542 | priv->dma_tx_size * sizeof(struct dma_desc), | |
543 | priv->dma_tx, priv->dma_tx_phy); | |
544 | dma_free_coherent(priv->device, | |
545 | priv->dma_rx_size * sizeof(struct dma_desc), | |
546 | priv->dma_rx, priv->dma_rx_phy); | |
547 | kfree(priv->rx_skbuff_dma); | |
548 | kfree(priv->rx_skbuff); | |
549 | kfree(priv->tx_skbuff); | |
47dd7a54 GC |
550 | } |
551 | ||
47dd7a54 GC |
552 | /** |
553 | * stmmac_dma_operation_mode - HW DMA operation mode | |
554 | * @priv : pointer to the private device structure. | |
555 | * Description: it sets the DMA operation mode: tx/rx DMA thresholds | |
ebbb293f | 556 | * or Store-And-Forward capability. |
47dd7a54 GC |
557 | */ |
558 | static void stmmac_dma_operation_mode(struct stmmac_priv *priv) | |
559 | { | |
61b8013a SK |
560 | if (likely(priv->plat->force_sf_dma_mode || |
561 | ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) { | |
562 | /* | |
563 | * In case of GMAC, SF mode can be enabled | |
564 | * to perform the TX COE in HW. This depends on: | |
ebbb293f GC |
565 | * 1) TX COE if actually supported |
566 | * 2) There is no bugged Jumbo frame support | |
567 | * that needs to not insert csum in the TDES. | |
568 | */ | |
569 | priv->hw->dma->dma_mode(priv->ioaddr, | |
570 | SF_DMA_MODE, SF_DMA_MODE); | |
571 | tc = SF_DMA_MODE; | |
572 | } else | |
573 | priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); | |
47dd7a54 GC |
574 | } |
575 | ||
47dd7a54 GC |
576 | /** |
577 | * stmmac_tx: | |
578 | * @priv: private driver structure | |
579 | * Description: it reclaims resources after transmission completes. | |
580 | */ | |
581 | static void stmmac_tx(struct stmmac_priv *priv) | |
582 | { | |
583 | unsigned int txsize = priv->dma_tx_size; | |
47dd7a54 GC |
584 | |
585 | while (priv->dirty_tx != priv->cur_tx) { | |
586 | int last; | |
587 | unsigned int entry = priv->dirty_tx % txsize; | |
588 | struct sk_buff *skb = priv->tx_skbuff[entry]; | |
589 | struct dma_desc *p = priv->dma_tx + entry; | |
590 | ||
591 | /* Check if the descriptor is owned by the DMA. */ | |
db98a0b0 | 592 | if (priv->hw->desc->get_tx_owner(p)) |
47dd7a54 GC |
593 | break; |
594 | ||
595 | /* Verify tx error by looking at the last segment */ | |
db98a0b0 | 596 | last = priv->hw->desc->get_tx_ls(p); |
47dd7a54 GC |
597 | if (likely(last)) { |
598 | int tx_error = | |
db98a0b0 GC |
599 | priv->hw->desc->tx_status(&priv->dev->stats, |
600 | &priv->xstats, p, | |
ad01b7d4 | 601 | priv->ioaddr); |
47dd7a54 GC |
602 | if (likely(tx_error == 0)) { |
603 | priv->dev->stats.tx_packets++; | |
604 | priv->xstats.tx_pkt_n++; | |
605 | } else | |
606 | priv->dev->stats.tx_errors++; | |
607 | } | |
608 | TX_DBG("%s: curr %d, dirty %d\n", __func__, | |
609 | priv->cur_tx, priv->dirty_tx); | |
610 | ||
611 | if (likely(p->des2)) | |
612 | dma_unmap_single(priv->device, p->des2, | |
db98a0b0 | 613 | priv->hw->desc->get_tx_len(p), |
47dd7a54 GC |
614 | DMA_TO_DEVICE); |
615 | if (unlikely(p->des3)) | |
616 | p->des3 = 0; | |
617 | ||
618 | if (likely(skb != NULL)) { | |
619 | /* | |
620 | * If there's room in the queue (limit it to size) | |
621 | * we add this skb back into the pool, | |
622 | * if it's the right size. | |
623 | */ | |
624 | if ((skb_queue_len(&priv->rx_recycle) < | |
625 | priv->dma_rx_size) && | |
626 | skb_recycle_check(skb, priv->dma_buf_sz)) | |
627 | __skb_queue_head(&priv->rx_recycle, skb); | |
628 | else | |
629 | dev_kfree_skb(skb); | |
630 | ||
631 | priv->tx_skbuff[entry] = NULL; | |
632 | } | |
633 | ||
db98a0b0 | 634 | priv->hw->desc->release_tx_desc(p); |
47dd7a54 GC |
635 | |
636 | entry = (++priv->dirty_tx) % txsize; | |
637 | } | |
638 | if (unlikely(netif_queue_stopped(priv->dev) && | |
639 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) { | |
640 | netif_tx_lock(priv->dev); | |
641 | if (netif_queue_stopped(priv->dev) && | |
642 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) { | |
643 | TX_DBG("%s: restart transmit\n", __func__); | |
644 | netif_wake_queue(priv->dev); | |
645 | } | |
646 | netif_tx_unlock(priv->dev); | |
647 | } | |
47dd7a54 GC |
648 | } |
649 | ||
650 | static inline void stmmac_enable_irq(struct stmmac_priv *priv) | |
651 | { | |
73cfe264 GC |
652 | #ifdef CONFIG_STMMAC_TIMER |
653 | if (likely(priv->tm->enable)) | |
654 | priv->tm->timer_start(tmrate); | |
655 | else | |
47dd7a54 | 656 | #endif |
ad01b7d4 | 657 | priv->hw->dma->enable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
658 | } |
659 | ||
660 | static inline void stmmac_disable_irq(struct stmmac_priv *priv) | |
661 | { | |
73cfe264 GC |
662 | #ifdef CONFIG_STMMAC_TIMER |
663 | if (likely(priv->tm->enable)) | |
664 | priv->tm->timer_stop(); | |
665 | else | |
47dd7a54 | 666 | #endif |
ad01b7d4 | 667 | priv->hw->dma->disable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
668 | } |
669 | ||
670 | static int stmmac_has_work(struct stmmac_priv *priv) | |
671 | { | |
672 | unsigned int has_work = 0; | |
673 | int rxret, tx_work = 0; | |
674 | ||
db98a0b0 | 675 | rxret = priv->hw->desc->get_rx_owner(priv->dma_rx + |
47dd7a54 GC |
676 | (priv->cur_rx % priv->dma_rx_size)); |
677 | ||
678 | if (priv->dirty_tx != priv->cur_tx) | |
679 | tx_work = 1; | |
680 | ||
681 | if (likely(!rxret || tx_work)) | |
682 | has_work = 1; | |
683 | ||
684 | return has_work; | |
685 | } | |
686 | ||
687 | static inline void _stmmac_schedule(struct stmmac_priv *priv) | |
688 | { | |
689 | if (likely(stmmac_has_work(priv))) { | |
690 | stmmac_disable_irq(priv); | |
691 | napi_schedule(&priv->napi); | |
692 | } | |
693 | } | |
694 | ||
695 | #ifdef CONFIG_STMMAC_TIMER | |
696 | void stmmac_schedule(struct net_device *dev) | |
697 | { | |
698 | struct stmmac_priv *priv = netdev_priv(dev); | |
699 | ||
700 | priv->xstats.sched_timer_n++; | |
701 | ||
702 | _stmmac_schedule(priv); | |
47dd7a54 GC |
703 | } |
704 | ||
705 | static void stmmac_no_timer_started(unsigned int x) | |
706 | {; | |
707 | }; | |
708 | ||
709 | static void stmmac_no_timer_stopped(void) | |
710 | {; | |
711 | }; | |
712 | #endif | |
713 | ||
714 | /** | |
715 | * stmmac_tx_err: | |
716 | * @priv: pointer to the private device structure | |
717 | * Description: it cleans the descriptors and restarts the transmission | |
718 | * in case of errors. | |
719 | */ | |
720 | static void stmmac_tx_err(struct stmmac_priv *priv) | |
721 | { | |
ad01b7d4 | 722 | |
47dd7a54 GC |
723 | netif_stop_queue(priv->dev); |
724 | ||
ad01b7d4 | 725 | priv->hw->dma->stop_tx(priv->ioaddr); |
47dd7a54 | 726 | dma_free_tx_skbufs(priv); |
db98a0b0 | 727 | priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); |
47dd7a54 GC |
728 | priv->dirty_tx = 0; |
729 | priv->cur_tx = 0; | |
ad01b7d4 | 730 | priv->hw->dma->start_tx(priv->ioaddr); |
47dd7a54 GC |
731 | |
732 | priv->dev->stats.tx_errors++; | |
733 | netif_wake_queue(priv->dev); | |
47dd7a54 GC |
734 | } |
735 | ||
47dd7a54 | 736 | |
aec7ff27 GC |
737 | static void stmmac_dma_interrupt(struct stmmac_priv *priv) |
738 | { | |
aec7ff27 GC |
739 | int status; |
740 | ||
ad01b7d4 | 741 | status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); |
aec7ff27 GC |
742 | if (likely(status == handle_tx_rx)) |
743 | _stmmac_schedule(priv); | |
744 | ||
745 | else if (unlikely(status == tx_hard_error_bump_tc)) { | |
746 | /* Try to bump up the dma threshold on this failure */ | |
747 | if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { | |
748 | tc += 64; | |
ad01b7d4 | 749 | priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); |
aec7ff27 | 750 | priv->xstats.threshold = tc; |
47dd7a54 | 751 | } |
aec7ff27 GC |
752 | } else if (unlikely(status == tx_hard_error)) |
753 | stmmac_tx_err(priv); | |
47dd7a54 GC |
754 | } |
755 | ||
756 | /** | |
757 | * stmmac_open - open entry point of the driver | |
758 | * @dev : pointer to the device structure. | |
759 | * Description: | |
760 | * This function is the open entry point of the driver. | |
761 | * Return value: | |
762 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
763 | * file on failure. | |
764 | */ | |
765 | static int stmmac_open(struct net_device *dev) | |
766 | { | |
767 | struct stmmac_priv *priv = netdev_priv(dev); | |
47dd7a54 GC |
768 | int ret; |
769 | ||
770 | /* Check that the MAC address is valid. If its not, refuse | |
771 | * to bring the device up. The user must specify an | |
772 | * address using the following linux command: | |
773 | * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */ | |
774 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
775 | random_ether_addr(dev->dev_addr); | |
776 | pr_warning("%s: generated random MAC address %pM\n", dev->name, | |
777 | dev->dev_addr); | |
778 | } | |
779 | ||
780 | stmmac_verify_args(); | |
781 | ||
47dd7a54 | 782 | #ifdef CONFIG_STMMAC_TIMER |
73cfe264 | 783 | priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL); |
47dd7a54 | 784 | if (unlikely(priv->tm == NULL)) { |
2381a55c | 785 | pr_err("%s: ERROR: timer memory alloc failed\n", __func__); |
47dd7a54 GC |
786 | return -ENOMEM; |
787 | } | |
788 | priv->tm->freq = tmrate; | |
789 | ||
73cfe264 GC |
790 | /* Test if the external timer can be actually used. |
791 | * In case of failure continue without timer. */ | |
47dd7a54 | 792 | if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) { |
73cfe264 | 793 | pr_warning("stmmaceth: cannot attach the external timer.\n"); |
47dd7a54 GC |
794 | priv->tm->freq = 0; |
795 | priv->tm->timer_start = stmmac_no_timer_started; | |
796 | priv->tm->timer_stop = stmmac_no_timer_stopped; | |
73cfe264 GC |
797 | } else |
798 | priv->tm->enable = 1; | |
47dd7a54 | 799 | #endif |
f66ffe28 GC |
800 | ret = stmmac_init_phy(dev); |
801 | if (unlikely(ret)) { | |
802 | pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret); | |
803 | goto open_error; | |
804 | } | |
47dd7a54 GC |
805 | |
806 | /* Create and initialize the TX/RX descriptors chains. */ | |
807 | priv->dma_tx_size = STMMAC_ALIGN(dma_txsize); | |
808 | priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize); | |
809 | priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); | |
810 | init_dma_desc_rings(dev); | |
811 | ||
812 | /* DMA initialization and SW reset */ | |
f66ffe28 GC |
813 | ret = priv->hw->dma->init(priv->ioaddr, priv->plat->pbl, |
814 | priv->dma_tx_phy, priv->dma_rx_phy); | |
815 | if (ret < 0) { | |
47dd7a54 | 816 | pr_err("%s: DMA initialization failed\n", __func__); |
f66ffe28 | 817 | goto open_error; |
47dd7a54 GC |
818 | } |
819 | ||
820 | /* Copy the MAC addr into the HW */ | |
ad01b7d4 | 821 | priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0); |
ca5f12c1 | 822 | /* If required, perform hw setup of the bus. */ |
9dfeb4d9 GC |
823 | if (priv->plat->bus_setup) |
824 | priv->plat->bus_setup(priv->ioaddr); | |
47dd7a54 | 825 | /* Initialize the MAC Core */ |
ad01b7d4 | 826 | priv->hw->mac->core_init(priv->ioaddr); |
47dd7a54 | 827 | |
ebbb293f GC |
828 | priv->rx_coe = priv->hw->mac->rx_coe(priv->ioaddr); |
829 | if (priv->rx_coe) | |
830 | pr_info("stmmac: Rx Checksum Offload Engine supported\n"); | |
9dfeb4d9 | 831 | if (priv->plat->tx_coe) |
ebbb293f | 832 | pr_info("\tTX Checksum insertion supported\n"); |
5e982f3b | 833 | netdev_update_features(dev); |
ebbb293f | 834 | |
47dd7a54 | 835 | /* Initialise the MMC (if present) to disable all interrupts. */ |
ad01b7d4 GC |
836 | writel(0xffffffff, priv->ioaddr + MMC_HIGH_INTR_MASK); |
837 | writel(0xffffffff, priv->ioaddr + MMC_LOW_INTR_MASK); | |
47dd7a54 | 838 | |
f66ffe28 GC |
839 | /* Request the IRQ lines */ |
840 | ret = request_irq(dev->irq, stmmac_interrupt, | |
841 | IRQF_SHARED, dev->name, dev); | |
842 | if (unlikely(ret < 0)) { | |
843 | pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", | |
844 | __func__, dev->irq, ret); | |
845 | goto open_error; | |
846 | } | |
847 | ||
47dd7a54 | 848 | /* Enable the MAC Rx/Tx */ |
19449bfc | 849 | stmmac_enable_mac(priv->ioaddr); |
47dd7a54 GC |
850 | |
851 | /* Set the HW DMA mode and the COE */ | |
852 | stmmac_dma_operation_mode(priv); | |
853 | ||
854 | /* Extra statistics */ | |
855 | memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); | |
856 | priv->xstats.threshold = tc; | |
857 | ||
858 | /* Start the ball rolling... */ | |
859 | DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name); | |
ad01b7d4 GC |
860 | priv->hw->dma->start_tx(priv->ioaddr); |
861 | priv->hw->dma->start_rx(priv->ioaddr); | |
47dd7a54 GC |
862 | |
863 | #ifdef CONFIG_STMMAC_TIMER | |
864 | priv->tm->timer_start(tmrate); | |
865 | #endif | |
866 | /* Dump DMA/MAC registers */ | |
867 | if (netif_msg_hw(priv)) { | |
ad01b7d4 GC |
868 | priv->hw->mac->dump_regs(priv->ioaddr); |
869 | priv->hw->dma->dump_regs(priv->ioaddr); | |
47dd7a54 GC |
870 | } |
871 | ||
872 | if (priv->phydev) | |
873 | phy_start(priv->phydev); | |
874 | ||
875 | napi_enable(&priv->napi); | |
876 | skb_queue_head_init(&priv->rx_recycle); | |
877 | netif_start_queue(dev); | |
f66ffe28 | 878 | |
47dd7a54 | 879 | return 0; |
f66ffe28 GC |
880 | |
881 | open_error: | |
882 | #ifdef CONFIG_STMMAC_TIMER | |
883 | kfree(priv->tm); | |
884 | #endif | |
885 | if (priv->phydev) | |
886 | phy_disconnect(priv->phydev); | |
887 | ||
888 | return ret; | |
47dd7a54 GC |
889 | } |
890 | ||
891 | /** | |
892 | * stmmac_release - close entry point of the driver | |
893 | * @dev : device pointer. | |
894 | * Description: | |
895 | * This is the stop entry point of the driver. | |
896 | */ | |
897 | static int stmmac_release(struct net_device *dev) | |
898 | { | |
899 | struct stmmac_priv *priv = netdev_priv(dev); | |
900 | ||
901 | /* Stop and disconnect the PHY */ | |
902 | if (priv->phydev) { | |
903 | phy_stop(priv->phydev); | |
904 | phy_disconnect(priv->phydev); | |
905 | priv->phydev = NULL; | |
906 | } | |
907 | ||
908 | netif_stop_queue(dev); | |
909 | ||
910 | #ifdef CONFIG_STMMAC_TIMER | |
911 | /* Stop and release the timer */ | |
912 | stmmac_close_ext_timer(); | |
913 | if (priv->tm != NULL) | |
914 | kfree(priv->tm); | |
915 | #endif | |
916 | napi_disable(&priv->napi); | |
917 | skb_queue_purge(&priv->rx_recycle); | |
918 | ||
919 | /* Free the IRQ lines */ | |
920 | free_irq(dev->irq, dev); | |
921 | ||
922 | /* Stop TX/RX DMA and clear the descriptors */ | |
ad01b7d4 GC |
923 | priv->hw->dma->stop_tx(priv->ioaddr); |
924 | priv->hw->dma->stop_rx(priv->ioaddr); | |
47dd7a54 GC |
925 | |
926 | /* Release and free the Rx/Tx resources */ | |
927 | free_dma_desc_resources(priv); | |
928 | ||
19449bfc | 929 | /* Disable the MAC Rx/Tx */ |
930 | stmmac_disable_mac(priv->ioaddr); | |
47dd7a54 GC |
931 | |
932 | netif_carrier_off(dev); | |
933 | ||
934 | return 0; | |
935 | } | |
936 | ||
47dd7a54 GC |
937 | static unsigned int stmmac_handle_jumbo_frames(struct sk_buff *skb, |
938 | struct net_device *dev, | |
939 | int csum_insertion) | |
940 | { | |
941 | struct stmmac_priv *priv = netdev_priv(dev); | |
942 | unsigned int nopaged_len = skb_headlen(skb); | |
943 | unsigned int txsize = priv->dma_tx_size; | |
944 | unsigned int entry = priv->cur_tx % txsize; | |
945 | struct dma_desc *desc = priv->dma_tx + entry; | |
946 | ||
947 | if (nopaged_len > BUF_SIZE_8KiB) { | |
948 | ||
949 | int buf2_size = nopaged_len - BUF_SIZE_8KiB; | |
950 | ||
951 | desc->des2 = dma_map_single(priv->device, skb->data, | |
952 | BUF_SIZE_8KiB, DMA_TO_DEVICE); | |
953 | desc->des3 = desc->des2 + BUF_SIZE_4KiB; | |
db98a0b0 GC |
954 | priv->hw->desc->prepare_tx_desc(desc, 1, BUF_SIZE_8KiB, |
955 | csum_insertion); | |
47dd7a54 GC |
956 | |
957 | entry = (++priv->cur_tx) % txsize; | |
958 | desc = priv->dma_tx + entry; | |
959 | ||
960 | desc->des2 = dma_map_single(priv->device, | |
961 | skb->data + BUF_SIZE_8KiB, | |
962 | buf2_size, DMA_TO_DEVICE); | |
963 | desc->des3 = desc->des2 + BUF_SIZE_4KiB; | |
db98a0b0 GC |
964 | priv->hw->desc->prepare_tx_desc(desc, 0, buf2_size, |
965 | csum_insertion); | |
966 | priv->hw->desc->set_tx_owner(desc); | |
47dd7a54 GC |
967 | priv->tx_skbuff[entry] = NULL; |
968 | } else { | |
969 | desc->des2 = dma_map_single(priv->device, skb->data, | |
970 | nopaged_len, DMA_TO_DEVICE); | |
971 | desc->des3 = desc->des2 + BUF_SIZE_4KiB; | |
db98a0b0 GC |
972 | priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, |
973 | csum_insertion); | |
47dd7a54 GC |
974 | } |
975 | return entry; | |
976 | } | |
977 | ||
978 | /** | |
979 | * stmmac_xmit: | |
980 | * @skb : the socket buffer | |
981 | * @dev : device pointer | |
982 | * Description : Tx entry point of the driver. | |
983 | */ | |
984 | static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) | |
985 | { | |
986 | struct stmmac_priv *priv = netdev_priv(dev); | |
987 | unsigned int txsize = priv->dma_tx_size; | |
988 | unsigned int entry; | |
989 | int i, csum_insertion = 0; | |
990 | int nfrags = skb_shinfo(skb)->nr_frags; | |
991 | struct dma_desc *desc, *first; | |
992 | ||
993 | if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { | |
994 | if (!netif_queue_stopped(dev)) { | |
995 | netif_stop_queue(dev); | |
996 | /* This is a hard error, log it. */ | |
997 | pr_err("%s: BUG! Tx Ring full when queue awake\n", | |
998 | __func__); | |
999 | } | |
1000 | return NETDEV_TX_BUSY; | |
1001 | } | |
1002 | ||
1003 | entry = priv->cur_tx % txsize; | |
1004 | ||
1005 | #ifdef STMMAC_XMIT_DEBUG | |
1006 | if ((skb->len > ETH_FRAME_LEN) || nfrags) | |
1007 | pr_info("stmmac xmit:\n" | |
1008 | "\tskb addr %p - len: %d - nopaged_len: %d\n" | |
1009 | "\tn_frags: %d - ip_summed: %d - %s gso\n", | |
1010 | skb, skb->len, skb_headlen(skb), nfrags, skb->ip_summed, | |
1011 | !skb_is_gso(skb) ? "isn't" : "is"); | |
1012 | #endif | |
1013 | ||
5e982f3b | 1014 | csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); |
47dd7a54 GC |
1015 | |
1016 | desc = priv->dma_tx + entry; | |
1017 | first = desc; | |
1018 | ||
1019 | #ifdef STMMAC_XMIT_DEBUG | |
1020 | if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN)) | |
1021 | pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n" | |
1022 | "\t\tn_frags: %d, ip_summed: %d\n", | |
1023 | skb->len, skb_headlen(skb), nfrags, skb->ip_summed); | |
1024 | #endif | |
1025 | priv->tx_skbuff[entry] = skb; | |
1026 | if (unlikely(skb->len >= BUF_SIZE_4KiB)) { | |
1027 | entry = stmmac_handle_jumbo_frames(skb, dev, csum_insertion); | |
1028 | desc = priv->dma_tx + entry; | |
1029 | } else { | |
1030 | unsigned int nopaged_len = skb_headlen(skb); | |
1031 | desc->des2 = dma_map_single(priv->device, skb->data, | |
1032 | nopaged_len, DMA_TO_DEVICE); | |
db98a0b0 GC |
1033 | priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, |
1034 | csum_insertion); | |
47dd7a54 GC |
1035 | } |
1036 | ||
1037 | for (i = 0; i < nfrags; i++) { | |
1038 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
1039 | int len = frag->size; | |
1040 | ||
1041 | entry = (++priv->cur_tx) % txsize; | |
1042 | desc = priv->dma_tx + entry; | |
1043 | ||
1044 | TX_DBG("\t[entry %d] segment len: %d\n", entry, len); | |
1045 | desc->des2 = dma_map_page(priv->device, frag->page, | |
1046 | frag->page_offset, | |
1047 | len, DMA_TO_DEVICE); | |
1048 | priv->tx_skbuff[entry] = NULL; | |
db98a0b0 | 1049 | priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion); |
eb0dc4bb | 1050 | wmb(); |
db98a0b0 | 1051 | priv->hw->desc->set_tx_owner(desc); |
47dd7a54 GC |
1052 | } |
1053 | ||
1054 | /* Interrupt on completition only for the latest segment */ | |
db98a0b0 | 1055 | priv->hw->desc->close_tx_desc(desc); |
73cfe264 | 1056 | |
47dd7a54 | 1057 | #ifdef CONFIG_STMMAC_TIMER |
73cfe264 GC |
1058 | /* Clean IC while using timer */ |
1059 | if (likely(priv->tm->enable)) | |
db98a0b0 | 1060 | priv->hw->desc->clear_tx_ic(desc); |
47dd7a54 | 1061 | #endif |
eb0dc4bb SH |
1062 | |
1063 | wmb(); | |
1064 | ||
47dd7a54 | 1065 | /* To avoid raise condition */ |
db98a0b0 | 1066 | priv->hw->desc->set_tx_owner(first); |
47dd7a54 GC |
1067 | |
1068 | priv->cur_tx++; | |
1069 | ||
1070 | #ifdef STMMAC_XMIT_DEBUG | |
1071 | if (netif_msg_pktdata(priv)) { | |
1072 | pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, " | |
1073 | "first=%p, nfrags=%d\n", | |
1074 | (priv->cur_tx % txsize), (priv->dirty_tx % txsize), | |
1075 | entry, first, nfrags); | |
1076 | display_ring(priv->dma_tx, txsize); | |
1077 | pr_info(">>> frame to be transmitted: "); | |
1078 | print_pkt(skb->data, skb->len); | |
1079 | } | |
1080 | #endif | |
1081 | if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { | |
1082 | TX_DBG("%s: stop transmitted packets\n", __func__); | |
1083 | netif_stop_queue(dev); | |
1084 | } | |
1085 | ||
1086 | dev->stats.tx_bytes += skb->len; | |
1087 | ||
3e82ce12 RC |
1088 | skb_tx_timestamp(skb); |
1089 | ||
52f64fae RC |
1090 | priv->hw->dma->enable_dma_transmission(priv->ioaddr); |
1091 | ||
47dd7a54 GC |
1092 | return NETDEV_TX_OK; |
1093 | } | |
1094 | ||
1095 | static inline void stmmac_rx_refill(struct stmmac_priv *priv) | |
1096 | { | |
1097 | unsigned int rxsize = priv->dma_rx_size; | |
1098 | int bfsize = priv->dma_buf_sz; | |
1099 | struct dma_desc *p = priv->dma_rx; | |
1100 | ||
1101 | for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) { | |
1102 | unsigned int entry = priv->dirty_rx % rxsize; | |
1103 | if (likely(priv->rx_skbuff[entry] == NULL)) { | |
1104 | struct sk_buff *skb; | |
1105 | ||
1106 | skb = __skb_dequeue(&priv->rx_recycle); | |
1107 | if (skb == NULL) | |
1108 | skb = netdev_alloc_skb_ip_align(priv->dev, | |
1109 | bfsize); | |
1110 | ||
1111 | if (unlikely(skb == NULL)) | |
1112 | break; | |
1113 | ||
1114 | priv->rx_skbuff[entry] = skb; | |
1115 | priv->rx_skbuff_dma[entry] = | |
1116 | dma_map_single(priv->device, skb->data, bfsize, | |
1117 | DMA_FROM_DEVICE); | |
1118 | ||
1119 | (p + entry)->des2 = priv->rx_skbuff_dma[entry]; | |
9dfeb4d9 | 1120 | if (unlikely(priv->plat->has_gmac)) { |
47dd7a54 GC |
1121 | if (bfsize >= BUF_SIZE_8KiB) |
1122 | (p + entry)->des3 = | |
1123 | (p + entry)->des2 + BUF_SIZE_8KiB; | |
1124 | } | |
1125 | RX_DBG(KERN_INFO "\trefill entry #%d\n", entry); | |
1126 | } | |
eb0dc4bb | 1127 | wmb(); |
db98a0b0 | 1128 | priv->hw->desc->set_rx_owner(p + entry); |
47dd7a54 | 1129 | } |
47dd7a54 GC |
1130 | } |
1131 | ||
1132 | static int stmmac_rx(struct stmmac_priv *priv, int limit) | |
1133 | { | |
1134 | unsigned int rxsize = priv->dma_rx_size; | |
1135 | unsigned int entry = priv->cur_rx % rxsize; | |
1136 | unsigned int next_entry; | |
1137 | unsigned int count = 0; | |
1138 | struct dma_desc *p = priv->dma_rx + entry; | |
1139 | struct dma_desc *p_next; | |
1140 | ||
1141 | #ifdef STMMAC_RX_DEBUG | |
1142 | if (netif_msg_hw(priv)) { | |
1143 | pr_debug(">>> stmmac_rx: descriptor ring:\n"); | |
1144 | display_ring(priv->dma_rx, rxsize); | |
1145 | } | |
1146 | #endif | |
1147 | count = 0; | |
db98a0b0 | 1148 | while (!priv->hw->desc->get_rx_owner(p)) { |
47dd7a54 GC |
1149 | int status; |
1150 | ||
1151 | if (count >= limit) | |
1152 | break; | |
1153 | ||
1154 | count++; | |
1155 | ||
1156 | next_entry = (++priv->cur_rx) % rxsize; | |
1157 | p_next = priv->dma_rx + next_entry; | |
1158 | prefetch(p_next); | |
1159 | ||
1160 | /* read the status of the incoming frame */ | |
db98a0b0 GC |
1161 | status = (priv->hw->desc->rx_status(&priv->dev->stats, |
1162 | &priv->xstats, p)); | |
47dd7a54 GC |
1163 | if (unlikely(status == discard_frame)) |
1164 | priv->dev->stats.rx_errors++; | |
1165 | else { | |
1166 | struct sk_buff *skb; | |
3eeb2997 | 1167 | int frame_len; |
47dd7a54 | 1168 | |
3eeb2997 GC |
1169 | frame_len = priv->hw->desc->get_rx_frame_len(p); |
1170 | /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 | |
1171 | * Type frames (LLC/LLC-SNAP) */ | |
1172 | if (unlikely(status != llc_snap)) | |
1173 | frame_len -= ETH_FCS_LEN; | |
47dd7a54 GC |
1174 | #ifdef STMMAC_RX_DEBUG |
1175 | if (frame_len > ETH_FRAME_LEN) | |
1176 | pr_debug("\tRX frame size %d, COE status: %d\n", | |
1177 | frame_len, status); | |
1178 | ||
1179 | if (netif_msg_hw(priv)) | |
1180 | pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", | |
1181 | p, entry, p->des2); | |
1182 | #endif | |
1183 | skb = priv->rx_skbuff[entry]; | |
1184 | if (unlikely(!skb)) { | |
1185 | pr_err("%s: Inconsistent Rx descriptor chain\n", | |
1186 | priv->dev->name); | |
1187 | priv->dev->stats.rx_dropped++; | |
1188 | break; | |
1189 | } | |
1190 | prefetch(skb->data - NET_IP_ALIGN); | |
1191 | priv->rx_skbuff[entry] = NULL; | |
1192 | ||
1193 | skb_put(skb, frame_len); | |
1194 | dma_unmap_single(priv->device, | |
1195 | priv->rx_skbuff_dma[entry], | |
1196 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
1197 | #ifdef STMMAC_RX_DEBUG | |
1198 | if (netif_msg_pktdata(priv)) { | |
1199 | pr_info(" frame received (%dbytes)", frame_len); | |
1200 | print_pkt(skb->data, frame_len); | |
1201 | } | |
1202 | #endif | |
1203 | skb->protocol = eth_type_trans(skb, priv->dev); | |
1204 | ||
1205 | if (unlikely(status == csum_none)) { | |
1206 | /* always for the old mac 10/100 */ | |
bc8acf2c | 1207 | skb_checksum_none_assert(skb); |
47dd7a54 GC |
1208 | netif_receive_skb(skb); |
1209 | } else { | |
1210 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1211 | napi_gro_receive(&priv->napi, skb); | |
1212 | } | |
1213 | ||
1214 | priv->dev->stats.rx_packets++; | |
1215 | priv->dev->stats.rx_bytes += frame_len; | |
47dd7a54 GC |
1216 | } |
1217 | entry = next_entry; | |
1218 | p = p_next; /* use prefetched values */ | |
1219 | } | |
1220 | ||
1221 | stmmac_rx_refill(priv); | |
1222 | ||
1223 | priv->xstats.rx_pkt_n += count; | |
1224 | ||
1225 | return count; | |
1226 | } | |
1227 | ||
1228 | /** | |
1229 | * stmmac_poll - stmmac poll method (NAPI) | |
1230 | * @napi : pointer to the napi structure. | |
1231 | * @budget : maximum number of packets that the current CPU can receive from | |
1232 | * all interfaces. | |
1233 | * Description : | |
1234 | * This function implements the the reception process. | |
1235 | * Also it runs the TX completion thread | |
1236 | */ | |
1237 | static int stmmac_poll(struct napi_struct *napi, int budget) | |
1238 | { | |
1239 | struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); | |
1240 | int work_done = 0; | |
1241 | ||
1242 | priv->xstats.poll_n++; | |
1243 | stmmac_tx(priv); | |
1244 | work_done = stmmac_rx(priv, budget); | |
1245 | ||
1246 | if (work_done < budget) { | |
1247 | napi_complete(napi); | |
1248 | stmmac_enable_irq(priv); | |
1249 | } | |
1250 | return work_done; | |
1251 | } | |
1252 | ||
1253 | /** | |
1254 | * stmmac_tx_timeout | |
1255 | * @dev : Pointer to net device structure | |
1256 | * Description: this function is called when a packet transmission fails to | |
1257 | * complete within a reasonable tmrate. The driver will mark the error in the | |
1258 | * netdev structure and arrange for the device to be reset to a sane state | |
1259 | * in order to transmit a new packet. | |
1260 | */ | |
1261 | static void stmmac_tx_timeout(struct net_device *dev) | |
1262 | { | |
1263 | struct stmmac_priv *priv = netdev_priv(dev); | |
1264 | ||
1265 | /* Clear Tx resources and restart transmitting again */ | |
1266 | stmmac_tx_err(priv); | |
47dd7a54 GC |
1267 | } |
1268 | ||
1269 | /* Configuration changes (passed on by ifconfig) */ | |
1270 | static int stmmac_config(struct net_device *dev, struct ifmap *map) | |
1271 | { | |
1272 | if (dev->flags & IFF_UP) /* can't act on a running interface */ | |
1273 | return -EBUSY; | |
1274 | ||
1275 | /* Don't allow changing the I/O address */ | |
1276 | if (map->base_addr != dev->base_addr) { | |
1277 | pr_warning("%s: can't change I/O address\n", dev->name); | |
1278 | return -EOPNOTSUPP; | |
1279 | } | |
1280 | ||
1281 | /* Don't allow changing the IRQ */ | |
1282 | if (map->irq != dev->irq) { | |
1283 | pr_warning("%s: can't change IRQ number %d\n", | |
1284 | dev->name, dev->irq); | |
1285 | return -EOPNOTSUPP; | |
1286 | } | |
1287 | ||
1288 | /* ignore other fields */ | |
1289 | return 0; | |
1290 | } | |
1291 | ||
1292 | /** | |
1293 | * stmmac_multicast_list - entry point for multicast addressing | |
1294 | * @dev : pointer to the device structure | |
1295 | * Description: | |
1296 | * This function is a driver entry point which gets called by the kernel | |
1297 | * whenever multicast addresses must be enabled/disabled. | |
1298 | * Return value: | |
1299 | * void. | |
1300 | */ | |
1301 | static void stmmac_multicast_list(struct net_device *dev) | |
1302 | { | |
1303 | struct stmmac_priv *priv = netdev_priv(dev); | |
1304 | ||
1305 | spin_lock(&priv->lock); | |
db98a0b0 | 1306 | priv->hw->mac->set_filter(dev); |
47dd7a54 | 1307 | spin_unlock(&priv->lock); |
47dd7a54 GC |
1308 | } |
1309 | ||
1310 | /** | |
1311 | * stmmac_change_mtu - entry point to change MTU size for the device. | |
1312 | * @dev : device pointer. | |
1313 | * @new_mtu : the new MTU size for the device. | |
1314 | * Description: the Maximum Transfer Unit (MTU) is used by the network layer | |
1315 | * to drive packet transmission. Ethernet has an MTU of 1500 octets | |
1316 | * (ETH_DATA_LEN). This value can be changed with ifconfig. | |
1317 | * Return value: | |
1318 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
1319 | * file on failure. | |
1320 | */ | |
1321 | static int stmmac_change_mtu(struct net_device *dev, int new_mtu) | |
1322 | { | |
1323 | struct stmmac_priv *priv = netdev_priv(dev); | |
1324 | int max_mtu; | |
1325 | ||
1326 | if (netif_running(dev)) { | |
1327 | pr_err("%s: must be stopped to change its MTU\n", dev->name); | |
1328 | return -EBUSY; | |
1329 | } | |
1330 | ||
9dfeb4d9 | 1331 | if (priv->plat->has_gmac) |
47dd7a54 GC |
1332 | max_mtu = JUMBO_LEN; |
1333 | else | |
1334 | max_mtu = ETH_DATA_LEN; | |
1335 | ||
1336 | if ((new_mtu < 46) || (new_mtu > max_mtu)) { | |
1337 | pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); | |
1338 | return -EINVAL; | |
1339 | } | |
1340 | ||
5e982f3b MM |
1341 | dev->mtu = new_mtu; |
1342 | netdev_update_features(dev); | |
1343 | ||
1344 | return 0; | |
1345 | } | |
1346 | ||
1347 | static u32 stmmac_fix_features(struct net_device *dev, u32 features) | |
1348 | { | |
1349 | struct stmmac_priv *priv = netdev_priv(dev); | |
1350 | ||
1351 | if (!priv->rx_coe) | |
1352 | features &= ~NETIF_F_RXCSUM; | |
1353 | if (!priv->plat->tx_coe) | |
1354 | features &= ~NETIF_F_ALL_CSUM; | |
1355 | ||
ebbb293f GC |
1356 | /* Some GMAC devices have a bugged Jumbo frame support that |
1357 | * needs to have the Tx COE disabled for oversized frames | |
1358 | * (due to limited buffer sizes). In this case we disable | |
1359 | * the TX csum insertionin the TDES and not use SF. */ | |
5e982f3b MM |
1360 | if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) |
1361 | features &= ~NETIF_F_ALL_CSUM; | |
ebbb293f | 1362 | |
5e982f3b | 1363 | return features; |
47dd7a54 GC |
1364 | } |
1365 | ||
1366 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id) | |
1367 | { | |
1368 | struct net_device *dev = (struct net_device *)dev_id; | |
1369 | struct stmmac_priv *priv = netdev_priv(dev); | |
1370 | ||
1371 | if (unlikely(!dev)) { | |
1372 | pr_err("%s: invalid dev pointer\n", __func__); | |
1373 | return IRQ_NONE; | |
1374 | } | |
1375 | ||
9dfeb4d9 | 1376 | if (priv->plat->has_gmac) |
47dd7a54 | 1377 | /* To handle GMAC own interrupts */ |
ad01b7d4 | 1378 | priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr); |
aec7ff27 GC |
1379 | |
1380 | stmmac_dma_interrupt(priv); | |
47dd7a54 GC |
1381 | |
1382 | return IRQ_HANDLED; | |
1383 | } | |
1384 | ||
1385 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1386 | /* Polling receive - used by NETCONSOLE and other diagnostic tools | |
1387 | * to allow network I/O with interrupts disabled. */ | |
1388 | static void stmmac_poll_controller(struct net_device *dev) | |
1389 | { | |
1390 | disable_irq(dev->irq); | |
1391 | stmmac_interrupt(dev->irq, dev); | |
1392 | enable_irq(dev->irq); | |
1393 | } | |
1394 | #endif | |
1395 | ||
1396 | /** | |
1397 | * stmmac_ioctl - Entry point for the Ioctl | |
1398 | * @dev: Device pointer. | |
1399 | * @rq: An IOCTL specefic structure, that can contain a pointer to | |
1400 | * a proprietary structure used to pass information to the driver. | |
1401 | * @cmd: IOCTL command | |
1402 | * Description: | |
1403 | * Currently there are no special functionality supported in IOCTL, just the | |
1404 | * phy_mii_ioctl(...) can be invoked. | |
1405 | */ | |
1406 | static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1407 | { | |
1408 | struct stmmac_priv *priv = netdev_priv(dev); | |
28b04113 | 1409 | int ret; |
47dd7a54 GC |
1410 | |
1411 | if (!netif_running(dev)) | |
1412 | return -EINVAL; | |
1413 | ||
28b04113 RC |
1414 | if (!priv->phydev) |
1415 | return -EINVAL; | |
1416 | ||
1417 | spin_lock(&priv->lock); | |
1418 | ret = phy_mii_ioctl(priv->phydev, rq, cmd); | |
1419 | spin_unlock(&priv->lock); | |
1420 | ||
47dd7a54 GC |
1421 | return ret; |
1422 | } | |
1423 | ||
47dd7a54 GC |
1424 | static const struct net_device_ops stmmac_netdev_ops = { |
1425 | .ndo_open = stmmac_open, | |
1426 | .ndo_start_xmit = stmmac_xmit, | |
1427 | .ndo_stop = stmmac_release, | |
1428 | .ndo_change_mtu = stmmac_change_mtu, | |
5e982f3b | 1429 | .ndo_fix_features = stmmac_fix_features, |
47dd7a54 GC |
1430 | .ndo_set_multicast_list = stmmac_multicast_list, |
1431 | .ndo_tx_timeout = stmmac_tx_timeout, | |
1432 | .ndo_do_ioctl = stmmac_ioctl, | |
1433 | .ndo_set_config = stmmac_config, | |
47dd7a54 GC |
1434 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1435 | .ndo_poll_controller = stmmac_poll_controller, | |
1436 | #endif | |
1437 | .ndo_set_mac_address = eth_mac_addr, | |
1438 | }; | |
1439 | ||
1440 | /** | |
1441 | * stmmac_probe - Initialization of the adapter . | |
1442 | * @dev : device pointer | |
1443 | * Description: The function initializes the network device structure for | |
1444 | * the STMMAC driver. It also calls the low level routines | |
1445 | * in order to init the HW (i.e. the DMA engine) | |
1446 | */ | |
1447 | static int stmmac_probe(struct net_device *dev) | |
1448 | { | |
1449 | int ret = 0; | |
1450 | struct stmmac_priv *priv = netdev_priv(dev); | |
1451 | ||
1452 | ether_setup(dev); | |
1453 | ||
1454 | dev->netdev_ops = &stmmac_netdev_ops; | |
1455 | stmmac_set_ethtool_ops(dev); | |
1456 | ||
5e982f3b MM |
1457 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; |
1458 | dev->features |= dev->hw_features | NETIF_F_HIGHDMA; | |
47dd7a54 GC |
1459 | dev->watchdog_timeo = msecs_to_jiffies(watchdog); |
1460 | #ifdef STMMAC_VLAN_TAG_USED | |
1461 | /* Both mac100 and gmac support receive VLAN tag detection */ | |
1462 | dev->features |= NETIF_F_HW_VLAN_RX; | |
1463 | #endif | |
1464 | priv->msg_enable = netif_msg_init(debug, default_msg_level); | |
1465 | ||
47dd7a54 GC |
1466 | if (flow_ctrl) |
1467 | priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ | |
1468 | ||
1469 | priv->pause = pause; | |
1470 | netif_napi_add(dev, &priv->napi, stmmac_poll, 64); | |
1471 | ||
1472 | /* Get the MAC address */ | |
ad01b7d4 GC |
1473 | priv->hw->mac->get_umac_addr((void __iomem *) dev->base_addr, |
1474 | dev->dev_addr, 0); | |
47dd7a54 GC |
1475 | |
1476 | if (!is_valid_ether_addr(dev->dev_addr)) | |
1477 | pr_warning("\tno valid MAC address;" | |
1478 | "please, use ifconfig or nwhwconfig!\n"); | |
1479 | ||
f8e96161 VL |
1480 | spin_lock_init(&priv->lock); |
1481 | ||
47dd7a54 GC |
1482 | ret = register_netdev(dev); |
1483 | if (ret) { | |
1484 | pr_err("%s: ERROR %i registering the device\n", | |
1485 | __func__, ret); | |
1486 | return -ENODEV; | |
1487 | } | |
1488 | ||
1489 | DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n", | |
1490 | dev->name, (dev->features & NETIF_F_SG) ? "on" : "off", | |
79032644 | 1491 | (dev->features & NETIF_F_IP_CSUM) ? "on" : "off"); |
47dd7a54 | 1492 | |
47dd7a54 GC |
1493 | return ret; |
1494 | } | |
1495 | ||
1496 | /** | |
1497 | * stmmac_mac_device_setup | |
1498 | * @dev : device pointer | |
1499 | * Description: select and initialise the mac device (mac100 or Gmac). | |
1500 | */ | |
1501 | static int stmmac_mac_device_setup(struct net_device *dev) | |
1502 | { | |
1503 | struct stmmac_priv *priv = netdev_priv(dev); | |
47dd7a54 GC |
1504 | |
1505 | struct mac_device_info *device; | |
1506 | ||
9dfeb4d9 | 1507 | if (priv->plat->has_gmac) |
ad01b7d4 | 1508 | device = dwmac1000_setup(priv->ioaddr); |
3d90c508 | 1509 | else |
ad01b7d4 | 1510 | device = dwmac100_setup(priv->ioaddr); |
3d90c508 | 1511 | |
1ff21906 DC |
1512 | if (!device) |
1513 | return -ENOMEM; | |
1514 | ||
9dfeb4d9 | 1515 | if (priv->plat->enh_desc) { |
3d90c508 GC |
1516 | device->desc = &enh_desc_ops; |
1517 | pr_info("\tEnhanced descriptor structure\n"); | |
1518 | } else | |
56b106ae | 1519 | device->desc = &ndesc_ops; |
47dd7a54 | 1520 | |
db98a0b0 | 1521 | priv->hw = device; |
47dd7a54 | 1522 | |
539c9aa5 | 1523 | if (device_can_wakeup(priv->device)) { |
543876c9 | 1524 | priv->wolopts = WAKE_MAGIC; /* Magic Frame as default */ |
539c9aa5 GC |
1525 | enable_irq_wake(dev->irq); |
1526 | } | |
47dd7a54 GC |
1527 | |
1528 | return 0; | |
1529 | } | |
1530 | ||
1531 | static int stmmacphy_dvr_probe(struct platform_device *pdev) | |
1532 | { | |
ee7946a7 | 1533 | struct plat_stmmacphy_data *plat_dat = pdev->dev.platform_data; |
47dd7a54 GC |
1534 | |
1535 | pr_debug("stmmacphy_dvr_probe: added phy for bus %d\n", | |
1536 | plat_dat->bus_id); | |
1537 | ||
1538 | return 0; | |
1539 | } | |
1540 | ||
1541 | static int stmmacphy_dvr_remove(struct platform_device *pdev) | |
1542 | { | |
1543 | return 0; | |
1544 | } | |
1545 | ||
1546 | static struct platform_driver stmmacphy_driver = { | |
1547 | .driver = { | |
1548 | .name = PHY_RESOURCE_NAME, | |
1549 | }, | |
1550 | .probe = stmmacphy_dvr_probe, | |
1551 | .remove = stmmacphy_dvr_remove, | |
1552 | }; | |
1553 | ||
1554 | /** | |
1555 | * stmmac_associate_phy | |
1556 | * @dev: pointer to device structure | |
1557 | * @data: points to the private structure. | |
1558 | * Description: Scans through all the PHYs we have registered and checks if | |
1559 | * any are associated with our MAC. If so, then just fill in | |
1560 | * the blanks in our local context structure | |
1561 | */ | |
1562 | static int stmmac_associate_phy(struct device *dev, void *data) | |
1563 | { | |
1564 | struct stmmac_priv *priv = (struct stmmac_priv *)data; | |
ee7946a7 | 1565 | struct plat_stmmacphy_data *plat_dat = dev->platform_data; |
47dd7a54 GC |
1566 | |
1567 | DBG(probe, DEBUG, "%s: checking phy for bus %d\n", __func__, | |
1568 | plat_dat->bus_id); | |
1569 | ||
1570 | /* Check that this phy is for the MAC being initialised */ | |
9dfeb4d9 | 1571 | if (priv->plat->bus_id != plat_dat->bus_id) |
47dd7a54 GC |
1572 | return 0; |
1573 | ||
1574 | /* OK, this PHY is connected to the MAC. | |
1575 | Go ahead and get the parameters */ | |
1576 | DBG(probe, DEBUG, "%s: OK. Found PHY config\n", __func__); | |
1577 | priv->phy_irq = | |
1578 | platform_get_irq_byname(to_platform_device(dev), "phyirq"); | |
1579 | DBG(probe, DEBUG, "%s: PHY irq on bus %d is %d\n", __func__, | |
1580 | plat_dat->bus_id, priv->phy_irq); | |
1581 | ||
1582 | /* Override with kernel parameters if supplied XXX CRS XXX | |
1583 | * this needs to have multiple instances */ | |
1584 | if ((phyaddr >= 0) && (phyaddr <= 31)) | |
1585 | plat_dat->phy_addr = phyaddr; | |
1586 | ||
1587 | priv->phy_addr = plat_dat->phy_addr; | |
1588 | priv->phy_mask = plat_dat->phy_mask; | |
1589 | priv->phy_interface = plat_dat->interface; | |
1590 | priv->phy_reset = plat_dat->phy_reset; | |
1591 | ||
1592 | DBG(probe, DEBUG, "%s: exiting\n", __func__); | |
1593 | return 1; /* forces exit of driver_for_each_device() */ | |
1594 | } | |
1595 | ||
1596 | /** | |
1597 | * stmmac_dvr_probe | |
1598 | * @pdev: platform device pointer | |
1599 | * Description: the driver is initialized through platform_device. | |
1600 | */ | |
1601 | static int stmmac_dvr_probe(struct platform_device *pdev) | |
1602 | { | |
1603 | int ret = 0; | |
1604 | struct resource *res; | |
ad01b7d4 | 1605 | void __iomem *addr = NULL; |
47dd7a54 | 1606 | struct net_device *ndev = NULL; |
293bb1c4 | 1607 | struct stmmac_priv *priv = NULL; |
47dd7a54 GC |
1608 | struct plat_stmmacenet_data *plat_dat; |
1609 | ||
1610 | pr_info("STMMAC driver:\n\tplatform registration... "); | |
1611 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
34a52f36 DC |
1612 | if (!res) |
1613 | return -ENODEV; | |
ebbb293f | 1614 | pr_info("\tdone!\n"); |
47dd7a54 | 1615 | |
b6222682 | 1616 | if (!request_mem_region(res->start, resource_size(res), |
47dd7a54 GC |
1617 | pdev->name)) { |
1618 | pr_err("%s: ERROR: memory allocation failed" | |
1619 | "cannot get the I/O addr 0x%x\n", | |
1620 | __func__, (unsigned int)res->start); | |
34a52f36 | 1621 | return -EBUSY; |
47dd7a54 GC |
1622 | } |
1623 | ||
7c5365bc | 1624 | addr = ioremap(res->start, resource_size(res)); |
47dd7a54 | 1625 | if (!addr) { |
7c5365bc | 1626 | pr_err("%s: ERROR: memory mapping failed\n", __func__); |
47dd7a54 | 1627 | ret = -ENOMEM; |
34a52f36 | 1628 | goto out_release_region; |
47dd7a54 GC |
1629 | } |
1630 | ||
1631 | ndev = alloc_etherdev(sizeof(struct stmmac_priv)); | |
1632 | if (!ndev) { | |
1633 | pr_err("%s: ERROR: allocating the device\n", __func__); | |
1634 | ret = -ENOMEM; | |
34a52f36 | 1635 | goto out_unmap; |
47dd7a54 GC |
1636 | } |
1637 | ||
1638 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1639 | ||
1640 | /* Get the MAC information */ | |
1641 | ndev->irq = platform_get_irq_byname(pdev, "macirq"); | |
1642 | if (ndev->irq == -ENXIO) { | |
1643 | pr_err("%s: ERROR: MAC IRQ configuration " | |
1644 | "information not found\n", __func__); | |
34a52f36 DC |
1645 | ret = -ENXIO; |
1646 | goto out_free_ndev; | |
47dd7a54 GC |
1647 | } |
1648 | ||
1649 | priv = netdev_priv(ndev); | |
1650 | priv->device = &(pdev->dev); | |
1651 | priv->dev = ndev; | |
ee7946a7 | 1652 | plat_dat = pdev->dev.platform_data; |
9dfeb4d9 GC |
1653 | |
1654 | priv->plat = plat_dat; | |
1655 | ||
ad01b7d4 | 1656 | priv->ioaddr = addr; |
47dd7a54 | 1657 | |
543876c9 GC |
1658 | /* PMT module is not integrated in all the MAC devices. */ |
1659 | if (plat_dat->pmt) { | |
1660 | pr_info("\tPMT module supported\n"); | |
1661 | device_set_wakeup_capable(&pdev->dev, 1); | |
1662 | } | |
1663 | ||
47dd7a54 GC |
1664 | platform_set_drvdata(pdev, ndev); |
1665 | ||
1666 | /* Set the I/O base addr */ | |
1667 | ndev->base_addr = (unsigned long)addr; | |
1668 | ||
293bb1c4 GC |
1669 | /* Custom initialisation */ |
1670 | if (priv->plat->init) { | |
1671 | ret = priv->plat->init(pdev); | |
1672 | if (unlikely(ret)) | |
34a52f36 | 1673 | goto out_free_ndev; |
293bb1c4 | 1674 | } |
ee7946a7 | 1675 | |
47dd7a54 GC |
1676 | /* MAC HW revice detection */ |
1677 | ret = stmmac_mac_device_setup(ndev); | |
1678 | if (ret < 0) | |
34a52f36 | 1679 | goto out_plat_exit; |
47dd7a54 GC |
1680 | |
1681 | /* Network Device Registration */ | |
1682 | ret = stmmac_probe(ndev); | |
1683 | if (ret < 0) | |
34a52f36 | 1684 | goto out_plat_exit; |
47dd7a54 GC |
1685 | |
1686 | /* associate a PHY - it is provided by another platform bus */ | |
1687 | if (!driver_for_each_device | |
1688 | (&(stmmacphy_driver.driver), NULL, (void *)priv, | |
1689 | stmmac_associate_phy)) { | |
1690 | pr_err("No PHY device is associated with this MAC!\n"); | |
1691 | ret = -ENODEV; | |
34a52f36 | 1692 | goto out_unregister; |
47dd7a54 GC |
1693 | } |
1694 | ||
47dd7a54 | 1695 | pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n" |
1f0f6388 DM |
1696 | "\tIO base addr: 0x%p)\n", ndev->name, pdev->name, |
1697 | pdev->id, ndev->irq, addr); | |
47dd7a54 GC |
1698 | |
1699 | /* MDIO bus Registration */ | |
9dfeb4d9 | 1700 | pr_debug("\tMDIO bus (id: %d)...", priv->plat->bus_id); |
47dd7a54 GC |
1701 | ret = stmmac_mdio_register(ndev); |
1702 | if (ret < 0) | |
34a52f36 | 1703 | goto out_unregister; |
47dd7a54 | 1704 | pr_debug("registered!\n"); |
34a52f36 | 1705 | return 0; |
47dd7a54 | 1706 | |
34a52f36 DC |
1707 | out_unregister: |
1708 | unregister_netdev(ndev); | |
1709 | out_plat_exit: | |
1710 | if (priv->plat->exit) | |
1711 | priv->plat->exit(pdev); | |
1712 | out_free_ndev: | |
1713 | free_netdev(ndev); | |
1714 | platform_set_drvdata(pdev, NULL); | |
1715 | out_unmap: | |
1716 | iounmap(addr); | |
1717 | out_release_region: | |
1718 | release_mem_region(res->start, resource_size(res)); | |
47dd7a54 GC |
1719 | |
1720 | return ret; | |
1721 | } | |
1722 | ||
1723 | /** | |
1724 | * stmmac_dvr_remove | |
1725 | * @pdev: platform device pointer | |
1726 | * Description: this function resets the TX/RX processes, disables the MAC RX/TX | |
1727 | * changes the link status, releases the DMA descriptor rings, | |
1728 | * unregisters the MDIO bus and unmaps the allocated memory. | |
1729 | */ | |
1730 | static int stmmac_dvr_remove(struct platform_device *pdev) | |
1731 | { | |
1732 | struct net_device *ndev = platform_get_drvdata(pdev); | |
aec7ff27 | 1733 | struct stmmac_priv *priv = netdev_priv(ndev); |
47dd7a54 GC |
1734 | struct resource *res; |
1735 | ||
1736 | pr_info("%s:\n\tremoving driver", __func__); | |
1737 | ||
ad01b7d4 GC |
1738 | priv->hw->dma->stop_rx(priv->ioaddr); |
1739 | priv->hw->dma->stop_tx(priv->ioaddr); | |
47dd7a54 | 1740 | |
19449bfc | 1741 | stmmac_disable_mac(priv->ioaddr); |
47dd7a54 GC |
1742 | |
1743 | netif_carrier_off(ndev); | |
1744 | ||
1745 | stmmac_mdio_unregister(ndev); | |
1746 | ||
293bb1c4 GC |
1747 | if (priv->plat->exit) |
1748 | priv->plat->exit(pdev); | |
1749 | ||
47dd7a54 GC |
1750 | platform_set_drvdata(pdev, NULL); |
1751 | unregister_netdev(ndev); | |
1752 | ||
ad01b7d4 | 1753 | iounmap((void *)priv->ioaddr); |
47dd7a54 | 1754 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
7c5365bc | 1755 | release_mem_region(res->start, resource_size(res)); |
47dd7a54 GC |
1756 | |
1757 | free_netdev(ndev); | |
1758 | ||
1759 | return 0; | |
1760 | } | |
1761 | ||
1762 | #ifdef CONFIG_PM | |
874bd42d | 1763 | static int stmmac_suspend(struct device *dev) |
47dd7a54 | 1764 | { |
874bd42d GC |
1765 | struct net_device *ndev = dev_get_drvdata(dev); |
1766 | struct stmmac_priv *priv = netdev_priv(ndev); | |
47dd7a54 GC |
1767 | int dis_ic = 0; |
1768 | ||
874bd42d | 1769 | if (!ndev || !netif_running(ndev)) |
47dd7a54 GC |
1770 | return 0; |
1771 | ||
1772 | spin_lock(&priv->lock); | |
1773 | ||
874bd42d GC |
1774 | netif_device_detach(ndev); |
1775 | netif_stop_queue(ndev); | |
1776 | if (priv->phydev) | |
1777 | phy_stop(priv->phydev); | |
47dd7a54 GC |
1778 | |
1779 | #ifdef CONFIG_STMMAC_TIMER | |
874bd42d GC |
1780 | priv->tm->timer_stop(); |
1781 | if (likely(priv->tm->enable)) | |
1782 | dis_ic = 1; | |
47dd7a54 | 1783 | #endif |
874bd42d GC |
1784 | napi_disable(&priv->napi); |
1785 | ||
1786 | /* Stop TX/RX DMA */ | |
1787 | priv->hw->dma->stop_tx(priv->ioaddr); | |
1788 | priv->hw->dma->stop_rx(priv->ioaddr); | |
1789 | /* Clear the Rx/Tx descriptors */ | |
1790 | priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size, | |
1791 | dis_ic); | |
1792 | priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); | |
1793 | ||
1794 | /* Enable Power down mode by programming the PMT regs */ | |
1795 | if (device_may_wakeup(priv->device)) | |
1796 | priv->hw->mac->pmt(priv->ioaddr, priv->wolopts); | |
1797 | else | |
1798 | stmmac_disable_mac(priv->ioaddr); | |
47dd7a54 GC |
1799 | |
1800 | spin_unlock(&priv->lock); | |
1801 | return 0; | |
1802 | } | |
1803 | ||
874bd42d | 1804 | static int stmmac_resume(struct device *dev) |
47dd7a54 | 1805 | { |
874bd42d GC |
1806 | struct net_device *ndev = dev_get_drvdata(dev); |
1807 | struct stmmac_priv *priv = netdev_priv(ndev); | |
47dd7a54 | 1808 | |
874bd42d | 1809 | if (!netif_running(ndev)) |
47dd7a54 GC |
1810 | return 0; |
1811 | ||
c4433be6 GC |
1812 | spin_lock(&priv->lock); |
1813 | ||
47dd7a54 GC |
1814 | /* Power Down bit, into the PM register, is cleared |
1815 | * automatically as soon as a magic packet or a Wake-up frame | |
1816 | * is received. Anyway, it's better to manually clear | |
1817 | * this bit because it can generate problems while resuming | |
1818 | * from another devices (e.g. serial console). */ | |
874bd42d | 1819 | if (device_may_wakeup(priv->device)) |
543876c9 | 1820 | priv->hw->mac->pmt(priv->ioaddr, 0); |
47dd7a54 | 1821 | |
874bd42d | 1822 | netif_device_attach(ndev); |
47dd7a54 GC |
1823 | |
1824 | /* Enable the MAC and DMA */ | |
19449bfc | 1825 | stmmac_enable_mac(priv->ioaddr); |
ad01b7d4 GC |
1826 | priv->hw->dma->start_tx(priv->ioaddr); |
1827 | priv->hw->dma->start_rx(priv->ioaddr); | |
47dd7a54 GC |
1828 | |
1829 | #ifdef CONFIG_STMMAC_TIMER | |
874bd42d GC |
1830 | if (likely(priv->tm->enable)) |
1831 | priv->tm->timer_start(tmrate); | |
47dd7a54 GC |
1832 | #endif |
1833 | napi_enable(&priv->napi); | |
1834 | ||
1835 | if (priv->phydev) | |
1836 | phy_start(priv->phydev); | |
1837 | ||
874bd42d | 1838 | netif_start_queue(ndev); |
47dd7a54 | 1839 | |
47dd7a54 GC |
1840 | spin_unlock(&priv->lock); |
1841 | return 0; | |
1842 | } | |
47dd7a54 | 1843 | |
874bd42d GC |
1844 | static int stmmac_freeze(struct device *dev) |
1845 | { | |
1846 | struct net_device *ndev = dev_get_drvdata(dev); | |
1847 | ||
1848 | if (!ndev || !netif_running(ndev)) | |
1849 | return 0; | |
1850 | ||
1851 | return stmmac_release(ndev); | |
1852 | } | |
1853 | ||
1854 | static int stmmac_restore(struct device *dev) | |
1855 | { | |
1856 | struct net_device *ndev = dev_get_drvdata(dev); | |
1857 | ||
1858 | if (!ndev || !netif_running(ndev)) | |
1859 | return 0; | |
1860 | ||
1861 | return stmmac_open(ndev); | |
1862 | } | |
1863 | ||
1864 | static const struct dev_pm_ops stmmac_pm_ops = { | |
47dd7a54 GC |
1865 | .suspend = stmmac_suspend, |
1866 | .resume = stmmac_resume, | |
874bd42d GC |
1867 | .freeze = stmmac_freeze, |
1868 | .thaw = stmmac_restore, | |
1869 | .restore = stmmac_restore, | |
1870 | }; | |
1871 | #else | |
1872 | static const struct dev_pm_ops stmmac_pm_ops; | |
1873 | #endif /* CONFIG_PM */ | |
47dd7a54 | 1874 | |
874bd42d GC |
1875 | static struct platform_driver stmmac_driver = { |
1876 | .probe = stmmac_dvr_probe, | |
1877 | .remove = stmmac_dvr_remove, | |
1878 | .driver = { | |
1879 | .name = STMMAC_RESOURCE_NAME, | |
1880 | .owner = THIS_MODULE, | |
1881 | .pm = &stmmac_pm_ops, | |
1882 | }, | |
47dd7a54 GC |
1883 | }; |
1884 | ||
1885 | /** | |
1886 | * stmmac_init_module - Entry point for the driver | |
1887 | * Description: This function is the entry point for the driver. | |
1888 | */ | |
1889 | static int __init stmmac_init_module(void) | |
1890 | { | |
1891 | int ret; | |
1892 | ||
1893 | if (platform_driver_register(&stmmacphy_driver)) { | |
1894 | pr_err("No PHY devices registered!\n"); | |
1895 | return -ENODEV; | |
1896 | } | |
1897 | ||
1898 | ret = platform_driver_register(&stmmac_driver); | |
1899 | return ret; | |
1900 | } | |
1901 | ||
1902 | /** | |
1903 | * stmmac_cleanup_module - Cleanup routine for the driver | |
1904 | * Description: This function is the cleanup routine for the driver. | |
1905 | */ | |
1906 | static void __exit stmmac_cleanup_module(void) | |
1907 | { | |
1908 | platform_driver_unregister(&stmmacphy_driver); | |
1909 | platform_driver_unregister(&stmmac_driver); | |
1910 | } | |
1911 | ||
1912 | #ifndef MODULE | |
1913 | static int __init stmmac_cmdline_opt(char *str) | |
1914 | { | |
1915 | char *opt; | |
1916 | ||
1917 | if (!str || !*str) | |
1918 | return -EINVAL; | |
1919 | while ((opt = strsep(&str, ",")) != NULL) { | |
1920 | if (!strncmp(opt, "debug:", 6)) | |
1921 | strict_strtoul(opt + 6, 0, (unsigned long *)&debug); | |
1922 | else if (!strncmp(opt, "phyaddr:", 8)) | |
1923 | strict_strtoul(opt + 8, 0, (unsigned long *)&phyaddr); | |
1924 | else if (!strncmp(opt, "dma_txsize:", 11)) | |
1925 | strict_strtoul(opt + 11, 0, | |
1926 | (unsigned long *)&dma_txsize); | |
1927 | else if (!strncmp(opt, "dma_rxsize:", 11)) | |
1928 | strict_strtoul(opt + 11, 0, | |
1929 | (unsigned long *)&dma_rxsize); | |
1930 | else if (!strncmp(opt, "buf_sz:", 7)) | |
1931 | strict_strtoul(opt + 7, 0, (unsigned long *)&buf_sz); | |
1932 | else if (!strncmp(opt, "tc:", 3)) | |
1933 | strict_strtoul(opt + 3, 0, (unsigned long *)&tc); | |
47dd7a54 GC |
1934 | else if (!strncmp(opt, "watchdog:", 9)) |
1935 | strict_strtoul(opt + 9, 0, (unsigned long *)&watchdog); | |
1936 | else if (!strncmp(opt, "flow_ctrl:", 10)) | |
1937 | strict_strtoul(opt + 10, 0, | |
1938 | (unsigned long *)&flow_ctrl); | |
1939 | else if (!strncmp(opt, "pause:", 6)) | |
1940 | strict_strtoul(opt + 6, 0, (unsigned long *)&pause); | |
1941 | #ifdef CONFIG_STMMAC_TIMER | |
1942 | else if (!strncmp(opt, "tmrate:", 7)) | |
1943 | strict_strtoul(opt + 7, 0, (unsigned long *)&tmrate); | |
1944 | #endif | |
1945 | } | |
1946 | return 0; | |
1947 | } | |
1948 | ||
1949 | __setup("stmmaceth=", stmmac_cmdline_opt); | |
1950 | #endif | |
1951 | ||
1952 | module_init(stmmac_init_module); | |
1953 | module_exit(stmmac_cleanup_module); | |
1954 | ||
1955 | MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet driver"); | |
1956 | MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); | |
1957 | MODULE_LICENSE("GPL"); |