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[SK_BUFF]: Introduce skb_copy_from_linear_data{_offset}
[deliverable/linux.git] / drivers / net / sunhme.c
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050bbb19 1/* sunhme.c: Sparc HME/BigMac 10/100baseT half/full duplex auto switching,
1da177e4
LT		 2 * auto carrier detecting ethernet driver. Also known as the
3 * "Happy Meal Ethernet" found on SunSwift SBUS cards.
4 *
050bbb19
DM		 5 * Copyright (C) 1996, 1998, 1999, 2002, 2003,
6 2006 David S. Miller (davem@davemloft.net)
1da177e4
LT		 7 *
8 * Changes :
9 * 2000/11/11 Willy Tarreau <willy AT meta-x.org>
10 * - port to non-sparc architectures. Tested only on x86 and
11 * only currently works with QFE PCI cards.
12 * - ability to specify the MAC address at module load time by passing this
13 * argument : macaddr=0x00,0x10,0x20,0x30,0x40,0x50
14 */
15
1da177e4
LT		 16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/fcntl.h>
20#include <linux/interrupt.h>
21#include <linux/ioport.h>
22#include <linux/in.h>
23#include <linux/slab.h>
24#include <linux/string.h>
25#include <linux/delay.h>
26#include <linux/init.h>
27#include <linux/ethtool.h>
28#include <linux/mii.h>
29#include <linux/crc32.h>
30#include <linux/random.h>
31#include <linux/errno.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
d7fe0f24 35#include <linux/mm.h>
1da177e4
LT		 36#include <linux/bitops.h>
37
38#include <asm/system.h>
39#include <asm/io.h>
40#include <asm/dma.h>
41#include <asm/byteorder.h>
42
9e326acf 43#ifdef CONFIG_SPARC
1da177e4
LT		 44#include <asm/idprom.h>
45#include <asm/sbus.h>
46#include <asm/openprom.h>
47#include <asm/oplib.h>
942a6bdd 48#include <asm/prom.h>
1da177e4 49#include <asm/auxio.h>
1da177e4
LT		 50#endif
51#include <asm/uaccess.h>
52
53#include <asm/pgtable.h>
54#include <asm/irq.h>
55
56#ifdef CONFIG_PCI
57#include <linux/pci.h>
9e326acf 58#ifdef CONFIG_SPARC
1da177e4
LT		 59#include <asm/pbm.h>
60#endif
61#endif
62
63#include "sunhme.h"
64
10158286 65#define DRV_NAME "sunhme"
050bbb19
DM		 66#define DRV_VERSION "3.00"
67#define DRV_RELDATE "June 23, 2006"
68#define DRV_AUTHOR "David S. Miller (davem@davemloft.net)"
10158286
TC		 69
70static char version[] =
71 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
1da177e4 72
10158286
TC		 73MODULE_VERSION(DRV_VERSION);
74MODULE_AUTHOR(DRV_AUTHOR);
75MODULE_DESCRIPTION("Sun HappyMealEthernet(HME) 10/100baseT ethernet driver");
76MODULE_LICENSE("GPL");
1da177e4
LT		 77
78static int macaddr[6];
79
80/* accept MAC address of the form macaddr=0x08,0x00,0x20,0x30,0x40,0x50 */
81module_param_array(macaddr, int, NULL, 0);
82MODULE_PARM_DESC(macaddr, "Happy Meal MAC address to set");
1da177e4 83
1da177e4
LT		 84#ifdef CONFIG_SBUS
85static struct quattro *qfe_sbus_list;
86#endif
87
88#ifdef CONFIG_PCI
89static struct quattro *qfe_pci_list;
90#endif
91
92#undef HMEDEBUG
93#undef SXDEBUG
94#undef RXDEBUG
95#undef TXDEBUG
96#undef TXLOGGING
97
98#ifdef TXLOGGING
99struct hme_tx_logent {
100 unsigned int tstamp;
101 int tx_new, tx_old;
102 unsigned int action;
103#define TXLOG_ACTION_IRQ 0x01
104#define TXLOG_ACTION_TXMIT 0x02
105#define TXLOG_ACTION_TBUSY 0x04
106#define TXLOG_ACTION_NBUFS 0x08
107 unsigned int status;
108};
109#define TX_LOG_LEN 128
110static struct hme_tx_logent tx_log[TX_LOG_LEN];
111static int txlog_cur_entry;
112static __inline__ void tx_add_log(struct happy_meal *hp, unsigned int a, unsigned int s)
113{
114 struct hme_tx_logent *tlp;
115 unsigned long flags;
116
117 save_and_cli(flags);
118 tlp = &tx_log[txlog_cur_entry];
119 tlp->tstamp = (unsigned int)jiffies;
120 tlp->tx_new = hp->tx_new;
121 tlp->tx_old = hp->tx_old;
122 tlp->action = a;
123 tlp->status = s;
124 txlog_cur_entry = (txlog_cur_entry + 1) & (TX_LOG_LEN - 1);
125 restore_flags(flags);
126}
127static __inline__ void tx_dump_log(void)
128{
129 int i, this;
130
131 this = txlog_cur_entry;
132 for (i = 0; i < TX_LOG_LEN; i++) {
133 printk("TXLOG[%d]: j[%08x] tx[N(%d)O(%d)] action[%08x] stat[%08x]\n", i,
134 tx_log[this].tstamp,
135 tx_log[this].tx_new, tx_log[this].tx_old,
136 tx_log[this].action, tx_log[this].status);
137 this = (this + 1) & (TX_LOG_LEN - 1);
138 }
139}
140static __inline__ void tx_dump_ring(struct happy_meal *hp)
141{
142 struct hmeal_init_block *hb = hp->happy_block;
143 struct happy_meal_txd *tp = &hb->happy_meal_txd[0];
144 int i;
145
146 for (i = 0; i < TX_RING_SIZE; i+=4) {
147 printk("TXD[%d..%d]: [%08x:%08x] [%08x:%08x] [%08x:%08x] [%08x:%08x]\n",
148 i, i + 4,
149 le32_to_cpu(tp[i].tx_flags), le32_to_cpu(tp[i].tx_addr),
150 le32_to_cpu(tp[i + 1].tx_flags), le32_to_cpu(tp[i + 1].tx_addr),
151 le32_to_cpu(tp[i + 2].tx_flags), le32_to_cpu(tp[i + 2].tx_addr),
152 le32_to_cpu(tp[i + 3].tx_flags), le32_to_cpu(tp[i + 3].tx_addr));
153 }
154}
155#else
156#define tx_add_log(hp, a, s) do { } while(0)
157#define tx_dump_log() do { } while(0)
158#define tx_dump_ring(hp) do { } while(0)
159#endif
160
161#ifdef HMEDEBUG
162#define HMD(x) printk x
163#else
164#define HMD(x)
165#endif
166
167/* #define AUTO_SWITCH_DEBUG */
168
169#ifdef AUTO_SWITCH_DEBUG
170#define ASD(x) printk x
171#else
172#define ASD(x)
173#endif
174
175#define DEFAULT_IPG0 16 /* For lance-mode only */
176#define DEFAULT_IPG1 8 /* For all modes */
177#define DEFAULT_IPG2 4 /* For all modes */
178#define DEFAULT_JAMSIZE 4 /* Toe jam */
179
1da177e4
LT		 180/* NOTE: In the descriptor writes one _must_ write the address
181 * member _first_. The card must not be allowed to see
182 * the updated descriptor flags until the address is
183 * correct. I've added a write memory barrier between
184 * the two stores so that I can sleep well at night... -DaveM
185 */
186
187#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
188static void sbus_hme_write32(void __iomem *reg, u32 val)
189{
190 sbus_writel(val, reg);
191}
192
193static u32 sbus_hme_read32(void __iomem *reg)
194{
195 return sbus_readl(reg);
196}
197
198static void sbus_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
199{
200 rxd->rx_addr = addr;
201 wmb();
202 rxd->rx_flags = flags;
203}
204
205static void sbus_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
206{
207 txd->tx_addr = addr;
208 wmb();
209 txd->tx_flags = flags;
210}
211
212static u32 sbus_hme_read_desc32(u32 *p)
213{
214 return *p;
215}
216
217static void pci_hme_write32(void __iomem *reg, u32 val)
218{
219 writel(val, reg);
220}
221
222static u32 pci_hme_read32(void __iomem *reg)
223{
224 return readl(reg);
225}
226
227static void pci_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
228{
229 rxd->rx_addr = cpu_to_le32(addr);
230 wmb();
231 rxd->rx_flags = cpu_to_le32(flags);
232}
233
234static void pci_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
235{
236 txd->tx_addr = cpu_to_le32(addr);
237 wmb();
238 txd->tx_flags = cpu_to_le32(flags);
239}
240
241static u32 pci_hme_read_desc32(u32 *p)
242{
243 return cpu_to_le32p(p);
244}
245
246#define hme_write32(__hp, __reg, __val) \
247 ((__hp)->write32((__reg), (__val)))
248#define hme_read32(__hp, __reg) \
249 ((__hp)->read32(__reg))
250#define hme_write_rxd(__hp, __rxd, __flags, __addr) \
251 ((__hp)->write_rxd((__rxd), (__flags), (__addr)))
252#define hme_write_txd(__hp, __txd, __flags, __addr) \
253 ((__hp)->write_txd((__txd), (__flags), (__addr)))
254#define hme_read_desc32(__hp, __p) \
255 ((__hp)->read_desc32(__p))
256#define hme_dma_map(__hp, __ptr, __size, __dir) \
257 ((__hp)->dma_map((__hp)->happy_dev, (__ptr), (__size), (__dir)))
258#define hme_dma_unmap(__hp, __addr, __size, __dir) \
259 ((__hp)->dma_unmap((__hp)->happy_dev, (__addr), (__size), (__dir)))
260#define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
261 ((__hp)->dma_sync_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir)))
262#define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
263 ((__hp)->dma_sync_for_device((__hp)->happy_dev, (__addr), (__size), (__dir)))
264#else
265#ifdef CONFIG_SBUS
266/* SBUS only compilation */
267#define hme_write32(__hp, __reg, __val) \
268 sbus_writel((__val), (__reg))
269#define hme_read32(__hp, __reg) \
270 sbus_readl(__reg)
271#define hme_write_rxd(__hp, __rxd, __flags, __addr) \
272do { (__rxd)->rx_addr = (__addr); \
273 wmb(); \
274 (__rxd)->rx_flags = (__flags); \
275} while(0)
276#define hme_write_txd(__hp, __txd, __flags, __addr) \
277do { (__txd)->tx_addr = (__addr); \
278 wmb(); \
279 (__txd)->tx_flags = (__flags); \
280} while(0)
281#define hme_read_desc32(__hp, __p) (*(__p))
282#define hme_dma_map(__hp, __ptr, __size, __dir) \
283 sbus_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
284#define hme_dma_unmap(__hp, __addr, __size, __dir) \
285 sbus_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
286#define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
287 sbus_dma_sync_single_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir))
288#define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
289 sbus_dma_sync_single_for_device((__hp)->happy_dev, (__addr), (__size), (__dir))
290#else
291/* PCI only compilation */
292#define hme_write32(__hp, __reg, __val) \
293 writel((__val), (__reg))
294#define hme_read32(__hp, __reg) \
295 readl(__reg)
296#define hme_write_rxd(__hp, __rxd, __flags, __addr) \
297do { (__rxd)->rx_addr = cpu_to_le32(__addr); \
298 wmb(); \
299 (__rxd)->rx_flags = cpu_to_le32(__flags); \
300} while(0)
301#define hme_write_txd(__hp, __txd, __flags, __addr) \
302do { (__txd)->tx_addr = cpu_to_le32(__addr); \
303 wmb(); \
304 (__txd)->tx_flags = cpu_to_le32(__flags); \
305} while(0)
306#define hme_read_desc32(__hp, __p) cpu_to_le32p(__p)
307#define hme_dma_map(__hp, __ptr, __size, __dir) \
308 pci_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
309#define hme_dma_unmap(__hp, __addr, __size, __dir) \
310 pci_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
311#define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
312 pci_dma_sync_single_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir))
313#define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
314 pci_dma_sync_single_for_device((__hp)->happy_dev, (__addr), (__size), (__dir))
315#endif
316#endif
317
318
319#ifdef SBUS_DMA_BIDIRECTIONAL
320# define DMA_BIDIRECTIONAL SBUS_DMA_BIDIRECTIONAL
321#else
322# define DMA_BIDIRECTIONAL 0
323#endif
324
325#ifdef SBUS_DMA_FROMDEVICE
326# define DMA_FROMDEVICE SBUS_DMA_FROMDEVICE
327#else
328# define DMA_TODEVICE 1
329#endif
330
331#ifdef SBUS_DMA_TODEVICE
332# define DMA_TODEVICE SBUS_DMA_TODEVICE
333#else
334# define DMA_FROMDEVICE 2
335#endif
336
337
338/* Oh yes, the MIF BitBang is mighty fun to program. BitBucket is more like it. */
339static void BB_PUT_BIT(struct happy_meal *hp, void __iomem *tregs, int bit)
340{
341 hme_write32(hp, tregs + TCVR_BBDATA, bit);
342 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
343 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
344}
345
346#if 0
347static u32 BB_GET_BIT(struct happy_meal *hp, void __iomem *tregs, int internal)
348{
349 u32 ret;
350
351 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
352 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
353 ret = hme_read32(hp, tregs + TCVR_CFG);
354 if (internal)
355 ret &= TCV_CFG_MDIO0;
356 else
357 ret &= TCV_CFG_MDIO1;
358
359 return ret;
360}
361#endif
362
363static u32 BB_GET_BIT2(struct happy_meal *hp, void __iomem *tregs, int internal)
364{
365 u32 retval;
366
367 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
368 udelay(1);
369 retval = hme_read32(hp, tregs + TCVR_CFG);
370 if (internal)
371 retval &= TCV_CFG_MDIO0;
372 else
373 retval &= TCV_CFG_MDIO1;
374 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
375
376 return retval;
377}
378
379#define TCVR_FAILURE 0x80000000 /* Impossible MIF read value */
380
381static int happy_meal_bb_read(struct happy_meal *hp,
382 void __iomem *tregs, int reg)
383{
384 u32 tmp;
385 int retval = 0;
386 int i;
387
388 ASD(("happy_meal_bb_read: reg=%d ", reg));
389
390 /* Enable the MIF BitBang outputs. */
391 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
392
393 /* Force BitBang into the idle state. */
394 for (i = 0; i < 32; i++)
395 BB_PUT_BIT(hp, tregs, 1);
396
397 /* Give it the read sequence. */
398 BB_PUT_BIT(hp, tregs, 0);
399 BB_PUT_BIT(hp, tregs, 1);
400 BB_PUT_BIT(hp, tregs, 1);
401 BB_PUT_BIT(hp, tregs, 0);
402
403 /* Give it the PHY address. */
404 tmp = hp->paddr & 0xff;
405 for (i = 4; i >= 0; i--)
406 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
407
408 /* Tell it what register we want to read. */
409 tmp = (reg & 0xff);
410 for (i = 4; i >= 0; i--)
411 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
412
413 /* Close down the MIF BitBang outputs. */
414 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
415
416 /* Now read in the value. */
417 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
418 for (i = 15; i >= 0; i--)
419 retval |= BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
420 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
421 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
422 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
423 ASD(("value=%x\n", retval));
424 return retval;
425}
426
427static void happy_meal_bb_write(struct happy_meal *hp,
428 void __iomem *tregs, int reg,
429 unsigned short value)
430{
431 u32 tmp;
432 int i;
433
434 ASD(("happy_meal_bb_write: reg=%d value=%x\n", reg, value));
435
436 /* Enable the MIF BitBang outputs. */
437 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
438
439 /* Force BitBang into the idle state. */
440 for (i = 0; i < 32; i++)
441 BB_PUT_BIT(hp, tregs, 1);
442
443 /* Give it write sequence. */
444 BB_PUT_BIT(hp, tregs, 0);
445 BB_PUT_BIT(hp, tregs, 1);
446 BB_PUT_BIT(hp, tregs, 0);
447 BB_PUT_BIT(hp, tregs, 1);
448
449 /* Give it the PHY address. */
450 tmp = (hp->paddr & 0xff);
451 for (i = 4; i >= 0; i--)
452 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
453
454 /* Tell it what register we will be writing. */
455 tmp = (reg & 0xff);
456 for (i = 4; i >= 0; i--)
457 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
458
459 /* Tell it to become ready for the bits. */
460 BB_PUT_BIT(hp, tregs, 1);
461 BB_PUT_BIT(hp, tregs, 0);
462
463 for (i = 15; i >= 0; i--)
464 BB_PUT_BIT(hp, tregs, ((value >> i) & 1));
465
466 /* Close down the MIF BitBang outputs. */
467 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
468}
469
470#define TCVR_READ_TRIES 16
471
472static int happy_meal_tcvr_read(struct happy_meal *hp,
473 void __iomem *tregs, int reg)
474{
475 int tries = TCVR_READ_TRIES;
476 int retval;
477
478 ASD(("happy_meal_tcvr_read: reg=0x%02x ", reg));
479 if (hp->tcvr_type == none) {
480 ASD(("no transceiver, value=TCVR_FAILURE\n"));
481 return TCVR_FAILURE;
482 }
483
484 if (!(hp->happy_flags & HFLAG_FENABLE)) {
485 ASD(("doing bit bang\n"));
486 return happy_meal_bb_read(hp, tregs, reg);
487 }
488
489 hme_write32(hp, tregs + TCVR_FRAME,
490 (FRAME_READ | (hp->paddr << 23) | ((reg & 0xff) << 18)));
491 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
492 udelay(20);
493 if (!tries) {
494 printk(KERN_ERR "happy meal: Aieee, transceiver MIF read bolixed\n");
495 return TCVR_FAILURE;
496 }
497 retval = hme_read32(hp, tregs + TCVR_FRAME) & 0xffff;
498 ASD(("value=%04x\n", retval));
499 return retval;
500}
501
502#define TCVR_WRITE_TRIES 16
503
504static void happy_meal_tcvr_write(struct happy_meal *hp,
505 void __iomem *tregs, int reg,
506 unsigned short value)
507{
508 int tries = TCVR_WRITE_TRIES;
6aa20a22 509
1da177e4
LT		 510 ASD(("happy_meal_tcvr_write: reg=0x%02x value=%04x\n", reg, value));
511
512 /* Welcome to Sun Microsystems, can I take your order please? */
513 if (!(hp->happy_flags & HFLAG_FENABLE)) {
514 happy_meal_bb_write(hp, tregs, reg, value);
515 return;
516 }
517
518 /* Would you like fries with that? */
519 hme_write32(hp, tregs + TCVR_FRAME,
520 (FRAME_WRITE | (hp->paddr << 23) |
521 ((reg & 0xff) << 18) | (value & 0xffff)));
522 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
523 udelay(20);
524
525 /* Anything else? */
526 if (!tries)
527 printk(KERN_ERR "happy meal: Aieee, transceiver MIF write bolixed\n");
528
529 /* Fifty-two cents is your change, have a nice day. */
530}
531
532/* Auto negotiation. The scheme is very simple. We have a timer routine
533 * that keeps watching the auto negotiation process as it progresses.
534 * The DP83840 is first told to start doing it's thing, we set up the time
535 * and place the timer state machine in it's initial state.
536 *
537 * Here the timer peeks at the DP83840 status registers at each click to see
538 * if the auto negotiation has completed, we assume here that the DP83840 PHY
539 * will time out at some point and just tell us what (didn't) happen. For
540 * complete coverage we only allow so many of the ticks at this level to run,
541 * when this has expired we print a warning message and try another strategy.
542 * This "other" strategy is to force the interface into various speed/duplex
543 * configurations and we stop when we see a link-up condition before the
544 * maximum number of "peek" ticks have occurred.
545 *
546 * Once a valid link status has been detected we configure the BigMAC and
547 * the rest of the Happy Meal to speak the most efficient protocol we could
548 * get a clean link for. The priority for link configurations, highest first
549 * is:
550 * 100 Base-T Full Duplex
551 * 100 Base-T Half Duplex
552 * 10 Base-T Full Duplex
553 * 10 Base-T Half Duplex
554 *
555 * We start a new timer now, after a successful auto negotiation status has
556 * been detected. This timer just waits for the link-up bit to get set in
557 * the BMCR of the DP83840. When this occurs we print a kernel log message
558 * describing the link type in use and the fact that it is up.
559 *
560 * If a fatal error of some sort is signalled and detected in the interrupt
561 * service routine, and the chip is reset, or the link is ifconfig'd down
562 * and then back up, this entire process repeats itself all over again.
563 */
564static int try_next_permutation(struct happy_meal *hp, void __iomem *tregs)
565{
566 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
567
568 /* Downgrade from full to half duplex. Only possible
569 * via ethtool.
570 */
571 if (hp->sw_bmcr & BMCR_FULLDPLX) {
572 hp->sw_bmcr &= ~(BMCR_FULLDPLX);
573 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
574 return 0;
575 }
576
577 /* Downgrade from 100 to 10. */
578 if (hp->sw_bmcr & BMCR_SPEED100) {
579 hp->sw_bmcr &= ~(BMCR_SPEED100);
580 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
581 return 0;
582 }
583
584 /* We've tried everything. */
585 return -1;
586}
587
588static void display_link_mode(struct happy_meal *hp, void __iomem *tregs)
589{
590 printk(KERN_INFO "%s: Link is up using ", hp->dev->name);
591 if (hp->tcvr_type == external)
592 printk("external ");
593 else
594 printk("internal ");
595 printk("transceiver at ");
596 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
597 if (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) {
598 if (hp->sw_lpa & LPA_100FULL)
599 printk("100Mb/s, Full Duplex.\n");
600 else
601 printk("100Mb/s, Half Duplex.\n");
602 } else {
603 if (hp->sw_lpa & LPA_10FULL)
604 printk("10Mb/s, Full Duplex.\n");
605 else
606 printk("10Mb/s, Half Duplex.\n");
607 }
608}
609
610static void display_forced_link_mode(struct happy_meal *hp, void __iomem *tregs)
611{
612 printk(KERN_INFO "%s: Link has been forced up using ", hp->dev->name);
613 if (hp->tcvr_type == external)
614 printk("external ");
615 else
616 printk("internal ");
617 printk("transceiver at ");
618 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
619 if (hp->sw_bmcr & BMCR_SPEED100)
620 printk("100Mb/s, ");
621 else
622 printk("10Mb/s, ");
623 if (hp->sw_bmcr & BMCR_FULLDPLX)
624 printk("Full Duplex.\n");
625 else
626 printk("Half Duplex.\n");
627}
628
629static int set_happy_link_modes(struct happy_meal *hp, void __iomem *tregs)
630{
631 int full;
632
633 /* All we care about is making sure the bigmac tx_cfg has a
634 * proper duplex setting.
635 */
636 if (hp->timer_state == arbwait) {
637 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
638 if (!(hp->sw_lpa & (LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL)))
639 goto no_response;
640 if (hp->sw_lpa & LPA_100FULL)
641 full = 1;
642 else if (hp->sw_lpa & LPA_100HALF)
643 full = 0;
644 else if (hp->sw_lpa & LPA_10FULL)
645 full = 1;
646 else
647 full = 0;
648 } else {
649 /* Forcing a link mode. */
650 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
651 if (hp->sw_bmcr & BMCR_FULLDPLX)
652 full = 1;
653 else
654 full = 0;
655 }
656
657 /* Before changing other bits in the tx_cfg register, and in
658 * general any of other the TX config registers too, you
659 * must:
660 * 1) Clear Enable
661 * 2) Poll with reads until that bit reads back as zero
662 * 3) Make TX configuration changes
663 * 4) Set Enable once more
664 */
665 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
666 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
667 ~(BIGMAC_TXCFG_ENABLE));
668 while (hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & BIGMAC_TXCFG_ENABLE)
669 barrier();
670 if (full) {
671 hp->happy_flags |= HFLAG_FULL;
672 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
673 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
674 BIGMAC_TXCFG_FULLDPLX);
675 } else {
676 hp->happy_flags &= ~(HFLAG_FULL);
677 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
678 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
679 ~(BIGMAC_TXCFG_FULLDPLX));
680 }
681 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
682 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
683 BIGMAC_TXCFG_ENABLE);
684 return 0;
685no_response:
686 return 1;
687}
688
689static int happy_meal_init(struct happy_meal *hp);
690
691static int is_lucent_phy(struct happy_meal *hp)
692{
693 void __iomem *tregs = hp->tcvregs;
694 unsigned short mr2, mr3;
695 int ret = 0;
696
697 mr2 = happy_meal_tcvr_read(hp, tregs, 2);
698 mr3 = happy_meal_tcvr_read(hp, tregs, 3);
699 if ((mr2 & 0xffff) == 0x0180 &&
700 ((mr3 & 0xffff) >> 10) == 0x1d)
701 ret = 1;
702
703 return ret;
704}
705
706static void happy_meal_timer(unsigned long data)
707{
708 struct happy_meal *hp = (struct happy_meal *) data;
709 void __iomem *tregs = hp->tcvregs;
710 int restart_timer = 0;
711
712 spin_lock_irq(&hp->happy_lock);
713
714 hp->timer_ticks++;
715 switch(hp->timer_state) {
716 case arbwait:
717 /* Only allow for 5 ticks, thats 10 seconds and much too
718 * long to wait for arbitration to complete.
719 */
720 if (hp->timer_ticks >= 10) {
721 /* Enter force mode. */
722 do_force_mode:
723 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
724 printk(KERN_NOTICE "%s: Auto-Negotiation unsuccessful, trying force link mode\n",
725 hp->dev->name);
726 hp->sw_bmcr = BMCR_SPEED100;
727 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
728
729 if (!is_lucent_phy(hp)) {
730 /* OK, seems we need do disable the transceiver for the first
731 * tick to make sure we get an accurate link state at the
732 * second tick.
733 */
734 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
735 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
736 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, hp->sw_csconfig);
737 }
738 hp->timer_state = ltrywait;
739 hp->timer_ticks = 0;
740 restart_timer = 1;
741 } else {
742 /* Anything interesting happen? */
743 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
744 if (hp->sw_bmsr & BMSR_ANEGCOMPLETE) {
745 int ret;
746
747 /* Just what we've been waiting for... */
748 ret = set_happy_link_modes(hp, tregs);
749 if (ret) {
750 /* Ooops, something bad happened, go to force
751 * mode.
752 *
753 * XXX Broken hubs which don't support 802.3u
754 * XXX auto-negotiation make this happen as well.
755 */
756 goto do_force_mode;
757 }
758
759 /* Success, at least so far, advance our state engine. */
760 hp->timer_state = lupwait;
761 restart_timer = 1;
762 } else {
763 restart_timer = 1;
764 }
765 }
766 break;
767
768 case lupwait:
769 /* Auto negotiation was successful and we are awaiting a
770 * link up status. I have decided to let this timer run
771 * forever until some sort of error is signalled, reporting
772 * a message to the user at 10 second intervals.
773 */
774 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
775 if (hp->sw_bmsr & BMSR_LSTATUS) {
776 /* Wheee, it's up, display the link mode in use and put
777 * the timer to sleep.
778 */
779 display_link_mode(hp, tregs);
780 hp->timer_state = asleep;
781 restart_timer = 0;
782 } else {
783 if (hp->timer_ticks >= 10) {
784 printk(KERN_NOTICE "%s: Auto negotiation successful, link still "
785 "not completely up.\n", hp->dev->name);
786 hp->timer_ticks = 0;
787 restart_timer = 1;
788 } else {
789 restart_timer = 1;
790 }
791 }
792 break;
793
794 case ltrywait:
795 /* Making the timeout here too long can make it take
796 * annoyingly long to attempt all of the link mode
797 * permutations, but then again this is essentially
798 * error recovery code for the most part.
799 */
800 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
801 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
802 if (hp->timer_ticks == 1) {
803 if (!is_lucent_phy(hp)) {
804 /* Re-enable transceiver, we'll re-enable the transceiver next
805 * tick, then check link state on the following tick.
806 */
807 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
808 happy_meal_tcvr_write(hp, tregs,
809 DP83840_CSCONFIG, hp->sw_csconfig);
810 }
811 restart_timer = 1;
812 break;
813 }
814 if (hp->timer_ticks == 2) {
815 if (!is_lucent_phy(hp)) {
816 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
817 happy_meal_tcvr_write(hp, tregs,
818 DP83840_CSCONFIG, hp->sw_csconfig);
819 }
820 restart_timer = 1;
821 break;
822 }
823 if (hp->sw_bmsr & BMSR_LSTATUS) {
824 /* Force mode selection success. */
825 display_forced_link_mode(hp, tregs);
826 set_happy_link_modes(hp, tregs); /* XXX error? then what? */
827 hp->timer_state = asleep;
828 restart_timer = 0;
829 } else {
830 if (hp->timer_ticks >= 4) { /* 6 seconds or so... */
831 int ret;
832
833 ret = try_next_permutation(hp, tregs);
834 if (ret == -1) {
835 /* Aieee, tried them all, reset the
836 * chip and try all over again.
837 */
838
839 /* Let the user know... */
840 printk(KERN_NOTICE "%s: Link down, cable problem?\n",
841 hp->dev->name);
842
843 ret = happy_meal_init(hp);
844 if (ret) {
845 /* ho hum... */
846 printk(KERN_ERR "%s: Error, cannot re-init the "
847 "Happy Meal.\n", hp->dev->name);
848 }
849 goto out;
850 }
851 if (!is_lucent_phy(hp)) {
852 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
853 DP83840_CSCONFIG);
854 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
855 happy_meal_tcvr_write(hp, tregs,
856 DP83840_CSCONFIG, hp->sw_csconfig);
857 }
858 hp->timer_ticks = 0;
859 restart_timer = 1;
860 } else {
861 restart_timer = 1;
862 }
863 }
864 break;
865
866 case asleep:
867 default:
868 /* Can't happens.... */
869 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
870 hp->dev->name);
871 restart_timer = 0;
872 hp->timer_ticks = 0;
873 hp->timer_state = asleep; /* foo on you */
874 break;
875 };
876
877 if (restart_timer) {
878 hp->happy_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
879 add_timer(&hp->happy_timer);
880 }
881
882out:
883 spin_unlock_irq(&hp->happy_lock);
884}
885
886#define TX_RESET_TRIES 32
887#define RX_RESET_TRIES 32
888
889/* hp->happy_lock must be held */
890static void happy_meal_tx_reset(struct happy_meal *hp, void __iomem *bregs)
891{
892 int tries = TX_RESET_TRIES;
893
894 HMD(("happy_meal_tx_reset: reset, "));
895
896 /* Would you like to try our SMCC Delux? */
897 hme_write32(hp, bregs + BMAC_TXSWRESET, 0);
898 while ((hme_read32(hp, bregs + BMAC_TXSWRESET) & 1) && --tries)
899 udelay(20);
900
901 /* Lettuce, tomato, buggy hardware (no extra charge)? */
902 if (!tries)
903 printk(KERN_ERR "happy meal: Transceiver BigMac ATTACK!");
904
905 /* Take care. */
906 HMD(("done\n"));
907}
908
909/* hp->happy_lock must be held */
910static void happy_meal_rx_reset(struct happy_meal *hp, void __iomem *bregs)
911{
912 int tries = RX_RESET_TRIES;
913
914 HMD(("happy_meal_rx_reset: reset, "));
915
916 /* We have a special on GNU/Viking hardware bugs today. */
917 hme_write32(hp, bregs + BMAC_RXSWRESET, 0);
918 while ((hme_read32(hp, bregs + BMAC_RXSWRESET) & 1) && --tries)
919 udelay(20);
920
921 /* Will that be all? */
922 if (!tries)
923 printk(KERN_ERR "happy meal: Receiver BigMac ATTACK!");
924
925 /* Don't forget your vik_1137125_wa. Have a nice day. */
926 HMD(("done\n"));
927}
928
929#define STOP_TRIES 16
930
931/* hp->happy_lock must be held */
932static void happy_meal_stop(struct happy_meal *hp, void __iomem *gregs)
933{
934 int tries = STOP_TRIES;
935
936 HMD(("happy_meal_stop: reset, "));
937
938 /* We're consolidating our STB products, it's your lucky day. */
939 hme_write32(hp, gregs + GREG_SWRESET, GREG_RESET_ALL);
940 while (hme_read32(hp, gregs + GREG_SWRESET) && --tries)
941 udelay(20);
942
943 /* Come back next week when we are "Sun Microelectronics". */
944 if (!tries)
945 printk(KERN_ERR "happy meal: Fry guys.");
946
947 /* Remember: "Different name, same old buggy as shit hardware." */
948 HMD(("done\n"));
949}
950
951/* hp->happy_lock must be held */
952static void happy_meal_get_counters(struct happy_meal *hp, void __iomem *bregs)
953{
954 struct net_device_stats *stats = &hp->net_stats;
955
956 stats->rx_crc_errors += hme_read32(hp, bregs + BMAC_RCRCECTR);
957 hme_write32(hp, bregs + BMAC_RCRCECTR, 0);
958
959 stats->rx_frame_errors += hme_read32(hp, bregs + BMAC_UNALECTR);
960 hme_write32(hp, bregs + BMAC_UNALECTR, 0);
961
962 stats->rx_length_errors += hme_read32(hp, bregs + BMAC_GLECTR);
963 hme_write32(hp, bregs + BMAC_GLECTR, 0);
964
965 stats->tx_aborted_errors += hme_read32(hp, bregs + BMAC_EXCTR);
966
967 stats->collisions +=
968 (hme_read32(hp, bregs + BMAC_EXCTR) +
969 hme_read32(hp, bregs + BMAC_LTCTR));
970 hme_write32(hp, bregs + BMAC_EXCTR, 0);
971 hme_write32(hp, bregs + BMAC_LTCTR, 0);
972}
973
974/* hp->happy_lock must be held */
975static void happy_meal_poll_stop(struct happy_meal *hp, void __iomem *tregs)
976{
977 ASD(("happy_meal_poll_stop: "));
978
979 /* If polling disabled or not polling already, nothing to do. */
980 if ((hp->happy_flags & (HFLAG_POLLENABLE | HFLAG_POLL)) !=
981 (HFLAG_POLLENABLE | HFLAG_POLL)) {
982 HMD(("not polling, return\n"));
983 return;
984 }
985
986 /* Shut up the MIF. */
987 ASD(("were polling, mif ints off, "));
988 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
989
990 /* Turn off polling. */
991 ASD(("polling off, "));
992 hme_write32(hp, tregs + TCVR_CFG,
993 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_PENABLE));
994
995 /* We are no longer polling. */
996 hp->happy_flags &= ~(HFLAG_POLL);
997
998 /* Let the bits set. */
999 udelay(200);
1000 ASD(("done\n"));
1001}
1002
1003/* Only Sun can take such nice parts and fuck up the programming interface
1004 * like this. Good job guys...
1005 */
1006#define TCVR_RESET_TRIES 16 /* It should reset quickly */
1007#define TCVR_UNISOLATE_TRIES 32 /* Dis-isolation can take longer. */
1008
1009/* hp->happy_lock must be held */
1010static int happy_meal_tcvr_reset(struct happy_meal *hp, void __iomem *tregs)
1011{
1012 u32 tconfig;
1013 int result, tries = TCVR_RESET_TRIES;
1014
1015 tconfig = hme_read32(hp, tregs + TCVR_CFG);
1016 ASD(("happy_meal_tcvr_reset: tcfg<%08lx> ", tconfig));
1017 if (hp->tcvr_type == external) {
1018 ASD(("external<"));
1019 hme_write32(hp, tregs + TCVR_CFG, tconfig & ~(TCV_CFG_PSELECT));
1020 hp->tcvr_type = internal;
1021 hp->paddr = TCV_PADDR_ITX;
1022 ASD(("ISOLATE,"));
1023 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1024 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1025 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1026 if (result == TCVR_FAILURE) {
1027 ASD(("phyread_fail>\n"));
1028 return -1;
1029 }
1030 ASD(("phyread_ok,PSELECT>"));
1031 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1032 hp->tcvr_type = external;
1033 hp->paddr = TCV_PADDR_ETX;
1034 } else {
1035 if (tconfig & TCV_CFG_MDIO1) {
1036 ASD(("internal<PSELECT,"));
1037 hme_write32(hp, tregs + TCVR_CFG, (tconfig | TCV_CFG_PSELECT));
1038 ASD(("ISOLATE,"));
1039 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1040 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1041 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1042 if (result == TCVR_FAILURE) {
1043 ASD(("phyread_fail>\n"));
1044 return -1;
1045 }
1046 ASD(("phyread_ok,~PSELECT>"));
1047 hme_write32(hp, tregs + TCVR_CFG, (tconfig & ~(TCV_CFG_PSELECT)));
1048 hp->tcvr_type = internal;
1049 hp->paddr = TCV_PADDR_ITX;
1050 }
1051 }
1052
1053 ASD(("BMCR_RESET "));
1054 happy_meal_tcvr_write(hp, tregs, MII_BMCR, BMCR_RESET);
1055
1056 while (--tries) {
1057 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1058 if (result == TCVR_FAILURE)
1059 return -1;
1060 hp->sw_bmcr = result;
1061 if (!(result & BMCR_RESET))
1062 break;
1063 udelay(20);
1064 }
1065 if (!tries) {
1066 ASD(("BMCR RESET FAILED!\n"));
1067 return -1;
1068 }
1069 ASD(("RESET_OK\n"));
1070
1071 /* Get fresh copies of the PHY registers. */
1072 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1073 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1074 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1075 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1076
1077 ASD(("UNISOLATE"));
1078 hp->sw_bmcr &= ~(BMCR_ISOLATE);
1079 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1080
1081 tries = TCVR_UNISOLATE_TRIES;
1082 while (--tries) {
1083 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1084 if (result == TCVR_FAILURE)
1085 return -1;
1086 if (!(result & BMCR_ISOLATE))
1087 break;
1088 udelay(20);
1089 }
1090 if (!tries) {
1091 ASD((" FAILED!\n"));
1092 return -1;
1093 }
1094 ASD((" SUCCESS and CSCONFIG_DFBYPASS\n"));
1095 if (!is_lucent_phy(hp)) {
1096 result = happy_meal_tcvr_read(hp, tregs,
1097 DP83840_CSCONFIG);
1098 happy_meal_tcvr_write(hp, tregs,
1099 DP83840_CSCONFIG, (result | CSCONFIG_DFBYPASS));
1100 }
1101 return 0;
1102}
1103
1104/* Figure out whether we have an internal or external transceiver.
1105 *
1106 * hp->happy_lock must be held
1107 */
1108static void happy_meal_transceiver_check(struct happy_meal *hp, void __iomem *tregs)
1109{
1110 unsigned long tconfig = hme_read32(hp, tregs + TCVR_CFG);
1111
1112 ASD(("happy_meal_transceiver_check: tcfg=%08lx ", tconfig));
1113 if (hp->happy_flags & HFLAG_POLL) {
1114 /* If we are polling, we must stop to get the transceiver type. */
1115 ASD(("<polling> "));
1116 if (hp->tcvr_type == internal) {
1117 if (tconfig & TCV_CFG_MDIO1) {
1118 ASD(("<internal> <poll stop> "));
1119 happy_meal_poll_stop(hp, tregs);
1120 hp->paddr = TCV_PADDR_ETX;
1121 hp->tcvr_type = external;
1122 ASD(("<external>\n"));
1123 tconfig &= ~(TCV_CFG_PENABLE);
1124 tconfig |= TCV_CFG_PSELECT;
1125 hme_write32(hp, tregs + TCVR_CFG, tconfig);
1126 }
1127 } else {
1128 if (hp->tcvr_type == external) {
1129 ASD(("<external> "));
1130 if (!(hme_read32(hp, tregs + TCVR_STATUS) >> 16)) {
1131 ASD(("<poll stop> "));
1132 happy_meal_poll_stop(hp, tregs);
1133 hp->paddr = TCV_PADDR_ITX;
1134 hp->tcvr_type = internal;
1135 ASD(("<internal>\n"));
1136 hme_write32(hp, tregs + TCVR_CFG,
1137 hme_read32(hp, tregs + TCVR_CFG) &
1138 ~(TCV_CFG_PSELECT));
1139 }
1140 ASD(("\n"));
1141 } else {
1142 ASD(("<none>\n"));
1143 }
1144 }
1145 } else {
1146 u32 reread = hme_read32(hp, tregs + TCVR_CFG);
1147
1148 /* Else we can just work off of the MDIO bits. */
1149 ASD(("<not polling> "));
1150 if (reread & TCV_CFG_MDIO1) {
1151 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1152 hp->paddr = TCV_PADDR_ETX;
1153 hp->tcvr_type = external;
1154 ASD(("<external>\n"));
1155 } else {
1156 if (reread & TCV_CFG_MDIO0) {
1157 hme_write32(hp, tregs + TCVR_CFG,
1158 tconfig & ~(TCV_CFG_PSELECT));
1159 hp->paddr = TCV_PADDR_ITX;
1160 hp->tcvr_type = internal;
1161 ASD(("<internal>\n"));
1162 } else {
1163 printk(KERN_ERR "happy meal: Transceiver and a coke please.");
1164 hp->tcvr_type = none; /* Grrr... */
1165 ASD(("<none>\n"));
1166 }
1167 }
1168 }
1169}
1170
1171/* The receive ring buffers are a bit tricky to get right. Here goes...
1172 *
1173 * The buffers we dma into must be 64 byte aligned. So we use a special
1174 * alloc_skb() routine for the happy meal to allocate 64 bytes more than
1175 * we really need.
1176 *
1177 * We use skb_reserve() to align the data block we get in the skb. We
1178 * also program the etxregs->cfg register to use an offset of 2. This
1179 * imperical constant plus the ethernet header size will always leave
1180 * us with a nicely aligned ip header once we pass things up to the
1181 * protocol layers.
1182 *
1183 * The numbers work out to:
1184 *
1185 * Max ethernet frame size 1518
1186 * Ethernet header size 14
1187 * Happy Meal base offset 2
1188 *
1189 * Say a skb data area is at 0xf001b010, and its size alloced is
1190 * (ETH_FRAME_LEN + 64 + 2) = (1514 + 64 + 2) = 1580 bytes.
1191 *
1192 * First our alloc_skb() routine aligns the data base to a 64 byte
1193 * boundary. We now have 0xf001b040 as our skb data address. We
1194 * plug this into the receive descriptor address.
1195 *
1196 * Next, we skb_reserve() 2 bytes to account for the Happy Meal offset.
1197 * So now the data we will end up looking at starts at 0xf001b042. When
1198 * the packet arrives, we will check out the size received and subtract
1199 * this from the skb->length. Then we just pass the packet up to the
1200 * protocols as is, and allocate a new skb to replace this slot we have
1201 * just received from.
1202 *
1203 * The ethernet layer will strip the ether header from the front of the
1204 * skb we just sent to it, this leaves us with the ip header sitting
1205 * nicely aligned at 0xf001b050. Also, for tcp and udp packets the
1206 * Happy Meal has even checksummed the tcp/udp data for us. The 16
1207 * bit checksum is obtained from the low bits of the receive descriptor
1208 * flags, thus:
1209 *
1210 * skb->csum = rxd->rx_flags & 0xffff;
84fa7933 1211 * skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4
LT		 1212 *
1213 * before sending off the skb to the protocols, and we are good as gold.
1214 */
1215static void happy_meal_clean_rings(struct happy_meal *hp)
1216{
1217 int i;
1218
1219 for (i = 0; i < RX_RING_SIZE; i++) {
1220 if (hp->rx_skbs[i] != NULL) {
1221 struct sk_buff *skb = hp->rx_skbs[i];
1222 struct happy_meal_rxd *rxd;
1223 u32 dma_addr;
1224
1225 rxd = &hp->happy_block->happy_meal_rxd[i];
1226 dma_addr = hme_read_desc32(hp, &rxd->rx_addr);
1227 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
1228 dev_kfree_skb_any(skb);
1229 hp->rx_skbs[i] = NULL;
1230 }
1231 }
1232
1233 for (i = 0; i < TX_RING_SIZE; i++) {
1234 if (hp->tx_skbs[i] != NULL) {
1235 struct sk_buff *skb = hp->tx_skbs[i];
1236 struct happy_meal_txd *txd;
1237 u32 dma_addr;
1238 int frag;
1239
1240 hp->tx_skbs[i] = NULL;
1241
1242 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1243 txd = &hp->happy_block->happy_meal_txd[i];
1244 dma_addr = hme_read_desc32(hp, &txd->tx_addr);
1245 hme_dma_unmap(hp, dma_addr,
1246 (hme_read_desc32(hp, &txd->tx_flags)
1247 & TXFLAG_SIZE),
1248 DMA_TODEVICE);
1249
1250 if (frag != skb_shinfo(skb)->nr_frags)
1251 i++;
1252 }
1253
1254 dev_kfree_skb_any(skb);
1255 }
1256 }
1257}
1258
1259/* hp->happy_lock must be held */
1260static void happy_meal_init_rings(struct happy_meal *hp)
1261{
1262 struct hmeal_init_block *hb = hp->happy_block;
1263 struct net_device *dev = hp->dev;
1264 int i;
1265
1266 HMD(("happy_meal_init_rings: counters to zero, "));
1267 hp->rx_new = hp->rx_old = hp->tx_new = hp->tx_old = 0;
1268
1269 /* Free any skippy bufs left around in the rings. */
1270 HMD(("clean, "));
1271 happy_meal_clean_rings(hp);
1272
1273 /* Now get new skippy bufs for the receive ring. */
1274 HMD(("init rxring, "));
1275 for (i = 0; i < RX_RING_SIZE; i++) {
1276 struct sk_buff *skb;
1277
1278 skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
1279 if (!skb) {
1280 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0);
1281 continue;
1282 }
1283 hp->rx_skbs[i] = skb;
1284 skb->dev = dev;
1285
1286 /* Because we reserve afterwards. */
1287 skb_put(skb, (ETH_FRAME_LEN + RX_OFFSET));
1288 hme_write_rxd(hp, &hb->happy_meal_rxd[i],
1289 (RXFLAG_OWN | ((RX_BUF_ALLOC_SIZE - RX_OFFSET) << 16)),
1290 hme_dma_map(hp, skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
1291 skb_reserve(skb, RX_OFFSET);
1292 }
1293
1294 HMD(("init txring, "));
1295 for (i = 0; i < TX_RING_SIZE; i++)
1296 hme_write_txd(hp, &hb->happy_meal_txd[i], 0, 0);
1297
1298 HMD(("done\n"));
1299}
1300
1301/* hp->happy_lock must be held */
1302static void happy_meal_begin_auto_negotiation(struct happy_meal *hp,
1303 void __iomem *tregs,
1304 struct ethtool_cmd *ep)
1305{
1306 int timeout;
1307
1308 /* Read all of the registers we are interested in now. */
1309 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1310 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1311 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1312 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1313
1314 /* XXX Check BMSR_ANEGCAPABLE, should not be necessary though. */
1315
1316 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1317 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1318 /* Advertise everything we can support. */
1319 if (hp->sw_bmsr & BMSR_10HALF)
1320 hp->sw_advertise |= (ADVERTISE_10HALF);
1321 else
1322 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1323
1324 if (hp->sw_bmsr & BMSR_10FULL)
1325 hp->sw_advertise |= (ADVERTISE_10FULL);
1326 else
1327 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1328 if (hp->sw_bmsr & BMSR_100HALF)
1329 hp->sw_advertise |= (ADVERTISE_100HALF);
1330 else
1331 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1332 if (hp->sw_bmsr & BMSR_100FULL)
1333 hp->sw_advertise |= (ADVERTISE_100FULL);
1334 else
1335 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1336 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1337
1338 /* XXX Currently no Happy Meal cards I know off support 100BaseT4,
1339 * XXX and this is because the DP83840 does not support it, changes
1340 * XXX would need to be made to the tx/rx logic in the driver as well
1341 * XXX so I completely skip checking for it in the BMSR for now.
1342 */
1343
1344#ifdef AUTO_SWITCH_DEBUG
1345 ASD(("%s: Advertising [ ", hp->dev->name));
1346 if (hp->sw_advertise & ADVERTISE_10HALF)
1347 ASD(("10H "));
1348 if (hp->sw_advertise & ADVERTISE_10FULL)
1349 ASD(("10F "));
1350 if (hp->sw_advertise & ADVERTISE_100HALF)
1351 ASD(("100H "));
1352 if (hp->sw_advertise & ADVERTISE_100FULL)
1353 ASD(("100F "));
1354#endif
1355
1356 /* Enable Auto-Negotiation, this is usually on already... */
1357 hp->sw_bmcr |= BMCR_ANENABLE;
1358 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1359
1360 /* Restart it to make sure it is going. */
1361 hp->sw_bmcr |= BMCR_ANRESTART;
1362 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1363
1364 /* BMCR_ANRESTART self clears when the process has begun. */
1365
1366 timeout = 64; /* More than enough. */
1367 while (--timeout) {
1368 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1369 if (!(hp->sw_bmcr & BMCR_ANRESTART))
1370 break; /* got it. */
1371 udelay(10);
1372 }
1373 if (!timeout) {
1374 printk(KERN_ERR "%s: Happy Meal would not start auto negotiation "
1375 "BMCR=0x%04x\n", hp->dev->name, hp->sw_bmcr);
1376 printk(KERN_NOTICE "%s: Performing force link detection.\n",
1377 hp->dev->name);
1378 goto force_link;
1379 } else {
1380 hp->timer_state = arbwait;
1381 }
1382 } else {
1383force_link:
1384 /* Force the link up, trying first a particular mode.
1385 * Either we are here at the request of ethtool or
1386 * because the Happy Meal would not start to autoneg.
1387 */
1388
1389 /* Disable auto-negotiation in BMCR, enable the duplex and
1390 * speed setting, init the timer state machine, and fire it off.
1391 */
1392 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1393 hp->sw_bmcr = BMCR_SPEED100;
1394 } else {
1395 if (ep->speed == SPEED_100)
1396 hp->sw_bmcr = BMCR_SPEED100;
1397 else
1398 hp->sw_bmcr = 0;
1399 if (ep->duplex == DUPLEX_FULL)
1400 hp->sw_bmcr |= BMCR_FULLDPLX;
1401 }
1402 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1403
1404 if (!is_lucent_phy(hp)) {
1405 /* OK, seems we need do disable the transceiver for the first
1406 * tick to make sure we get an accurate link state at the
1407 * second tick.
1408 */
1409 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
1410 DP83840_CSCONFIG);
1411 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
1412 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG,
1413 hp->sw_csconfig);
1414 }
1415 hp->timer_state = ltrywait;
1416 }
1417
1418 hp->timer_ticks = 0;
1419 hp->happy_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
1420 hp->happy_timer.data = (unsigned long) hp;
1421 hp->happy_timer.function = &happy_meal_timer;
1422 add_timer(&hp->happy_timer);
1423}
1424
1425/* hp->happy_lock must be held */
1426static int happy_meal_init(struct happy_meal *hp)
1427{
1428 void __iomem *gregs = hp->gregs;
1429 void __iomem *etxregs = hp->etxregs;
1430 void __iomem *erxregs = hp->erxregs;
1431 void __iomem *bregs = hp->bigmacregs;
1432 void __iomem *tregs = hp->tcvregs;
1433 u32 regtmp, rxcfg;
1434 unsigned char *e = &hp->dev->dev_addr[0];
1435
1436 /* If auto-negotiation timer is running, kill it. */
1437 del_timer(&hp->happy_timer);
1438
1439 HMD(("happy_meal_init: happy_flags[%08x] ",
1440 hp->happy_flags));
1441 if (!(hp->happy_flags & HFLAG_INIT)) {
1442 HMD(("set HFLAG_INIT, "));
1443 hp->happy_flags |= HFLAG_INIT;
1444 happy_meal_get_counters(hp, bregs);
1445 }
1446
1447 /* Stop polling. */
1448 HMD(("to happy_meal_poll_stop\n"));
1449 happy_meal_poll_stop(hp, tregs);
1450
1451 /* Stop transmitter and receiver. */
1452 HMD(("happy_meal_init: to happy_meal_stop\n"));
1453 happy_meal_stop(hp, gregs);
1454
1455 /* Alloc and reset the tx/rx descriptor chains. */
1456 HMD(("happy_meal_init: to happy_meal_init_rings\n"));
1457 happy_meal_init_rings(hp);
1458
1459 /* Shut up the MIF. */
1460 HMD(("happy_meal_init: Disable all MIF irqs (old[%08x]), ",
1461 hme_read32(hp, tregs + TCVR_IMASK)));
1462 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1463
1464 /* See if we can enable the MIF frame on this card to speak to the DP83840. */
1465 if (hp->happy_flags & HFLAG_FENABLE) {
1466 HMD(("use frame old[%08x], ",
1467 hme_read32(hp, tregs + TCVR_CFG)));
1468 hme_write32(hp, tregs + TCVR_CFG,
1469 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1470 } else {
1471 HMD(("use bitbang old[%08x], ",
1472 hme_read32(hp, tregs + TCVR_CFG)));
1473 hme_write32(hp, tregs + TCVR_CFG,
1474 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1475 }
1476
1477 /* Check the state of the transceiver. */
1478 HMD(("to happy_meal_transceiver_check\n"));
1479 happy_meal_transceiver_check(hp, tregs);
1480
1481 /* Put the Big Mac into a sane state. */
1482 HMD(("happy_meal_init: "));
1483 switch(hp->tcvr_type) {
1484 case none:
1485 /* Cannot operate if we don't know the transceiver type! */
1486 HMD(("AAIEEE no transceiver type, EAGAIN"));
1487 return -EAGAIN;
1488
1489 case internal:
1490 /* Using the MII buffers. */
1491 HMD(("internal, using MII, "));
1492 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1493 break;
1494
1495 case external:
1496 /* Not using the MII, disable it. */
1497 HMD(("external, disable MII, "));
1498 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1499 break;
1500 };
1501
1502 if (happy_meal_tcvr_reset(hp, tregs))
1503 return -EAGAIN;
1504
1505 /* Reset the Happy Meal Big Mac transceiver and the receiver. */
1506 HMD(("tx/rx reset, "));
1507 happy_meal_tx_reset(hp, bregs);
1508 happy_meal_rx_reset(hp, bregs);
1509
1510 /* Set jam size and inter-packet gaps to reasonable defaults. */
1511 HMD(("jsize/ipg1/ipg2, "));
1512 hme_write32(hp, bregs + BMAC_JSIZE, DEFAULT_JAMSIZE);
1513 hme_write32(hp, bregs + BMAC_IGAP1, DEFAULT_IPG1);
1514 hme_write32(hp, bregs + BMAC_IGAP2, DEFAULT_IPG2);
1515
1516 /* Load up the MAC address and random seed. */
1517 HMD(("rseed/macaddr, "));
1518
1519 /* The docs recommend to use the 10LSB of our MAC here. */
1520 hme_write32(hp, bregs + BMAC_RSEED, ((e[5] | e[4]<<8)&0x3ff));
1521
1522 hme_write32(hp, bregs + BMAC_MACADDR2, ((e[4] << 8) | e[5]));
1523 hme_write32(hp, bregs + BMAC_MACADDR1, ((e[2] << 8) | e[3]));
1524 hme_write32(hp, bregs + BMAC_MACADDR0, ((e[0] << 8) | e[1]));
1525
1526 HMD(("htable, "));
1527 if ((hp->dev->flags & IFF_ALLMULTI) ||
1528 (hp->dev->mc_count > 64)) {
1529 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
1530 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
1531 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
1532 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
1533 } else if ((hp->dev->flags & IFF_PROMISC) == 0) {
1534 u16 hash_table[4];
1535 struct dev_mc_list *dmi = hp->dev->mc_list;
1536 char *addrs;
1537 int i;
1538 u32 crc;
1539
1540 for (i = 0; i < 4; i++)
1541 hash_table[i] = 0;
1542
1543 for (i = 0; i < hp->dev->mc_count; i++) {
1544 addrs = dmi->dmi_addr;
1545 dmi = dmi->next;
1546
1547 if (!(*addrs & 1))
1548 continue;
1549
1550 crc = ether_crc_le(6, addrs);
1551 crc >>= 26;
1552 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1553 }
1554 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
1555 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
1556 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
1557 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
1558 } else {
1559 hme_write32(hp, bregs + BMAC_HTABLE3, 0);
1560 hme_write32(hp, bregs + BMAC_HTABLE2, 0);
1561 hme_write32(hp, bregs + BMAC_HTABLE1, 0);
1562 hme_write32(hp, bregs + BMAC_HTABLE0, 0);
1563 }
1564
1565 /* Set the RX and TX ring ptrs. */
1566 HMD(("ring ptrs rxr[%08x] txr[%08x]\n",
1567 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)),
1568 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))));
1569 hme_write32(hp, erxregs + ERX_RING,
1570 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)));
1571 hme_write32(hp, etxregs + ETX_RING,
1572 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)));
1573
1574 /* Parity issues in the ERX unit of some HME revisions can cause some
1575 * registers to not be written unless their parity is even. Detect such
1576 * lost writes and simply rewrite with a low bit set (which will be ignored
1577 * since the rxring needs to be 2K aligned).
1578 */
1579 if (hme_read32(hp, erxregs + ERX_RING) !=
1580 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)))
1581 hme_write32(hp, erxregs + ERX_RING,
1582 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0))
1583 | 0x4);
1584
1585 /* Set the supported burst sizes. */
1586 HMD(("happy_meal_init: old[%08x] bursts<",
1587 hme_read32(hp, gregs + GREG_CFG)));
1588
9e326acf 1589#ifndef CONFIG_SPARC
1da177e4
LT		 1590 /* It is always PCI and can handle 64byte bursts. */
1591 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST64);
1592#else
1593 if ((hp->happy_bursts & DMA_BURST64) &&
1594 ((hp->happy_flags & HFLAG_PCI) != 0
1595#ifdef CONFIG_SBUS
1596 || sbus_can_burst64(hp->happy_dev)
1597#endif
1598 || 0)) {
1599 u32 gcfg = GREG_CFG_BURST64;
1600
1601 /* I have no idea if I should set the extended
1602 * transfer mode bit for Cheerio, so for now I
1603 * do not. -DaveM
1604 */
1605#ifdef CONFIG_SBUS
1606 if ((hp->happy_flags & HFLAG_PCI) == 0 &&
1607 sbus_can_dma_64bit(hp->happy_dev)) {
1608 sbus_set_sbus64(hp->happy_dev,
1609 hp->happy_bursts);
1610 gcfg |= GREG_CFG_64BIT;
1611 }
1612#endif
1613
1614 HMD(("64>"));
1615 hme_write32(hp, gregs + GREG_CFG, gcfg);
1616 } else if (hp->happy_bursts & DMA_BURST32) {
1617 HMD(("32>"));
1618 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST32);
1619 } else if (hp->happy_bursts & DMA_BURST16) {
1620 HMD(("16>"));
1621 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST16);
1622 } else {
1623 HMD(("XXX>"));
1624 hme_write32(hp, gregs + GREG_CFG, 0);
1625 }
9e326acf 1626#endif /* CONFIG_SPARC */
1da177e4
LT		 1627
1628 /* Turn off interrupts we do not want to hear. */
1629 HMD((", enable global interrupts, "));
1630 hme_write32(hp, gregs + GREG_IMASK,
1631 (GREG_IMASK_GOTFRAME | GREG_IMASK_RCNTEXP |
1632 GREG_IMASK_SENTFRAME | GREG_IMASK_TXPERR));
1633
1634 /* Set the transmit ring buffer size. */
1635 HMD(("tx rsize=%d oreg[%08x], ", (int)TX_RING_SIZE,
1636 hme_read32(hp, etxregs + ETX_RSIZE)));
1637 hme_write32(hp, etxregs + ETX_RSIZE, (TX_RING_SIZE >> ETX_RSIZE_SHIFT) - 1);
1638
1639 /* Enable transmitter DVMA. */
1640 HMD(("tx dma enable old[%08x], ",
1641 hme_read32(hp, etxregs + ETX_CFG)));
1642 hme_write32(hp, etxregs + ETX_CFG,
1643 hme_read32(hp, etxregs + ETX_CFG) | ETX_CFG_DMAENABLE);
1644
1645 /* This chip really rots, for the receiver sometimes when you
1646 * write to its control registers not all the bits get there
1647 * properly. I cannot think of a sane way to provide complete
1648 * coverage for this hardware bug yet.
1649 */
1650 HMD(("erx regs bug old[%08x]\n",
1651 hme_read32(hp, erxregs + ERX_CFG)));
1652 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1653 regtmp = hme_read32(hp, erxregs + ERX_CFG);
1654 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1655 if (hme_read32(hp, erxregs + ERX_CFG) != ERX_CFG_DEFAULT(RX_OFFSET)) {
1656 printk(KERN_ERR "happy meal: Eieee, rx config register gets greasy fries.\n");
1657 printk(KERN_ERR "happy meal: Trying to set %08x, reread gives %08x\n",
1658 ERX_CFG_DEFAULT(RX_OFFSET), regtmp);
1659 /* XXX Should return failure here... */
1660 }
1661
1662 /* Enable Big Mac hash table filter. */
1663 HMD(("happy_meal_init: enable hash rx_cfg_old[%08x], ",
1664 hme_read32(hp, bregs + BMAC_RXCFG)));
1665 rxcfg = BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_REJME;
1666 if (hp->dev->flags & IFF_PROMISC)
1667 rxcfg |= BIGMAC_RXCFG_PMISC;
1668 hme_write32(hp, bregs + BMAC_RXCFG, rxcfg);
1669
1670 /* Let the bits settle in the chip. */
1671 udelay(10);
1672
1673 /* Ok, configure the Big Mac transmitter. */
1674 HMD(("BIGMAC init, "));
1675 regtmp = 0;
1676 if (hp->happy_flags & HFLAG_FULL)
1677 regtmp |= BIGMAC_TXCFG_FULLDPLX;
1678
1679 /* Don't turn on the "don't give up" bit for now. It could cause hme
1680 * to deadlock with the PHY if a Jabber occurs.
1681 */
1682 hme_write32(hp, bregs + BMAC_TXCFG, regtmp /*| BIGMAC_TXCFG_DGIVEUP*/);
1683
1684 /* Give up after 16 TX attempts. */
1685 hme_write32(hp, bregs + BMAC_ALIMIT, 16);
1686
1687 /* Enable the output drivers no matter what. */
1688 regtmp = BIGMAC_XCFG_ODENABLE;
1689
1690 /* If card can do lance mode, enable it. */
1691 if (hp->happy_flags & HFLAG_LANCE)
1692 regtmp |= (DEFAULT_IPG0 << 5) | BIGMAC_XCFG_LANCE;
1693
1694 /* Disable the MII buffers if using external transceiver. */
1695 if (hp->tcvr_type == external)
1696 regtmp |= BIGMAC_XCFG_MIIDISAB;
1697
1698 HMD(("XIF config old[%08x], ",
1699 hme_read32(hp, bregs + BMAC_XIFCFG)));
1700 hme_write32(hp, bregs + BMAC_XIFCFG, regtmp);
1701
1702 /* Start things up. */
1703 HMD(("tx old[%08x] and rx [%08x] ON!\n",
1704 hme_read32(hp, bregs + BMAC_TXCFG),
1705 hme_read32(hp, bregs + BMAC_RXCFG)));
1706 hme_write32(hp, bregs + BMAC_TXCFG,
1707 hme_read32(hp, bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE);
1708 hme_write32(hp, bregs + BMAC_RXCFG,
1709 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE);
1710
1711 /* Get the autonegotiation started, and the watch timer ticking. */
1712 happy_meal_begin_auto_negotiation(hp, tregs, NULL);
1713
1714 /* Success. */
1715 return 0;
1716}
1717
1718/* hp->happy_lock must be held */
1719static void happy_meal_set_initial_advertisement(struct happy_meal *hp)
1720{
1721 void __iomem *tregs = hp->tcvregs;
1722 void __iomem *bregs = hp->bigmacregs;
1723 void __iomem *gregs = hp->gregs;
1724
1725 happy_meal_stop(hp, gregs);
1726 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1727 if (hp->happy_flags & HFLAG_FENABLE)
1728 hme_write32(hp, tregs + TCVR_CFG,
1729 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1730 else
1731 hme_write32(hp, tregs + TCVR_CFG,
1732 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1733 happy_meal_transceiver_check(hp, tregs);
1734 switch(hp->tcvr_type) {
1735 case none:
1736 return;
1737 case internal:
1738 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1739 break;
1740 case external:
1741 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1742 break;
1743 };
1744 if (happy_meal_tcvr_reset(hp, tregs))
1745 return;
1746
1747 /* Latch PHY registers as of now. */
1748 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1749 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1750
1751 /* Advertise everything we can support. */
1752 if (hp->sw_bmsr & BMSR_10HALF)
1753 hp->sw_advertise |= (ADVERTISE_10HALF);
1754 else
1755 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1756
1757 if (hp->sw_bmsr & BMSR_10FULL)
1758 hp->sw_advertise |= (ADVERTISE_10FULL);
1759 else
1760 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1761 if (hp->sw_bmsr & BMSR_100HALF)
1762 hp->sw_advertise |= (ADVERTISE_100HALF);
1763 else
1764 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1765 if (hp->sw_bmsr & BMSR_100FULL)
1766 hp->sw_advertise |= (ADVERTISE_100FULL);
1767 else
1768 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1769
1770 /* Update the PHY advertisement register. */
1771 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1772}
1773
1774/* Once status is latched (by happy_meal_interrupt) it is cleared by
1775 * the hardware, so we cannot re-read it and get a correct value.
1776 *
1777 * hp->happy_lock must be held
1778 */
1779static int happy_meal_is_not_so_happy(struct happy_meal *hp, u32 status)
1780{
1781 int reset = 0;
6aa20a22 1782
1da177e4
LT		 1783 /* Only print messages for non-counter related interrupts. */
1784 if (status & (GREG_STAT_STSTERR | GREG_STAT_TFIFO_UND |
1785 GREG_STAT_MAXPKTERR | GREG_STAT_RXERR |
1786 GREG_STAT_RXPERR | GREG_STAT_RXTERR | GREG_STAT_EOPERR |
1787 GREG_STAT_MIFIRQ | GREG_STAT_TXEACK | GREG_STAT_TXLERR |
1788 GREG_STAT_TXPERR | GREG_STAT_TXTERR | GREG_STAT_SLVERR |
1789 GREG_STAT_SLVPERR))
1790 printk(KERN_ERR "%s: Error interrupt for happy meal, status = %08x\n",
1791 hp->dev->name, status);
1792
1793 if (status & GREG_STAT_RFIFOVF) {
1794 /* Receive FIFO overflow is harmless and the hardware will take
1795 care of it, just some packets are lost. Who cares. */
1796 printk(KERN_DEBUG "%s: Happy Meal receive FIFO overflow.\n", hp->dev->name);
1797 }
1798
1799 if (status & GREG_STAT_STSTERR) {
1800 /* BigMAC SQE link test failed. */
1801 printk(KERN_ERR "%s: Happy Meal BigMAC SQE test failed.\n", hp->dev->name);
1802 reset = 1;
1803 }
1804
1805 if (status & GREG_STAT_TFIFO_UND) {
1806 /* Transmit FIFO underrun, again DMA error likely. */
1807 printk(KERN_ERR "%s: Happy Meal transmitter FIFO underrun, DMA error.\n",
1808 hp->dev->name);
1809 reset = 1;
1810 }
1811
1812 if (status & GREG_STAT_MAXPKTERR) {
1813 /* Driver error, tried to transmit something larger
1814 * than ethernet max mtu.
1815 */
1816 printk(KERN_ERR "%s: Happy Meal MAX Packet size error.\n", hp->dev->name);
1817 reset = 1;
1818 }
1819
1820 if (status & GREG_STAT_NORXD) {
1821 /* This is harmless, it just means the system is
1822 * quite loaded and the incoming packet rate was
1823 * faster than the interrupt handler could keep up
1824 * with.
1825 */
1826 printk(KERN_INFO "%s: Happy Meal out of receive "
1827 "descriptors, packet dropped.\n",
1828 hp->dev->name);
1829 }
1830
1831 if (status & (GREG_STAT_RXERR|GREG_STAT_RXPERR|GREG_STAT_RXTERR)) {
1832 /* All sorts of DMA receive errors. */
1833 printk(KERN_ERR "%s: Happy Meal rx DMA errors [ ", hp->dev->name);
1834 if (status & GREG_STAT_RXERR)
1835 printk("GenericError ");
1836 if (status & GREG_STAT_RXPERR)
1837 printk("ParityError ");
1838 if (status & GREG_STAT_RXTERR)
1839 printk("RxTagBotch ");
1840 printk("]\n");
1841 reset = 1;
1842 }
1843
1844 if (status & GREG_STAT_EOPERR) {
1845 /* Driver bug, didn't set EOP bit in tx descriptor given
1846 * to the happy meal.
1847 */
1848 printk(KERN_ERR "%s: EOP not set in happy meal transmit descriptor!\n",
1849 hp->dev->name);
1850 reset = 1;
1851 }
1852
1853 if (status & GREG_STAT_MIFIRQ) {
1854 /* MIF signalled an interrupt, were we polling it? */
1855 printk(KERN_ERR "%s: Happy Meal MIF interrupt.\n", hp->dev->name);
1856 }
1857
1858 if (status &
1859 (GREG_STAT_TXEACK|GREG_STAT_TXLERR|GREG_STAT_TXPERR|GREG_STAT_TXTERR)) {
1860 /* All sorts of transmit DMA errors. */
1861 printk(KERN_ERR "%s: Happy Meal tx DMA errors [ ", hp->dev->name);
1862 if (status & GREG_STAT_TXEACK)
1863 printk("GenericError ");
1864 if (status & GREG_STAT_TXLERR)
1865 printk("LateError ");
1866 if (status & GREG_STAT_TXPERR)
1867 printk("ParityErro ");
1868 if (status & GREG_STAT_TXTERR)
1869 printk("TagBotch ");
1870 printk("]\n");
1871 reset = 1;
1872 }
1873
1874 if (status & (GREG_STAT_SLVERR|GREG_STAT_SLVPERR)) {
1875 /* Bus or parity error when cpu accessed happy meal registers
1876 * or it's internal FIFO's. Should never see this.
1877 */
1878 printk(KERN_ERR "%s: Happy Meal register access SBUS slave (%s) error.\n",
1879 hp->dev->name,
1880 (status & GREG_STAT_SLVPERR) ? "parity" : "generic");
1881 reset = 1;
1882 }
1883
1884 if (reset) {
1885 printk(KERN_NOTICE "%s: Resetting...\n", hp->dev->name);
1886 happy_meal_init(hp);
1887 return 1;
1888 }
1889 return 0;
1890}
1891
1892/* hp->happy_lock must be held */
1893static void happy_meal_mif_interrupt(struct happy_meal *hp)
1894{
1895 void __iomem *tregs = hp->tcvregs;
1896
1897 printk(KERN_INFO "%s: Link status change.\n", hp->dev->name);
1898 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1899 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
1900
1901 /* Use the fastest transmission protocol possible. */
1902 if (hp->sw_lpa & LPA_100FULL) {
1903 printk(KERN_INFO "%s: Switching to 100Mbps at full duplex.", hp->dev->name);
1904 hp->sw_bmcr |= (BMCR_FULLDPLX | BMCR_SPEED100);
1905 } else if (hp->sw_lpa & LPA_100HALF) {
1906 printk(KERN_INFO "%s: Switching to 100MBps at half duplex.", hp->dev->name);
1907 hp->sw_bmcr |= BMCR_SPEED100;
1908 } else if (hp->sw_lpa & LPA_10FULL) {
1909 printk(KERN_INFO "%s: Switching to 10MBps at full duplex.", hp->dev->name);
1910 hp->sw_bmcr |= BMCR_FULLDPLX;
1911 } else {
1912 printk(KERN_INFO "%s: Using 10Mbps at half duplex.", hp->dev->name);
1913 }
1914 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1915
1916 /* Finally stop polling and shut up the MIF. */
1917 happy_meal_poll_stop(hp, tregs);
1918}
1919
1920#ifdef TXDEBUG
1921#define TXD(x) printk x
1922#else
1923#define TXD(x)
1924#endif
1925
1926/* hp->happy_lock must be held */
1927static void happy_meal_tx(struct happy_meal *hp)
1928{
1929 struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0];
1930 struct happy_meal_txd *this;
1931 struct net_device *dev = hp->dev;
1932 int elem;
1933
1934 elem = hp->tx_old;
1935 TXD(("TX<"));
1936 while (elem != hp->tx_new) {
1937 struct sk_buff *skb;
1938 u32 flags, dma_addr, dma_len;
1939 int frag;
1940
1941 TXD(("[%d]", elem));
1942 this = &txbase[elem];
1943 flags = hme_read_desc32(hp, &this->tx_flags);
1944 if (flags & TXFLAG_OWN)
1945 break;
1946 skb = hp->tx_skbs[elem];
1947 if (skb_shinfo(skb)->nr_frags) {
1948 int last;
1949
1950 last = elem + skb_shinfo(skb)->nr_frags;
1951 last &= (TX_RING_SIZE - 1);
1952 flags = hme_read_desc32(hp, &txbase[last].tx_flags);
1953 if (flags & TXFLAG_OWN)
1954 break;
1955 }
1956 hp->tx_skbs[elem] = NULL;
1957 hp->net_stats.tx_bytes += skb->len;
1958
1959 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1960 dma_addr = hme_read_desc32(hp, &this->tx_addr);
1961 dma_len = hme_read_desc32(hp, &this->tx_flags);
1962
1963 dma_len &= TXFLAG_SIZE;
1964 hme_dma_unmap(hp, dma_addr, dma_len, DMA_TODEVICE);
1965
1966 elem = NEXT_TX(elem);
1967 this = &txbase[elem];
1968 }
1969
1970 dev_kfree_skb_irq(skb);
1971 hp->net_stats.tx_packets++;
1972 }
1973 hp->tx_old = elem;
1974 TXD((">"));
1975
1976 if (netif_queue_stopped(dev) &&
1977 TX_BUFFS_AVAIL(hp) > (MAX_SKB_FRAGS + 1))
1978 netif_wake_queue(dev);
1979}
1980
1981#ifdef RXDEBUG
1982#define RXD(x) printk x
1983#else
1984#define RXD(x)
1985#endif
1986
1987/* Originally I used to handle the allocation failure by just giving back just
1988 * that one ring buffer to the happy meal. Problem is that usually when that
1989 * condition is triggered, the happy meal expects you to do something reasonable
1990 * with all of the packets it has DMA'd in. So now I just drop the entire
1991 * ring when we cannot get a new skb and give them all back to the happy meal,
1992 * maybe things will be "happier" now.
1993 *
1994 * hp->happy_lock must be held
1995 */
1996static void happy_meal_rx(struct happy_meal *hp, struct net_device *dev)
1997{
1998 struct happy_meal_rxd *rxbase = &hp->happy_block->happy_meal_rxd[0];
1999 struct happy_meal_rxd *this;
2000 int elem = hp->rx_new, drops = 0;
2001 u32 flags;
2002
2003 RXD(("RX<"));
2004 this = &rxbase[elem];
2005 while (!((flags = hme_read_desc32(hp, &this->rx_flags)) & RXFLAG_OWN)) {
2006 struct sk_buff *skb;
2007 int len = flags >> 16;
2008 u16 csum = flags & RXFLAG_CSUM;
2009 u32 dma_addr = hme_read_desc32(hp, &this->rx_addr);
2010
2011 RXD(("[%d ", elem));
2012
2013 /* Check for errors. */
2014 if ((len < ETH_ZLEN) || (flags & RXFLAG_OVERFLOW)) {
2015 RXD(("ERR(%08x)]", flags));
2016 hp->net_stats.rx_errors++;
2017 if (len < ETH_ZLEN)
2018 hp->net_stats.rx_length_errors++;
2019 if (len & (RXFLAG_OVERFLOW >> 16)) {
2020 hp->net_stats.rx_over_errors++;
2021 hp->net_stats.rx_fifo_errors++;
2022 }
2023
2024 /* Return it to the Happy meal. */
2025 drop_it:
2026 hp->net_stats.rx_dropped++;
2027 hme_write_rxd(hp, this,
2028 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2029 dma_addr);
2030 goto next;
2031 }
2032 skb = hp->rx_skbs[elem];
2033 if (len > RX_COPY_THRESHOLD) {
2034 struct sk_buff *new_skb;
2035
2036 /* Now refill the entry, if we can. */
2037 new_skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
2038 if (new_skb == NULL) {
2039 drops++;
2040 goto drop_it;
2041 }
2042 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
2043 hp->rx_skbs[elem] = new_skb;
2044 new_skb->dev = dev;
2045 skb_put(new_skb, (ETH_FRAME_LEN + RX_OFFSET));
2046 hme_write_rxd(hp, this,
2047 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2048 hme_dma_map(hp, new_skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
2049 skb_reserve(new_skb, RX_OFFSET);
2050
2051 /* Trim the original skb for the netif. */
2052 skb_trim(skb, len);
2053 } else {
2054 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
2055
2056 if (copy_skb == NULL) {
2057 drops++;
2058 goto drop_it;
2059 }
2060
1da177e4
LT		 2061 skb_reserve(copy_skb, 2);
2062 skb_put(copy_skb, len);
2063 hme_dma_sync_for_cpu(hp, dma_addr, len, DMA_FROMDEVICE);
d626f62b 2064 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 2065 hme_dma_sync_for_device(hp, dma_addr, len, DMA_FROMDEVICE);
2066
2067 /* Reuse original ring buffer. */
2068 hme_write_rxd(hp, this,
2069 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2070 dma_addr);
2071
2072 skb = copy_skb;
2073 }
2074
2075 /* This card is _fucking_ hot... */
2076 skb->csum = ntohs(csum ^ 0xffff);
84fa7933 2077 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4
LT		 2078
2079 RXD(("len=%d csum=%4x]", len, csum));
2080 skb->protocol = eth_type_trans(skb, dev);
2081 netif_rx(skb);
2082
2083 dev->last_rx = jiffies;
2084 hp->net_stats.rx_packets++;
2085 hp->net_stats.rx_bytes += len;
2086 next:
2087 elem = NEXT_RX(elem);
2088 this = &rxbase[elem];
2089 }
2090 hp->rx_new = elem;
2091 if (drops)
2092 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", hp->dev->name);
2093 RXD((">"));
2094}
2095
7d12e780 2096static irqreturn_t happy_meal_interrupt(int irq, void *dev_id)
1da177e4 2097{
c31f28e7
JG		 2098 struct net_device *dev = dev_id;
2099 struct happy_meal *hp = netdev_priv(dev);
1da177e4
LT		 2100 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2101
2102 HMD(("happy_meal_interrupt: status=%08x ", happy_status));
2103
2104 spin_lock(&hp->happy_lock);
2105
2106 if (happy_status & GREG_STAT_ERRORS) {
2107 HMD(("ERRORS "));
2108 if (happy_meal_is_not_so_happy(hp, /* un- */ happy_status))
2109 goto out;
2110 }
2111
2112 if (happy_status & GREG_STAT_MIFIRQ) {
2113 HMD(("MIFIRQ "));
2114 happy_meal_mif_interrupt(hp);
2115 }
2116
2117 if (happy_status & GREG_STAT_TXALL) {
2118 HMD(("TXALL "));
2119 happy_meal_tx(hp);
2120 }
2121
2122 if (happy_status & GREG_STAT_RXTOHOST) {
2123 HMD(("RXTOHOST "));
2124 happy_meal_rx(hp, dev);
2125 }
2126
2127 HMD(("done\n"));
2128out:
2129 spin_unlock(&hp->happy_lock);
2130
2131 return IRQ_HANDLED;
2132}
2133
2134#ifdef CONFIG_SBUS
7d12e780 2135static irqreturn_t quattro_sbus_interrupt(int irq, void *cookie)
1da177e4
LT		 2136{
2137 struct quattro *qp = (struct quattro *) cookie;
2138 int i;
2139
2140 for (i = 0; i < 4; i++) {
2141 struct net_device *dev = qp->happy_meals[i];
2142 struct happy_meal *hp = dev->priv;
2143 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2144
2145 HMD(("quattro_interrupt: status=%08x ", happy_status));
2146
2147 if (!(happy_status & (GREG_STAT_ERRORS |
2148 GREG_STAT_MIFIRQ |
2149 GREG_STAT_TXALL |
2150 GREG_STAT_RXTOHOST)))
2151 continue;
2152
2153 spin_lock(&hp->happy_lock);
2154
2155 if (happy_status & GREG_STAT_ERRORS) {
2156 HMD(("ERRORS "));
2157 if (happy_meal_is_not_so_happy(hp, happy_status))
2158 goto next;
2159 }
2160
2161 if (happy_status & GREG_STAT_MIFIRQ) {
2162 HMD(("MIFIRQ "));
2163 happy_meal_mif_interrupt(hp);
2164 }
2165
2166 if (happy_status & GREG_STAT_TXALL) {
2167 HMD(("TXALL "));
2168 happy_meal_tx(hp);
2169 }
2170
2171 if (happy_status & GREG_STAT_RXTOHOST) {
2172 HMD(("RXTOHOST "));
2173 happy_meal_rx(hp, dev);
2174 }
2175
2176 next:
2177 spin_unlock(&hp->happy_lock);
2178 }
2179 HMD(("done\n"));
2180
2181 return IRQ_HANDLED;
2182}
2183#endif
2184
2185static int happy_meal_open(struct net_device *dev)
2186{
2187 struct happy_meal *hp = dev->priv;
2188 int res;
2189
2190 HMD(("happy_meal_open: "));
2191
2192 /* On SBUS Quattro QFE cards, all hme interrupts are concentrated
2193 * into a single source which we register handling at probe time.
2194 */
2195 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO) {
2196 if (request_irq(dev->irq, &happy_meal_interrupt,
1fb9df5d 2197 IRQF_SHARED, dev->name, (void *)dev)) {
1da177e4 2198 HMD(("EAGAIN\n"));
1da177e4
LT		 2199 printk(KERN_ERR "happy_meal(SBUS): Can't order irq %d to go.\n",
2200 dev->irq);
1da177e4
LT		 2201
2202 return -EAGAIN;
2203 }
2204 }
2205
2206 HMD(("to happy_meal_init\n"));
2207
2208 spin_lock_irq(&hp->happy_lock);
2209 res = happy_meal_init(hp);
2210 spin_unlock_irq(&hp->happy_lock);
2211
2212 if (res && ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO))
2213 free_irq(dev->irq, dev);
2214 return res;
2215}
2216
2217static int happy_meal_close(struct net_device *dev)
2218{
2219 struct happy_meal *hp = dev->priv;
2220
2221 spin_lock_irq(&hp->happy_lock);
2222 happy_meal_stop(hp, hp->gregs);
2223 happy_meal_clean_rings(hp);
2224
2225 /* If auto-negotiation timer is running, kill it. */
2226 del_timer(&hp->happy_timer);
2227
2228 spin_unlock_irq(&hp->happy_lock);
2229
2230 /* On Quattro QFE cards, all hme interrupts are concentrated
2231 * into a single source which we register handling at probe
2232 * time and never unregister.
2233 */
2234 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO)
2235 free_irq(dev->irq, dev);
2236
2237 return 0;
2238}
2239
2240#ifdef SXDEBUG
2241#define SXD(x) printk x
2242#else
2243#define SXD(x)
2244#endif
2245
2246static void happy_meal_tx_timeout(struct net_device *dev)
2247{
2248 struct happy_meal *hp = dev->priv;
2249
2250 printk (KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2251 tx_dump_log();
2252 printk (KERN_ERR "%s: Happy Status %08x TX[%08x:%08x]\n", dev->name,
2253 hme_read32(hp, hp->gregs + GREG_STAT),
2254 hme_read32(hp, hp->etxregs + ETX_CFG),
2255 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG));
2256
2257 spin_lock_irq(&hp->happy_lock);
2258 happy_meal_init(hp);
2259 spin_unlock_irq(&hp->happy_lock);
2260
2261 netif_wake_queue(dev);
2262}
2263
2264static int happy_meal_start_xmit(struct sk_buff *skb, struct net_device *dev)
2265{
2266 struct happy_meal *hp = dev->priv;
2267 int entry;
2268 u32 tx_flags;
2269
2270 tx_flags = TXFLAG_OWN;
84fa7933 2271 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ea2ae17d
ACM		 2272 const u32 csum_start_off = skb_transport_offset(skb);
2273 const u32 csum_stuff_off = csum_start_off + skb->csum_offset;
1da177e4
LT		 2274
2275 tx_flags = (TXFLAG_OWN | TXFLAG_CSENABLE |
2276 ((csum_start_off << 14) & TXFLAG_CSBUFBEGIN) |
2277 ((csum_stuff_off << 20) & TXFLAG_CSLOCATION));
2278 }
2279
2280 spin_lock_irq(&hp->happy_lock);
2281
2282 if (TX_BUFFS_AVAIL(hp) <= (skb_shinfo(skb)->nr_frags + 1)) {
2283 netif_stop_queue(dev);
2284 spin_unlock_irq(&hp->happy_lock);
2285 printk(KERN_ERR "%s: BUG! Tx Ring full when queue awake!\n",
2286 dev->name);
2287 return 1;
2288 }
2289
2290 entry = hp->tx_new;
2291 SXD(("SX<l[%d]e[%d]>", len, entry));
2292 hp->tx_skbs[entry] = skb;
2293
2294 if (skb_shinfo(skb)->nr_frags == 0) {
2295 u32 mapping, len;
2296
2297 len = skb->len;
2298 mapping = hme_dma_map(hp, skb->data, len, DMA_TODEVICE);
2299 tx_flags |= (TXFLAG_SOP | TXFLAG_EOP);
2300 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2301 (tx_flags | (len & TXFLAG_SIZE)),
2302 mapping);
2303 entry = NEXT_TX(entry);
2304 } else {
2305 u32 first_len, first_mapping;
2306 int frag, first_entry = entry;
2307
2308 /* We must give this initial chunk to the device last.
2309 * Otherwise we could race with the device.
2310 */
2311 first_len = skb_headlen(skb);
2312 first_mapping = hme_dma_map(hp, skb->data, first_len, DMA_TODEVICE);
2313 entry = NEXT_TX(entry);
2314
2315 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
2316 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
2317 u32 len, mapping, this_txflags;
2318
2319 len = this_frag->size;
2320 mapping = hme_dma_map(hp,
2321 ((void *) page_address(this_frag->page) +
2322 this_frag->page_offset),
2323 len, DMA_TODEVICE);
2324 this_txflags = tx_flags;
2325 if (frag == skb_shinfo(skb)->nr_frags - 1)
2326 this_txflags |= TXFLAG_EOP;
2327 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2328 (this_txflags | (len & TXFLAG_SIZE)),
2329 mapping);
2330 entry = NEXT_TX(entry);
2331 }
2332 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[first_entry],
2333 (tx_flags | TXFLAG_SOP | (first_len & TXFLAG_SIZE)),
2334 first_mapping);
2335 }
2336
2337 hp->tx_new = entry;
2338
2339 if (TX_BUFFS_AVAIL(hp) <= (MAX_SKB_FRAGS + 1))
2340 netif_stop_queue(dev);
2341
2342 /* Get it going. */
2343 hme_write32(hp, hp->etxregs + ETX_PENDING, ETX_TP_DMAWAKEUP);
2344
2345 spin_unlock_irq(&hp->happy_lock);
2346
2347 dev->trans_start = jiffies;
2348
2349 tx_add_log(hp, TXLOG_ACTION_TXMIT, 0);
2350 return 0;
2351}
2352
2353static struct net_device_stats *happy_meal_get_stats(struct net_device *dev)
2354{
2355 struct happy_meal *hp = dev->priv;
2356
2357 spin_lock_irq(&hp->happy_lock);
2358 happy_meal_get_counters(hp, hp->bigmacregs);
2359 spin_unlock_irq(&hp->happy_lock);
2360
2361 return &hp->net_stats;
2362}
2363
2364static void happy_meal_set_multicast(struct net_device *dev)
2365{
2366 struct happy_meal *hp = dev->priv;
2367 void __iomem *bregs = hp->bigmacregs;
2368 struct dev_mc_list *dmi = dev->mc_list;
2369 char *addrs;
2370 int i;
2371 u32 crc;
2372
2373 spin_lock_irq(&hp->happy_lock);
2374
2375 netif_stop_queue(dev);
2376
2377 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
2378 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
2379 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
2380 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
2381 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
2382 } else if (dev->flags & IFF_PROMISC) {
2383 hme_write32(hp, bregs + BMAC_RXCFG,
2384 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_PMISC);
2385 } else {
2386 u16 hash_table[4];
2387
2388 for (i = 0; i < 4; i++)
2389 hash_table[i] = 0;
2390
2391 for (i = 0; i < dev->mc_count; i++) {
2392 addrs = dmi->dmi_addr;
2393 dmi = dmi->next;
2394
2395 if (!(*addrs & 1))
2396 continue;
2397
2398 crc = ether_crc_le(6, addrs);
2399 crc >>= 26;
2400 hash_table[crc >> 4] |= 1 << (crc & 0xf);
2401 }
2402 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
2403 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
2404 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
2405 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
2406 }
2407
2408 netif_wake_queue(dev);
2409
2410 spin_unlock_irq(&hp->happy_lock);
2411}
2412
2413/* Ethtool support... */
2414static int hme_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2415{
2416 struct happy_meal *hp = dev->priv;
2417
2418 cmd->supported =
2419 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2420 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2421 SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
2422
2423 /* XXX hardcoded stuff for now */
2424 cmd->port = PORT_TP; /* XXX no MII support */
2425 cmd->transceiver = XCVR_INTERNAL; /* XXX no external xcvr support */
2426 cmd->phy_address = 0; /* XXX fixed PHYAD */
2427
2428 /* Record PHY settings. */
2429 spin_lock_irq(&hp->happy_lock);
2430 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2431 hp->sw_lpa = happy_meal_tcvr_read(hp, hp->tcvregs, MII_LPA);
2432 spin_unlock_irq(&hp->happy_lock);
2433
2434 if (hp->sw_bmcr & BMCR_ANENABLE) {
2435 cmd->autoneg = AUTONEG_ENABLE;
2436 cmd->speed =
2437 (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) ?
2438 SPEED_100 : SPEED_10;
2439 if (cmd->speed == SPEED_100)
2440 cmd->duplex =
2441 (hp->sw_lpa & (LPA_100FULL)) ?
2442 DUPLEX_FULL : DUPLEX_HALF;
2443 else
2444 cmd->duplex =
2445 (hp->sw_lpa & (LPA_10FULL)) ?
2446 DUPLEX_FULL : DUPLEX_HALF;
2447 } else {
2448 cmd->autoneg = AUTONEG_DISABLE;
2449 cmd->speed =
2450 (hp->sw_bmcr & BMCR_SPEED100) ?
2451 SPEED_100 : SPEED_10;
2452 cmd->duplex =
2453 (hp->sw_bmcr & BMCR_FULLDPLX) ?
2454 DUPLEX_FULL : DUPLEX_HALF;
2455 }
2456 return 0;
2457}
2458
2459static int hme_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2460{
2461 struct happy_meal *hp = dev->priv;
2462
2463 /* Verify the settings we care about. */
2464 if (cmd->autoneg != AUTONEG_ENABLE &&
2465 cmd->autoneg != AUTONEG_DISABLE)
2466 return -EINVAL;
2467 if (cmd->autoneg == AUTONEG_DISABLE &&
2468 ((cmd->speed != SPEED_100 &&
2469 cmd->speed != SPEED_10) ||
2470 (cmd->duplex != DUPLEX_HALF &&
2471 cmd->duplex != DUPLEX_FULL)))
2472 return -EINVAL;
2473
2474 /* Ok, do it to it. */
2475 spin_lock_irq(&hp->happy_lock);
2476 del_timer(&hp->happy_timer);
2477 happy_meal_begin_auto_negotiation(hp, hp->tcvregs, cmd);
2478 spin_unlock_irq(&hp->happy_lock);
2479
2480 return 0;
2481}
2482
2483static void hme_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2484{
2485 struct happy_meal *hp = dev->priv;
2486
2487 strcpy(info->driver, "sunhme");
2488 strcpy(info->version, "2.02");
2489 if (hp->happy_flags & HFLAG_PCI) {
2490 struct pci_dev *pdev = hp->happy_dev;
2491 strcpy(info->bus_info, pci_name(pdev));
2492 }
2493#ifdef CONFIG_SBUS
2494 else {
2495 struct sbus_dev *sdev = hp->happy_dev;
2496 sprintf(info->bus_info, "SBUS:%d",
2497 sdev->slot);
2498 }
2499#endif
2500}
2501
2502static u32 hme_get_link(struct net_device *dev)
2503{
2504 struct happy_meal *hp = dev->priv;
2505
2506 spin_lock_irq(&hp->happy_lock);
2507 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2508 spin_unlock_irq(&hp->happy_lock);
2509
2510 return (hp->sw_bmsr & BMSR_LSTATUS);
2511}
2512
7282d491 2513static const struct ethtool_ops hme_ethtool_ops = {
1da177e4
LT		 2514 .get_settings = hme_get_settings,
2515 .set_settings = hme_set_settings,
2516 .get_drvinfo = hme_get_drvinfo,
2517 .get_link = hme_get_link,
2518};
2519
2520static int hme_version_printed;
2521
2522#ifdef CONFIG_SBUS
6002e450 2523void __devinit quattro_get_ranges(struct quattro *qp)
1da177e4
LT		 2524{
2525 struct sbus_dev *sdev = qp->quattro_dev;
2526 int err;
2527
2528 err = prom_getproperty(sdev->prom_node,
2529 "ranges",
2530 (char *)&qp->ranges[0],
2531 sizeof(qp->ranges));
2532 if (err == 0 || err == -1) {
2533 qp->nranges = 0;
2534 return;
2535 }
2536 qp->nranges = (err / sizeof(struct linux_prom_ranges));
2537}
2538
6002e450 2539static void __devinit quattro_apply_ranges(struct quattro *qp, struct happy_meal *hp)
1da177e4
LT		 2540{
2541 struct sbus_dev *sdev = hp->happy_dev;
2542 int rng;
2543
2544 for (rng = 0; rng < qp->nranges; rng++) {
2545 struct linux_prom_ranges *rngp = &qp->ranges[rng];
2546 int reg;
2547
2548 for (reg = 0; reg < 5; reg++) {
2549 if (sdev->reg_addrs[reg].which_io ==
2550 rngp->ot_child_space)
2551 break;
2552 }
2553 if (reg == 5)
2554 continue;
2555
2556 sdev->reg_addrs[reg].which_io = rngp->ot_parent_space;
2557 sdev->reg_addrs[reg].phys_addr += rngp->ot_parent_base;
2558 }
2559}
2560
2561/* Given a happy meal sbus device, find it's quattro parent.
2562 * If none exist, allocate and return a new one.
2563 *
2564 * Return NULL on failure.
2565 */
6002e450 2566static struct quattro * __devinit quattro_sbus_find(struct sbus_dev *goal_sdev)
1da177e4 2567{
1da177e4
LT		 2568 struct sbus_dev *sdev;
2569 struct quattro *qp;
2570 int i;
2571
1da177e4
LT		 2572 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2573 for (i = 0, sdev = qp->quattro_dev;
2574 (sdev != NULL) && (i < 4);
2575 sdev = sdev->next, i++) {
2576 if (sdev == goal_sdev)
2577 return qp;
2578 }
2579 }
1da177e4 2580
1da177e4
LT		 2581 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2582 if (qp != NULL) {
2583 int i;
2584
2585 for (i = 0; i < 4; i++)
2586 qp->happy_meals[i] = NULL;
2587
2588 qp->quattro_dev = goal_sdev;
2589 qp->next = qfe_sbus_list;
2590 qfe_sbus_list = qp;
2591 quattro_get_ranges(qp);
2592 }
2593 return qp;
2594}
2595
2596/* After all quattro cards have been probed, we call these functions
2597 * to register the IRQ handlers.
2598 */
2599static void __init quattro_sbus_register_irqs(void)
2600{
2601 struct quattro *qp;
2602
2603 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2604 struct sbus_dev *sdev = qp->quattro_dev;
2605 int err;
2606
2607 err = request_irq(sdev->irqs[0],
2608 quattro_sbus_interrupt,
1fb9df5d 2609 IRQF_SHARED, "Quattro",
1da177e4
LT		 2610 qp);
2611 if (err != 0) {
2612 printk(KERN_ERR "Quattro: Fatal IRQ registery error %d.\n", err);
2613 panic("QFE request irq");
2614 }
2615 }
2616}
050bbb19 2617
6002e450 2618static void quattro_sbus_free_irqs(void)
050bbb19
DM		 2619{
2620 struct quattro *qp;
2621
2622 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2623 struct sbus_dev *sdev = qp->quattro_dev;
2624
2625 free_irq(sdev->irqs[0], qp);
2626 }
2627}
1da177e4
LT		 2628#endif /* CONFIG_SBUS */
2629
2630#ifdef CONFIG_PCI
2631static struct quattro * __init quattro_pci_find(struct pci_dev *pdev)
2632{
2633 struct pci_dev *bdev = pdev->bus->self;
2634 struct quattro *qp;
2635
2636 if (!bdev) return NULL;
2637 for (qp = qfe_pci_list; qp != NULL; qp = qp->next) {
2638 struct pci_dev *qpdev = qp->quattro_dev;
2639
2640 if (qpdev == bdev)
2641 return qp;
2642 }
2643 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2644 if (qp != NULL) {
2645 int i;
2646
2647 for (i = 0; i < 4; i++)
2648 qp->happy_meals[i] = NULL;
2649
2650 qp->quattro_dev = bdev;
2651 qp->next = qfe_pci_list;
2652 qfe_pci_list = qp;
2653
2654 /* No range tricks necessary on PCI. */
2655 qp->nranges = 0;
2656 }
2657 return qp;
2658}
2659#endif /* CONFIG_PCI */
2660
2661#ifdef CONFIG_SBUS
6002e450 2662static int __devinit happy_meal_sbus_probe_one(struct sbus_dev *sdev, int is_qfe)
1da177e4 2663{
050bbb19 2664 struct device_node *dp = sdev->ofdev.node;
1da177e4
LT		 2665 struct quattro *qp = NULL;
2666 struct happy_meal *hp;
2667 struct net_device *dev;
2668 int i, qfe_slot = -1;
2669 int err = -ENODEV;
2670
2671 if (is_qfe) {
2672 qp = quattro_sbus_find(sdev);
2673 if (qp == NULL)
2674 goto err_out;
2675 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
2676 if (qp->happy_meals[qfe_slot] == NULL)
2677 break;
2678 if (qfe_slot == 4)
2679 goto err_out;
2680 }
2681
2682 err = -ENOMEM;
2683 dev = alloc_etherdev(sizeof(struct happy_meal));
2684 if (!dev)
2685 goto err_out;
2686 SET_MODULE_OWNER(dev);
050bbb19 2687 SET_NETDEV_DEV(dev, &sdev->ofdev.dev);
1da177e4
LT		 2688
2689 if (hme_version_printed++ == 0)
2690 printk(KERN_INFO "%s", version);
2691
2692 /* If user did not specify a MAC address specifically, use
2693 * the Quattro local-mac-address property...
2694 */
2695 for (i = 0; i < 6; i++) {
2696 if (macaddr[i] != 0)
2697 break;
2698 }
2699 if (i < 6) { /* a mac address was given */
2700 for (i = 0; i < 6; i++)
2701 dev->dev_addr[i] = macaddr[i];
2702 macaddr[5]++;
1da177e4 2703 } else {
050bbb19
DM		 2704 unsigned char *addr;
2705 int len;
2706
2707 addr = of_get_property(dp, "local-mac-address", &len);
2708
2709 if (qfe_slot != -1 && addr && len == 6)
2710 memcpy(dev->dev_addr, addr, 6);
2711 else
2712 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 2713 }
2714
2715 hp = dev->priv;
2716
2717 hp->happy_dev = sdev;
2718
2719 spin_lock_init(&hp->happy_lock);
2720
2721 err = -ENODEV;
2722 if (sdev->num_registers != 5) {
050bbb19 2723 printk(KERN_ERR "happymeal: Device needs 5 regs, has %d.\n",
1da177e4 2724 sdev->num_registers);
1da177e4
LT		 2725 goto err_out_free_netdev;
2726 }
2727
2728 if (qp != NULL) {
2729 hp->qfe_parent = qp;
2730 hp->qfe_ent = qfe_slot;
2731 qp->happy_meals[qfe_slot] = dev;
2732 quattro_apply_ranges(qp, hp);
2733 }
2734
2735 hp->gregs = sbus_ioremap(&sdev->resource[0], 0,
2736 GREG_REG_SIZE, "HME Global Regs");
2737 if (!hp->gregs) {
050bbb19 2738 printk(KERN_ERR "happymeal: Cannot map global registers.\n");
1da177e4
LT		 2739 goto err_out_free_netdev;
2740 }
2741
2742 hp->etxregs = sbus_ioremap(&sdev->resource[1], 0,
2743 ETX_REG_SIZE, "HME TX Regs");
2744 if (!hp->etxregs) {
050bbb19 2745 printk(KERN_ERR "happymeal: Cannot map MAC TX registers.\n");
1da177e4
LT		 2746 goto err_out_iounmap;
2747 }
2748
2749 hp->erxregs = sbus_ioremap(&sdev->resource[2], 0,
2750 ERX_REG_SIZE, "HME RX Regs");
2751 if (!hp->erxregs) {
050bbb19 2752 printk(KERN_ERR "happymeal: Cannot map MAC RX registers.\n");
1da177e4
LT		 2753 goto err_out_iounmap;
2754 }
2755
2756 hp->bigmacregs = sbus_ioremap(&sdev->resource[3], 0,
2757 BMAC_REG_SIZE, "HME BIGMAC Regs");
2758 if (!hp->bigmacregs) {
050bbb19 2759 printk(KERN_ERR "happymeal: Cannot map BIGMAC registers.\n");
1da177e4
LT		 2760 goto err_out_iounmap;
2761 }
2762
2763 hp->tcvregs = sbus_ioremap(&sdev->resource[4], 0,
2764 TCVR_REG_SIZE, "HME Tranceiver Regs");
2765 if (!hp->tcvregs) {
050bbb19 2766 printk(KERN_ERR "happymeal: Cannot map TCVR registers.\n");
1da177e4
LT		 2767 goto err_out_iounmap;
2768 }
2769
050bbb19 2770 hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff);
1da177e4
LT		 2771 if (hp->hm_revision == 0xff)
2772 hp->hm_revision = 0xa0;
2773
2774 /* Now enable the feature flags we can. */
2775 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
2776 hp->happy_flags = HFLAG_20_21;
2777 else if (hp->hm_revision != 0xa0)
2778 hp->happy_flags = HFLAG_NOT_A0;
2779
2780 if (qp != NULL)
2781 hp->happy_flags |= HFLAG_QUATTRO;
2782
2783 /* Get the supported DVMA burst sizes from our Happy SBUS. */
050bbb19
DM		 2784 hp->happy_bursts = of_getintprop_default(sdev->bus->ofdev.node,
2785 "burst-sizes", 0x00);
1da177e4
LT		 2786
2787 hp->happy_block = sbus_alloc_consistent(hp->happy_dev,
2788 PAGE_SIZE,
2789 &hp->hblock_dvma);
2790 err = -ENOMEM;
2791 if (!hp->happy_block) {
2792 printk(KERN_ERR "happymeal: Cannot allocate descriptors.\n");
2793 goto err_out_iounmap;
2794 }
2795
2796 /* Force check of the link first time we are brought up. */
2797 hp->linkcheck = 0;
2798
2799 /* Force timer state to 'asleep' with count of zero. */
2800 hp->timer_state = asleep;
2801 hp->timer_ticks = 0;
2802
2803 init_timer(&hp->happy_timer);
2804
2805 hp->dev = dev;
2806 dev->open = &happy_meal_open;
2807 dev->stop = &happy_meal_close;
2808 dev->hard_start_xmit = &happy_meal_start_xmit;
2809 dev->get_stats = &happy_meal_get_stats;
2810 dev->set_multicast_list = &happy_meal_set_multicast;
2811 dev->tx_timeout = &happy_meal_tx_timeout;
2812 dev->watchdog_timeo = 5*HZ;
2813 dev->ethtool_ops = &hme_ethtool_ops;
2814
2815 /* Happy Meal can do it all... except VLAN. */
2816 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_VLAN_CHALLENGED;
2817
2818 dev->irq = sdev->irqs[0];
2819
2820#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
2821 /* Hook up PCI register/dma accessors. */
2822 hp->read_desc32 = sbus_hme_read_desc32;
2823 hp->write_txd = sbus_hme_write_txd;
2824 hp->write_rxd = sbus_hme_write_rxd;
2825 hp->dma_map = (u32 (*)(void *, void *, long, int))sbus_map_single;
2826 hp->dma_unmap = (void (*)(void *, u32, long, int))sbus_unmap_single;
2827 hp->dma_sync_for_cpu = (void (*)(void *, u32, long, int))
2828 sbus_dma_sync_single_for_cpu;
2829 hp->dma_sync_for_device = (void (*)(void *, u32, long, int))
2830 sbus_dma_sync_single_for_device;
2831 hp->read32 = sbus_hme_read32;
2832 hp->write32 = sbus_hme_write32;
2833#endif
2834
2835 /* Grrr, Happy Meal comes up by default not advertising
2836 * full duplex 100baseT capabilities, fix this.
2837 */
2838 spin_lock_irq(&hp->happy_lock);
2839 happy_meal_set_initial_advertisement(hp);
2840 spin_unlock_irq(&hp->happy_lock);
2841
2842 if (register_netdev(hp->dev)) {
2843 printk(KERN_ERR "happymeal: Cannot register net device, "
2844 "aborting.\n");
2845 goto err_out_free_consistent;
2846 }
2847
050bbb19
DM		 2848 dev_set_drvdata(&sdev->ofdev.dev, hp);
2849
1da177e4
LT		 2850 if (qfe_slot != -1)
2851 printk(KERN_INFO "%s: Quattro HME slot %d (SBUS) 10/100baseT Ethernet ",
2852 dev->name, qfe_slot);
2853 else
2854 printk(KERN_INFO "%s: HAPPY MEAL (SBUS) 10/100baseT Ethernet ",
2855 dev->name);
2856
2857 for (i = 0; i < 6; i++)
2858 printk("%2.2x%c",
2859 dev->dev_addr[i], i == 5 ? ' ' : ':');
2860 printk("\n");
2861
1da177e4
LT		 2862 return 0;
2863
2864err_out_free_consistent:
2865 sbus_free_consistent(hp->happy_dev,
2866 PAGE_SIZE,
2867 hp->happy_block,
2868 hp->hblock_dvma);
2869
2870err_out_iounmap:
2871 if (hp->gregs)
2872 sbus_iounmap(hp->gregs, GREG_REG_SIZE);
2873 if (hp->etxregs)
2874 sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
2875 if (hp->erxregs)
2876 sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
2877 if (hp->bigmacregs)
2878 sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
2879 if (hp->tcvregs)
2880 sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
2881
2882err_out_free_netdev:
2883 free_netdev(dev);
2884
2885err_out:
2886 return err;
2887}
2888#endif
2889
2890#ifdef CONFIG_PCI
9e326acf 2891#ifndef CONFIG_SPARC
1da177e4
LT		 2892static int is_quattro_p(struct pci_dev *pdev)
2893{
2894 struct pci_dev *busdev = pdev->bus->self;
2895 struct list_head *tmp;
2896 int n_hmes;
2897
2898 if (busdev == NULL ||
2899 busdev->vendor != PCI_VENDOR_ID_DEC ||
2900 busdev->device != PCI_DEVICE_ID_DEC_21153)
2901 return 0;
2902
2903 n_hmes = 0;
2904 tmp = pdev->bus->devices.next;
2905 while (tmp != &pdev->bus->devices) {
2906 struct pci_dev *this_pdev = pci_dev_b(tmp);
2907
2908 if (this_pdev->vendor == PCI_VENDOR_ID_SUN &&
2909 this_pdev->device == PCI_DEVICE_ID_SUN_HAPPYMEAL)
2910 n_hmes++;
2911
2912 tmp = tmp->next;
2913 }
2914
2915 if (n_hmes != 4)
2916 return 0;
2917
2918 return 1;
2919}
2920
2921/* Fetch MAC address from vital product data of PCI ROM. */
ce1289ad 2922static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, int index, unsigned char *dev_addr)
1da177e4
LT		 2923{
2924 int this_offset;
2925
2926 for (this_offset = 0x20; this_offset < len; this_offset++) {
2927 void __iomem *p = rom_base + this_offset;
2928
2929 if (readb(p + 0) != 0x90 ||
2930 readb(p + 1) != 0x00 ||
2931 readb(p + 2) != 0x09 ||
2932 readb(p + 3) != 0x4e ||
2933 readb(p + 4) != 0x41 ||
2934 readb(p + 5) != 0x06)
2935 continue;
2936
2937 this_offset += 6;
2938 p += 6;
2939
2940 if (index == 0) {
2941 int i;
2942
2943 for (i = 0; i < 6; i++)
2944 dev_addr[i] = readb(p + i);
ce1289ad 2945 return 1;
1da177e4
LT		 2946 }
2947 index--;
2948 }
ce1289ad 2949 return 0;
1da177e4
LT		 2950}
2951
2952static void get_hme_mac_nonsparc(struct pci_dev *pdev, unsigned char *dev_addr)
2953{
ce1289ad
WT		 2954 size_t size;
2955 void __iomem *p = pci_map_rom(pdev, &size);
1da177e4 2956
ce1289ad
WT		 2957 if (p) {
2958 int index = 0;
2959 int found;
1da177e4 2960
ce1289ad
WT		 2961 if (is_quattro_p(pdev))
2962 index = PCI_SLOT(pdev->devfn);
1da177e4 2963
ce1289ad
WT		 2964 found = readb(p) == 0x55 &&
2965 readb(p + 1) == 0xaa &&
2966 find_eth_addr_in_vpd(p, (64 * 1024), index, dev_addr);
2967 pci_unmap_rom(pdev, p);
2968 if (found)
2969 return;
2970 }
1da177e4 2971
1da177e4
LT		 2972 /* Sun MAC prefix then 3 random bytes. */
2973 dev_addr[0] = 0x08;
2974 dev_addr[1] = 0x00;
2975 dev_addr[2] = 0x20;
2976 get_random_bytes(&dev_addr[3], 3);
2977 return;
2978}
9e326acf 2979#endif /* !(CONFIG_SPARC) */
1da177e4 2980
050bbb19
DM		 2981static int __devinit happy_meal_pci_probe(struct pci_dev *pdev,
2982 const struct pci_device_id *ent)
1da177e4
LT		 2983{
2984 struct quattro *qp = NULL;
9e326acf 2985#ifdef CONFIG_SPARC
1da177e4 2986 struct pcidev_cookie *pcp;
1da177e4
LT		 2987#endif
2988 struct happy_meal *hp;
2989 struct net_device *dev;
2990 void __iomem *hpreg_base;
2991 unsigned long hpreg_res;
2992 int i, qfe_slot = -1;
2993 char prom_name[64];
2994 int err;
2995
2996 /* Now make sure pci_dev cookie is there. */
9e326acf 2997#ifdef CONFIG_SPARC
1da177e4 2998 pcp = pdev->sysdata;
de8d28b1 2999 if (pcp == NULL) {
1da177e4
LT		 3000 printk(KERN_ERR "happymeal(PCI): Some PCI device info missing\n");
3001 return -ENODEV;
3002 }
6aa20a22 3003
de8d28b1 3004 strcpy(prom_name, pcp->prom_node->name);
1da177e4
LT		 3005#else
3006 if (is_quattro_p(pdev))
3007 strcpy(prom_name, "SUNW,qfe");
3008 else
3009 strcpy(prom_name, "SUNW,hme");
3010#endif
3011
3012 err = -ENODEV;
ef9467f8
JS		 3013
3014 if (pci_enable_device(pdev))
3015 goto err_out;
3016 pci_set_master(pdev);
3017
1da177e4
LT		 3018 if (!strcmp(prom_name, "SUNW,qfe") || !strcmp(prom_name, "qfe")) {
3019 qp = quattro_pci_find(pdev);
3020 if (qp == NULL)
3021 goto err_out;
3022 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
3023 if (qp->happy_meals[qfe_slot] == NULL)
3024 break;
3025 if (qfe_slot == 4)
3026 goto err_out;
3027 }
3028
3029 dev = alloc_etherdev(sizeof(struct happy_meal));
3030 err = -ENOMEM;
3031 if (!dev)
3032 goto err_out;
3033 SET_MODULE_OWNER(dev);
3034 SET_NETDEV_DEV(dev, &pdev->dev);
3035
3036 if (hme_version_printed++ == 0)
3037 printk(KERN_INFO "%s", version);
3038
3039 dev->base_addr = (long) pdev;
3040
3041 hp = (struct happy_meal *)dev->priv;
3042 memset(hp, 0, sizeof(*hp));
3043
3044 hp->happy_dev = pdev;
3045
3046 spin_lock_init(&hp->happy_lock);
3047
3048 if (qp != NULL) {
3049 hp->qfe_parent = qp;
3050 hp->qfe_ent = qfe_slot;
3051 qp->happy_meals[qfe_slot] = dev;
6aa20a22 3052 }
1da177e4
LT		 3053
3054 hpreg_res = pci_resource_start(pdev, 0);
3055 err = -ENODEV;
3056 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
3057 printk(KERN_ERR "happymeal(PCI): Cannot find proper PCI device base address.\n");
3058 goto err_out_clear_quattro;
3059 }
3060 if (pci_request_regions(pdev, DRV_NAME)) {
3061 printk(KERN_ERR "happymeal(PCI): Cannot obtain PCI resources, "
3062 "aborting.\n");
3063 goto err_out_clear_quattro;
3064 }
3065
3066 if ((hpreg_base = ioremap(hpreg_res, 0x8000)) == 0) {
3067 printk(KERN_ERR "happymeal(PCI): Unable to remap card memory.\n");
3068 goto err_out_free_res;
3069 }
3070
3071 for (i = 0; i < 6; i++) {
3072 if (macaddr[i] != 0)
3073 break;
3074 }
3075 if (i < 6) { /* a mac address was given */
3076 for (i = 0; i < 6; i++)
3077 dev->dev_addr[i] = macaddr[i];
3078 macaddr[5]++;
3079 } else {
9e326acf 3080#ifdef CONFIG_SPARC
de8d28b1
DM		 3081 unsigned char *addr;
3082 int len;
3083
1da177e4 3084 if (qfe_slot != -1 &&
de8d28b1
DM		 3085 (addr = of_get_property(pcp->prom_node,
3086 "local-mac-address", &len)) != NULL
3087 && len == 6) {
3088 memcpy(dev->dev_addr, addr, 6);
1da177e4
LT		 3089 } else {
3090 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
3091 }
3092#else
3093 get_hme_mac_nonsparc(pdev, &dev->dev_addr[0]);
3094#endif
3095 }
6aa20a22 3096
1da177e4
LT		 3097 /* Layout registers. */
3098 hp->gregs = (hpreg_base + 0x0000UL);
3099 hp->etxregs = (hpreg_base + 0x2000UL);
3100 hp->erxregs = (hpreg_base + 0x4000UL);
3101 hp->bigmacregs = (hpreg_base + 0x6000UL);
3102 hp->tcvregs = (hpreg_base + 0x7000UL);
3103
9e326acf 3104#ifdef CONFIG_SPARC
de8d28b1 3105 hp->hm_revision = of_getintprop_default(pcp->prom_node, "hm-rev", 0xff);
1da177e4
LT		 3106 if (hp->hm_revision == 0xff) {
3107 unsigned char prev;
3108
3109 pci_read_config_byte(pdev, PCI_REVISION_ID, &prev);
3110 hp->hm_revision = 0xc0 | (prev & 0x0f);
3111 }
3112#else
3113 /* works with this on non-sparc hosts */
3114 hp->hm_revision = 0x20;
3115#endif
3116
3117 /* Now enable the feature flags we can. */
3118 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
3119 hp->happy_flags = HFLAG_20_21;
3120 else if (hp->hm_revision != 0xa0 && hp->hm_revision != 0xc0)
3121 hp->happy_flags = HFLAG_NOT_A0;
3122
3123 if (qp != NULL)
3124 hp->happy_flags |= HFLAG_QUATTRO;
3125
3126 /* And of course, indicate this is PCI. */
3127 hp->happy_flags |= HFLAG_PCI;
3128
9e326acf 3129#ifdef CONFIG_SPARC
1da177e4
LT		 3130 /* Assume PCI happy meals can handle all burst sizes. */
3131 hp->happy_bursts = DMA_BURSTBITS;
3132#endif
3133
3134 hp->happy_block = (struct hmeal_init_block *)
3135 pci_alloc_consistent(pdev, PAGE_SIZE, &hp->hblock_dvma);
3136
3137 err = -ENODEV;
3138 if (!hp->happy_block) {
3139 printk(KERN_ERR "happymeal(PCI): Cannot get hme init block.\n");
3140 goto err_out_iounmap;
3141 }
3142
3143 hp->linkcheck = 0;
3144 hp->timer_state = asleep;
3145 hp->timer_ticks = 0;
3146
3147 init_timer(&hp->happy_timer);
3148
3149 hp->dev = dev;
3150 dev->open = &happy_meal_open;
3151 dev->stop = &happy_meal_close;
3152 dev->hard_start_xmit = &happy_meal_start_xmit;
3153 dev->get_stats = &happy_meal_get_stats;
3154 dev->set_multicast_list = &happy_meal_set_multicast;
3155 dev->tx_timeout = &happy_meal_tx_timeout;
3156 dev->watchdog_timeo = 5*HZ;
3157 dev->ethtool_ops = &hme_ethtool_ops;
3158 dev->irq = pdev->irq;
3159 dev->dma = 0;
3160
3161 /* Happy Meal can do it all... */
3162 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
3163
3164#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
3165 /* Hook up PCI register/dma accessors. */
3166 hp->read_desc32 = pci_hme_read_desc32;
3167 hp->write_txd = pci_hme_write_txd;
3168 hp->write_rxd = pci_hme_write_rxd;
3169 hp->dma_map = (u32 (*)(void *, void *, long, int))pci_map_single;
3170 hp->dma_unmap = (void (*)(void *, u32, long, int))pci_unmap_single;
3171 hp->dma_sync_for_cpu = (void (*)(void *, u32, long, int))
3172 pci_dma_sync_single_for_cpu;
3173 hp->dma_sync_for_device = (void (*)(void *, u32, long, int))
3174 pci_dma_sync_single_for_device;
3175 hp->read32 = pci_hme_read32;
3176 hp->write32 = pci_hme_write32;
3177#endif
3178
3179 /* Grrr, Happy Meal comes up by default not advertising
3180 * full duplex 100baseT capabilities, fix this.
3181 */
3182 spin_lock_irq(&hp->happy_lock);
3183 happy_meal_set_initial_advertisement(hp);
3184 spin_unlock_irq(&hp->happy_lock);
3185
3186 if (register_netdev(hp->dev)) {
3187 printk(KERN_ERR "happymeal(PCI): Cannot register net device, "
3188 "aborting.\n");
3189 goto err_out_iounmap;
3190 }
3191
050bbb19
DM		 3192 dev_set_drvdata(&pdev->dev, hp);
3193
1da177e4
LT		 3194 if (!qfe_slot) {
3195 struct pci_dev *qpdev = qp->quattro_dev;
3196
3197 prom_name[0] = 0;
3198 if (!strncmp(dev->name, "eth", 3)) {
3199 int i = simple_strtoul(dev->name + 3, NULL, 10);
3200 sprintf(prom_name, "-%d", i + 3);
3201 }
3202 printk(KERN_INFO "%s%s: Quattro HME (PCI/CheerIO) 10/100baseT Ethernet ", dev->name, prom_name);
3203 if (qpdev->vendor == PCI_VENDOR_ID_DEC &&
3204 qpdev->device == PCI_DEVICE_ID_DEC_21153)
3205 printk("DEC 21153 PCI Bridge\n");
3206 else
6aa20a22 3207 printk("unknown bridge %04x.%04x\n",
1da177e4
LT		 3208 qpdev->vendor, qpdev->device);
3209 }
3210
3211 if (qfe_slot != -1)
3212 printk(KERN_INFO "%s: Quattro HME slot %d (PCI/CheerIO) 10/100baseT Ethernet ",
3213 dev->name, qfe_slot);
3214 else
3215 printk(KERN_INFO "%s: HAPPY MEAL (PCI/CheerIO) 10/100BaseT Ethernet ",
3216 dev->name);
3217
3218 for (i = 0; i < 6; i++)
3219 printk("%2.2x%c", dev->dev_addr[i], i == 5 ? ' ' : ':');
3220
3221 printk("\n");
3222
1da177e4
LT		 3223 return 0;
3224
3225err_out_iounmap:
3226 iounmap(hp->gregs);
3227
3228err_out_free_res:
3229 pci_release_regions(pdev);
3230
3231err_out_clear_quattro:
3232 if (qp != NULL)
3233 qp->happy_meals[qfe_slot] = NULL;
3234
3235 free_netdev(dev);
3236
3237err_out:
3238 return err;
3239}
1da177e4 3240
050bbb19 3241static void __devexit happy_meal_pci_remove(struct pci_dev *pdev)
1da177e4 3242{
050bbb19
DM		 3243 struct happy_meal *hp = dev_get_drvdata(&pdev->dev);
3244 struct net_device *net_dev = hp->dev;
1da177e4 3245
050bbb19
DM		 3246 unregister_netdev(net_dev);
3247
3248 pci_free_consistent(hp->happy_dev,
3249 PAGE_SIZE,
3250 hp->happy_block,
3251 hp->hblock_dvma);
3252 iounmap(hp->gregs);
3253 pci_release_regions(hp->happy_dev);
3254
3255 free_netdev(net_dev);
3256
3257 dev_set_drvdata(&pdev->dev, NULL);
1da177e4 3258}
1da177e4 3259
050bbb19 3260static struct pci_device_id happymeal_pci_ids[] = {
a0ee7c70 3261 { PCI_DEVICE(PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_HAPPYMEAL) },
050bbb19
DM		 3262 { } /* Terminating entry */
3263};
3264
3265MODULE_DEVICE_TABLE(pci, happymeal_pci_ids);
3266
3267static struct pci_driver hme_pci_driver = {
3268 .name = "hme",
3269 .id_table = happymeal_pci_ids,
3270 .probe = happy_meal_pci_probe,
3271 .remove = __devexit_p(happy_meal_pci_remove),
3272};
3273
3274static int __init happy_meal_pci_init(void)
1da177e4 3275{
a0ee7c70 3276 return pci_register_driver(&hme_pci_driver);
050bbb19 3277}
1da177e4 3278
050bbb19
DM		 3279static void happy_meal_pci_exit(void)
3280{
3281 pci_unregister_driver(&hme_pci_driver);
3282
3283 while (qfe_pci_list) {
3284 struct quattro *qfe = qfe_pci_list;
3285 struct quattro *next = qfe->next;
3286
3287 kfree(qfe);
3288
3289 qfe_pci_list = next;
1da177e4 3290 }
1da177e4 3291}
050bbb19 3292
1da177e4
LT		 3293#endif
3294
050bbb19
DM		 3295#ifdef CONFIG_SBUS
3296static int __devinit hme_sbus_probe(struct of_device *dev, const struct of_device_id *match)
1da177e4 3297{
050bbb19
DM		 3298 struct sbus_dev *sdev = to_sbus_device(&dev->dev);
3299 struct device_node *dp = dev->node;
3300 char *model = of_get_property(dp, "model", NULL);
3301 int is_qfe = (match->data != NULL);
1da177e4 3302
050bbb19
DM		 3303 if (!is_qfe && model && !strcmp(model, "SUNW,sbus-qfe"))
3304 is_qfe = 1;
1da177e4 3305
050bbb19
DM		 3306 return happy_meal_sbus_probe_one(sdev, is_qfe);
3307}
3308
3309static int __devexit hme_sbus_remove(struct of_device *dev)
3310{
3311 struct happy_meal *hp = dev_get_drvdata(&dev->dev);
3312 struct net_device *net_dev = hp->dev;
3313
c3b99f0d 3314 unregister_netdev(net_dev);
050bbb19
DM		 3315
3316 /* XXX qfe parent interrupt... */
3317
3318 sbus_iounmap(hp->gregs, GREG_REG_SIZE);
3319 sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
3320 sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
3321 sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
3322 sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
3323 sbus_free_consistent(hp->happy_dev,
3324 PAGE_SIZE,
3325 hp->happy_block,
3326 hp->hblock_dvma);
3327
3328 free_netdev(net_dev);
3329
3330 dev_set_drvdata(&dev->dev, NULL);
1da177e4 3331
1da177e4
LT		 3332 return 0;
3333}
3334
050bbb19
DM		 3335static struct of_device_id hme_sbus_match[] = {
3336 {
3337 .name = "SUNW,hme",
3338 },
3339 {
3340 .name = "SUNW,qfe",
3341 .data = (void *) 1,
3342 },
3343 {
3344 .name = "qfe",
3345 .data = (void *) 1,
3346 },
3347 {},
3348};
1da177e4 3349
050bbb19 3350MODULE_DEVICE_TABLE(of, hme_sbus_match);
1da177e4 3351
050bbb19
DM		 3352static struct of_platform_driver hme_sbus_driver = {
3353 .name = "hme",
3354 .match_table = hme_sbus_match,
3355 .probe = hme_sbus_probe,
3356 .remove = __devexit_p(hme_sbus_remove),
3357};
1da177e4 3358
050bbb19
DM		 3359static int __init happy_meal_sbus_init(void)
3360{
3361 int err;
1da177e4 3362
050bbb19
DM		 3363 err = of_register_driver(&hme_sbus_driver, &sbus_bus_type);
3364 if (!err)
3365 quattro_sbus_register_irqs();
1da177e4 3366
050bbb19
DM		 3367 return err;
3368}
1da177e4 3369
050bbb19
DM		 3370static void happy_meal_sbus_exit(void)
3371{
3372 of_unregister_driver(&hme_sbus_driver);
3373 quattro_sbus_free_irqs();
1da177e4 3374
1da177e4
LT		 3375 while (qfe_sbus_list) {
3376 struct quattro *qfe = qfe_sbus_list;
3377 struct quattro *next = qfe->next;
3378
3379 kfree(qfe);
3380
3381 qfe_sbus_list = next;
3382 }
050bbb19 3383}
1da177e4 3384#endif
1da177e4 3385
050bbb19
DM		 3386static int __init happy_meal_probe(void)
3387{
3388 int err = 0;
1da177e4 3389
050bbb19
DM		 3390#ifdef CONFIG_SBUS
3391 err = happy_meal_sbus_init();
3392#endif
3393#ifdef CONFIG_PCI
3394 if (!err) {
3395 err = happy_meal_pci_init();
3396#ifdef CONFIG_SBUS
3397 if (err)
3398 happy_meal_sbus_exit();
3399#endif
1da177e4
LT		 3400 }
3401#endif
050bbb19
DM		 3402
3403 return err;
3404}
3405
3406
3407static void __exit happy_meal_exit(void)
3408{
3409#ifdef CONFIG_SBUS
3410 happy_meal_sbus_exit();
3411#endif
3412#ifdef CONFIG_PCI
3413 happy_meal_pci_exit();
3414#endif
1da177e4
LT		 3415}
3416
3417module_init(happy_meal_probe);
050bbb19 3418module_exit(happy_meal_exit);
Linux kernel - Deliverables
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