Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * tg3.c: Broadcom Tigon3 ethernet driver. | |
3 | * | |
4 | * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) | |
5 | * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com) | |
6 | * Copyright (C) 2004 Sun Microsystems Inc. | |
ba5b0bfa | 7 | * Copyright (C) 2005-2010 Broadcom Corporation. |
1da177e4 LT |
8 | * |
9 | * Firmware is: | |
49cabf49 MC |
10 | * Derived from proprietary unpublished source code, |
11 | * Copyright (C) 2000-2003 Broadcom Corporation. | |
12 | * | |
13 | * Permission is hereby granted for the distribution of this firmware | |
14 | * data in hexadecimal or equivalent format, provided this copyright | |
15 | * notice is accompanying it. | |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | |
19 | #include <linux/module.h> | |
20 | #include <linux/moduleparam.h> | |
6867c843 | 21 | #include <linux/stringify.h> |
1da177e4 LT |
22 | #include <linux/kernel.h> |
23 | #include <linux/types.h> | |
24 | #include <linux/compiler.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/delay.h> | |
14c85021 | 27 | #include <linux/in.h> |
1da177e4 LT |
28 | #include <linux/init.h> |
29 | #include <linux/ioport.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/etherdevice.h> | |
33 | #include <linux/skbuff.h> | |
34 | #include <linux/ethtool.h> | |
3110f5f5 | 35 | #include <linux/mdio.h> |
1da177e4 | 36 | #include <linux/mii.h> |
158d7abd | 37 | #include <linux/phy.h> |
a9daf367 | 38 | #include <linux/brcmphy.h> |
1da177e4 LT |
39 | #include <linux/if_vlan.h> |
40 | #include <linux/ip.h> | |
41 | #include <linux/tcp.h> | |
42 | #include <linux/workqueue.h> | |
61487480 | 43 | #include <linux/prefetch.h> |
f9a5f7d3 | 44 | #include <linux/dma-mapping.h> |
077f849d | 45 | #include <linux/firmware.h> |
1da177e4 LT |
46 | |
47 | #include <net/checksum.h> | |
c9bdd4b5 | 48 | #include <net/ip.h> |
1da177e4 LT |
49 | |
50 | #include <asm/system.h> | |
51 | #include <asm/io.h> | |
52 | #include <asm/byteorder.h> | |
53 | #include <asm/uaccess.h> | |
54 | ||
49b6e95f | 55 | #ifdef CONFIG_SPARC |
1da177e4 | 56 | #include <asm/idprom.h> |
49b6e95f | 57 | #include <asm/prom.h> |
1da177e4 LT |
58 | #endif |
59 | ||
63532394 MC |
60 | #define BAR_0 0 |
61 | #define BAR_2 2 | |
62 | ||
1da177e4 LT |
63 | #include "tg3.h" |
64 | ||
65 | #define DRV_MODULE_NAME "tg3" | |
6867c843 | 66 | #define TG3_MAJ_NUM 3 |
5ee49376 | 67 | #define TG3_MIN_NUM 116 |
6867c843 MC |
68 | #define DRV_MODULE_VERSION \ |
69 | __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM) | |
5ee49376 | 70 | #define DRV_MODULE_RELDATE "December 3, 2010" |
1da177e4 LT |
71 | |
72 | #define TG3_DEF_MAC_MODE 0 | |
73 | #define TG3_DEF_RX_MODE 0 | |
74 | #define TG3_DEF_TX_MODE 0 | |
75 | #define TG3_DEF_MSG_ENABLE \ | |
76 | (NETIF_MSG_DRV | \ | |
77 | NETIF_MSG_PROBE | \ | |
78 | NETIF_MSG_LINK | \ | |
79 | NETIF_MSG_TIMER | \ | |
80 | NETIF_MSG_IFDOWN | \ | |
81 | NETIF_MSG_IFUP | \ | |
82 | NETIF_MSG_RX_ERR | \ | |
83 | NETIF_MSG_TX_ERR) | |
84 | ||
85 | /* length of time before we decide the hardware is borked, | |
86 | * and dev->tx_timeout() should be called to fix the problem | |
87 | */ | |
88 | #define TG3_TX_TIMEOUT (5 * HZ) | |
89 | ||
90 | /* hardware minimum and maximum for a single frame's data payload */ | |
91 | #define TG3_MIN_MTU 60 | |
92 | #define TG3_MAX_MTU(tp) \ | |
8f666b07 | 93 | ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500) |
1da177e4 LT |
94 | |
95 | /* These numbers seem to be hard coded in the NIC firmware somehow. | |
96 | * You can't change the ring sizes, but you can change where you place | |
97 | * them in the NIC onboard memory. | |
98 | */ | |
7cb32cf2 MC |
99 | #define TG3_RX_STD_RING_SIZE(tp) \ |
100 | ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \ | |
101 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \ | |
102 | RX_STD_MAX_SIZE_5717 : 512) | |
1da177e4 | 103 | #define TG3_DEF_RX_RING_PENDING 200 |
7cb32cf2 MC |
104 | #define TG3_RX_JMB_RING_SIZE(tp) \ |
105 | ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \ | |
106 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \ | |
107 | 1024 : 256) | |
1da177e4 | 108 | #define TG3_DEF_RX_JUMBO_RING_PENDING 100 |
c6cdf436 | 109 | #define TG3_RSS_INDIR_TBL_SIZE 128 |
1da177e4 LT |
110 | |
111 | /* Do not place this n-ring entries value into the tp struct itself, | |
112 | * we really want to expose these constants to GCC so that modulo et | |
113 | * al. operations are done with shifts and masks instead of with | |
114 | * hw multiply/modulo instructions. Another solution would be to | |
115 | * replace things like '% foo' with '& (foo - 1)'. | |
116 | */ | |
1da177e4 LT |
117 | |
118 | #define TG3_TX_RING_SIZE 512 | |
119 | #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1) | |
120 | ||
2c49a44d MC |
121 | #define TG3_RX_STD_RING_BYTES(tp) \ |
122 | (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp)) | |
123 | #define TG3_RX_JMB_RING_BYTES(tp) \ | |
124 | (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp)) | |
125 | #define TG3_RX_RCB_RING_BYTES(tp) \ | |
7cb32cf2 | 126 | (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1)) |
1da177e4 LT |
127 | #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \ |
128 | TG3_TX_RING_SIZE) | |
1da177e4 LT |
129 | #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1)) |
130 | ||
287be12e MC |
131 | #define TG3_DMA_BYTE_ENAB 64 |
132 | ||
133 | #define TG3_RX_STD_DMA_SZ 1536 | |
134 | #define TG3_RX_JMB_DMA_SZ 9046 | |
135 | ||
136 | #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB) | |
137 | ||
138 | #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ) | |
139 | #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ) | |
1da177e4 | 140 | |
2c49a44d MC |
141 | #define TG3_RX_STD_BUFF_RING_SIZE(tp) \ |
142 | (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp)) | |
2b2cdb65 | 143 | |
2c49a44d MC |
144 | #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \ |
145 | (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp)) | |
2b2cdb65 | 146 | |
d2757fc4 MC |
147 | /* Due to a hardware bug, the 5701 can only DMA to memory addresses |
148 | * that are at least dword aligned when used in PCIX mode. The driver | |
149 | * works around this bug by double copying the packet. This workaround | |
150 | * is built into the normal double copy length check for efficiency. | |
151 | * | |
152 | * However, the double copy is only necessary on those architectures | |
153 | * where unaligned memory accesses are inefficient. For those architectures | |
154 | * where unaligned memory accesses incur little penalty, we can reintegrate | |
155 | * the 5701 in the normal rx path. Doing so saves a device structure | |
156 | * dereference by hardcoding the double copy threshold in place. | |
157 | */ | |
158 | #define TG3_RX_COPY_THRESHOLD 256 | |
159 | #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) | |
160 | #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD | |
161 | #else | |
162 | #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh) | |
163 | #endif | |
164 | ||
1da177e4 | 165 | /* minimum number of free TX descriptors required to wake up TX process */ |
f3f3f27e | 166 | #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4) |
1da177e4 | 167 | |
ad829268 MC |
168 | #define TG3_RAW_IP_ALIGN 2 |
169 | ||
1da177e4 LT |
170 | /* number of ETHTOOL_GSTATS u64's */ |
171 | #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64)) | |
172 | ||
4cafd3f5 MC |
173 | #define TG3_NUM_TEST 6 |
174 | ||
c6cdf436 MC |
175 | #define TG3_FW_UPDATE_TIMEOUT_SEC 5 |
176 | ||
077f849d JSR |
177 | #define FIRMWARE_TG3 "tigon/tg3.bin" |
178 | #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" | |
179 | #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" | |
180 | ||
1da177e4 | 181 | static char version[] __devinitdata = |
05dbe005 | 182 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")"; |
1da177e4 LT |
183 | |
184 | MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)"); | |
185 | MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver"); | |
186 | MODULE_LICENSE("GPL"); | |
187 | MODULE_VERSION(DRV_MODULE_VERSION); | |
077f849d JSR |
188 | MODULE_FIRMWARE(FIRMWARE_TG3); |
189 | MODULE_FIRMWARE(FIRMWARE_TG3TSO); | |
190 | MODULE_FIRMWARE(FIRMWARE_TG3TSO5); | |
191 | ||
1da177e4 LT |
192 | static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */ |
193 | module_param(tg3_debug, int, 0); | |
194 | MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value"); | |
195 | ||
a3aa1884 | 196 | static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = { |
13185217 HK |
197 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)}, |
198 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)}, | |
199 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)}, | |
200 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)}, | |
201 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)}, | |
202 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)}, | |
203 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)}, | |
204 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)}, | |
205 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)}, | |
206 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)}, | |
207 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)}, | |
208 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)}, | |
209 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)}, | |
210 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)}, | |
211 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)}, | |
212 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)}, | |
213 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)}, | |
214 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)}, | |
215 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)}, | |
216 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)}, | |
217 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)}, | |
218 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)}, | |
13185217 | 219 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)}, |
126a3368 | 220 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)}, |
13185217 | 221 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)}, |
13185217 HK |
222 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)}, |
223 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)}, | |
224 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)}, | |
225 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)}, | |
226 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)}, | |
227 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)}, | |
228 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)}, | |
229 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)}, | |
230 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)}, | |
231 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)}, | |
232 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)}, | |
126a3368 | 233 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)}, |
13185217 HK |
234 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)}, |
235 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)}, | |
236 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)}, | |
676917d4 | 237 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)}, |
13185217 HK |
238 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)}, |
239 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)}, | |
240 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)}, | |
241 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)}, | |
242 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)}, | |
243 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)}, | |
244 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)}, | |
b5d3772c MC |
245 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)}, |
246 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)}, | |
d30cdd28 MC |
247 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)}, |
248 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)}, | |
6c7af27c | 249 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)}, |
9936bcf6 MC |
250 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)}, |
251 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)}, | |
c88e668b MC |
252 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)}, |
253 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)}, | |
2befdcea MC |
254 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)}, |
255 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)}, | |
321d32a0 MC |
256 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)}, |
257 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)}, | |
258 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)}, | |
5e7ccf20 | 259 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)}, |
5001e2f6 MC |
260 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)}, |
261 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)}, | |
b0f75221 MC |
262 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)}, |
263 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)}, | |
264 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)}, | |
265 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)}, | |
266 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)}, | |
267 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)}, | |
302b500b | 268 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)}, |
13185217 HK |
269 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, |
270 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, | |
271 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)}, | |
272 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)}, | |
273 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)}, | |
274 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)}, | |
275 | {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)}, | |
276 | {} | |
1da177e4 LT |
277 | }; |
278 | ||
279 | MODULE_DEVICE_TABLE(pci, tg3_pci_tbl); | |
280 | ||
50da859d | 281 | static const struct { |
1da177e4 LT |
282 | const char string[ETH_GSTRING_LEN]; |
283 | } ethtool_stats_keys[TG3_NUM_STATS] = { | |
284 | { "rx_octets" }, | |
285 | { "rx_fragments" }, | |
286 | { "rx_ucast_packets" }, | |
287 | { "rx_mcast_packets" }, | |
288 | { "rx_bcast_packets" }, | |
289 | { "rx_fcs_errors" }, | |
290 | { "rx_align_errors" }, | |
291 | { "rx_xon_pause_rcvd" }, | |
292 | { "rx_xoff_pause_rcvd" }, | |
293 | { "rx_mac_ctrl_rcvd" }, | |
294 | { "rx_xoff_entered" }, | |
295 | { "rx_frame_too_long_errors" }, | |
296 | { "rx_jabbers" }, | |
297 | { "rx_undersize_packets" }, | |
298 | { "rx_in_length_errors" }, | |
299 | { "rx_out_length_errors" }, | |
300 | { "rx_64_or_less_octet_packets" }, | |
301 | { "rx_65_to_127_octet_packets" }, | |
302 | { "rx_128_to_255_octet_packets" }, | |
303 | { "rx_256_to_511_octet_packets" }, | |
304 | { "rx_512_to_1023_octet_packets" }, | |
305 | { "rx_1024_to_1522_octet_packets" }, | |
306 | { "rx_1523_to_2047_octet_packets" }, | |
307 | { "rx_2048_to_4095_octet_packets" }, | |
308 | { "rx_4096_to_8191_octet_packets" }, | |
309 | { "rx_8192_to_9022_octet_packets" }, | |
310 | ||
311 | { "tx_octets" }, | |
312 | { "tx_collisions" }, | |
313 | ||
314 | { "tx_xon_sent" }, | |
315 | { "tx_xoff_sent" }, | |
316 | { "tx_flow_control" }, | |
317 | { "tx_mac_errors" }, | |
318 | { "tx_single_collisions" }, | |
319 | { "tx_mult_collisions" }, | |
320 | { "tx_deferred" }, | |
321 | { "tx_excessive_collisions" }, | |
322 | { "tx_late_collisions" }, | |
323 | { "tx_collide_2times" }, | |
324 | { "tx_collide_3times" }, | |
325 | { "tx_collide_4times" }, | |
326 | { "tx_collide_5times" }, | |
327 | { "tx_collide_6times" }, | |
328 | { "tx_collide_7times" }, | |
329 | { "tx_collide_8times" }, | |
330 | { "tx_collide_9times" }, | |
331 | { "tx_collide_10times" }, | |
332 | { "tx_collide_11times" }, | |
333 | { "tx_collide_12times" }, | |
334 | { "tx_collide_13times" }, | |
335 | { "tx_collide_14times" }, | |
336 | { "tx_collide_15times" }, | |
337 | { "tx_ucast_packets" }, | |
338 | { "tx_mcast_packets" }, | |
339 | { "tx_bcast_packets" }, | |
340 | { "tx_carrier_sense_errors" }, | |
341 | { "tx_discards" }, | |
342 | { "tx_errors" }, | |
343 | ||
344 | { "dma_writeq_full" }, | |
345 | { "dma_write_prioq_full" }, | |
346 | { "rxbds_empty" }, | |
347 | { "rx_discards" }, | |
348 | { "rx_errors" }, | |
349 | { "rx_threshold_hit" }, | |
350 | ||
351 | { "dma_readq_full" }, | |
352 | { "dma_read_prioq_full" }, | |
353 | { "tx_comp_queue_full" }, | |
354 | ||
355 | { "ring_set_send_prod_index" }, | |
356 | { "ring_status_update" }, | |
357 | { "nic_irqs" }, | |
358 | { "nic_avoided_irqs" }, | |
359 | { "nic_tx_threshold_hit" } | |
360 | }; | |
361 | ||
50da859d | 362 | static const struct { |
4cafd3f5 MC |
363 | const char string[ETH_GSTRING_LEN]; |
364 | } ethtool_test_keys[TG3_NUM_TEST] = { | |
365 | { "nvram test (online) " }, | |
366 | { "link test (online) " }, | |
367 | { "register test (offline)" }, | |
368 | { "memory test (offline)" }, | |
369 | { "loopback test (offline)" }, | |
370 | { "interrupt test (offline)" }, | |
371 | }; | |
372 | ||
b401e9e2 MC |
373 | static void tg3_write32(struct tg3 *tp, u32 off, u32 val) |
374 | { | |
375 | writel(val, tp->regs + off); | |
376 | } | |
377 | ||
378 | static u32 tg3_read32(struct tg3 *tp, u32 off) | |
379 | { | |
de6f31eb | 380 | return readl(tp->regs + off); |
b401e9e2 MC |
381 | } |
382 | ||
0d3031d9 MC |
383 | static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) |
384 | { | |
385 | writel(val, tp->aperegs + off); | |
386 | } | |
387 | ||
388 | static u32 tg3_ape_read32(struct tg3 *tp, u32 off) | |
389 | { | |
de6f31eb | 390 | return readl(tp->aperegs + off); |
0d3031d9 MC |
391 | } |
392 | ||
1da177e4 LT |
393 | static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) |
394 | { | |
6892914f MC |
395 | unsigned long flags; |
396 | ||
397 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
1ee582d8 MC |
398 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); |
399 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
6892914f | 400 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1ee582d8 MC |
401 | } |
402 | ||
403 | static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) | |
404 | { | |
405 | writel(val, tp->regs + off); | |
406 | readl(tp->regs + off); | |
1da177e4 LT |
407 | } |
408 | ||
6892914f | 409 | static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) |
1da177e4 | 410 | { |
6892914f MC |
411 | unsigned long flags; |
412 | u32 val; | |
413 | ||
414 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
415 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); | |
416 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
417 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
418 | return val; | |
419 | } | |
420 | ||
421 | static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) | |
422 | { | |
423 | unsigned long flags; | |
424 | ||
425 | if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) { | |
426 | pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + | |
427 | TG3_64BIT_REG_LOW, val); | |
428 | return; | |
429 | } | |
66711e66 | 430 | if (off == TG3_RX_STD_PROD_IDX_REG) { |
6892914f MC |
431 | pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + |
432 | TG3_64BIT_REG_LOW, val); | |
433 | return; | |
1da177e4 | 434 | } |
6892914f MC |
435 | |
436 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
437 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
438 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
439 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
440 | ||
441 | /* In indirect mode when disabling interrupts, we also need | |
442 | * to clear the interrupt bit in the GRC local ctrl register. | |
443 | */ | |
444 | if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) && | |
445 | (val == 0x1)) { | |
446 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, | |
447 | tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); | |
448 | } | |
449 | } | |
450 | ||
451 | static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) | |
452 | { | |
453 | unsigned long flags; | |
454 | u32 val; | |
455 | ||
456 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
457 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
458 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
459 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
460 | return val; | |
461 | } | |
462 | ||
b401e9e2 MC |
463 | /* usec_wait specifies the wait time in usec when writing to certain registers |
464 | * where it is unsafe to read back the register without some delay. | |
465 | * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power. | |
466 | * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed. | |
467 | */ | |
468 | static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) | |
6892914f | 469 | { |
b401e9e2 MC |
470 | if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) || |
471 | (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)) | |
472 | /* Non-posted methods */ | |
473 | tp->write32(tp, off, val); | |
474 | else { | |
475 | /* Posted method */ | |
476 | tg3_write32(tp, off, val); | |
477 | if (usec_wait) | |
478 | udelay(usec_wait); | |
479 | tp->read32(tp, off); | |
480 | } | |
481 | /* Wait again after the read for the posted method to guarantee that | |
482 | * the wait time is met. | |
483 | */ | |
484 | if (usec_wait) | |
485 | udelay(usec_wait); | |
1da177e4 LT |
486 | } |
487 | ||
09ee929c MC |
488 | static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) |
489 | { | |
490 | tp->write32_mbox(tp, off, val); | |
6892914f MC |
491 | if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) && |
492 | !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)) | |
493 | tp->read32_mbox(tp, off); | |
09ee929c MC |
494 | } |
495 | ||
20094930 | 496 | static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) |
1da177e4 LT |
497 | { |
498 | void __iomem *mbox = tp->regs + off; | |
499 | writel(val, mbox); | |
500 | if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) | |
501 | writel(val, mbox); | |
502 | if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) | |
503 | readl(mbox); | |
504 | } | |
505 | ||
b5d3772c MC |
506 | static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) |
507 | { | |
de6f31eb | 508 | return readl(tp->regs + off + GRCMBOX_BASE); |
b5d3772c MC |
509 | } |
510 | ||
511 | static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) | |
512 | { | |
513 | writel(val, tp->regs + off + GRCMBOX_BASE); | |
514 | } | |
515 | ||
c6cdf436 | 516 | #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) |
09ee929c | 517 | #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) |
c6cdf436 MC |
518 | #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) |
519 | #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) | |
520 | #define tr32_mailbox(reg) tp->read32_mbox(tp, reg) | |
20094930 | 521 | |
c6cdf436 MC |
522 | #define tw32(reg, val) tp->write32(tp, reg, val) |
523 | #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0) | |
524 | #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us)) | |
525 | #define tr32(reg) tp->read32(tp, reg) | |
1da177e4 LT |
526 | |
527 | static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) | |
528 | { | |
6892914f MC |
529 | unsigned long flags; |
530 | ||
b5d3772c MC |
531 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) && |
532 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) | |
533 | return; | |
534 | ||
6892914f | 535 | spin_lock_irqsave(&tp->indirect_lock, flags); |
bbadf503 MC |
536 | if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) { |
537 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); | |
538 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 539 | |
bbadf503 MC |
540 | /* Always leave this as zero. */ |
541 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
542 | } else { | |
543 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
544 | tw32_f(TG3PCI_MEM_WIN_DATA, val); | |
28fbef78 | 545 | |
bbadf503 MC |
546 | /* Always leave this as zero. */ |
547 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
548 | } | |
549 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
758a6139 DM |
550 | } |
551 | ||
1da177e4 LT |
552 | static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) |
553 | { | |
6892914f MC |
554 | unsigned long flags; |
555 | ||
b5d3772c MC |
556 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) && |
557 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) { | |
558 | *val = 0; | |
559 | return; | |
560 | } | |
561 | ||
6892914f | 562 | spin_lock_irqsave(&tp->indirect_lock, flags); |
bbadf503 MC |
563 | if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) { |
564 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); | |
565 | pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 566 | |
bbadf503 MC |
567 | /* Always leave this as zero. */ |
568 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
569 | } else { | |
570 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
571 | *val = tr32(TG3PCI_MEM_WIN_DATA); | |
572 | ||
573 | /* Always leave this as zero. */ | |
574 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
575 | } | |
6892914f | 576 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1da177e4 LT |
577 | } |
578 | ||
0d3031d9 MC |
579 | static void tg3_ape_lock_init(struct tg3 *tp) |
580 | { | |
581 | int i; | |
f92d9dc1 MC |
582 | u32 regbase; |
583 | ||
584 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
585 | regbase = TG3_APE_LOCK_GRANT; | |
586 | else | |
587 | regbase = TG3_APE_PER_LOCK_GRANT; | |
0d3031d9 MC |
588 | |
589 | /* Make sure the driver hasn't any stale locks. */ | |
590 | for (i = 0; i < 8; i++) | |
f92d9dc1 | 591 | tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER); |
0d3031d9 MC |
592 | } |
593 | ||
594 | static int tg3_ape_lock(struct tg3 *tp, int locknum) | |
595 | { | |
596 | int i, off; | |
597 | int ret = 0; | |
f92d9dc1 | 598 | u32 status, req, gnt; |
0d3031d9 MC |
599 | |
600 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
601 | return 0; | |
602 | ||
603 | switch (locknum) { | |
33f401ae MC |
604 | case TG3_APE_LOCK_GRC: |
605 | case TG3_APE_LOCK_MEM: | |
606 | break; | |
607 | default: | |
608 | return -EINVAL; | |
0d3031d9 MC |
609 | } |
610 | ||
f92d9dc1 MC |
611 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { |
612 | req = TG3_APE_LOCK_REQ; | |
613 | gnt = TG3_APE_LOCK_GRANT; | |
614 | } else { | |
615 | req = TG3_APE_PER_LOCK_REQ; | |
616 | gnt = TG3_APE_PER_LOCK_GRANT; | |
617 | } | |
618 | ||
0d3031d9 MC |
619 | off = 4 * locknum; |
620 | ||
f92d9dc1 | 621 | tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER); |
0d3031d9 MC |
622 | |
623 | /* Wait for up to 1 millisecond to acquire lock. */ | |
624 | for (i = 0; i < 100; i++) { | |
f92d9dc1 | 625 | status = tg3_ape_read32(tp, gnt + off); |
0d3031d9 MC |
626 | if (status == APE_LOCK_GRANT_DRIVER) |
627 | break; | |
628 | udelay(10); | |
629 | } | |
630 | ||
631 | if (status != APE_LOCK_GRANT_DRIVER) { | |
632 | /* Revoke the lock request. */ | |
f92d9dc1 | 633 | tg3_ape_write32(tp, gnt + off, |
0d3031d9 MC |
634 | APE_LOCK_GRANT_DRIVER); |
635 | ||
636 | ret = -EBUSY; | |
637 | } | |
638 | ||
639 | return ret; | |
640 | } | |
641 | ||
642 | static void tg3_ape_unlock(struct tg3 *tp, int locknum) | |
643 | { | |
f92d9dc1 | 644 | u32 gnt; |
0d3031d9 MC |
645 | |
646 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
647 | return; | |
648 | ||
649 | switch (locknum) { | |
33f401ae MC |
650 | case TG3_APE_LOCK_GRC: |
651 | case TG3_APE_LOCK_MEM: | |
652 | break; | |
653 | default: | |
654 | return; | |
0d3031d9 MC |
655 | } |
656 | ||
f92d9dc1 MC |
657 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
658 | gnt = TG3_APE_LOCK_GRANT; | |
659 | else | |
660 | gnt = TG3_APE_PER_LOCK_GRANT; | |
661 | ||
662 | tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER); | |
0d3031d9 MC |
663 | } |
664 | ||
1da177e4 LT |
665 | static void tg3_disable_ints(struct tg3 *tp) |
666 | { | |
89aeb3bc MC |
667 | int i; |
668 | ||
1da177e4 LT |
669 | tw32(TG3PCI_MISC_HOST_CTRL, |
670 | (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc MC |
671 | for (i = 0; i < tp->irq_max; i++) |
672 | tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); | |
1da177e4 LT |
673 | } |
674 | ||
1da177e4 LT |
675 | static void tg3_enable_ints(struct tg3 *tp) |
676 | { | |
89aeb3bc | 677 | int i; |
89aeb3bc | 678 | |
bbe832c0 MC |
679 | tp->irq_sync = 0; |
680 | wmb(); | |
681 | ||
1da177e4 LT |
682 | tw32(TG3PCI_MISC_HOST_CTRL, |
683 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc | 684 | |
f89f38b8 | 685 | tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; |
89aeb3bc MC |
686 | for (i = 0; i < tp->irq_cnt; i++) { |
687 | struct tg3_napi *tnapi = &tp->napi[i]; | |
c6cdf436 | 688 | |
898a56f8 | 689 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
89aeb3bc MC |
690 | if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) |
691 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); | |
f19af9c2 | 692 | |
f89f38b8 | 693 | tp->coal_now |= tnapi->coal_now; |
89aeb3bc | 694 | } |
f19af9c2 MC |
695 | |
696 | /* Force an initial interrupt */ | |
697 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && | |
698 | (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) | |
699 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
700 | else | |
f89f38b8 MC |
701 | tw32(HOSTCC_MODE, tp->coal_now); |
702 | ||
703 | tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); | |
1da177e4 LT |
704 | } |
705 | ||
17375d25 | 706 | static inline unsigned int tg3_has_work(struct tg3_napi *tnapi) |
04237ddd | 707 | { |
17375d25 | 708 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 709 | struct tg3_hw_status *sblk = tnapi->hw_status; |
04237ddd MC |
710 | unsigned int work_exists = 0; |
711 | ||
712 | /* check for phy events */ | |
713 | if (!(tp->tg3_flags & | |
714 | (TG3_FLAG_USE_LINKCHG_REG | | |
715 | TG3_FLAG_POLL_SERDES))) { | |
716 | if (sblk->status & SD_STATUS_LINK_CHG) | |
717 | work_exists = 1; | |
718 | } | |
719 | /* check for RX/TX work to do */ | |
f3f3f27e | 720 | if (sblk->idx[0].tx_consumer != tnapi->tx_cons || |
8d9d7cfc | 721 | *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
04237ddd MC |
722 | work_exists = 1; |
723 | ||
724 | return work_exists; | |
725 | } | |
726 | ||
17375d25 | 727 | /* tg3_int_reenable |
04237ddd MC |
728 | * similar to tg3_enable_ints, but it accurately determines whether there |
729 | * is new work pending and can return without flushing the PIO write | |
6aa20a22 | 730 | * which reenables interrupts |
1da177e4 | 731 | */ |
17375d25 | 732 | static void tg3_int_reenable(struct tg3_napi *tnapi) |
1da177e4 | 733 | { |
17375d25 MC |
734 | struct tg3 *tp = tnapi->tp; |
735 | ||
898a56f8 | 736 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); |
1da177e4 LT |
737 | mmiowb(); |
738 | ||
fac9b83e DM |
739 | /* When doing tagged status, this work check is unnecessary. |
740 | * The last_tag we write above tells the chip which piece of | |
741 | * work we've completed. | |
742 | */ | |
743 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && | |
17375d25 | 744 | tg3_has_work(tnapi)) |
04237ddd | 745 | tw32(HOSTCC_MODE, tp->coalesce_mode | |
fd2ce37f | 746 | HOSTCC_MODE_ENABLE | tnapi->coal_now); |
1da177e4 LT |
747 | } |
748 | ||
1da177e4 LT |
749 | static void tg3_switch_clocks(struct tg3 *tp) |
750 | { | |
f6eb9b1f | 751 | u32 clock_ctrl; |
1da177e4 LT |
752 | u32 orig_clock_ctrl; |
753 | ||
795d01c5 MC |
754 | if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || |
755 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
4cf78e4f MC |
756 | return; |
757 | ||
f6eb9b1f MC |
758 | clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); |
759 | ||
1da177e4 LT |
760 | orig_clock_ctrl = clock_ctrl; |
761 | clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | | |
762 | CLOCK_CTRL_CLKRUN_OENABLE | | |
763 | 0x1f); | |
764 | tp->pci_clock_ctrl = clock_ctrl; | |
765 | ||
766 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
767 | if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) { | |
b401e9e2 MC |
768 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
769 | clock_ctrl | CLOCK_CTRL_625_CORE, 40); | |
1da177e4 LT |
770 | } |
771 | } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { | |
b401e9e2 MC |
772 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
773 | clock_ctrl | | |
774 | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK), | |
775 | 40); | |
776 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
777 | clock_ctrl | (CLOCK_CTRL_ALTCLK), | |
778 | 40); | |
1da177e4 | 779 | } |
b401e9e2 | 780 | tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40); |
1da177e4 LT |
781 | } |
782 | ||
783 | #define PHY_BUSY_LOOPS 5000 | |
784 | ||
785 | static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) | |
786 | { | |
787 | u32 frame_val; | |
788 | unsigned int loops; | |
789 | int ret; | |
790 | ||
791 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
792 | tw32_f(MAC_MI_MODE, | |
793 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
794 | udelay(80); | |
795 | } | |
796 | ||
797 | *val = 0x0; | |
798 | ||
882e9793 | 799 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
800 | MI_COM_PHY_ADDR_MASK); |
801 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
802 | MI_COM_REG_ADDR_MASK); | |
803 | frame_val |= (MI_COM_CMD_READ | MI_COM_START); | |
6aa20a22 | 804 | |
1da177e4 LT |
805 | tw32_f(MAC_MI_COM, frame_val); |
806 | ||
807 | loops = PHY_BUSY_LOOPS; | |
808 | while (loops != 0) { | |
809 | udelay(10); | |
810 | frame_val = tr32(MAC_MI_COM); | |
811 | ||
812 | if ((frame_val & MI_COM_BUSY) == 0) { | |
813 | udelay(5); | |
814 | frame_val = tr32(MAC_MI_COM); | |
815 | break; | |
816 | } | |
817 | loops -= 1; | |
818 | } | |
819 | ||
820 | ret = -EBUSY; | |
821 | if (loops != 0) { | |
822 | *val = frame_val & MI_COM_DATA_MASK; | |
823 | ret = 0; | |
824 | } | |
825 | ||
826 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
827 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
828 | udelay(80); | |
829 | } | |
830 | ||
831 | return ret; | |
832 | } | |
833 | ||
834 | static int tg3_writephy(struct tg3 *tp, int reg, u32 val) | |
835 | { | |
836 | u32 frame_val; | |
837 | unsigned int loops; | |
838 | int ret; | |
839 | ||
f07e9af3 | 840 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && |
b5d3772c MC |
841 | (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL)) |
842 | return 0; | |
843 | ||
1da177e4 LT |
844 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
845 | tw32_f(MAC_MI_MODE, | |
846 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
847 | udelay(80); | |
848 | } | |
849 | ||
882e9793 | 850 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
851 | MI_COM_PHY_ADDR_MASK); |
852 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
853 | MI_COM_REG_ADDR_MASK); | |
854 | frame_val |= (val & MI_COM_DATA_MASK); | |
855 | frame_val |= (MI_COM_CMD_WRITE | MI_COM_START); | |
6aa20a22 | 856 | |
1da177e4 LT |
857 | tw32_f(MAC_MI_COM, frame_val); |
858 | ||
859 | loops = PHY_BUSY_LOOPS; | |
860 | while (loops != 0) { | |
861 | udelay(10); | |
862 | frame_val = tr32(MAC_MI_COM); | |
863 | if ((frame_val & MI_COM_BUSY) == 0) { | |
864 | udelay(5); | |
865 | frame_val = tr32(MAC_MI_COM); | |
866 | break; | |
867 | } | |
868 | loops -= 1; | |
869 | } | |
870 | ||
871 | ret = -EBUSY; | |
872 | if (loops != 0) | |
873 | ret = 0; | |
874 | ||
875 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
876 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
877 | udelay(80); | |
878 | } | |
879 | ||
880 | return ret; | |
881 | } | |
882 | ||
95e2869a MC |
883 | static int tg3_bmcr_reset(struct tg3 *tp) |
884 | { | |
885 | u32 phy_control; | |
886 | int limit, err; | |
887 | ||
888 | /* OK, reset it, and poll the BMCR_RESET bit until it | |
889 | * clears or we time out. | |
890 | */ | |
891 | phy_control = BMCR_RESET; | |
892 | err = tg3_writephy(tp, MII_BMCR, phy_control); | |
893 | if (err != 0) | |
894 | return -EBUSY; | |
895 | ||
896 | limit = 5000; | |
897 | while (limit--) { | |
898 | err = tg3_readphy(tp, MII_BMCR, &phy_control); | |
899 | if (err != 0) | |
900 | return -EBUSY; | |
901 | ||
902 | if ((phy_control & BMCR_RESET) == 0) { | |
903 | udelay(40); | |
904 | break; | |
905 | } | |
906 | udelay(10); | |
907 | } | |
d4675b52 | 908 | if (limit < 0) |
95e2869a MC |
909 | return -EBUSY; |
910 | ||
911 | return 0; | |
912 | } | |
913 | ||
158d7abd MC |
914 | static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg) |
915 | { | |
3d16543d | 916 | struct tg3 *tp = bp->priv; |
158d7abd MC |
917 | u32 val; |
918 | ||
24bb4fb6 | 919 | spin_lock_bh(&tp->lock); |
158d7abd MC |
920 | |
921 | if (tg3_readphy(tp, reg, &val)) | |
24bb4fb6 MC |
922 | val = -EIO; |
923 | ||
924 | spin_unlock_bh(&tp->lock); | |
158d7abd MC |
925 | |
926 | return val; | |
927 | } | |
928 | ||
929 | static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val) | |
930 | { | |
3d16543d | 931 | struct tg3 *tp = bp->priv; |
24bb4fb6 | 932 | u32 ret = 0; |
158d7abd | 933 | |
24bb4fb6 | 934 | spin_lock_bh(&tp->lock); |
158d7abd MC |
935 | |
936 | if (tg3_writephy(tp, reg, val)) | |
24bb4fb6 | 937 | ret = -EIO; |
158d7abd | 938 | |
24bb4fb6 MC |
939 | spin_unlock_bh(&tp->lock); |
940 | ||
941 | return ret; | |
158d7abd MC |
942 | } |
943 | ||
944 | static int tg3_mdio_reset(struct mii_bus *bp) | |
945 | { | |
946 | return 0; | |
947 | } | |
948 | ||
9c61d6bc | 949 | static void tg3_mdio_config_5785(struct tg3 *tp) |
a9daf367 MC |
950 | { |
951 | u32 val; | |
fcb389df | 952 | struct phy_device *phydev; |
a9daf367 | 953 | |
3f0e3ad7 | 954 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
fcb389df | 955 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { |
6a443a0f MC |
956 | case PHY_ID_BCM50610: |
957 | case PHY_ID_BCM50610M: | |
fcb389df MC |
958 | val = MAC_PHYCFG2_50610_LED_MODES; |
959 | break; | |
6a443a0f | 960 | case PHY_ID_BCMAC131: |
fcb389df MC |
961 | val = MAC_PHYCFG2_AC131_LED_MODES; |
962 | break; | |
6a443a0f | 963 | case PHY_ID_RTL8211C: |
fcb389df MC |
964 | val = MAC_PHYCFG2_RTL8211C_LED_MODES; |
965 | break; | |
6a443a0f | 966 | case PHY_ID_RTL8201E: |
fcb389df MC |
967 | val = MAC_PHYCFG2_RTL8201E_LED_MODES; |
968 | break; | |
969 | default: | |
a9daf367 | 970 | return; |
fcb389df MC |
971 | } |
972 | ||
973 | if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { | |
974 | tw32(MAC_PHYCFG2, val); | |
975 | ||
976 | val = tr32(MAC_PHYCFG1); | |
bb85fbb6 MC |
977 | val &= ~(MAC_PHYCFG1_RGMII_INT | |
978 | MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK); | |
979 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT; | |
fcb389df MC |
980 | tw32(MAC_PHYCFG1, val); |
981 | ||
982 | return; | |
983 | } | |
984 | ||
14417063 | 985 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) |
fcb389df MC |
986 | val |= MAC_PHYCFG2_EMODE_MASK_MASK | |
987 | MAC_PHYCFG2_FMODE_MASK_MASK | | |
988 | MAC_PHYCFG2_GMODE_MASK_MASK | | |
989 | MAC_PHYCFG2_ACT_MASK_MASK | | |
990 | MAC_PHYCFG2_QUAL_MASK_MASK | | |
991 | MAC_PHYCFG2_INBAND_ENABLE; | |
992 | ||
993 | tw32(MAC_PHYCFG2, val); | |
a9daf367 | 994 | |
bb85fbb6 MC |
995 | val = tr32(MAC_PHYCFG1); |
996 | val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK | | |
997 | MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN); | |
14417063 | 998 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) { |
a9daf367 MC |
999 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) |
1000 | val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC; | |
1001 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
1002 | val |= MAC_PHYCFG1_RGMII_SND_STAT_EN; | |
1003 | } | |
bb85fbb6 MC |
1004 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT | |
1005 | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV; | |
1006 | tw32(MAC_PHYCFG1, val); | |
a9daf367 | 1007 | |
a9daf367 MC |
1008 | val = tr32(MAC_EXT_RGMII_MODE); |
1009 | val &= ~(MAC_RGMII_MODE_RX_INT_B | | |
1010 | MAC_RGMII_MODE_RX_QUALITY | | |
1011 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1012 | MAC_RGMII_MODE_RX_ENG_DET | | |
1013 | MAC_RGMII_MODE_TX_ENABLE | | |
1014 | MAC_RGMII_MODE_TX_LOWPWR | | |
1015 | MAC_RGMII_MODE_TX_RESET); | |
14417063 | 1016 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) { |
a9daf367 MC |
1017 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) |
1018 | val |= MAC_RGMII_MODE_RX_INT_B | | |
1019 | MAC_RGMII_MODE_RX_QUALITY | | |
1020 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1021 | MAC_RGMII_MODE_RX_ENG_DET; | |
1022 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
1023 | val |= MAC_RGMII_MODE_TX_ENABLE | | |
1024 | MAC_RGMII_MODE_TX_LOWPWR | | |
1025 | MAC_RGMII_MODE_TX_RESET; | |
1026 | } | |
1027 | tw32(MAC_EXT_RGMII_MODE, val); | |
1028 | } | |
1029 | ||
158d7abd MC |
1030 | static void tg3_mdio_start(struct tg3 *tp) |
1031 | { | |
158d7abd MC |
1032 | tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; |
1033 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
1034 | udelay(80); | |
a9daf367 | 1035 | |
9ea4818d MC |
1036 | if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) && |
1037 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1038 | tg3_mdio_config_5785(tp); | |
1039 | } | |
1040 | ||
1041 | static int tg3_mdio_init(struct tg3 *tp) | |
1042 | { | |
1043 | int i; | |
1044 | u32 reg; | |
1045 | struct phy_device *phydev; | |
1046 | ||
a50d0796 MC |
1047 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
1048 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) { | |
9c7df915 | 1049 | u32 is_serdes; |
882e9793 | 1050 | |
9c7df915 | 1051 | tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1; |
882e9793 | 1052 | |
d1ec96af MC |
1053 | if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) |
1054 | is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; | |
1055 | else | |
1056 | is_serdes = tr32(TG3_CPMU_PHY_STRAP) & | |
1057 | TG3_CPMU_PHY_STRAP_IS_SERDES; | |
882e9793 MC |
1058 | if (is_serdes) |
1059 | tp->phy_addr += 7; | |
1060 | } else | |
3f0e3ad7 | 1061 | tp->phy_addr = TG3_PHY_MII_ADDR; |
882e9793 | 1062 | |
158d7abd MC |
1063 | tg3_mdio_start(tp); |
1064 | ||
1065 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) || | |
1066 | (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED)) | |
1067 | return 0; | |
1068 | ||
298cf9be LB |
1069 | tp->mdio_bus = mdiobus_alloc(); |
1070 | if (tp->mdio_bus == NULL) | |
1071 | return -ENOMEM; | |
158d7abd | 1072 | |
298cf9be LB |
1073 | tp->mdio_bus->name = "tg3 mdio bus"; |
1074 | snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", | |
158d7abd | 1075 | (tp->pdev->bus->number << 8) | tp->pdev->devfn); |
298cf9be LB |
1076 | tp->mdio_bus->priv = tp; |
1077 | tp->mdio_bus->parent = &tp->pdev->dev; | |
1078 | tp->mdio_bus->read = &tg3_mdio_read; | |
1079 | tp->mdio_bus->write = &tg3_mdio_write; | |
1080 | tp->mdio_bus->reset = &tg3_mdio_reset; | |
3f0e3ad7 | 1081 | tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR); |
298cf9be | 1082 | tp->mdio_bus->irq = &tp->mdio_irq[0]; |
158d7abd MC |
1083 | |
1084 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
298cf9be | 1085 | tp->mdio_bus->irq[i] = PHY_POLL; |
158d7abd MC |
1086 | |
1087 | /* The bus registration will look for all the PHYs on the mdio bus. | |
1088 | * Unfortunately, it does not ensure the PHY is powered up before | |
1089 | * accessing the PHY ID registers. A chip reset is the | |
1090 | * quickest way to bring the device back to an operational state.. | |
1091 | */ | |
1092 | if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) | |
1093 | tg3_bmcr_reset(tp); | |
1094 | ||
298cf9be | 1095 | i = mdiobus_register(tp->mdio_bus); |
a9daf367 | 1096 | if (i) { |
ab96b241 | 1097 | dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); |
9c61d6bc | 1098 | mdiobus_free(tp->mdio_bus); |
a9daf367 MC |
1099 | return i; |
1100 | } | |
158d7abd | 1101 | |
3f0e3ad7 | 1102 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
a9daf367 | 1103 | |
9c61d6bc | 1104 | if (!phydev || !phydev->drv) { |
ab96b241 | 1105 | dev_warn(&tp->pdev->dev, "No PHY devices\n"); |
9c61d6bc MC |
1106 | mdiobus_unregister(tp->mdio_bus); |
1107 | mdiobus_free(tp->mdio_bus); | |
1108 | return -ENODEV; | |
1109 | } | |
1110 | ||
1111 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { | |
6a443a0f | 1112 | case PHY_ID_BCM57780: |
321d32a0 | 1113 | phydev->interface = PHY_INTERFACE_MODE_GMII; |
c704dc23 | 1114 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
321d32a0 | 1115 | break; |
6a443a0f MC |
1116 | case PHY_ID_BCM50610: |
1117 | case PHY_ID_BCM50610M: | |
32e5a8d6 | 1118 | phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | |
c704dc23 | 1119 | PHY_BRCM_RX_REFCLK_UNUSED | |
52fae083 | 1120 | PHY_BRCM_DIS_TXCRXC_NOENRGY | |
c704dc23 | 1121 | PHY_BRCM_AUTO_PWRDWN_ENABLE; |
14417063 | 1122 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE) |
a9daf367 MC |
1123 | phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; |
1124 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) | |
1125 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE; | |
1126 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
1127 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; | |
fcb389df | 1128 | /* fallthru */ |
6a443a0f | 1129 | case PHY_ID_RTL8211C: |
fcb389df | 1130 | phydev->interface = PHY_INTERFACE_MODE_RGMII; |
a9daf367 | 1131 | break; |
6a443a0f MC |
1132 | case PHY_ID_RTL8201E: |
1133 | case PHY_ID_BCMAC131: | |
a9daf367 | 1134 | phydev->interface = PHY_INTERFACE_MODE_MII; |
cdd4e09d | 1135 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
f07e9af3 | 1136 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
a9daf367 MC |
1137 | break; |
1138 | } | |
1139 | ||
9c61d6bc MC |
1140 | tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED; |
1141 | ||
1142 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1143 | tg3_mdio_config_5785(tp); | |
a9daf367 MC |
1144 | |
1145 | return 0; | |
158d7abd MC |
1146 | } |
1147 | ||
1148 | static void tg3_mdio_fini(struct tg3 *tp) | |
1149 | { | |
1150 | if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) { | |
1151 | tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED; | |
298cf9be LB |
1152 | mdiobus_unregister(tp->mdio_bus); |
1153 | mdiobus_free(tp->mdio_bus); | |
158d7abd MC |
1154 | } |
1155 | } | |
1156 | ||
ddfc87bf MC |
1157 | static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) |
1158 | { | |
1159 | int err; | |
1160 | ||
1161 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
1162 | if (err) | |
1163 | goto done; | |
1164 | ||
1165 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
1166 | if (err) | |
1167 | goto done; | |
1168 | ||
1169 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
1170 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
1171 | if (err) | |
1172 | goto done; | |
1173 | ||
1174 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); | |
1175 | ||
1176 | done: | |
1177 | return err; | |
1178 | } | |
1179 | ||
1180 | static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val) | |
1181 | { | |
1182 | int err; | |
1183 | ||
1184 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
1185 | if (err) | |
1186 | goto done; | |
1187 | ||
1188 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
1189 | if (err) | |
1190 | goto done; | |
1191 | ||
1192 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
1193 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
1194 | if (err) | |
1195 | goto done; | |
1196 | ||
1197 | err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val); | |
1198 | ||
1199 | done: | |
1200 | return err; | |
1201 | } | |
1202 | ||
4ba526ce MC |
1203 | /* tp->lock is held. */ |
1204 | static inline void tg3_generate_fw_event(struct tg3 *tp) | |
1205 | { | |
1206 | u32 val; | |
1207 | ||
1208 | val = tr32(GRC_RX_CPU_EVENT); | |
1209 | val |= GRC_RX_CPU_DRIVER_EVENT; | |
1210 | tw32_f(GRC_RX_CPU_EVENT, val); | |
1211 | ||
1212 | tp->last_event_jiffies = jiffies; | |
1213 | } | |
1214 | ||
1215 | #define TG3_FW_EVENT_TIMEOUT_USEC 2500 | |
1216 | ||
95e2869a MC |
1217 | /* tp->lock is held. */ |
1218 | static void tg3_wait_for_event_ack(struct tg3 *tp) | |
1219 | { | |
1220 | int i; | |
4ba526ce MC |
1221 | unsigned int delay_cnt; |
1222 | long time_remain; | |
1223 | ||
1224 | /* If enough time has passed, no wait is necessary. */ | |
1225 | time_remain = (long)(tp->last_event_jiffies + 1 + | |
1226 | usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - | |
1227 | (long)jiffies; | |
1228 | if (time_remain < 0) | |
1229 | return; | |
1230 | ||
1231 | /* Check if we can shorten the wait time. */ | |
1232 | delay_cnt = jiffies_to_usecs(time_remain); | |
1233 | if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC) | |
1234 | delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC; | |
1235 | delay_cnt = (delay_cnt >> 3) + 1; | |
95e2869a | 1236 | |
4ba526ce | 1237 | for (i = 0; i < delay_cnt; i++) { |
95e2869a MC |
1238 | if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) |
1239 | break; | |
4ba526ce | 1240 | udelay(8); |
95e2869a MC |
1241 | } |
1242 | } | |
1243 | ||
1244 | /* tp->lock is held. */ | |
1245 | static void tg3_ump_link_report(struct tg3 *tp) | |
1246 | { | |
1247 | u32 reg; | |
1248 | u32 val; | |
1249 | ||
1250 | if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || | |
1251 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
1252 | return; | |
1253 | ||
1254 | tg3_wait_for_event_ack(tp); | |
1255 | ||
1256 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); | |
1257 | ||
1258 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); | |
1259 | ||
1260 | val = 0; | |
1261 | if (!tg3_readphy(tp, MII_BMCR, ®)) | |
1262 | val = reg << 16; | |
1263 | if (!tg3_readphy(tp, MII_BMSR, ®)) | |
1264 | val |= (reg & 0xffff); | |
1265 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val); | |
1266 | ||
1267 | val = 0; | |
1268 | if (!tg3_readphy(tp, MII_ADVERTISE, ®)) | |
1269 | val = reg << 16; | |
1270 | if (!tg3_readphy(tp, MII_LPA, ®)) | |
1271 | val |= (reg & 0xffff); | |
1272 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val); | |
1273 | ||
1274 | val = 0; | |
f07e9af3 | 1275 | if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { |
95e2869a MC |
1276 | if (!tg3_readphy(tp, MII_CTRL1000, ®)) |
1277 | val = reg << 16; | |
1278 | if (!tg3_readphy(tp, MII_STAT1000, ®)) | |
1279 | val |= (reg & 0xffff); | |
1280 | } | |
1281 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val); | |
1282 | ||
1283 | if (!tg3_readphy(tp, MII_PHYADDR, ®)) | |
1284 | val = reg << 16; | |
1285 | else | |
1286 | val = 0; | |
1287 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val); | |
1288 | ||
4ba526ce | 1289 | tg3_generate_fw_event(tp); |
95e2869a MC |
1290 | } |
1291 | ||
1292 | static void tg3_link_report(struct tg3 *tp) | |
1293 | { | |
1294 | if (!netif_carrier_ok(tp->dev)) { | |
05dbe005 | 1295 | netif_info(tp, link, tp->dev, "Link is down\n"); |
95e2869a MC |
1296 | tg3_ump_link_report(tp); |
1297 | } else if (netif_msg_link(tp)) { | |
05dbe005 JP |
1298 | netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", |
1299 | (tp->link_config.active_speed == SPEED_1000 ? | |
1300 | 1000 : | |
1301 | (tp->link_config.active_speed == SPEED_100 ? | |
1302 | 100 : 10)), | |
1303 | (tp->link_config.active_duplex == DUPLEX_FULL ? | |
1304 | "full" : "half")); | |
1305 | ||
1306 | netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", | |
1307 | (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? | |
1308 | "on" : "off", | |
1309 | (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? | |
1310 | "on" : "off"); | |
95e2869a MC |
1311 | tg3_ump_link_report(tp); |
1312 | } | |
1313 | } | |
1314 | ||
1315 | static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl) | |
1316 | { | |
1317 | u16 miireg; | |
1318 | ||
e18ce346 | 1319 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1320 | miireg = ADVERTISE_PAUSE_CAP; |
e18ce346 | 1321 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1322 | miireg = ADVERTISE_PAUSE_ASYM; |
e18ce346 | 1323 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1324 | miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1325 | else | |
1326 | miireg = 0; | |
1327 | ||
1328 | return miireg; | |
1329 | } | |
1330 | ||
1331 | static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) | |
1332 | { | |
1333 | u16 miireg; | |
1334 | ||
e18ce346 | 1335 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1336 | miireg = ADVERTISE_1000XPAUSE; |
e18ce346 | 1337 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1338 | miireg = ADVERTISE_1000XPSE_ASYM; |
e18ce346 | 1339 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1340 | miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; |
1341 | else | |
1342 | miireg = 0; | |
1343 | ||
1344 | return miireg; | |
1345 | } | |
1346 | ||
95e2869a MC |
1347 | static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) |
1348 | { | |
1349 | u8 cap = 0; | |
1350 | ||
1351 | if (lcladv & ADVERTISE_1000XPAUSE) { | |
1352 | if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1353 | if (rmtadv & LPA_1000XPAUSE) | |
e18ce346 | 1354 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; |
95e2869a | 1355 | else if (rmtadv & LPA_1000XPAUSE_ASYM) |
e18ce346 | 1356 | cap = FLOW_CTRL_RX; |
95e2869a MC |
1357 | } else { |
1358 | if (rmtadv & LPA_1000XPAUSE) | |
e18ce346 | 1359 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; |
95e2869a MC |
1360 | } |
1361 | } else if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1362 | if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM)) | |
e18ce346 | 1363 | cap = FLOW_CTRL_TX; |
95e2869a MC |
1364 | } |
1365 | ||
1366 | return cap; | |
1367 | } | |
1368 | ||
f51f3562 | 1369 | static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) |
95e2869a | 1370 | { |
b02fd9e3 | 1371 | u8 autoneg; |
f51f3562 | 1372 | u8 flowctrl = 0; |
95e2869a MC |
1373 | u32 old_rx_mode = tp->rx_mode; |
1374 | u32 old_tx_mode = tp->tx_mode; | |
1375 | ||
b02fd9e3 | 1376 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) |
3f0e3ad7 | 1377 | autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg; |
b02fd9e3 MC |
1378 | else |
1379 | autoneg = tp->link_config.autoneg; | |
1380 | ||
1381 | if (autoneg == AUTONEG_ENABLE && | |
95e2869a | 1382 | (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) { |
f07e9af3 | 1383 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
f51f3562 | 1384 | flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv); |
95e2869a | 1385 | else |
bc02ff95 | 1386 | flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
f51f3562 MC |
1387 | } else |
1388 | flowctrl = tp->link_config.flowctrl; | |
95e2869a | 1389 | |
f51f3562 | 1390 | tp->link_config.active_flowctrl = flowctrl; |
95e2869a | 1391 | |
e18ce346 | 1392 | if (flowctrl & FLOW_CTRL_RX) |
95e2869a MC |
1393 | tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; |
1394 | else | |
1395 | tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; | |
1396 | ||
f51f3562 | 1397 | if (old_rx_mode != tp->rx_mode) |
95e2869a | 1398 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
95e2869a | 1399 | |
e18ce346 | 1400 | if (flowctrl & FLOW_CTRL_TX) |
95e2869a MC |
1401 | tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; |
1402 | else | |
1403 | tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; | |
1404 | ||
f51f3562 | 1405 | if (old_tx_mode != tp->tx_mode) |
95e2869a | 1406 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
95e2869a MC |
1407 | } |
1408 | ||
b02fd9e3 MC |
1409 | static void tg3_adjust_link(struct net_device *dev) |
1410 | { | |
1411 | u8 oldflowctrl, linkmesg = 0; | |
1412 | u32 mac_mode, lcl_adv, rmt_adv; | |
1413 | struct tg3 *tp = netdev_priv(dev); | |
3f0e3ad7 | 1414 | struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1415 | |
24bb4fb6 | 1416 | spin_lock_bh(&tp->lock); |
b02fd9e3 MC |
1417 | |
1418 | mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | | |
1419 | MAC_MODE_HALF_DUPLEX); | |
1420 | ||
1421 | oldflowctrl = tp->link_config.active_flowctrl; | |
1422 | ||
1423 | if (phydev->link) { | |
1424 | lcl_adv = 0; | |
1425 | rmt_adv = 0; | |
1426 | ||
1427 | if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) | |
1428 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
c3df0748 MC |
1429 | else if (phydev->speed == SPEED_1000 || |
1430 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) | |
b02fd9e3 | 1431 | mac_mode |= MAC_MODE_PORT_MODE_GMII; |
c3df0748 MC |
1432 | else |
1433 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
b02fd9e3 MC |
1434 | |
1435 | if (phydev->duplex == DUPLEX_HALF) | |
1436 | mac_mode |= MAC_MODE_HALF_DUPLEX; | |
1437 | else { | |
1438 | lcl_adv = tg3_advert_flowctrl_1000T( | |
1439 | tp->link_config.flowctrl); | |
1440 | ||
1441 | if (phydev->pause) | |
1442 | rmt_adv = LPA_PAUSE_CAP; | |
1443 | if (phydev->asym_pause) | |
1444 | rmt_adv |= LPA_PAUSE_ASYM; | |
1445 | } | |
1446 | ||
1447 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1448 | } else | |
1449 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
1450 | ||
1451 | if (mac_mode != tp->mac_mode) { | |
1452 | tp->mac_mode = mac_mode; | |
1453 | tw32_f(MAC_MODE, tp->mac_mode); | |
1454 | udelay(40); | |
1455 | } | |
1456 | ||
fcb389df MC |
1457 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
1458 | if (phydev->speed == SPEED_10) | |
1459 | tw32(MAC_MI_STAT, | |
1460 | MAC_MI_STAT_10MBPS_MODE | | |
1461 | MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1462 | else | |
1463 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1464 | } | |
1465 | ||
b02fd9e3 MC |
1466 | if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) |
1467 | tw32(MAC_TX_LENGTHS, | |
1468 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1469 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1470 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1471 | else | |
1472 | tw32(MAC_TX_LENGTHS, | |
1473 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1474 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1475 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1476 | ||
1477 | if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) || | |
1478 | (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) || | |
1479 | phydev->speed != tp->link_config.active_speed || | |
1480 | phydev->duplex != tp->link_config.active_duplex || | |
1481 | oldflowctrl != tp->link_config.active_flowctrl) | |
c6cdf436 | 1482 | linkmesg = 1; |
b02fd9e3 MC |
1483 | |
1484 | tp->link_config.active_speed = phydev->speed; | |
1485 | tp->link_config.active_duplex = phydev->duplex; | |
1486 | ||
24bb4fb6 | 1487 | spin_unlock_bh(&tp->lock); |
b02fd9e3 MC |
1488 | |
1489 | if (linkmesg) | |
1490 | tg3_link_report(tp); | |
1491 | } | |
1492 | ||
1493 | static int tg3_phy_init(struct tg3 *tp) | |
1494 | { | |
1495 | struct phy_device *phydev; | |
1496 | ||
f07e9af3 | 1497 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) |
b02fd9e3 MC |
1498 | return 0; |
1499 | ||
1500 | /* Bring the PHY back to a known state. */ | |
1501 | tg3_bmcr_reset(tp); | |
1502 | ||
3f0e3ad7 | 1503 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 MC |
1504 | |
1505 | /* Attach the MAC to the PHY. */ | |
fb28ad35 | 1506 | phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link, |
a9daf367 | 1507 | phydev->dev_flags, phydev->interface); |
b02fd9e3 | 1508 | if (IS_ERR(phydev)) { |
ab96b241 | 1509 | dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); |
b02fd9e3 MC |
1510 | return PTR_ERR(phydev); |
1511 | } | |
1512 | ||
b02fd9e3 | 1513 | /* Mask with MAC supported features. */ |
9c61d6bc MC |
1514 | switch (phydev->interface) { |
1515 | case PHY_INTERFACE_MODE_GMII: | |
1516 | case PHY_INTERFACE_MODE_RGMII: | |
f07e9af3 | 1517 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
321d32a0 MC |
1518 | phydev->supported &= (PHY_GBIT_FEATURES | |
1519 | SUPPORTED_Pause | | |
1520 | SUPPORTED_Asym_Pause); | |
1521 | break; | |
1522 | } | |
1523 | /* fallthru */ | |
9c61d6bc MC |
1524 | case PHY_INTERFACE_MODE_MII: |
1525 | phydev->supported &= (PHY_BASIC_FEATURES | | |
1526 | SUPPORTED_Pause | | |
1527 | SUPPORTED_Asym_Pause); | |
1528 | break; | |
1529 | default: | |
3f0e3ad7 | 1530 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
9c61d6bc MC |
1531 | return -EINVAL; |
1532 | } | |
1533 | ||
f07e9af3 | 1534 | tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
1535 | |
1536 | phydev->advertising = phydev->supported; | |
1537 | ||
b02fd9e3 MC |
1538 | return 0; |
1539 | } | |
1540 | ||
1541 | static void tg3_phy_start(struct tg3 *tp) | |
1542 | { | |
1543 | struct phy_device *phydev; | |
1544 | ||
f07e9af3 | 1545 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
1546 | return; |
1547 | ||
3f0e3ad7 | 1548 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1549 | |
80096068 MC |
1550 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
1551 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | |
b02fd9e3 MC |
1552 | phydev->speed = tp->link_config.orig_speed; |
1553 | phydev->duplex = tp->link_config.orig_duplex; | |
1554 | phydev->autoneg = tp->link_config.orig_autoneg; | |
1555 | phydev->advertising = tp->link_config.orig_advertising; | |
1556 | } | |
1557 | ||
1558 | phy_start(phydev); | |
1559 | ||
1560 | phy_start_aneg(phydev); | |
1561 | } | |
1562 | ||
1563 | static void tg3_phy_stop(struct tg3 *tp) | |
1564 | { | |
f07e9af3 | 1565 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
1566 | return; |
1567 | ||
3f0e3ad7 | 1568 | phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
1569 | } |
1570 | ||
1571 | static void tg3_phy_fini(struct tg3 *tp) | |
1572 | { | |
f07e9af3 | 1573 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 | 1574 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
f07e9af3 | 1575 | tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
1576 | } |
1577 | } | |
1578 | ||
52b02d04 MC |
1579 | static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val) |
1580 | { | |
1581 | int err; | |
1582 | ||
1583 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
1584 | if (!err) | |
1585 | err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); | |
1586 | ||
1587 | return err; | |
1588 | } | |
1589 | ||
6ee7c0a0 | 1590 | static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) |
b2a5c19c | 1591 | { |
6ee7c0a0 MC |
1592 | int err; |
1593 | ||
1594 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
1595 | if (!err) | |
1596 | err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); | |
1597 | ||
1598 | return err; | |
b2a5c19c MC |
1599 | } |
1600 | ||
7f97a4bd MC |
1601 | static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) |
1602 | { | |
1603 | u32 phytest; | |
1604 | ||
1605 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
1606 | u32 phy; | |
1607 | ||
1608 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1609 | phytest | MII_TG3_FET_SHADOW_EN); | |
1610 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { | |
1611 | if (enable) | |
1612 | phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1613 | else | |
1614 | phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1615 | tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); | |
1616 | } | |
1617 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
1618 | } | |
1619 | } | |
1620 | ||
6833c043 MC |
1621 | static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) |
1622 | { | |
1623 | u32 reg; | |
1624 | ||
ecf1410b | 1625 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || |
a50d0796 MC |
1626 | ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
1627 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) && | |
f07e9af3 | 1628 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) |
6833c043 MC |
1629 | return; |
1630 | ||
f07e9af3 | 1631 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
7f97a4bd MC |
1632 | tg3_phy_fet_toggle_apd(tp, enable); |
1633 | return; | |
1634 | } | |
1635 | ||
6833c043 MC |
1636 | reg = MII_TG3_MISC_SHDW_WREN | |
1637 | MII_TG3_MISC_SHDW_SCR5_SEL | | |
1638 | MII_TG3_MISC_SHDW_SCR5_LPED | | |
1639 | MII_TG3_MISC_SHDW_SCR5_DLPTLM | | |
1640 | MII_TG3_MISC_SHDW_SCR5_SDTL | | |
1641 | MII_TG3_MISC_SHDW_SCR5_C125OE; | |
1642 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable) | |
1643 | reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; | |
1644 | ||
1645 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1646 | ||
1647 | ||
1648 | reg = MII_TG3_MISC_SHDW_WREN | | |
1649 | MII_TG3_MISC_SHDW_APD_SEL | | |
1650 | MII_TG3_MISC_SHDW_APD_WKTM_84MS; | |
1651 | if (enable) | |
1652 | reg |= MII_TG3_MISC_SHDW_APD_ENABLE; | |
1653 | ||
1654 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1655 | } | |
1656 | ||
9ef8ca99 MC |
1657 | static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable) |
1658 | { | |
1659 | u32 phy; | |
1660 | ||
1661 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || | |
f07e9af3 | 1662 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
9ef8ca99 MC |
1663 | return; |
1664 | ||
f07e9af3 | 1665 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
9ef8ca99 MC |
1666 | u32 ephy; |
1667 | ||
535ef6e1 MC |
1668 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { |
1669 | u32 reg = MII_TG3_FET_SHDW_MISCCTRL; | |
1670 | ||
1671 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1672 | ephy | MII_TG3_FET_SHADOW_EN); | |
1673 | if (!tg3_readphy(tp, reg, &phy)) { | |
9ef8ca99 | 1674 | if (enable) |
535ef6e1 | 1675 | phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
9ef8ca99 | 1676 | else |
535ef6e1 MC |
1677 | phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
1678 | tg3_writephy(tp, reg, phy); | |
9ef8ca99 | 1679 | } |
535ef6e1 | 1680 | tg3_writephy(tp, MII_TG3_FET_TEST, ephy); |
9ef8ca99 MC |
1681 | } |
1682 | } else { | |
1683 | phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC | | |
1684 | MII_TG3_AUXCTL_SHDWSEL_MISC; | |
1685 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) && | |
1686 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) { | |
1687 | if (enable) | |
1688 | phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
1689 | else | |
1690 | phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
1691 | phy |= MII_TG3_AUXCTL_MISC_WREN; | |
1692 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1693 | } | |
1694 | } | |
1695 | } | |
1696 | ||
1da177e4 LT |
1697 | static void tg3_phy_set_wirespeed(struct tg3 *tp) |
1698 | { | |
1699 | u32 val; | |
1700 | ||
f07e9af3 | 1701 | if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) |
1da177e4 LT |
1702 | return; |
1703 | ||
1704 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) && | |
1705 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val)) | |
1706 | tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
1707 | (val | (1 << 15) | (1 << 4))); | |
1708 | } | |
1709 | ||
b2a5c19c MC |
1710 | static void tg3_phy_apply_otp(struct tg3 *tp) |
1711 | { | |
1712 | u32 otp, phy; | |
1713 | ||
1714 | if (!tp->phy_otp) | |
1715 | return; | |
1716 | ||
1717 | otp = tp->phy_otp; | |
1718 | ||
1719 | /* Enable SM_DSP clock and tx 6dB coding. */ | |
1720 | phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
1721 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | | |
1722 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
1723 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1724 | ||
1725 | phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT); | |
1726 | phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT; | |
1727 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); | |
1728 | ||
1729 | phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) | | |
1730 | ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT); | |
1731 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); | |
1732 | ||
1733 | phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT); | |
1734 | phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ; | |
1735 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); | |
1736 | ||
1737 | phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT); | |
1738 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); | |
1739 | ||
1740 | phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT); | |
1741 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); | |
1742 | ||
1743 | phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) | | |
1744 | ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT); | |
1745 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); | |
1746 | ||
1747 | /* Turn off SM_DSP clock. */ | |
1748 | phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
1749 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
1750 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1751 | } | |
1752 | ||
52b02d04 MC |
1753 | static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up) |
1754 | { | |
1755 | u32 val; | |
1756 | ||
1757 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) | |
1758 | return; | |
1759 | ||
1760 | tp->setlpicnt = 0; | |
1761 | ||
1762 | if (tp->link_config.autoneg == AUTONEG_ENABLE && | |
1763 | current_link_up == 1 && | |
a6b68dab MC |
1764 | tp->link_config.active_duplex == DUPLEX_FULL && |
1765 | (tp->link_config.active_speed == SPEED_100 || | |
1766 | tp->link_config.active_speed == SPEED_1000)) { | |
52b02d04 MC |
1767 | u32 eeectl; |
1768 | ||
1769 | if (tp->link_config.active_speed == SPEED_1000) | |
1770 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US; | |
1771 | else | |
1772 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US; | |
1773 | ||
1774 | tw32(TG3_CPMU_EEE_CTRL, eeectl); | |
1775 | ||
3110f5f5 MC |
1776 | tg3_phy_cl45_read(tp, MDIO_MMD_AN, |
1777 | TG3_CL45_D7_EEERES_STAT, &val); | |
52b02d04 MC |
1778 | |
1779 | if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T || | |
1780 | val == TG3_CL45_D7_EEERES_STAT_LP_100TX) | |
1781 | tp->setlpicnt = 2; | |
1782 | } | |
1783 | ||
1784 | if (!tp->setlpicnt) { | |
1785 | val = tr32(TG3_CPMU_EEE_MODE); | |
1786 | tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
1787 | } | |
1788 | } | |
1789 | ||
1da177e4 LT |
1790 | static int tg3_wait_macro_done(struct tg3 *tp) |
1791 | { | |
1792 | int limit = 100; | |
1793 | ||
1794 | while (limit--) { | |
1795 | u32 tmp32; | |
1796 | ||
f08aa1a8 | 1797 | if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) { |
1da177e4 LT |
1798 | if ((tmp32 & 0x1000) == 0) |
1799 | break; | |
1800 | } | |
1801 | } | |
d4675b52 | 1802 | if (limit < 0) |
1da177e4 LT |
1803 | return -EBUSY; |
1804 | ||
1805 | return 0; | |
1806 | } | |
1807 | ||
1808 | static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) | |
1809 | { | |
1810 | static const u32 test_pat[4][6] = { | |
1811 | { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 }, | |
1812 | { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 }, | |
1813 | { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 }, | |
1814 | { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 } | |
1815 | }; | |
1816 | int chan; | |
1817 | ||
1818 | for (chan = 0; chan < 4; chan++) { | |
1819 | int i; | |
1820 | ||
1821 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1822 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 1823 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
1824 | |
1825 | for (i = 0; i < 6; i++) | |
1826 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, | |
1827 | test_pat[chan][i]); | |
1828 | ||
f08aa1a8 | 1829 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
1830 | if (tg3_wait_macro_done(tp)) { |
1831 | *resetp = 1; | |
1832 | return -EBUSY; | |
1833 | } | |
1834 | ||
1835 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1836 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 1837 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); |
1da177e4 LT |
1838 | if (tg3_wait_macro_done(tp)) { |
1839 | *resetp = 1; | |
1840 | return -EBUSY; | |
1841 | } | |
1842 | ||
f08aa1a8 | 1843 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); |
1da177e4 LT |
1844 | if (tg3_wait_macro_done(tp)) { |
1845 | *resetp = 1; | |
1846 | return -EBUSY; | |
1847 | } | |
1848 | ||
1849 | for (i = 0; i < 6; i += 2) { | |
1850 | u32 low, high; | |
1851 | ||
1852 | if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || | |
1853 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || | |
1854 | tg3_wait_macro_done(tp)) { | |
1855 | *resetp = 1; | |
1856 | return -EBUSY; | |
1857 | } | |
1858 | low &= 0x7fff; | |
1859 | high &= 0x000f; | |
1860 | if (low != test_pat[chan][i] || | |
1861 | high != test_pat[chan][i+1]) { | |
1862 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); | |
1863 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); | |
1864 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); | |
1865 | ||
1866 | return -EBUSY; | |
1867 | } | |
1868 | } | |
1869 | } | |
1870 | ||
1871 | return 0; | |
1872 | } | |
1873 | ||
1874 | static int tg3_phy_reset_chanpat(struct tg3 *tp) | |
1875 | { | |
1876 | int chan; | |
1877 | ||
1878 | for (chan = 0; chan < 4; chan++) { | |
1879 | int i; | |
1880 | ||
1881 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1882 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 1883 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
1884 | for (i = 0; i < 6; i++) |
1885 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); | |
f08aa1a8 | 1886 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
1887 | if (tg3_wait_macro_done(tp)) |
1888 | return -EBUSY; | |
1889 | } | |
1890 | ||
1891 | return 0; | |
1892 | } | |
1893 | ||
1894 | static int tg3_phy_reset_5703_4_5(struct tg3 *tp) | |
1895 | { | |
1896 | u32 reg32, phy9_orig; | |
1897 | int retries, do_phy_reset, err; | |
1898 | ||
1899 | retries = 10; | |
1900 | do_phy_reset = 1; | |
1901 | do { | |
1902 | if (do_phy_reset) { | |
1903 | err = tg3_bmcr_reset(tp); | |
1904 | if (err) | |
1905 | return err; | |
1906 | do_phy_reset = 0; | |
1907 | } | |
1908 | ||
1909 | /* Disable transmitter and interrupt. */ | |
1910 | if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) | |
1911 | continue; | |
1912 | ||
1913 | reg32 |= 0x3000; | |
1914 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
1915 | ||
1916 | /* Set full-duplex, 1000 mbps. */ | |
1917 | tg3_writephy(tp, MII_BMCR, | |
1918 | BMCR_FULLDPLX | TG3_BMCR_SPEED1000); | |
1919 | ||
1920 | /* Set to master mode. */ | |
1921 | if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig)) | |
1922 | continue; | |
1923 | ||
1924 | tg3_writephy(tp, MII_TG3_CTRL, | |
1925 | (MII_TG3_CTRL_AS_MASTER | | |
1926 | MII_TG3_CTRL_ENABLE_AS_MASTER)); | |
1927 | ||
1928 | /* Enable SM_DSP_CLOCK and 6dB. */ | |
1929 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); | |
1930 | ||
1931 | /* Block the PHY control access. */ | |
6ee7c0a0 | 1932 | tg3_phydsp_write(tp, 0x8005, 0x0800); |
1da177e4 LT |
1933 | |
1934 | err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); | |
1935 | if (!err) | |
1936 | break; | |
1937 | } while (--retries); | |
1938 | ||
1939 | err = tg3_phy_reset_chanpat(tp); | |
1940 | if (err) | |
1941 | return err; | |
1942 | ||
6ee7c0a0 | 1943 | tg3_phydsp_write(tp, 0x8005, 0x0000); |
1da177e4 LT |
1944 | |
1945 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); | |
f08aa1a8 | 1946 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); |
1da177e4 LT |
1947 | |
1948 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
1949 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
1950 | /* Set Extended packet length bit for jumbo frames */ | |
1951 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400); | |
859a5887 | 1952 | } else { |
1da177e4 LT |
1953 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); |
1954 | } | |
1955 | ||
1956 | tg3_writephy(tp, MII_TG3_CTRL, phy9_orig); | |
1957 | ||
1958 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) { | |
1959 | reg32 &= ~0x3000; | |
1960 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
1961 | } else if (!err) | |
1962 | err = -EBUSY; | |
1963 | ||
1964 | return err; | |
1965 | } | |
1966 | ||
1967 | /* This will reset the tigon3 PHY if there is no valid | |
1968 | * link unless the FORCE argument is non-zero. | |
1969 | */ | |
1970 | static int tg3_phy_reset(struct tg3 *tp) | |
1971 | { | |
f833c4c1 | 1972 | u32 val, cpmuctrl; |
1da177e4 LT |
1973 | int err; |
1974 | ||
60189ddf | 1975 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
1976 | val = tr32(GRC_MISC_CFG); |
1977 | tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ); | |
1978 | udelay(40); | |
1979 | } | |
f833c4c1 MC |
1980 | err = tg3_readphy(tp, MII_BMSR, &val); |
1981 | err |= tg3_readphy(tp, MII_BMSR, &val); | |
1da177e4 LT |
1982 | if (err != 0) |
1983 | return -EBUSY; | |
1984 | ||
c8e1e82b MC |
1985 | if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) { |
1986 | netif_carrier_off(tp->dev); | |
1987 | tg3_link_report(tp); | |
1988 | } | |
1989 | ||
1da177e4 LT |
1990 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || |
1991 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
1992 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
1993 | err = tg3_phy_reset_5703_4_5(tp); | |
1994 | if (err) | |
1995 | return err; | |
1996 | goto out; | |
1997 | } | |
1998 | ||
b2a5c19c MC |
1999 | cpmuctrl = 0; |
2000 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
2001 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
2002 | cpmuctrl = tr32(TG3_CPMU_CTRL); | |
2003 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) | |
2004 | tw32(TG3_CPMU_CTRL, | |
2005 | cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY); | |
2006 | } | |
2007 | ||
1da177e4 LT |
2008 | err = tg3_bmcr_reset(tp); |
2009 | if (err) | |
2010 | return err; | |
2011 | ||
b2a5c19c | 2012 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) { |
f833c4c1 MC |
2013 | val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz; |
2014 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val); | |
b2a5c19c MC |
2015 | |
2016 | tw32(TG3_CPMU_CTRL, cpmuctrl); | |
2017 | } | |
2018 | ||
bcb37f6c MC |
2019 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2020 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2021 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2022 | if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) == | |
2023 | CPMU_LSPD_1000MB_MACCLK_12_5) { | |
2024 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2025 | udelay(40); | |
2026 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2027 | } | |
2028 | } | |
2029 | ||
a50d0796 MC |
2030 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
2031 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) && | |
f07e9af3 | 2032 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) |
ecf1410b MC |
2033 | return 0; |
2034 | ||
b2a5c19c MC |
2035 | tg3_phy_apply_otp(tp); |
2036 | ||
f07e9af3 | 2037 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
2038 | tg3_phy_toggle_apd(tp, true); |
2039 | else | |
2040 | tg3_phy_toggle_apd(tp, false); | |
2041 | ||
1da177e4 | 2042 | out: |
f07e9af3 | 2043 | if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) { |
1da177e4 | 2044 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); |
6ee7c0a0 MC |
2045 | tg3_phydsp_write(tp, 0x201f, 0x2aaa); |
2046 | tg3_phydsp_write(tp, 0x000a, 0x0323); | |
1da177e4 LT |
2047 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); |
2048 | } | |
f07e9af3 | 2049 | if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { |
f08aa1a8 MC |
2050 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); |
2051 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
1da177e4 | 2052 | } |
f07e9af3 | 2053 | if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { |
1da177e4 | 2054 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); |
6ee7c0a0 MC |
2055 | tg3_phydsp_write(tp, 0x000a, 0x310b); |
2056 | tg3_phydsp_write(tp, 0x201f, 0x9506); | |
2057 | tg3_phydsp_write(tp, 0x401f, 0x14e2); | |
1da177e4 | 2058 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); |
f07e9af3 | 2059 | } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { |
c424cb24 MC |
2060 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); |
2061 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
f07e9af3 | 2062 | if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { |
c1d2a196 MC |
2063 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); |
2064 | tg3_writephy(tp, MII_TG3_TEST1, | |
2065 | MII_TG3_TEST1_TRIM_EN | 0x4); | |
2066 | } else | |
2067 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); | |
c424cb24 MC |
2068 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); |
2069 | } | |
1da177e4 LT |
2070 | /* Set Extended packet length bit (bit 14) on all chips that */ |
2071 | /* support jumbo frames */ | |
79eb6904 | 2072 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
2073 | /* Cannot do read-modify-write on 5401 */ |
2074 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20); | |
8f666b07 | 2075 | } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { |
1da177e4 LT |
2076 | /* Set bit 14 with read-modify-write to preserve other bits */ |
2077 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) && | |
f833c4c1 MC |
2078 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val)) |
2079 | tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000); | |
1da177e4 LT |
2080 | } |
2081 | ||
2082 | /* Set phy register 0x10 bit 0 to high fifo elasticity to support | |
2083 | * jumbo frames transmission. | |
2084 | */ | |
8f666b07 | 2085 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { |
f833c4c1 | 2086 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val)) |
c6cdf436 | 2087 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
f833c4c1 | 2088 | val | MII_TG3_EXT_CTRL_FIFO_ELASTIC); |
1da177e4 LT |
2089 | } |
2090 | ||
715116a1 | 2091 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
715116a1 | 2092 | /* adjust output voltage */ |
535ef6e1 | 2093 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); |
715116a1 MC |
2094 | } |
2095 | ||
9ef8ca99 | 2096 | tg3_phy_toggle_automdix(tp, 1); |
1da177e4 LT |
2097 | tg3_phy_set_wirespeed(tp); |
2098 | return 0; | |
2099 | } | |
2100 | ||
2101 | static void tg3_frob_aux_power(struct tg3 *tp) | |
2102 | { | |
2103 | struct tg3 *tp_peer = tp; | |
2104 | ||
334355aa MC |
2105 | /* The GPIOs do something completely different on 57765. */ |
2106 | if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 || | |
a50d0796 | 2107 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
334355aa | 2108 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
1da177e4 LT |
2109 | return; |
2110 | ||
f6eb9b1f MC |
2111 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
2112 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 || | |
2113 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { | |
8c2dc7e1 MC |
2114 | struct net_device *dev_peer; |
2115 | ||
2116 | dev_peer = pci_get_drvdata(tp->pdev_peer); | |
bc1c7567 | 2117 | /* remove_one() may have been run on the peer. */ |
8c2dc7e1 | 2118 | if (!dev_peer) |
bc1c7567 MC |
2119 | tp_peer = tp; |
2120 | else | |
2121 | tp_peer = netdev_priv(dev_peer); | |
1da177e4 LT |
2122 | } |
2123 | ||
1da177e4 | 2124 | if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 || |
6921d201 MC |
2125 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 || |
2126 | (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 || | |
2127 | (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) { | |
1da177e4 LT |
2128 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
2129 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
b401e9e2 MC |
2130 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2131 | (GRC_LCLCTRL_GPIO_OE0 | | |
2132 | GRC_LCLCTRL_GPIO_OE1 | | |
2133 | GRC_LCLCTRL_GPIO_OE2 | | |
2134 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2135 | GRC_LCLCTRL_GPIO_OUTPUT1), | |
2136 | 100); | |
8d519ab2 MC |
2137 | } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
2138 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
5f0c4a3c MC |
2139 | /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ |
2140 | u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 | | |
2141 | GRC_LCLCTRL_GPIO_OE1 | | |
2142 | GRC_LCLCTRL_GPIO_OE2 | | |
2143 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2144 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2145 | tp->grc_local_ctrl; | |
2146 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
2147 | ||
2148 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2; | |
2149 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
2150 | ||
2151 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0; | |
2152 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
1da177e4 LT |
2153 | } else { |
2154 | u32 no_gpio2; | |
dc56b7d4 | 2155 | u32 grc_local_ctrl = 0; |
1da177e4 LT |
2156 | |
2157 | if (tp_peer != tp && | |
2158 | (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0) | |
2159 | return; | |
2160 | ||
dc56b7d4 MC |
2161 | /* Workaround to prevent overdrawing Amps. */ |
2162 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
2163 | ASIC_REV_5714) { | |
2164 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
b401e9e2 MC |
2165 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2166 | grc_local_ctrl, 100); | |
dc56b7d4 MC |
2167 | } |
2168 | ||
1da177e4 LT |
2169 | /* On 5753 and variants, GPIO2 cannot be used. */ |
2170 | no_gpio2 = tp->nic_sram_data_cfg & | |
2171 | NIC_SRAM_DATA_CFG_NO_GPIO2; | |
2172 | ||
dc56b7d4 | 2173 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | |
1da177e4 LT |
2174 | GRC_LCLCTRL_GPIO_OE1 | |
2175 | GRC_LCLCTRL_GPIO_OE2 | | |
2176 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2177 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
2178 | if (no_gpio2) { | |
2179 | grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 | | |
2180 | GRC_LCLCTRL_GPIO_OUTPUT2); | |
2181 | } | |
b401e9e2 MC |
2182 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2183 | grc_local_ctrl, 100); | |
1da177e4 LT |
2184 | |
2185 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0; | |
2186 | ||
b401e9e2 MC |
2187 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2188 | grc_local_ctrl, 100); | |
1da177e4 LT |
2189 | |
2190 | if (!no_gpio2) { | |
2191 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2; | |
b401e9e2 MC |
2192 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2193 | grc_local_ctrl, 100); | |
1da177e4 LT |
2194 | } |
2195 | } | |
2196 | } else { | |
2197 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
2198 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
2199 | if (tp_peer != tp && | |
2200 | (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0) | |
2201 | return; | |
2202 | ||
b401e9e2 MC |
2203 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2204 | (GRC_LCLCTRL_GPIO_OE1 | | |
2205 | GRC_LCLCTRL_GPIO_OUTPUT1), 100); | |
1da177e4 | 2206 | |
b401e9e2 MC |
2207 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2208 | GRC_LCLCTRL_GPIO_OE1, 100); | |
1da177e4 | 2209 | |
b401e9e2 MC |
2210 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2211 | (GRC_LCLCTRL_GPIO_OE1 | | |
2212 | GRC_LCLCTRL_GPIO_OUTPUT1), 100); | |
1da177e4 LT |
2213 | } |
2214 | } | |
2215 | } | |
2216 | ||
e8f3f6ca MC |
2217 | static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) |
2218 | { | |
2219 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) | |
2220 | return 1; | |
79eb6904 | 2221 | else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { |
e8f3f6ca MC |
2222 | if (speed != SPEED_10) |
2223 | return 1; | |
2224 | } else if (speed == SPEED_10) | |
2225 | return 1; | |
2226 | ||
2227 | return 0; | |
2228 | } | |
2229 | ||
1da177e4 LT |
2230 | static int tg3_setup_phy(struct tg3 *, int); |
2231 | ||
2232 | #define RESET_KIND_SHUTDOWN 0 | |
2233 | #define RESET_KIND_INIT 1 | |
2234 | #define RESET_KIND_SUSPEND 2 | |
2235 | ||
2236 | static void tg3_write_sig_post_reset(struct tg3 *, int); | |
2237 | static int tg3_halt_cpu(struct tg3 *, u32); | |
2238 | ||
0a459aac | 2239 | static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) |
15c3b696 | 2240 | { |
ce057f01 MC |
2241 | u32 val; |
2242 | ||
f07e9af3 | 2243 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
5129724a MC |
2244 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
2245 | u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
2246 | u32 serdes_cfg = tr32(MAC_SERDES_CFG); | |
2247 | ||
2248 | sg_dig_ctrl |= | |
2249 | SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET; | |
2250 | tw32(SG_DIG_CTRL, sg_dig_ctrl); | |
2251 | tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15)); | |
2252 | } | |
3f7045c1 | 2253 | return; |
5129724a | 2254 | } |
3f7045c1 | 2255 | |
60189ddf | 2256 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2257 | tg3_bmcr_reset(tp); |
2258 | val = tr32(GRC_MISC_CFG); | |
2259 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); | |
2260 | udelay(40); | |
2261 | return; | |
f07e9af3 | 2262 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
0e5f784c MC |
2263 | u32 phytest; |
2264 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
2265 | u32 phy; | |
2266 | ||
2267 | tg3_writephy(tp, MII_ADVERTISE, 0); | |
2268 | tg3_writephy(tp, MII_BMCR, | |
2269 | BMCR_ANENABLE | BMCR_ANRESTART); | |
2270 | ||
2271 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
2272 | phytest | MII_TG3_FET_SHADOW_EN); | |
2273 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { | |
2274 | phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD; | |
2275 | tg3_writephy(tp, | |
2276 | MII_TG3_FET_SHDW_AUXMODE4, | |
2277 | phy); | |
2278 | } | |
2279 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
2280 | } | |
2281 | return; | |
0a459aac | 2282 | } else if (do_low_power) { |
715116a1 MC |
2283 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
2284 | MII_TG3_EXT_CTRL_FORCE_LED_OFF); | |
0a459aac MC |
2285 | |
2286 | tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
2287 | MII_TG3_AUXCTL_SHDWSEL_PWRCTL | | |
2288 | MII_TG3_AUXCTL_PCTL_100TX_LPWR | | |
2289 | MII_TG3_AUXCTL_PCTL_SPR_ISOLATE | | |
2290 | MII_TG3_AUXCTL_PCTL_VREG_11V); | |
715116a1 | 2291 | } |
3f7045c1 | 2292 | |
15c3b696 MC |
2293 | /* The PHY should not be powered down on some chips because |
2294 | * of bugs. | |
2295 | */ | |
2296 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2297 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2298 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 && | |
f07e9af3 | 2299 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) |
15c3b696 | 2300 | return; |
ce057f01 | 2301 | |
bcb37f6c MC |
2302 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2303 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2304 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2305 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2306 | val |= CPMU_LSPD_1000MB_MACCLK_12_5; | |
2307 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2308 | } | |
2309 | ||
15c3b696 MC |
2310 | tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); |
2311 | } | |
2312 | ||
ffbcfed4 MC |
2313 | /* tp->lock is held. */ |
2314 | static int tg3_nvram_lock(struct tg3 *tp) | |
2315 | { | |
2316 | if (tp->tg3_flags & TG3_FLAG_NVRAM) { | |
2317 | int i; | |
2318 | ||
2319 | if (tp->nvram_lock_cnt == 0) { | |
2320 | tw32(NVRAM_SWARB, SWARB_REQ_SET1); | |
2321 | for (i = 0; i < 8000; i++) { | |
2322 | if (tr32(NVRAM_SWARB) & SWARB_GNT1) | |
2323 | break; | |
2324 | udelay(20); | |
2325 | } | |
2326 | if (i == 8000) { | |
2327 | tw32(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2328 | return -ENODEV; | |
2329 | } | |
2330 | } | |
2331 | tp->nvram_lock_cnt++; | |
2332 | } | |
2333 | return 0; | |
2334 | } | |
2335 | ||
2336 | /* tp->lock is held. */ | |
2337 | static void tg3_nvram_unlock(struct tg3 *tp) | |
2338 | { | |
2339 | if (tp->tg3_flags & TG3_FLAG_NVRAM) { | |
2340 | if (tp->nvram_lock_cnt > 0) | |
2341 | tp->nvram_lock_cnt--; | |
2342 | if (tp->nvram_lock_cnt == 0) | |
2343 | tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2344 | } | |
2345 | } | |
2346 | ||
2347 | /* tp->lock is held. */ | |
2348 | static void tg3_enable_nvram_access(struct tg3 *tp) | |
2349 | { | |
2350 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
f66a29b0 | 2351 | !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2352 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2353 | ||
2354 | tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); | |
2355 | } | |
2356 | } | |
2357 | ||
2358 | /* tp->lock is held. */ | |
2359 | static void tg3_disable_nvram_access(struct tg3 *tp) | |
2360 | { | |
2361 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
f66a29b0 | 2362 | !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2363 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2364 | ||
2365 | tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); | |
2366 | } | |
2367 | } | |
2368 | ||
2369 | static int tg3_nvram_read_using_eeprom(struct tg3 *tp, | |
2370 | u32 offset, u32 *val) | |
2371 | { | |
2372 | u32 tmp; | |
2373 | int i; | |
2374 | ||
2375 | if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0) | |
2376 | return -EINVAL; | |
2377 | ||
2378 | tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | | |
2379 | EEPROM_ADDR_DEVID_MASK | | |
2380 | EEPROM_ADDR_READ); | |
2381 | tw32(GRC_EEPROM_ADDR, | |
2382 | tmp | | |
2383 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
2384 | ((offset << EEPROM_ADDR_ADDR_SHIFT) & | |
2385 | EEPROM_ADDR_ADDR_MASK) | | |
2386 | EEPROM_ADDR_READ | EEPROM_ADDR_START); | |
2387 | ||
2388 | for (i = 0; i < 1000; i++) { | |
2389 | tmp = tr32(GRC_EEPROM_ADDR); | |
2390 | ||
2391 | if (tmp & EEPROM_ADDR_COMPLETE) | |
2392 | break; | |
2393 | msleep(1); | |
2394 | } | |
2395 | if (!(tmp & EEPROM_ADDR_COMPLETE)) | |
2396 | return -EBUSY; | |
2397 | ||
62cedd11 MC |
2398 | tmp = tr32(GRC_EEPROM_DATA); |
2399 | ||
2400 | /* | |
2401 | * The data will always be opposite the native endian | |
2402 | * format. Perform a blind byteswap to compensate. | |
2403 | */ | |
2404 | *val = swab32(tmp); | |
2405 | ||
ffbcfed4 MC |
2406 | return 0; |
2407 | } | |
2408 | ||
2409 | #define NVRAM_CMD_TIMEOUT 10000 | |
2410 | ||
2411 | static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) | |
2412 | { | |
2413 | int i; | |
2414 | ||
2415 | tw32(NVRAM_CMD, nvram_cmd); | |
2416 | for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { | |
2417 | udelay(10); | |
2418 | if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { | |
2419 | udelay(10); | |
2420 | break; | |
2421 | } | |
2422 | } | |
2423 | ||
2424 | if (i == NVRAM_CMD_TIMEOUT) | |
2425 | return -EBUSY; | |
2426 | ||
2427 | return 0; | |
2428 | } | |
2429 | ||
2430 | static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) | |
2431 | { | |
2432 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | |
2433 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | |
2434 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | |
2435 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | |
2436 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | |
2437 | ||
2438 | addr = ((addr / tp->nvram_pagesize) << | |
2439 | ATMEL_AT45DB0X1B_PAGE_POS) + | |
2440 | (addr % tp->nvram_pagesize); | |
2441 | ||
2442 | return addr; | |
2443 | } | |
2444 | ||
2445 | static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) | |
2446 | { | |
2447 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | |
2448 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | |
2449 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | |
2450 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | |
2451 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | |
2452 | ||
2453 | addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * | |
2454 | tp->nvram_pagesize) + | |
2455 | (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); | |
2456 | ||
2457 | return addr; | |
2458 | } | |
2459 | ||
e4f34110 MC |
2460 | /* NOTE: Data read in from NVRAM is byteswapped according to |
2461 | * the byteswapping settings for all other register accesses. | |
2462 | * tg3 devices are BE devices, so on a BE machine, the data | |
2463 | * returned will be exactly as it is seen in NVRAM. On a LE | |
2464 | * machine, the 32-bit value will be byteswapped. | |
2465 | */ | |
ffbcfed4 MC |
2466 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) |
2467 | { | |
2468 | int ret; | |
2469 | ||
2470 | if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) | |
2471 | return tg3_nvram_read_using_eeprom(tp, offset, val); | |
2472 | ||
2473 | offset = tg3_nvram_phys_addr(tp, offset); | |
2474 | ||
2475 | if (offset > NVRAM_ADDR_MSK) | |
2476 | return -EINVAL; | |
2477 | ||
2478 | ret = tg3_nvram_lock(tp); | |
2479 | if (ret) | |
2480 | return ret; | |
2481 | ||
2482 | tg3_enable_nvram_access(tp); | |
2483 | ||
2484 | tw32(NVRAM_ADDR, offset); | |
2485 | ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | | |
2486 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); | |
2487 | ||
2488 | if (ret == 0) | |
e4f34110 | 2489 | *val = tr32(NVRAM_RDDATA); |
ffbcfed4 MC |
2490 | |
2491 | tg3_disable_nvram_access(tp); | |
2492 | ||
2493 | tg3_nvram_unlock(tp); | |
2494 | ||
2495 | return ret; | |
2496 | } | |
2497 | ||
a9dc529d MC |
2498 | /* Ensures NVRAM data is in bytestream format. */ |
2499 | static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) | |
ffbcfed4 MC |
2500 | { |
2501 | u32 v; | |
a9dc529d | 2502 | int res = tg3_nvram_read(tp, offset, &v); |
ffbcfed4 | 2503 | if (!res) |
a9dc529d | 2504 | *val = cpu_to_be32(v); |
ffbcfed4 MC |
2505 | return res; |
2506 | } | |
2507 | ||
3f007891 MC |
2508 | /* tp->lock is held. */ |
2509 | static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) | |
2510 | { | |
2511 | u32 addr_high, addr_low; | |
2512 | int i; | |
2513 | ||
2514 | addr_high = ((tp->dev->dev_addr[0] << 8) | | |
2515 | tp->dev->dev_addr[1]); | |
2516 | addr_low = ((tp->dev->dev_addr[2] << 24) | | |
2517 | (tp->dev->dev_addr[3] << 16) | | |
2518 | (tp->dev->dev_addr[4] << 8) | | |
2519 | (tp->dev->dev_addr[5] << 0)); | |
2520 | for (i = 0; i < 4; i++) { | |
2521 | if (i == 1 && skip_mac_1) | |
2522 | continue; | |
2523 | tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high); | |
2524 | tw32(MAC_ADDR_0_LOW + (i * 8), addr_low); | |
2525 | } | |
2526 | ||
2527 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
2528 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
2529 | for (i = 0; i < 12; i++) { | |
2530 | tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high); | |
2531 | tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low); | |
2532 | } | |
2533 | } | |
2534 | ||
2535 | addr_high = (tp->dev->dev_addr[0] + | |
2536 | tp->dev->dev_addr[1] + | |
2537 | tp->dev->dev_addr[2] + | |
2538 | tp->dev->dev_addr[3] + | |
2539 | tp->dev->dev_addr[4] + | |
2540 | tp->dev->dev_addr[5]) & | |
2541 | TX_BACKOFF_SEED_MASK; | |
2542 | tw32(MAC_TX_BACKOFF_SEED, addr_high); | |
2543 | } | |
2544 | ||
c866b7ea | 2545 | static void tg3_enable_register_access(struct tg3 *tp) |
1da177e4 | 2546 | { |
c866b7ea RW |
2547 | /* |
2548 | * Make sure register accesses (indirect or otherwise) will function | |
2549 | * correctly. | |
1da177e4 LT |
2550 | */ |
2551 | pci_write_config_dword(tp->pdev, | |
c866b7ea RW |
2552 | TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); |
2553 | } | |
1da177e4 | 2554 | |
c866b7ea RW |
2555 | static int tg3_power_up(struct tg3 *tp) |
2556 | { | |
2557 | tg3_enable_register_access(tp); | |
8c6bda1a | 2558 | |
c866b7ea | 2559 | pci_set_power_state(tp->pdev, PCI_D0); |
1da177e4 | 2560 | |
c866b7ea RW |
2561 | /* Switch out of Vaux if it is a NIC */ |
2562 | if (tp->tg3_flags2 & TG3_FLG2_IS_NIC) | |
2563 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100); | |
1da177e4 | 2564 | |
c866b7ea RW |
2565 | return 0; |
2566 | } | |
1da177e4 | 2567 | |
c866b7ea RW |
2568 | static int tg3_power_down_prepare(struct tg3 *tp) |
2569 | { | |
2570 | u32 misc_host_ctrl; | |
2571 | bool device_should_wake, do_low_power; | |
2572 | ||
2573 | tg3_enable_register_access(tp); | |
5e7dfd0f MC |
2574 | |
2575 | /* Restore the CLKREQ setting. */ | |
2576 | if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) { | |
2577 | u16 lnkctl; | |
2578 | ||
2579 | pci_read_config_word(tp->pdev, | |
2580 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
2581 | &lnkctl); | |
2582 | lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
2583 | pci_write_config_word(tp->pdev, | |
2584 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
2585 | lnkctl); | |
2586 | } | |
2587 | ||
1da177e4 LT |
2588 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
2589 | tw32(TG3PCI_MISC_HOST_CTRL, | |
2590 | misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); | |
2591 | ||
c866b7ea | 2592 | device_should_wake = device_may_wakeup(&tp->pdev->dev) && |
05ac4cb7 MC |
2593 | (tp->tg3_flags & TG3_FLAG_WOL_ENABLE); |
2594 | ||
dd477003 | 2595 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
0a459aac | 2596 | do_low_power = false; |
f07e9af3 | 2597 | if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && |
80096068 | 2598 | !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
b02fd9e3 | 2599 | struct phy_device *phydev; |
0a459aac | 2600 | u32 phyid, advertising; |
b02fd9e3 | 2601 | |
3f0e3ad7 | 2602 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 2603 | |
80096068 | 2604 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; |
b02fd9e3 MC |
2605 | |
2606 | tp->link_config.orig_speed = phydev->speed; | |
2607 | tp->link_config.orig_duplex = phydev->duplex; | |
2608 | tp->link_config.orig_autoneg = phydev->autoneg; | |
2609 | tp->link_config.orig_advertising = phydev->advertising; | |
2610 | ||
2611 | advertising = ADVERTISED_TP | | |
2612 | ADVERTISED_Pause | | |
2613 | ADVERTISED_Autoneg | | |
2614 | ADVERTISED_10baseT_Half; | |
2615 | ||
2616 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
05ac4cb7 | 2617 | device_should_wake) { |
b02fd9e3 MC |
2618 | if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) |
2619 | advertising |= | |
2620 | ADVERTISED_100baseT_Half | | |
2621 | ADVERTISED_100baseT_Full | | |
2622 | ADVERTISED_10baseT_Full; | |
2623 | else | |
2624 | advertising |= ADVERTISED_10baseT_Full; | |
2625 | } | |
2626 | ||
2627 | phydev->advertising = advertising; | |
2628 | ||
2629 | phy_start_aneg(phydev); | |
0a459aac MC |
2630 | |
2631 | phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; | |
6a443a0f MC |
2632 | if (phyid != PHY_ID_BCMAC131) { |
2633 | phyid &= PHY_BCM_OUI_MASK; | |
2634 | if (phyid == PHY_BCM_OUI_1 || | |
2635 | phyid == PHY_BCM_OUI_2 || | |
2636 | phyid == PHY_BCM_OUI_3) | |
0a459aac MC |
2637 | do_low_power = true; |
2638 | } | |
b02fd9e3 | 2639 | } |
dd477003 | 2640 | } else { |
2023276e | 2641 | do_low_power = true; |
0a459aac | 2642 | |
80096068 MC |
2643 | if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
2644 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; | |
dd477003 MC |
2645 | tp->link_config.orig_speed = tp->link_config.speed; |
2646 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
2647 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
2648 | } | |
1da177e4 | 2649 | |
f07e9af3 | 2650 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
dd477003 MC |
2651 | tp->link_config.speed = SPEED_10; |
2652 | tp->link_config.duplex = DUPLEX_HALF; | |
2653 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
2654 | tg3_setup_phy(tp, 0); | |
2655 | } | |
1da177e4 LT |
2656 | } |
2657 | ||
b5d3772c MC |
2658 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
2659 | u32 val; | |
2660 | ||
2661 | val = tr32(GRC_VCPU_EXT_CTRL); | |
2662 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL); | |
2663 | } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { | |
6921d201 MC |
2664 | int i; |
2665 | u32 val; | |
2666 | ||
2667 | for (i = 0; i < 200; i++) { | |
2668 | tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); | |
2669 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
2670 | break; | |
2671 | msleep(1); | |
2672 | } | |
2673 | } | |
a85feb8c GZ |
2674 | if (tp->tg3_flags & TG3_FLAG_WOL_CAP) |
2675 | tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | | |
2676 | WOL_DRV_STATE_SHUTDOWN | | |
2677 | WOL_DRV_WOL | | |
2678 | WOL_SET_MAGIC_PKT); | |
6921d201 | 2679 | |
05ac4cb7 | 2680 | if (device_should_wake) { |
1da177e4 LT |
2681 | u32 mac_mode; |
2682 | ||
f07e9af3 | 2683 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
0a459aac | 2684 | if (do_low_power) { |
dd477003 MC |
2685 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a); |
2686 | udelay(40); | |
2687 | } | |
1da177e4 | 2688 | |
f07e9af3 | 2689 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
3f7045c1 MC |
2690 | mac_mode = MAC_MODE_PORT_MODE_GMII; |
2691 | else | |
2692 | mac_mode = MAC_MODE_PORT_MODE_MII; | |
1da177e4 | 2693 | |
e8f3f6ca MC |
2694 | mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; |
2695 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
2696 | ASIC_REV_5700) { | |
2697 | u32 speed = (tp->tg3_flags & | |
2698 | TG3_FLAG_WOL_SPEED_100MB) ? | |
2699 | SPEED_100 : SPEED_10; | |
2700 | if (tg3_5700_link_polarity(tp, speed)) | |
2701 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
2702 | else | |
2703 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
2704 | } | |
1da177e4 LT |
2705 | } else { |
2706 | mac_mode = MAC_MODE_PORT_MODE_TBI; | |
2707 | } | |
2708 | ||
cbf46853 | 2709 | if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) |
1da177e4 LT |
2710 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
2711 | ||
05ac4cb7 MC |
2712 | mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; |
2713 | if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && | |
2714 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) && | |
2715 | ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
2716 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))) | |
2717 | mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL; | |
1da177e4 | 2718 | |
d2394e6b MC |
2719 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
2720 | mac_mode |= MAC_MODE_APE_TX_EN | | |
2721 | MAC_MODE_APE_RX_EN | | |
2722 | MAC_MODE_TDE_ENABLE; | |
3bda1258 | 2723 | |
1da177e4 LT |
2724 | tw32_f(MAC_MODE, mac_mode); |
2725 | udelay(100); | |
2726 | ||
2727 | tw32_f(MAC_RX_MODE, RX_MODE_ENABLE); | |
2728 | udelay(10); | |
2729 | } | |
2730 | ||
2731 | if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) && | |
2732 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2733 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
2734 | u32 base_val; | |
2735 | ||
2736 | base_val = tp->pci_clock_ctrl; | |
2737 | base_val |= (CLOCK_CTRL_RXCLK_DISABLE | | |
2738 | CLOCK_CTRL_TXCLK_DISABLE); | |
2739 | ||
b401e9e2 MC |
2740 | tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK | |
2741 | CLOCK_CTRL_PWRDOWN_PLL133, 40); | |
d7b0a857 | 2742 | } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || |
795d01c5 | 2743 | (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || |
d7b0a857 | 2744 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) { |
4cf78e4f | 2745 | /* do nothing */ |
85e94ced | 2746 | } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && |
1da177e4 LT |
2747 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) { |
2748 | u32 newbits1, newbits2; | |
2749 | ||
2750 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2751 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2752 | newbits1 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2753 | CLOCK_CTRL_TXCLK_DISABLE | | |
2754 | CLOCK_CTRL_ALTCLK); | |
2755 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
2756 | } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
2757 | newbits1 = CLOCK_CTRL_625_CORE; | |
2758 | newbits2 = newbits1 | CLOCK_CTRL_ALTCLK; | |
2759 | } else { | |
2760 | newbits1 = CLOCK_CTRL_ALTCLK; | |
2761 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
2762 | } | |
2763 | ||
b401e9e2 MC |
2764 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, |
2765 | 40); | |
1da177e4 | 2766 | |
b401e9e2 MC |
2767 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, |
2768 | 40); | |
1da177e4 LT |
2769 | |
2770 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
2771 | u32 newbits3; | |
2772 | ||
2773 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2774 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2775 | newbits3 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2776 | CLOCK_CTRL_TXCLK_DISABLE | | |
2777 | CLOCK_CTRL_44MHZ_CORE); | |
2778 | } else { | |
2779 | newbits3 = CLOCK_CTRL_44MHZ_CORE; | |
2780 | } | |
2781 | ||
b401e9e2 MC |
2782 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
2783 | tp->pci_clock_ctrl | newbits3, 40); | |
1da177e4 LT |
2784 | } |
2785 | } | |
2786 | ||
05ac4cb7 | 2787 | if (!(device_should_wake) && |
22435849 | 2788 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) |
0a459aac | 2789 | tg3_power_down_phy(tp, do_low_power); |
6921d201 | 2790 | |
1da177e4 LT |
2791 | tg3_frob_aux_power(tp); |
2792 | ||
2793 | /* Workaround for unstable PLL clock */ | |
2794 | if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || | |
2795 | (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) { | |
2796 | u32 val = tr32(0x7d00); | |
2797 | ||
2798 | val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); | |
2799 | tw32(0x7d00, val); | |
6921d201 | 2800 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { |
ec41c7df MC |
2801 | int err; |
2802 | ||
2803 | err = tg3_nvram_lock(tp); | |
1da177e4 | 2804 | tg3_halt_cpu(tp, RX_CPU_BASE); |
ec41c7df MC |
2805 | if (!err) |
2806 | tg3_nvram_unlock(tp); | |
6921d201 | 2807 | } |
1da177e4 LT |
2808 | } |
2809 | ||
bbadf503 MC |
2810 | tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); |
2811 | ||
c866b7ea RW |
2812 | return 0; |
2813 | } | |
12dac075 | 2814 | |
c866b7ea RW |
2815 | static void tg3_power_down(struct tg3 *tp) |
2816 | { | |
2817 | tg3_power_down_prepare(tp); | |
1da177e4 | 2818 | |
c866b7ea RW |
2819 | pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE); |
2820 | pci_set_power_state(tp->pdev, PCI_D3hot); | |
1da177e4 LT |
2821 | } |
2822 | ||
1da177e4 LT |
2823 | static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex) |
2824 | { | |
2825 | switch (val & MII_TG3_AUX_STAT_SPDMASK) { | |
2826 | case MII_TG3_AUX_STAT_10HALF: | |
2827 | *speed = SPEED_10; | |
2828 | *duplex = DUPLEX_HALF; | |
2829 | break; | |
2830 | ||
2831 | case MII_TG3_AUX_STAT_10FULL: | |
2832 | *speed = SPEED_10; | |
2833 | *duplex = DUPLEX_FULL; | |
2834 | break; | |
2835 | ||
2836 | case MII_TG3_AUX_STAT_100HALF: | |
2837 | *speed = SPEED_100; | |
2838 | *duplex = DUPLEX_HALF; | |
2839 | break; | |
2840 | ||
2841 | case MII_TG3_AUX_STAT_100FULL: | |
2842 | *speed = SPEED_100; | |
2843 | *duplex = DUPLEX_FULL; | |
2844 | break; | |
2845 | ||
2846 | case MII_TG3_AUX_STAT_1000HALF: | |
2847 | *speed = SPEED_1000; | |
2848 | *duplex = DUPLEX_HALF; | |
2849 | break; | |
2850 | ||
2851 | case MII_TG3_AUX_STAT_1000FULL: | |
2852 | *speed = SPEED_1000; | |
2853 | *duplex = DUPLEX_FULL; | |
2854 | break; | |
2855 | ||
2856 | default: | |
f07e9af3 | 2857 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
715116a1 MC |
2858 | *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 : |
2859 | SPEED_10; | |
2860 | *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL : | |
2861 | DUPLEX_HALF; | |
2862 | break; | |
2863 | } | |
1da177e4 LT |
2864 | *speed = SPEED_INVALID; |
2865 | *duplex = DUPLEX_INVALID; | |
2866 | break; | |
855e1111 | 2867 | } |
1da177e4 LT |
2868 | } |
2869 | ||
2870 | static void tg3_phy_copper_begin(struct tg3 *tp) | |
2871 | { | |
2872 | u32 new_adv; | |
2873 | int i; | |
2874 | ||
80096068 | 2875 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
1da177e4 LT |
2876 | /* Entering low power mode. Disable gigabit and |
2877 | * 100baseT advertisements. | |
2878 | */ | |
2879 | tg3_writephy(tp, MII_TG3_CTRL, 0); | |
2880 | ||
2881 | new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL | | |
2882 | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
2883 | if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) | |
2884 | new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL); | |
2885 | ||
2886 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
2887 | } else if (tp->link_config.speed == SPEED_INVALID) { | |
f07e9af3 | 2888 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) |
1da177e4 LT |
2889 | tp->link_config.advertising &= |
2890 | ~(ADVERTISED_1000baseT_Half | | |
2891 | ADVERTISED_1000baseT_Full); | |
2892 | ||
ba4d07a8 | 2893 | new_adv = ADVERTISE_CSMA; |
1da177e4 LT |
2894 | if (tp->link_config.advertising & ADVERTISED_10baseT_Half) |
2895 | new_adv |= ADVERTISE_10HALF; | |
2896 | if (tp->link_config.advertising & ADVERTISED_10baseT_Full) | |
2897 | new_adv |= ADVERTISE_10FULL; | |
2898 | if (tp->link_config.advertising & ADVERTISED_100baseT_Half) | |
2899 | new_adv |= ADVERTISE_100HALF; | |
2900 | if (tp->link_config.advertising & ADVERTISED_100baseT_Full) | |
2901 | new_adv |= ADVERTISE_100FULL; | |
ba4d07a8 MC |
2902 | |
2903 | new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
2904 | ||
1da177e4 LT |
2905 | tg3_writephy(tp, MII_ADVERTISE, new_adv); |
2906 | ||
2907 | if (tp->link_config.advertising & | |
2908 | (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) { | |
2909 | new_adv = 0; | |
2910 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) | |
2911 | new_adv |= MII_TG3_CTRL_ADV_1000_HALF; | |
2912 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) | |
2913 | new_adv |= MII_TG3_CTRL_ADV_1000_FULL; | |
f07e9af3 | 2914 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) && |
1da177e4 LT |
2915 | (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || |
2916 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) | |
2917 | new_adv |= (MII_TG3_CTRL_AS_MASTER | | |
2918 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
2919 | tg3_writephy(tp, MII_TG3_CTRL, new_adv); | |
2920 | } else { | |
2921 | tg3_writephy(tp, MII_TG3_CTRL, 0); | |
2922 | } | |
2923 | } else { | |
ba4d07a8 MC |
2924 | new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); |
2925 | new_adv |= ADVERTISE_CSMA; | |
2926 | ||
1da177e4 LT |
2927 | /* Asking for a specific link mode. */ |
2928 | if (tp->link_config.speed == SPEED_1000) { | |
1da177e4 LT |
2929 | tg3_writephy(tp, MII_ADVERTISE, new_adv); |
2930 | ||
2931 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2932 | new_adv = MII_TG3_CTRL_ADV_1000_FULL; | |
2933 | else | |
2934 | new_adv = MII_TG3_CTRL_ADV_1000_HALF; | |
2935 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
2936 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
2937 | new_adv |= (MII_TG3_CTRL_AS_MASTER | | |
2938 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
1da177e4 | 2939 | } else { |
1da177e4 LT |
2940 | if (tp->link_config.speed == SPEED_100) { |
2941 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2942 | new_adv |= ADVERTISE_100FULL; | |
2943 | else | |
2944 | new_adv |= ADVERTISE_100HALF; | |
2945 | } else { | |
2946 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2947 | new_adv |= ADVERTISE_10FULL; | |
2948 | else | |
2949 | new_adv |= ADVERTISE_10HALF; | |
2950 | } | |
2951 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
ba4d07a8 MC |
2952 | |
2953 | new_adv = 0; | |
1da177e4 | 2954 | } |
ba4d07a8 MC |
2955 | |
2956 | tg3_writephy(tp, MII_TG3_CTRL, new_adv); | |
1da177e4 LT |
2957 | } |
2958 | ||
52b02d04 | 2959 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) { |
a6b68dab | 2960 | u32 val; |
52b02d04 MC |
2961 | |
2962 | tw32(TG3_CPMU_EEE_MODE, | |
2963 | tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
2964 | ||
2965 | /* Enable SM_DSP clock and tx 6dB coding. */ | |
2966 | val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
2967 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | | |
2968 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
2969 | tg3_writephy(tp, MII_TG3_AUX_CTRL, val); | |
2970 | ||
2971 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
2972 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) && | |
2973 | !tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) | |
2974 | tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, | |
2975 | val | MII_TG3_DSP_CH34TP2_HIBW01); | |
2976 | ||
a6b68dab | 2977 | val = 0; |
52b02d04 MC |
2978 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { |
2979 | /* Advertise 100-BaseTX EEE ability */ | |
2980 | if (tp->link_config.advertising & | |
3110f5f5 MC |
2981 | ADVERTISED_100baseT_Full) |
2982 | val |= MDIO_AN_EEE_ADV_100TX; | |
52b02d04 MC |
2983 | /* Advertise 1000-BaseT EEE ability */ |
2984 | if (tp->link_config.advertising & | |
3110f5f5 MC |
2985 | ADVERTISED_1000baseT_Full) |
2986 | val |= MDIO_AN_EEE_ADV_1000T; | |
52b02d04 | 2987 | } |
3110f5f5 | 2988 | tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); |
52b02d04 MC |
2989 | |
2990 | /* Turn off SM_DSP clock. */ | |
2991 | val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
2992 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
2993 | tg3_writephy(tp, MII_TG3_AUX_CTRL, val); | |
2994 | } | |
2995 | ||
1da177e4 LT |
2996 | if (tp->link_config.autoneg == AUTONEG_DISABLE && |
2997 | tp->link_config.speed != SPEED_INVALID) { | |
2998 | u32 bmcr, orig_bmcr; | |
2999 | ||
3000 | tp->link_config.active_speed = tp->link_config.speed; | |
3001 | tp->link_config.active_duplex = tp->link_config.duplex; | |
3002 | ||
3003 | bmcr = 0; | |
3004 | switch (tp->link_config.speed) { | |
3005 | default: | |
3006 | case SPEED_10: | |
3007 | break; | |
3008 | ||
3009 | case SPEED_100: | |
3010 | bmcr |= BMCR_SPEED100; | |
3011 | break; | |
3012 | ||
3013 | case SPEED_1000: | |
3014 | bmcr |= TG3_BMCR_SPEED1000; | |
3015 | break; | |
855e1111 | 3016 | } |
1da177e4 LT |
3017 | |
3018 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3019 | bmcr |= BMCR_FULLDPLX; | |
3020 | ||
3021 | if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && | |
3022 | (bmcr != orig_bmcr)) { | |
3023 | tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); | |
3024 | for (i = 0; i < 1500; i++) { | |
3025 | u32 tmp; | |
3026 | ||
3027 | udelay(10); | |
3028 | if (tg3_readphy(tp, MII_BMSR, &tmp) || | |
3029 | tg3_readphy(tp, MII_BMSR, &tmp)) | |
3030 | continue; | |
3031 | if (!(tmp & BMSR_LSTATUS)) { | |
3032 | udelay(40); | |
3033 | break; | |
3034 | } | |
3035 | } | |
3036 | tg3_writephy(tp, MII_BMCR, bmcr); | |
3037 | udelay(40); | |
3038 | } | |
3039 | } else { | |
3040 | tg3_writephy(tp, MII_BMCR, | |
3041 | BMCR_ANENABLE | BMCR_ANRESTART); | |
3042 | } | |
3043 | } | |
3044 | ||
3045 | static int tg3_init_5401phy_dsp(struct tg3 *tp) | |
3046 | { | |
3047 | int err; | |
3048 | ||
3049 | /* Turn off tap power management. */ | |
3050 | /* Set Extended packet length bit */ | |
3051 | err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20); | |
3052 | ||
6ee7c0a0 MC |
3053 | err |= tg3_phydsp_write(tp, 0x0012, 0x1804); |
3054 | err |= tg3_phydsp_write(tp, 0x0013, 0x1204); | |
3055 | err |= tg3_phydsp_write(tp, 0x8006, 0x0132); | |
3056 | err |= tg3_phydsp_write(tp, 0x8006, 0x0232); | |
3057 | err |= tg3_phydsp_write(tp, 0x201f, 0x0a20); | |
1da177e4 LT |
3058 | |
3059 | udelay(40); | |
3060 | ||
3061 | return err; | |
3062 | } | |
3063 | ||
3600d918 | 3064 | static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask) |
1da177e4 | 3065 | { |
3600d918 MC |
3066 | u32 adv_reg, all_mask = 0; |
3067 | ||
3068 | if (mask & ADVERTISED_10baseT_Half) | |
3069 | all_mask |= ADVERTISE_10HALF; | |
3070 | if (mask & ADVERTISED_10baseT_Full) | |
3071 | all_mask |= ADVERTISE_10FULL; | |
3072 | if (mask & ADVERTISED_100baseT_Half) | |
3073 | all_mask |= ADVERTISE_100HALF; | |
3074 | if (mask & ADVERTISED_100baseT_Full) | |
3075 | all_mask |= ADVERTISE_100FULL; | |
1da177e4 LT |
3076 | |
3077 | if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg)) | |
3078 | return 0; | |
3079 | ||
1da177e4 LT |
3080 | if ((adv_reg & all_mask) != all_mask) |
3081 | return 0; | |
f07e9af3 | 3082 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
1da177e4 LT |
3083 | u32 tg3_ctrl; |
3084 | ||
3600d918 MC |
3085 | all_mask = 0; |
3086 | if (mask & ADVERTISED_1000baseT_Half) | |
3087 | all_mask |= ADVERTISE_1000HALF; | |
3088 | if (mask & ADVERTISED_1000baseT_Full) | |
3089 | all_mask |= ADVERTISE_1000FULL; | |
3090 | ||
1da177e4 LT |
3091 | if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl)) |
3092 | return 0; | |
3093 | ||
1da177e4 LT |
3094 | if ((tg3_ctrl & all_mask) != all_mask) |
3095 | return 0; | |
3096 | } | |
3097 | return 1; | |
3098 | } | |
3099 | ||
ef167e27 MC |
3100 | static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv) |
3101 | { | |
3102 | u32 curadv, reqadv; | |
3103 | ||
3104 | if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) | |
3105 | return 1; | |
3106 | ||
3107 | curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); | |
3108 | reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
3109 | ||
3110 | if (tp->link_config.active_duplex == DUPLEX_FULL) { | |
3111 | if (curadv != reqadv) | |
3112 | return 0; | |
3113 | ||
3114 | if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) | |
3115 | tg3_readphy(tp, MII_LPA, rmtadv); | |
3116 | } else { | |
3117 | /* Reprogram the advertisement register, even if it | |
3118 | * does not affect the current link. If the link | |
3119 | * gets renegotiated in the future, we can save an | |
3120 | * additional renegotiation cycle by advertising | |
3121 | * it correctly in the first place. | |
3122 | */ | |
3123 | if (curadv != reqadv) { | |
3124 | *lcladv &= ~(ADVERTISE_PAUSE_CAP | | |
3125 | ADVERTISE_PAUSE_ASYM); | |
3126 | tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv); | |
3127 | } | |
3128 | } | |
3129 | ||
3130 | return 1; | |
3131 | } | |
3132 | ||
1da177e4 LT |
3133 | static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) |
3134 | { | |
3135 | int current_link_up; | |
f833c4c1 | 3136 | u32 bmsr, val; |
ef167e27 | 3137 | u32 lcl_adv, rmt_adv; |
1da177e4 LT |
3138 | u16 current_speed; |
3139 | u8 current_duplex; | |
3140 | int i, err; | |
3141 | ||
3142 | tw32(MAC_EVENT, 0); | |
3143 | ||
3144 | tw32_f(MAC_STATUS, | |
3145 | (MAC_STATUS_SYNC_CHANGED | | |
3146 | MAC_STATUS_CFG_CHANGED | | |
3147 | MAC_STATUS_MI_COMPLETION | | |
3148 | MAC_STATUS_LNKSTATE_CHANGED)); | |
3149 | udelay(40); | |
3150 | ||
8ef21428 MC |
3151 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
3152 | tw32_f(MAC_MI_MODE, | |
3153 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
3154 | udelay(80); | |
3155 | } | |
1da177e4 LT |
3156 | |
3157 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02); | |
3158 | ||
3159 | /* Some third-party PHYs need to be reset on link going | |
3160 | * down. | |
3161 | */ | |
3162 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
3163 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
3164 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
3165 | netif_carrier_ok(tp->dev)) { | |
3166 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3167 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3168 | !(bmsr & BMSR_LSTATUS)) | |
3169 | force_reset = 1; | |
3170 | } | |
3171 | if (force_reset) | |
3172 | tg3_phy_reset(tp); | |
3173 | ||
79eb6904 | 3174 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
3175 | tg3_readphy(tp, MII_BMSR, &bmsr); |
3176 | if (tg3_readphy(tp, MII_BMSR, &bmsr) || | |
3177 | !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) | |
3178 | bmsr = 0; | |
3179 | ||
3180 | if (!(bmsr & BMSR_LSTATUS)) { | |
3181 | err = tg3_init_5401phy_dsp(tp); | |
3182 | if (err) | |
3183 | return err; | |
3184 | ||
3185 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3186 | for (i = 0; i < 1000; i++) { | |
3187 | udelay(10); | |
3188 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3189 | (bmsr & BMSR_LSTATUS)) { | |
3190 | udelay(40); | |
3191 | break; | |
3192 | } | |
3193 | } | |
3194 | ||
79eb6904 MC |
3195 | if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == |
3196 | TG3_PHY_REV_BCM5401_B0 && | |
1da177e4 LT |
3197 | !(bmsr & BMSR_LSTATUS) && |
3198 | tp->link_config.active_speed == SPEED_1000) { | |
3199 | err = tg3_phy_reset(tp); | |
3200 | if (!err) | |
3201 | err = tg3_init_5401phy_dsp(tp); | |
3202 | if (err) | |
3203 | return err; | |
3204 | } | |
3205 | } | |
3206 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
3207 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { | |
3208 | /* 5701 {A0,B0} CRC bug workaround */ | |
3209 | tg3_writephy(tp, 0x15, 0x0a75); | |
f08aa1a8 MC |
3210 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); |
3211 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
3212 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); | |
1da177e4 LT |
3213 | } |
3214 | ||
3215 | /* Clear pending interrupts... */ | |
f833c4c1 MC |
3216 | tg3_readphy(tp, MII_TG3_ISTAT, &val); |
3217 | tg3_readphy(tp, MII_TG3_ISTAT, &val); | |
1da177e4 | 3218 | |
f07e9af3 | 3219 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) |
1da177e4 | 3220 | tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); |
f07e9af3 | 3221 | else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) |
1da177e4 LT |
3222 | tg3_writephy(tp, MII_TG3_IMASK, ~0); |
3223 | ||
3224 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3225 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3226 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) | |
3227 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
3228 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
3229 | else | |
3230 | tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); | |
3231 | } | |
3232 | ||
3233 | current_link_up = 0; | |
3234 | current_speed = SPEED_INVALID; | |
3235 | current_duplex = DUPLEX_INVALID; | |
3236 | ||
f07e9af3 | 3237 | if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { |
1da177e4 LT |
3238 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007); |
3239 | tg3_readphy(tp, MII_TG3_AUX_CTRL, &val); | |
3240 | if (!(val & (1 << 10))) { | |
3241 | val |= (1 << 10); | |
3242 | tg3_writephy(tp, MII_TG3_AUX_CTRL, val); | |
3243 | goto relink; | |
3244 | } | |
3245 | } | |
3246 | ||
3247 | bmsr = 0; | |
3248 | for (i = 0; i < 100; i++) { | |
3249 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3250 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3251 | (bmsr & BMSR_LSTATUS)) | |
3252 | break; | |
3253 | udelay(40); | |
3254 | } | |
3255 | ||
3256 | if (bmsr & BMSR_LSTATUS) { | |
3257 | u32 aux_stat, bmcr; | |
3258 | ||
3259 | tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); | |
3260 | for (i = 0; i < 2000; i++) { | |
3261 | udelay(10); | |
3262 | if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && | |
3263 | aux_stat) | |
3264 | break; | |
3265 | } | |
3266 | ||
3267 | tg3_aux_stat_to_speed_duplex(tp, aux_stat, | |
3268 | ¤t_speed, | |
3269 | ¤t_duplex); | |
3270 | ||
3271 | bmcr = 0; | |
3272 | for (i = 0; i < 200; i++) { | |
3273 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
3274 | if (tg3_readphy(tp, MII_BMCR, &bmcr)) | |
3275 | continue; | |
3276 | if (bmcr && bmcr != 0x7fff) | |
3277 | break; | |
3278 | udelay(10); | |
3279 | } | |
3280 | ||
ef167e27 MC |
3281 | lcl_adv = 0; |
3282 | rmt_adv = 0; | |
1da177e4 | 3283 | |
ef167e27 MC |
3284 | tp->link_config.active_speed = current_speed; |
3285 | tp->link_config.active_duplex = current_duplex; | |
3286 | ||
3287 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
3288 | if ((bmcr & BMCR_ANENABLE) && | |
3289 | tg3_copper_is_advertising_all(tp, | |
3290 | tp->link_config.advertising)) { | |
3291 | if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv, | |
3292 | &rmt_adv)) | |
3293 | current_link_up = 1; | |
1da177e4 LT |
3294 | } |
3295 | } else { | |
3296 | if (!(bmcr & BMCR_ANENABLE) && | |
3297 | tp->link_config.speed == current_speed && | |
ef167e27 MC |
3298 | tp->link_config.duplex == current_duplex && |
3299 | tp->link_config.flowctrl == | |
3300 | tp->link_config.active_flowctrl) { | |
1da177e4 | 3301 | current_link_up = 1; |
1da177e4 LT |
3302 | } |
3303 | } | |
3304 | ||
ef167e27 MC |
3305 | if (current_link_up == 1 && |
3306 | tp->link_config.active_duplex == DUPLEX_FULL) | |
3307 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1da177e4 LT |
3308 | } |
3309 | ||
1da177e4 | 3310 | relink: |
80096068 | 3311 | if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
1da177e4 LT |
3312 | tg3_phy_copper_begin(tp); |
3313 | ||
f833c4c1 MC |
3314 | tg3_readphy(tp, MII_BMSR, &bmsr); |
3315 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3316 | (bmsr & BMSR_LSTATUS)) | |
1da177e4 LT |
3317 | current_link_up = 1; |
3318 | } | |
3319 | ||
3320 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; | |
3321 | if (current_link_up == 1) { | |
3322 | if (tp->link_config.active_speed == SPEED_100 || | |
3323 | tp->link_config.active_speed == SPEED_10) | |
3324 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
3325 | else | |
3326 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
f07e9af3 | 3327 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) |
7f97a4bd MC |
3328 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; |
3329 | else | |
1da177e4 LT |
3330 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
3331 | ||
3332 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
3333 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
3334 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
3335 | ||
1da177e4 | 3336 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
e8f3f6ca MC |
3337 | if (current_link_up == 1 && |
3338 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) | |
1da177e4 | 3339 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; |
e8f3f6ca MC |
3340 | else |
3341 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
3342 | } |
3343 | ||
3344 | /* ??? Without this setting Netgear GA302T PHY does not | |
3345 | * ??? send/receive packets... | |
3346 | */ | |
79eb6904 | 3347 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && |
1da177e4 LT |
3348 | tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { |
3349 | tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; | |
3350 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
3351 | udelay(80); | |
3352 | } | |
3353 | ||
3354 | tw32_f(MAC_MODE, tp->mac_mode); | |
3355 | udelay(40); | |
3356 | ||
52b02d04 MC |
3357 | tg3_phy_eee_adjust(tp, current_link_up); |
3358 | ||
1da177e4 LT |
3359 | if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) { |
3360 | /* Polled via timer. */ | |
3361 | tw32_f(MAC_EVENT, 0); | |
3362 | } else { | |
3363 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3364 | } | |
3365 | udelay(40); | |
3366 | ||
3367 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && | |
3368 | current_link_up == 1 && | |
3369 | tp->link_config.active_speed == SPEED_1000 && | |
3370 | ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) || | |
3371 | (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) { | |
3372 | udelay(120); | |
3373 | tw32_f(MAC_STATUS, | |
3374 | (MAC_STATUS_SYNC_CHANGED | | |
3375 | MAC_STATUS_CFG_CHANGED)); | |
3376 | udelay(40); | |
3377 | tg3_write_mem(tp, | |
3378 | NIC_SRAM_FIRMWARE_MBOX, | |
3379 | NIC_SRAM_FIRMWARE_MBOX_MAGIC2); | |
3380 | } | |
3381 | ||
5e7dfd0f MC |
3382 | /* Prevent send BD corruption. */ |
3383 | if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) { | |
3384 | u16 oldlnkctl, newlnkctl; | |
3385 | ||
3386 | pci_read_config_word(tp->pdev, | |
3387 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
3388 | &oldlnkctl); | |
3389 | if (tp->link_config.active_speed == SPEED_100 || | |
3390 | tp->link_config.active_speed == SPEED_10) | |
3391 | newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
3392 | else | |
3393 | newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN; | |
3394 | if (newlnkctl != oldlnkctl) | |
3395 | pci_write_config_word(tp->pdev, | |
3396 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
3397 | newlnkctl); | |
3398 | } | |
3399 | ||
1da177e4 LT |
3400 | if (current_link_up != netif_carrier_ok(tp->dev)) { |
3401 | if (current_link_up) | |
3402 | netif_carrier_on(tp->dev); | |
3403 | else | |
3404 | netif_carrier_off(tp->dev); | |
3405 | tg3_link_report(tp); | |
3406 | } | |
3407 | ||
3408 | return 0; | |
3409 | } | |
3410 | ||
3411 | struct tg3_fiber_aneginfo { | |
3412 | int state; | |
3413 | #define ANEG_STATE_UNKNOWN 0 | |
3414 | #define ANEG_STATE_AN_ENABLE 1 | |
3415 | #define ANEG_STATE_RESTART_INIT 2 | |
3416 | #define ANEG_STATE_RESTART 3 | |
3417 | #define ANEG_STATE_DISABLE_LINK_OK 4 | |
3418 | #define ANEG_STATE_ABILITY_DETECT_INIT 5 | |
3419 | #define ANEG_STATE_ABILITY_DETECT 6 | |
3420 | #define ANEG_STATE_ACK_DETECT_INIT 7 | |
3421 | #define ANEG_STATE_ACK_DETECT 8 | |
3422 | #define ANEG_STATE_COMPLETE_ACK_INIT 9 | |
3423 | #define ANEG_STATE_COMPLETE_ACK 10 | |
3424 | #define ANEG_STATE_IDLE_DETECT_INIT 11 | |
3425 | #define ANEG_STATE_IDLE_DETECT 12 | |
3426 | #define ANEG_STATE_LINK_OK 13 | |
3427 | #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14 | |
3428 | #define ANEG_STATE_NEXT_PAGE_WAIT 15 | |
3429 | ||
3430 | u32 flags; | |
3431 | #define MR_AN_ENABLE 0x00000001 | |
3432 | #define MR_RESTART_AN 0x00000002 | |
3433 | #define MR_AN_COMPLETE 0x00000004 | |
3434 | #define MR_PAGE_RX 0x00000008 | |
3435 | #define MR_NP_LOADED 0x00000010 | |
3436 | #define MR_TOGGLE_TX 0x00000020 | |
3437 | #define MR_LP_ADV_FULL_DUPLEX 0x00000040 | |
3438 | #define MR_LP_ADV_HALF_DUPLEX 0x00000080 | |
3439 | #define MR_LP_ADV_SYM_PAUSE 0x00000100 | |
3440 | #define MR_LP_ADV_ASYM_PAUSE 0x00000200 | |
3441 | #define MR_LP_ADV_REMOTE_FAULT1 0x00000400 | |
3442 | #define MR_LP_ADV_REMOTE_FAULT2 0x00000800 | |
3443 | #define MR_LP_ADV_NEXT_PAGE 0x00001000 | |
3444 | #define MR_TOGGLE_RX 0x00002000 | |
3445 | #define MR_NP_RX 0x00004000 | |
3446 | ||
3447 | #define MR_LINK_OK 0x80000000 | |
3448 | ||
3449 | unsigned long link_time, cur_time; | |
3450 | ||
3451 | u32 ability_match_cfg; | |
3452 | int ability_match_count; | |
3453 | ||
3454 | char ability_match, idle_match, ack_match; | |
3455 | ||
3456 | u32 txconfig, rxconfig; | |
3457 | #define ANEG_CFG_NP 0x00000080 | |
3458 | #define ANEG_CFG_ACK 0x00000040 | |
3459 | #define ANEG_CFG_RF2 0x00000020 | |
3460 | #define ANEG_CFG_RF1 0x00000010 | |
3461 | #define ANEG_CFG_PS2 0x00000001 | |
3462 | #define ANEG_CFG_PS1 0x00008000 | |
3463 | #define ANEG_CFG_HD 0x00004000 | |
3464 | #define ANEG_CFG_FD 0x00002000 | |
3465 | #define ANEG_CFG_INVAL 0x00001f06 | |
3466 | ||
3467 | }; | |
3468 | #define ANEG_OK 0 | |
3469 | #define ANEG_DONE 1 | |
3470 | #define ANEG_TIMER_ENAB 2 | |
3471 | #define ANEG_FAILED -1 | |
3472 | ||
3473 | #define ANEG_STATE_SETTLE_TIME 10000 | |
3474 | ||
3475 | static int tg3_fiber_aneg_smachine(struct tg3 *tp, | |
3476 | struct tg3_fiber_aneginfo *ap) | |
3477 | { | |
5be73b47 | 3478 | u16 flowctrl; |
1da177e4 LT |
3479 | unsigned long delta; |
3480 | u32 rx_cfg_reg; | |
3481 | int ret; | |
3482 | ||
3483 | if (ap->state == ANEG_STATE_UNKNOWN) { | |
3484 | ap->rxconfig = 0; | |
3485 | ap->link_time = 0; | |
3486 | ap->cur_time = 0; | |
3487 | ap->ability_match_cfg = 0; | |
3488 | ap->ability_match_count = 0; | |
3489 | ap->ability_match = 0; | |
3490 | ap->idle_match = 0; | |
3491 | ap->ack_match = 0; | |
3492 | } | |
3493 | ap->cur_time++; | |
3494 | ||
3495 | if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { | |
3496 | rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); | |
3497 | ||
3498 | if (rx_cfg_reg != ap->ability_match_cfg) { | |
3499 | ap->ability_match_cfg = rx_cfg_reg; | |
3500 | ap->ability_match = 0; | |
3501 | ap->ability_match_count = 0; | |
3502 | } else { | |
3503 | if (++ap->ability_match_count > 1) { | |
3504 | ap->ability_match = 1; | |
3505 | ap->ability_match_cfg = rx_cfg_reg; | |
3506 | } | |
3507 | } | |
3508 | if (rx_cfg_reg & ANEG_CFG_ACK) | |
3509 | ap->ack_match = 1; | |
3510 | else | |
3511 | ap->ack_match = 0; | |
3512 | ||
3513 | ap->idle_match = 0; | |
3514 | } else { | |
3515 | ap->idle_match = 1; | |
3516 | ap->ability_match_cfg = 0; | |
3517 | ap->ability_match_count = 0; | |
3518 | ap->ability_match = 0; | |
3519 | ap->ack_match = 0; | |
3520 | ||
3521 | rx_cfg_reg = 0; | |
3522 | } | |
3523 | ||
3524 | ap->rxconfig = rx_cfg_reg; | |
3525 | ret = ANEG_OK; | |
3526 | ||
33f401ae | 3527 | switch (ap->state) { |
1da177e4 LT |
3528 | case ANEG_STATE_UNKNOWN: |
3529 | if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) | |
3530 | ap->state = ANEG_STATE_AN_ENABLE; | |
3531 | ||
3532 | /* fallthru */ | |
3533 | case ANEG_STATE_AN_ENABLE: | |
3534 | ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); | |
3535 | if (ap->flags & MR_AN_ENABLE) { | |
3536 | ap->link_time = 0; | |
3537 | ap->cur_time = 0; | |
3538 | ap->ability_match_cfg = 0; | |
3539 | ap->ability_match_count = 0; | |
3540 | ap->ability_match = 0; | |
3541 | ap->idle_match = 0; | |
3542 | ap->ack_match = 0; | |
3543 | ||
3544 | ap->state = ANEG_STATE_RESTART_INIT; | |
3545 | } else { | |
3546 | ap->state = ANEG_STATE_DISABLE_LINK_OK; | |
3547 | } | |
3548 | break; | |
3549 | ||
3550 | case ANEG_STATE_RESTART_INIT: | |
3551 | ap->link_time = ap->cur_time; | |
3552 | ap->flags &= ~(MR_NP_LOADED); | |
3553 | ap->txconfig = 0; | |
3554 | tw32(MAC_TX_AUTO_NEG, 0); | |
3555 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3556 | tw32_f(MAC_MODE, tp->mac_mode); | |
3557 | udelay(40); | |
3558 | ||
3559 | ret = ANEG_TIMER_ENAB; | |
3560 | ap->state = ANEG_STATE_RESTART; | |
3561 | ||
3562 | /* fallthru */ | |
3563 | case ANEG_STATE_RESTART: | |
3564 | delta = ap->cur_time - ap->link_time; | |
859a5887 | 3565 | if (delta > ANEG_STATE_SETTLE_TIME) |
1da177e4 | 3566 | ap->state = ANEG_STATE_ABILITY_DETECT_INIT; |
859a5887 | 3567 | else |
1da177e4 | 3568 | ret = ANEG_TIMER_ENAB; |
1da177e4 LT |
3569 | break; |
3570 | ||
3571 | case ANEG_STATE_DISABLE_LINK_OK: | |
3572 | ret = ANEG_DONE; | |
3573 | break; | |
3574 | ||
3575 | case ANEG_STATE_ABILITY_DETECT_INIT: | |
3576 | ap->flags &= ~(MR_TOGGLE_TX); | |
5be73b47 MC |
3577 | ap->txconfig = ANEG_CFG_FD; |
3578 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
3579 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
3580 | ap->txconfig |= ANEG_CFG_PS1; | |
3581 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
3582 | ap->txconfig |= ANEG_CFG_PS2; | |
1da177e4 LT |
3583 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); |
3584 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3585 | tw32_f(MAC_MODE, tp->mac_mode); | |
3586 | udelay(40); | |
3587 | ||
3588 | ap->state = ANEG_STATE_ABILITY_DETECT; | |
3589 | break; | |
3590 | ||
3591 | case ANEG_STATE_ABILITY_DETECT: | |
859a5887 | 3592 | if (ap->ability_match != 0 && ap->rxconfig != 0) |
1da177e4 | 3593 | ap->state = ANEG_STATE_ACK_DETECT_INIT; |
1da177e4 LT |
3594 | break; |
3595 | ||
3596 | case ANEG_STATE_ACK_DETECT_INIT: | |
3597 | ap->txconfig |= ANEG_CFG_ACK; | |
3598 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); | |
3599 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3600 | tw32_f(MAC_MODE, tp->mac_mode); | |
3601 | udelay(40); | |
3602 | ||
3603 | ap->state = ANEG_STATE_ACK_DETECT; | |
3604 | ||
3605 | /* fallthru */ | |
3606 | case ANEG_STATE_ACK_DETECT: | |
3607 | if (ap->ack_match != 0) { | |
3608 | if ((ap->rxconfig & ~ANEG_CFG_ACK) == | |
3609 | (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { | |
3610 | ap->state = ANEG_STATE_COMPLETE_ACK_INIT; | |
3611 | } else { | |
3612 | ap->state = ANEG_STATE_AN_ENABLE; | |
3613 | } | |
3614 | } else if (ap->ability_match != 0 && | |
3615 | ap->rxconfig == 0) { | |
3616 | ap->state = ANEG_STATE_AN_ENABLE; | |
3617 | } | |
3618 | break; | |
3619 | ||
3620 | case ANEG_STATE_COMPLETE_ACK_INIT: | |
3621 | if (ap->rxconfig & ANEG_CFG_INVAL) { | |
3622 | ret = ANEG_FAILED; | |
3623 | break; | |
3624 | } | |
3625 | ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | | |
3626 | MR_LP_ADV_HALF_DUPLEX | | |
3627 | MR_LP_ADV_SYM_PAUSE | | |
3628 | MR_LP_ADV_ASYM_PAUSE | | |
3629 | MR_LP_ADV_REMOTE_FAULT1 | | |
3630 | MR_LP_ADV_REMOTE_FAULT2 | | |
3631 | MR_LP_ADV_NEXT_PAGE | | |
3632 | MR_TOGGLE_RX | | |
3633 | MR_NP_RX); | |
3634 | if (ap->rxconfig & ANEG_CFG_FD) | |
3635 | ap->flags |= MR_LP_ADV_FULL_DUPLEX; | |
3636 | if (ap->rxconfig & ANEG_CFG_HD) | |
3637 | ap->flags |= MR_LP_ADV_HALF_DUPLEX; | |
3638 | if (ap->rxconfig & ANEG_CFG_PS1) | |
3639 | ap->flags |= MR_LP_ADV_SYM_PAUSE; | |
3640 | if (ap->rxconfig & ANEG_CFG_PS2) | |
3641 | ap->flags |= MR_LP_ADV_ASYM_PAUSE; | |
3642 | if (ap->rxconfig & ANEG_CFG_RF1) | |
3643 | ap->flags |= MR_LP_ADV_REMOTE_FAULT1; | |
3644 | if (ap->rxconfig & ANEG_CFG_RF2) | |
3645 | ap->flags |= MR_LP_ADV_REMOTE_FAULT2; | |
3646 | if (ap->rxconfig & ANEG_CFG_NP) | |
3647 | ap->flags |= MR_LP_ADV_NEXT_PAGE; | |
3648 | ||
3649 | ap->link_time = ap->cur_time; | |
3650 | ||
3651 | ap->flags ^= (MR_TOGGLE_TX); | |
3652 | if (ap->rxconfig & 0x0008) | |
3653 | ap->flags |= MR_TOGGLE_RX; | |
3654 | if (ap->rxconfig & ANEG_CFG_NP) | |
3655 | ap->flags |= MR_NP_RX; | |
3656 | ap->flags |= MR_PAGE_RX; | |
3657 | ||
3658 | ap->state = ANEG_STATE_COMPLETE_ACK; | |
3659 | ret = ANEG_TIMER_ENAB; | |
3660 | break; | |
3661 | ||
3662 | case ANEG_STATE_COMPLETE_ACK: | |
3663 | if (ap->ability_match != 0 && | |
3664 | ap->rxconfig == 0) { | |
3665 | ap->state = ANEG_STATE_AN_ENABLE; | |
3666 | break; | |
3667 | } | |
3668 | delta = ap->cur_time - ap->link_time; | |
3669 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3670 | if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { | |
3671 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3672 | } else { | |
3673 | if ((ap->txconfig & ANEG_CFG_NP) == 0 && | |
3674 | !(ap->flags & MR_NP_RX)) { | |
3675 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3676 | } else { | |
3677 | ret = ANEG_FAILED; | |
3678 | } | |
3679 | } | |
3680 | } | |
3681 | break; | |
3682 | ||
3683 | case ANEG_STATE_IDLE_DETECT_INIT: | |
3684 | ap->link_time = ap->cur_time; | |
3685 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3686 | tw32_f(MAC_MODE, tp->mac_mode); | |
3687 | udelay(40); | |
3688 | ||
3689 | ap->state = ANEG_STATE_IDLE_DETECT; | |
3690 | ret = ANEG_TIMER_ENAB; | |
3691 | break; | |
3692 | ||
3693 | case ANEG_STATE_IDLE_DETECT: | |
3694 | if (ap->ability_match != 0 && | |
3695 | ap->rxconfig == 0) { | |
3696 | ap->state = ANEG_STATE_AN_ENABLE; | |
3697 | break; | |
3698 | } | |
3699 | delta = ap->cur_time - ap->link_time; | |
3700 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3701 | /* XXX another gem from the Broadcom driver :( */ | |
3702 | ap->state = ANEG_STATE_LINK_OK; | |
3703 | } | |
3704 | break; | |
3705 | ||
3706 | case ANEG_STATE_LINK_OK: | |
3707 | ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); | |
3708 | ret = ANEG_DONE; | |
3709 | break; | |
3710 | ||
3711 | case ANEG_STATE_NEXT_PAGE_WAIT_INIT: | |
3712 | /* ??? unimplemented */ | |
3713 | break; | |
3714 | ||
3715 | case ANEG_STATE_NEXT_PAGE_WAIT: | |
3716 | /* ??? unimplemented */ | |
3717 | break; | |
3718 | ||
3719 | default: | |
3720 | ret = ANEG_FAILED; | |
3721 | break; | |
855e1111 | 3722 | } |
1da177e4 LT |
3723 | |
3724 | return ret; | |
3725 | } | |
3726 | ||
5be73b47 | 3727 | static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) |
1da177e4 LT |
3728 | { |
3729 | int res = 0; | |
3730 | struct tg3_fiber_aneginfo aninfo; | |
3731 | int status = ANEG_FAILED; | |
3732 | unsigned int tick; | |
3733 | u32 tmp; | |
3734 | ||
3735 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
3736 | ||
3737 | tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; | |
3738 | tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII); | |
3739 | udelay(40); | |
3740 | ||
3741 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); | |
3742 | udelay(40); | |
3743 | ||
3744 | memset(&aninfo, 0, sizeof(aninfo)); | |
3745 | aninfo.flags |= MR_AN_ENABLE; | |
3746 | aninfo.state = ANEG_STATE_UNKNOWN; | |
3747 | aninfo.cur_time = 0; | |
3748 | tick = 0; | |
3749 | while (++tick < 195000) { | |
3750 | status = tg3_fiber_aneg_smachine(tp, &aninfo); | |
3751 | if (status == ANEG_DONE || status == ANEG_FAILED) | |
3752 | break; | |
3753 | ||
3754 | udelay(1); | |
3755 | } | |
3756 | ||
3757 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3758 | tw32_f(MAC_MODE, tp->mac_mode); | |
3759 | udelay(40); | |
3760 | ||
5be73b47 MC |
3761 | *txflags = aninfo.txconfig; |
3762 | *rxflags = aninfo.flags; | |
1da177e4 LT |
3763 | |
3764 | if (status == ANEG_DONE && | |
3765 | (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK | | |
3766 | MR_LP_ADV_FULL_DUPLEX))) | |
3767 | res = 1; | |
3768 | ||
3769 | return res; | |
3770 | } | |
3771 | ||
3772 | static void tg3_init_bcm8002(struct tg3 *tp) | |
3773 | { | |
3774 | u32 mac_status = tr32(MAC_STATUS); | |
3775 | int i; | |
3776 | ||
3777 | /* Reset when initting first time or we have a link. */ | |
3778 | if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) && | |
3779 | !(mac_status & MAC_STATUS_PCS_SYNCED)) | |
3780 | return; | |
3781 | ||
3782 | /* Set PLL lock range. */ | |
3783 | tg3_writephy(tp, 0x16, 0x8007); | |
3784 | ||
3785 | /* SW reset */ | |
3786 | tg3_writephy(tp, MII_BMCR, BMCR_RESET); | |
3787 | ||
3788 | /* Wait for reset to complete. */ | |
3789 | /* XXX schedule_timeout() ... */ | |
3790 | for (i = 0; i < 500; i++) | |
3791 | udelay(10); | |
3792 | ||
3793 | /* Config mode; select PMA/Ch 1 regs. */ | |
3794 | tg3_writephy(tp, 0x10, 0x8411); | |
3795 | ||
3796 | /* Enable auto-lock and comdet, select txclk for tx. */ | |
3797 | tg3_writephy(tp, 0x11, 0x0a10); | |
3798 | ||
3799 | tg3_writephy(tp, 0x18, 0x00a0); | |
3800 | tg3_writephy(tp, 0x16, 0x41ff); | |
3801 | ||
3802 | /* Assert and deassert POR. */ | |
3803 | tg3_writephy(tp, 0x13, 0x0400); | |
3804 | udelay(40); | |
3805 | tg3_writephy(tp, 0x13, 0x0000); | |
3806 | ||
3807 | tg3_writephy(tp, 0x11, 0x0a50); | |
3808 | udelay(40); | |
3809 | tg3_writephy(tp, 0x11, 0x0a10); | |
3810 | ||
3811 | /* Wait for signal to stabilize */ | |
3812 | /* XXX schedule_timeout() ... */ | |
3813 | for (i = 0; i < 15000; i++) | |
3814 | udelay(10); | |
3815 | ||
3816 | /* Deselect the channel register so we can read the PHYID | |
3817 | * later. | |
3818 | */ | |
3819 | tg3_writephy(tp, 0x10, 0x8011); | |
3820 | } | |
3821 | ||
3822 | static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) | |
3823 | { | |
82cd3d11 | 3824 | u16 flowctrl; |
1da177e4 LT |
3825 | u32 sg_dig_ctrl, sg_dig_status; |
3826 | u32 serdes_cfg, expected_sg_dig_ctrl; | |
3827 | int workaround, port_a; | |
3828 | int current_link_up; | |
3829 | ||
3830 | serdes_cfg = 0; | |
3831 | expected_sg_dig_ctrl = 0; | |
3832 | workaround = 0; | |
3833 | port_a = 1; | |
3834 | current_link_up = 0; | |
3835 | ||
3836 | if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 && | |
3837 | tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) { | |
3838 | workaround = 1; | |
3839 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) | |
3840 | port_a = 0; | |
3841 | ||
3842 | /* preserve bits 0-11,13,14 for signal pre-emphasis */ | |
3843 | /* preserve bits 20-23 for voltage regulator */ | |
3844 | serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; | |
3845 | } | |
3846 | ||
3847 | sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
3848 | ||
3849 | if (tp->link_config.autoneg != AUTONEG_ENABLE) { | |
c98f6e3b | 3850 | if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) { |
1da177e4 LT |
3851 | if (workaround) { |
3852 | u32 val = serdes_cfg; | |
3853 | ||
3854 | if (port_a) | |
3855 | val |= 0xc010000; | |
3856 | else | |
3857 | val |= 0x4010000; | |
3858 | tw32_f(MAC_SERDES_CFG, val); | |
3859 | } | |
c98f6e3b MC |
3860 | |
3861 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); | |
1da177e4 LT |
3862 | } |
3863 | if (mac_status & MAC_STATUS_PCS_SYNCED) { | |
3864 | tg3_setup_flow_control(tp, 0, 0); | |
3865 | current_link_up = 1; | |
3866 | } | |
3867 | goto out; | |
3868 | } | |
3869 | ||
3870 | /* Want auto-negotiation. */ | |
c98f6e3b | 3871 | expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP; |
1da177e4 | 3872 | |
82cd3d11 MC |
3873 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
3874 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
3875 | expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP; | |
3876 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
3877 | expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE; | |
1da177e4 LT |
3878 | |
3879 | if (sg_dig_ctrl != expected_sg_dig_ctrl) { | |
f07e9af3 | 3880 | if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && |
3d3ebe74 MC |
3881 | tp->serdes_counter && |
3882 | ((mac_status & (MAC_STATUS_PCS_SYNCED | | |
3883 | MAC_STATUS_RCVD_CFG)) == | |
3884 | MAC_STATUS_PCS_SYNCED)) { | |
3885 | tp->serdes_counter--; | |
3886 | current_link_up = 1; | |
3887 | goto out; | |
3888 | } | |
3889 | restart_autoneg: | |
1da177e4 LT |
3890 | if (workaround) |
3891 | tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000); | |
c98f6e3b | 3892 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET); |
1da177e4 LT |
3893 | udelay(5); |
3894 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl); | |
3895 | ||
3d3ebe74 | 3896 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; |
f07e9af3 | 3897 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
3898 | } else if (mac_status & (MAC_STATUS_PCS_SYNCED | |
3899 | MAC_STATUS_SIGNAL_DET)) { | |
3d3ebe74 | 3900 | sg_dig_status = tr32(SG_DIG_STATUS); |
1da177e4 LT |
3901 | mac_status = tr32(MAC_STATUS); |
3902 | ||
c98f6e3b | 3903 | if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) && |
1da177e4 | 3904 | (mac_status & MAC_STATUS_PCS_SYNCED)) { |
82cd3d11 MC |
3905 | u32 local_adv = 0, remote_adv = 0; |
3906 | ||
3907 | if (sg_dig_ctrl & SG_DIG_PAUSE_CAP) | |
3908 | local_adv |= ADVERTISE_1000XPAUSE; | |
3909 | if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE) | |
3910 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
1da177e4 | 3911 | |
c98f6e3b | 3912 | if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE) |
82cd3d11 | 3913 | remote_adv |= LPA_1000XPAUSE; |
c98f6e3b | 3914 | if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE) |
82cd3d11 | 3915 | remote_adv |= LPA_1000XPAUSE_ASYM; |
1da177e4 LT |
3916 | |
3917 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
3918 | current_link_up = 1; | |
3d3ebe74 | 3919 | tp->serdes_counter = 0; |
f07e9af3 | 3920 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
c98f6e3b | 3921 | } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { |
3d3ebe74 MC |
3922 | if (tp->serdes_counter) |
3923 | tp->serdes_counter--; | |
1da177e4 LT |
3924 | else { |
3925 | if (workaround) { | |
3926 | u32 val = serdes_cfg; | |
3927 | ||
3928 | if (port_a) | |
3929 | val |= 0xc010000; | |
3930 | else | |
3931 | val |= 0x4010000; | |
3932 | ||
3933 | tw32_f(MAC_SERDES_CFG, val); | |
3934 | } | |
3935 | ||
c98f6e3b | 3936 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); |
1da177e4 LT |
3937 | udelay(40); |
3938 | ||
3939 | /* Link parallel detection - link is up */ | |
3940 | /* only if we have PCS_SYNC and not */ | |
3941 | /* receiving config code words */ | |
3942 | mac_status = tr32(MAC_STATUS); | |
3943 | if ((mac_status & MAC_STATUS_PCS_SYNCED) && | |
3944 | !(mac_status & MAC_STATUS_RCVD_CFG)) { | |
3945 | tg3_setup_flow_control(tp, 0, 0); | |
3946 | current_link_up = 1; | |
f07e9af3 MC |
3947 | tp->phy_flags |= |
3948 | TG3_PHYFLG_PARALLEL_DETECT; | |
3d3ebe74 MC |
3949 | tp->serdes_counter = |
3950 | SERDES_PARALLEL_DET_TIMEOUT; | |
3951 | } else | |
3952 | goto restart_autoneg; | |
1da177e4 LT |
3953 | } |
3954 | } | |
3d3ebe74 MC |
3955 | } else { |
3956 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; | |
f07e9af3 | 3957 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
3958 | } |
3959 | ||
3960 | out: | |
3961 | return current_link_up; | |
3962 | } | |
3963 | ||
3964 | static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) | |
3965 | { | |
3966 | int current_link_up = 0; | |
3967 | ||
5cf64b8a | 3968 | if (!(mac_status & MAC_STATUS_PCS_SYNCED)) |
1da177e4 | 3969 | goto out; |
1da177e4 LT |
3970 | |
3971 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
5be73b47 | 3972 | u32 txflags, rxflags; |
1da177e4 | 3973 | int i; |
6aa20a22 | 3974 | |
5be73b47 MC |
3975 | if (fiber_autoneg(tp, &txflags, &rxflags)) { |
3976 | u32 local_adv = 0, remote_adv = 0; | |
1da177e4 | 3977 | |
5be73b47 MC |
3978 | if (txflags & ANEG_CFG_PS1) |
3979 | local_adv |= ADVERTISE_1000XPAUSE; | |
3980 | if (txflags & ANEG_CFG_PS2) | |
3981 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
3982 | ||
3983 | if (rxflags & MR_LP_ADV_SYM_PAUSE) | |
3984 | remote_adv |= LPA_1000XPAUSE; | |
3985 | if (rxflags & MR_LP_ADV_ASYM_PAUSE) | |
3986 | remote_adv |= LPA_1000XPAUSE_ASYM; | |
1da177e4 LT |
3987 | |
3988 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
3989 | ||
1da177e4 LT |
3990 | current_link_up = 1; |
3991 | } | |
3992 | for (i = 0; i < 30; i++) { | |
3993 | udelay(20); | |
3994 | tw32_f(MAC_STATUS, | |
3995 | (MAC_STATUS_SYNC_CHANGED | | |
3996 | MAC_STATUS_CFG_CHANGED)); | |
3997 | udelay(40); | |
3998 | if ((tr32(MAC_STATUS) & | |
3999 | (MAC_STATUS_SYNC_CHANGED | | |
4000 | MAC_STATUS_CFG_CHANGED)) == 0) | |
4001 | break; | |
4002 | } | |
4003 | ||
4004 | mac_status = tr32(MAC_STATUS); | |
4005 | if (current_link_up == 0 && | |
4006 | (mac_status & MAC_STATUS_PCS_SYNCED) && | |
4007 | !(mac_status & MAC_STATUS_RCVD_CFG)) | |
4008 | current_link_up = 1; | |
4009 | } else { | |
5be73b47 MC |
4010 | tg3_setup_flow_control(tp, 0, 0); |
4011 | ||
1da177e4 LT |
4012 | /* Forcing 1000FD link up. */ |
4013 | current_link_up = 1; | |
1da177e4 LT |
4014 | |
4015 | tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); | |
4016 | udelay(40); | |
e8f3f6ca MC |
4017 | |
4018 | tw32_f(MAC_MODE, tp->mac_mode); | |
4019 | udelay(40); | |
1da177e4 LT |
4020 | } |
4021 | ||
4022 | out: | |
4023 | return current_link_up; | |
4024 | } | |
4025 | ||
4026 | static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | |
4027 | { | |
4028 | u32 orig_pause_cfg; | |
4029 | u16 orig_active_speed; | |
4030 | u8 orig_active_duplex; | |
4031 | u32 mac_status; | |
4032 | int current_link_up; | |
4033 | int i; | |
4034 | ||
8d018621 | 4035 | orig_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
4036 | orig_active_speed = tp->link_config.active_speed; |
4037 | orig_active_duplex = tp->link_config.active_duplex; | |
4038 | ||
4039 | if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) && | |
4040 | netif_carrier_ok(tp->dev) && | |
4041 | (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) { | |
4042 | mac_status = tr32(MAC_STATUS); | |
4043 | mac_status &= (MAC_STATUS_PCS_SYNCED | | |
4044 | MAC_STATUS_SIGNAL_DET | | |
4045 | MAC_STATUS_CFG_CHANGED | | |
4046 | MAC_STATUS_RCVD_CFG); | |
4047 | if (mac_status == (MAC_STATUS_PCS_SYNCED | | |
4048 | MAC_STATUS_SIGNAL_DET)) { | |
4049 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
4050 | MAC_STATUS_CFG_CHANGED)); | |
4051 | return 0; | |
4052 | } | |
4053 | } | |
4054 | ||
4055 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
4056 | ||
4057 | tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
4058 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; | |
4059 | tw32_f(MAC_MODE, tp->mac_mode); | |
4060 | udelay(40); | |
4061 | ||
79eb6904 | 4062 | if (tp->phy_id == TG3_PHY_ID_BCM8002) |
1da177e4 LT |
4063 | tg3_init_bcm8002(tp); |
4064 | ||
4065 | /* Enable link change event even when serdes polling. */ | |
4066 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4067 | udelay(40); | |
4068 | ||
4069 | current_link_up = 0; | |
4070 | mac_status = tr32(MAC_STATUS); | |
4071 | ||
4072 | if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) | |
4073 | current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); | |
4074 | else | |
4075 | current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); | |
4076 | ||
898a56f8 | 4077 | tp->napi[0].hw_status->status = |
1da177e4 | 4078 | (SD_STATUS_UPDATED | |
898a56f8 | 4079 | (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); |
1da177e4 LT |
4080 | |
4081 | for (i = 0; i < 100; i++) { | |
4082 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
4083 | MAC_STATUS_CFG_CHANGED)); | |
4084 | udelay(5); | |
4085 | if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | | |
3d3ebe74 MC |
4086 | MAC_STATUS_CFG_CHANGED | |
4087 | MAC_STATUS_LNKSTATE_CHANGED)) == 0) | |
1da177e4 LT |
4088 | break; |
4089 | } | |
4090 | ||
4091 | mac_status = tr32(MAC_STATUS); | |
4092 | if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { | |
4093 | current_link_up = 0; | |
3d3ebe74 MC |
4094 | if (tp->link_config.autoneg == AUTONEG_ENABLE && |
4095 | tp->serdes_counter == 0) { | |
1da177e4 LT |
4096 | tw32_f(MAC_MODE, (tp->mac_mode | |
4097 | MAC_MODE_SEND_CONFIGS)); | |
4098 | udelay(1); | |
4099 | tw32_f(MAC_MODE, tp->mac_mode); | |
4100 | } | |
4101 | } | |
4102 | ||
4103 | if (current_link_up == 1) { | |
4104 | tp->link_config.active_speed = SPEED_1000; | |
4105 | tp->link_config.active_duplex = DUPLEX_FULL; | |
4106 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4107 | LED_CTRL_LNKLED_OVERRIDE | | |
4108 | LED_CTRL_1000MBPS_ON)); | |
4109 | } else { | |
4110 | tp->link_config.active_speed = SPEED_INVALID; | |
4111 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
4112 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4113 | LED_CTRL_LNKLED_OVERRIDE | | |
4114 | LED_CTRL_TRAFFIC_OVERRIDE)); | |
4115 | } | |
4116 | ||
4117 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4118 | if (current_link_up) | |
4119 | netif_carrier_on(tp->dev); | |
4120 | else | |
4121 | netif_carrier_off(tp->dev); | |
4122 | tg3_link_report(tp); | |
4123 | } else { | |
8d018621 | 4124 | u32 now_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
4125 | if (orig_pause_cfg != now_pause_cfg || |
4126 | orig_active_speed != tp->link_config.active_speed || | |
4127 | orig_active_duplex != tp->link_config.active_duplex) | |
4128 | tg3_link_report(tp); | |
4129 | } | |
4130 | ||
4131 | return 0; | |
4132 | } | |
4133 | ||
747e8f8b MC |
4134 | static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) |
4135 | { | |
4136 | int current_link_up, err = 0; | |
4137 | u32 bmsr, bmcr; | |
4138 | u16 current_speed; | |
4139 | u8 current_duplex; | |
ef167e27 | 4140 | u32 local_adv, remote_adv; |
747e8f8b MC |
4141 | |
4142 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
4143 | tw32_f(MAC_MODE, tp->mac_mode); | |
4144 | udelay(40); | |
4145 | ||
4146 | tw32(MAC_EVENT, 0); | |
4147 | ||
4148 | tw32_f(MAC_STATUS, | |
4149 | (MAC_STATUS_SYNC_CHANGED | | |
4150 | MAC_STATUS_CFG_CHANGED | | |
4151 | MAC_STATUS_MI_COMPLETION | | |
4152 | MAC_STATUS_LNKSTATE_CHANGED)); | |
4153 | udelay(40); | |
4154 | ||
4155 | if (force_reset) | |
4156 | tg3_phy_reset(tp); | |
4157 | ||
4158 | current_link_up = 0; | |
4159 | current_speed = SPEED_INVALID; | |
4160 | current_duplex = DUPLEX_INVALID; | |
4161 | ||
4162 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4163 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
4164 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
4165 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4166 | bmsr |= BMSR_LSTATUS; | |
4167 | else | |
4168 | bmsr &= ~BMSR_LSTATUS; | |
4169 | } | |
747e8f8b MC |
4170 | |
4171 | err |= tg3_readphy(tp, MII_BMCR, &bmcr); | |
4172 | ||
4173 | if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && | |
f07e9af3 | 4174 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
4175 | /* do nothing, just check for link up at the end */ |
4176 | } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
4177 | u32 adv, new_adv; | |
4178 | ||
4179 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4180 | new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF | | |
4181 | ADVERTISE_1000XPAUSE | | |
4182 | ADVERTISE_1000XPSE_ASYM | | |
4183 | ADVERTISE_SLCT); | |
4184 | ||
ba4d07a8 | 4185 | new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
747e8f8b MC |
4186 | |
4187 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) | |
4188 | new_adv |= ADVERTISE_1000XHALF; | |
4189 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) | |
4190 | new_adv |= ADVERTISE_1000XFULL; | |
4191 | ||
4192 | if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) { | |
4193 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
4194 | bmcr |= BMCR_ANENABLE | BMCR_ANRESTART; | |
4195 | tg3_writephy(tp, MII_BMCR, bmcr); | |
4196 | ||
4197 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3d3ebe74 | 4198 | tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; |
f07e9af3 | 4199 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4200 | |
4201 | return err; | |
4202 | } | |
4203 | } else { | |
4204 | u32 new_bmcr; | |
4205 | ||
4206 | bmcr &= ~BMCR_SPEED1000; | |
4207 | new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX); | |
4208 | ||
4209 | if (tp->link_config.duplex == DUPLEX_FULL) | |
4210 | new_bmcr |= BMCR_FULLDPLX; | |
4211 | ||
4212 | if (new_bmcr != bmcr) { | |
4213 | /* BMCR_SPEED1000 is a reserved bit that needs | |
4214 | * to be set on write. | |
4215 | */ | |
4216 | new_bmcr |= BMCR_SPEED1000; | |
4217 | ||
4218 | /* Force a linkdown */ | |
4219 | if (netif_carrier_ok(tp->dev)) { | |
4220 | u32 adv; | |
4221 | ||
4222 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4223 | adv &= ~(ADVERTISE_1000XFULL | | |
4224 | ADVERTISE_1000XHALF | | |
4225 | ADVERTISE_SLCT); | |
4226 | tg3_writephy(tp, MII_ADVERTISE, adv); | |
4227 | tg3_writephy(tp, MII_BMCR, bmcr | | |
4228 | BMCR_ANRESTART | | |
4229 | BMCR_ANENABLE); | |
4230 | udelay(10); | |
4231 | netif_carrier_off(tp->dev); | |
4232 | } | |
4233 | tg3_writephy(tp, MII_BMCR, new_bmcr); | |
4234 | bmcr = new_bmcr; | |
4235 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4236 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
4237 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
4238 | ASIC_REV_5714) { | |
4239 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4240 | bmsr |= BMSR_LSTATUS; | |
4241 | else | |
4242 | bmsr &= ~BMSR_LSTATUS; | |
4243 | } | |
f07e9af3 | 4244 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4245 | } |
4246 | } | |
4247 | ||
4248 | if (bmsr & BMSR_LSTATUS) { | |
4249 | current_speed = SPEED_1000; | |
4250 | current_link_up = 1; | |
4251 | if (bmcr & BMCR_FULLDPLX) | |
4252 | current_duplex = DUPLEX_FULL; | |
4253 | else | |
4254 | current_duplex = DUPLEX_HALF; | |
4255 | ||
ef167e27 MC |
4256 | local_adv = 0; |
4257 | remote_adv = 0; | |
4258 | ||
747e8f8b | 4259 | if (bmcr & BMCR_ANENABLE) { |
ef167e27 | 4260 | u32 common; |
747e8f8b MC |
4261 | |
4262 | err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); | |
4263 | err |= tg3_readphy(tp, MII_LPA, &remote_adv); | |
4264 | common = local_adv & remote_adv; | |
4265 | if (common & (ADVERTISE_1000XHALF | | |
4266 | ADVERTISE_1000XFULL)) { | |
4267 | if (common & ADVERTISE_1000XFULL) | |
4268 | current_duplex = DUPLEX_FULL; | |
4269 | else | |
4270 | current_duplex = DUPLEX_HALF; | |
57d8b880 MC |
4271 | } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
4272 | /* Link is up via parallel detect */ | |
859a5887 | 4273 | } else { |
747e8f8b | 4274 | current_link_up = 0; |
859a5887 | 4275 | } |
747e8f8b MC |
4276 | } |
4277 | } | |
4278 | ||
ef167e27 MC |
4279 | if (current_link_up == 1 && current_duplex == DUPLEX_FULL) |
4280 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4281 | ||
747e8f8b MC |
4282 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; |
4283 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
4284 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
4285 | ||
4286 | tw32_f(MAC_MODE, tp->mac_mode); | |
4287 | udelay(40); | |
4288 | ||
4289 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4290 | ||
4291 | tp->link_config.active_speed = current_speed; | |
4292 | tp->link_config.active_duplex = current_duplex; | |
4293 | ||
4294 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4295 | if (current_link_up) | |
4296 | netif_carrier_on(tp->dev); | |
4297 | else { | |
4298 | netif_carrier_off(tp->dev); | |
f07e9af3 | 4299 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4300 | } |
4301 | tg3_link_report(tp); | |
4302 | } | |
4303 | return err; | |
4304 | } | |
4305 | ||
4306 | static void tg3_serdes_parallel_detect(struct tg3 *tp) | |
4307 | { | |
3d3ebe74 | 4308 | if (tp->serdes_counter) { |
747e8f8b | 4309 | /* Give autoneg time to complete. */ |
3d3ebe74 | 4310 | tp->serdes_counter--; |
747e8f8b MC |
4311 | return; |
4312 | } | |
c6cdf436 | 4313 | |
747e8f8b MC |
4314 | if (!netif_carrier_ok(tp->dev) && |
4315 | (tp->link_config.autoneg == AUTONEG_ENABLE)) { | |
4316 | u32 bmcr; | |
4317 | ||
4318 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4319 | if (bmcr & BMCR_ANENABLE) { | |
4320 | u32 phy1, phy2; | |
4321 | ||
4322 | /* Select shadow register 0x1f */ | |
f08aa1a8 MC |
4323 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); |
4324 | tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1); | |
747e8f8b MC |
4325 | |
4326 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
4327 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
4328 | MII_TG3_DSP_EXP1_INT_STAT); | |
4329 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
4330 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
4331 | |
4332 | if ((phy1 & 0x10) && !(phy2 & 0x20)) { | |
4333 | /* We have signal detect and not receiving | |
4334 | * config code words, link is up by parallel | |
4335 | * detection. | |
4336 | */ | |
4337 | ||
4338 | bmcr &= ~BMCR_ANENABLE; | |
4339 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; | |
4340 | tg3_writephy(tp, MII_BMCR, bmcr); | |
f07e9af3 | 4341 | tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4342 | } |
4343 | } | |
859a5887 MC |
4344 | } else if (netif_carrier_ok(tp->dev) && |
4345 | (tp->link_config.autoneg == AUTONEG_ENABLE) && | |
f07e9af3 | 4346 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
4347 | u32 phy2; |
4348 | ||
4349 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
4350 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
4351 | MII_TG3_DSP_EXP1_INT_STAT); | |
4352 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
4353 | if (phy2 & 0x20) { |
4354 | u32 bmcr; | |
4355 | ||
4356 | /* Config code words received, turn on autoneg. */ | |
4357 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4358 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); | |
4359 | ||
f07e9af3 | 4360 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4361 | |
4362 | } | |
4363 | } | |
4364 | } | |
4365 | ||
1da177e4 LT |
4366 | static int tg3_setup_phy(struct tg3 *tp, int force_reset) |
4367 | { | |
4368 | int err; | |
4369 | ||
f07e9af3 | 4370 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 | 4371 | err = tg3_setup_fiber_phy(tp, force_reset); |
f07e9af3 | 4372 | else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
747e8f8b | 4373 | err = tg3_setup_fiber_mii_phy(tp, force_reset); |
859a5887 | 4374 | else |
1da177e4 | 4375 | err = tg3_setup_copper_phy(tp, force_reset); |
1da177e4 | 4376 | |
bcb37f6c | 4377 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
aa6c91fe MC |
4378 | u32 val, scale; |
4379 | ||
4380 | val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; | |
4381 | if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5) | |
4382 | scale = 65; | |
4383 | else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25) | |
4384 | scale = 6; | |
4385 | else | |
4386 | scale = 12; | |
4387 | ||
4388 | val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; | |
4389 | val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
4390 | tw32(GRC_MISC_CFG, val); | |
4391 | } | |
4392 | ||
1da177e4 LT |
4393 | if (tp->link_config.active_speed == SPEED_1000 && |
4394 | tp->link_config.active_duplex == DUPLEX_HALF) | |
4395 | tw32(MAC_TX_LENGTHS, | |
4396 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
4397 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
4398 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
4399 | else | |
4400 | tw32(MAC_TX_LENGTHS, | |
4401 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
4402 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
4403 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
4404 | ||
4405 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
4406 | if (netif_carrier_ok(tp->dev)) { | |
4407 | tw32(HOSTCC_STAT_COAL_TICKS, | |
15f9850d | 4408 | tp->coal.stats_block_coalesce_usecs); |
1da177e4 LT |
4409 | } else { |
4410 | tw32(HOSTCC_STAT_COAL_TICKS, 0); | |
4411 | } | |
4412 | } | |
4413 | ||
8ed5d97e MC |
4414 | if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) { |
4415 | u32 val = tr32(PCIE_PWR_MGMT_THRESH); | |
4416 | if (!netif_carrier_ok(tp->dev)) | |
4417 | val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) | | |
4418 | tp->pwrmgmt_thresh; | |
4419 | else | |
4420 | val |= PCIE_PWR_MGMT_L1_THRESH_MSK; | |
4421 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
4422 | } | |
4423 | ||
1da177e4 LT |
4424 | return err; |
4425 | } | |
4426 | ||
66cfd1bd MC |
4427 | static inline int tg3_irq_sync(struct tg3 *tp) |
4428 | { | |
4429 | return tp->irq_sync; | |
4430 | } | |
4431 | ||
df3e6548 MC |
4432 | /* This is called whenever we suspect that the system chipset is re- |
4433 | * ordering the sequence of MMIO to the tx send mailbox. The symptom | |
4434 | * is bogus tx completions. We try to recover by setting the | |
4435 | * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later | |
4436 | * in the workqueue. | |
4437 | */ | |
4438 | static void tg3_tx_recover(struct tg3 *tp) | |
4439 | { | |
4440 | BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) || | |
4441 | tp->write32_tx_mbox == tg3_write_indirect_mbox); | |
4442 | ||
5129c3a3 MC |
4443 | netdev_warn(tp->dev, |
4444 | "The system may be re-ordering memory-mapped I/O " | |
4445 | "cycles to the network device, attempting to recover. " | |
4446 | "Please report the problem to the driver maintainer " | |
4447 | "and include system chipset information.\n"); | |
df3e6548 MC |
4448 | |
4449 | spin_lock(&tp->lock); | |
df3e6548 | 4450 | tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING; |
df3e6548 MC |
4451 | spin_unlock(&tp->lock); |
4452 | } | |
4453 | ||
f3f3f27e | 4454 | static inline u32 tg3_tx_avail(struct tg3_napi *tnapi) |
1b2a7205 | 4455 | { |
f65aac16 MC |
4456 | /* Tell compiler to fetch tx indices from memory. */ |
4457 | barrier(); | |
f3f3f27e MC |
4458 | return tnapi->tx_pending - |
4459 | ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); | |
1b2a7205 MC |
4460 | } |
4461 | ||
1da177e4 LT |
4462 | /* Tigon3 never reports partial packet sends. So we do not |
4463 | * need special logic to handle SKBs that have not had all | |
4464 | * of their frags sent yet, like SunGEM does. | |
4465 | */ | |
17375d25 | 4466 | static void tg3_tx(struct tg3_napi *tnapi) |
1da177e4 | 4467 | { |
17375d25 | 4468 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 4469 | u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; |
f3f3f27e | 4470 | u32 sw_idx = tnapi->tx_cons; |
fe5f5787 MC |
4471 | struct netdev_queue *txq; |
4472 | int index = tnapi - tp->napi; | |
4473 | ||
19cfaecc | 4474 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
fe5f5787 MC |
4475 | index--; |
4476 | ||
4477 | txq = netdev_get_tx_queue(tp->dev, index); | |
1da177e4 LT |
4478 | |
4479 | while (sw_idx != hw_idx) { | |
f4188d8a | 4480 | struct ring_info *ri = &tnapi->tx_buffers[sw_idx]; |
1da177e4 | 4481 | struct sk_buff *skb = ri->skb; |
df3e6548 MC |
4482 | int i, tx_bug = 0; |
4483 | ||
4484 | if (unlikely(skb == NULL)) { | |
4485 | tg3_tx_recover(tp); | |
4486 | return; | |
4487 | } | |
1da177e4 | 4488 | |
f4188d8a | 4489 | pci_unmap_single(tp->pdev, |
4e5e4f0d | 4490 | dma_unmap_addr(ri, mapping), |
f4188d8a AD |
4491 | skb_headlen(skb), |
4492 | PCI_DMA_TODEVICE); | |
1da177e4 LT |
4493 | |
4494 | ri->skb = NULL; | |
4495 | ||
4496 | sw_idx = NEXT_TX(sw_idx); | |
4497 | ||
4498 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
f3f3f27e | 4499 | ri = &tnapi->tx_buffers[sw_idx]; |
df3e6548 MC |
4500 | if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) |
4501 | tx_bug = 1; | |
f4188d8a AD |
4502 | |
4503 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 4504 | dma_unmap_addr(ri, mapping), |
f4188d8a AD |
4505 | skb_shinfo(skb)->frags[i].size, |
4506 | PCI_DMA_TODEVICE); | |
1da177e4 LT |
4507 | sw_idx = NEXT_TX(sw_idx); |
4508 | } | |
4509 | ||
f47c11ee | 4510 | dev_kfree_skb(skb); |
df3e6548 MC |
4511 | |
4512 | if (unlikely(tx_bug)) { | |
4513 | tg3_tx_recover(tp); | |
4514 | return; | |
4515 | } | |
1da177e4 LT |
4516 | } |
4517 | ||
f3f3f27e | 4518 | tnapi->tx_cons = sw_idx; |
1da177e4 | 4519 | |
1b2a7205 MC |
4520 | /* Need to make the tx_cons update visible to tg3_start_xmit() |
4521 | * before checking for netif_queue_stopped(). Without the | |
4522 | * memory barrier, there is a small possibility that tg3_start_xmit() | |
4523 | * will miss it and cause the queue to be stopped forever. | |
4524 | */ | |
4525 | smp_mb(); | |
4526 | ||
fe5f5787 | 4527 | if (unlikely(netif_tx_queue_stopped(txq) && |
f3f3f27e | 4528 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) { |
fe5f5787 MC |
4529 | __netif_tx_lock(txq, smp_processor_id()); |
4530 | if (netif_tx_queue_stopped(txq) && | |
f3f3f27e | 4531 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))) |
fe5f5787 MC |
4532 | netif_tx_wake_queue(txq); |
4533 | __netif_tx_unlock(txq); | |
51b91468 | 4534 | } |
1da177e4 LT |
4535 | } |
4536 | ||
2b2cdb65 MC |
4537 | static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) |
4538 | { | |
4539 | if (!ri->skb) | |
4540 | return; | |
4541 | ||
4e5e4f0d | 4542 | pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping), |
2b2cdb65 MC |
4543 | map_sz, PCI_DMA_FROMDEVICE); |
4544 | dev_kfree_skb_any(ri->skb); | |
4545 | ri->skb = NULL; | |
4546 | } | |
4547 | ||
1da177e4 LT |
4548 | /* Returns size of skb allocated or < 0 on error. |
4549 | * | |
4550 | * We only need to fill in the address because the other members | |
4551 | * of the RX descriptor are invariant, see tg3_init_rings. | |
4552 | * | |
4553 | * Note the purposeful assymetry of cpu vs. chip accesses. For | |
4554 | * posting buffers we only dirty the first cache line of the RX | |
4555 | * descriptor (containing the address). Whereas for the RX status | |
4556 | * buffers the cpu only reads the last cacheline of the RX descriptor | |
4557 | * (to fetch the error flags, vlan tag, checksum, and opaque cookie). | |
4558 | */ | |
86b21e59 | 4559 | static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr, |
a3896167 | 4560 | u32 opaque_key, u32 dest_idx_unmasked) |
1da177e4 LT |
4561 | { |
4562 | struct tg3_rx_buffer_desc *desc; | |
f94e290e | 4563 | struct ring_info *map; |
1da177e4 LT |
4564 | struct sk_buff *skb; |
4565 | dma_addr_t mapping; | |
4566 | int skb_size, dest_idx; | |
4567 | ||
1da177e4 LT |
4568 | switch (opaque_key) { |
4569 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 4570 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
21f581a5 MC |
4571 | desc = &tpr->rx_std[dest_idx]; |
4572 | map = &tpr->rx_std_buffers[dest_idx]; | |
287be12e | 4573 | skb_size = tp->rx_pkt_map_sz; |
1da177e4 LT |
4574 | break; |
4575 | ||
4576 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 4577 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
79ed5ac7 | 4578 | desc = &tpr->rx_jmb[dest_idx].std; |
21f581a5 | 4579 | map = &tpr->rx_jmb_buffers[dest_idx]; |
287be12e | 4580 | skb_size = TG3_RX_JMB_MAP_SZ; |
1da177e4 LT |
4581 | break; |
4582 | ||
4583 | default: | |
4584 | return -EINVAL; | |
855e1111 | 4585 | } |
1da177e4 LT |
4586 | |
4587 | /* Do not overwrite any of the map or rp information | |
4588 | * until we are sure we can commit to a new buffer. | |
4589 | * | |
4590 | * Callers depend upon this behavior and assume that | |
4591 | * we leave everything unchanged if we fail. | |
4592 | */ | |
287be12e | 4593 | skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset); |
1da177e4 LT |
4594 | if (skb == NULL) |
4595 | return -ENOMEM; | |
4596 | ||
1da177e4 LT |
4597 | skb_reserve(skb, tp->rx_offset); |
4598 | ||
287be12e | 4599 | mapping = pci_map_single(tp->pdev, skb->data, skb_size, |
1da177e4 | 4600 | PCI_DMA_FROMDEVICE); |
a21771dd MC |
4601 | if (pci_dma_mapping_error(tp->pdev, mapping)) { |
4602 | dev_kfree_skb(skb); | |
4603 | return -EIO; | |
4604 | } | |
1da177e4 LT |
4605 | |
4606 | map->skb = skb; | |
4e5e4f0d | 4607 | dma_unmap_addr_set(map, mapping, mapping); |
1da177e4 | 4608 | |
1da177e4 LT |
4609 | desc->addr_hi = ((u64)mapping >> 32); |
4610 | desc->addr_lo = ((u64)mapping & 0xffffffff); | |
4611 | ||
4612 | return skb_size; | |
4613 | } | |
4614 | ||
4615 | /* We only need to move over in the address because the other | |
4616 | * members of the RX descriptor are invariant. See notes above | |
4617 | * tg3_alloc_rx_skb for full details. | |
4618 | */ | |
a3896167 MC |
4619 | static void tg3_recycle_rx(struct tg3_napi *tnapi, |
4620 | struct tg3_rx_prodring_set *dpr, | |
4621 | u32 opaque_key, int src_idx, | |
4622 | u32 dest_idx_unmasked) | |
1da177e4 | 4623 | { |
17375d25 | 4624 | struct tg3 *tp = tnapi->tp; |
1da177e4 LT |
4625 | struct tg3_rx_buffer_desc *src_desc, *dest_desc; |
4626 | struct ring_info *src_map, *dest_map; | |
8fea32b9 | 4627 | struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; |
c6cdf436 | 4628 | int dest_idx; |
1da177e4 LT |
4629 | |
4630 | switch (opaque_key) { | |
4631 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 4632 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
a3896167 MC |
4633 | dest_desc = &dpr->rx_std[dest_idx]; |
4634 | dest_map = &dpr->rx_std_buffers[dest_idx]; | |
4635 | src_desc = &spr->rx_std[src_idx]; | |
4636 | src_map = &spr->rx_std_buffers[src_idx]; | |
1da177e4 LT |
4637 | break; |
4638 | ||
4639 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 4640 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
a3896167 MC |
4641 | dest_desc = &dpr->rx_jmb[dest_idx].std; |
4642 | dest_map = &dpr->rx_jmb_buffers[dest_idx]; | |
4643 | src_desc = &spr->rx_jmb[src_idx].std; | |
4644 | src_map = &spr->rx_jmb_buffers[src_idx]; | |
1da177e4 LT |
4645 | break; |
4646 | ||
4647 | default: | |
4648 | return; | |
855e1111 | 4649 | } |
1da177e4 LT |
4650 | |
4651 | dest_map->skb = src_map->skb; | |
4e5e4f0d FT |
4652 | dma_unmap_addr_set(dest_map, mapping, |
4653 | dma_unmap_addr(src_map, mapping)); | |
1da177e4 LT |
4654 | dest_desc->addr_hi = src_desc->addr_hi; |
4655 | dest_desc->addr_lo = src_desc->addr_lo; | |
e92967bf MC |
4656 | |
4657 | /* Ensure that the update to the skb happens after the physical | |
4658 | * addresses have been transferred to the new BD location. | |
4659 | */ | |
4660 | smp_wmb(); | |
4661 | ||
1da177e4 LT |
4662 | src_map->skb = NULL; |
4663 | } | |
4664 | ||
1da177e4 LT |
4665 | /* The RX ring scheme is composed of multiple rings which post fresh |
4666 | * buffers to the chip, and one special ring the chip uses to report | |
4667 | * status back to the host. | |
4668 | * | |
4669 | * The special ring reports the status of received packets to the | |
4670 | * host. The chip does not write into the original descriptor the | |
4671 | * RX buffer was obtained from. The chip simply takes the original | |
4672 | * descriptor as provided by the host, updates the status and length | |
4673 | * field, then writes this into the next status ring entry. | |
4674 | * | |
4675 | * Each ring the host uses to post buffers to the chip is described | |
4676 | * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives, | |
4677 | * it is first placed into the on-chip ram. When the packet's length | |
4678 | * is known, it walks down the TG3_BDINFO entries to select the ring. | |
4679 | * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO | |
4680 | * which is within the range of the new packet's length is chosen. | |
4681 | * | |
4682 | * The "separate ring for rx status" scheme may sound queer, but it makes | |
4683 | * sense from a cache coherency perspective. If only the host writes | |
4684 | * to the buffer post rings, and only the chip writes to the rx status | |
4685 | * rings, then cache lines never move beyond shared-modified state. | |
4686 | * If both the host and chip were to write into the same ring, cache line | |
4687 | * eviction could occur since both entities want it in an exclusive state. | |
4688 | */ | |
17375d25 | 4689 | static int tg3_rx(struct tg3_napi *tnapi, int budget) |
1da177e4 | 4690 | { |
17375d25 | 4691 | struct tg3 *tp = tnapi->tp; |
f92905de | 4692 | u32 work_mask, rx_std_posted = 0; |
4361935a | 4693 | u32 std_prod_idx, jmb_prod_idx; |
72334482 | 4694 | u32 sw_idx = tnapi->rx_rcb_ptr; |
483ba50b | 4695 | u16 hw_idx; |
1da177e4 | 4696 | int received; |
8fea32b9 | 4697 | struct tg3_rx_prodring_set *tpr = &tnapi->prodring; |
1da177e4 | 4698 | |
8d9d7cfc | 4699 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
1da177e4 LT |
4700 | /* |
4701 | * We need to order the read of hw_idx and the read of | |
4702 | * the opaque cookie. | |
4703 | */ | |
4704 | rmb(); | |
1da177e4 LT |
4705 | work_mask = 0; |
4706 | received = 0; | |
4361935a MC |
4707 | std_prod_idx = tpr->rx_std_prod_idx; |
4708 | jmb_prod_idx = tpr->rx_jmb_prod_idx; | |
1da177e4 | 4709 | while (sw_idx != hw_idx && budget > 0) { |
afc081f8 | 4710 | struct ring_info *ri; |
72334482 | 4711 | struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; |
1da177e4 LT |
4712 | unsigned int len; |
4713 | struct sk_buff *skb; | |
4714 | dma_addr_t dma_addr; | |
4715 | u32 opaque_key, desc_idx, *post_ptr; | |
4716 | ||
4717 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
4718 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
4719 | if (opaque_key == RXD_OPAQUE_RING_STD) { | |
8fea32b9 | 4720 | ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; |
4e5e4f0d | 4721 | dma_addr = dma_unmap_addr(ri, mapping); |
21f581a5 | 4722 | skb = ri->skb; |
4361935a | 4723 | post_ptr = &std_prod_idx; |
f92905de | 4724 | rx_std_posted++; |
1da177e4 | 4725 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { |
8fea32b9 | 4726 | ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; |
4e5e4f0d | 4727 | dma_addr = dma_unmap_addr(ri, mapping); |
21f581a5 | 4728 | skb = ri->skb; |
4361935a | 4729 | post_ptr = &jmb_prod_idx; |
21f581a5 | 4730 | } else |
1da177e4 | 4731 | goto next_pkt_nopost; |
1da177e4 LT |
4732 | |
4733 | work_mask |= opaque_key; | |
4734 | ||
4735 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
4736 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) { | |
4737 | drop_it: | |
a3896167 | 4738 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
4739 | desc_idx, *post_ptr); |
4740 | drop_it_no_recycle: | |
4741 | /* Other statistics kept track of by card. */ | |
b0057c51 | 4742 | tp->rx_dropped++; |
1da177e4 LT |
4743 | goto next_pkt; |
4744 | } | |
4745 | ||
ad829268 MC |
4746 | len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - |
4747 | ETH_FCS_LEN; | |
1da177e4 | 4748 | |
d2757fc4 | 4749 | if (len > TG3_RX_COPY_THRESH(tp)) { |
1da177e4 LT |
4750 | int skb_size; |
4751 | ||
86b21e59 | 4752 | skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key, |
afc081f8 | 4753 | *post_ptr); |
1da177e4 LT |
4754 | if (skb_size < 0) |
4755 | goto drop_it; | |
4756 | ||
287be12e | 4757 | pci_unmap_single(tp->pdev, dma_addr, skb_size, |
1da177e4 LT |
4758 | PCI_DMA_FROMDEVICE); |
4759 | ||
61e800cf MC |
4760 | /* Ensure that the update to the skb happens |
4761 | * after the usage of the old DMA mapping. | |
4762 | */ | |
4763 | smp_wmb(); | |
4764 | ||
4765 | ri->skb = NULL; | |
4766 | ||
1da177e4 LT |
4767 | skb_put(skb, len); |
4768 | } else { | |
4769 | struct sk_buff *copy_skb; | |
4770 | ||
a3896167 | 4771 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
4772 | desc_idx, *post_ptr); |
4773 | ||
bf933c80 | 4774 | copy_skb = netdev_alloc_skb(tp->dev, len + |
9dc7a113 | 4775 | TG3_RAW_IP_ALIGN); |
1da177e4 LT |
4776 | if (copy_skb == NULL) |
4777 | goto drop_it_no_recycle; | |
4778 | ||
bf933c80 | 4779 | skb_reserve(copy_skb, TG3_RAW_IP_ALIGN); |
1da177e4 LT |
4780 | skb_put(copy_skb, len); |
4781 | pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); | |
d626f62b | 4782 | skb_copy_from_linear_data(skb, copy_skb->data, len); |
1da177e4 LT |
4783 | pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); |
4784 | ||
4785 | /* We'll reuse the original ring buffer. */ | |
4786 | skb = copy_skb; | |
4787 | } | |
4788 | ||
4789 | if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) && | |
4790 | (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && | |
4791 | (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
4792 | >> RXD_TCPCSUM_SHIFT) == 0xffff)) | |
4793 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
4794 | else | |
bc8acf2c | 4795 | skb_checksum_none_assert(skb); |
1da177e4 LT |
4796 | |
4797 | skb->protocol = eth_type_trans(skb, tp->dev); | |
f7b493e0 MC |
4798 | |
4799 | if (len > (tp->dev->mtu + ETH_HLEN) && | |
4800 | skb->protocol != htons(ETH_P_8021Q)) { | |
4801 | dev_kfree_skb(skb); | |
b0057c51 | 4802 | goto drop_it_no_recycle; |
f7b493e0 MC |
4803 | } |
4804 | ||
9dc7a113 | 4805 | if (desc->type_flags & RXD_FLAG_VLAN && |
bf933c80 MC |
4806 | !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) |
4807 | __vlan_hwaccel_put_tag(skb, | |
4808 | desc->err_vlan & RXD_VLAN_MASK); | |
9dc7a113 | 4809 | |
bf933c80 | 4810 | napi_gro_receive(&tnapi->napi, skb); |
1da177e4 | 4811 | |
1da177e4 LT |
4812 | received++; |
4813 | budget--; | |
4814 | ||
4815 | next_pkt: | |
4816 | (*post_ptr)++; | |
f92905de MC |
4817 | |
4818 | if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { | |
2c49a44d MC |
4819 | tpr->rx_std_prod_idx = std_prod_idx & |
4820 | tp->rx_std_ring_mask; | |
86cfe4ff MC |
4821 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
4822 | tpr->rx_std_prod_idx); | |
f92905de MC |
4823 | work_mask &= ~RXD_OPAQUE_RING_STD; |
4824 | rx_std_posted = 0; | |
4825 | } | |
1da177e4 | 4826 | next_pkt_nopost: |
483ba50b | 4827 | sw_idx++; |
7cb32cf2 | 4828 | sw_idx &= tp->rx_ret_ring_mask; |
52f6d697 MC |
4829 | |
4830 | /* Refresh hw_idx to see if there is new work */ | |
4831 | if (sw_idx == hw_idx) { | |
8d9d7cfc | 4832 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
52f6d697 MC |
4833 | rmb(); |
4834 | } | |
1da177e4 LT |
4835 | } |
4836 | ||
4837 | /* ACK the status ring. */ | |
72334482 MC |
4838 | tnapi->rx_rcb_ptr = sw_idx; |
4839 | tw32_rx_mbox(tnapi->consmbox, sw_idx); | |
1da177e4 LT |
4840 | |
4841 | /* Refill RX ring(s). */ | |
e4af1af9 | 4842 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) { |
b196c7e4 | 4843 | if (work_mask & RXD_OPAQUE_RING_STD) { |
2c49a44d MC |
4844 | tpr->rx_std_prod_idx = std_prod_idx & |
4845 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
4846 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
4847 | tpr->rx_std_prod_idx); | |
4848 | } | |
4849 | if (work_mask & RXD_OPAQUE_RING_JUMBO) { | |
2c49a44d MC |
4850 | tpr->rx_jmb_prod_idx = jmb_prod_idx & |
4851 | tp->rx_jmb_ring_mask; | |
b196c7e4 MC |
4852 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, |
4853 | tpr->rx_jmb_prod_idx); | |
4854 | } | |
4855 | mmiowb(); | |
4856 | } else if (work_mask) { | |
4857 | /* rx_std_buffers[] and rx_jmb_buffers[] entries must be | |
4858 | * updated before the producer indices can be updated. | |
4859 | */ | |
4860 | smp_wmb(); | |
4861 | ||
2c49a44d MC |
4862 | tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; |
4863 | tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; | |
b196c7e4 | 4864 | |
e4af1af9 MC |
4865 | if (tnapi != &tp->napi[1]) |
4866 | napi_schedule(&tp->napi[1].napi); | |
1da177e4 | 4867 | } |
1da177e4 LT |
4868 | |
4869 | return received; | |
4870 | } | |
4871 | ||
35f2d7d0 | 4872 | static void tg3_poll_link(struct tg3 *tp) |
1da177e4 | 4873 | { |
1da177e4 LT |
4874 | /* handle link change and other phy events */ |
4875 | if (!(tp->tg3_flags & | |
4876 | (TG3_FLAG_USE_LINKCHG_REG | | |
4877 | TG3_FLAG_POLL_SERDES))) { | |
35f2d7d0 MC |
4878 | struct tg3_hw_status *sblk = tp->napi[0].hw_status; |
4879 | ||
1da177e4 LT |
4880 | if (sblk->status & SD_STATUS_LINK_CHG) { |
4881 | sblk->status = SD_STATUS_UPDATED | | |
35f2d7d0 | 4882 | (sblk->status & ~SD_STATUS_LINK_CHG); |
f47c11ee | 4883 | spin_lock(&tp->lock); |
dd477003 MC |
4884 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
4885 | tw32_f(MAC_STATUS, | |
4886 | (MAC_STATUS_SYNC_CHANGED | | |
4887 | MAC_STATUS_CFG_CHANGED | | |
4888 | MAC_STATUS_MI_COMPLETION | | |
4889 | MAC_STATUS_LNKSTATE_CHANGED)); | |
4890 | udelay(40); | |
4891 | } else | |
4892 | tg3_setup_phy(tp, 0); | |
f47c11ee | 4893 | spin_unlock(&tp->lock); |
1da177e4 LT |
4894 | } |
4895 | } | |
35f2d7d0 MC |
4896 | } |
4897 | ||
f89f38b8 MC |
4898 | static int tg3_rx_prodring_xfer(struct tg3 *tp, |
4899 | struct tg3_rx_prodring_set *dpr, | |
4900 | struct tg3_rx_prodring_set *spr) | |
b196c7e4 MC |
4901 | { |
4902 | u32 si, di, cpycnt, src_prod_idx; | |
f89f38b8 | 4903 | int i, err = 0; |
b196c7e4 MC |
4904 | |
4905 | while (1) { | |
4906 | src_prod_idx = spr->rx_std_prod_idx; | |
4907 | ||
4908 | /* Make sure updates to the rx_std_buffers[] entries and the | |
4909 | * standard producer index are seen in the correct order. | |
4910 | */ | |
4911 | smp_rmb(); | |
4912 | ||
4913 | if (spr->rx_std_cons_idx == src_prod_idx) | |
4914 | break; | |
4915 | ||
4916 | if (spr->rx_std_cons_idx < src_prod_idx) | |
4917 | cpycnt = src_prod_idx - spr->rx_std_cons_idx; | |
4918 | else | |
2c49a44d MC |
4919 | cpycnt = tp->rx_std_ring_mask + 1 - |
4920 | spr->rx_std_cons_idx; | |
b196c7e4 | 4921 | |
2c49a44d MC |
4922 | cpycnt = min(cpycnt, |
4923 | tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); | |
b196c7e4 MC |
4924 | |
4925 | si = spr->rx_std_cons_idx; | |
4926 | di = dpr->rx_std_prod_idx; | |
4927 | ||
e92967bf MC |
4928 | for (i = di; i < di + cpycnt; i++) { |
4929 | if (dpr->rx_std_buffers[i].skb) { | |
4930 | cpycnt = i - di; | |
f89f38b8 | 4931 | err = -ENOSPC; |
e92967bf MC |
4932 | break; |
4933 | } | |
4934 | } | |
4935 | ||
4936 | if (!cpycnt) | |
4937 | break; | |
4938 | ||
4939 | /* Ensure that updates to the rx_std_buffers ring and the | |
4940 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
4941 | * ordered correctly WRT the skb check above. | |
4942 | */ | |
4943 | smp_rmb(); | |
4944 | ||
b196c7e4 MC |
4945 | memcpy(&dpr->rx_std_buffers[di], |
4946 | &spr->rx_std_buffers[si], | |
4947 | cpycnt * sizeof(struct ring_info)); | |
4948 | ||
4949 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
4950 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
4951 | sbd = &spr->rx_std[si]; | |
4952 | dbd = &dpr->rx_std[di]; | |
4953 | dbd->addr_hi = sbd->addr_hi; | |
4954 | dbd->addr_lo = sbd->addr_lo; | |
4955 | } | |
4956 | ||
2c49a44d MC |
4957 | spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) & |
4958 | tp->rx_std_ring_mask; | |
4959 | dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) & | |
4960 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
4961 | } |
4962 | ||
4963 | while (1) { | |
4964 | src_prod_idx = spr->rx_jmb_prod_idx; | |
4965 | ||
4966 | /* Make sure updates to the rx_jmb_buffers[] entries and | |
4967 | * the jumbo producer index are seen in the correct order. | |
4968 | */ | |
4969 | smp_rmb(); | |
4970 | ||
4971 | if (spr->rx_jmb_cons_idx == src_prod_idx) | |
4972 | break; | |
4973 | ||
4974 | if (spr->rx_jmb_cons_idx < src_prod_idx) | |
4975 | cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; | |
4976 | else | |
2c49a44d MC |
4977 | cpycnt = tp->rx_jmb_ring_mask + 1 - |
4978 | spr->rx_jmb_cons_idx; | |
b196c7e4 MC |
4979 | |
4980 | cpycnt = min(cpycnt, | |
2c49a44d | 4981 | tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); |
b196c7e4 MC |
4982 | |
4983 | si = spr->rx_jmb_cons_idx; | |
4984 | di = dpr->rx_jmb_prod_idx; | |
4985 | ||
e92967bf MC |
4986 | for (i = di; i < di + cpycnt; i++) { |
4987 | if (dpr->rx_jmb_buffers[i].skb) { | |
4988 | cpycnt = i - di; | |
f89f38b8 | 4989 | err = -ENOSPC; |
e92967bf MC |
4990 | break; |
4991 | } | |
4992 | } | |
4993 | ||
4994 | if (!cpycnt) | |
4995 | break; | |
4996 | ||
4997 | /* Ensure that updates to the rx_jmb_buffers ring and the | |
4998 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
4999 | * ordered correctly WRT the skb check above. | |
5000 | */ | |
5001 | smp_rmb(); | |
5002 | ||
b196c7e4 MC |
5003 | memcpy(&dpr->rx_jmb_buffers[di], |
5004 | &spr->rx_jmb_buffers[si], | |
5005 | cpycnt * sizeof(struct ring_info)); | |
5006 | ||
5007 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
5008 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
5009 | sbd = &spr->rx_jmb[si].std; | |
5010 | dbd = &dpr->rx_jmb[di].std; | |
5011 | dbd->addr_hi = sbd->addr_hi; | |
5012 | dbd->addr_lo = sbd->addr_lo; | |
5013 | } | |
5014 | ||
2c49a44d MC |
5015 | spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) & |
5016 | tp->rx_jmb_ring_mask; | |
5017 | dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) & | |
5018 | tp->rx_jmb_ring_mask; | |
b196c7e4 | 5019 | } |
f89f38b8 MC |
5020 | |
5021 | return err; | |
b196c7e4 MC |
5022 | } |
5023 | ||
35f2d7d0 MC |
5024 | static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget) |
5025 | { | |
5026 | struct tg3 *tp = tnapi->tp; | |
1da177e4 LT |
5027 | |
5028 | /* run TX completion thread */ | |
f3f3f27e | 5029 | if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { |
17375d25 | 5030 | tg3_tx(tnapi); |
6f535763 | 5031 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) |
4fd7ab59 | 5032 | return work_done; |
1da177e4 LT |
5033 | } |
5034 | ||
1da177e4 LT |
5035 | /* run RX thread, within the bounds set by NAPI. |
5036 | * All RX "locking" is done by ensuring outside | |
bea3348e | 5037 | * code synchronizes with tg3->napi.poll() |
1da177e4 | 5038 | */ |
8d9d7cfc | 5039 | if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
17375d25 | 5040 | work_done += tg3_rx(tnapi, budget - work_done); |
1da177e4 | 5041 | |
b196c7e4 | 5042 | if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) { |
8fea32b9 | 5043 | struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; |
f89f38b8 | 5044 | int i, err = 0; |
e4af1af9 MC |
5045 | u32 std_prod_idx = dpr->rx_std_prod_idx; |
5046 | u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; | |
b196c7e4 | 5047 | |
e4af1af9 | 5048 | for (i = 1; i < tp->irq_cnt; i++) |
f89f38b8 | 5049 | err |= tg3_rx_prodring_xfer(tp, dpr, |
8fea32b9 | 5050 | &tp->napi[i].prodring); |
b196c7e4 MC |
5051 | |
5052 | wmb(); | |
5053 | ||
e4af1af9 MC |
5054 | if (std_prod_idx != dpr->rx_std_prod_idx) |
5055 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, | |
5056 | dpr->rx_std_prod_idx); | |
b196c7e4 | 5057 | |
e4af1af9 MC |
5058 | if (jmb_prod_idx != dpr->rx_jmb_prod_idx) |
5059 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, | |
5060 | dpr->rx_jmb_prod_idx); | |
b196c7e4 MC |
5061 | |
5062 | mmiowb(); | |
f89f38b8 MC |
5063 | |
5064 | if (err) | |
5065 | tw32_f(HOSTCC_MODE, tp->coal_now); | |
b196c7e4 MC |
5066 | } |
5067 | ||
6f535763 DM |
5068 | return work_done; |
5069 | } | |
5070 | ||
35f2d7d0 MC |
5071 | static int tg3_poll_msix(struct napi_struct *napi, int budget) |
5072 | { | |
5073 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); | |
5074 | struct tg3 *tp = tnapi->tp; | |
5075 | int work_done = 0; | |
5076 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
5077 | ||
5078 | while (1) { | |
5079 | work_done = tg3_poll_work(tnapi, work_done, budget); | |
5080 | ||
5081 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) | |
5082 | goto tx_recovery; | |
5083 | ||
5084 | if (unlikely(work_done >= budget)) | |
5085 | break; | |
5086 | ||
c6cdf436 | 5087 | /* tp->last_tag is used in tg3_int_reenable() below |
35f2d7d0 MC |
5088 | * to tell the hw how much work has been processed, |
5089 | * so we must read it before checking for more work. | |
5090 | */ | |
5091 | tnapi->last_tag = sblk->status_tag; | |
5092 | tnapi->last_irq_tag = tnapi->last_tag; | |
5093 | rmb(); | |
5094 | ||
5095 | /* check for RX/TX work to do */ | |
6d40db7b MC |
5096 | if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && |
5097 | *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { | |
35f2d7d0 MC |
5098 | napi_complete(napi); |
5099 | /* Reenable interrupts. */ | |
5100 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); | |
5101 | mmiowb(); | |
5102 | break; | |
5103 | } | |
5104 | } | |
5105 | ||
5106 | return work_done; | |
5107 | ||
5108 | tx_recovery: | |
5109 | /* work_done is guaranteed to be less than budget. */ | |
5110 | napi_complete(napi); | |
5111 | schedule_work(&tp->reset_task); | |
5112 | return work_done; | |
5113 | } | |
5114 | ||
6f535763 DM |
5115 | static int tg3_poll(struct napi_struct *napi, int budget) |
5116 | { | |
8ef0442f MC |
5117 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); |
5118 | struct tg3 *tp = tnapi->tp; | |
6f535763 | 5119 | int work_done = 0; |
898a56f8 | 5120 | struct tg3_hw_status *sblk = tnapi->hw_status; |
6f535763 DM |
5121 | |
5122 | while (1) { | |
35f2d7d0 MC |
5123 | tg3_poll_link(tp); |
5124 | ||
17375d25 | 5125 | work_done = tg3_poll_work(tnapi, work_done, budget); |
6f535763 DM |
5126 | |
5127 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) | |
5128 | goto tx_recovery; | |
5129 | ||
5130 | if (unlikely(work_done >= budget)) | |
5131 | break; | |
5132 | ||
4fd7ab59 | 5133 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) { |
17375d25 | 5134 | /* tp->last_tag is used in tg3_int_reenable() below |
4fd7ab59 MC |
5135 | * to tell the hw how much work has been processed, |
5136 | * so we must read it before checking for more work. | |
5137 | */ | |
898a56f8 MC |
5138 | tnapi->last_tag = sblk->status_tag; |
5139 | tnapi->last_irq_tag = tnapi->last_tag; | |
4fd7ab59 MC |
5140 | rmb(); |
5141 | } else | |
5142 | sblk->status &= ~SD_STATUS_UPDATED; | |
6f535763 | 5143 | |
17375d25 | 5144 | if (likely(!tg3_has_work(tnapi))) { |
288379f0 | 5145 | napi_complete(napi); |
17375d25 | 5146 | tg3_int_reenable(tnapi); |
6f535763 DM |
5147 | break; |
5148 | } | |
1da177e4 LT |
5149 | } |
5150 | ||
bea3348e | 5151 | return work_done; |
6f535763 DM |
5152 | |
5153 | tx_recovery: | |
4fd7ab59 | 5154 | /* work_done is guaranteed to be less than budget. */ |
288379f0 | 5155 | napi_complete(napi); |
6f535763 | 5156 | schedule_work(&tp->reset_task); |
4fd7ab59 | 5157 | return work_done; |
1da177e4 LT |
5158 | } |
5159 | ||
66cfd1bd MC |
5160 | static void tg3_napi_disable(struct tg3 *tp) |
5161 | { | |
5162 | int i; | |
5163 | ||
5164 | for (i = tp->irq_cnt - 1; i >= 0; i--) | |
5165 | napi_disable(&tp->napi[i].napi); | |
5166 | } | |
5167 | ||
5168 | static void tg3_napi_enable(struct tg3 *tp) | |
5169 | { | |
5170 | int i; | |
5171 | ||
5172 | for (i = 0; i < tp->irq_cnt; i++) | |
5173 | napi_enable(&tp->napi[i].napi); | |
5174 | } | |
5175 | ||
5176 | static void tg3_napi_init(struct tg3 *tp) | |
5177 | { | |
5178 | int i; | |
5179 | ||
5180 | netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64); | |
5181 | for (i = 1; i < tp->irq_cnt; i++) | |
5182 | netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64); | |
5183 | } | |
5184 | ||
5185 | static void tg3_napi_fini(struct tg3 *tp) | |
5186 | { | |
5187 | int i; | |
5188 | ||
5189 | for (i = 0; i < tp->irq_cnt; i++) | |
5190 | netif_napi_del(&tp->napi[i].napi); | |
5191 | } | |
5192 | ||
5193 | static inline void tg3_netif_stop(struct tg3 *tp) | |
5194 | { | |
5195 | tp->dev->trans_start = jiffies; /* prevent tx timeout */ | |
5196 | tg3_napi_disable(tp); | |
5197 | netif_tx_disable(tp->dev); | |
5198 | } | |
5199 | ||
5200 | static inline void tg3_netif_start(struct tg3 *tp) | |
5201 | { | |
5202 | /* NOTE: unconditional netif_tx_wake_all_queues is only | |
5203 | * appropriate so long as all callers are assured to | |
5204 | * have free tx slots (such as after tg3_init_hw) | |
5205 | */ | |
5206 | netif_tx_wake_all_queues(tp->dev); | |
5207 | ||
5208 | tg3_napi_enable(tp); | |
5209 | tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; | |
5210 | tg3_enable_ints(tp); | |
5211 | } | |
5212 | ||
f47c11ee DM |
5213 | static void tg3_irq_quiesce(struct tg3 *tp) |
5214 | { | |
4f125f42 MC |
5215 | int i; |
5216 | ||
f47c11ee DM |
5217 | BUG_ON(tp->irq_sync); |
5218 | ||
5219 | tp->irq_sync = 1; | |
5220 | smp_mb(); | |
5221 | ||
4f125f42 MC |
5222 | for (i = 0; i < tp->irq_cnt; i++) |
5223 | synchronize_irq(tp->napi[i].irq_vec); | |
f47c11ee DM |
5224 | } |
5225 | ||
f47c11ee DM |
5226 | /* Fully shutdown all tg3 driver activity elsewhere in the system. |
5227 | * If irq_sync is non-zero, then the IRQ handler must be synchronized | |
5228 | * with as well. Most of the time, this is not necessary except when | |
5229 | * shutting down the device. | |
5230 | */ | |
5231 | static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) | |
5232 | { | |
46966545 | 5233 | spin_lock_bh(&tp->lock); |
f47c11ee DM |
5234 | if (irq_sync) |
5235 | tg3_irq_quiesce(tp); | |
f47c11ee DM |
5236 | } |
5237 | ||
5238 | static inline void tg3_full_unlock(struct tg3 *tp) | |
5239 | { | |
f47c11ee DM |
5240 | spin_unlock_bh(&tp->lock); |
5241 | } | |
5242 | ||
fcfa0a32 MC |
5243 | /* One-shot MSI handler - Chip automatically disables interrupt |
5244 | * after sending MSI so driver doesn't have to do it. | |
5245 | */ | |
7d12e780 | 5246 | static irqreturn_t tg3_msi_1shot(int irq, void *dev_id) |
fcfa0a32 | 5247 | { |
09943a18 MC |
5248 | struct tg3_napi *tnapi = dev_id; |
5249 | struct tg3 *tp = tnapi->tp; | |
fcfa0a32 | 5250 | |
898a56f8 | 5251 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
5252 | if (tnapi->rx_rcb) |
5253 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
fcfa0a32 MC |
5254 | |
5255 | if (likely(!tg3_irq_sync(tp))) | |
09943a18 | 5256 | napi_schedule(&tnapi->napi); |
fcfa0a32 MC |
5257 | |
5258 | return IRQ_HANDLED; | |
5259 | } | |
5260 | ||
88b06bc2 MC |
5261 | /* MSI ISR - No need to check for interrupt sharing and no need to |
5262 | * flush status block and interrupt mailbox. PCI ordering rules | |
5263 | * guarantee that MSI will arrive after the status block. | |
5264 | */ | |
7d12e780 | 5265 | static irqreturn_t tg3_msi(int irq, void *dev_id) |
88b06bc2 | 5266 | { |
09943a18 MC |
5267 | struct tg3_napi *tnapi = dev_id; |
5268 | struct tg3 *tp = tnapi->tp; | |
88b06bc2 | 5269 | |
898a56f8 | 5270 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
5271 | if (tnapi->rx_rcb) |
5272 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
88b06bc2 | 5273 | /* |
fac9b83e | 5274 | * Writing any value to intr-mbox-0 clears PCI INTA# and |
88b06bc2 | 5275 | * chip-internal interrupt pending events. |
fac9b83e | 5276 | * Writing non-zero to intr-mbox-0 additional tells the |
88b06bc2 MC |
5277 | * NIC to stop sending us irqs, engaging "in-intr-handler" |
5278 | * event coalescing. | |
5279 | */ | |
5280 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); | |
61487480 | 5281 | if (likely(!tg3_irq_sync(tp))) |
09943a18 | 5282 | napi_schedule(&tnapi->napi); |
61487480 | 5283 | |
88b06bc2 MC |
5284 | return IRQ_RETVAL(1); |
5285 | } | |
5286 | ||
7d12e780 | 5287 | static irqreturn_t tg3_interrupt(int irq, void *dev_id) |
1da177e4 | 5288 | { |
09943a18 MC |
5289 | struct tg3_napi *tnapi = dev_id; |
5290 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5291 | struct tg3_hw_status *sblk = tnapi->hw_status; |
1da177e4 LT |
5292 | unsigned int handled = 1; |
5293 | ||
1da177e4 LT |
5294 | /* In INTx mode, it is possible for the interrupt to arrive at |
5295 | * the CPU before the status block posted prior to the interrupt. | |
5296 | * Reading the PCI State register will confirm whether the | |
5297 | * interrupt is ours and will flush the status block. | |
5298 | */ | |
d18edcb2 MC |
5299 | if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { |
5300 | if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) || | |
5301 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
5302 | handled = 0; | |
f47c11ee | 5303 | goto out; |
fac9b83e | 5304 | } |
d18edcb2 MC |
5305 | } |
5306 | ||
5307 | /* | |
5308 | * Writing any value to intr-mbox-0 clears PCI INTA# and | |
5309 | * chip-internal interrupt pending events. | |
5310 | * Writing non-zero to intr-mbox-0 additional tells the | |
5311 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
5312 | * event coalescing. | |
c04cb347 MC |
5313 | * |
5314 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
5315 | * spurious interrupts. The flush impacts performance but | |
5316 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 5317 | */ |
c04cb347 | 5318 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
d18edcb2 MC |
5319 | if (tg3_irq_sync(tp)) |
5320 | goto out; | |
5321 | sblk->status &= ~SD_STATUS_UPDATED; | |
17375d25 | 5322 | if (likely(tg3_has_work(tnapi))) { |
72334482 | 5323 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
09943a18 | 5324 | napi_schedule(&tnapi->napi); |
d18edcb2 MC |
5325 | } else { |
5326 | /* No work, shared interrupt perhaps? re-enable | |
5327 | * interrupts, and flush that PCI write | |
5328 | */ | |
5329 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | |
5330 | 0x00000000); | |
fac9b83e | 5331 | } |
f47c11ee | 5332 | out: |
fac9b83e DM |
5333 | return IRQ_RETVAL(handled); |
5334 | } | |
5335 | ||
7d12e780 | 5336 | static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) |
fac9b83e | 5337 | { |
09943a18 MC |
5338 | struct tg3_napi *tnapi = dev_id; |
5339 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5340 | struct tg3_hw_status *sblk = tnapi->hw_status; |
fac9b83e DM |
5341 | unsigned int handled = 1; |
5342 | ||
fac9b83e DM |
5343 | /* In INTx mode, it is possible for the interrupt to arrive at |
5344 | * the CPU before the status block posted prior to the interrupt. | |
5345 | * Reading the PCI State register will confirm whether the | |
5346 | * interrupt is ours and will flush the status block. | |
5347 | */ | |
898a56f8 | 5348 | if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { |
d18edcb2 MC |
5349 | if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) || |
5350 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
5351 | handled = 0; | |
f47c11ee | 5352 | goto out; |
1da177e4 | 5353 | } |
d18edcb2 MC |
5354 | } |
5355 | ||
5356 | /* | |
5357 | * writing any value to intr-mbox-0 clears PCI INTA# and | |
5358 | * chip-internal interrupt pending events. | |
5359 | * writing non-zero to intr-mbox-0 additional tells the | |
5360 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
5361 | * event coalescing. | |
c04cb347 MC |
5362 | * |
5363 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
5364 | * spurious interrupts. The flush impacts performance but | |
5365 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 5366 | */ |
c04cb347 | 5367 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
624f8e50 MC |
5368 | |
5369 | /* | |
5370 | * In a shared interrupt configuration, sometimes other devices' | |
5371 | * interrupts will scream. We record the current status tag here | |
5372 | * so that the above check can report that the screaming interrupts | |
5373 | * are unhandled. Eventually they will be silenced. | |
5374 | */ | |
898a56f8 | 5375 | tnapi->last_irq_tag = sblk->status_tag; |
624f8e50 | 5376 | |
d18edcb2 MC |
5377 | if (tg3_irq_sync(tp)) |
5378 | goto out; | |
624f8e50 | 5379 | |
72334482 | 5380 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
624f8e50 | 5381 | |
09943a18 | 5382 | napi_schedule(&tnapi->napi); |
624f8e50 | 5383 | |
f47c11ee | 5384 | out: |
1da177e4 LT |
5385 | return IRQ_RETVAL(handled); |
5386 | } | |
5387 | ||
7938109f | 5388 | /* ISR for interrupt test */ |
7d12e780 | 5389 | static irqreturn_t tg3_test_isr(int irq, void *dev_id) |
7938109f | 5390 | { |
09943a18 MC |
5391 | struct tg3_napi *tnapi = dev_id; |
5392 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5393 | struct tg3_hw_status *sblk = tnapi->hw_status; |
7938109f | 5394 | |
f9804ddb MC |
5395 | if ((sblk->status & SD_STATUS_UPDATED) || |
5396 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
b16250e3 | 5397 | tg3_disable_ints(tp); |
7938109f MC |
5398 | return IRQ_RETVAL(1); |
5399 | } | |
5400 | return IRQ_RETVAL(0); | |
5401 | } | |
5402 | ||
8e7a22e3 | 5403 | static int tg3_init_hw(struct tg3 *, int); |
944d980e | 5404 | static int tg3_halt(struct tg3 *, int, int); |
1da177e4 | 5405 | |
b9ec6c1b MC |
5406 | /* Restart hardware after configuration changes, self-test, etc. |
5407 | * Invoked with tp->lock held. | |
5408 | */ | |
5409 | static int tg3_restart_hw(struct tg3 *tp, int reset_phy) | |
78c6146f ED |
5410 | __releases(tp->lock) |
5411 | __acquires(tp->lock) | |
b9ec6c1b MC |
5412 | { |
5413 | int err; | |
5414 | ||
5415 | err = tg3_init_hw(tp, reset_phy); | |
5416 | if (err) { | |
5129c3a3 MC |
5417 | netdev_err(tp->dev, |
5418 | "Failed to re-initialize device, aborting\n"); | |
b9ec6c1b MC |
5419 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
5420 | tg3_full_unlock(tp); | |
5421 | del_timer_sync(&tp->timer); | |
5422 | tp->irq_sync = 0; | |
fed97810 | 5423 | tg3_napi_enable(tp); |
b9ec6c1b MC |
5424 | dev_close(tp->dev); |
5425 | tg3_full_lock(tp, 0); | |
5426 | } | |
5427 | return err; | |
5428 | } | |
5429 | ||
1da177e4 LT |
5430 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5431 | static void tg3_poll_controller(struct net_device *dev) | |
5432 | { | |
4f125f42 | 5433 | int i; |
88b06bc2 MC |
5434 | struct tg3 *tp = netdev_priv(dev); |
5435 | ||
4f125f42 | 5436 | for (i = 0; i < tp->irq_cnt; i++) |
fe234f0e | 5437 | tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); |
1da177e4 LT |
5438 | } |
5439 | #endif | |
5440 | ||
c4028958 | 5441 | static void tg3_reset_task(struct work_struct *work) |
1da177e4 | 5442 | { |
c4028958 | 5443 | struct tg3 *tp = container_of(work, struct tg3, reset_task); |
b02fd9e3 | 5444 | int err; |
1da177e4 LT |
5445 | unsigned int restart_timer; |
5446 | ||
7faa006f | 5447 | tg3_full_lock(tp, 0); |
7faa006f MC |
5448 | |
5449 | if (!netif_running(tp->dev)) { | |
7faa006f MC |
5450 | tg3_full_unlock(tp); |
5451 | return; | |
5452 | } | |
5453 | ||
5454 | tg3_full_unlock(tp); | |
5455 | ||
b02fd9e3 MC |
5456 | tg3_phy_stop(tp); |
5457 | ||
1da177e4 LT |
5458 | tg3_netif_stop(tp); |
5459 | ||
f47c11ee | 5460 | tg3_full_lock(tp, 1); |
1da177e4 LT |
5461 | |
5462 | restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER; | |
5463 | tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER; | |
5464 | ||
df3e6548 MC |
5465 | if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) { |
5466 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | |
5467 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
5468 | tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; | |
5469 | tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING; | |
5470 | } | |
5471 | ||
944d980e | 5472 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); |
b02fd9e3 MC |
5473 | err = tg3_init_hw(tp, 1); |
5474 | if (err) | |
b9ec6c1b | 5475 | goto out; |
1da177e4 LT |
5476 | |
5477 | tg3_netif_start(tp); | |
5478 | ||
1da177e4 LT |
5479 | if (restart_timer) |
5480 | mod_timer(&tp->timer, jiffies + 1); | |
7faa006f | 5481 | |
b9ec6c1b | 5482 | out: |
7faa006f | 5483 | tg3_full_unlock(tp); |
b02fd9e3 MC |
5484 | |
5485 | if (!err) | |
5486 | tg3_phy_start(tp); | |
1da177e4 LT |
5487 | } |
5488 | ||
b0408751 MC |
5489 | static void tg3_dump_short_state(struct tg3 *tp) |
5490 | { | |
05dbe005 JP |
5491 | netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n", |
5492 | tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS)); | |
5493 | netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n", | |
5494 | tr32(RDMAC_STATUS), tr32(WDMAC_STATUS)); | |
b0408751 MC |
5495 | } |
5496 | ||
1da177e4 LT |
5497 | static void tg3_tx_timeout(struct net_device *dev) |
5498 | { | |
5499 | struct tg3 *tp = netdev_priv(dev); | |
5500 | ||
b0408751 | 5501 | if (netif_msg_tx_err(tp)) { |
05dbe005 | 5502 | netdev_err(dev, "transmit timed out, resetting\n"); |
b0408751 MC |
5503 | tg3_dump_short_state(tp); |
5504 | } | |
1da177e4 LT |
5505 | |
5506 | schedule_work(&tp->reset_task); | |
5507 | } | |
5508 | ||
c58ec932 MC |
5509 | /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */ |
5510 | static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len) | |
5511 | { | |
5512 | u32 base = (u32) mapping & 0xffffffff; | |
5513 | ||
807540ba | 5514 | return (base > 0xffffdcc0) && (base + len + 8 < base); |
c58ec932 MC |
5515 | } |
5516 | ||
72f2afb8 MC |
5517 | /* Test for DMA addresses > 40-bit */ |
5518 | static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, | |
5519 | int len) | |
5520 | { | |
5521 | #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) | |
6728a8e2 | 5522 | if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) |
807540ba | 5523 | return ((u64) mapping + len) > DMA_BIT_MASK(40); |
72f2afb8 MC |
5524 | return 0; |
5525 | #else | |
5526 | return 0; | |
5527 | #endif | |
5528 | } | |
5529 | ||
f3f3f27e | 5530 | static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32); |
1da177e4 | 5531 | |
72f2afb8 | 5532 | /* Workaround 4GB and 40-bit hardware DMA bugs. */ |
24f4efd4 MC |
5533 | static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi, |
5534 | struct sk_buff *skb, u32 last_plus_one, | |
5535 | u32 *start, u32 base_flags, u32 mss) | |
1da177e4 | 5536 | { |
24f4efd4 | 5537 | struct tg3 *tp = tnapi->tp; |
41588ba1 | 5538 | struct sk_buff *new_skb; |
c58ec932 | 5539 | dma_addr_t new_addr = 0; |
1da177e4 | 5540 | u32 entry = *start; |
c58ec932 | 5541 | int i, ret = 0; |
1da177e4 | 5542 | |
41588ba1 MC |
5543 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) |
5544 | new_skb = skb_copy(skb, GFP_ATOMIC); | |
5545 | else { | |
5546 | int more_headroom = 4 - ((unsigned long)skb->data & 3); | |
5547 | ||
5548 | new_skb = skb_copy_expand(skb, | |
5549 | skb_headroom(skb) + more_headroom, | |
5550 | skb_tailroom(skb), GFP_ATOMIC); | |
5551 | } | |
5552 | ||
1da177e4 | 5553 | if (!new_skb) { |
c58ec932 MC |
5554 | ret = -1; |
5555 | } else { | |
5556 | /* New SKB is guaranteed to be linear. */ | |
5557 | entry = *start; | |
f4188d8a AD |
5558 | new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len, |
5559 | PCI_DMA_TODEVICE); | |
5560 | /* Make sure the mapping succeeded */ | |
5561 | if (pci_dma_mapping_error(tp->pdev, new_addr)) { | |
5562 | ret = -1; | |
5563 | dev_kfree_skb(new_skb); | |
5564 | new_skb = NULL; | |
90079ce8 | 5565 | |
c58ec932 MC |
5566 | /* Make sure new skb does not cross any 4G boundaries. |
5567 | * Drop the packet if it does. | |
5568 | */ | |
f4188d8a AD |
5569 | } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && |
5570 | tg3_4g_overflow_test(new_addr, new_skb->len)) { | |
5571 | pci_unmap_single(tp->pdev, new_addr, new_skb->len, | |
5572 | PCI_DMA_TODEVICE); | |
c58ec932 MC |
5573 | ret = -1; |
5574 | dev_kfree_skb(new_skb); | |
5575 | new_skb = NULL; | |
5576 | } else { | |
f3f3f27e | 5577 | tg3_set_txd(tnapi, entry, new_addr, new_skb->len, |
c58ec932 MC |
5578 | base_flags, 1 | (mss << 1)); |
5579 | *start = NEXT_TX(entry); | |
5580 | } | |
1da177e4 LT |
5581 | } |
5582 | ||
1da177e4 LT |
5583 | /* Now clean up the sw ring entries. */ |
5584 | i = 0; | |
5585 | while (entry != last_plus_one) { | |
f4188d8a AD |
5586 | int len; |
5587 | ||
f3f3f27e | 5588 | if (i == 0) |
f4188d8a | 5589 | len = skb_headlen(skb); |
f3f3f27e | 5590 | else |
f4188d8a AD |
5591 | len = skb_shinfo(skb)->frags[i-1].size; |
5592 | ||
5593 | pci_unmap_single(tp->pdev, | |
4e5e4f0d | 5594 | dma_unmap_addr(&tnapi->tx_buffers[entry], |
f4188d8a AD |
5595 | mapping), |
5596 | len, PCI_DMA_TODEVICE); | |
5597 | if (i == 0) { | |
5598 | tnapi->tx_buffers[entry].skb = new_skb; | |
4e5e4f0d | 5599 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, |
f4188d8a AD |
5600 | new_addr); |
5601 | } else { | |
f3f3f27e | 5602 | tnapi->tx_buffers[entry].skb = NULL; |
f4188d8a | 5603 | } |
1da177e4 LT |
5604 | entry = NEXT_TX(entry); |
5605 | i++; | |
5606 | } | |
5607 | ||
5608 | dev_kfree_skb(skb); | |
5609 | ||
c58ec932 | 5610 | return ret; |
1da177e4 LT |
5611 | } |
5612 | ||
f3f3f27e | 5613 | static void tg3_set_txd(struct tg3_napi *tnapi, int entry, |
1da177e4 LT |
5614 | dma_addr_t mapping, int len, u32 flags, |
5615 | u32 mss_and_is_end) | |
5616 | { | |
f3f3f27e | 5617 | struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry]; |
1da177e4 LT |
5618 | int is_end = (mss_and_is_end & 0x1); |
5619 | u32 mss = (mss_and_is_end >> 1); | |
5620 | u32 vlan_tag = 0; | |
5621 | ||
5622 | if (is_end) | |
5623 | flags |= TXD_FLAG_END; | |
5624 | if (flags & TXD_FLAG_VLAN) { | |
5625 | vlan_tag = flags >> 16; | |
5626 | flags &= 0xffff; | |
5627 | } | |
5628 | vlan_tag |= (mss << TXD_MSS_SHIFT); | |
5629 | ||
5630 | txd->addr_hi = ((u64) mapping >> 32); | |
5631 | txd->addr_lo = ((u64) mapping & 0xffffffff); | |
5632 | txd->len_flags = (len << TXD_LEN_SHIFT) | flags; | |
5633 | txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT; | |
5634 | } | |
5635 | ||
5a6f3074 | 5636 | /* hard_start_xmit for devices that don't have any bugs and |
e849cdc3 | 5637 | * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only. |
5a6f3074 | 5638 | */ |
61357325 SH |
5639 | static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, |
5640 | struct net_device *dev) | |
5a6f3074 MC |
5641 | { |
5642 | struct tg3 *tp = netdev_priv(dev); | |
5a6f3074 | 5643 | u32 len, entry, base_flags, mss; |
90079ce8 | 5644 | dma_addr_t mapping; |
fe5f5787 MC |
5645 | struct tg3_napi *tnapi; |
5646 | struct netdev_queue *txq; | |
f4188d8a AD |
5647 | unsigned int i, last; |
5648 | ||
fe5f5787 MC |
5649 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); |
5650 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; | |
19cfaecc | 5651 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
fe5f5787 | 5652 | tnapi++; |
5a6f3074 | 5653 | |
00b70504 | 5654 | /* We are running in BH disabled context with netif_tx_lock |
bea3348e | 5655 | * and TX reclaim runs via tp->napi.poll inside of a software |
5a6f3074 MC |
5656 | * interrupt. Furthermore, IRQ processing runs lockless so we have |
5657 | * no IRQ context deadlocks to worry about either. Rejoice! | |
5658 | */ | |
f3f3f27e | 5659 | if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) { |
fe5f5787 MC |
5660 | if (!netif_tx_queue_stopped(txq)) { |
5661 | netif_tx_stop_queue(txq); | |
5a6f3074 MC |
5662 | |
5663 | /* This is a hard error, log it. */ | |
5129c3a3 MC |
5664 | netdev_err(dev, |
5665 | "BUG! Tx Ring full when queue awake!\n"); | |
5a6f3074 | 5666 | } |
5a6f3074 MC |
5667 | return NETDEV_TX_BUSY; |
5668 | } | |
5669 | ||
f3f3f27e | 5670 | entry = tnapi->tx_prod; |
5a6f3074 | 5671 | base_flags = 0; |
be98da6a MC |
5672 | mss = skb_shinfo(skb)->gso_size; |
5673 | if (mss) { | |
5a6f3074 | 5674 | int tcp_opt_len, ip_tcp_len; |
f6eb9b1f | 5675 | u32 hdrlen; |
5a6f3074 MC |
5676 | |
5677 | if (skb_header_cloned(skb) && | |
5678 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
5679 | dev_kfree_skb(skb); | |
5680 | goto out_unlock; | |
5681 | } | |
5682 | ||
02e96080 | 5683 | if (skb_is_gso_v6(skb)) { |
f6eb9b1f | 5684 | hdrlen = skb_headlen(skb) - ETH_HLEN; |
02e96080 | 5685 | } else { |
eddc9ec5 ACM |
5686 | struct iphdr *iph = ip_hdr(skb); |
5687 | ||
ab6a5bb6 | 5688 | tcp_opt_len = tcp_optlen(skb); |
c9bdd4b5 | 5689 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); |
b0026624 | 5690 | |
eddc9ec5 ACM |
5691 | iph->check = 0; |
5692 | iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len); | |
f6eb9b1f | 5693 | hdrlen = ip_tcp_len + tcp_opt_len; |
b0026624 | 5694 | } |
5a6f3074 | 5695 | |
e849cdc3 | 5696 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) { |
f6eb9b1f MC |
5697 | mss |= (hdrlen & 0xc) << 12; |
5698 | if (hdrlen & 0x10) | |
5699 | base_flags |= 0x00000010; | |
5700 | base_flags |= (hdrlen & 0x3e0) << 5; | |
5701 | } else | |
5702 | mss |= hdrlen << 9; | |
5703 | ||
5a6f3074 MC |
5704 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | |
5705 | TXD_FLAG_CPU_POST_DMA); | |
5706 | ||
aa8223c7 | 5707 | tcp_hdr(skb)->check = 0; |
5a6f3074 | 5708 | |
859a5887 | 5709 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
5a6f3074 | 5710 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
859a5887 MC |
5711 | } |
5712 | ||
eab6d18d | 5713 | if (vlan_tx_tag_present(skb)) |
5a6f3074 MC |
5714 | base_flags |= (TXD_FLAG_VLAN | |
5715 | (vlan_tx_tag_get(skb) << 16)); | |
5a6f3074 | 5716 | |
f4188d8a AD |
5717 | len = skb_headlen(skb); |
5718 | ||
5719 | /* Queue skb data, a.k.a. the main skb fragment. */ | |
5720 | mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
5721 | if (pci_dma_mapping_error(tp->pdev, mapping)) { | |
90079ce8 DM |
5722 | dev_kfree_skb(skb); |
5723 | goto out_unlock; | |
5724 | } | |
5725 | ||
f3f3f27e | 5726 | tnapi->tx_buffers[entry].skb = skb; |
4e5e4f0d | 5727 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); |
fe5f5787 | 5728 | |
b703df6f | 5729 | if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) && |
8fc2f995 | 5730 | !mss && skb->len > VLAN_ETH_FRAME_LEN) |
f6eb9b1f MC |
5731 | base_flags |= TXD_FLAG_JMB_PKT; |
5732 | ||
f3f3f27e | 5733 | tg3_set_txd(tnapi, entry, mapping, len, base_flags, |
5a6f3074 MC |
5734 | (skb_shinfo(skb)->nr_frags == 0) | (mss << 1)); |
5735 | ||
5736 | entry = NEXT_TX(entry); | |
5737 | ||
5738 | /* Now loop through additional data fragments, and queue them. */ | |
5739 | if (skb_shinfo(skb)->nr_frags > 0) { | |
5a6f3074 MC |
5740 | last = skb_shinfo(skb)->nr_frags - 1; |
5741 | for (i = 0; i <= last; i++) { | |
5742 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5743 | ||
5744 | len = frag->size; | |
f4188d8a AD |
5745 | mapping = pci_map_page(tp->pdev, |
5746 | frag->page, | |
5747 | frag->page_offset, | |
5748 | len, PCI_DMA_TODEVICE); | |
5749 | if (pci_dma_mapping_error(tp->pdev, mapping)) | |
5750 | goto dma_error; | |
5751 | ||
f3f3f27e | 5752 | tnapi->tx_buffers[entry].skb = NULL; |
4e5e4f0d | 5753 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, |
f4188d8a | 5754 | mapping); |
5a6f3074 | 5755 | |
f3f3f27e | 5756 | tg3_set_txd(tnapi, entry, mapping, len, |
5a6f3074 MC |
5757 | base_flags, (i == last) | (mss << 1)); |
5758 | ||
5759 | entry = NEXT_TX(entry); | |
5760 | } | |
5761 | } | |
5762 | ||
5763 | /* Packets are ready, update Tx producer idx local and on card. */ | |
f3f3f27e | 5764 | tw32_tx_mbox(tnapi->prodmbox, entry); |
5a6f3074 | 5765 | |
f3f3f27e MC |
5766 | tnapi->tx_prod = entry; |
5767 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
fe5f5787 | 5768 | netif_tx_stop_queue(txq); |
f65aac16 MC |
5769 | |
5770 | /* netif_tx_stop_queue() must be done before checking | |
5771 | * checking tx index in tg3_tx_avail() below, because in | |
5772 | * tg3_tx(), we update tx index before checking for | |
5773 | * netif_tx_queue_stopped(). | |
5774 | */ | |
5775 | smp_mb(); | |
f3f3f27e | 5776 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) |
fe5f5787 | 5777 | netif_tx_wake_queue(txq); |
5a6f3074 MC |
5778 | } |
5779 | ||
5780 | out_unlock: | |
cdd0db05 | 5781 | mmiowb(); |
5a6f3074 MC |
5782 | |
5783 | return NETDEV_TX_OK; | |
f4188d8a AD |
5784 | |
5785 | dma_error: | |
5786 | last = i; | |
5787 | entry = tnapi->tx_prod; | |
5788 | tnapi->tx_buffers[entry].skb = NULL; | |
5789 | pci_unmap_single(tp->pdev, | |
4e5e4f0d | 5790 | dma_unmap_addr(&tnapi->tx_buffers[entry], mapping), |
f4188d8a AD |
5791 | skb_headlen(skb), |
5792 | PCI_DMA_TODEVICE); | |
5793 | for (i = 0; i <= last; i++) { | |
5794 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5795 | entry = NEXT_TX(entry); | |
5796 | ||
5797 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 5798 | dma_unmap_addr(&tnapi->tx_buffers[entry], |
f4188d8a AD |
5799 | mapping), |
5800 | frag->size, PCI_DMA_TODEVICE); | |
5801 | } | |
5802 | ||
5803 | dev_kfree_skb(skb); | |
5804 | return NETDEV_TX_OK; | |
5a6f3074 MC |
5805 | } |
5806 | ||
61357325 SH |
5807 | static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *, |
5808 | struct net_device *); | |
52c0fd83 MC |
5809 | |
5810 | /* Use GSO to workaround a rare TSO bug that may be triggered when the | |
5811 | * TSO header is greater than 80 bytes. | |
5812 | */ | |
5813 | static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb) | |
5814 | { | |
5815 | struct sk_buff *segs, *nskb; | |
f3f3f27e | 5816 | u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; |
52c0fd83 MC |
5817 | |
5818 | /* Estimate the number of fragments in the worst case */ | |
f3f3f27e | 5819 | if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) { |
52c0fd83 | 5820 | netif_stop_queue(tp->dev); |
f65aac16 MC |
5821 | |
5822 | /* netif_tx_stop_queue() must be done before checking | |
5823 | * checking tx index in tg3_tx_avail() below, because in | |
5824 | * tg3_tx(), we update tx index before checking for | |
5825 | * netif_tx_queue_stopped(). | |
5826 | */ | |
5827 | smp_mb(); | |
f3f3f27e | 5828 | if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est) |
7f62ad5d MC |
5829 | return NETDEV_TX_BUSY; |
5830 | ||
5831 | netif_wake_queue(tp->dev); | |
52c0fd83 MC |
5832 | } |
5833 | ||
5834 | segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO); | |
801678c5 | 5835 | if (IS_ERR(segs)) |
52c0fd83 MC |
5836 | goto tg3_tso_bug_end; |
5837 | ||
5838 | do { | |
5839 | nskb = segs; | |
5840 | segs = segs->next; | |
5841 | nskb->next = NULL; | |
5842 | tg3_start_xmit_dma_bug(nskb, tp->dev); | |
5843 | } while (segs); | |
5844 | ||
5845 | tg3_tso_bug_end: | |
5846 | dev_kfree_skb(skb); | |
5847 | ||
5848 | return NETDEV_TX_OK; | |
5849 | } | |
52c0fd83 | 5850 | |
5a6f3074 MC |
5851 | /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and |
5852 | * support TG3_FLG2_HW_TSO_1 or firmware TSO only. | |
5853 | */ | |
61357325 SH |
5854 | static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb, |
5855 | struct net_device *dev) | |
1da177e4 LT |
5856 | { |
5857 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 LT |
5858 | u32 len, entry, base_flags, mss; |
5859 | int would_hit_hwbug; | |
90079ce8 | 5860 | dma_addr_t mapping; |
24f4efd4 MC |
5861 | struct tg3_napi *tnapi; |
5862 | struct netdev_queue *txq; | |
f4188d8a AD |
5863 | unsigned int i, last; |
5864 | ||
24f4efd4 MC |
5865 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); |
5866 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; | |
19cfaecc | 5867 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
24f4efd4 | 5868 | tnapi++; |
1da177e4 | 5869 | |
00b70504 | 5870 | /* We are running in BH disabled context with netif_tx_lock |
bea3348e | 5871 | * and TX reclaim runs via tp->napi.poll inside of a software |
f47c11ee DM |
5872 | * interrupt. Furthermore, IRQ processing runs lockless so we have |
5873 | * no IRQ context deadlocks to worry about either. Rejoice! | |
1da177e4 | 5874 | */ |
f3f3f27e | 5875 | if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) { |
24f4efd4 MC |
5876 | if (!netif_tx_queue_stopped(txq)) { |
5877 | netif_tx_stop_queue(txq); | |
1f064a87 SH |
5878 | |
5879 | /* This is a hard error, log it. */ | |
5129c3a3 MC |
5880 | netdev_err(dev, |
5881 | "BUG! Tx Ring full when queue awake!\n"); | |
1f064a87 | 5882 | } |
1da177e4 LT |
5883 | return NETDEV_TX_BUSY; |
5884 | } | |
5885 | ||
f3f3f27e | 5886 | entry = tnapi->tx_prod; |
1da177e4 | 5887 | base_flags = 0; |
84fa7933 | 5888 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
1da177e4 | 5889 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
24f4efd4 | 5890 | |
be98da6a MC |
5891 | mss = skb_shinfo(skb)->gso_size; |
5892 | if (mss) { | |
eddc9ec5 | 5893 | struct iphdr *iph; |
34195c3d | 5894 | u32 tcp_opt_len, hdr_len; |
1da177e4 LT |
5895 | |
5896 | if (skb_header_cloned(skb) && | |
5897 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
5898 | dev_kfree_skb(skb); | |
5899 | goto out_unlock; | |
5900 | } | |
5901 | ||
34195c3d | 5902 | iph = ip_hdr(skb); |
ab6a5bb6 | 5903 | tcp_opt_len = tcp_optlen(skb); |
1da177e4 | 5904 | |
02e96080 | 5905 | if (skb_is_gso_v6(skb)) { |
34195c3d MC |
5906 | hdr_len = skb_headlen(skb) - ETH_HLEN; |
5907 | } else { | |
5908 | u32 ip_tcp_len; | |
5909 | ||
5910 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); | |
5911 | hdr_len = ip_tcp_len + tcp_opt_len; | |
5912 | ||
5913 | iph->check = 0; | |
5914 | iph->tot_len = htons(mss + hdr_len); | |
5915 | } | |
5916 | ||
52c0fd83 | 5917 | if (unlikely((ETH_HLEN + hdr_len) > 80) && |
7f62ad5d | 5918 | (tp->tg3_flags2 & TG3_FLG2_TSO_BUG)) |
de6f31eb | 5919 | return tg3_tso_bug(tp, skb); |
52c0fd83 | 5920 | |
1da177e4 LT |
5921 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | |
5922 | TXD_FLAG_CPU_POST_DMA); | |
5923 | ||
1da177e4 | 5924 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) { |
aa8223c7 | 5925 | tcp_hdr(skb)->check = 0; |
1da177e4 | 5926 | base_flags &= ~TXD_FLAG_TCPUDP_CSUM; |
aa8223c7 ACM |
5927 | } else |
5928 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
5929 | iph->daddr, 0, | |
5930 | IPPROTO_TCP, | |
5931 | 0); | |
1da177e4 | 5932 | |
615774fe MC |
5933 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) { |
5934 | mss |= (hdr_len & 0xc) << 12; | |
5935 | if (hdr_len & 0x10) | |
5936 | base_flags |= 0x00000010; | |
5937 | base_flags |= (hdr_len & 0x3e0) << 5; | |
5938 | } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) | |
92c6b8d1 MC |
5939 | mss |= hdr_len << 9; |
5940 | else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) || | |
5941 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
eddc9ec5 | 5942 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
5943 | int tsflags; |
5944 | ||
eddc9ec5 | 5945 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
5946 | mss |= (tsflags << 11); |
5947 | } | |
5948 | } else { | |
eddc9ec5 | 5949 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
5950 | int tsflags; |
5951 | ||
eddc9ec5 | 5952 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
5953 | base_flags |= tsflags << 12; |
5954 | } | |
5955 | } | |
5956 | } | |
bf933c80 | 5957 | |
eab6d18d | 5958 | if (vlan_tx_tag_present(skb)) |
1da177e4 LT |
5959 | base_flags |= (TXD_FLAG_VLAN | |
5960 | (vlan_tx_tag_get(skb) << 16)); | |
1da177e4 | 5961 | |
b703df6f | 5962 | if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) && |
8fc2f995 | 5963 | !mss && skb->len > VLAN_ETH_FRAME_LEN) |
615774fe MC |
5964 | base_flags |= TXD_FLAG_JMB_PKT; |
5965 | ||
f4188d8a AD |
5966 | len = skb_headlen(skb); |
5967 | ||
5968 | mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
5969 | if (pci_dma_mapping_error(tp->pdev, mapping)) { | |
90079ce8 DM |
5970 | dev_kfree_skb(skb); |
5971 | goto out_unlock; | |
5972 | } | |
5973 | ||
f3f3f27e | 5974 | tnapi->tx_buffers[entry].skb = skb; |
4e5e4f0d | 5975 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); |
1da177e4 LT |
5976 | |
5977 | would_hit_hwbug = 0; | |
5978 | ||
92c6b8d1 MC |
5979 | if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8) |
5980 | would_hit_hwbug = 1; | |
5981 | ||
0e1406dd MC |
5982 | if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && |
5983 | tg3_4g_overflow_test(mapping, len)) | |
5984 | would_hit_hwbug = 1; | |
5985 | ||
5986 | if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) && | |
5987 | tg3_40bit_overflow_test(tp, mapping, len)) | |
41588ba1 | 5988 | would_hit_hwbug = 1; |
0e1406dd MC |
5989 | |
5990 | if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG) | |
c58ec932 | 5991 | would_hit_hwbug = 1; |
1da177e4 | 5992 | |
f3f3f27e | 5993 | tg3_set_txd(tnapi, entry, mapping, len, base_flags, |
1da177e4 LT |
5994 | (skb_shinfo(skb)->nr_frags == 0) | (mss << 1)); |
5995 | ||
5996 | entry = NEXT_TX(entry); | |
5997 | ||
5998 | /* Now loop through additional data fragments, and queue them. */ | |
5999 | if (skb_shinfo(skb)->nr_frags > 0) { | |
1da177e4 LT |
6000 | last = skb_shinfo(skb)->nr_frags - 1; |
6001 | for (i = 0; i <= last; i++) { | |
6002 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6003 | ||
6004 | len = frag->size; | |
f4188d8a AD |
6005 | mapping = pci_map_page(tp->pdev, |
6006 | frag->page, | |
6007 | frag->page_offset, | |
6008 | len, PCI_DMA_TODEVICE); | |
1da177e4 | 6009 | |
f3f3f27e | 6010 | tnapi->tx_buffers[entry].skb = NULL; |
4e5e4f0d | 6011 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, |
f4188d8a AD |
6012 | mapping); |
6013 | if (pci_dma_mapping_error(tp->pdev, mapping)) | |
6014 | goto dma_error; | |
1da177e4 | 6015 | |
92c6b8d1 MC |
6016 | if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && |
6017 | len <= 8) | |
6018 | would_hit_hwbug = 1; | |
6019 | ||
0e1406dd MC |
6020 | if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && |
6021 | tg3_4g_overflow_test(mapping, len)) | |
c58ec932 | 6022 | would_hit_hwbug = 1; |
1da177e4 | 6023 | |
0e1406dd MC |
6024 | if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) && |
6025 | tg3_40bit_overflow_test(tp, mapping, len)) | |
72f2afb8 MC |
6026 | would_hit_hwbug = 1; |
6027 | ||
1da177e4 | 6028 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) |
f3f3f27e | 6029 | tg3_set_txd(tnapi, entry, mapping, len, |
1da177e4 LT |
6030 | base_flags, (i == last)|(mss << 1)); |
6031 | else | |
f3f3f27e | 6032 | tg3_set_txd(tnapi, entry, mapping, len, |
1da177e4 LT |
6033 | base_flags, (i == last)); |
6034 | ||
6035 | entry = NEXT_TX(entry); | |
6036 | } | |
6037 | } | |
6038 | ||
6039 | if (would_hit_hwbug) { | |
6040 | u32 last_plus_one = entry; | |
6041 | u32 start; | |
1da177e4 | 6042 | |
c58ec932 MC |
6043 | start = entry - 1 - skb_shinfo(skb)->nr_frags; |
6044 | start &= (TG3_TX_RING_SIZE - 1); | |
1da177e4 LT |
6045 | |
6046 | /* If the workaround fails due to memory/mapping | |
6047 | * failure, silently drop this packet. | |
6048 | */ | |
24f4efd4 | 6049 | if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one, |
c58ec932 | 6050 | &start, base_flags, mss)) |
1da177e4 LT |
6051 | goto out_unlock; |
6052 | ||
6053 | entry = start; | |
6054 | } | |
6055 | ||
6056 | /* Packets are ready, update Tx producer idx local and on card. */ | |
24f4efd4 | 6057 | tw32_tx_mbox(tnapi->prodmbox, entry); |
1da177e4 | 6058 | |
f3f3f27e MC |
6059 | tnapi->tx_prod = entry; |
6060 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
24f4efd4 | 6061 | netif_tx_stop_queue(txq); |
f65aac16 MC |
6062 | |
6063 | /* netif_tx_stop_queue() must be done before checking | |
6064 | * checking tx index in tg3_tx_avail() below, because in | |
6065 | * tg3_tx(), we update tx index before checking for | |
6066 | * netif_tx_queue_stopped(). | |
6067 | */ | |
6068 | smp_mb(); | |
f3f3f27e | 6069 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) |
24f4efd4 | 6070 | netif_tx_wake_queue(txq); |
51b91468 | 6071 | } |
1da177e4 LT |
6072 | |
6073 | out_unlock: | |
cdd0db05 | 6074 | mmiowb(); |
1da177e4 LT |
6075 | |
6076 | return NETDEV_TX_OK; | |
f4188d8a AD |
6077 | |
6078 | dma_error: | |
6079 | last = i; | |
6080 | entry = tnapi->tx_prod; | |
6081 | tnapi->tx_buffers[entry].skb = NULL; | |
6082 | pci_unmap_single(tp->pdev, | |
4e5e4f0d | 6083 | dma_unmap_addr(&tnapi->tx_buffers[entry], mapping), |
f4188d8a AD |
6084 | skb_headlen(skb), |
6085 | PCI_DMA_TODEVICE); | |
6086 | for (i = 0; i <= last; i++) { | |
6087 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6088 | entry = NEXT_TX(entry); | |
6089 | ||
6090 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 6091 | dma_unmap_addr(&tnapi->tx_buffers[entry], |
f4188d8a AD |
6092 | mapping), |
6093 | frag->size, PCI_DMA_TODEVICE); | |
6094 | } | |
6095 | ||
6096 | dev_kfree_skb(skb); | |
6097 | return NETDEV_TX_OK; | |
1da177e4 LT |
6098 | } |
6099 | ||
6100 | static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, | |
6101 | int new_mtu) | |
6102 | { | |
6103 | dev->mtu = new_mtu; | |
6104 | ||
ef7f5ec0 | 6105 | if (new_mtu > ETH_DATA_LEN) { |
a4e2b347 | 6106 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { |
ef7f5ec0 MC |
6107 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; |
6108 | ethtool_op_set_tso(dev, 0); | |
859a5887 | 6109 | } else { |
ef7f5ec0 | 6110 | tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE; |
859a5887 | 6111 | } |
ef7f5ec0 | 6112 | } else { |
a4e2b347 | 6113 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) |
ef7f5ec0 | 6114 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; |
0f893dc6 | 6115 | tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE; |
ef7f5ec0 | 6116 | } |
1da177e4 LT |
6117 | } |
6118 | ||
6119 | static int tg3_change_mtu(struct net_device *dev, int new_mtu) | |
6120 | { | |
6121 | struct tg3 *tp = netdev_priv(dev); | |
b9ec6c1b | 6122 | int err; |
1da177e4 LT |
6123 | |
6124 | if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) | |
6125 | return -EINVAL; | |
6126 | ||
6127 | if (!netif_running(dev)) { | |
6128 | /* We'll just catch it later when the | |
6129 | * device is up'd. | |
6130 | */ | |
6131 | tg3_set_mtu(dev, tp, new_mtu); | |
6132 | return 0; | |
6133 | } | |
6134 | ||
b02fd9e3 MC |
6135 | tg3_phy_stop(tp); |
6136 | ||
1da177e4 | 6137 | tg3_netif_stop(tp); |
f47c11ee DM |
6138 | |
6139 | tg3_full_lock(tp, 1); | |
1da177e4 | 6140 | |
944d980e | 6141 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
6142 | |
6143 | tg3_set_mtu(dev, tp, new_mtu); | |
6144 | ||
b9ec6c1b | 6145 | err = tg3_restart_hw(tp, 0); |
1da177e4 | 6146 | |
b9ec6c1b MC |
6147 | if (!err) |
6148 | tg3_netif_start(tp); | |
1da177e4 | 6149 | |
f47c11ee | 6150 | tg3_full_unlock(tp); |
1da177e4 | 6151 | |
b02fd9e3 MC |
6152 | if (!err) |
6153 | tg3_phy_start(tp); | |
6154 | ||
b9ec6c1b | 6155 | return err; |
1da177e4 LT |
6156 | } |
6157 | ||
21f581a5 MC |
6158 | static void tg3_rx_prodring_free(struct tg3 *tp, |
6159 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6160 | { |
1da177e4 LT |
6161 | int i; |
6162 | ||
8fea32b9 | 6163 | if (tpr != &tp->napi[0].prodring) { |
b196c7e4 | 6164 | for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; |
2c49a44d | 6165 | i = (i + 1) & tp->rx_std_ring_mask) |
b196c7e4 MC |
6166 | tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], |
6167 | tp->rx_pkt_map_sz); | |
6168 | ||
6169 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { | |
6170 | for (i = tpr->rx_jmb_cons_idx; | |
6171 | i != tpr->rx_jmb_prod_idx; | |
2c49a44d | 6172 | i = (i + 1) & tp->rx_jmb_ring_mask) { |
b196c7e4 MC |
6173 | tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i], |
6174 | TG3_RX_JMB_MAP_SZ); | |
6175 | } | |
6176 | } | |
6177 | ||
2b2cdb65 | 6178 | return; |
b196c7e4 | 6179 | } |
1da177e4 | 6180 | |
2c49a44d | 6181 | for (i = 0; i <= tp->rx_std_ring_mask; i++) |
2b2cdb65 MC |
6182 | tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], |
6183 | tp->rx_pkt_map_sz); | |
1da177e4 | 6184 | |
48035728 MC |
6185 | if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && |
6186 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { | |
2c49a44d | 6187 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) |
2b2cdb65 MC |
6188 | tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i], |
6189 | TG3_RX_JMB_MAP_SZ); | |
1da177e4 LT |
6190 | } |
6191 | } | |
6192 | ||
c6cdf436 | 6193 | /* Initialize rx rings for packet processing. |
1da177e4 LT |
6194 | * |
6195 | * The chip has been shut down and the driver detached from | |
6196 | * the networking, so no interrupts or new tx packets will | |
6197 | * end up in the driver. tp->{tx,}lock are held and thus | |
6198 | * we may not sleep. | |
6199 | */ | |
21f581a5 MC |
6200 | static int tg3_rx_prodring_alloc(struct tg3 *tp, |
6201 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6202 | { |
287be12e | 6203 | u32 i, rx_pkt_dma_sz; |
1da177e4 | 6204 | |
b196c7e4 MC |
6205 | tpr->rx_std_cons_idx = 0; |
6206 | tpr->rx_std_prod_idx = 0; | |
6207 | tpr->rx_jmb_cons_idx = 0; | |
6208 | tpr->rx_jmb_prod_idx = 0; | |
6209 | ||
8fea32b9 | 6210 | if (tpr != &tp->napi[0].prodring) { |
2c49a44d MC |
6211 | memset(&tpr->rx_std_buffers[0], 0, |
6212 | TG3_RX_STD_BUFF_RING_SIZE(tp)); | |
48035728 | 6213 | if (tpr->rx_jmb_buffers) |
2b2cdb65 | 6214 | memset(&tpr->rx_jmb_buffers[0], 0, |
2c49a44d | 6215 | TG3_RX_JMB_BUFF_RING_SIZE(tp)); |
2b2cdb65 MC |
6216 | goto done; |
6217 | } | |
6218 | ||
1da177e4 | 6219 | /* Zero out all descriptors. */ |
2c49a44d | 6220 | memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); |
1da177e4 | 6221 | |
287be12e | 6222 | rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ; |
a4e2b347 | 6223 | if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) && |
287be12e MC |
6224 | tp->dev->mtu > ETH_DATA_LEN) |
6225 | rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ; | |
6226 | tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); | |
7e72aad4 | 6227 | |
1da177e4 LT |
6228 | /* Initialize invariants of the rings, we only set this |
6229 | * stuff once. This works because the card does not | |
6230 | * write into the rx buffer posting rings. | |
6231 | */ | |
2c49a44d | 6232 | for (i = 0; i <= tp->rx_std_ring_mask; i++) { |
1da177e4 LT |
6233 | struct tg3_rx_buffer_desc *rxd; |
6234 | ||
21f581a5 | 6235 | rxd = &tpr->rx_std[i]; |
287be12e | 6236 | rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; |
1da177e4 LT |
6237 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); |
6238 | rxd->opaque = (RXD_OPAQUE_RING_STD | | |
6239 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
6240 | } | |
6241 | ||
1da177e4 LT |
6242 | /* Now allocate fresh SKBs for each rx ring. */ |
6243 | for (i = 0; i < tp->rx_pending; i++) { | |
86b21e59 | 6244 | if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) { |
5129c3a3 MC |
6245 | netdev_warn(tp->dev, |
6246 | "Using a smaller RX standard ring. Only " | |
6247 | "%d out of %d buffers were allocated " | |
6248 | "successfully\n", i, tp->rx_pending); | |
32d8c572 | 6249 | if (i == 0) |
cf7a7298 | 6250 | goto initfail; |
32d8c572 | 6251 | tp->rx_pending = i; |
1da177e4 | 6252 | break; |
32d8c572 | 6253 | } |
1da177e4 LT |
6254 | } |
6255 | ||
48035728 MC |
6256 | if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) || |
6257 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
cf7a7298 MC |
6258 | goto done; |
6259 | ||
2c49a44d | 6260 | memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); |
cf7a7298 | 6261 | |
0d86df80 MC |
6262 | if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)) |
6263 | goto done; | |
cf7a7298 | 6264 | |
2c49a44d | 6265 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { |
0d86df80 MC |
6266 | struct tg3_rx_buffer_desc *rxd; |
6267 | ||
6268 | rxd = &tpr->rx_jmb[i].std; | |
6269 | rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; | |
6270 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | | |
6271 | RXD_FLAG_JUMBO; | |
6272 | rxd->opaque = (RXD_OPAQUE_RING_JUMBO | | |
6273 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
6274 | } | |
6275 | ||
6276 | for (i = 0; i < tp->rx_jumbo_pending; i++) { | |
6277 | if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) { | |
5129c3a3 MC |
6278 | netdev_warn(tp->dev, |
6279 | "Using a smaller RX jumbo ring. Only %d " | |
6280 | "out of %d buffers were allocated " | |
6281 | "successfully\n", i, tp->rx_jumbo_pending); | |
0d86df80 MC |
6282 | if (i == 0) |
6283 | goto initfail; | |
6284 | tp->rx_jumbo_pending = i; | |
6285 | break; | |
1da177e4 LT |
6286 | } |
6287 | } | |
cf7a7298 MC |
6288 | |
6289 | done: | |
32d8c572 | 6290 | return 0; |
cf7a7298 MC |
6291 | |
6292 | initfail: | |
21f581a5 | 6293 | tg3_rx_prodring_free(tp, tpr); |
cf7a7298 | 6294 | return -ENOMEM; |
1da177e4 LT |
6295 | } |
6296 | ||
21f581a5 MC |
6297 | static void tg3_rx_prodring_fini(struct tg3 *tp, |
6298 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6299 | { |
21f581a5 MC |
6300 | kfree(tpr->rx_std_buffers); |
6301 | tpr->rx_std_buffers = NULL; | |
6302 | kfree(tpr->rx_jmb_buffers); | |
6303 | tpr->rx_jmb_buffers = NULL; | |
6304 | if (tpr->rx_std) { | |
4bae65c8 MC |
6305 | dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), |
6306 | tpr->rx_std, tpr->rx_std_mapping); | |
21f581a5 | 6307 | tpr->rx_std = NULL; |
1da177e4 | 6308 | } |
21f581a5 | 6309 | if (tpr->rx_jmb) { |
4bae65c8 MC |
6310 | dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), |
6311 | tpr->rx_jmb, tpr->rx_jmb_mapping); | |
21f581a5 | 6312 | tpr->rx_jmb = NULL; |
1da177e4 | 6313 | } |
cf7a7298 MC |
6314 | } |
6315 | ||
21f581a5 MC |
6316 | static int tg3_rx_prodring_init(struct tg3 *tp, |
6317 | struct tg3_rx_prodring_set *tpr) | |
cf7a7298 | 6318 | { |
2c49a44d MC |
6319 | tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), |
6320 | GFP_KERNEL); | |
21f581a5 | 6321 | if (!tpr->rx_std_buffers) |
cf7a7298 MC |
6322 | return -ENOMEM; |
6323 | ||
4bae65c8 MC |
6324 | tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, |
6325 | TG3_RX_STD_RING_BYTES(tp), | |
6326 | &tpr->rx_std_mapping, | |
6327 | GFP_KERNEL); | |
21f581a5 | 6328 | if (!tpr->rx_std) |
cf7a7298 MC |
6329 | goto err_out; |
6330 | ||
48035728 MC |
6331 | if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && |
6332 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { | |
2c49a44d | 6333 | tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), |
21f581a5 MC |
6334 | GFP_KERNEL); |
6335 | if (!tpr->rx_jmb_buffers) | |
cf7a7298 MC |
6336 | goto err_out; |
6337 | ||
4bae65c8 MC |
6338 | tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, |
6339 | TG3_RX_JMB_RING_BYTES(tp), | |
6340 | &tpr->rx_jmb_mapping, | |
6341 | GFP_KERNEL); | |
21f581a5 | 6342 | if (!tpr->rx_jmb) |
cf7a7298 MC |
6343 | goto err_out; |
6344 | } | |
6345 | ||
6346 | return 0; | |
6347 | ||
6348 | err_out: | |
21f581a5 | 6349 | tg3_rx_prodring_fini(tp, tpr); |
cf7a7298 MC |
6350 | return -ENOMEM; |
6351 | } | |
6352 | ||
6353 | /* Free up pending packets in all rx/tx rings. | |
6354 | * | |
6355 | * The chip has been shut down and the driver detached from | |
6356 | * the networking, so no interrupts or new tx packets will | |
6357 | * end up in the driver. tp->{tx,}lock is not held and we are not | |
6358 | * in an interrupt context and thus may sleep. | |
6359 | */ | |
6360 | static void tg3_free_rings(struct tg3 *tp) | |
6361 | { | |
f77a6a8e | 6362 | int i, j; |
cf7a7298 | 6363 | |
f77a6a8e MC |
6364 | for (j = 0; j < tp->irq_cnt; j++) { |
6365 | struct tg3_napi *tnapi = &tp->napi[j]; | |
cf7a7298 | 6366 | |
8fea32b9 | 6367 | tg3_rx_prodring_free(tp, &tnapi->prodring); |
b28f6428 | 6368 | |
0c1d0e2b MC |
6369 | if (!tnapi->tx_buffers) |
6370 | continue; | |
6371 | ||
f77a6a8e | 6372 | for (i = 0; i < TG3_TX_RING_SIZE; ) { |
f4188d8a | 6373 | struct ring_info *txp; |
f77a6a8e | 6374 | struct sk_buff *skb; |
f4188d8a | 6375 | unsigned int k; |
cf7a7298 | 6376 | |
f77a6a8e MC |
6377 | txp = &tnapi->tx_buffers[i]; |
6378 | skb = txp->skb; | |
cf7a7298 | 6379 | |
f77a6a8e MC |
6380 | if (skb == NULL) { |
6381 | i++; | |
6382 | continue; | |
6383 | } | |
cf7a7298 | 6384 | |
f4188d8a | 6385 | pci_unmap_single(tp->pdev, |
4e5e4f0d | 6386 | dma_unmap_addr(txp, mapping), |
f4188d8a AD |
6387 | skb_headlen(skb), |
6388 | PCI_DMA_TODEVICE); | |
f77a6a8e | 6389 | txp->skb = NULL; |
cf7a7298 | 6390 | |
f4188d8a AD |
6391 | i++; |
6392 | ||
6393 | for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) { | |
6394 | txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)]; | |
6395 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 6396 | dma_unmap_addr(txp, mapping), |
f4188d8a AD |
6397 | skb_shinfo(skb)->frags[k].size, |
6398 | PCI_DMA_TODEVICE); | |
6399 | i++; | |
6400 | } | |
f77a6a8e MC |
6401 | |
6402 | dev_kfree_skb_any(skb); | |
6403 | } | |
2b2cdb65 | 6404 | } |
cf7a7298 MC |
6405 | } |
6406 | ||
6407 | /* Initialize tx/rx rings for packet processing. | |
6408 | * | |
6409 | * The chip has been shut down and the driver detached from | |
6410 | * the networking, so no interrupts or new tx packets will | |
6411 | * end up in the driver. tp->{tx,}lock are held and thus | |
6412 | * we may not sleep. | |
6413 | */ | |
6414 | static int tg3_init_rings(struct tg3 *tp) | |
6415 | { | |
f77a6a8e | 6416 | int i; |
72334482 | 6417 | |
cf7a7298 MC |
6418 | /* Free up all the SKBs. */ |
6419 | tg3_free_rings(tp); | |
6420 | ||
f77a6a8e MC |
6421 | for (i = 0; i < tp->irq_cnt; i++) { |
6422 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6423 | ||
6424 | tnapi->last_tag = 0; | |
6425 | tnapi->last_irq_tag = 0; | |
6426 | tnapi->hw_status->status = 0; | |
6427 | tnapi->hw_status->status_tag = 0; | |
6428 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
cf7a7298 | 6429 | |
f77a6a8e MC |
6430 | tnapi->tx_prod = 0; |
6431 | tnapi->tx_cons = 0; | |
0c1d0e2b MC |
6432 | if (tnapi->tx_ring) |
6433 | memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); | |
f77a6a8e MC |
6434 | |
6435 | tnapi->rx_rcb_ptr = 0; | |
0c1d0e2b MC |
6436 | if (tnapi->rx_rcb) |
6437 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | |
2b2cdb65 | 6438 | |
8fea32b9 | 6439 | if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { |
e4af1af9 | 6440 | tg3_free_rings(tp); |
2b2cdb65 | 6441 | return -ENOMEM; |
e4af1af9 | 6442 | } |
f77a6a8e | 6443 | } |
72334482 | 6444 | |
2b2cdb65 | 6445 | return 0; |
cf7a7298 MC |
6446 | } |
6447 | ||
6448 | /* | |
6449 | * Must not be invoked with interrupt sources disabled and | |
6450 | * the hardware shutdown down. | |
6451 | */ | |
6452 | static void tg3_free_consistent(struct tg3 *tp) | |
6453 | { | |
f77a6a8e | 6454 | int i; |
898a56f8 | 6455 | |
f77a6a8e MC |
6456 | for (i = 0; i < tp->irq_cnt; i++) { |
6457 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6458 | ||
6459 | if (tnapi->tx_ring) { | |
4bae65c8 | 6460 | dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, |
f77a6a8e MC |
6461 | tnapi->tx_ring, tnapi->tx_desc_mapping); |
6462 | tnapi->tx_ring = NULL; | |
6463 | } | |
6464 | ||
6465 | kfree(tnapi->tx_buffers); | |
6466 | tnapi->tx_buffers = NULL; | |
6467 | ||
6468 | if (tnapi->rx_rcb) { | |
4bae65c8 MC |
6469 | dma_free_coherent(&tp->pdev->dev, |
6470 | TG3_RX_RCB_RING_BYTES(tp), | |
6471 | tnapi->rx_rcb, | |
6472 | tnapi->rx_rcb_mapping); | |
f77a6a8e MC |
6473 | tnapi->rx_rcb = NULL; |
6474 | } | |
6475 | ||
8fea32b9 MC |
6476 | tg3_rx_prodring_fini(tp, &tnapi->prodring); |
6477 | ||
f77a6a8e | 6478 | if (tnapi->hw_status) { |
4bae65c8 MC |
6479 | dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, |
6480 | tnapi->hw_status, | |
6481 | tnapi->status_mapping); | |
f77a6a8e MC |
6482 | tnapi->hw_status = NULL; |
6483 | } | |
1da177e4 | 6484 | } |
f77a6a8e | 6485 | |
1da177e4 | 6486 | if (tp->hw_stats) { |
4bae65c8 MC |
6487 | dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), |
6488 | tp->hw_stats, tp->stats_mapping); | |
1da177e4 LT |
6489 | tp->hw_stats = NULL; |
6490 | } | |
6491 | } | |
6492 | ||
6493 | /* | |
6494 | * Must not be invoked with interrupt sources disabled and | |
6495 | * the hardware shutdown down. Can sleep. | |
6496 | */ | |
6497 | static int tg3_alloc_consistent(struct tg3 *tp) | |
6498 | { | |
f77a6a8e | 6499 | int i; |
898a56f8 | 6500 | |
4bae65c8 MC |
6501 | tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, |
6502 | sizeof(struct tg3_hw_stats), | |
6503 | &tp->stats_mapping, | |
6504 | GFP_KERNEL); | |
f77a6a8e | 6505 | if (!tp->hw_stats) |
1da177e4 LT |
6506 | goto err_out; |
6507 | ||
f77a6a8e | 6508 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); |
1da177e4 | 6509 | |
f77a6a8e MC |
6510 | for (i = 0; i < tp->irq_cnt; i++) { |
6511 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8d9d7cfc | 6512 | struct tg3_hw_status *sblk; |
1da177e4 | 6513 | |
4bae65c8 MC |
6514 | tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, |
6515 | TG3_HW_STATUS_SIZE, | |
6516 | &tnapi->status_mapping, | |
6517 | GFP_KERNEL); | |
f77a6a8e MC |
6518 | if (!tnapi->hw_status) |
6519 | goto err_out; | |
898a56f8 | 6520 | |
f77a6a8e | 6521 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); |
8d9d7cfc MC |
6522 | sblk = tnapi->hw_status; |
6523 | ||
8fea32b9 MC |
6524 | if (tg3_rx_prodring_init(tp, &tnapi->prodring)) |
6525 | goto err_out; | |
6526 | ||
19cfaecc MC |
6527 | /* If multivector TSS is enabled, vector 0 does not handle |
6528 | * tx interrupts. Don't allocate any resources for it. | |
6529 | */ | |
6530 | if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) || | |
6531 | (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) { | |
6532 | tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) * | |
6533 | TG3_TX_RING_SIZE, | |
6534 | GFP_KERNEL); | |
6535 | if (!tnapi->tx_buffers) | |
6536 | goto err_out; | |
6537 | ||
4bae65c8 MC |
6538 | tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, |
6539 | TG3_TX_RING_BYTES, | |
6540 | &tnapi->tx_desc_mapping, | |
6541 | GFP_KERNEL); | |
19cfaecc MC |
6542 | if (!tnapi->tx_ring) |
6543 | goto err_out; | |
6544 | } | |
6545 | ||
8d9d7cfc MC |
6546 | /* |
6547 | * When RSS is enabled, the status block format changes | |
6548 | * slightly. The "rx_jumbo_consumer", "reserved", | |
6549 | * and "rx_mini_consumer" members get mapped to the | |
6550 | * other three rx return ring producer indexes. | |
6551 | */ | |
6552 | switch (i) { | |
6553 | default: | |
6554 | tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; | |
6555 | break; | |
6556 | case 2: | |
6557 | tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer; | |
6558 | break; | |
6559 | case 3: | |
6560 | tnapi->rx_rcb_prod_idx = &sblk->reserved; | |
6561 | break; | |
6562 | case 4: | |
6563 | tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer; | |
6564 | break; | |
6565 | } | |
72334482 | 6566 | |
0c1d0e2b MC |
6567 | /* |
6568 | * If multivector RSS is enabled, vector 0 does not handle | |
6569 | * rx or tx interrupts. Don't allocate any resources for it. | |
6570 | */ | |
6571 | if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) | |
6572 | continue; | |
6573 | ||
4bae65c8 MC |
6574 | tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, |
6575 | TG3_RX_RCB_RING_BYTES(tp), | |
6576 | &tnapi->rx_rcb_mapping, | |
6577 | GFP_KERNEL); | |
f77a6a8e MC |
6578 | if (!tnapi->rx_rcb) |
6579 | goto err_out; | |
72334482 | 6580 | |
f77a6a8e | 6581 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); |
f77a6a8e | 6582 | } |
1da177e4 LT |
6583 | |
6584 | return 0; | |
6585 | ||
6586 | err_out: | |
6587 | tg3_free_consistent(tp); | |
6588 | return -ENOMEM; | |
6589 | } | |
6590 | ||
6591 | #define MAX_WAIT_CNT 1000 | |
6592 | ||
6593 | /* To stop a block, clear the enable bit and poll till it | |
6594 | * clears. tp->lock is held. | |
6595 | */ | |
b3b7d6be | 6596 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent) |
1da177e4 LT |
6597 | { |
6598 | unsigned int i; | |
6599 | u32 val; | |
6600 | ||
6601 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
6602 | switch (ofs) { | |
6603 | case RCVLSC_MODE: | |
6604 | case DMAC_MODE: | |
6605 | case MBFREE_MODE: | |
6606 | case BUFMGR_MODE: | |
6607 | case MEMARB_MODE: | |
6608 | /* We can't enable/disable these bits of the | |
6609 | * 5705/5750, just say success. | |
6610 | */ | |
6611 | return 0; | |
6612 | ||
6613 | default: | |
6614 | break; | |
855e1111 | 6615 | } |
1da177e4 LT |
6616 | } |
6617 | ||
6618 | val = tr32(ofs); | |
6619 | val &= ~enable_bit; | |
6620 | tw32_f(ofs, val); | |
6621 | ||
6622 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
6623 | udelay(100); | |
6624 | val = tr32(ofs); | |
6625 | if ((val & enable_bit) == 0) | |
6626 | break; | |
6627 | } | |
6628 | ||
b3b7d6be | 6629 | if (i == MAX_WAIT_CNT && !silent) { |
2445e461 MC |
6630 | dev_err(&tp->pdev->dev, |
6631 | "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n", | |
6632 | ofs, enable_bit); | |
1da177e4 LT |
6633 | return -ENODEV; |
6634 | } | |
6635 | ||
6636 | return 0; | |
6637 | } | |
6638 | ||
6639 | /* tp->lock is held. */ | |
b3b7d6be | 6640 | static int tg3_abort_hw(struct tg3 *tp, int silent) |
1da177e4 LT |
6641 | { |
6642 | int i, err; | |
6643 | ||
6644 | tg3_disable_ints(tp); | |
6645 | ||
6646 | tp->rx_mode &= ~RX_MODE_ENABLE; | |
6647 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
6648 | udelay(10); | |
6649 | ||
b3b7d6be DM |
6650 | err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); |
6651 | err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); | |
6652 | err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); | |
6653 | err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); | |
6654 | err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); | |
6655 | err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); | |
6656 | ||
6657 | err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); | |
6658 | err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); | |
6659 | err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); | |
6660 | err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); | |
6661 | err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); | |
6662 | err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); | |
6663 | err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); | |
1da177e4 LT |
6664 | |
6665 | tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; | |
6666 | tw32_f(MAC_MODE, tp->mac_mode); | |
6667 | udelay(40); | |
6668 | ||
6669 | tp->tx_mode &= ~TX_MODE_ENABLE; | |
6670 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
6671 | ||
6672 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
6673 | udelay(100); | |
6674 | if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) | |
6675 | break; | |
6676 | } | |
6677 | if (i >= MAX_WAIT_CNT) { | |
ab96b241 MC |
6678 | dev_err(&tp->pdev->dev, |
6679 | "%s timed out, TX_MODE_ENABLE will not clear " | |
6680 | "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE)); | |
e6de8ad1 | 6681 | err |= -ENODEV; |
1da177e4 LT |
6682 | } |
6683 | ||
e6de8ad1 | 6684 | err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); |
b3b7d6be DM |
6685 | err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); |
6686 | err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); | |
1da177e4 LT |
6687 | |
6688 | tw32(FTQ_RESET, 0xffffffff); | |
6689 | tw32(FTQ_RESET, 0x00000000); | |
6690 | ||
b3b7d6be DM |
6691 | err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); |
6692 | err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); | |
1da177e4 | 6693 | |
f77a6a8e MC |
6694 | for (i = 0; i < tp->irq_cnt; i++) { |
6695 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6696 | if (tnapi->hw_status) | |
6697 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
6698 | } | |
1da177e4 LT |
6699 | if (tp->hw_stats) |
6700 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); | |
6701 | ||
1da177e4 LT |
6702 | return err; |
6703 | } | |
6704 | ||
0d3031d9 MC |
6705 | static void tg3_ape_send_event(struct tg3 *tp, u32 event) |
6706 | { | |
6707 | int i; | |
6708 | u32 apedata; | |
6709 | ||
dc6d0744 MC |
6710 | /* NCSI does not support APE events */ |
6711 | if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI) | |
6712 | return; | |
6713 | ||
0d3031d9 MC |
6714 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); |
6715 | if (apedata != APE_SEG_SIG_MAGIC) | |
6716 | return; | |
6717 | ||
6718 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
731fd79c | 6719 | if (!(apedata & APE_FW_STATUS_READY)) |
0d3031d9 MC |
6720 | return; |
6721 | ||
6722 | /* Wait for up to 1 millisecond for APE to service previous event. */ | |
6723 | for (i = 0; i < 10; i++) { | |
6724 | if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) | |
6725 | return; | |
6726 | ||
6727 | apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); | |
6728 | ||
6729 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6730 | tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, | |
6731 | event | APE_EVENT_STATUS_EVENT_PENDING); | |
6732 | ||
6733 | tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); | |
6734 | ||
6735 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6736 | break; | |
6737 | ||
6738 | udelay(100); | |
6739 | } | |
6740 | ||
6741 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6742 | tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); | |
6743 | } | |
6744 | ||
6745 | static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) | |
6746 | { | |
6747 | u32 event; | |
6748 | u32 apedata; | |
6749 | ||
6750 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
6751 | return; | |
6752 | ||
6753 | switch (kind) { | |
33f401ae MC |
6754 | case RESET_KIND_INIT: |
6755 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, | |
6756 | APE_HOST_SEG_SIG_MAGIC); | |
6757 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, | |
6758 | APE_HOST_SEG_LEN_MAGIC); | |
6759 | apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); | |
6760 | tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); | |
6761 | tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, | |
6867c843 | 6762 | APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM)); |
33f401ae MC |
6763 | tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, |
6764 | APE_HOST_BEHAV_NO_PHYLOCK); | |
dc6d0744 MC |
6765 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, |
6766 | TG3_APE_HOST_DRVR_STATE_START); | |
33f401ae MC |
6767 | |
6768 | event = APE_EVENT_STATUS_STATE_START; | |
6769 | break; | |
6770 | case RESET_KIND_SHUTDOWN: | |
6771 | /* With the interface we are currently using, | |
6772 | * APE does not track driver state. Wiping | |
6773 | * out the HOST SEGMENT SIGNATURE forces | |
6774 | * the APE to assume OS absent status. | |
6775 | */ | |
6776 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0); | |
b2aee154 | 6777 | |
dc6d0744 MC |
6778 | if (device_may_wakeup(&tp->pdev->dev) && |
6779 | (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) { | |
6780 | tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED, | |
6781 | TG3_APE_HOST_WOL_SPEED_AUTO); | |
6782 | apedata = TG3_APE_HOST_DRVR_STATE_WOL; | |
6783 | } else | |
6784 | apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD; | |
6785 | ||
6786 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata); | |
6787 | ||
33f401ae MC |
6788 | event = APE_EVENT_STATUS_STATE_UNLOAD; |
6789 | break; | |
6790 | case RESET_KIND_SUSPEND: | |
6791 | event = APE_EVENT_STATUS_STATE_SUSPEND; | |
6792 | break; | |
6793 | default: | |
6794 | return; | |
0d3031d9 MC |
6795 | } |
6796 | ||
6797 | event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; | |
6798 | ||
6799 | tg3_ape_send_event(tp, event); | |
6800 | } | |
6801 | ||
1da177e4 LT |
6802 | /* tp->lock is held. */ |
6803 | static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) | |
6804 | { | |
f49639e6 DM |
6805 | tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, |
6806 | NIC_SRAM_FIRMWARE_MBOX_MAGIC1); | |
1da177e4 LT |
6807 | |
6808 | if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) { | |
6809 | switch (kind) { | |
6810 | case RESET_KIND_INIT: | |
6811 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6812 | DRV_STATE_START); | |
6813 | break; | |
6814 | ||
6815 | case RESET_KIND_SHUTDOWN: | |
6816 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6817 | DRV_STATE_UNLOAD); | |
6818 | break; | |
6819 | ||
6820 | case RESET_KIND_SUSPEND: | |
6821 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6822 | DRV_STATE_SUSPEND); | |
6823 | break; | |
6824 | ||
6825 | default: | |
6826 | break; | |
855e1111 | 6827 | } |
1da177e4 | 6828 | } |
0d3031d9 MC |
6829 | |
6830 | if (kind == RESET_KIND_INIT || | |
6831 | kind == RESET_KIND_SUSPEND) | |
6832 | tg3_ape_driver_state_change(tp, kind); | |
1da177e4 LT |
6833 | } |
6834 | ||
6835 | /* tp->lock is held. */ | |
6836 | static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) | |
6837 | { | |
6838 | if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) { | |
6839 | switch (kind) { | |
6840 | case RESET_KIND_INIT: | |
6841 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6842 | DRV_STATE_START_DONE); | |
6843 | break; | |
6844 | ||
6845 | case RESET_KIND_SHUTDOWN: | |
6846 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6847 | DRV_STATE_UNLOAD_DONE); | |
6848 | break; | |
6849 | ||
6850 | default: | |
6851 | break; | |
855e1111 | 6852 | } |
1da177e4 | 6853 | } |
0d3031d9 MC |
6854 | |
6855 | if (kind == RESET_KIND_SHUTDOWN) | |
6856 | tg3_ape_driver_state_change(tp, kind); | |
1da177e4 LT |
6857 | } |
6858 | ||
6859 | /* tp->lock is held. */ | |
6860 | static void tg3_write_sig_legacy(struct tg3 *tp, int kind) | |
6861 | { | |
6862 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { | |
6863 | switch (kind) { | |
6864 | case RESET_KIND_INIT: | |
6865 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6866 | DRV_STATE_START); | |
6867 | break; | |
6868 | ||
6869 | case RESET_KIND_SHUTDOWN: | |
6870 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6871 | DRV_STATE_UNLOAD); | |
6872 | break; | |
6873 | ||
6874 | case RESET_KIND_SUSPEND: | |
6875 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6876 | DRV_STATE_SUSPEND); | |
6877 | break; | |
6878 | ||
6879 | default: | |
6880 | break; | |
855e1111 | 6881 | } |
1da177e4 LT |
6882 | } |
6883 | } | |
6884 | ||
7a6f4369 MC |
6885 | static int tg3_poll_fw(struct tg3 *tp) |
6886 | { | |
6887 | int i; | |
6888 | u32 val; | |
6889 | ||
b5d3772c | 6890 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
0ccead18 GZ |
6891 | /* Wait up to 20ms for init done. */ |
6892 | for (i = 0; i < 200; i++) { | |
b5d3772c MC |
6893 | if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) |
6894 | return 0; | |
0ccead18 | 6895 | udelay(100); |
b5d3772c MC |
6896 | } |
6897 | return -ENODEV; | |
6898 | } | |
6899 | ||
7a6f4369 MC |
6900 | /* Wait for firmware initialization to complete. */ |
6901 | for (i = 0; i < 100000; i++) { | |
6902 | tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); | |
6903 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
6904 | break; | |
6905 | udelay(10); | |
6906 | } | |
6907 | ||
6908 | /* Chip might not be fitted with firmware. Some Sun onboard | |
6909 | * parts are configured like that. So don't signal the timeout | |
6910 | * of the above loop as an error, but do report the lack of | |
6911 | * running firmware once. | |
6912 | */ | |
6913 | if (i >= 100000 && | |
6914 | !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) { | |
6915 | tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED; | |
6916 | ||
05dbe005 | 6917 | netdev_info(tp->dev, "No firmware running\n"); |
7a6f4369 MC |
6918 | } |
6919 | ||
6b10c165 MC |
6920 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { |
6921 | /* The 57765 A0 needs a little more | |
6922 | * time to do some important work. | |
6923 | */ | |
6924 | mdelay(10); | |
6925 | } | |
6926 | ||
7a6f4369 MC |
6927 | return 0; |
6928 | } | |
6929 | ||
ee6a99b5 MC |
6930 | /* Save PCI command register before chip reset */ |
6931 | static void tg3_save_pci_state(struct tg3 *tp) | |
6932 | { | |
8a6eac90 | 6933 | pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); |
ee6a99b5 MC |
6934 | } |
6935 | ||
6936 | /* Restore PCI state after chip reset */ | |
6937 | static void tg3_restore_pci_state(struct tg3 *tp) | |
6938 | { | |
6939 | u32 val; | |
6940 | ||
6941 | /* Re-enable indirect register accesses. */ | |
6942 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
6943 | tp->misc_host_ctrl); | |
6944 | ||
6945 | /* Set MAX PCI retry to zero. */ | |
6946 | val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); | |
6947 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
6948 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) | |
6949 | val |= PCISTATE_RETRY_SAME_DMA; | |
0d3031d9 MC |
6950 | /* Allow reads and writes to the APE register and memory space. */ |
6951 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
6952 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
6953 | PCISTATE_ALLOW_APE_SHMEM_WR | |
6954 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
ee6a99b5 MC |
6955 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); |
6956 | ||
8a6eac90 | 6957 | pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); |
ee6a99b5 | 6958 | |
fcb389df MC |
6959 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) { |
6960 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) | |
cf79003d | 6961 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); |
fcb389df MC |
6962 | else { |
6963 | pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, | |
6964 | tp->pci_cacheline_sz); | |
6965 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
6966 | tp->pci_lat_timer); | |
6967 | } | |
114342f2 | 6968 | } |
5f5c51e3 | 6969 | |
ee6a99b5 | 6970 | /* Make sure PCI-X relaxed ordering bit is clear. */ |
52f4490c | 6971 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { |
9974a356 MC |
6972 | u16 pcix_cmd; |
6973 | ||
6974 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
6975 | &pcix_cmd); | |
6976 | pcix_cmd &= ~PCI_X_CMD_ERO; | |
6977 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
6978 | pcix_cmd); | |
6979 | } | |
ee6a99b5 MC |
6980 | |
6981 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { | |
ee6a99b5 MC |
6982 | |
6983 | /* Chip reset on 5780 will reset MSI enable bit, | |
6984 | * so need to restore it. | |
6985 | */ | |
6986 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | |
6987 | u16 ctrl; | |
6988 | ||
6989 | pci_read_config_word(tp->pdev, | |
6990 | tp->msi_cap + PCI_MSI_FLAGS, | |
6991 | &ctrl); | |
6992 | pci_write_config_word(tp->pdev, | |
6993 | tp->msi_cap + PCI_MSI_FLAGS, | |
6994 | ctrl | PCI_MSI_FLAGS_ENABLE); | |
6995 | val = tr32(MSGINT_MODE); | |
6996 | tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE); | |
6997 | } | |
6998 | } | |
6999 | } | |
7000 | ||
1da177e4 LT |
7001 | static void tg3_stop_fw(struct tg3 *); |
7002 | ||
7003 | /* tp->lock is held. */ | |
7004 | static int tg3_chip_reset(struct tg3 *tp) | |
7005 | { | |
7006 | u32 val; | |
1ee582d8 | 7007 | void (*write_op)(struct tg3 *, u32, u32); |
4f125f42 | 7008 | int i, err; |
1da177e4 | 7009 | |
f49639e6 DM |
7010 | tg3_nvram_lock(tp); |
7011 | ||
77b483f1 MC |
7012 | tg3_ape_lock(tp, TG3_APE_LOCK_GRC); |
7013 | ||
f49639e6 DM |
7014 | /* No matching tg3_nvram_unlock() after this because |
7015 | * chip reset below will undo the nvram lock. | |
7016 | */ | |
7017 | tp->nvram_lock_cnt = 0; | |
1da177e4 | 7018 | |
ee6a99b5 MC |
7019 | /* GRC_MISC_CFG core clock reset will clear the memory |
7020 | * enable bit in PCI register 4 and the MSI enable bit | |
7021 | * on some chips, so we save relevant registers here. | |
7022 | */ | |
7023 | tg3_save_pci_state(tp); | |
7024 | ||
d9ab5ad1 | 7025 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || |
321d32a0 | 7026 | (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) |
d9ab5ad1 MC |
7027 | tw32(GRC_FASTBOOT_PC, 0); |
7028 | ||
1da177e4 LT |
7029 | /* |
7030 | * We must avoid the readl() that normally takes place. | |
7031 | * It locks machines, causes machine checks, and other | |
7032 | * fun things. So, temporarily disable the 5701 | |
7033 | * hardware workaround, while we do the reset. | |
7034 | */ | |
1ee582d8 MC |
7035 | write_op = tp->write32; |
7036 | if (write_op == tg3_write_flush_reg32) | |
7037 | tp->write32 = tg3_write32; | |
1da177e4 | 7038 | |
d18edcb2 MC |
7039 | /* Prevent the irq handler from reading or writing PCI registers |
7040 | * during chip reset when the memory enable bit in the PCI command | |
7041 | * register may be cleared. The chip does not generate interrupt | |
7042 | * at this time, but the irq handler may still be called due to irq | |
7043 | * sharing or irqpoll. | |
7044 | */ | |
7045 | tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING; | |
f77a6a8e MC |
7046 | for (i = 0; i < tp->irq_cnt; i++) { |
7047 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7048 | if (tnapi->hw_status) { | |
7049 | tnapi->hw_status->status = 0; | |
7050 | tnapi->hw_status->status_tag = 0; | |
7051 | } | |
7052 | tnapi->last_tag = 0; | |
7053 | tnapi->last_irq_tag = 0; | |
b8fa2f3a | 7054 | } |
d18edcb2 | 7055 | smp_mb(); |
4f125f42 MC |
7056 | |
7057 | for (i = 0; i < tp->irq_cnt; i++) | |
7058 | synchronize_irq(tp->napi[i].irq_vec); | |
d18edcb2 | 7059 | |
255ca311 MC |
7060 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
7061 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; | |
7062 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
7063 | } | |
7064 | ||
1da177e4 LT |
7065 | /* do the reset */ |
7066 | val = GRC_MISC_CFG_CORECLK_RESET; | |
7067 | ||
7068 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
88075d91 MC |
7069 | /* Force PCIe 1.0a mode */ |
7070 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
7071 | !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) && | |
7072 | tr32(TG3_PCIE_PHY_TSTCTL) == | |
7073 | (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM)) | |
7074 | tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM); | |
7075 | ||
1da177e4 LT |
7076 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { |
7077 | tw32(GRC_MISC_CFG, (1 << 29)); | |
7078 | val |= (1 << 29); | |
7079 | } | |
7080 | } | |
7081 | ||
b5d3772c MC |
7082 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
7083 | tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); | |
7084 | tw32(GRC_VCPU_EXT_CTRL, | |
7085 | tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); | |
7086 | } | |
7087 | ||
f37500d3 MC |
7088 | /* Manage gphy power for all CPMU absent PCIe devices. */ |
7089 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && | |
7090 | !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) | |
1da177e4 | 7091 | val |= GRC_MISC_CFG_KEEP_GPHY_POWER; |
f37500d3 | 7092 | |
1da177e4 LT |
7093 | tw32(GRC_MISC_CFG, val); |
7094 | ||
1ee582d8 MC |
7095 | /* restore 5701 hardware bug workaround write method */ |
7096 | tp->write32 = write_op; | |
1da177e4 LT |
7097 | |
7098 | /* Unfortunately, we have to delay before the PCI read back. | |
7099 | * Some 575X chips even will not respond to a PCI cfg access | |
7100 | * when the reset command is given to the chip. | |
7101 | * | |
7102 | * How do these hardware designers expect things to work | |
7103 | * properly if the PCI write is posted for a long period | |
7104 | * of time? It is always necessary to have some method by | |
7105 | * which a register read back can occur to push the write | |
7106 | * out which does the reset. | |
7107 | * | |
7108 | * For most tg3 variants the trick below was working. | |
7109 | * Ho hum... | |
7110 | */ | |
7111 | udelay(120); | |
7112 | ||
7113 | /* Flush PCI posted writes. The normal MMIO registers | |
7114 | * are inaccessible at this time so this is the only | |
7115 | * way to make this reliably (actually, this is no longer | |
7116 | * the case, see above). I tried to use indirect | |
7117 | * register read/write but this upset some 5701 variants. | |
7118 | */ | |
7119 | pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); | |
7120 | ||
7121 | udelay(120); | |
7122 | ||
5e7dfd0f | 7123 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) { |
e7126997 MC |
7124 | u16 val16; |
7125 | ||
1da177e4 LT |
7126 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { |
7127 | int i; | |
7128 | u32 cfg_val; | |
7129 | ||
7130 | /* Wait for link training to complete. */ | |
7131 | for (i = 0; i < 5000; i++) | |
7132 | udelay(100); | |
7133 | ||
7134 | pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); | |
7135 | pci_write_config_dword(tp->pdev, 0xc4, | |
7136 | cfg_val | (1 << 15)); | |
7137 | } | |
5e7dfd0f | 7138 | |
e7126997 MC |
7139 | /* Clear the "no snoop" and "relaxed ordering" bits. */ |
7140 | pci_read_config_word(tp->pdev, | |
7141 | tp->pcie_cap + PCI_EXP_DEVCTL, | |
7142 | &val16); | |
7143 | val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN | | |
7144 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
7145 | /* | |
7146 | * Older PCIe devices only support the 128 byte | |
7147 | * MPS setting. Enforce the restriction. | |
5e7dfd0f | 7148 | */ |
6de34cb9 | 7149 | if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) |
e7126997 | 7150 | val16 &= ~PCI_EXP_DEVCTL_PAYLOAD; |
5e7dfd0f MC |
7151 | pci_write_config_word(tp->pdev, |
7152 | tp->pcie_cap + PCI_EXP_DEVCTL, | |
e7126997 | 7153 | val16); |
5e7dfd0f | 7154 | |
cf79003d | 7155 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); |
5e7dfd0f MC |
7156 | |
7157 | /* Clear error status */ | |
7158 | pci_write_config_word(tp->pdev, | |
7159 | tp->pcie_cap + PCI_EXP_DEVSTA, | |
7160 | PCI_EXP_DEVSTA_CED | | |
7161 | PCI_EXP_DEVSTA_NFED | | |
7162 | PCI_EXP_DEVSTA_FED | | |
7163 | PCI_EXP_DEVSTA_URD); | |
1da177e4 LT |
7164 | } |
7165 | ||
ee6a99b5 | 7166 | tg3_restore_pci_state(tp); |
1da177e4 | 7167 | |
d18edcb2 MC |
7168 | tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING; |
7169 | ||
ee6a99b5 MC |
7170 | val = 0; |
7171 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) | |
4cf78e4f | 7172 | val = tr32(MEMARB_MODE); |
ee6a99b5 | 7173 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); |
1da177e4 LT |
7174 | |
7175 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) { | |
7176 | tg3_stop_fw(tp); | |
7177 | tw32(0x5000, 0x400); | |
7178 | } | |
7179 | ||
7180 | tw32(GRC_MODE, tp->grc_mode); | |
7181 | ||
7182 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { | |
ab0049b4 | 7183 | val = tr32(0xc4); |
1da177e4 LT |
7184 | |
7185 | tw32(0xc4, val | (1 << 15)); | |
7186 | } | |
7187 | ||
7188 | if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && | |
7189 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
7190 | tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; | |
7191 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) | |
7192 | tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; | |
7193 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
7194 | } | |
7195 | ||
d2394e6b MC |
7196 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
7197 | tp->mac_mode = MAC_MODE_APE_TX_EN | | |
7198 | MAC_MODE_APE_RX_EN | | |
7199 | MAC_MODE_TDE_ENABLE; | |
7200 | ||
f07e9af3 | 7201 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
d2394e6b MC |
7202 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; |
7203 | val = tp->mac_mode; | |
f07e9af3 | 7204 | } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
d2394e6b MC |
7205 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
7206 | val = tp->mac_mode; | |
1da177e4 | 7207 | } else |
d2394e6b MC |
7208 | val = 0; |
7209 | ||
7210 | tw32_f(MAC_MODE, val); | |
1da177e4 LT |
7211 | udelay(40); |
7212 | ||
77b483f1 MC |
7213 | tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); |
7214 | ||
7a6f4369 MC |
7215 | err = tg3_poll_fw(tp); |
7216 | if (err) | |
7217 | return err; | |
1da177e4 | 7218 | |
0a9140cf MC |
7219 | tg3_mdio_start(tp); |
7220 | ||
1da177e4 | 7221 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && |
f6eb9b1f MC |
7222 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && |
7223 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
c885e824 | 7224 | !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) { |
ab0049b4 | 7225 | val = tr32(0x7c00); |
1da177e4 LT |
7226 | |
7227 | tw32(0x7c00, val | (1 << 25)); | |
7228 | } | |
7229 | ||
7230 | /* Reprobe ASF enable state. */ | |
7231 | tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF; | |
7232 | tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE; | |
7233 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); | |
7234 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
7235 | u32 nic_cfg; | |
7236 | ||
7237 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
7238 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
7239 | tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; | |
4ba526ce | 7240 | tp->last_event_jiffies = jiffies; |
cbf46853 | 7241 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
1da177e4 LT |
7242 | tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; |
7243 | } | |
7244 | } | |
7245 | ||
7246 | return 0; | |
7247 | } | |
7248 | ||
7249 | /* tp->lock is held. */ | |
7250 | static void tg3_stop_fw(struct tg3 *tp) | |
7251 | { | |
0d3031d9 MC |
7252 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && |
7253 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
7c5026aa MC |
7254 | /* Wait for RX cpu to ACK the previous event. */ |
7255 | tg3_wait_for_event_ack(tp); | |
1da177e4 LT |
7256 | |
7257 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); | |
4ba526ce MC |
7258 | |
7259 | tg3_generate_fw_event(tp); | |
1da177e4 | 7260 | |
7c5026aa MC |
7261 | /* Wait for RX cpu to ACK this event. */ |
7262 | tg3_wait_for_event_ack(tp); | |
1da177e4 LT |
7263 | } |
7264 | } | |
7265 | ||
7266 | /* tp->lock is held. */ | |
944d980e | 7267 | static int tg3_halt(struct tg3 *tp, int kind, int silent) |
1da177e4 LT |
7268 | { |
7269 | int err; | |
7270 | ||
7271 | tg3_stop_fw(tp); | |
7272 | ||
944d980e | 7273 | tg3_write_sig_pre_reset(tp, kind); |
1da177e4 | 7274 | |
b3b7d6be | 7275 | tg3_abort_hw(tp, silent); |
1da177e4 LT |
7276 | err = tg3_chip_reset(tp); |
7277 | ||
daba2a63 MC |
7278 | __tg3_set_mac_addr(tp, 0); |
7279 | ||
944d980e MC |
7280 | tg3_write_sig_legacy(tp, kind); |
7281 | tg3_write_sig_post_reset(tp, kind); | |
1da177e4 LT |
7282 | |
7283 | if (err) | |
7284 | return err; | |
7285 | ||
7286 | return 0; | |
7287 | } | |
7288 | ||
1da177e4 LT |
7289 | #define RX_CPU_SCRATCH_BASE 0x30000 |
7290 | #define RX_CPU_SCRATCH_SIZE 0x04000 | |
7291 | #define TX_CPU_SCRATCH_BASE 0x34000 | |
7292 | #define TX_CPU_SCRATCH_SIZE 0x04000 | |
7293 | ||
7294 | /* tp->lock is held. */ | |
7295 | static int tg3_halt_cpu(struct tg3 *tp, u32 offset) | |
7296 | { | |
7297 | int i; | |
7298 | ||
5d9428de ES |
7299 | BUG_ON(offset == TX_CPU_BASE && |
7300 | (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)); | |
1da177e4 | 7301 | |
b5d3772c MC |
7302 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
7303 | u32 val = tr32(GRC_VCPU_EXT_CTRL); | |
7304 | ||
7305 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); | |
7306 | return 0; | |
7307 | } | |
1da177e4 LT |
7308 | if (offset == RX_CPU_BASE) { |
7309 | for (i = 0; i < 10000; i++) { | |
7310 | tw32(offset + CPU_STATE, 0xffffffff); | |
7311 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
7312 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
7313 | break; | |
7314 | } | |
7315 | ||
7316 | tw32(offset + CPU_STATE, 0xffffffff); | |
7317 | tw32_f(offset + CPU_MODE, CPU_MODE_HALT); | |
7318 | udelay(10); | |
7319 | } else { | |
7320 | for (i = 0; i < 10000; i++) { | |
7321 | tw32(offset + CPU_STATE, 0xffffffff); | |
7322 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
7323 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
7324 | break; | |
7325 | } | |
7326 | } | |
7327 | ||
7328 | if (i >= 10000) { | |
05dbe005 JP |
7329 | netdev_err(tp->dev, "%s timed out, %s CPU\n", |
7330 | __func__, offset == RX_CPU_BASE ? "RX" : "TX"); | |
1da177e4 LT |
7331 | return -ENODEV; |
7332 | } | |
ec41c7df MC |
7333 | |
7334 | /* Clear firmware's nvram arbitration. */ | |
7335 | if (tp->tg3_flags & TG3_FLAG_NVRAM) | |
7336 | tw32(NVRAM_SWARB, SWARB_REQ_CLR0); | |
1da177e4 LT |
7337 | return 0; |
7338 | } | |
7339 | ||
7340 | struct fw_info { | |
077f849d JSR |
7341 | unsigned int fw_base; |
7342 | unsigned int fw_len; | |
7343 | const __be32 *fw_data; | |
1da177e4 LT |
7344 | }; |
7345 | ||
7346 | /* tp->lock is held. */ | |
7347 | static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base, | |
7348 | int cpu_scratch_size, struct fw_info *info) | |
7349 | { | |
ec41c7df | 7350 | int err, lock_err, i; |
1da177e4 LT |
7351 | void (*write_op)(struct tg3 *, u32, u32); |
7352 | ||
7353 | if (cpu_base == TX_CPU_BASE && | |
7354 | (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
5129c3a3 MC |
7355 | netdev_err(tp->dev, |
7356 | "%s: Trying to load TX cpu firmware which is 5705\n", | |
05dbe005 | 7357 | __func__); |
1da177e4 LT |
7358 | return -EINVAL; |
7359 | } | |
7360 | ||
7361 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | |
7362 | write_op = tg3_write_mem; | |
7363 | else | |
7364 | write_op = tg3_write_indirect_reg32; | |
7365 | ||
1b628151 MC |
7366 | /* It is possible that bootcode is still loading at this point. |
7367 | * Get the nvram lock first before halting the cpu. | |
7368 | */ | |
ec41c7df | 7369 | lock_err = tg3_nvram_lock(tp); |
1da177e4 | 7370 | err = tg3_halt_cpu(tp, cpu_base); |
ec41c7df MC |
7371 | if (!lock_err) |
7372 | tg3_nvram_unlock(tp); | |
1da177e4 LT |
7373 | if (err) |
7374 | goto out; | |
7375 | ||
7376 | for (i = 0; i < cpu_scratch_size; i += sizeof(u32)) | |
7377 | write_op(tp, cpu_scratch_base + i, 0); | |
7378 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7379 | tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT); | |
077f849d | 7380 | for (i = 0; i < (info->fw_len / sizeof(u32)); i++) |
1da177e4 | 7381 | write_op(tp, (cpu_scratch_base + |
077f849d | 7382 | (info->fw_base & 0xffff) + |
1da177e4 | 7383 | (i * sizeof(u32))), |
077f849d | 7384 | be32_to_cpu(info->fw_data[i])); |
1da177e4 LT |
7385 | |
7386 | err = 0; | |
7387 | ||
7388 | out: | |
1da177e4 LT |
7389 | return err; |
7390 | } | |
7391 | ||
7392 | /* tp->lock is held. */ | |
7393 | static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) | |
7394 | { | |
7395 | struct fw_info info; | |
077f849d | 7396 | const __be32 *fw_data; |
1da177e4 LT |
7397 | int err, i; |
7398 | ||
077f849d JSR |
7399 | fw_data = (void *)tp->fw->data; |
7400 | ||
7401 | /* Firmware blob starts with version numbers, followed by | |
7402 | start address and length. We are setting complete length. | |
7403 | length = end_address_of_bss - start_address_of_text. | |
7404 | Remainder is the blob to be loaded contiguously | |
7405 | from start address. */ | |
7406 | ||
7407 | info.fw_base = be32_to_cpu(fw_data[1]); | |
7408 | info.fw_len = tp->fw->size - 12; | |
7409 | info.fw_data = &fw_data[3]; | |
1da177e4 LT |
7410 | |
7411 | err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, | |
7412 | RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE, | |
7413 | &info); | |
7414 | if (err) | |
7415 | return err; | |
7416 | ||
7417 | err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, | |
7418 | TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE, | |
7419 | &info); | |
7420 | if (err) | |
7421 | return err; | |
7422 | ||
7423 | /* Now startup only the RX cpu. */ | |
7424 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
077f849d | 7425 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); |
1da177e4 LT |
7426 | |
7427 | for (i = 0; i < 5; i++) { | |
077f849d | 7428 | if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base) |
1da177e4 LT |
7429 | break; |
7430 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
7431 | tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT); | |
077f849d | 7432 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); |
1da177e4 LT |
7433 | udelay(1000); |
7434 | } | |
7435 | if (i >= 5) { | |
5129c3a3 MC |
7436 | netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " |
7437 | "should be %08x\n", __func__, | |
05dbe005 | 7438 | tr32(RX_CPU_BASE + CPU_PC), info.fw_base); |
1da177e4 LT |
7439 | return -ENODEV; |
7440 | } | |
7441 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
7442 | tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000); | |
7443 | ||
7444 | return 0; | |
7445 | } | |
7446 | ||
1da177e4 | 7447 | /* 5705 needs a special version of the TSO firmware. */ |
1da177e4 LT |
7448 | |
7449 | /* tp->lock is held. */ | |
7450 | static int tg3_load_tso_firmware(struct tg3 *tp) | |
7451 | { | |
7452 | struct fw_info info; | |
077f849d | 7453 | const __be32 *fw_data; |
1da177e4 LT |
7454 | unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; |
7455 | int err, i; | |
7456 | ||
7457 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) | |
7458 | return 0; | |
7459 | ||
077f849d JSR |
7460 | fw_data = (void *)tp->fw->data; |
7461 | ||
7462 | /* Firmware blob starts with version numbers, followed by | |
7463 | start address and length. We are setting complete length. | |
7464 | length = end_address_of_bss - start_address_of_text. | |
7465 | Remainder is the blob to be loaded contiguously | |
7466 | from start address. */ | |
7467 | ||
7468 | info.fw_base = be32_to_cpu(fw_data[1]); | |
7469 | cpu_scratch_size = tp->fw_len; | |
7470 | info.fw_len = tp->fw->size - 12; | |
7471 | info.fw_data = &fw_data[3]; | |
7472 | ||
1da177e4 | 7473 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
7474 | cpu_base = RX_CPU_BASE; |
7475 | cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705; | |
1da177e4 | 7476 | } else { |
1da177e4 LT |
7477 | cpu_base = TX_CPU_BASE; |
7478 | cpu_scratch_base = TX_CPU_SCRATCH_BASE; | |
7479 | cpu_scratch_size = TX_CPU_SCRATCH_SIZE; | |
7480 | } | |
7481 | ||
7482 | err = tg3_load_firmware_cpu(tp, cpu_base, | |
7483 | cpu_scratch_base, cpu_scratch_size, | |
7484 | &info); | |
7485 | if (err) | |
7486 | return err; | |
7487 | ||
7488 | /* Now startup the cpu. */ | |
7489 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
077f849d | 7490 | tw32_f(cpu_base + CPU_PC, info.fw_base); |
1da177e4 LT |
7491 | |
7492 | for (i = 0; i < 5; i++) { | |
077f849d | 7493 | if (tr32(cpu_base + CPU_PC) == info.fw_base) |
1da177e4 LT |
7494 | break; |
7495 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7496 | tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); | |
077f849d | 7497 | tw32_f(cpu_base + CPU_PC, info.fw_base); |
1da177e4 LT |
7498 | udelay(1000); |
7499 | } | |
7500 | if (i >= 5) { | |
5129c3a3 MC |
7501 | netdev_err(tp->dev, |
7502 | "%s fails to set CPU PC, is %08x should be %08x\n", | |
05dbe005 | 7503 | __func__, tr32(cpu_base + CPU_PC), info.fw_base); |
1da177e4 LT |
7504 | return -ENODEV; |
7505 | } | |
7506 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7507 | tw32_f(cpu_base + CPU_MODE, 0x00000000); | |
7508 | return 0; | |
7509 | } | |
7510 | ||
1da177e4 | 7511 | |
1da177e4 LT |
7512 | static int tg3_set_mac_addr(struct net_device *dev, void *p) |
7513 | { | |
7514 | struct tg3 *tp = netdev_priv(dev); | |
7515 | struct sockaddr *addr = p; | |
986e0aeb | 7516 | int err = 0, skip_mac_1 = 0; |
1da177e4 | 7517 | |
f9804ddb MC |
7518 | if (!is_valid_ether_addr(addr->sa_data)) |
7519 | return -EINVAL; | |
7520 | ||
1da177e4 LT |
7521 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
7522 | ||
e75f7c90 MC |
7523 | if (!netif_running(dev)) |
7524 | return 0; | |
7525 | ||
58712ef9 | 7526 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { |
986e0aeb | 7527 | u32 addr0_high, addr0_low, addr1_high, addr1_low; |
58712ef9 | 7528 | |
986e0aeb MC |
7529 | addr0_high = tr32(MAC_ADDR_0_HIGH); |
7530 | addr0_low = tr32(MAC_ADDR_0_LOW); | |
7531 | addr1_high = tr32(MAC_ADDR_1_HIGH); | |
7532 | addr1_low = tr32(MAC_ADDR_1_LOW); | |
7533 | ||
7534 | /* Skip MAC addr 1 if ASF is using it. */ | |
7535 | if ((addr0_high != addr1_high || addr0_low != addr1_low) && | |
7536 | !(addr1_high == 0 && addr1_low == 0)) | |
7537 | skip_mac_1 = 1; | |
58712ef9 | 7538 | } |
986e0aeb MC |
7539 | spin_lock_bh(&tp->lock); |
7540 | __tg3_set_mac_addr(tp, skip_mac_1); | |
7541 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 7542 | |
b9ec6c1b | 7543 | return err; |
1da177e4 LT |
7544 | } |
7545 | ||
7546 | /* tp->lock is held. */ | |
7547 | static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, | |
7548 | dma_addr_t mapping, u32 maxlen_flags, | |
7549 | u32 nic_addr) | |
7550 | { | |
7551 | tg3_write_mem(tp, | |
7552 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
7553 | ((u64) mapping >> 32)); | |
7554 | tg3_write_mem(tp, | |
7555 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW), | |
7556 | ((u64) mapping & 0xffffffff)); | |
7557 | tg3_write_mem(tp, | |
7558 | (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS), | |
7559 | maxlen_flags); | |
7560 | ||
7561 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
7562 | tg3_write_mem(tp, | |
7563 | (bdinfo_addr + TG3_BDINFO_NIC_ADDR), | |
7564 | nic_addr); | |
7565 | } | |
7566 | ||
7567 | static void __tg3_set_rx_mode(struct net_device *); | |
d244c892 | 7568 | static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) |
15f9850d | 7569 | { |
b6080e12 MC |
7570 | int i; |
7571 | ||
19cfaecc | 7572 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) { |
b6080e12 MC |
7573 | tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); |
7574 | tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); | |
7575 | tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); | |
b6080e12 MC |
7576 | } else { |
7577 | tw32(HOSTCC_TXCOL_TICKS, 0); | |
7578 | tw32(HOSTCC_TXMAX_FRAMES, 0); | |
7579 | tw32(HOSTCC_TXCOAL_MAXF_INT, 0); | |
19cfaecc | 7580 | } |
b6080e12 | 7581 | |
20d7375c | 7582 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) { |
19cfaecc MC |
7583 | tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); |
7584 | tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); | |
7585 | tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); | |
7586 | } else { | |
b6080e12 MC |
7587 | tw32(HOSTCC_RXCOL_TICKS, 0); |
7588 | tw32(HOSTCC_RXMAX_FRAMES, 0); | |
7589 | tw32(HOSTCC_RXCOAL_MAXF_INT, 0); | |
15f9850d | 7590 | } |
b6080e12 | 7591 | |
15f9850d DM |
7592 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { |
7593 | u32 val = ec->stats_block_coalesce_usecs; | |
7594 | ||
b6080e12 MC |
7595 | tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); |
7596 | tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); | |
7597 | ||
15f9850d DM |
7598 | if (!netif_carrier_ok(tp->dev)) |
7599 | val = 0; | |
7600 | ||
7601 | tw32(HOSTCC_STAT_COAL_TICKS, val); | |
7602 | } | |
b6080e12 MC |
7603 | |
7604 | for (i = 0; i < tp->irq_cnt - 1; i++) { | |
7605 | u32 reg; | |
7606 | ||
7607 | reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18; | |
7608 | tw32(reg, ec->rx_coalesce_usecs); | |
b6080e12 MC |
7609 | reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18; |
7610 | tw32(reg, ec->rx_max_coalesced_frames); | |
b6080e12 MC |
7611 | reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18; |
7612 | tw32(reg, ec->rx_max_coalesced_frames_irq); | |
19cfaecc MC |
7613 | |
7614 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) { | |
7615 | reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18; | |
7616 | tw32(reg, ec->tx_coalesce_usecs); | |
7617 | reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18; | |
7618 | tw32(reg, ec->tx_max_coalesced_frames); | |
7619 | reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18; | |
7620 | tw32(reg, ec->tx_max_coalesced_frames_irq); | |
7621 | } | |
b6080e12 MC |
7622 | } |
7623 | ||
7624 | for (; i < tp->irq_max - 1; i++) { | |
7625 | tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0); | |
b6080e12 | 7626 | tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0); |
b6080e12 | 7627 | tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); |
19cfaecc MC |
7628 | |
7629 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) { | |
7630 | tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0); | |
7631 | tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0); | |
7632 | tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); | |
7633 | } | |
b6080e12 | 7634 | } |
15f9850d | 7635 | } |
1da177e4 | 7636 | |
2d31ecaf MC |
7637 | /* tp->lock is held. */ |
7638 | static void tg3_rings_reset(struct tg3 *tp) | |
7639 | { | |
7640 | int i; | |
f77a6a8e | 7641 | u32 stblk, txrcb, rxrcb, limit; |
2d31ecaf MC |
7642 | struct tg3_napi *tnapi = &tp->napi[0]; |
7643 | ||
7644 | /* Disable all transmit rings but the first. */ | |
7645 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
7646 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; | |
3d37728b MC |
7647 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
7648 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
7649 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; | |
b703df6f MC |
7650 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
7651 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; | |
2d31ecaf MC |
7652 | else |
7653 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
7654 | ||
7655 | for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
7656 | txrcb < limit; txrcb += TG3_BDINFO_SIZE) | |
7657 | tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
7658 | BDINFO_FLAGS_DISABLED); | |
7659 | ||
7660 | ||
7661 | /* Disable all receive return rings but the first. */ | |
a50d0796 MC |
7662 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
7663 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
f6eb9b1f MC |
7664 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; |
7665 | else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
2d31ecaf | 7666 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; |
b703df6f MC |
7667 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
7668 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
2d31ecaf MC |
7669 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; |
7670 | else | |
7671 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
7672 | ||
7673 | for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
7674 | rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) | |
7675 | tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
7676 | BDINFO_FLAGS_DISABLED); | |
7677 | ||
7678 | /* Disable interrupts */ | |
7679 | tw32_mailbox_f(tp->napi[0].int_mbox, 1); | |
7680 | ||
7681 | /* Zero mailbox registers. */ | |
f77a6a8e | 7682 | if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) { |
6fd45cb8 | 7683 | for (i = 1; i < tp->irq_max; i++) { |
f77a6a8e MC |
7684 | tp->napi[i].tx_prod = 0; |
7685 | tp->napi[i].tx_cons = 0; | |
c2353a32 MC |
7686 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
7687 | tw32_mailbox(tp->napi[i].prodmbox, 0); | |
f77a6a8e MC |
7688 | tw32_rx_mbox(tp->napi[i].consmbox, 0); |
7689 | tw32_mailbox_f(tp->napi[i].int_mbox, 1); | |
7690 | } | |
c2353a32 MC |
7691 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) |
7692 | tw32_mailbox(tp->napi[0].prodmbox, 0); | |
f77a6a8e MC |
7693 | } else { |
7694 | tp->napi[0].tx_prod = 0; | |
7695 | tp->napi[0].tx_cons = 0; | |
7696 | tw32_mailbox(tp->napi[0].prodmbox, 0); | |
7697 | tw32_rx_mbox(tp->napi[0].consmbox, 0); | |
7698 | } | |
2d31ecaf MC |
7699 | |
7700 | /* Make sure the NIC-based send BD rings are disabled. */ | |
7701 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
7702 | u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
7703 | for (i = 0; i < 16; i++) | |
7704 | tw32_tx_mbox(mbox + i * 8, 0); | |
7705 | } | |
7706 | ||
7707 | txrcb = NIC_SRAM_SEND_RCB; | |
7708 | rxrcb = NIC_SRAM_RCV_RET_RCB; | |
7709 | ||
7710 | /* Clear status block in ram. */ | |
7711 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7712 | ||
7713 | /* Set status block DMA address */ | |
7714 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
7715 | ((u64) tnapi->status_mapping >> 32)); | |
7716 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
7717 | ((u64) tnapi->status_mapping & 0xffffffff)); | |
7718 | ||
f77a6a8e MC |
7719 | if (tnapi->tx_ring) { |
7720 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
7721 | (TG3_TX_RING_SIZE << | |
7722 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
7723 | NIC_SRAM_TX_BUFFER_DESC); | |
7724 | txrcb += TG3_BDINFO_SIZE; | |
7725 | } | |
7726 | ||
7727 | if (tnapi->rx_rcb) { | |
7728 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 MC |
7729 | (tp->rx_ret_ring_mask + 1) << |
7730 | BDINFO_FLAGS_MAXLEN_SHIFT, 0); | |
f77a6a8e MC |
7731 | rxrcb += TG3_BDINFO_SIZE; |
7732 | } | |
7733 | ||
7734 | stblk = HOSTCC_STATBLCK_RING1; | |
2d31ecaf | 7735 | |
f77a6a8e MC |
7736 | for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { |
7737 | u64 mapping = (u64)tnapi->status_mapping; | |
7738 | tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32); | |
7739 | tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff); | |
7740 | ||
7741 | /* Clear status block in ram. */ | |
7742 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7743 | ||
19cfaecc MC |
7744 | if (tnapi->tx_ring) { |
7745 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
7746 | (TG3_TX_RING_SIZE << | |
7747 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
7748 | NIC_SRAM_TX_BUFFER_DESC); | |
7749 | txrcb += TG3_BDINFO_SIZE; | |
7750 | } | |
f77a6a8e MC |
7751 | |
7752 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 | 7753 | ((tp->rx_ret_ring_mask + 1) << |
f77a6a8e MC |
7754 | BDINFO_FLAGS_MAXLEN_SHIFT), 0); |
7755 | ||
7756 | stblk += 8; | |
f77a6a8e MC |
7757 | rxrcb += TG3_BDINFO_SIZE; |
7758 | } | |
2d31ecaf MC |
7759 | } |
7760 | ||
1da177e4 | 7761 | /* tp->lock is held. */ |
8e7a22e3 | 7762 | static int tg3_reset_hw(struct tg3 *tp, int reset_phy) |
1da177e4 LT |
7763 | { |
7764 | u32 val, rdmac_mode; | |
7765 | int i, err, limit; | |
8fea32b9 | 7766 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
1da177e4 LT |
7767 | |
7768 | tg3_disable_ints(tp); | |
7769 | ||
7770 | tg3_stop_fw(tp); | |
7771 | ||
7772 | tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); | |
7773 | ||
859a5887 | 7774 | if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) |
e6de8ad1 | 7775 | tg3_abort_hw(tp, 1); |
1da177e4 | 7776 | |
699c0193 MC |
7777 | /* Enable MAC control of LPI */ |
7778 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) { | |
7779 | tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, | |
7780 | TG3_CPMU_EEE_LNKIDL_PCIE_NL0 | | |
7781 | TG3_CPMU_EEE_LNKIDL_UART_IDL); | |
7782 | ||
7783 | tw32_f(TG3_CPMU_EEE_CTRL, | |
7784 | TG3_CPMU_EEE_CTRL_EXIT_20_1_US); | |
7785 | ||
a386b901 MC |
7786 | val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET | |
7787 | TG3_CPMU_EEEMD_LPI_IN_TX | | |
7788 | TG3_CPMU_EEEMD_LPI_IN_RX | | |
7789 | TG3_CPMU_EEEMD_EEE_ENABLE; | |
7790 | ||
7791 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) | |
7792 | val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN; | |
7793 | ||
7794 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
7795 | val |= TG3_CPMU_EEEMD_APE_TX_DET_EN; | |
7796 | ||
7797 | tw32_f(TG3_CPMU_EEE_MODE, val); | |
7798 | ||
7799 | tw32_f(TG3_CPMU_EEE_DBTMR1, | |
7800 | TG3_CPMU_DBTMR1_PCIEXIT_2047US | | |
7801 | TG3_CPMU_DBTMR1_LNKIDLE_2047US); | |
7802 | ||
7803 | tw32_f(TG3_CPMU_EEE_DBTMR2, | |
7804 | TG3_CPMU_DBTMR1_APE_TX_2047US | | |
7805 | TG3_CPMU_DBTMR2_TXIDXEQ_2047US); | |
699c0193 MC |
7806 | } |
7807 | ||
603f1173 | 7808 | if (reset_phy) |
d4d2c558 MC |
7809 | tg3_phy_reset(tp); |
7810 | ||
1da177e4 LT |
7811 | err = tg3_chip_reset(tp); |
7812 | if (err) | |
7813 | return err; | |
7814 | ||
7815 | tg3_write_sig_legacy(tp, RESET_KIND_INIT); | |
7816 | ||
bcb37f6c | 7817 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
d30cdd28 MC |
7818 | val = tr32(TG3_CPMU_CTRL); |
7819 | val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); | |
7820 | tw32(TG3_CPMU_CTRL, val); | |
9acb961e MC |
7821 | |
7822 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
7823 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
7824 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
7825 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
7826 | ||
7827 | val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); | |
7828 | val &= ~CPMU_LNK_AWARE_MACCLK_MASK; | |
7829 | val |= CPMU_LNK_AWARE_MACCLK_6_25; | |
7830 | tw32(TG3_CPMU_LNK_AWARE_PWRMD, val); | |
7831 | ||
7832 | val = tr32(TG3_CPMU_HST_ACC); | |
7833 | val &= ~CPMU_HST_ACC_MACCLK_MASK; | |
7834 | val |= CPMU_HST_ACC_MACCLK_6_25; | |
7835 | tw32(TG3_CPMU_HST_ACC, val); | |
d30cdd28 MC |
7836 | } |
7837 | ||
33466d93 MC |
7838 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
7839 | val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; | |
7840 | val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | | |
7841 | PCIE_PWR_MGMT_L1_THRESH_4MS; | |
7842 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
521e6b90 MC |
7843 | |
7844 | val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; | |
7845 | tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS); | |
7846 | ||
7847 | tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR); | |
33466d93 | 7848 | |
f40386c8 MC |
7849 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; |
7850 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
255ca311 MC |
7851 | } |
7852 | ||
614b0590 MC |
7853 | if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) { |
7854 | u32 grc_mode = tr32(GRC_MODE); | |
7855 | ||
7856 | /* Access the lower 1K of PL PCIE block registers. */ | |
7857 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
7858 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
7859 | ||
7860 | val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); | |
7861 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, | |
7862 | val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN); | |
7863 | ||
7864 | tw32(GRC_MODE, grc_mode); | |
7865 | } | |
7866 | ||
5093eedc MC |
7867 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { |
7868 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { | |
7869 | u32 grc_mode = tr32(GRC_MODE); | |
cea46462 | 7870 | |
5093eedc MC |
7871 | /* Access the lower 1K of PL PCIE block registers. */ |
7872 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
7873 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
cea46462 | 7874 | |
5093eedc MC |
7875 | val = tr32(TG3_PCIE_TLDLPL_PORT + |
7876 | TG3_PCIE_PL_LO_PHYCTL5); | |
7877 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, | |
7878 | val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ); | |
cea46462 | 7879 | |
5093eedc MC |
7880 | tw32(GRC_MODE, grc_mode); |
7881 | } | |
a977dbe8 MC |
7882 | |
7883 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
7884 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
7885 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
7886 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
cea46462 MC |
7887 | } |
7888 | ||
1da177e4 LT |
7889 | /* This works around an issue with Athlon chipsets on |
7890 | * B3 tigon3 silicon. This bit has no effect on any | |
7891 | * other revision. But do not set this on PCI Express | |
795d01c5 | 7892 | * chips and don't even touch the clocks if the CPMU is present. |
1da177e4 | 7893 | */ |
795d01c5 MC |
7894 | if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) { |
7895 | if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
7896 | tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; | |
7897 | tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
7898 | } | |
1da177e4 LT |
7899 | |
7900 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
7901 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { | |
7902 | val = tr32(TG3PCI_PCISTATE); | |
7903 | val |= PCISTATE_RETRY_SAME_DMA; | |
7904 | tw32(TG3PCI_PCISTATE, val); | |
7905 | } | |
7906 | ||
0d3031d9 MC |
7907 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
7908 | /* Allow reads and writes to the | |
7909 | * APE register and memory space. | |
7910 | */ | |
7911 | val = tr32(TG3PCI_PCISTATE); | |
7912 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
7913 | PCISTATE_ALLOW_APE_SHMEM_WR | |
7914 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
7915 | tw32(TG3PCI_PCISTATE, val); |
7916 | } | |
7917 | ||
1da177e4 LT |
7918 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) { |
7919 | /* Enable some hw fixes. */ | |
7920 | val = tr32(TG3PCI_MSI_DATA); | |
7921 | val |= (1 << 26) | (1 << 28) | (1 << 29); | |
7922 | tw32(TG3PCI_MSI_DATA, val); | |
7923 | } | |
7924 | ||
7925 | /* Descriptor ring init may make accesses to the | |
7926 | * NIC SRAM area to setup the TX descriptors, so we | |
7927 | * can only do this after the hardware has been | |
7928 | * successfully reset. | |
7929 | */ | |
32d8c572 MC |
7930 | err = tg3_init_rings(tp); |
7931 | if (err) | |
7932 | return err; | |
1da177e4 | 7933 | |
c885e824 | 7934 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) { |
cbf9ca6c MC |
7935 | val = tr32(TG3PCI_DMA_RW_CTRL) & |
7936 | ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; | |
1a319025 MC |
7937 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) |
7938 | val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK; | |
cbf9ca6c MC |
7939 | tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); |
7940 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && | |
7941 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { | |
d30cdd28 MC |
7942 | /* This value is determined during the probe time DMA |
7943 | * engine test, tg3_test_dma. | |
7944 | */ | |
7945 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
7946 | } | |
1da177e4 LT |
7947 | |
7948 | tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | | |
7949 | GRC_MODE_4X_NIC_SEND_RINGS | | |
7950 | GRC_MODE_NO_TX_PHDR_CSUM | | |
7951 | GRC_MODE_NO_RX_PHDR_CSUM); | |
7952 | tp->grc_mode |= GRC_MODE_HOST_SENDBDS; | |
d2d746f8 MC |
7953 | |
7954 | /* Pseudo-header checksum is done by hardware logic and not | |
7955 | * the offload processers, so make the chip do the pseudo- | |
7956 | * header checksums on receive. For transmit it is more | |
7957 | * convenient to do the pseudo-header checksum in software | |
7958 | * as Linux does that on transmit for us in all cases. | |
7959 | */ | |
7960 | tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; | |
1da177e4 LT |
7961 | |
7962 | tw32(GRC_MODE, | |
7963 | tp->grc_mode | | |
7964 | (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP)); | |
7965 | ||
7966 | /* Setup the timer prescalar register. Clock is always 66Mhz. */ | |
7967 | val = tr32(GRC_MISC_CFG); | |
7968 | val &= ~0xff; | |
7969 | val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
7970 | tw32(GRC_MISC_CFG, val); | |
7971 | ||
7972 | /* Initialize MBUF/DESC pool. */ | |
cbf46853 | 7973 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { |
1da177e4 LT |
7974 | /* Do nothing. */ |
7975 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { | |
7976 | tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); | |
7977 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
7978 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); | |
7979 | else | |
7980 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); | |
7981 | tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); | |
7982 | tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); | |
859a5887 | 7983 | } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) { |
1da177e4 LT |
7984 | int fw_len; |
7985 | ||
077f849d | 7986 | fw_len = tp->fw_len; |
1da177e4 LT |
7987 | fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); |
7988 | tw32(BUFMGR_MB_POOL_ADDR, | |
7989 | NIC_SRAM_MBUF_POOL_BASE5705 + fw_len); | |
7990 | tw32(BUFMGR_MB_POOL_SIZE, | |
7991 | NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); | |
7992 | } | |
1da177e4 | 7993 | |
0f893dc6 | 7994 | if (tp->dev->mtu <= ETH_DATA_LEN) { |
1da177e4 LT |
7995 | tw32(BUFMGR_MB_RDMA_LOW_WATER, |
7996 | tp->bufmgr_config.mbuf_read_dma_low_water); | |
7997 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
7998 | tp->bufmgr_config.mbuf_mac_rx_low_water); | |
7999 | tw32(BUFMGR_MB_HIGH_WATER, | |
8000 | tp->bufmgr_config.mbuf_high_water); | |
8001 | } else { | |
8002 | tw32(BUFMGR_MB_RDMA_LOW_WATER, | |
8003 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); | |
8004 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
8005 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); | |
8006 | tw32(BUFMGR_MB_HIGH_WATER, | |
8007 | tp->bufmgr_config.mbuf_high_water_jumbo); | |
8008 | } | |
8009 | tw32(BUFMGR_DMA_LOW_WATER, | |
8010 | tp->bufmgr_config.dma_low_water); | |
8011 | tw32(BUFMGR_DMA_HIGH_WATER, | |
8012 | tp->bufmgr_config.dma_high_water); | |
8013 | ||
d309a46e MC |
8014 | val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE; |
8015 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
8016 | val |= BUFMGR_MODE_NO_TX_UNDERRUN; | |
8017 | tw32(BUFMGR_MODE, val); | |
1da177e4 LT |
8018 | for (i = 0; i < 2000; i++) { |
8019 | if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) | |
8020 | break; | |
8021 | udelay(10); | |
8022 | } | |
8023 | if (i >= 2000) { | |
05dbe005 | 8024 | netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); |
1da177e4 LT |
8025 | return -ENODEV; |
8026 | } | |
8027 | ||
8028 | /* Setup replenish threshold. */ | |
f92905de MC |
8029 | val = tp->rx_pending / 8; |
8030 | if (val == 0) | |
8031 | val = 1; | |
8032 | else if (val > tp->rx_std_max_post) | |
8033 | val = tp->rx_std_max_post; | |
b5d3772c MC |
8034 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
8035 | if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1) | |
8036 | tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); | |
8037 | ||
8038 | if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2)) | |
8039 | val = TG3_RX_INTERNAL_RING_SZ_5906 / 2; | |
8040 | } | |
f92905de MC |
8041 | |
8042 | tw32(RCVBDI_STD_THRESH, val); | |
1da177e4 LT |
8043 | |
8044 | /* Initialize TG3_BDINFO's at: | |
8045 | * RCVDBDI_STD_BD: standard eth size rx ring | |
8046 | * RCVDBDI_JUMBO_BD: jumbo frame rx ring | |
8047 | * RCVDBDI_MINI_BD: small frame rx ring (??? does not work) | |
8048 | * | |
8049 | * like so: | |
8050 | * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring | |
8051 | * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) | | |
8052 | * ring attribute flags | |
8053 | * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM | |
8054 | * | |
8055 | * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries. | |
8056 | * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries. | |
8057 | * | |
8058 | * The size of each ring is fixed in the firmware, but the location is | |
8059 | * configurable. | |
8060 | */ | |
8061 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
21f581a5 | 8062 | ((u64) tpr->rx_std_mapping >> 32)); |
1da177e4 | 8063 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 8064 | ((u64) tpr->rx_std_mapping & 0xffffffff)); |
a50d0796 MC |
8065 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && |
8066 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719) | |
87668d35 MC |
8067 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, |
8068 | NIC_SRAM_RX_BUFFER_DESC); | |
1da177e4 | 8069 | |
fdb72b38 MC |
8070 | /* Disable the mini ring */ |
8071 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
1da177e4 LT |
8072 | tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, |
8073 | BDINFO_FLAGS_DISABLED); | |
8074 | ||
fdb72b38 MC |
8075 | /* Program the jumbo buffer descriptor ring control |
8076 | * blocks on those devices that have them. | |
8077 | */ | |
4d163b75 MC |
8078 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || |
8079 | ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && | |
8080 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))) { | |
1da177e4 LT |
8081 | /* Setup replenish threshold. */ |
8082 | tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8); | |
8083 | ||
0f893dc6 | 8084 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) { |
1da177e4 | 8085 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, |
21f581a5 | 8086 | ((u64) tpr->rx_jmb_mapping >> 32)); |
1da177e4 | 8087 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 8088 | ((u64) tpr->rx_jmb_mapping & 0xffffffff)); |
1da177e4 | 8089 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, |
79ed5ac7 MC |
8090 | (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) | |
8091 | BDINFO_FLAGS_USE_EXT_RECV); | |
a50d0796 MC |
8092 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) || |
8093 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
87668d35 MC |
8094 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, |
8095 | NIC_SRAM_RX_JUMBO_BUFFER_DESC); | |
1da177e4 LT |
8096 | } else { |
8097 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
8098 | BDINFO_FLAGS_DISABLED); | |
8099 | } | |
8100 | ||
7cb32cf2 MC |
8101 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) { |
8102 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
8103 | val = RX_STD_MAX_SIZE_5705; | |
8104 | else | |
8105 | val = RX_STD_MAX_SIZE_5717; | |
8106 | val <<= BDINFO_FLAGS_MAXLEN_SHIFT; | |
8107 | val |= (TG3_RX_STD_DMA_SZ << 2); | |
8108 | } else | |
04380d40 | 8109 | val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 MC |
8110 | } else |
8111 | val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT; | |
8112 | ||
8113 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val); | |
1da177e4 | 8114 | |
411da640 | 8115 | tpr->rx_std_prod_idx = tp->rx_pending; |
66711e66 | 8116 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); |
1da177e4 | 8117 | |
411da640 | 8118 | tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ? |
21f581a5 | 8119 | tp->rx_jumbo_pending : 0; |
66711e66 | 8120 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); |
1da177e4 | 8121 | |
c885e824 | 8122 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) { |
f6eb9b1f MC |
8123 | tw32(STD_REPLENISH_LWM, 32); |
8124 | tw32(JMB_REPLENISH_LWM, 16); | |
8125 | } | |
8126 | ||
2d31ecaf MC |
8127 | tg3_rings_reset(tp); |
8128 | ||
1da177e4 | 8129 | /* Initialize MAC address and backoff seed. */ |
986e0aeb | 8130 | __tg3_set_mac_addr(tp, 0); |
1da177e4 LT |
8131 | |
8132 | /* MTU + ethernet header + FCS + optional VLAN tag */ | |
f7b493e0 MC |
8133 | tw32(MAC_RX_MTU_SIZE, |
8134 | tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); | |
1da177e4 LT |
8135 | |
8136 | /* The slot time is changed by tg3_setup_phy if we | |
8137 | * run at gigabit with half duplex. | |
8138 | */ | |
8139 | tw32(MAC_TX_LENGTHS, | |
8140 | (2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
8141 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
8142 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
8143 | ||
8144 | /* Receive rules. */ | |
8145 | tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS); | |
8146 | tw32(RCVLPC_CONFIG, 0x0181); | |
8147 | ||
8148 | /* Calculate RDMAC_MODE setting early, we need it to determine | |
8149 | * the RCVLPC_STATE_ENABLE mask. | |
8150 | */ | |
8151 | rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB | | |
8152 | RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB | | |
8153 | RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB | | |
8154 | RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | | |
8155 | RDMAC_MODE_LNGREAD_ENAB); | |
85e94ced | 8156 | |
deabaac8 | 8157 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) |
0339e4e3 MC |
8158 | rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS; |
8159 | ||
57e6983c | 8160 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 MC |
8161 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
8162 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
d30cdd28 MC |
8163 | rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | |
8164 | RDMAC_MODE_MBUF_RBD_CRPT_ENAB | | |
8165 | RDMAC_MODE_MBUF_SBD_CRPT_ENAB; | |
8166 | ||
85e94ced MC |
8167 | /* If statement applies to 5705 and 5750 PCI devices only */ |
8168 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
8169 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) || | |
8170 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) { | |
1da177e4 | 8171 | if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE && |
c13e3713 | 8172 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
8173 | rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128; |
8174 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
8175 | !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) { | |
8176 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; | |
8177 | } | |
8178 | } | |
8179 | ||
85e94ced MC |
8180 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) |
8181 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; | |
8182 | ||
1da177e4 | 8183 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) |
027455ad MC |
8184 | rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN; |
8185 | ||
e849cdc3 MC |
8186 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) || |
8187 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
027455ad MC |
8188 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
8189 | rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN; | |
1da177e4 | 8190 | |
41a8a7ee MC |
8191 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
8192 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
8193 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
8194 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
8195 | (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) { | |
8196 | val = tr32(TG3_RDMA_RSRVCTRL_REG); | |
b75cc0e4 | 8197 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) { |
b4495ed8 MC |
8198 | val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK | |
8199 | TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK | | |
8200 | TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK); | |
8201 | val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B | | |
8202 | TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K | | |
8203 | TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K; | |
b75cc0e4 | 8204 | } |
41a8a7ee MC |
8205 | tw32(TG3_RDMA_RSRVCTRL_REG, |
8206 | val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX); | |
8207 | } | |
8208 | ||
d309a46e MC |
8209 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) { |
8210 | val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); | |
8211 | tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val | | |
8212 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K | | |
8213 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K); | |
8214 | } | |
8215 | ||
1da177e4 | 8216 | /* Receive/send statistics. */ |
1661394e MC |
8217 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { |
8218 | val = tr32(RCVLPC_STATS_ENABLE); | |
8219 | val &= ~RCVLPC_STATSENAB_DACK_FIX; | |
8220 | tw32(RCVLPC_STATS_ENABLE, val); | |
8221 | } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) && | |
8222 | (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
1da177e4 LT |
8223 | val = tr32(RCVLPC_STATS_ENABLE); |
8224 | val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX; | |
8225 | tw32(RCVLPC_STATS_ENABLE, val); | |
8226 | } else { | |
8227 | tw32(RCVLPC_STATS_ENABLE, 0xffffff); | |
8228 | } | |
8229 | tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE); | |
8230 | tw32(SNDDATAI_STATSENAB, 0xffffff); | |
8231 | tw32(SNDDATAI_STATSCTRL, | |
8232 | (SNDDATAI_SCTRL_ENABLE | | |
8233 | SNDDATAI_SCTRL_FASTUPD)); | |
8234 | ||
8235 | /* Setup host coalescing engine. */ | |
8236 | tw32(HOSTCC_MODE, 0); | |
8237 | for (i = 0; i < 2000; i++) { | |
8238 | if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) | |
8239 | break; | |
8240 | udelay(10); | |
8241 | } | |
8242 | ||
d244c892 | 8243 | __tg3_set_coalesce(tp, &tp->coal); |
1da177e4 | 8244 | |
1da177e4 LT |
8245 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { |
8246 | /* Status/statistics block address. See tg3_timer, | |
8247 | * the tg3_periodic_fetch_stats call there, and | |
8248 | * tg3_get_stats to see how this works for 5705/5750 chips. | |
8249 | */ | |
1da177e4 LT |
8250 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, |
8251 | ((u64) tp->stats_mapping >> 32)); | |
8252 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
8253 | ((u64) tp->stats_mapping & 0xffffffff)); | |
8254 | tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK); | |
2d31ecaf | 8255 | |
1da177e4 | 8256 | tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK); |
2d31ecaf MC |
8257 | |
8258 | /* Clear statistics and status block memory areas */ | |
8259 | for (i = NIC_SRAM_STATS_BLK; | |
8260 | i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE; | |
8261 | i += sizeof(u32)) { | |
8262 | tg3_write_mem(tp, i, 0); | |
8263 | udelay(40); | |
8264 | } | |
1da177e4 LT |
8265 | } |
8266 | ||
8267 | tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); | |
8268 | ||
8269 | tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE); | |
8270 | tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE); | |
8271 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
8272 | tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE); | |
8273 | ||
f07e9af3 MC |
8274 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
8275 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | |
c94e3941 MC |
8276 | /* reset to prevent losing 1st rx packet intermittently */ |
8277 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
8278 | udelay(10); | |
8279 | } | |
8280 | ||
3bda1258 | 8281 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
d2394e6b | 8282 | tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; |
3bda1258 MC |
8283 | else |
8284 | tp->mac_mode = 0; | |
8285 | tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | | |
1da177e4 | 8286 | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE; |
e8f3f6ca | 8287 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && |
f07e9af3 | 8288 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
e8f3f6ca MC |
8289 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |
8290 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
8291 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); |
8292 | udelay(40); | |
8293 | ||
314fba34 | 8294 | /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). |
9d26e213 | 8295 | * If TG3_FLG2_IS_NIC is zero, we should read the |
314fba34 MC |
8296 | * register to preserve the GPIO settings for LOMs. The GPIOs, |
8297 | * whether used as inputs or outputs, are set by boot code after | |
8298 | * reset. | |
8299 | */ | |
9d26e213 | 8300 | if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) { |
314fba34 MC |
8301 | u32 gpio_mask; |
8302 | ||
9d26e213 MC |
8303 | gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 | |
8304 | GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
8305 | GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
3e7d83bc MC |
8306 | |
8307 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
8308 | gpio_mask |= GRC_LCLCTRL_GPIO_OE3 | | |
8309 | GRC_LCLCTRL_GPIO_OUTPUT3; | |
8310 | ||
af36e6b6 MC |
8311 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
8312 | gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL; | |
8313 | ||
aaf84465 | 8314 | tp->grc_local_ctrl &= ~gpio_mask; |
314fba34 MC |
8315 | tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; |
8316 | ||
8317 | /* GPIO1 must be driven high for eeprom write protect */ | |
9d26e213 MC |
8318 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) |
8319 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | | |
8320 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
314fba34 | 8321 | } |
1da177e4 LT |
8322 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
8323 | udelay(100); | |
8324 | ||
0583d521 MC |
8325 | if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) && |
8326 | tp->irq_cnt > 1) { | |
baf8a94a MC |
8327 | val = tr32(MSGINT_MODE); |
8328 | val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE; | |
8329 | tw32(MSGINT_MODE, val); | |
8330 | } | |
8331 | ||
1da177e4 LT |
8332 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { |
8333 | tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); | |
8334 | udelay(40); | |
8335 | } | |
8336 | ||
8337 | val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB | | |
8338 | WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB | | |
8339 | WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB | | |
8340 | WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | | |
8341 | WDMAC_MODE_LNGREAD_ENAB); | |
8342 | ||
85e94ced MC |
8343 | /* If statement applies to 5705 and 5750 PCI devices only */ |
8344 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
8345 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) || | |
8346 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) { | |
29ea095f | 8347 | if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) && |
1da177e4 LT |
8348 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || |
8349 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { | |
8350 | /* nothing */ | |
8351 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
8352 | !(tp->tg3_flags2 & TG3_FLG2_IS_5788) && | |
8353 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) { | |
8354 | val |= WDMAC_MODE_RX_ACCEL; | |
8355 | } | |
8356 | } | |
8357 | ||
d9ab5ad1 | 8358 | /* Enable host coalescing bug fix */ |
321d32a0 | 8359 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
f51f3562 | 8360 | val |= WDMAC_MODE_STATUS_TAG_FIX; |
d9ab5ad1 | 8361 | |
788a035e MC |
8362 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
8363 | val |= WDMAC_MODE_BURST_ALL_DATA; | |
8364 | ||
1da177e4 LT |
8365 | tw32_f(WDMAC_MODE, val); |
8366 | udelay(40); | |
8367 | ||
9974a356 MC |
8368 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { |
8369 | u16 pcix_cmd; | |
8370 | ||
8371 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
8372 | &pcix_cmd); | |
1da177e4 | 8373 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { |
9974a356 MC |
8374 | pcix_cmd &= ~PCI_X_CMD_MAX_READ; |
8375 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 8376 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
9974a356 MC |
8377 | pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ); |
8378 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 8379 | } |
9974a356 MC |
8380 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, |
8381 | pcix_cmd); | |
1da177e4 LT |
8382 | } |
8383 | ||
8384 | tw32_f(RDMAC_MODE, rdmac_mode); | |
8385 | udelay(40); | |
8386 | ||
8387 | tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE); | |
8388 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
8389 | tw32(MBFREE_MODE, MBFREE_MODE_ENABLE); | |
9936bcf6 MC |
8390 | |
8391 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
8392 | tw32(SNDDATAC_MODE, | |
8393 | SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY); | |
8394 | else | |
8395 | tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE); | |
8396 | ||
1da177e4 LT |
8397 | tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE); |
8398 | tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB); | |
7cb32cf2 MC |
8399 | val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ; |
8400 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
8401 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
8402 | val |= RCVDBDI_MODE_LRG_RING_SZ; | |
8403 | tw32(RCVDBDI_MODE, val); | |
1da177e4 | 8404 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); |
1da177e4 LT |
8405 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) |
8406 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8); | |
baf8a94a | 8407 | val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE; |
19cfaecc | 8408 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
baf8a94a MC |
8409 | val |= SNDBDI_MODE_MULTI_TXQ_EN; |
8410 | tw32(SNDBDI_MODE, val); | |
1da177e4 LT |
8411 | tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); |
8412 | ||
8413 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
8414 | err = tg3_load_5701_a0_firmware_fix(tp); | |
8415 | if (err) | |
8416 | return err; | |
8417 | } | |
8418 | ||
1da177e4 LT |
8419 | if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) { |
8420 | err = tg3_load_tso_firmware(tp); | |
8421 | if (err) | |
8422 | return err; | |
8423 | } | |
1da177e4 LT |
8424 | |
8425 | tp->tx_mode = TX_MODE_ENABLE; | |
b1d05210 MC |
8426 | if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || |
8427 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
8428 | tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; | |
1da177e4 LT |
8429 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
8430 | udelay(100); | |
8431 | ||
baf8a94a MC |
8432 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) { |
8433 | u32 reg = MAC_RSS_INDIR_TBL_0; | |
8434 | u8 *ent = (u8 *)&val; | |
8435 | ||
8436 | /* Setup the indirection table */ | |
8437 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) { | |
8438 | int idx = i % sizeof(val); | |
8439 | ||
5efeeea1 | 8440 | ent[idx] = i % (tp->irq_cnt - 1); |
baf8a94a MC |
8441 | if (idx == sizeof(val) - 1) { |
8442 | tw32(reg, val); | |
8443 | reg += 4; | |
8444 | } | |
8445 | } | |
8446 | ||
8447 | /* Setup the "secret" hash key. */ | |
8448 | tw32(MAC_RSS_HASH_KEY_0, 0x5f865437); | |
8449 | tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc); | |
8450 | tw32(MAC_RSS_HASH_KEY_2, 0x50103a45); | |
8451 | tw32(MAC_RSS_HASH_KEY_3, 0x36621985); | |
8452 | tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8); | |
8453 | tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e); | |
8454 | tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556); | |
8455 | tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe); | |
8456 | tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7); | |
8457 | tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481); | |
8458 | } | |
8459 | ||
1da177e4 | 8460 | tp->rx_mode = RX_MODE_ENABLE; |
321d32a0 | 8461 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
af36e6b6 MC |
8462 | tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; |
8463 | ||
baf8a94a MC |
8464 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) |
8465 | tp->rx_mode |= RX_MODE_RSS_ENABLE | | |
8466 | RX_MODE_RSS_ITBL_HASH_BITS_7 | | |
8467 | RX_MODE_RSS_IPV6_HASH_EN | | |
8468 | RX_MODE_RSS_TCP_IPV6_HASH_EN | | |
8469 | RX_MODE_RSS_IPV4_HASH_EN | | |
8470 | RX_MODE_RSS_TCP_IPV4_HASH_EN; | |
8471 | ||
1da177e4 LT |
8472 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
8473 | udelay(10); | |
8474 | ||
1da177e4 LT |
8475 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
8476 | ||
8477 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
f07e9af3 | 8478 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 LT |
8479 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
8480 | udelay(10); | |
8481 | } | |
8482 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
8483 | udelay(10); | |
8484 | ||
f07e9af3 | 8485 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 | 8486 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) && |
f07e9af3 | 8487 | !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { |
1da177e4 LT |
8488 | /* Set drive transmission level to 1.2V */ |
8489 | /* only if the signal pre-emphasis bit is not set */ | |
8490 | val = tr32(MAC_SERDES_CFG); | |
8491 | val &= 0xfffff000; | |
8492 | val |= 0x880; | |
8493 | tw32(MAC_SERDES_CFG, val); | |
8494 | } | |
8495 | if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) | |
8496 | tw32(MAC_SERDES_CFG, 0x616000); | |
8497 | } | |
8498 | ||
8499 | /* Prevent chip from dropping frames when flow control | |
8500 | * is enabled. | |
8501 | */ | |
666bc831 MC |
8502 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
8503 | val = 1; | |
8504 | else | |
8505 | val = 2; | |
8506 | tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val); | |
1da177e4 LT |
8507 | |
8508 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && | |
f07e9af3 | 8509 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
1da177e4 LT |
8510 | /* Use hardware link auto-negotiation */ |
8511 | tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG; | |
8512 | } | |
8513 | ||
f07e9af3 | 8514 | if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
d4d2c558 MC |
8515 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) { |
8516 | u32 tmp; | |
8517 | ||
8518 | tmp = tr32(SERDES_RX_CTRL); | |
8519 | tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT); | |
8520 | tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; | |
8521 | tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; | |
8522 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
8523 | } | |
8524 | ||
dd477003 | 8525 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { |
80096068 MC |
8526 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
8527 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | |
dd477003 MC |
8528 | tp->link_config.speed = tp->link_config.orig_speed; |
8529 | tp->link_config.duplex = tp->link_config.orig_duplex; | |
8530 | tp->link_config.autoneg = tp->link_config.orig_autoneg; | |
8531 | } | |
1da177e4 | 8532 | |
dd477003 MC |
8533 | err = tg3_setup_phy(tp, 0); |
8534 | if (err) | |
8535 | return err; | |
1da177e4 | 8536 | |
f07e9af3 MC |
8537 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
8538 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
dd477003 MC |
8539 | u32 tmp; |
8540 | ||
8541 | /* Clear CRC stats. */ | |
8542 | if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { | |
8543 | tg3_writephy(tp, MII_TG3_TEST1, | |
8544 | tmp | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 8545 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp); |
dd477003 | 8546 | } |
1da177e4 LT |
8547 | } |
8548 | } | |
8549 | ||
8550 | __tg3_set_rx_mode(tp->dev); | |
8551 | ||
8552 | /* Initialize receive rules. */ | |
8553 | tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK); | |
8554 | tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
8555 | tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); | |
8556 | tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
8557 | ||
4cf78e4f | 8558 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && |
a4e2b347 | 8559 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) |
1da177e4 LT |
8560 | limit = 8; |
8561 | else | |
8562 | limit = 16; | |
8563 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) | |
8564 | limit -= 4; | |
8565 | switch (limit) { | |
8566 | case 16: | |
8567 | tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0); | |
8568 | case 15: | |
8569 | tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0); | |
8570 | case 14: | |
8571 | tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0); | |
8572 | case 13: | |
8573 | tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0); | |
8574 | case 12: | |
8575 | tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0); | |
8576 | case 11: | |
8577 | tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0); | |
8578 | case 10: | |
8579 | tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0); | |
8580 | case 9: | |
8581 | tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0); | |
8582 | case 8: | |
8583 | tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0); | |
8584 | case 7: | |
8585 | tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0); | |
8586 | case 6: | |
8587 | tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0); | |
8588 | case 5: | |
8589 | tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0); | |
8590 | case 4: | |
8591 | /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */ | |
8592 | case 3: | |
8593 | /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */ | |
8594 | case 2: | |
8595 | case 1: | |
8596 | ||
8597 | default: | |
8598 | break; | |
855e1111 | 8599 | } |
1da177e4 | 8600 | |
9ce768ea MC |
8601 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
8602 | /* Write our heartbeat update interval to APE. */ | |
8603 | tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, | |
8604 | APE_HOST_HEARTBEAT_INT_DISABLE); | |
0d3031d9 | 8605 | |
1da177e4 LT |
8606 | tg3_write_sig_post_reset(tp, RESET_KIND_INIT); |
8607 | ||
1da177e4 LT |
8608 | return 0; |
8609 | } | |
8610 | ||
8611 | /* Called at device open time to get the chip ready for | |
8612 | * packet processing. Invoked with tp->lock held. | |
8613 | */ | |
8e7a22e3 | 8614 | static int tg3_init_hw(struct tg3 *tp, int reset_phy) |
1da177e4 | 8615 | { |
1da177e4 LT |
8616 | tg3_switch_clocks(tp); |
8617 | ||
8618 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
8619 | ||
2f751b67 | 8620 | return tg3_reset_hw(tp, reset_phy); |
1da177e4 LT |
8621 | } |
8622 | ||
8623 | #define TG3_STAT_ADD32(PSTAT, REG) \ | |
8624 | do { u32 __val = tr32(REG); \ | |
8625 | (PSTAT)->low += __val; \ | |
8626 | if ((PSTAT)->low < __val) \ | |
8627 | (PSTAT)->high += 1; \ | |
8628 | } while (0) | |
8629 | ||
8630 | static void tg3_periodic_fetch_stats(struct tg3 *tp) | |
8631 | { | |
8632 | struct tg3_hw_stats *sp = tp->hw_stats; | |
8633 | ||
8634 | if (!netif_carrier_ok(tp->dev)) | |
8635 | return; | |
8636 | ||
8637 | TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); | |
8638 | TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); | |
8639 | TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); | |
8640 | TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); | |
8641 | TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); | |
8642 | TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); | |
8643 | TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); | |
8644 | TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); | |
8645 | TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); | |
8646 | TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); | |
8647 | TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); | |
8648 | TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); | |
8649 | TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); | |
8650 | ||
8651 | TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); | |
8652 | TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); | |
8653 | TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); | |
8654 | TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); | |
8655 | TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); | |
8656 | TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); | |
8657 | TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); | |
8658 | TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); | |
8659 | TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); | |
8660 | TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); | |
8661 | TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); | |
8662 | TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); | |
8663 | TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); | |
8664 | TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); | |
463d305b MC |
8665 | |
8666 | TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); | |
8667 | TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); | |
8668 | TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); | |
1da177e4 LT |
8669 | } |
8670 | ||
8671 | static void tg3_timer(unsigned long __opaque) | |
8672 | { | |
8673 | struct tg3 *tp = (struct tg3 *) __opaque; | |
1da177e4 | 8674 | |
f475f163 MC |
8675 | if (tp->irq_sync) |
8676 | goto restart_timer; | |
8677 | ||
f47c11ee | 8678 | spin_lock(&tp->lock); |
1da177e4 | 8679 | |
fac9b83e DM |
8680 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { |
8681 | /* All of this garbage is because when using non-tagged | |
8682 | * IRQ status the mailbox/status_block protocol the chip | |
8683 | * uses with the cpu is race prone. | |
8684 | */ | |
898a56f8 | 8685 | if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { |
fac9b83e DM |
8686 | tw32(GRC_LOCAL_CTRL, |
8687 | tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
8688 | } else { | |
8689 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
fd2ce37f | 8690 | HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW); |
fac9b83e | 8691 | } |
1da177e4 | 8692 | |
fac9b83e DM |
8693 | if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { |
8694 | tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER; | |
f47c11ee | 8695 | spin_unlock(&tp->lock); |
fac9b83e DM |
8696 | schedule_work(&tp->reset_task); |
8697 | return; | |
8698 | } | |
1da177e4 LT |
8699 | } |
8700 | ||
1da177e4 LT |
8701 | /* This part only runs once per second. */ |
8702 | if (!--tp->timer_counter) { | |
fac9b83e DM |
8703 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) |
8704 | tg3_periodic_fetch_stats(tp); | |
8705 | ||
52b02d04 MC |
8706 | if (tp->setlpicnt && !--tp->setlpicnt) { |
8707 | u32 val = tr32(TG3_CPMU_EEE_MODE); | |
8708 | tw32(TG3_CPMU_EEE_MODE, | |
8709 | val | TG3_CPMU_EEEMD_LPI_ENABLE); | |
8710 | } | |
8711 | ||
1da177e4 LT |
8712 | if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) { |
8713 | u32 mac_stat; | |
8714 | int phy_event; | |
8715 | ||
8716 | mac_stat = tr32(MAC_STATUS); | |
8717 | ||
8718 | phy_event = 0; | |
f07e9af3 | 8719 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { |
1da177e4 LT |
8720 | if (mac_stat & MAC_STATUS_MI_INTERRUPT) |
8721 | phy_event = 1; | |
8722 | } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) | |
8723 | phy_event = 1; | |
8724 | ||
8725 | if (phy_event) | |
8726 | tg3_setup_phy(tp, 0); | |
8727 | } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) { | |
8728 | u32 mac_stat = tr32(MAC_STATUS); | |
8729 | int need_setup = 0; | |
8730 | ||
8731 | if (netif_carrier_ok(tp->dev) && | |
8732 | (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) { | |
8733 | need_setup = 1; | |
8734 | } | |
be98da6a | 8735 | if (!netif_carrier_ok(tp->dev) && |
1da177e4 LT |
8736 | (mac_stat & (MAC_STATUS_PCS_SYNCED | |
8737 | MAC_STATUS_SIGNAL_DET))) { | |
8738 | need_setup = 1; | |
8739 | } | |
8740 | if (need_setup) { | |
3d3ebe74 MC |
8741 | if (!tp->serdes_counter) { |
8742 | tw32_f(MAC_MODE, | |
8743 | (tp->mac_mode & | |
8744 | ~MAC_MODE_PORT_MODE_MASK)); | |
8745 | udelay(40); | |
8746 | tw32_f(MAC_MODE, tp->mac_mode); | |
8747 | udelay(40); | |
8748 | } | |
1da177e4 LT |
8749 | tg3_setup_phy(tp, 0); |
8750 | } | |
f07e9af3 | 8751 | } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
2138c002 | 8752 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
747e8f8b | 8753 | tg3_serdes_parallel_detect(tp); |
57d8b880 | 8754 | } |
1da177e4 LT |
8755 | |
8756 | tp->timer_counter = tp->timer_multiplier; | |
8757 | } | |
8758 | ||
130b8e4d MC |
8759 | /* Heartbeat is only sent once every 2 seconds. |
8760 | * | |
8761 | * The heartbeat is to tell the ASF firmware that the host | |
8762 | * driver is still alive. In the event that the OS crashes, | |
8763 | * ASF needs to reset the hardware to free up the FIFO space | |
8764 | * that may be filled with rx packets destined for the host. | |
8765 | * If the FIFO is full, ASF will no longer function properly. | |
8766 | * | |
8767 | * Unintended resets have been reported on real time kernels | |
8768 | * where the timer doesn't run on time. Netpoll will also have | |
8769 | * same problem. | |
8770 | * | |
8771 | * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware | |
8772 | * to check the ring condition when the heartbeat is expiring | |
8773 | * before doing the reset. This will prevent most unintended | |
8774 | * resets. | |
8775 | */ | |
1da177e4 | 8776 | if (!--tp->asf_counter) { |
bc7959b2 MC |
8777 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && |
8778 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
7c5026aa MC |
8779 | tg3_wait_for_event_ack(tp); |
8780 | ||
bbadf503 | 8781 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, |
130b8e4d | 8782 | FWCMD_NICDRV_ALIVE3); |
bbadf503 | 8783 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); |
c6cdf436 MC |
8784 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, |
8785 | TG3_FW_UPDATE_TIMEOUT_SEC); | |
4ba526ce MC |
8786 | |
8787 | tg3_generate_fw_event(tp); | |
1da177e4 LT |
8788 | } |
8789 | tp->asf_counter = tp->asf_multiplier; | |
8790 | } | |
8791 | ||
f47c11ee | 8792 | spin_unlock(&tp->lock); |
1da177e4 | 8793 | |
f475f163 | 8794 | restart_timer: |
1da177e4 LT |
8795 | tp->timer.expires = jiffies + tp->timer_offset; |
8796 | add_timer(&tp->timer); | |
8797 | } | |
8798 | ||
4f125f42 | 8799 | static int tg3_request_irq(struct tg3 *tp, int irq_num) |
fcfa0a32 | 8800 | { |
7d12e780 | 8801 | irq_handler_t fn; |
fcfa0a32 | 8802 | unsigned long flags; |
4f125f42 MC |
8803 | char *name; |
8804 | struct tg3_napi *tnapi = &tp->napi[irq_num]; | |
8805 | ||
8806 | if (tp->irq_cnt == 1) | |
8807 | name = tp->dev->name; | |
8808 | else { | |
8809 | name = &tnapi->irq_lbl[0]; | |
8810 | snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num); | |
8811 | name[IFNAMSIZ-1] = 0; | |
8812 | } | |
fcfa0a32 | 8813 | |
679563f4 | 8814 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) { |
fcfa0a32 MC |
8815 | fn = tg3_msi; |
8816 | if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) | |
8817 | fn = tg3_msi_1shot; | |
1fb9df5d | 8818 | flags = IRQF_SAMPLE_RANDOM; |
fcfa0a32 MC |
8819 | } else { |
8820 | fn = tg3_interrupt; | |
8821 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) | |
8822 | fn = tg3_interrupt_tagged; | |
1fb9df5d | 8823 | flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM; |
fcfa0a32 | 8824 | } |
4f125f42 MC |
8825 | |
8826 | return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); | |
fcfa0a32 MC |
8827 | } |
8828 | ||
7938109f MC |
8829 | static int tg3_test_interrupt(struct tg3 *tp) |
8830 | { | |
09943a18 | 8831 | struct tg3_napi *tnapi = &tp->napi[0]; |
7938109f | 8832 | struct net_device *dev = tp->dev; |
b16250e3 | 8833 | int err, i, intr_ok = 0; |
f6eb9b1f | 8834 | u32 val; |
7938109f | 8835 | |
d4bc3927 MC |
8836 | if (!netif_running(dev)) |
8837 | return -ENODEV; | |
8838 | ||
7938109f MC |
8839 | tg3_disable_ints(tp); |
8840 | ||
4f125f42 | 8841 | free_irq(tnapi->irq_vec, tnapi); |
7938109f | 8842 | |
f6eb9b1f MC |
8843 | /* |
8844 | * Turn off MSI one shot mode. Otherwise this test has no | |
8845 | * observable way to know whether the interrupt was delivered. | |
8846 | */ | |
c885e824 | 8847 | if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) && |
f6eb9b1f MC |
8848 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) { |
8849 | val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; | |
8850 | tw32(MSGINT_MODE, val); | |
8851 | } | |
8852 | ||
4f125f42 | 8853 | err = request_irq(tnapi->irq_vec, tg3_test_isr, |
09943a18 | 8854 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi); |
7938109f MC |
8855 | if (err) |
8856 | return err; | |
8857 | ||
898a56f8 | 8858 | tnapi->hw_status->status &= ~SD_STATUS_UPDATED; |
7938109f MC |
8859 | tg3_enable_ints(tp); |
8860 | ||
8861 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
fd2ce37f | 8862 | tnapi->coal_now); |
7938109f MC |
8863 | |
8864 | for (i = 0; i < 5; i++) { | |
b16250e3 MC |
8865 | u32 int_mbox, misc_host_ctrl; |
8866 | ||
898a56f8 | 8867 | int_mbox = tr32_mailbox(tnapi->int_mbox); |
b16250e3 MC |
8868 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
8869 | ||
8870 | if ((int_mbox != 0) || | |
8871 | (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) { | |
8872 | intr_ok = 1; | |
7938109f | 8873 | break; |
b16250e3 MC |
8874 | } |
8875 | ||
7938109f MC |
8876 | msleep(10); |
8877 | } | |
8878 | ||
8879 | tg3_disable_ints(tp); | |
8880 | ||
4f125f42 | 8881 | free_irq(tnapi->irq_vec, tnapi); |
6aa20a22 | 8882 | |
4f125f42 | 8883 | err = tg3_request_irq(tp, 0); |
7938109f MC |
8884 | |
8885 | if (err) | |
8886 | return err; | |
8887 | ||
f6eb9b1f MC |
8888 | if (intr_ok) { |
8889 | /* Reenable MSI one shot mode. */ | |
c885e824 | 8890 | if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) && |
f6eb9b1f MC |
8891 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) { |
8892 | val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; | |
8893 | tw32(MSGINT_MODE, val); | |
8894 | } | |
7938109f | 8895 | return 0; |
f6eb9b1f | 8896 | } |
7938109f MC |
8897 | |
8898 | return -EIO; | |
8899 | } | |
8900 | ||
8901 | /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is | |
8902 | * successfully restored | |
8903 | */ | |
8904 | static int tg3_test_msi(struct tg3 *tp) | |
8905 | { | |
7938109f MC |
8906 | int err; |
8907 | u16 pci_cmd; | |
8908 | ||
8909 | if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI)) | |
8910 | return 0; | |
8911 | ||
8912 | /* Turn off SERR reporting in case MSI terminates with Master | |
8913 | * Abort. | |
8914 | */ | |
8915 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
8916 | pci_write_config_word(tp->pdev, PCI_COMMAND, | |
8917 | pci_cmd & ~PCI_COMMAND_SERR); | |
8918 | ||
8919 | err = tg3_test_interrupt(tp); | |
8920 | ||
8921 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
8922 | ||
8923 | if (!err) | |
8924 | return 0; | |
8925 | ||
8926 | /* other failures */ | |
8927 | if (err != -EIO) | |
8928 | return err; | |
8929 | ||
8930 | /* MSI test failed, go back to INTx mode */ | |
5129c3a3 MC |
8931 | netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " |
8932 | "to INTx mode. Please report this failure to the PCI " | |
8933 | "maintainer and include system chipset information\n"); | |
7938109f | 8934 | |
4f125f42 | 8935 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
09943a18 | 8936 | |
7938109f MC |
8937 | pci_disable_msi(tp->pdev); |
8938 | ||
8939 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI; | |
dc8bf1b1 | 8940 | tp->napi[0].irq_vec = tp->pdev->irq; |
7938109f | 8941 | |
4f125f42 | 8942 | err = tg3_request_irq(tp, 0); |
7938109f MC |
8943 | if (err) |
8944 | return err; | |
8945 | ||
8946 | /* Need to reset the chip because the MSI cycle may have terminated | |
8947 | * with Master Abort. | |
8948 | */ | |
f47c11ee | 8949 | tg3_full_lock(tp, 1); |
7938109f | 8950 | |
944d980e | 8951 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
8e7a22e3 | 8952 | err = tg3_init_hw(tp, 1); |
7938109f | 8953 | |
f47c11ee | 8954 | tg3_full_unlock(tp); |
7938109f MC |
8955 | |
8956 | if (err) | |
4f125f42 | 8957 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
7938109f MC |
8958 | |
8959 | return err; | |
8960 | } | |
8961 | ||
9e9fd12d MC |
8962 | static int tg3_request_firmware(struct tg3 *tp) |
8963 | { | |
8964 | const __be32 *fw_data; | |
8965 | ||
8966 | if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { | |
05dbe005 JP |
8967 | netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", |
8968 | tp->fw_needed); | |
9e9fd12d MC |
8969 | return -ENOENT; |
8970 | } | |
8971 | ||
8972 | fw_data = (void *)tp->fw->data; | |
8973 | ||
8974 | /* Firmware blob starts with version numbers, followed by | |
8975 | * start address and _full_ length including BSS sections | |
8976 | * (which must be longer than the actual data, of course | |
8977 | */ | |
8978 | ||
8979 | tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */ | |
8980 | if (tp->fw_len < (tp->fw->size - 12)) { | |
05dbe005 JP |
8981 | netdev_err(tp->dev, "bogus length %d in \"%s\"\n", |
8982 | tp->fw_len, tp->fw_needed); | |
9e9fd12d MC |
8983 | release_firmware(tp->fw); |
8984 | tp->fw = NULL; | |
8985 | return -EINVAL; | |
8986 | } | |
8987 | ||
8988 | /* We no longer need firmware; we have it. */ | |
8989 | tp->fw_needed = NULL; | |
8990 | return 0; | |
8991 | } | |
8992 | ||
679563f4 MC |
8993 | static bool tg3_enable_msix(struct tg3 *tp) |
8994 | { | |
8995 | int i, rc, cpus = num_online_cpus(); | |
8996 | struct msix_entry msix_ent[tp->irq_max]; | |
8997 | ||
8998 | if (cpus == 1) | |
8999 | /* Just fallback to the simpler MSI mode. */ | |
9000 | return false; | |
9001 | ||
9002 | /* | |
9003 | * We want as many rx rings enabled as there are cpus. | |
9004 | * The first MSIX vector only deals with link interrupts, etc, | |
9005 | * so we add one to the number of vectors we are requesting. | |
9006 | */ | |
9007 | tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max); | |
9008 | ||
9009 | for (i = 0; i < tp->irq_max; i++) { | |
9010 | msix_ent[i].entry = i; | |
9011 | msix_ent[i].vector = 0; | |
9012 | } | |
9013 | ||
9014 | rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt); | |
2430b031 MC |
9015 | if (rc < 0) { |
9016 | return false; | |
9017 | } else if (rc != 0) { | |
679563f4 MC |
9018 | if (pci_enable_msix(tp->pdev, msix_ent, rc)) |
9019 | return false; | |
05dbe005 JP |
9020 | netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", |
9021 | tp->irq_cnt, rc); | |
679563f4 MC |
9022 | tp->irq_cnt = rc; |
9023 | } | |
9024 | ||
9025 | for (i = 0; i < tp->irq_max; i++) | |
9026 | tp->napi[i].irq_vec = msix_ent[i].vector; | |
9027 | ||
2ddaad39 BH |
9028 | netif_set_real_num_tx_queues(tp->dev, 1); |
9029 | rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1; | |
9030 | if (netif_set_real_num_rx_queues(tp->dev, rc)) { | |
9031 | pci_disable_msix(tp->pdev); | |
9032 | return false; | |
9033 | } | |
b92b9040 MC |
9034 | |
9035 | if (tp->irq_cnt > 1) { | |
2430b031 | 9036 | tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS; |
b92b9040 MC |
9037 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) { |
9038 | tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS; | |
9039 | netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1); | |
9040 | } | |
9041 | } | |
2430b031 | 9042 | |
679563f4 MC |
9043 | return true; |
9044 | } | |
9045 | ||
07b0173c MC |
9046 | static void tg3_ints_init(struct tg3 *tp) |
9047 | { | |
679563f4 MC |
9048 | if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) && |
9049 | !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { | |
07b0173c MC |
9050 | /* All MSI supporting chips should support tagged |
9051 | * status. Assert that this is the case. | |
9052 | */ | |
5129c3a3 MC |
9053 | netdev_warn(tp->dev, |
9054 | "MSI without TAGGED_STATUS? Not using MSI\n"); | |
679563f4 | 9055 | goto defcfg; |
07b0173c | 9056 | } |
4f125f42 | 9057 | |
679563f4 MC |
9058 | if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp)) |
9059 | tp->tg3_flags2 |= TG3_FLG2_USING_MSIX; | |
9060 | else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) && | |
9061 | pci_enable_msi(tp->pdev) == 0) | |
9062 | tp->tg3_flags2 |= TG3_FLG2_USING_MSI; | |
9063 | ||
9064 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) { | |
9065 | u32 msi_mode = tr32(MSGINT_MODE); | |
0583d521 MC |
9066 | if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) && |
9067 | tp->irq_cnt > 1) | |
baf8a94a | 9068 | msi_mode |= MSGINT_MODE_MULTIVEC_EN; |
679563f4 MC |
9069 | tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE); |
9070 | } | |
9071 | defcfg: | |
9072 | if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) { | |
9073 | tp->irq_cnt = 1; | |
9074 | tp->napi[0].irq_vec = tp->pdev->irq; | |
2ddaad39 | 9075 | netif_set_real_num_tx_queues(tp->dev, 1); |
85407885 | 9076 | netif_set_real_num_rx_queues(tp->dev, 1); |
679563f4 | 9077 | } |
07b0173c MC |
9078 | } |
9079 | ||
9080 | static void tg3_ints_fini(struct tg3 *tp) | |
9081 | { | |
679563f4 MC |
9082 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) |
9083 | pci_disable_msix(tp->pdev); | |
9084 | else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) | |
9085 | pci_disable_msi(tp->pdev); | |
9086 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX; | |
774ee752 | 9087 | tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS); |
07b0173c MC |
9088 | } |
9089 | ||
1da177e4 LT |
9090 | static int tg3_open(struct net_device *dev) |
9091 | { | |
9092 | struct tg3 *tp = netdev_priv(dev); | |
4f125f42 | 9093 | int i, err; |
1da177e4 | 9094 | |
9e9fd12d MC |
9095 | if (tp->fw_needed) { |
9096 | err = tg3_request_firmware(tp); | |
9097 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
9098 | if (err) | |
9099 | return err; | |
9100 | } else if (err) { | |
05dbe005 | 9101 | netdev_warn(tp->dev, "TSO capability disabled\n"); |
9e9fd12d MC |
9102 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; |
9103 | } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
05dbe005 | 9104 | netdev_notice(tp->dev, "TSO capability restored\n"); |
9e9fd12d MC |
9105 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; |
9106 | } | |
9107 | } | |
9108 | ||
c49a1561 MC |
9109 | netif_carrier_off(tp->dev); |
9110 | ||
c866b7ea | 9111 | err = tg3_power_up(tp); |
2f751b67 | 9112 | if (err) |
bc1c7567 | 9113 | return err; |
2f751b67 MC |
9114 | |
9115 | tg3_full_lock(tp, 0); | |
bc1c7567 | 9116 | |
1da177e4 LT |
9117 | tg3_disable_ints(tp); |
9118 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; | |
9119 | ||
f47c11ee | 9120 | tg3_full_unlock(tp); |
1da177e4 | 9121 | |
679563f4 MC |
9122 | /* |
9123 | * Setup interrupts first so we know how | |
9124 | * many NAPI resources to allocate | |
9125 | */ | |
9126 | tg3_ints_init(tp); | |
9127 | ||
1da177e4 LT |
9128 | /* The placement of this call is tied |
9129 | * to the setup and use of Host TX descriptors. | |
9130 | */ | |
9131 | err = tg3_alloc_consistent(tp); | |
9132 | if (err) | |
679563f4 | 9133 | goto err_out1; |
88b06bc2 | 9134 | |
66cfd1bd MC |
9135 | tg3_napi_init(tp); |
9136 | ||
fed97810 | 9137 | tg3_napi_enable(tp); |
1da177e4 | 9138 | |
4f125f42 MC |
9139 | for (i = 0; i < tp->irq_cnt; i++) { |
9140 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9141 | err = tg3_request_irq(tp, i); | |
9142 | if (err) { | |
9143 | for (i--; i >= 0; i--) | |
9144 | free_irq(tnapi->irq_vec, tnapi); | |
9145 | break; | |
9146 | } | |
9147 | } | |
1da177e4 | 9148 | |
07b0173c | 9149 | if (err) |
679563f4 | 9150 | goto err_out2; |
bea3348e | 9151 | |
f47c11ee | 9152 | tg3_full_lock(tp, 0); |
1da177e4 | 9153 | |
8e7a22e3 | 9154 | err = tg3_init_hw(tp, 1); |
1da177e4 | 9155 | if (err) { |
944d980e | 9156 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
9157 | tg3_free_rings(tp); |
9158 | } else { | |
fac9b83e DM |
9159 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) |
9160 | tp->timer_offset = HZ; | |
9161 | else | |
9162 | tp->timer_offset = HZ / 10; | |
9163 | ||
9164 | BUG_ON(tp->timer_offset > HZ); | |
9165 | tp->timer_counter = tp->timer_multiplier = | |
9166 | (HZ / tp->timer_offset); | |
9167 | tp->asf_counter = tp->asf_multiplier = | |
28fbef78 | 9168 | ((HZ / tp->timer_offset) * 2); |
1da177e4 LT |
9169 | |
9170 | init_timer(&tp->timer); | |
9171 | tp->timer.expires = jiffies + tp->timer_offset; | |
9172 | tp->timer.data = (unsigned long) tp; | |
9173 | tp->timer.function = tg3_timer; | |
1da177e4 LT |
9174 | } |
9175 | ||
f47c11ee | 9176 | tg3_full_unlock(tp); |
1da177e4 | 9177 | |
07b0173c | 9178 | if (err) |
679563f4 | 9179 | goto err_out3; |
1da177e4 | 9180 | |
7938109f MC |
9181 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { |
9182 | err = tg3_test_msi(tp); | |
fac9b83e | 9183 | |
7938109f | 9184 | if (err) { |
f47c11ee | 9185 | tg3_full_lock(tp, 0); |
944d980e | 9186 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
7938109f | 9187 | tg3_free_rings(tp); |
f47c11ee | 9188 | tg3_full_unlock(tp); |
7938109f | 9189 | |
679563f4 | 9190 | goto err_out2; |
7938109f | 9191 | } |
fcfa0a32 | 9192 | |
c885e824 MC |
9193 | if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) && |
9194 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) { | |
f6eb9b1f | 9195 | u32 val = tr32(PCIE_TRANSACTION_CFG); |
fcfa0a32 | 9196 | |
f6eb9b1f MC |
9197 | tw32(PCIE_TRANSACTION_CFG, |
9198 | val | PCIE_TRANS_CFG_1SHOT_MSI); | |
fcfa0a32 | 9199 | } |
7938109f MC |
9200 | } |
9201 | ||
b02fd9e3 MC |
9202 | tg3_phy_start(tp); |
9203 | ||
f47c11ee | 9204 | tg3_full_lock(tp, 0); |
1da177e4 | 9205 | |
7938109f MC |
9206 | add_timer(&tp->timer); |
9207 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; | |
1da177e4 LT |
9208 | tg3_enable_ints(tp); |
9209 | ||
f47c11ee | 9210 | tg3_full_unlock(tp); |
1da177e4 | 9211 | |
fe5f5787 | 9212 | netif_tx_start_all_queues(dev); |
1da177e4 LT |
9213 | |
9214 | return 0; | |
07b0173c | 9215 | |
679563f4 | 9216 | err_out3: |
4f125f42 MC |
9217 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
9218 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9219 | free_irq(tnapi->irq_vec, tnapi); | |
9220 | } | |
07b0173c | 9221 | |
679563f4 | 9222 | err_out2: |
fed97810 | 9223 | tg3_napi_disable(tp); |
66cfd1bd | 9224 | tg3_napi_fini(tp); |
07b0173c | 9225 | tg3_free_consistent(tp); |
679563f4 MC |
9226 | |
9227 | err_out1: | |
9228 | tg3_ints_fini(tp); | |
07b0173c | 9229 | return err; |
1da177e4 LT |
9230 | } |
9231 | ||
511d2224 ED |
9232 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *, |
9233 | struct rtnl_link_stats64 *); | |
1da177e4 LT |
9234 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *); |
9235 | ||
9236 | static int tg3_close(struct net_device *dev) | |
9237 | { | |
4f125f42 | 9238 | int i; |
1da177e4 LT |
9239 | struct tg3 *tp = netdev_priv(dev); |
9240 | ||
fed97810 | 9241 | tg3_napi_disable(tp); |
28e53bdd | 9242 | cancel_work_sync(&tp->reset_task); |
7faa006f | 9243 | |
fe5f5787 | 9244 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
9245 | |
9246 | del_timer_sync(&tp->timer); | |
9247 | ||
24bb4fb6 MC |
9248 | tg3_phy_stop(tp); |
9249 | ||
f47c11ee | 9250 | tg3_full_lock(tp, 1); |
1da177e4 LT |
9251 | |
9252 | tg3_disable_ints(tp); | |
9253 | ||
944d980e | 9254 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 | 9255 | tg3_free_rings(tp); |
5cf64b8a | 9256 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; |
1da177e4 | 9257 | |
f47c11ee | 9258 | tg3_full_unlock(tp); |
1da177e4 | 9259 | |
4f125f42 MC |
9260 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
9261 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9262 | free_irq(tnapi->irq_vec, tnapi); | |
9263 | } | |
07b0173c MC |
9264 | |
9265 | tg3_ints_fini(tp); | |
1da177e4 | 9266 | |
511d2224 ED |
9267 | tg3_get_stats64(tp->dev, &tp->net_stats_prev); |
9268 | ||
1da177e4 LT |
9269 | memcpy(&tp->estats_prev, tg3_get_estats(tp), |
9270 | sizeof(tp->estats_prev)); | |
9271 | ||
66cfd1bd MC |
9272 | tg3_napi_fini(tp); |
9273 | ||
1da177e4 LT |
9274 | tg3_free_consistent(tp); |
9275 | ||
c866b7ea | 9276 | tg3_power_down(tp); |
bc1c7567 MC |
9277 | |
9278 | netif_carrier_off(tp->dev); | |
9279 | ||
1da177e4 LT |
9280 | return 0; |
9281 | } | |
9282 | ||
511d2224 | 9283 | static inline u64 get_stat64(tg3_stat64_t *val) |
816f8b86 SB |
9284 | { |
9285 | return ((u64)val->high << 32) | ((u64)val->low); | |
9286 | } | |
9287 | ||
511d2224 | 9288 | static u64 calc_crc_errors(struct tg3 *tp) |
1da177e4 LT |
9289 | { |
9290 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9291 | ||
f07e9af3 | 9292 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
1da177e4 LT |
9293 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
9294 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
1da177e4 LT |
9295 | u32 val; |
9296 | ||
f47c11ee | 9297 | spin_lock_bh(&tp->lock); |
569a5df8 MC |
9298 | if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { |
9299 | tg3_writephy(tp, MII_TG3_TEST1, | |
9300 | val | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 9301 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val); |
1da177e4 LT |
9302 | } else |
9303 | val = 0; | |
f47c11ee | 9304 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
9305 | |
9306 | tp->phy_crc_errors += val; | |
9307 | ||
9308 | return tp->phy_crc_errors; | |
9309 | } | |
9310 | ||
9311 | return get_stat64(&hw_stats->rx_fcs_errors); | |
9312 | } | |
9313 | ||
9314 | #define ESTAT_ADD(member) \ | |
9315 | estats->member = old_estats->member + \ | |
511d2224 | 9316 | get_stat64(&hw_stats->member) |
1da177e4 LT |
9317 | |
9318 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp) | |
9319 | { | |
9320 | struct tg3_ethtool_stats *estats = &tp->estats; | |
9321 | struct tg3_ethtool_stats *old_estats = &tp->estats_prev; | |
9322 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9323 | ||
9324 | if (!hw_stats) | |
9325 | return old_estats; | |
9326 | ||
9327 | ESTAT_ADD(rx_octets); | |
9328 | ESTAT_ADD(rx_fragments); | |
9329 | ESTAT_ADD(rx_ucast_packets); | |
9330 | ESTAT_ADD(rx_mcast_packets); | |
9331 | ESTAT_ADD(rx_bcast_packets); | |
9332 | ESTAT_ADD(rx_fcs_errors); | |
9333 | ESTAT_ADD(rx_align_errors); | |
9334 | ESTAT_ADD(rx_xon_pause_rcvd); | |
9335 | ESTAT_ADD(rx_xoff_pause_rcvd); | |
9336 | ESTAT_ADD(rx_mac_ctrl_rcvd); | |
9337 | ESTAT_ADD(rx_xoff_entered); | |
9338 | ESTAT_ADD(rx_frame_too_long_errors); | |
9339 | ESTAT_ADD(rx_jabbers); | |
9340 | ESTAT_ADD(rx_undersize_packets); | |
9341 | ESTAT_ADD(rx_in_length_errors); | |
9342 | ESTAT_ADD(rx_out_length_errors); | |
9343 | ESTAT_ADD(rx_64_or_less_octet_packets); | |
9344 | ESTAT_ADD(rx_65_to_127_octet_packets); | |
9345 | ESTAT_ADD(rx_128_to_255_octet_packets); | |
9346 | ESTAT_ADD(rx_256_to_511_octet_packets); | |
9347 | ESTAT_ADD(rx_512_to_1023_octet_packets); | |
9348 | ESTAT_ADD(rx_1024_to_1522_octet_packets); | |
9349 | ESTAT_ADD(rx_1523_to_2047_octet_packets); | |
9350 | ESTAT_ADD(rx_2048_to_4095_octet_packets); | |
9351 | ESTAT_ADD(rx_4096_to_8191_octet_packets); | |
9352 | ESTAT_ADD(rx_8192_to_9022_octet_packets); | |
9353 | ||
9354 | ESTAT_ADD(tx_octets); | |
9355 | ESTAT_ADD(tx_collisions); | |
9356 | ESTAT_ADD(tx_xon_sent); | |
9357 | ESTAT_ADD(tx_xoff_sent); | |
9358 | ESTAT_ADD(tx_flow_control); | |
9359 | ESTAT_ADD(tx_mac_errors); | |
9360 | ESTAT_ADD(tx_single_collisions); | |
9361 | ESTAT_ADD(tx_mult_collisions); | |
9362 | ESTAT_ADD(tx_deferred); | |
9363 | ESTAT_ADD(tx_excessive_collisions); | |
9364 | ESTAT_ADD(tx_late_collisions); | |
9365 | ESTAT_ADD(tx_collide_2times); | |
9366 | ESTAT_ADD(tx_collide_3times); | |
9367 | ESTAT_ADD(tx_collide_4times); | |
9368 | ESTAT_ADD(tx_collide_5times); | |
9369 | ESTAT_ADD(tx_collide_6times); | |
9370 | ESTAT_ADD(tx_collide_7times); | |
9371 | ESTAT_ADD(tx_collide_8times); | |
9372 | ESTAT_ADD(tx_collide_9times); | |
9373 | ESTAT_ADD(tx_collide_10times); | |
9374 | ESTAT_ADD(tx_collide_11times); | |
9375 | ESTAT_ADD(tx_collide_12times); | |
9376 | ESTAT_ADD(tx_collide_13times); | |
9377 | ESTAT_ADD(tx_collide_14times); | |
9378 | ESTAT_ADD(tx_collide_15times); | |
9379 | ESTAT_ADD(tx_ucast_packets); | |
9380 | ESTAT_ADD(tx_mcast_packets); | |
9381 | ESTAT_ADD(tx_bcast_packets); | |
9382 | ESTAT_ADD(tx_carrier_sense_errors); | |
9383 | ESTAT_ADD(tx_discards); | |
9384 | ESTAT_ADD(tx_errors); | |
9385 | ||
9386 | ESTAT_ADD(dma_writeq_full); | |
9387 | ESTAT_ADD(dma_write_prioq_full); | |
9388 | ESTAT_ADD(rxbds_empty); | |
9389 | ESTAT_ADD(rx_discards); | |
9390 | ESTAT_ADD(rx_errors); | |
9391 | ESTAT_ADD(rx_threshold_hit); | |
9392 | ||
9393 | ESTAT_ADD(dma_readq_full); | |
9394 | ESTAT_ADD(dma_read_prioq_full); | |
9395 | ESTAT_ADD(tx_comp_queue_full); | |
9396 | ||
9397 | ESTAT_ADD(ring_set_send_prod_index); | |
9398 | ESTAT_ADD(ring_status_update); | |
9399 | ESTAT_ADD(nic_irqs); | |
9400 | ESTAT_ADD(nic_avoided_irqs); | |
9401 | ESTAT_ADD(nic_tx_threshold_hit); | |
9402 | ||
9403 | return estats; | |
9404 | } | |
9405 | ||
511d2224 ED |
9406 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev, |
9407 | struct rtnl_link_stats64 *stats) | |
1da177e4 LT |
9408 | { |
9409 | struct tg3 *tp = netdev_priv(dev); | |
511d2224 | 9410 | struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; |
1da177e4 LT |
9411 | struct tg3_hw_stats *hw_stats = tp->hw_stats; |
9412 | ||
9413 | if (!hw_stats) | |
9414 | return old_stats; | |
9415 | ||
9416 | stats->rx_packets = old_stats->rx_packets + | |
9417 | get_stat64(&hw_stats->rx_ucast_packets) + | |
9418 | get_stat64(&hw_stats->rx_mcast_packets) + | |
9419 | get_stat64(&hw_stats->rx_bcast_packets); | |
6aa20a22 | 9420 | |
1da177e4 LT |
9421 | stats->tx_packets = old_stats->tx_packets + |
9422 | get_stat64(&hw_stats->tx_ucast_packets) + | |
9423 | get_stat64(&hw_stats->tx_mcast_packets) + | |
9424 | get_stat64(&hw_stats->tx_bcast_packets); | |
9425 | ||
9426 | stats->rx_bytes = old_stats->rx_bytes + | |
9427 | get_stat64(&hw_stats->rx_octets); | |
9428 | stats->tx_bytes = old_stats->tx_bytes + | |
9429 | get_stat64(&hw_stats->tx_octets); | |
9430 | ||
9431 | stats->rx_errors = old_stats->rx_errors + | |
4f63b877 | 9432 | get_stat64(&hw_stats->rx_errors); |
1da177e4 LT |
9433 | stats->tx_errors = old_stats->tx_errors + |
9434 | get_stat64(&hw_stats->tx_errors) + | |
9435 | get_stat64(&hw_stats->tx_mac_errors) + | |
9436 | get_stat64(&hw_stats->tx_carrier_sense_errors) + | |
9437 | get_stat64(&hw_stats->tx_discards); | |
9438 | ||
9439 | stats->multicast = old_stats->multicast + | |
9440 | get_stat64(&hw_stats->rx_mcast_packets); | |
9441 | stats->collisions = old_stats->collisions + | |
9442 | get_stat64(&hw_stats->tx_collisions); | |
9443 | ||
9444 | stats->rx_length_errors = old_stats->rx_length_errors + | |
9445 | get_stat64(&hw_stats->rx_frame_too_long_errors) + | |
9446 | get_stat64(&hw_stats->rx_undersize_packets); | |
9447 | ||
9448 | stats->rx_over_errors = old_stats->rx_over_errors + | |
9449 | get_stat64(&hw_stats->rxbds_empty); | |
9450 | stats->rx_frame_errors = old_stats->rx_frame_errors + | |
9451 | get_stat64(&hw_stats->rx_align_errors); | |
9452 | stats->tx_aborted_errors = old_stats->tx_aborted_errors + | |
9453 | get_stat64(&hw_stats->tx_discards); | |
9454 | stats->tx_carrier_errors = old_stats->tx_carrier_errors + | |
9455 | get_stat64(&hw_stats->tx_carrier_sense_errors); | |
9456 | ||
9457 | stats->rx_crc_errors = old_stats->rx_crc_errors + | |
9458 | calc_crc_errors(tp); | |
9459 | ||
4f63b877 JL |
9460 | stats->rx_missed_errors = old_stats->rx_missed_errors + |
9461 | get_stat64(&hw_stats->rx_discards); | |
9462 | ||
b0057c51 ED |
9463 | stats->rx_dropped = tp->rx_dropped; |
9464 | ||
1da177e4 LT |
9465 | return stats; |
9466 | } | |
9467 | ||
9468 | static inline u32 calc_crc(unsigned char *buf, int len) | |
9469 | { | |
9470 | u32 reg; | |
9471 | u32 tmp; | |
9472 | int j, k; | |
9473 | ||
9474 | reg = 0xffffffff; | |
9475 | ||
9476 | for (j = 0; j < len; j++) { | |
9477 | reg ^= buf[j]; | |
9478 | ||
9479 | for (k = 0; k < 8; k++) { | |
9480 | tmp = reg & 0x01; | |
9481 | ||
9482 | reg >>= 1; | |
9483 | ||
859a5887 | 9484 | if (tmp) |
1da177e4 | 9485 | reg ^= 0xedb88320; |
1da177e4 LT |
9486 | } |
9487 | } | |
9488 | ||
9489 | return ~reg; | |
9490 | } | |
9491 | ||
9492 | static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) | |
9493 | { | |
9494 | /* accept or reject all multicast frames */ | |
9495 | tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0); | |
9496 | tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0); | |
9497 | tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0); | |
9498 | tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0); | |
9499 | } | |
9500 | ||
9501 | static void __tg3_set_rx_mode(struct net_device *dev) | |
9502 | { | |
9503 | struct tg3 *tp = netdev_priv(dev); | |
9504 | u32 rx_mode; | |
9505 | ||
9506 | rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | | |
9507 | RX_MODE_KEEP_VLAN_TAG); | |
9508 | ||
bf933c80 | 9509 | #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE) |
1da177e4 LT |
9510 | /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG |
9511 | * flag clear. | |
9512 | */ | |
1da177e4 LT |
9513 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) |
9514 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; | |
9515 | #endif | |
9516 | ||
9517 | if (dev->flags & IFF_PROMISC) { | |
9518 | /* Promiscuous mode. */ | |
9519 | rx_mode |= RX_MODE_PROMISC; | |
9520 | } else if (dev->flags & IFF_ALLMULTI) { | |
9521 | /* Accept all multicast. */ | |
de6f31eb | 9522 | tg3_set_multi(tp, 1); |
4cd24eaf | 9523 | } else if (netdev_mc_empty(dev)) { |
1da177e4 | 9524 | /* Reject all multicast. */ |
de6f31eb | 9525 | tg3_set_multi(tp, 0); |
1da177e4 LT |
9526 | } else { |
9527 | /* Accept one or more multicast(s). */ | |
22bedad3 | 9528 | struct netdev_hw_addr *ha; |
1da177e4 LT |
9529 | u32 mc_filter[4] = { 0, }; |
9530 | u32 regidx; | |
9531 | u32 bit; | |
9532 | u32 crc; | |
9533 | ||
22bedad3 JP |
9534 | netdev_for_each_mc_addr(ha, dev) { |
9535 | crc = calc_crc(ha->addr, ETH_ALEN); | |
1da177e4 LT |
9536 | bit = ~crc & 0x7f; |
9537 | regidx = (bit & 0x60) >> 5; | |
9538 | bit &= 0x1f; | |
9539 | mc_filter[regidx] |= (1 << bit); | |
9540 | } | |
9541 | ||
9542 | tw32(MAC_HASH_REG_0, mc_filter[0]); | |
9543 | tw32(MAC_HASH_REG_1, mc_filter[1]); | |
9544 | tw32(MAC_HASH_REG_2, mc_filter[2]); | |
9545 | tw32(MAC_HASH_REG_3, mc_filter[3]); | |
9546 | } | |
9547 | ||
9548 | if (rx_mode != tp->rx_mode) { | |
9549 | tp->rx_mode = rx_mode; | |
9550 | tw32_f(MAC_RX_MODE, rx_mode); | |
9551 | udelay(10); | |
9552 | } | |
9553 | } | |
9554 | ||
9555 | static void tg3_set_rx_mode(struct net_device *dev) | |
9556 | { | |
9557 | struct tg3 *tp = netdev_priv(dev); | |
9558 | ||
e75f7c90 MC |
9559 | if (!netif_running(dev)) |
9560 | return; | |
9561 | ||
f47c11ee | 9562 | tg3_full_lock(tp, 0); |
1da177e4 | 9563 | __tg3_set_rx_mode(dev); |
f47c11ee | 9564 | tg3_full_unlock(tp); |
1da177e4 LT |
9565 | } |
9566 | ||
9567 | #define TG3_REGDUMP_LEN (32 * 1024) | |
9568 | ||
9569 | static int tg3_get_regs_len(struct net_device *dev) | |
9570 | { | |
9571 | return TG3_REGDUMP_LEN; | |
9572 | } | |
9573 | ||
9574 | static void tg3_get_regs(struct net_device *dev, | |
9575 | struct ethtool_regs *regs, void *_p) | |
9576 | { | |
9577 | u32 *p = _p; | |
9578 | struct tg3 *tp = netdev_priv(dev); | |
9579 | u8 *orig_p = _p; | |
9580 | int i; | |
9581 | ||
9582 | regs->version = 0; | |
9583 | ||
9584 | memset(p, 0, TG3_REGDUMP_LEN); | |
9585 | ||
80096068 | 9586 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
9587 | return; |
9588 | ||
f47c11ee | 9589 | tg3_full_lock(tp, 0); |
1da177e4 LT |
9590 | |
9591 | #define __GET_REG32(reg) (*(p)++ = tr32(reg)) | |
be98da6a | 9592 | #define GET_REG32_LOOP(base, len) \ |
1da177e4 LT |
9593 | do { p = (u32 *)(orig_p + (base)); \ |
9594 | for (i = 0; i < len; i += 4) \ | |
9595 | __GET_REG32((base) + i); \ | |
9596 | } while (0) | |
9597 | #define GET_REG32_1(reg) \ | |
9598 | do { p = (u32 *)(orig_p + (reg)); \ | |
9599 | __GET_REG32((reg)); \ | |
9600 | } while (0) | |
9601 | ||
9602 | GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0); | |
9603 | GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200); | |
9604 | GET_REG32_LOOP(MAC_MODE, 0x4f0); | |
9605 | GET_REG32_LOOP(SNDDATAI_MODE, 0xe0); | |
9606 | GET_REG32_1(SNDDATAC_MODE); | |
9607 | GET_REG32_LOOP(SNDBDS_MODE, 0x80); | |
9608 | GET_REG32_LOOP(SNDBDI_MODE, 0x48); | |
9609 | GET_REG32_1(SNDBDC_MODE); | |
9610 | GET_REG32_LOOP(RCVLPC_MODE, 0x20); | |
9611 | GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c); | |
9612 | GET_REG32_LOOP(RCVDBDI_MODE, 0x0c); | |
9613 | GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c); | |
9614 | GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44); | |
9615 | GET_REG32_1(RCVDCC_MODE); | |
9616 | GET_REG32_LOOP(RCVBDI_MODE, 0x20); | |
9617 | GET_REG32_LOOP(RCVCC_MODE, 0x14); | |
9618 | GET_REG32_LOOP(RCVLSC_MODE, 0x08); | |
9619 | GET_REG32_1(MBFREE_MODE); | |
9620 | GET_REG32_LOOP(HOSTCC_MODE, 0x100); | |
9621 | GET_REG32_LOOP(MEMARB_MODE, 0x10); | |
9622 | GET_REG32_LOOP(BUFMGR_MODE, 0x58); | |
9623 | GET_REG32_LOOP(RDMAC_MODE, 0x08); | |
9624 | GET_REG32_LOOP(WDMAC_MODE, 0x08); | |
091465d7 CE |
9625 | GET_REG32_1(RX_CPU_MODE); |
9626 | GET_REG32_1(RX_CPU_STATE); | |
9627 | GET_REG32_1(RX_CPU_PGMCTR); | |
9628 | GET_REG32_1(RX_CPU_HWBKPT); | |
9629 | GET_REG32_1(TX_CPU_MODE); | |
9630 | GET_REG32_1(TX_CPU_STATE); | |
9631 | GET_REG32_1(TX_CPU_PGMCTR); | |
1da177e4 LT |
9632 | GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110); |
9633 | GET_REG32_LOOP(FTQ_RESET, 0x120); | |
9634 | GET_REG32_LOOP(MSGINT_MODE, 0x0c); | |
9635 | GET_REG32_1(DMAC_MODE); | |
9636 | GET_REG32_LOOP(GRC_MODE, 0x4c); | |
9637 | if (tp->tg3_flags & TG3_FLAG_NVRAM) | |
9638 | GET_REG32_LOOP(NVRAM_CMD, 0x24); | |
9639 | ||
9640 | #undef __GET_REG32 | |
9641 | #undef GET_REG32_LOOP | |
9642 | #undef GET_REG32_1 | |
9643 | ||
f47c11ee | 9644 | tg3_full_unlock(tp); |
1da177e4 LT |
9645 | } |
9646 | ||
9647 | static int tg3_get_eeprom_len(struct net_device *dev) | |
9648 | { | |
9649 | struct tg3 *tp = netdev_priv(dev); | |
9650 | ||
9651 | return tp->nvram_size; | |
9652 | } | |
9653 | ||
1da177e4 LT |
9654 | static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) |
9655 | { | |
9656 | struct tg3 *tp = netdev_priv(dev); | |
9657 | int ret; | |
9658 | u8 *pd; | |
b9fc7dc5 | 9659 | u32 i, offset, len, b_offset, b_count; |
a9dc529d | 9660 | __be32 val; |
1da177e4 | 9661 | |
df259d8c MC |
9662 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) |
9663 | return -EINVAL; | |
9664 | ||
80096068 | 9665 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
9666 | return -EAGAIN; |
9667 | ||
1da177e4 LT |
9668 | offset = eeprom->offset; |
9669 | len = eeprom->len; | |
9670 | eeprom->len = 0; | |
9671 | ||
9672 | eeprom->magic = TG3_EEPROM_MAGIC; | |
9673 | ||
9674 | if (offset & 3) { | |
9675 | /* adjustments to start on required 4 byte boundary */ | |
9676 | b_offset = offset & 3; | |
9677 | b_count = 4 - b_offset; | |
9678 | if (b_count > len) { | |
9679 | /* i.e. offset=1 len=2 */ | |
9680 | b_count = len; | |
9681 | } | |
a9dc529d | 9682 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); |
1da177e4 LT |
9683 | if (ret) |
9684 | return ret; | |
be98da6a | 9685 | memcpy(data, ((char *)&val) + b_offset, b_count); |
1da177e4 LT |
9686 | len -= b_count; |
9687 | offset += b_count; | |
c6cdf436 | 9688 | eeprom->len += b_count; |
1da177e4 LT |
9689 | } |
9690 | ||
9691 | /* read bytes upto the last 4 byte boundary */ | |
9692 | pd = &data[eeprom->len]; | |
9693 | for (i = 0; i < (len - (len & 3)); i += 4) { | |
a9dc529d | 9694 | ret = tg3_nvram_read_be32(tp, offset + i, &val); |
1da177e4 LT |
9695 | if (ret) { |
9696 | eeprom->len += i; | |
9697 | return ret; | |
9698 | } | |
1da177e4 LT |
9699 | memcpy(pd + i, &val, 4); |
9700 | } | |
9701 | eeprom->len += i; | |
9702 | ||
9703 | if (len & 3) { | |
9704 | /* read last bytes not ending on 4 byte boundary */ | |
9705 | pd = &data[eeprom->len]; | |
9706 | b_count = len & 3; | |
9707 | b_offset = offset + len - b_count; | |
a9dc529d | 9708 | ret = tg3_nvram_read_be32(tp, b_offset, &val); |
1da177e4 LT |
9709 | if (ret) |
9710 | return ret; | |
b9fc7dc5 | 9711 | memcpy(pd, &val, b_count); |
1da177e4 LT |
9712 | eeprom->len += b_count; |
9713 | } | |
9714 | return 0; | |
9715 | } | |
9716 | ||
6aa20a22 | 9717 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf); |
1da177e4 LT |
9718 | |
9719 | static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) | |
9720 | { | |
9721 | struct tg3 *tp = netdev_priv(dev); | |
9722 | int ret; | |
b9fc7dc5 | 9723 | u32 offset, len, b_offset, odd_len; |
1da177e4 | 9724 | u8 *buf; |
a9dc529d | 9725 | __be32 start, end; |
1da177e4 | 9726 | |
80096068 | 9727 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
9728 | return -EAGAIN; |
9729 | ||
df259d8c MC |
9730 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || |
9731 | eeprom->magic != TG3_EEPROM_MAGIC) | |
1da177e4 LT |
9732 | return -EINVAL; |
9733 | ||
9734 | offset = eeprom->offset; | |
9735 | len = eeprom->len; | |
9736 | ||
9737 | if ((b_offset = (offset & 3))) { | |
9738 | /* adjustments to start on required 4 byte boundary */ | |
a9dc529d | 9739 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); |
1da177e4 LT |
9740 | if (ret) |
9741 | return ret; | |
1da177e4 LT |
9742 | len += b_offset; |
9743 | offset &= ~3; | |
1c8594b4 MC |
9744 | if (len < 4) |
9745 | len = 4; | |
1da177e4 LT |
9746 | } |
9747 | ||
9748 | odd_len = 0; | |
1c8594b4 | 9749 | if (len & 3) { |
1da177e4 LT |
9750 | /* adjustments to end on required 4 byte boundary */ |
9751 | odd_len = 1; | |
9752 | len = (len + 3) & ~3; | |
a9dc529d | 9753 | ret = tg3_nvram_read_be32(tp, offset+len-4, &end); |
1da177e4 LT |
9754 | if (ret) |
9755 | return ret; | |
1da177e4 LT |
9756 | } |
9757 | ||
9758 | buf = data; | |
9759 | if (b_offset || odd_len) { | |
9760 | buf = kmalloc(len, GFP_KERNEL); | |
ab0049b4 | 9761 | if (!buf) |
1da177e4 LT |
9762 | return -ENOMEM; |
9763 | if (b_offset) | |
9764 | memcpy(buf, &start, 4); | |
9765 | if (odd_len) | |
9766 | memcpy(buf+len-4, &end, 4); | |
9767 | memcpy(buf + b_offset, data, eeprom->len); | |
9768 | } | |
9769 | ||
9770 | ret = tg3_nvram_write_block(tp, offset, len, buf); | |
9771 | ||
9772 | if (buf != data) | |
9773 | kfree(buf); | |
9774 | ||
9775 | return ret; | |
9776 | } | |
9777 | ||
9778 | static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
9779 | { | |
b02fd9e3 MC |
9780 | struct tg3 *tp = netdev_priv(dev); |
9781 | ||
9782 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { | |
3f0e3ad7 | 9783 | struct phy_device *phydev; |
f07e9af3 | 9784 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 9785 | return -EAGAIN; |
3f0e3ad7 MC |
9786 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
9787 | return phy_ethtool_gset(phydev, cmd); | |
b02fd9e3 | 9788 | } |
6aa20a22 | 9789 | |
1da177e4 LT |
9790 | cmd->supported = (SUPPORTED_Autoneg); |
9791 | ||
f07e9af3 | 9792 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
1da177e4 LT |
9793 | cmd->supported |= (SUPPORTED_1000baseT_Half | |
9794 | SUPPORTED_1000baseT_Full); | |
9795 | ||
f07e9af3 | 9796 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
1da177e4 LT |
9797 | cmd->supported |= (SUPPORTED_100baseT_Half | |
9798 | SUPPORTED_100baseT_Full | | |
9799 | SUPPORTED_10baseT_Half | | |
9800 | SUPPORTED_10baseT_Full | | |
3bebab59 | 9801 | SUPPORTED_TP); |
ef348144 KK |
9802 | cmd->port = PORT_TP; |
9803 | } else { | |
1da177e4 | 9804 | cmd->supported |= SUPPORTED_FIBRE; |
ef348144 KK |
9805 | cmd->port = PORT_FIBRE; |
9806 | } | |
6aa20a22 | 9807 | |
1da177e4 LT |
9808 | cmd->advertising = tp->link_config.advertising; |
9809 | if (netif_running(dev)) { | |
9810 | cmd->speed = tp->link_config.active_speed; | |
9811 | cmd->duplex = tp->link_config.active_duplex; | |
64c22182 MC |
9812 | } else { |
9813 | cmd->speed = SPEED_INVALID; | |
9814 | cmd->duplex = DUPLEX_INVALID; | |
1da177e4 | 9815 | } |
882e9793 | 9816 | cmd->phy_address = tp->phy_addr; |
7e5856bd | 9817 | cmd->transceiver = XCVR_INTERNAL; |
1da177e4 LT |
9818 | cmd->autoneg = tp->link_config.autoneg; |
9819 | cmd->maxtxpkt = 0; | |
9820 | cmd->maxrxpkt = 0; | |
9821 | return 0; | |
9822 | } | |
6aa20a22 | 9823 | |
1da177e4 LT |
9824 | static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
9825 | { | |
9826 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 9827 | |
b02fd9e3 | 9828 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
3f0e3ad7 | 9829 | struct phy_device *phydev; |
f07e9af3 | 9830 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 9831 | return -EAGAIN; |
3f0e3ad7 MC |
9832 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
9833 | return phy_ethtool_sset(phydev, cmd); | |
b02fd9e3 MC |
9834 | } |
9835 | ||
7e5856bd MC |
9836 | if (cmd->autoneg != AUTONEG_ENABLE && |
9837 | cmd->autoneg != AUTONEG_DISABLE) | |
37ff238d | 9838 | return -EINVAL; |
7e5856bd MC |
9839 | |
9840 | if (cmd->autoneg == AUTONEG_DISABLE && | |
9841 | cmd->duplex != DUPLEX_FULL && | |
9842 | cmd->duplex != DUPLEX_HALF) | |
37ff238d | 9843 | return -EINVAL; |
1da177e4 | 9844 | |
7e5856bd MC |
9845 | if (cmd->autoneg == AUTONEG_ENABLE) { |
9846 | u32 mask = ADVERTISED_Autoneg | | |
9847 | ADVERTISED_Pause | | |
9848 | ADVERTISED_Asym_Pause; | |
9849 | ||
f07e9af3 | 9850 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
7e5856bd MC |
9851 | mask |= ADVERTISED_1000baseT_Half | |
9852 | ADVERTISED_1000baseT_Full; | |
9853 | ||
f07e9af3 | 9854 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
7e5856bd MC |
9855 | mask |= ADVERTISED_100baseT_Half | |
9856 | ADVERTISED_100baseT_Full | | |
9857 | ADVERTISED_10baseT_Half | | |
9858 | ADVERTISED_10baseT_Full | | |
9859 | ADVERTISED_TP; | |
9860 | else | |
9861 | mask |= ADVERTISED_FIBRE; | |
9862 | ||
9863 | if (cmd->advertising & ~mask) | |
9864 | return -EINVAL; | |
9865 | ||
9866 | mask &= (ADVERTISED_1000baseT_Half | | |
9867 | ADVERTISED_1000baseT_Full | | |
9868 | ADVERTISED_100baseT_Half | | |
9869 | ADVERTISED_100baseT_Full | | |
9870 | ADVERTISED_10baseT_Half | | |
9871 | ADVERTISED_10baseT_Full); | |
9872 | ||
9873 | cmd->advertising &= mask; | |
9874 | } else { | |
f07e9af3 | 9875 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { |
7e5856bd MC |
9876 | if (cmd->speed != SPEED_1000) |
9877 | return -EINVAL; | |
9878 | ||
9879 | if (cmd->duplex != DUPLEX_FULL) | |
9880 | return -EINVAL; | |
9881 | } else { | |
9882 | if (cmd->speed != SPEED_100 && | |
9883 | cmd->speed != SPEED_10) | |
9884 | return -EINVAL; | |
9885 | } | |
9886 | } | |
9887 | ||
f47c11ee | 9888 | tg3_full_lock(tp, 0); |
1da177e4 LT |
9889 | |
9890 | tp->link_config.autoneg = cmd->autoneg; | |
9891 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
405d8e5c AG |
9892 | tp->link_config.advertising = (cmd->advertising | |
9893 | ADVERTISED_Autoneg); | |
1da177e4 LT |
9894 | tp->link_config.speed = SPEED_INVALID; |
9895 | tp->link_config.duplex = DUPLEX_INVALID; | |
9896 | } else { | |
9897 | tp->link_config.advertising = 0; | |
9898 | tp->link_config.speed = cmd->speed; | |
9899 | tp->link_config.duplex = cmd->duplex; | |
b02fd9e3 | 9900 | } |
6aa20a22 | 9901 | |
24fcad6b MC |
9902 | tp->link_config.orig_speed = tp->link_config.speed; |
9903 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
9904 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
9905 | ||
1da177e4 LT |
9906 | if (netif_running(dev)) |
9907 | tg3_setup_phy(tp, 1); | |
9908 | ||
f47c11ee | 9909 | tg3_full_unlock(tp); |
6aa20a22 | 9910 | |
1da177e4 LT |
9911 | return 0; |
9912 | } | |
6aa20a22 | 9913 | |
1da177e4 LT |
9914 | static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
9915 | { | |
9916 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 9917 | |
1da177e4 LT |
9918 | strcpy(info->driver, DRV_MODULE_NAME); |
9919 | strcpy(info->version, DRV_MODULE_VERSION); | |
c4e6575c | 9920 | strcpy(info->fw_version, tp->fw_ver); |
1da177e4 LT |
9921 | strcpy(info->bus_info, pci_name(tp->pdev)); |
9922 | } | |
6aa20a22 | 9923 | |
1da177e4 LT |
9924 | static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
9925 | { | |
9926 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 9927 | |
12dac075 RW |
9928 | if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) && |
9929 | device_can_wakeup(&tp->pdev->dev)) | |
a85feb8c GZ |
9930 | wol->supported = WAKE_MAGIC; |
9931 | else | |
9932 | wol->supported = 0; | |
1da177e4 | 9933 | wol->wolopts = 0; |
05ac4cb7 MC |
9934 | if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) && |
9935 | device_can_wakeup(&tp->pdev->dev)) | |
1da177e4 LT |
9936 | wol->wolopts = WAKE_MAGIC; |
9937 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
9938 | } | |
6aa20a22 | 9939 | |
1da177e4 LT |
9940 | static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
9941 | { | |
9942 | struct tg3 *tp = netdev_priv(dev); | |
12dac075 | 9943 | struct device *dp = &tp->pdev->dev; |
6aa20a22 | 9944 | |
1da177e4 LT |
9945 | if (wol->wolopts & ~WAKE_MAGIC) |
9946 | return -EINVAL; | |
9947 | if ((wol->wolopts & WAKE_MAGIC) && | |
12dac075 | 9948 | !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp))) |
1da177e4 | 9949 | return -EINVAL; |
6aa20a22 | 9950 | |
f2dc0d18 RW |
9951 | device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC); |
9952 | ||
f47c11ee | 9953 | spin_lock_bh(&tp->lock); |
f2dc0d18 | 9954 | if (device_may_wakeup(dp)) |
1da177e4 | 9955 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; |
f2dc0d18 | 9956 | else |
1da177e4 | 9957 | tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE; |
f47c11ee | 9958 | spin_unlock_bh(&tp->lock); |
6aa20a22 | 9959 | |
f2dc0d18 | 9960 | |
1da177e4 LT |
9961 | return 0; |
9962 | } | |
6aa20a22 | 9963 | |
1da177e4 LT |
9964 | static u32 tg3_get_msglevel(struct net_device *dev) |
9965 | { | |
9966 | struct tg3 *tp = netdev_priv(dev); | |
9967 | return tp->msg_enable; | |
9968 | } | |
6aa20a22 | 9969 | |
1da177e4 LT |
9970 | static void tg3_set_msglevel(struct net_device *dev, u32 value) |
9971 | { | |
9972 | struct tg3 *tp = netdev_priv(dev); | |
9973 | tp->msg_enable = value; | |
9974 | } | |
6aa20a22 | 9975 | |
1da177e4 LT |
9976 | static int tg3_set_tso(struct net_device *dev, u32 value) |
9977 | { | |
9978 | struct tg3 *tp = netdev_priv(dev); | |
9979 | ||
9980 | if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
9981 | if (value) | |
9982 | return -EINVAL; | |
9983 | return 0; | |
9984 | } | |
027455ad | 9985 | if ((dev->features & NETIF_F_IPV6_CSUM) && |
e849cdc3 MC |
9986 | ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) || |
9987 | (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) { | |
9936bcf6 | 9988 | if (value) { |
b0026624 | 9989 | dev->features |= NETIF_F_TSO6; |
e849cdc3 MC |
9990 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) || |
9991 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
57e6983c MC |
9992 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
9993 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
321d32a0 | 9994 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
e849cdc3 | 9995 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
9936bcf6 MC |
9996 | dev->features |= NETIF_F_TSO_ECN; |
9997 | } else | |
9998 | dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN); | |
b0026624 | 9999 | } |
1da177e4 LT |
10000 | return ethtool_op_set_tso(dev, value); |
10001 | } | |
6aa20a22 | 10002 | |
1da177e4 LT |
10003 | static int tg3_nway_reset(struct net_device *dev) |
10004 | { | |
10005 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 | 10006 | int r; |
6aa20a22 | 10007 | |
1da177e4 LT |
10008 | if (!netif_running(dev)) |
10009 | return -EAGAIN; | |
10010 | ||
f07e9af3 | 10011 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
c94e3941 MC |
10012 | return -EINVAL; |
10013 | ||
b02fd9e3 | 10014 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
f07e9af3 | 10015 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10016 | return -EAGAIN; |
3f0e3ad7 | 10017 | r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
10018 | } else { |
10019 | u32 bmcr; | |
10020 | ||
10021 | spin_lock_bh(&tp->lock); | |
10022 | r = -EINVAL; | |
10023 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
10024 | if (!tg3_readphy(tp, MII_BMCR, &bmcr) && | |
10025 | ((bmcr & BMCR_ANENABLE) || | |
f07e9af3 | 10026 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { |
b02fd9e3 MC |
10027 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | |
10028 | BMCR_ANENABLE); | |
10029 | r = 0; | |
10030 | } | |
10031 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 10032 | } |
6aa20a22 | 10033 | |
1da177e4 LT |
10034 | return r; |
10035 | } | |
6aa20a22 | 10036 | |
1da177e4 LT |
10037 | static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
10038 | { | |
10039 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10040 | |
2c49a44d | 10041 | ering->rx_max_pending = tp->rx_std_ring_mask; |
1da177e4 | 10042 | ering->rx_mini_max_pending = 0; |
4f81c32b | 10043 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) |
2c49a44d | 10044 | ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; |
4f81c32b MC |
10045 | else |
10046 | ering->rx_jumbo_max_pending = 0; | |
10047 | ||
10048 | ering->tx_max_pending = TG3_TX_RING_SIZE - 1; | |
1da177e4 LT |
10049 | |
10050 | ering->rx_pending = tp->rx_pending; | |
10051 | ering->rx_mini_pending = 0; | |
4f81c32b MC |
10052 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) |
10053 | ering->rx_jumbo_pending = tp->rx_jumbo_pending; | |
10054 | else | |
10055 | ering->rx_jumbo_pending = 0; | |
10056 | ||
f3f3f27e | 10057 | ering->tx_pending = tp->napi[0].tx_pending; |
1da177e4 | 10058 | } |
6aa20a22 | 10059 | |
1da177e4 LT |
10060 | static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
10061 | { | |
10062 | struct tg3 *tp = netdev_priv(dev); | |
646c9edd | 10063 | int i, irq_sync = 0, err = 0; |
6aa20a22 | 10064 | |
2c49a44d MC |
10065 | if ((ering->rx_pending > tp->rx_std_ring_mask) || |
10066 | (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || | |
bc3a9254 MC |
10067 | (ering->tx_pending > TG3_TX_RING_SIZE - 1) || |
10068 | (ering->tx_pending <= MAX_SKB_FRAGS) || | |
7f62ad5d | 10069 | ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) && |
bc3a9254 | 10070 | (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) |
1da177e4 | 10071 | return -EINVAL; |
6aa20a22 | 10072 | |
bbe832c0 | 10073 | if (netif_running(dev)) { |
b02fd9e3 | 10074 | tg3_phy_stop(tp); |
1da177e4 | 10075 | tg3_netif_stop(tp); |
bbe832c0 MC |
10076 | irq_sync = 1; |
10077 | } | |
1da177e4 | 10078 | |
bbe832c0 | 10079 | tg3_full_lock(tp, irq_sync); |
6aa20a22 | 10080 | |
1da177e4 LT |
10081 | tp->rx_pending = ering->rx_pending; |
10082 | ||
10083 | if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) && | |
10084 | tp->rx_pending > 63) | |
10085 | tp->rx_pending = 63; | |
10086 | tp->rx_jumbo_pending = ering->rx_jumbo_pending; | |
646c9edd | 10087 | |
6fd45cb8 | 10088 | for (i = 0; i < tp->irq_max; i++) |
646c9edd | 10089 | tp->napi[i].tx_pending = ering->tx_pending; |
1da177e4 LT |
10090 | |
10091 | if (netif_running(dev)) { | |
944d980e | 10092 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
b9ec6c1b MC |
10093 | err = tg3_restart_hw(tp, 1); |
10094 | if (!err) | |
10095 | tg3_netif_start(tp); | |
1da177e4 LT |
10096 | } |
10097 | ||
f47c11ee | 10098 | tg3_full_unlock(tp); |
6aa20a22 | 10099 | |
b02fd9e3 MC |
10100 | if (irq_sync && !err) |
10101 | tg3_phy_start(tp); | |
10102 | ||
b9ec6c1b | 10103 | return err; |
1da177e4 | 10104 | } |
6aa20a22 | 10105 | |
1da177e4 LT |
10106 | static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
10107 | { | |
10108 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10109 | |
1da177e4 | 10110 | epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0; |
8d018621 | 10111 | |
e18ce346 | 10112 | if (tp->link_config.active_flowctrl & FLOW_CTRL_RX) |
8d018621 MC |
10113 | epause->rx_pause = 1; |
10114 | else | |
10115 | epause->rx_pause = 0; | |
10116 | ||
e18ce346 | 10117 | if (tp->link_config.active_flowctrl & FLOW_CTRL_TX) |
8d018621 MC |
10118 | epause->tx_pause = 1; |
10119 | else | |
10120 | epause->tx_pause = 0; | |
1da177e4 | 10121 | } |
6aa20a22 | 10122 | |
1da177e4 LT |
10123 | static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
10124 | { | |
10125 | struct tg3 *tp = netdev_priv(dev); | |
b02fd9e3 | 10126 | int err = 0; |
6aa20a22 | 10127 | |
b02fd9e3 | 10128 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
2712168f MC |
10129 | u32 newadv; |
10130 | struct phy_device *phydev; | |
1da177e4 | 10131 | |
2712168f | 10132 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
f47c11ee | 10133 | |
2712168f MC |
10134 | if (!(phydev->supported & SUPPORTED_Pause) || |
10135 | (!(phydev->supported & SUPPORTED_Asym_Pause) && | |
2259dca3 | 10136 | (epause->rx_pause != epause->tx_pause))) |
2712168f | 10137 | return -EINVAL; |
1da177e4 | 10138 | |
2712168f MC |
10139 | tp->link_config.flowctrl = 0; |
10140 | if (epause->rx_pause) { | |
10141 | tp->link_config.flowctrl |= FLOW_CTRL_RX; | |
10142 | ||
10143 | if (epause->tx_pause) { | |
10144 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10145 | newadv = ADVERTISED_Pause; | |
b02fd9e3 | 10146 | } else |
2712168f MC |
10147 | newadv = ADVERTISED_Pause | |
10148 | ADVERTISED_Asym_Pause; | |
10149 | } else if (epause->tx_pause) { | |
10150 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10151 | newadv = ADVERTISED_Asym_Pause; | |
10152 | } else | |
10153 | newadv = 0; | |
10154 | ||
10155 | if (epause->autoneg) | |
10156 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | |
10157 | else | |
10158 | tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG; | |
10159 | ||
f07e9af3 | 10160 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
2712168f MC |
10161 | u32 oldadv = phydev->advertising & |
10162 | (ADVERTISED_Pause | ADVERTISED_Asym_Pause); | |
10163 | if (oldadv != newadv) { | |
10164 | phydev->advertising &= | |
10165 | ~(ADVERTISED_Pause | | |
10166 | ADVERTISED_Asym_Pause); | |
10167 | phydev->advertising |= newadv; | |
10168 | if (phydev->autoneg) { | |
10169 | /* | |
10170 | * Always renegotiate the link to | |
10171 | * inform our link partner of our | |
10172 | * flow control settings, even if the | |
10173 | * flow control is forced. Let | |
10174 | * tg3_adjust_link() do the final | |
10175 | * flow control setup. | |
10176 | */ | |
10177 | return phy_start_aneg(phydev); | |
b02fd9e3 | 10178 | } |
b02fd9e3 | 10179 | } |
b02fd9e3 | 10180 | |
2712168f | 10181 | if (!epause->autoneg) |
b02fd9e3 | 10182 | tg3_setup_flow_control(tp, 0, 0); |
2712168f MC |
10183 | } else { |
10184 | tp->link_config.orig_advertising &= | |
10185 | ~(ADVERTISED_Pause | | |
10186 | ADVERTISED_Asym_Pause); | |
10187 | tp->link_config.orig_advertising |= newadv; | |
b02fd9e3 MC |
10188 | } |
10189 | } else { | |
10190 | int irq_sync = 0; | |
10191 | ||
10192 | if (netif_running(dev)) { | |
10193 | tg3_netif_stop(tp); | |
10194 | irq_sync = 1; | |
10195 | } | |
10196 | ||
10197 | tg3_full_lock(tp, irq_sync); | |
10198 | ||
10199 | if (epause->autoneg) | |
10200 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | |
10201 | else | |
10202 | tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG; | |
10203 | if (epause->rx_pause) | |
e18ce346 | 10204 | tp->link_config.flowctrl |= FLOW_CTRL_RX; |
b02fd9e3 | 10205 | else |
e18ce346 | 10206 | tp->link_config.flowctrl &= ~FLOW_CTRL_RX; |
b02fd9e3 | 10207 | if (epause->tx_pause) |
e18ce346 | 10208 | tp->link_config.flowctrl |= FLOW_CTRL_TX; |
b02fd9e3 | 10209 | else |
e18ce346 | 10210 | tp->link_config.flowctrl &= ~FLOW_CTRL_TX; |
b02fd9e3 MC |
10211 | |
10212 | if (netif_running(dev)) { | |
10213 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
10214 | err = tg3_restart_hw(tp, 1); | |
10215 | if (!err) | |
10216 | tg3_netif_start(tp); | |
10217 | } | |
10218 | ||
10219 | tg3_full_unlock(tp); | |
10220 | } | |
6aa20a22 | 10221 | |
b9ec6c1b | 10222 | return err; |
1da177e4 | 10223 | } |
6aa20a22 | 10224 | |
1da177e4 LT |
10225 | static u32 tg3_get_rx_csum(struct net_device *dev) |
10226 | { | |
10227 | struct tg3 *tp = netdev_priv(dev); | |
10228 | return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0; | |
10229 | } | |
6aa20a22 | 10230 | |
1da177e4 LT |
10231 | static int tg3_set_rx_csum(struct net_device *dev, u32 data) |
10232 | { | |
10233 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10234 | |
1da177e4 LT |
10235 | if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) { |
10236 | if (data != 0) | |
10237 | return -EINVAL; | |
c6cdf436 MC |
10238 | return 0; |
10239 | } | |
6aa20a22 | 10240 | |
f47c11ee | 10241 | spin_lock_bh(&tp->lock); |
1da177e4 LT |
10242 | if (data) |
10243 | tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS; | |
10244 | else | |
10245 | tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS; | |
f47c11ee | 10246 | spin_unlock_bh(&tp->lock); |
6aa20a22 | 10247 | |
1da177e4 LT |
10248 | return 0; |
10249 | } | |
6aa20a22 | 10250 | |
1da177e4 LT |
10251 | static int tg3_set_tx_csum(struct net_device *dev, u32 data) |
10252 | { | |
10253 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10254 | |
1da177e4 LT |
10255 | if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) { |
10256 | if (data != 0) | |
10257 | return -EINVAL; | |
c6cdf436 MC |
10258 | return 0; |
10259 | } | |
6aa20a22 | 10260 | |
321d32a0 | 10261 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
6460d948 | 10262 | ethtool_op_set_tx_ipv6_csum(dev, data); |
1da177e4 | 10263 | else |
9c27dbdf | 10264 | ethtool_op_set_tx_csum(dev, data); |
1da177e4 LT |
10265 | |
10266 | return 0; | |
10267 | } | |
10268 | ||
de6f31eb | 10269 | static int tg3_get_sset_count(struct net_device *dev, int sset) |
1da177e4 | 10270 | { |
b9f2c044 JG |
10271 | switch (sset) { |
10272 | case ETH_SS_TEST: | |
10273 | return TG3_NUM_TEST; | |
10274 | case ETH_SS_STATS: | |
10275 | return TG3_NUM_STATS; | |
10276 | default: | |
10277 | return -EOPNOTSUPP; | |
10278 | } | |
4cafd3f5 MC |
10279 | } |
10280 | ||
de6f31eb | 10281 | static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf) |
1da177e4 LT |
10282 | { |
10283 | switch (stringset) { | |
10284 | case ETH_SS_STATS: | |
10285 | memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys)); | |
10286 | break; | |
4cafd3f5 MC |
10287 | case ETH_SS_TEST: |
10288 | memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys)); | |
10289 | break; | |
1da177e4 LT |
10290 | default: |
10291 | WARN_ON(1); /* we need a WARN() */ | |
10292 | break; | |
10293 | } | |
10294 | } | |
10295 | ||
4009a93d MC |
10296 | static int tg3_phys_id(struct net_device *dev, u32 data) |
10297 | { | |
10298 | struct tg3 *tp = netdev_priv(dev); | |
10299 | int i; | |
10300 | ||
10301 | if (!netif_running(tp->dev)) | |
10302 | return -EAGAIN; | |
10303 | ||
10304 | if (data == 0) | |
759afc31 | 10305 | data = UINT_MAX / 2; |
4009a93d MC |
10306 | |
10307 | for (i = 0; i < (data * 2); i++) { | |
10308 | if ((i % 2) == 0) | |
10309 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10310 | LED_CTRL_1000MBPS_ON | | |
10311 | LED_CTRL_100MBPS_ON | | |
10312 | LED_CTRL_10MBPS_ON | | |
10313 | LED_CTRL_TRAFFIC_OVERRIDE | | |
10314 | LED_CTRL_TRAFFIC_BLINK | | |
10315 | LED_CTRL_TRAFFIC_LED); | |
6aa20a22 | 10316 | |
4009a93d MC |
10317 | else |
10318 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10319 | LED_CTRL_TRAFFIC_OVERRIDE); | |
10320 | ||
10321 | if (msleep_interruptible(500)) | |
10322 | break; | |
10323 | } | |
10324 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
10325 | return 0; | |
10326 | } | |
10327 | ||
de6f31eb | 10328 | static void tg3_get_ethtool_stats(struct net_device *dev, |
1da177e4 LT |
10329 | struct ethtool_stats *estats, u64 *tmp_stats) |
10330 | { | |
10331 | struct tg3 *tp = netdev_priv(dev); | |
10332 | memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats)); | |
10333 | } | |
10334 | ||
566f86ad | 10335 | #define NVRAM_TEST_SIZE 0x100 |
a5767dec MC |
10336 | #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14 |
10337 | #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18 | |
10338 | #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c | |
b16250e3 MC |
10339 | #define NVRAM_SELFBOOT_HW_SIZE 0x20 |
10340 | #define NVRAM_SELFBOOT_DATA_SIZE 0x1c | |
566f86ad MC |
10341 | |
10342 | static int tg3_test_nvram(struct tg3 *tp) | |
10343 | { | |
b9fc7dc5 | 10344 | u32 csum, magic; |
a9dc529d | 10345 | __be32 *buf; |
ab0049b4 | 10346 | int i, j, k, err = 0, size; |
566f86ad | 10347 | |
df259d8c MC |
10348 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) |
10349 | return 0; | |
10350 | ||
e4f34110 | 10351 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1b27777a MC |
10352 | return -EIO; |
10353 | ||
1b27777a MC |
10354 | if (magic == TG3_EEPROM_MAGIC) |
10355 | size = NVRAM_TEST_SIZE; | |
b16250e3 | 10356 | else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) { |
a5767dec MC |
10357 | if ((magic & TG3_EEPROM_SB_FORMAT_MASK) == |
10358 | TG3_EEPROM_SB_FORMAT_1) { | |
10359 | switch (magic & TG3_EEPROM_SB_REVISION_MASK) { | |
10360 | case TG3_EEPROM_SB_REVISION_0: | |
10361 | size = NVRAM_SELFBOOT_FORMAT1_0_SIZE; | |
10362 | break; | |
10363 | case TG3_EEPROM_SB_REVISION_2: | |
10364 | size = NVRAM_SELFBOOT_FORMAT1_2_SIZE; | |
10365 | break; | |
10366 | case TG3_EEPROM_SB_REVISION_3: | |
10367 | size = NVRAM_SELFBOOT_FORMAT1_3_SIZE; | |
10368 | break; | |
10369 | default: | |
10370 | return 0; | |
10371 | } | |
10372 | } else | |
1b27777a | 10373 | return 0; |
b16250e3 MC |
10374 | } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
10375 | size = NVRAM_SELFBOOT_HW_SIZE; | |
10376 | else | |
1b27777a MC |
10377 | return -EIO; |
10378 | ||
10379 | buf = kmalloc(size, GFP_KERNEL); | |
566f86ad MC |
10380 | if (buf == NULL) |
10381 | return -ENOMEM; | |
10382 | ||
1b27777a MC |
10383 | err = -EIO; |
10384 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
a9dc529d MC |
10385 | err = tg3_nvram_read_be32(tp, i, &buf[j]); |
10386 | if (err) | |
566f86ad | 10387 | break; |
566f86ad | 10388 | } |
1b27777a | 10389 | if (i < size) |
566f86ad MC |
10390 | goto out; |
10391 | ||
1b27777a | 10392 | /* Selfboot format */ |
a9dc529d | 10393 | magic = be32_to_cpu(buf[0]); |
b9fc7dc5 | 10394 | if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == |
b16250e3 | 10395 | TG3_EEPROM_MAGIC_FW) { |
1b27777a MC |
10396 | u8 *buf8 = (u8 *) buf, csum8 = 0; |
10397 | ||
b9fc7dc5 | 10398 | if ((magic & TG3_EEPROM_SB_REVISION_MASK) == |
a5767dec MC |
10399 | TG3_EEPROM_SB_REVISION_2) { |
10400 | /* For rev 2, the csum doesn't include the MBA. */ | |
10401 | for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++) | |
10402 | csum8 += buf8[i]; | |
10403 | for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++) | |
10404 | csum8 += buf8[i]; | |
10405 | } else { | |
10406 | for (i = 0; i < size; i++) | |
10407 | csum8 += buf8[i]; | |
10408 | } | |
1b27777a | 10409 | |
ad96b485 AB |
10410 | if (csum8 == 0) { |
10411 | err = 0; | |
10412 | goto out; | |
10413 | } | |
10414 | ||
10415 | err = -EIO; | |
10416 | goto out; | |
1b27777a | 10417 | } |
566f86ad | 10418 | |
b9fc7dc5 | 10419 | if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == |
b16250e3 MC |
10420 | TG3_EEPROM_MAGIC_HW) { |
10421 | u8 data[NVRAM_SELFBOOT_DATA_SIZE]; | |
a9dc529d | 10422 | u8 parity[NVRAM_SELFBOOT_DATA_SIZE]; |
b16250e3 | 10423 | u8 *buf8 = (u8 *) buf; |
b16250e3 MC |
10424 | |
10425 | /* Separate the parity bits and the data bytes. */ | |
10426 | for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) { | |
10427 | if ((i == 0) || (i == 8)) { | |
10428 | int l; | |
10429 | u8 msk; | |
10430 | ||
10431 | for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1) | |
10432 | parity[k++] = buf8[i] & msk; | |
10433 | i++; | |
859a5887 | 10434 | } else if (i == 16) { |
b16250e3 MC |
10435 | int l; |
10436 | u8 msk; | |
10437 | ||
10438 | for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1) | |
10439 | parity[k++] = buf8[i] & msk; | |
10440 | i++; | |
10441 | ||
10442 | for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1) | |
10443 | parity[k++] = buf8[i] & msk; | |
10444 | i++; | |
10445 | } | |
10446 | data[j++] = buf8[i]; | |
10447 | } | |
10448 | ||
10449 | err = -EIO; | |
10450 | for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) { | |
10451 | u8 hw8 = hweight8(data[i]); | |
10452 | ||
10453 | if ((hw8 & 0x1) && parity[i]) | |
10454 | goto out; | |
10455 | else if (!(hw8 & 0x1) && !parity[i]) | |
10456 | goto out; | |
10457 | } | |
10458 | err = 0; | |
10459 | goto out; | |
10460 | } | |
10461 | ||
566f86ad MC |
10462 | /* Bootstrap checksum at offset 0x10 */ |
10463 | csum = calc_crc((unsigned char *) buf, 0x10); | |
a9dc529d | 10464 | if (csum != be32_to_cpu(buf[0x10/4])) |
566f86ad MC |
10465 | goto out; |
10466 | ||
10467 | /* Manufacturing block starts at offset 0x74, checksum at 0xfc */ | |
10468 | csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88); | |
a9dc529d MC |
10469 | if (csum != be32_to_cpu(buf[0xfc/4])) |
10470 | goto out; | |
566f86ad MC |
10471 | |
10472 | err = 0; | |
10473 | ||
10474 | out: | |
10475 | kfree(buf); | |
10476 | return err; | |
10477 | } | |
10478 | ||
ca43007a MC |
10479 | #define TG3_SERDES_TIMEOUT_SEC 2 |
10480 | #define TG3_COPPER_TIMEOUT_SEC 6 | |
10481 | ||
10482 | static int tg3_test_link(struct tg3 *tp) | |
10483 | { | |
10484 | int i, max; | |
10485 | ||
10486 | if (!netif_running(tp->dev)) | |
10487 | return -ENODEV; | |
10488 | ||
f07e9af3 | 10489 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
ca43007a MC |
10490 | max = TG3_SERDES_TIMEOUT_SEC; |
10491 | else | |
10492 | max = TG3_COPPER_TIMEOUT_SEC; | |
10493 | ||
10494 | for (i = 0; i < max; i++) { | |
10495 | if (netif_carrier_ok(tp->dev)) | |
10496 | return 0; | |
10497 | ||
10498 | if (msleep_interruptible(1000)) | |
10499 | break; | |
10500 | } | |
10501 | ||
10502 | return -EIO; | |
10503 | } | |
10504 | ||
a71116d1 | 10505 | /* Only test the commonly used registers */ |
30ca3e37 | 10506 | static int tg3_test_registers(struct tg3 *tp) |
a71116d1 | 10507 | { |
b16250e3 | 10508 | int i, is_5705, is_5750; |
a71116d1 MC |
10509 | u32 offset, read_mask, write_mask, val, save_val, read_val; |
10510 | static struct { | |
10511 | u16 offset; | |
10512 | u16 flags; | |
10513 | #define TG3_FL_5705 0x1 | |
10514 | #define TG3_FL_NOT_5705 0x2 | |
10515 | #define TG3_FL_NOT_5788 0x4 | |
b16250e3 | 10516 | #define TG3_FL_NOT_5750 0x8 |
a71116d1 MC |
10517 | u32 read_mask; |
10518 | u32 write_mask; | |
10519 | } reg_tbl[] = { | |
10520 | /* MAC Control Registers */ | |
10521 | { MAC_MODE, TG3_FL_NOT_5705, | |
10522 | 0x00000000, 0x00ef6f8c }, | |
10523 | { MAC_MODE, TG3_FL_5705, | |
10524 | 0x00000000, 0x01ef6b8c }, | |
10525 | { MAC_STATUS, TG3_FL_NOT_5705, | |
10526 | 0x03800107, 0x00000000 }, | |
10527 | { MAC_STATUS, TG3_FL_5705, | |
10528 | 0x03800100, 0x00000000 }, | |
10529 | { MAC_ADDR_0_HIGH, 0x0000, | |
10530 | 0x00000000, 0x0000ffff }, | |
10531 | { MAC_ADDR_0_LOW, 0x0000, | |
c6cdf436 | 10532 | 0x00000000, 0xffffffff }, |
a71116d1 MC |
10533 | { MAC_RX_MTU_SIZE, 0x0000, |
10534 | 0x00000000, 0x0000ffff }, | |
10535 | { MAC_TX_MODE, 0x0000, | |
10536 | 0x00000000, 0x00000070 }, | |
10537 | { MAC_TX_LENGTHS, 0x0000, | |
10538 | 0x00000000, 0x00003fff }, | |
10539 | { MAC_RX_MODE, TG3_FL_NOT_5705, | |
10540 | 0x00000000, 0x000007fc }, | |
10541 | { MAC_RX_MODE, TG3_FL_5705, | |
10542 | 0x00000000, 0x000007dc }, | |
10543 | { MAC_HASH_REG_0, 0x0000, | |
10544 | 0x00000000, 0xffffffff }, | |
10545 | { MAC_HASH_REG_1, 0x0000, | |
10546 | 0x00000000, 0xffffffff }, | |
10547 | { MAC_HASH_REG_2, 0x0000, | |
10548 | 0x00000000, 0xffffffff }, | |
10549 | { MAC_HASH_REG_3, 0x0000, | |
10550 | 0x00000000, 0xffffffff }, | |
10551 | ||
10552 | /* Receive Data and Receive BD Initiator Control Registers. */ | |
10553 | { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705, | |
10554 | 0x00000000, 0xffffffff }, | |
10555 | { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705, | |
10556 | 0x00000000, 0xffffffff }, | |
10557 | { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705, | |
10558 | 0x00000000, 0x00000003 }, | |
10559 | { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705, | |
10560 | 0x00000000, 0xffffffff }, | |
10561 | { RCVDBDI_STD_BD+0, 0x0000, | |
10562 | 0x00000000, 0xffffffff }, | |
10563 | { RCVDBDI_STD_BD+4, 0x0000, | |
10564 | 0x00000000, 0xffffffff }, | |
10565 | { RCVDBDI_STD_BD+8, 0x0000, | |
10566 | 0x00000000, 0xffff0002 }, | |
10567 | { RCVDBDI_STD_BD+0xc, 0x0000, | |
10568 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 10569 | |
a71116d1 MC |
10570 | /* Receive BD Initiator Control Registers. */ |
10571 | { RCVBDI_STD_THRESH, TG3_FL_NOT_5705, | |
10572 | 0x00000000, 0xffffffff }, | |
10573 | { RCVBDI_STD_THRESH, TG3_FL_5705, | |
10574 | 0x00000000, 0x000003ff }, | |
10575 | { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705, | |
10576 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 10577 | |
a71116d1 MC |
10578 | /* Host Coalescing Control Registers. */ |
10579 | { HOSTCC_MODE, TG3_FL_NOT_5705, | |
10580 | 0x00000000, 0x00000004 }, | |
10581 | { HOSTCC_MODE, TG3_FL_5705, | |
10582 | 0x00000000, 0x000000f6 }, | |
10583 | { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705, | |
10584 | 0x00000000, 0xffffffff }, | |
10585 | { HOSTCC_RXCOL_TICKS, TG3_FL_5705, | |
10586 | 0x00000000, 0x000003ff }, | |
10587 | { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705, | |
10588 | 0x00000000, 0xffffffff }, | |
10589 | { HOSTCC_TXCOL_TICKS, TG3_FL_5705, | |
10590 | 0x00000000, 0x000003ff }, | |
10591 | { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705, | |
10592 | 0x00000000, 0xffffffff }, | |
10593 | { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10594 | 0x00000000, 0x000000ff }, | |
10595 | { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705, | |
10596 | 0x00000000, 0xffffffff }, | |
10597 | { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10598 | 0x00000000, 0x000000ff }, | |
10599 | { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
10600 | 0x00000000, 0xffffffff }, | |
10601 | { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
10602 | 0x00000000, 0xffffffff }, | |
10603 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
10604 | 0x00000000, 0xffffffff }, | |
10605 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10606 | 0x00000000, 0x000000ff }, | |
10607 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
10608 | 0x00000000, 0xffffffff }, | |
10609 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10610 | 0x00000000, 0x000000ff }, | |
10611 | { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705, | |
10612 | 0x00000000, 0xffffffff }, | |
10613 | { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705, | |
10614 | 0x00000000, 0xffffffff }, | |
10615 | { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705, | |
10616 | 0x00000000, 0xffffffff }, | |
10617 | { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000, | |
10618 | 0x00000000, 0xffffffff }, | |
10619 | { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000, | |
10620 | 0x00000000, 0xffffffff }, | |
10621 | { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000, | |
10622 | 0xffffffff, 0x00000000 }, | |
10623 | { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000, | |
10624 | 0xffffffff, 0x00000000 }, | |
10625 | ||
10626 | /* Buffer Manager Control Registers. */ | |
b16250e3 | 10627 | { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750, |
a71116d1 | 10628 | 0x00000000, 0x007fff80 }, |
b16250e3 | 10629 | { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750, |
a71116d1 MC |
10630 | 0x00000000, 0x007fffff }, |
10631 | { BUFMGR_MB_RDMA_LOW_WATER, 0x0000, | |
10632 | 0x00000000, 0x0000003f }, | |
10633 | { BUFMGR_MB_MACRX_LOW_WATER, 0x0000, | |
10634 | 0x00000000, 0x000001ff }, | |
10635 | { BUFMGR_MB_HIGH_WATER, 0x0000, | |
10636 | 0x00000000, 0x000001ff }, | |
10637 | { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705, | |
10638 | 0xffffffff, 0x00000000 }, | |
10639 | { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705, | |
10640 | 0xffffffff, 0x00000000 }, | |
6aa20a22 | 10641 | |
a71116d1 MC |
10642 | /* Mailbox Registers */ |
10643 | { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000, | |
10644 | 0x00000000, 0x000001ff }, | |
10645 | { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705, | |
10646 | 0x00000000, 0x000001ff }, | |
10647 | { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000, | |
10648 | 0x00000000, 0x000007ff }, | |
10649 | { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000, | |
10650 | 0x00000000, 0x000001ff }, | |
10651 | ||
10652 | { 0xffff, 0x0000, 0x00000000, 0x00000000 }, | |
10653 | }; | |
10654 | ||
b16250e3 MC |
10655 | is_5705 = is_5750 = 0; |
10656 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
a71116d1 | 10657 | is_5705 = 1; |
b16250e3 MC |
10658 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
10659 | is_5750 = 1; | |
10660 | } | |
a71116d1 MC |
10661 | |
10662 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { | |
10663 | if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) | |
10664 | continue; | |
10665 | ||
10666 | if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) | |
10667 | continue; | |
10668 | ||
10669 | if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) && | |
10670 | (reg_tbl[i].flags & TG3_FL_NOT_5788)) | |
10671 | continue; | |
10672 | ||
b16250e3 MC |
10673 | if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) |
10674 | continue; | |
10675 | ||
a71116d1 MC |
10676 | offset = (u32) reg_tbl[i].offset; |
10677 | read_mask = reg_tbl[i].read_mask; | |
10678 | write_mask = reg_tbl[i].write_mask; | |
10679 | ||
10680 | /* Save the original register content */ | |
10681 | save_val = tr32(offset); | |
10682 | ||
10683 | /* Determine the read-only value. */ | |
10684 | read_val = save_val & read_mask; | |
10685 | ||
10686 | /* Write zero to the register, then make sure the read-only bits | |
10687 | * are not changed and the read/write bits are all zeros. | |
10688 | */ | |
10689 | tw32(offset, 0); | |
10690 | ||
10691 | val = tr32(offset); | |
10692 | ||
10693 | /* Test the read-only and read/write bits. */ | |
10694 | if (((val & read_mask) != read_val) || (val & write_mask)) | |
10695 | goto out; | |
10696 | ||
10697 | /* Write ones to all the bits defined by RdMask and WrMask, then | |
10698 | * make sure the read-only bits are not changed and the | |
10699 | * read/write bits are all ones. | |
10700 | */ | |
10701 | tw32(offset, read_mask | write_mask); | |
10702 | ||
10703 | val = tr32(offset); | |
10704 | ||
10705 | /* Test the read-only bits. */ | |
10706 | if ((val & read_mask) != read_val) | |
10707 | goto out; | |
10708 | ||
10709 | /* Test the read/write bits. */ | |
10710 | if ((val & write_mask) != write_mask) | |
10711 | goto out; | |
10712 | ||
10713 | tw32(offset, save_val); | |
10714 | } | |
10715 | ||
10716 | return 0; | |
10717 | ||
10718 | out: | |
9f88f29f | 10719 | if (netif_msg_hw(tp)) |
2445e461 MC |
10720 | netdev_err(tp->dev, |
10721 | "Register test failed at offset %x\n", offset); | |
a71116d1 MC |
10722 | tw32(offset, save_val); |
10723 | return -EIO; | |
10724 | } | |
10725 | ||
7942e1db MC |
10726 | static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) |
10727 | { | |
f71e1309 | 10728 | static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a }; |
7942e1db MC |
10729 | int i; |
10730 | u32 j; | |
10731 | ||
e9edda69 | 10732 | for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { |
7942e1db MC |
10733 | for (j = 0; j < len; j += 4) { |
10734 | u32 val; | |
10735 | ||
10736 | tg3_write_mem(tp, offset + j, test_pattern[i]); | |
10737 | tg3_read_mem(tp, offset + j, &val); | |
10738 | if (val != test_pattern[i]) | |
10739 | return -EIO; | |
10740 | } | |
10741 | } | |
10742 | return 0; | |
10743 | } | |
10744 | ||
10745 | static int tg3_test_memory(struct tg3 *tp) | |
10746 | { | |
10747 | static struct mem_entry { | |
10748 | u32 offset; | |
10749 | u32 len; | |
10750 | } mem_tbl_570x[] = { | |
38690194 | 10751 | { 0x00000000, 0x00b50}, |
7942e1db MC |
10752 | { 0x00002000, 0x1c000}, |
10753 | { 0xffffffff, 0x00000} | |
10754 | }, mem_tbl_5705[] = { | |
10755 | { 0x00000100, 0x0000c}, | |
10756 | { 0x00000200, 0x00008}, | |
7942e1db MC |
10757 | { 0x00004000, 0x00800}, |
10758 | { 0x00006000, 0x01000}, | |
10759 | { 0x00008000, 0x02000}, | |
10760 | { 0x00010000, 0x0e000}, | |
10761 | { 0xffffffff, 0x00000} | |
79f4d13a MC |
10762 | }, mem_tbl_5755[] = { |
10763 | { 0x00000200, 0x00008}, | |
10764 | { 0x00004000, 0x00800}, | |
10765 | { 0x00006000, 0x00800}, | |
10766 | { 0x00008000, 0x02000}, | |
10767 | { 0x00010000, 0x0c000}, | |
10768 | { 0xffffffff, 0x00000} | |
b16250e3 MC |
10769 | }, mem_tbl_5906[] = { |
10770 | { 0x00000200, 0x00008}, | |
10771 | { 0x00004000, 0x00400}, | |
10772 | { 0x00006000, 0x00400}, | |
10773 | { 0x00008000, 0x01000}, | |
10774 | { 0x00010000, 0x01000}, | |
10775 | { 0xffffffff, 0x00000} | |
8b5a6c42 MC |
10776 | }, mem_tbl_5717[] = { |
10777 | { 0x00000200, 0x00008}, | |
10778 | { 0x00010000, 0x0a000}, | |
10779 | { 0x00020000, 0x13c00}, | |
10780 | { 0xffffffff, 0x00000} | |
10781 | }, mem_tbl_57765[] = { | |
10782 | { 0x00000200, 0x00008}, | |
10783 | { 0x00004000, 0x00800}, | |
10784 | { 0x00006000, 0x09800}, | |
10785 | { 0x00010000, 0x0a000}, | |
10786 | { 0xffffffff, 0x00000} | |
7942e1db MC |
10787 | }; |
10788 | struct mem_entry *mem_tbl; | |
10789 | int err = 0; | |
10790 | int i; | |
10791 | ||
a50d0796 MC |
10792 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
10793 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
8b5a6c42 MC |
10794 | mem_tbl = mem_tbl_5717; |
10795 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
10796 | mem_tbl = mem_tbl_57765; | |
10797 | else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) | |
321d32a0 MC |
10798 | mem_tbl = mem_tbl_5755; |
10799 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
10800 | mem_tbl = mem_tbl_5906; | |
10801 | else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | |
10802 | mem_tbl = mem_tbl_5705; | |
10803 | else | |
7942e1db MC |
10804 | mem_tbl = mem_tbl_570x; |
10805 | ||
10806 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | |
be98da6a MC |
10807 | err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len); |
10808 | if (err) | |
7942e1db MC |
10809 | break; |
10810 | } | |
6aa20a22 | 10811 | |
7942e1db MC |
10812 | return err; |
10813 | } | |
10814 | ||
9f40dead MC |
10815 | #define TG3_MAC_LOOPBACK 0 |
10816 | #define TG3_PHY_LOOPBACK 1 | |
10817 | ||
10818 | static int tg3_run_loopback(struct tg3 *tp, int loopback_mode) | |
c76949a6 | 10819 | { |
9f40dead | 10820 | u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key; |
fd2ce37f | 10821 | u32 desc_idx, coal_now; |
c76949a6 MC |
10822 | struct sk_buff *skb, *rx_skb; |
10823 | u8 *tx_data; | |
10824 | dma_addr_t map; | |
10825 | int num_pkts, tx_len, rx_len, i, err; | |
10826 | struct tg3_rx_buffer_desc *desc; | |
898a56f8 | 10827 | struct tg3_napi *tnapi, *rnapi; |
8fea32b9 | 10828 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
c76949a6 | 10829 | |
c8873405 MC |
10830 | tnapi = &tp->napi[0]; |
10831 | rnapi = &tp->napi[0]; | |
0c1d0e2b | 10832 | if (tp->irq_cnt > 1) { |
1da85aa3 MC |
10833 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) |
10834 | rnapi = &tp->napi[1]; | |
c8873405 MC |
10835 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
10836 | tnapi = &tp->napi[1]; | |
0c1d0e2b | 10837 | } |
fd2ce37f | 10838 | coal_now = tnapi->coal_now | rnapi->coal_now; |
898a56f8 | 10839 | |
9f40dead | 10840 | if (loopback_mode == TG3_MAC_LOOPBACK) { |
c94e3941 MC |
10841 | /* HW errata - mac loopback fails in some cases on 5780. |
10842 | * Normal traffic and PHY loopback are not affected by | |
aba49f24 MC |
10843 | * errata. Also, the MAC loopback test is deprecated for |
10844 | * all newer ASIC revisions. | |
c94e3941 | 10845 | */ |
aba49f24 MC |
10846 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || |
10847 | (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) | |
c94e3941 MC |
10848 | return 0; |
10849 | ||
49692ca1 MC |
10850 | mac_mode = tp->mac_mode & |
10851 | ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
10852 | mac_mode |= MAC_MODE_PORT_INT_LPBACK; | |
e8f3f6ca MC |
10853 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) |
10854 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
f07e9af3 | 10855 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) |
3f7045c1 MC |
10856 | mac_mode |= MAC_MODE_PORT_MODE_MII; |
10857 | else | |
10858 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
9f40dead MC |
10859 | tw32(MAC_MODE, mac_mode); |
10860 | } else if (loopback_mode == TG3_PHY_LOOPBACK) { | |
3f7045c1 MC |
10861 | u32 val; |
10862 | ||
f07e9af3 | 10863 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
7f97a4bd | 10864 | tg3_phy_fet_toggle_apd(tp, false); |
5d64ad34 MC |
10865 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100; |
10866 | } else | |
10867 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000; | |
3f7045c1 | 10868 | |
9ef8ca99 MC |
10869 | tg3_phy_toggle_automdix(tp, 0); |
10870 | ||
3f7045c1 | 10871 | tg3_writephy(tp, MII_BMCR, val); |
c94e3941 | 10872 | udelay(40); |
5d64ad34 | 10873 | |
49692ca1 MC |
10874 | mac_mode = tp->mac_mode & |
10875 | ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
f07e9af3 | 10876 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
1061b7c5 MC |
10877 | tg3_writephy(tp, MII_TG3_FET_PTEST, |
10878 | MII_TG3_FET_PTEST_FRC_TX_LINK | | |
10879 | MII_TG3_FET_PTEST_FRC_TX_LOCK); | |
10880 | /* The write needs to be flushed for the AC131 */ | |
10881 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
10882 | tg3_readphy(tp, MII_TG3_FET_PTEST, &val); | |
5d64ad34 MC |
10883 | mac_mode |= MAC_MODE_PORT_MODE_MII; |
10884 | } else | |
10885 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
b16250e3 | 10886 | |
c94e3941 | 10887 | /* reset to prevent losing 1st rx packet intermittently */ |
f07e9af3 | 10888 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
c94e3941 MC |
10889 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
10890 | udelay(10); | |
10891 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
10892 | } | |
e8f3f6ca | 10893 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
79eb6904 MC |
10894 | u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; |
10895 | if (masked_phy_id == TG3_PHY_ID_BCM5401) | |
e8f3f6ca | 10896 | mac_mode &= ~MAC_MODE_LINK_POLARITY; |
79eb6904 | 10897 | else if (masked_phy_id == TG3_PHY_ID_BCM5411) |
e8f3f6ca | 10898 | mac_mode |= MAC_MODE_LINK_POLARITY; |
ff18ff02 MC |
10899 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
10900 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
10901 | } | |
9f40dead | 10902 | tw32(MAC_MODE, mac_mode); |
49692ca1 MC |
10903 | |
10904 | /* Wait for link */ | |
10905 | for (i = 0; i < 100; i++) { | |
10906 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
10907 | break; | |
10908 | mdelay(1); | |
10909 | } | |
859a5887 | 10910 | } else { |
9f40dead | 10911 | return -EINVAL; |
859a5887 | 10912 | } |
c76949a6 MC |
10913 | |
10914 | err = -EIO; | |
10915 | ||
c76949a6 | 10916 | tx_len = 1514; |
a20e9c62 | 10917 | skb = netdev_alloc_skb(tp->dev, tx_len); |
a50bb7b9 JJ |
10918 | if (!skb) |
10919 | return -ENOMEM; | |
10920 | ||
c76949a6 MC |
10921 | tx_data = skb_put(skb, tx_len); |
10922 | memcpy(tx_data, tp->dev->dev_addr, 6); | |
10923 | memset(tx_data + 6, 0x0, 8); | |
10924 | ||
10925 | tw32(MAC_RX_MTU_SIZE, tx_len + 4); | |
10926 | ||
10927 | for (i = 14; i < tx_len; i++) | |
10928 | tx_data[i] = (u8) (i & 0xff); | |
10929 | ||
f4188d8a AD |
10930 | map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); |
10931 | if (pci_dma_mapping_error(tp->pdev, map)) { | |
a21771dd MC |
10932 | dev_kfree_skb(skb); |
10933 | return -EIO; | |
10934 | } | |
c76949a6 MC |
10935 | |
10936 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
fd2ce37f | 10937 | rnapi->coal_now); |
c76949a6 MC |
10938 | |
10939 | udelay(10); | |
10940 | ||
898a56f8 | 10941 | rx_start_idx = rnapi->hw_status->idx[0].rx_producer; |
c76949a6 | 10942 | |
c76949a6 MC |
10943 | num_pkts = 0; |
10944 | ||
f4188d8a | 10945 | tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1); |
c76949a6 | 10946 | |
f3f3f27e | 10947 | tnapi->tx_prod++; |
c76949a6 MC |
10948 | num_pkts++; |
10949 | ||
f3f3f27e MC |
10950 | tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); |
10951 | tr32_mailbox(tnapi->prodmbox); | |
c76949a6 MC |
10952 | |
10953 | udelay(10); | |
10954 | ||
303fc921 MC |
10955 | /* 350 usec to allow enough time on some 10/100 Mbps devices. */ |
10956 | for (i = 0; i < 35; i++) { | |
c76949a6 | 10957 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
fd2ce37f | 10958 | coal_now); |
c76949a6 MC |
10959 | |
10960 | udelay(10); | |
10961 | ||
898a56f8 MC |
10962 | tx_idx = tnapi->hw_status->idx[0].tx_consumer; |
10963 | rx_idx = rnapi->hw_status->idx[0].rx_producer; | |
f3f3f27e | 10964 | if ((tx_idx == tnapi->tx_prod) && |
c76949a6 MC |
10965 | (rx_idx == (rx_start_idx + num_pkts))) |
10966 | break; | |
10967 | } | |
10968 | ||
f4188d8a | 10969 | pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE); |
c76949a6 MC |
10970 | dev_kfree_skb(skb); |
10971 | ||
f3f3f27e | 10972 | if (tx_idx != tnapi->tx_prod) |
c76949a6 MC |
10973 | goto out; |
10974 | ||
10975 | if (rx_idx != rx_start_idx + num_pkts) | |
10976 | goto out; | |
10977 | ||
72334482 | 10978 | desc = &rnapi->rx_rcb[rx_start_idx]; |
c76949a6 MC |
10979 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; |
10980 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
10981 | if (opaque_key != RXD_OPAQUE_RING_STD) | |
10982 | goto out; | |
10983 | ||
10984 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
10985 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) | |
10986 | goto out; | |
10987 | ||
10988 | rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; | |
10989 | if (rx_len != tx_len) | |
10990 | goto out; | |
10991 | ||
21f581a5 | 10992 | rx_skb = tpr->rx_std_buffers[desc_idx].skb; |
c76949a6 | 10993 | |
4e5e4f0d | 10994 | map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping); |
c76949a6 MC |
10995 | pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE); |
10996 | ||
10997 | for (i = 14; i < tx_len; i++) { | |
10998 | if (*(rx_skb->data + i) != (u8) (i & 0xff)) | |
10999 | goto out; | |
11000 | } | |
11001 | err = 0; | |
6aa20a22 | 11002 | |
c76949a6 MC |
11003 | /* tg3_free_rings will unmap and free the rx_skb */ |
11004 | out: | |
11005 | return err; | |
11006 | } | |
11007 | ||
9f40dead MC |
11008 | #define TG3_MAC_LOOPBACK_FAILED 1 |
11009 | #define TG3_PHY_LOOPBACK_FAILED 2 | |
11010 | #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \ | |
11011 | TG3_PHY_LOOPBACK_FAILED) | |
11012 | ||
11013 | static int tg3_test_loopback(struct tg3 *tp) | |
11014 | { | |
11015 | int err = 0; | |
9936bcf6 | 11016 | u32 cpmuctrl = 0; |
9f40dead MC |
11017 | |
11018 | if (!netif_running(tp->dev)) | |
11019 | return TG3_LOOPBACK_FAILED; | |
11020 | ||
b9ec6c1b MC |
11021 | err = tg3_reset_hw(tp, 1); |
11022 | if (err) | |
11023 | return TG3_LOOPBACK_FAILED; | |
9f40dead | 11024 | |
6833c043 | 11025 | /* Turn off gphy autopowerdown. */ |
f07e9af3 | 11026 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
11027 | tg3_phy_toggle_apd(tp, false); |
11028 | ||
321d32a0 | 11029 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) { |
9936bcf6 MC |
11030 | int i; |
11031 | u32 status; | |
11032 | ||
11033 | tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER); | |
11034 | ||
11035 | /* Wait for up to 40 microseconds to acquire lock. */ | |
11036 | for (i = 0; i < 4; i++) { | |
11037 | status = tr32(TG3_CPMU_MUTEX_GNT); | |
11038 | if (status == CPMU_MUTEX_GNT_DRIVER) | |
11039 | break; | |
11040 | udelay(10); | |
11041 | } | |
11042 | ||
11043 | if (status != CPMU_MUTEX_GNT_DRIVER) | |
11044 | return TG3_LOOPBACK_FAILED; | |
11045 | ||
b2a5c19c | 11046 | /* Turn off link-based power management. */ |
e875093c | 11047 | cpmuctrl = tr32(TG3_CPMU_CTRL); |
109115e1 MC |
11048 | tw32(TG3_CPMU_CTRL, |
11049 | cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE | | |
11050 | CPMU_CTRL_LINK_AWARE_MODE)); | |
9936bcf6 MC |
11051 | } |
11052 | ||
9f40dead MC |
11053 | if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK)) |
11054 | err |= TG3_MAC_LOOPBACK_FAILED; | |
9936bcf6 | 11055 | |
321d32a0 | 11056 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) { |
9936bcf6 MC |
11057 | tw32(TG3_CPMU_CTRL, cpmuctrl); |
11058 | ||
11059 | /* Release the mutex */ | |
11060 | tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER); | |
11061 | } | |
11062 | ||
f07e9af3 | 11063 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
dd477003 | 11064 | !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { |
9f40dead MC |
11065 | if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK)) |
11066 | err |= TG3_PHY_LOOPBACK_FAILED; | |
11067 | } | |
11068 | ||
6833c043 | 11069 | /* Re-enable gphy autopowerdown. */ |
f07e9af3 | 11070 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
11071 | tg3_phy_toggle_apd(tp, true); |
11072 | ||
9f40dead MC |
11073 | return err; |
11074 | } | |
11075 | ||
4cafd3f5 MC |
11076 | static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest, |
11077 | u64 *data) | |
11078 | { | |
566f86ad MC |
11079 | struct tg3 *tp = netdev_priv(dev); |
11080 | ||
80096068 | 11081 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
c866b7ea | 11082 | tg3_power_up(tp); |
bc1c7567 | 11083 | |
566f86ad MC |
11084 | memset(data, 0, sizeof(u64) * TG3_NUM_TEST); |
11085 | ||
11086 | if (tg3_test_nvram(tp) != 0) { | |
11087 | etest->flags |= ETH_TEST_FL_FAILED; | |
11088 | data[0] = 1; | |
11089 | } | |
ca43007a MC |
11090 | if (tg3_test_link(tp) != 0) { |
11091 | etest->flags |= ETH_TEST_FL_FAILED; | |
11092 | data[1] = 1; | |
11093 | } | |
a71116d1 | 11094 | if (etest->flags & ETH_TEST_FL_OFFLINE) { |
b02fd9e3 | 11095 | int err, err2 = 0, irq_sync = 0; |
bbe832c0 MC |
11096 | |
11097 | if (netif_running(dev)) { | |
b02fd9e3 | 11098 | tg3_phy_stop(tp); |
a71116d1 | 11099 | tg3_netif_stop(tp); |
bbe832c0 MC |
11100 | irq_sync = 1; |
11101 | } | |
a71116d1 | 11102 | |
bbe832c0 | 11103 | tg3_full_lock(tp, irq_sync); |
a71116d1 MC |
11104 | |
11105 | tg3_halt(tp, RESET_KIND_SUSPEND, 1); | |
ec41c7df | 11106 | err = tg3_nvram_lock(tp); |
a71116d1 MC |
11107 | tg3_halt_cpu(tp, RX_CPU_BASE); |
11108 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
11109 | tg3_halt_cpu(tp, TX_CPU_BASE); | |
ec41c7df MC |
11110 | if (!err) |
11111 | tg3_nvram_unlock(tp); | |
a71116d1 | 11112 | |
f07e9af3 | 11113 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
d9ab5ad1 MC |
11114 | tg3_phy_reset(tp); |
11115 | ||
a71116d1 MC |
11116 | if (tg3_test_registers(tp) != 0) { |
11117 | etest->flags |= ETH_TEST_FL_FAILED; | |
11118 | data[2] = 1; | |
11119 | } | |
7942e1db MC |
11120 | if (tg3_test_memory(tp) != 0) { |
11121 | etest->flags |= ETH_TEST_FL_FAILED; | |
11122 | data[3] = 1; | |
11123 | } | |
9f40dead | 11124 | if ((data[4] = tg3_test_loopback(tp)) != 0) |
c76949a6 | 11125 | etest->flags |= ETH_TEST_FL_FAILED; |
a71116d1 | 11126 | |
f47c11ee DM |
11127 | tg3_full_unlock(tp); |
11128 | ||
d4bc3927 MC |
11129 | if (tg3_test_interrupt(tp) != 0) { |
11130 | etest->flags |= ETH_TEST_FL_FAILED; | |
11131 | data[5] = 1; | |
11132 | } | |
f47c11ee DM |
11133 | |
11134 | tg3_full_lock(tp, 0); | |
d4bc3927 | 11135 | |
a71116d1 MC |
11136 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
11137 | if (netif_running(dev)) { | |
11138 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; | |
b02fd9e3 MC |
11139 | err2 = tg3_restart_hw(tp, 1); |
11140 | if (!err2) | |
b9ec6c1b | 11141 | tg3_netif_start(tp); |
a71116d1 | 11142 | } |
f47c11ee DM |
11143 | |
11144 | tg3_full_unlock(tp); | |
b02fd9e3 MC |
11145 | |
11146 | if (irq_sync && !err2) | |
11147 | tg3_phy_start(tp); | |
a71116d1 | 11148 | } |
80096068 | 11149 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
c866b7ea | 11150 | tg3_power_down(tp); |
bc1c7567 | 11151 | |
4cafd3f5 MC |
11152 | } |
11153 | ||
1da177e4 LT |
11154 | static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
11155 | { | |
11156 | struct mii_ioctl_data *data = if_mii(ifr); | |
11157 | struct tg3 *tp = netdev_priv(dev); | |
11158 | int err; | |
11159 | ||
b02fd9e3 | 11160 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
3f0e3ad7 | 11161 | struct phy_device *phydev; |
f07e9af3 | 11162 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 11163 | return -EAGAIN; |
3f0e3ad7 | 11164 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
28b04113 | 11165 | return phy_mii_ioctl(phydev, ifr, cmd); |
b02fd9e3 MC |
11166 | } |
11167 | ||
33f401ae | 11168 | switch (cmd) { |
1da177e4 | 11169 | case SIOCGMIIPHY: |
882e9793 | 11170 | data->phy_id = tp->phy_addr; |
1da177e4 LT |
11171 | |
11172 | /* fallthru */ | |
11173 | case SIOCGMIIREG: { | |
11174 | u32 mii_regval; | |
11175 | ||
f07e9af3 | 11176 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
11177 | break; /* We have no PHY */ |
11178 | ||
f746a313 MC |
11179 | if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) || |
11180 | ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && | |
11181 | !netif_running(dev))) | |
bc1c7567 MC |
11182 | return -EAGAIN; |
11183 | ||
f47c11ee | 11184 | spin_lock_bh(&tp->lock); |
1da177e4 | 11185 | err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); |
f47c11ee | 11186 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
11187 | |
11188 | data->val_out = mii_regval; | |
11189 | ||
11190 | return err; | |
11191 | } | |
11192 | ||
11193 | case SIOCSMIIREG: | |
f07e9af3 | 11194 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
11195 | break; /* We have no PHY */ |
11196 | ||
f746a313 MC |
11197 | if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) || |
11198 | ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && | |
11199 | !netif_running(dev))) | |
bc1c7567 MC |
11200 | return -EAGAIN; |
11201 | ||
f47c11ee | 11202 | spin_lock_bh(&tp->lock); |
1da177e4 | 11203 | err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); |
f47c11ee | 11204 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
11205 | |
11206 | return err; | |
11207 | ||
11208 | default: | |
11209 | /* do nothing */ | |
11210 | break; | |
11211 | } | |
11212 | return -EOPNOTSUPP; | |
11213 | } | |
11214 | ||
15f9850d DM |
11215 | static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
11216 | { | |
11217 | struct tg3 *tp = netdev_priv(dev); | |
11218 | ||
11219 | memcpy(ec, &tp->coal, sizeof(*ec)); | |
11220 | return 0; | |
11221 | } | |
11222 | ||
d244c892 MC |
11223 | static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
11224 | { | |
11225 | struct tg3 *tp = netdev_priv(dev); | |
11226 | u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0; | |
11227 | u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0; | |
11228 | ||
11229 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
11230 | max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT; | |
11231 | max_txcoal_tick_int = MAX_TXCOAL_TICK_INT; | |
11232 | max_stat_coal_ticks = MAX_STAT_COAL_TICKS; | |
11233 | min_stat_coal_ticks = MIN_STAT_COAL_TICKS; | |
11234 | } | |
11235 | ||
11236 | if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || | |
11237 | (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || | |
11238 | (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || | |
11239 | (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || | |
11240 | (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || | |
11241 | (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || | |
11242 | (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || | |
11243 | (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || | |
11244 | (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || | |
11245 | (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) | |
11246 | return -EINVAL; | |
11247 | ||
11248 | /* No rx interrupts will be generated if both are zero */ | |
11249 | if ((ec->rx_coalesce_usecs == 0) && | |
11250 | (ec->rx_max_coalesced_frames == 0)) | |
11251 | return -EINVAL; | |
11252 | ||
11253 | /* No tx interrupts will be generated if both are zero */ | |
11254 | if ((ec->tx_coalesce_usecs == 0) && | |
11255 | (ec->tx_max_coalesced_frames == 0)) | |
11256 | return -EINVAL; | |
11257 | ||
11258 | /* Only copy relevant parameters, ignore all others. */ | |
11259 | tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; | |
11260 | tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; | |
11261 | tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; | |
11262 | tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; | |
11263 | tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; | |
11264 | tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; | |
11265 | tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; | |
11266 | tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; | |
11267 | tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; | |
11268 | ||
11269 | if (netif_running(dev)) { | |
11270 | tg3_full_lock(tp, 0); | |
11271 | __tg3_set_coalesce(tp, &tp->coal); | |
11272 | tg3_full_unlock(tp); | |
11273 | } | |
11274 | return 0; | |
11275 | } | |
11276 | ||
7282d491 | 11277 | static const struct ethtool_ops tg3_ethtool_ops = { |
1da177e4 LT |
11278 | .get_settings = tg3_get_settings, |
11279 | .set_settings = tg3_set_settings, | |
11280 | .get_drvinfo = tg3_get_drvinfo, | |
11281 | .get_regs_len = tg3_get_regs_len, | |
11282 | .get_regs = tg3_get_regs, | |
11283 | .get_wol = tg3_get_wol, | |
11284 | .set_wol = tg3_set_wol, | |
11285 | .get_msglevel = tg3_get_msglevel, | |
11286 | .set_msglevel = tg3_set_msglevel, | |
11287 | .nway_reset = tg3_nway_reset, | |
11288 | .get_link = ethtool_op_get_link, | |
11289 | .get_eeprom_len = tg3_get_eeprom_len, | |
11290 | .get_eeprom = tg3_get_eeprom, | |
11291 | .set_eeprom = tg3_set_eeprom, | |
11292 | .get_ringparam = tg3_get_ringparam, | |
11293 | .set_ringparam = tg3_set_ringparam, | |
11294 | .get_pauseparam = tg3_get_pauseparam, | |
11295 | .set_pauseparam = tg3_set_pauseparam, | |
11296 | .get_rx_csum = tg3_get_rx_csum, | |
11297 | .set_rx_csum = tg3_set_rx_csum, | |
1da177e4 | 11298 | .set_tx_csum = tg3_set_tx_csum, |
1da177e4 | 11299 | .set_sg = ethtool_op_set_sg, |
1da177e4 | 11300 | .set_tso = tg3_set_tso, |
4cafd3f5 | 11301 | .self_test = tg3_self_test, |
1da177e4 | 11302 | .get_strings = tg3_get_strings, |
4009a93d | 11303 | .phys_id = tg3_phys_id, |
1da177e4 | 11304 | .get_ethtool_stats = tg3_get_ethtool_stats, |
15f9850d | 11305 | .get_coalesce = tg3_get_coalesce, |
d244c892 | 11306 | .set_coalesce = tg3_set_coalesce, |
b9f2c044 | 11307 | .get_sset_count = tg3_get_sset_count, |
1da177e4 LT |
11308 | }; |
11309 | ||
11310 | static void __devinit tg3_get_eeprom_size(struct tg3 *tp) | |
11311 | { | |
1b27777a | 11312 | u32 cursize, val, magic; |
1da177e4 LT |
11313 | |
11314 | tp->nvram_size = EEPROM_CHIP_SIZE; | |
11315 | ||
e4f34110 | 11316 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1da177e4 LT |
11317 | return; |
11318 | ||
b16250e3 MC |
11319 | if ((magic != TG3_EEPROM_MAGIC) && |
11320 | ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) && | |
11321 | ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW)) | |
1da177e4 LT |
11322 | return; |
11323 | ||
11324 | /* | |
11325 | * Size the chip by reading offsets at increasing powers of two. | |
11326 | * When we encounter our validation signature, we know the addressing | |
11327 | * has wrapped around, and thus have our chip size. | |
11328 | */ | |
1b27777a | 11329 | cursize = 0x10; |
1da177e4 LT |
11330 | |
11331 | while (cursize < tp->nvram_size) { | |
e4f34110 | 11332 | if (tg3_nvram_read(tp, cursize, &val) != 0) |
1da177e4 LT |
11333 | return; |
11334 | ||
1820180b | 11335 | if (val == magic) |
1da177e4 LT |
11336 | break; |
11337 | ||
11338 | cursize <<= 1; | |
11339 | } | |
11340 | ||
11341 | tp->nvram_size = cursize; | |
11342 | } | |
6aa20a22 | 11343 | |
1da177e4 LT |
11344 | static void __devinit tg3_get_nvram_size(struct tg3 *tp) |
11345 | { | |
11346 | u32 val; | |
11347 | ||
df259d8c MC |
11348 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || |
11349 | tg3_nvram_read(tp, 0, &val) != 0) | |
1b27777a MC |
11350 | return; |
11351 | ||
11352 | /* Selfboot format */ | |
1820180b | 11353 | if (val != TG3_EEPROM_MAGIC) { |
1b27777a MC |
11354 | tg3_get_eeprom_size(tp); |
11355 | return; | |
11356 | } | |
11357 | ||
6d348f2c | 11358 | if (tg3_nvram_read(tp, 0xf0, &val) == 0) { |
1da177e4 | 11359 | if (val != 0) { |
6d348f2c MC |
11360 | /* This is confusing. We want to operate on the |
11361 | * 16-bit value at offset 0xf2. The tg3_nvram_read() | |
11362 | * call will read from NVRAM and byteswap the data | |
11363 | * according to the byteswapping settings for all | |
11364 | * other register accesses. This ensures the data we | |
11365 | * want will always reside in the lower 16-bits. | |
11366 | * However, the data in NVRAM is in LE format, which | |
11367 | * means the data from the NVRAM read will always be | |
11368 | * opposite the endianness of the CPU. The 16-bit | |
11369 | * byteswap then brings the data to CPU endianness. | |
11370 | */ | |
11371 | tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; | |
1da177e4 LT |
11372 | return; |
11373 | } | |
11374 | } | |
fd1122a2 | 11375 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; |
1da177e4 LT |
11376 | } |
11377 | ||
11378 | static void __devinit tg3_get_nvram_info(struct tg3 *tp) | |
11379 | { | |
11380 | u32 nvcfg1; | |
11381 | ||
11382 | nvcfg1 = tr32(NVRAM_CFG1); | |
11383 | if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) { | |
11384 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
8590a603 | 11385 | } else { |
1da177e4 LT |
11386 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
11387 | tw32(NVRAM_CFG1, nvcfg1); | |
11388 | } | |
11389 | ||
4c987487 | 11390 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) || |
a4e2b347 | 11391 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
1da177e4 | 11392 | switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { |
8590a603 MC |
11393 | case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: |
11394 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11395 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
11396 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11397 | break; | |
11398 | case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED: | |
11399 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11400 | tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; | |
11401 | break; | |
11402 | case FLASH_VENDOR_ATMEL_EEPROM: | |
11403 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11404 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11405 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11406 | break; | |
11407 | case FLASH_VENDOR_ST: | |
11408 | tp->nvram_jedecnum = JEDEC_ST; | |
11409 | tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; | |
11410 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11411 | break; | |
11412 | case FLASH_VENDOR_SAIFUN: | |
11413 | tp->nvram_jedecnum = JEDEC_SAIFUN; | |
11414 | tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; | |
11415 | break; | |
11416 | case FLASH_VENDOR_SST_SMALL: | |
11417 | case FLASH_VENDOR_SST_LARGE: | |
11418 | tp->nvram_jedecnum = JEDEC_SST; | |
11419 | tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; | |
11420 | break; | |
1da177e4 | 11421 | } |
8590a603 | 11422 | } else { |
1da177e4 LT |
11423 | tp->nvram_jedecnum = JEDEC_ATMEL; |
11424 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
11425 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11426 | } | |
11427 | } | |
11428 | ||
a1b950d5 MC |
11429 | static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) |
11430 | { | |
11431 | switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) { | |
11432 | case FLASH_5752PAGE_SIZE_256: | |
11433 | tp->nvram_pagesize = 256; | |
11434 | break; | |
11435 | case FLASH_5752PAGE_SIZE_512: | |
11436 | tp->nvram_pagesize = 512; | |
11437 | break; | |
11438 | case FLASH_5752PAGE_SIZE_1K: | |
11439 | tp->nvram_pagesize = 1024; | |
11440 | break; | |
11441 | case FLASH_5752PAGE_SIZE_2K: | |
11442 | tp->nvram_pagesize = 2048; | |
11443 | break; | |
11444 | case FLASH_5752PAGE_SIZE_4K: | |
11445 | tp->nvram_pagesize = 4096; | |
11446 | break; | |
11447 | case FLASH_5752PAGE_SIZE_264: | |
11448 | tp->nvram_pagesize = 264; | |
11449 | break; | |
11450 | case FLASH_5752PAGE_SIZE_528: | |
11451 | tp->nvram_pagesize = 528; | |
11452 | break; | |
11453 | } | |
11454 | } | |
11455 | ||
361b4ac2 MC |
11456 | static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp) |
11457 | { | |
11458 | u32 nvcfg1; | |
11459 | ||
11460 | nvcfg1 = tr32(NVRAM_CFG1); | |
11461 | ||
e6af301b MC |
11462 | /* NVRAM protection for TPM */ |
11463 | if (nvcfg1 & (1 << 27)) | |
f66a29b0 | 11464 | tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; |
e6af301b | 11465 | |
361b4ac2 | 11466 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { |
8590a603 MC |
11467 | case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: |
11468 | case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ: | |
11469 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11470 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11471 | break; | |
11472 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11473 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11474 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11475 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11476 | break; | |
11477 | case FLASH_5752VENDOR_ST_M45PE10: | |
11478 | case FLASH_5752VENDOR_ST_M45PE20: | |
11479 | case FLASH_5752VENDOR_ST_M45PE40: | |
11480 | tp->nvram_jedecnum = JEDEC_ST; | |
11481 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11482 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11483 | break; | |
361b4ac2 MC |
11484 | } |
11485 | ||
11486 | if (tp->tg3_flags2 & TG3_FLG2_FLASH) { | |
a1b950d5 | 11487 | tg3_nvram_get_pagesize(tp, nvcfg1); |
8590a603 | 11488 | } else { |
361b4ac2 MC |
11489 | /* For eeprom, set pagesize to maximum eeprom size */ |
11490 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11491 | ||
11492 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11493 | tw32(NVRAM_CFG1, nvcfg1); | |
11494 | } | |
11495 | } | |
11496 | ||
d3c7b886 MC |
11497 | static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp) |
11498 | { | |
989a9d23 | 11499 | u32 nvcfg1, protect = 0; |
d3c7b886 MC |
11500 | |
11501 | nvcfg1 = tr32(NVRAM_CFG1); | |
11502 | ||
11503 | /* NVRAM protection for TPM */ | |
989a9d23 | 11504 | if (nvcfg1 & (1 << 27)) { |
f66a29b0 | 11505 | tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; |
989a9d23 MC |
11506 | protect = 1; |
11507 | } | |
d3c7b886 | 11508 | |
989a9d23 MC |
11509 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; |
11510 | switch (nvcfg1) { | |
8590a603 MC |
11511 | case FLASH_5755VENDOR_ATMEL_FLASH_1: |
11512 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
11513 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
11514 | case FLASH_5755VENDOR_ATMEL_FLASH_5: | |
11515 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11516 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11517 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11518 | tp->nvram_pagesize = 264; | |
11519 | if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 || | |
11520 | nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5) | |
11521 | tp->nvram_size = (protect ? 0x3e200 : | |
11522 | TG3_NVRAM_SIZE_512KB); | |
11523 | else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2) | |
11524 | tp->nvram_size = (protect ? 0x1f200 : | |
11525 | TG3_NVRAM_SIZE_256KB); | |
11526 | else | |
11527 | tp->nvram_size = (protect ? 0x1f200 : | |
11528 | TG3_NVRAM_SIZE_128KB); | |
11529 | break; | |
11530 | case FLASH_5752VENDOR_ST_M45PE10: | |
11531 | case FLASH_5752VENDOR_ST_M45PE20: | |
11532 | case FLASH_5752VENDOR_ST_M45PE40: | |
11533 | tp->nvram_jedecnum = JEDEC_ST; | |
11534 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11535 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11536 | tp->nvram_pagesize = 256; | |
11537 | if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10) | |
11538 | tp->nvram_size = (protect ? | |
11539 | TG3_NVRAM_SIZE_64KB : | |
11540 | TG3_NVRAM_SIZE_128KB); | |
11541 | else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20) | |
11542 | tp->nvram_size = (protect ? | |
11543 | TG3_NVRAM_SIZE_64KB : | |
11544 | TG3_NVRAM_SIZE_256KB); | |
11545 | else | |
11546 | tp->nvram_size = (protect ? | |
11547 | TG3_NVRAM_SIZE_128KB : | |
11548 | TG3_NVRAM_SIZE_512KB); | |
11549 | break; | |
d3c7b886 MC |
11550 | } |
11551 | } | |
11552 | ||
1b27777a MC |
11553 | static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp) |
11554 | { | |
11555 | u32 nvcfg1; | |
11556 | ||
11557 | nvcfg1 = tr32(NVRAM_CFG1); | |
11558 | ||
11559 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
8590a603 MC |
11560 | case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ: |
11561 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
11562 | case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ: | |
11563 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
11564 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11565 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11566 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
1b27777a | 11567 | |
8590a603 MC |
11568 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
11569 | tw32(NVRAM_CFG1, nvcfg1); | |
11570 | break; | |
11571 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11572 | case FLASH_5755VENDOR_ATMEL_FLASH_1: | |
11573 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
11574 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
11575 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11576 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11577 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11578 | tp->nvram_pagesize = 264; | |
11579 | break; | |
11580 | case FLASH_5752VENDOR_ST_M45PE10: | |
11581 | case FLASH_5752VENDOR_ST_M45PE20: | |
11582 | case FLASH_5752VENDOR_ST_M45PE40: | |
11583 | tp->nvram_jedecnum = JEDEC_ST; | |
11584 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11585 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11586 | tp->nvram_pagesize = 256; | |
11587 | break; | |
1b27777a MC |
11588 | } |
11589 | } | |
11590 | ||
6b91fa02 MC |
11591 | static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp) |
11592 | { | |
11593 | u32 nvcfg1, protect = 0; | |
11594 | ||
11595 | nvcfg1 = tr32(NVRAM_CFG1); | |
11596 | ||
11597 | /* NVRAM protection for TPM */ | |
11598 | if (nvcfg1 & (1 << 27)) { | |
f66a29b0 | 11599 | tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; |
6b91fa02 MC |
11600 | protect = 1; |
11601 | } | |
11602 | ||
11603 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; | |
11604 | switch (nvcfg1) { | |
8590a603 MC |
11605 | case FLASH_5761VENDOR_ATMEL_ADB021D: |
11606 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
11607 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
11608 | case FLASH_5761VENDOR_ATMEL_ADB161D: | |
11609 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
11610 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
11611 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
11612 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
11613 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11614 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11615 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11616 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
11617 | tp->nvram_pagesize = 256; | |
11618 | break; | |
11619 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
11620 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
11621 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
11622 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
11623 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
11624 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
11625 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
11626 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
11627 | tp->nvram_jedecnum = JEDEC_ST; | |
11628 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11629 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11630 | tp->nvram_pagesize = 256; | |
11631 | break; | |
6b91fa02 MC |
11632 | } |
11633 | ||
11634 | if (protect) { | |
11635 | tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); | |
11636 | } else { | |
11637 | switch (nvcfg1) { | |
8590a603 MC |
11638 | case FLASH_5761VENDOR_ATMEL_ADB161D: |
11639 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
11640 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
11641 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
11642 | tp->nvram_size = TG3_NVRAM_SIZE_2MB; | |
11643 | break; | |
11644 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
11645 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
11646 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
11647 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
11648 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
11649 | break; | |
11650 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
11651 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
11652 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
11653 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
11654 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11655 | break; | |
11656 | case FLASH_5761VENDOR_ATMEL_ADB021D: | |
11657 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
11658 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
11659 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
11660 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11661 | break; | |
6b91fa02 MC |
11662 | } |
11663 | } | |
11664 | } | |
11665 | ||
b5d3772c MC |
11666 | static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp) |
11667 | { | |
11668 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11669 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11670 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11671 | } | |
11672 | ||
321d32a0 MC |
11673 | static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp) |
11674 | { | |
11675 | u32 nvcfg1; | |
11676 | ||
11677 | nvcfg1 = tr32(NVRAM_CFG1); | |
11678 | ||
11679 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11680 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
11681 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
11682 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11683 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11684 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11685 | ||
11686 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11687 | tw32(NVRAM_CFG1, nvcfg1); | |
11688 | return; | |
11689 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11690 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
11691 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
11692 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
11693 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
11694 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
11695 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
11696 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11697 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11698 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11699 | ||
11700 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11701 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11702 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
11703 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
11704 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11705 | break; | |
11706 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
11707 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
11708 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11709 | break; | |
11710 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
11711 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
11712 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11713 | break; | |
11714 | } | |
11715 | break; | |
11716 | case FLASH_5752VENDOR_ST_M45PE10: | |
11717 | case FLASH_5752VENDOR_ST_M45PE20: | |
11718 | case FLASH_5752VENDOR_ST_M45PE40: | |
11719 | tp->nvram_jedecnum = JEDEC_ST; | |
11720 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11721 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11722 | ||
11723 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11724 | case FLASH_5752VENDOR_ST_M45PE10: | |
11725 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11726 | break; | |
11727 | case FLASH_5752VENDOR_ST_M45PE20: | |
11728 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11729 | break; | |
11730 | case FLASH_5752VENDOR_ST_M45PE40: | |
11731 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11732 | break; | |
11733 | } | |
11734 | break; | |
11735 | default: | |
df259d8c | 11736 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM; |
321d32a0 MC |
11737 | return; |
11738 | } | |
11739 | ||
a1b950d5 MC |
11740 | tg3_nvram_get_pagesize(tp, nvcfg1); |
11741 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
321d32a0 | 11742 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; |
a1b950d5 MC |
11743 | } |
11744 | ||
11745 | ||
11746 | static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp) | |
11747 | { | |
11748 | u32 nvcfg1; | |
11749 | ||
11750 | nvcfg1 = tr32(NVRAM_CFG1); | |
11751 | ||
11752 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11753 | case FLASH_5717VENDOR_ATMEL_EEPROM: | |
11754 | case FLASH_5717VENDOR_MICRO_EEPROM: | |
11755 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11756 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11757 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11758 | ||
11759 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11760 | tw32(NVRAM_CFG1, nvcfg1); | |
11761 | return; | |
11762 | case FLASH_5717VENDOR_ATMEL_MDB011D: | |
11763 | case FLASH_5717VENDOR_ATMEL_ADB011B: | |
11764 | case FLASH_5717VENDOR_ATMEL_ADB011D: | |
11765 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
11766 | case FLASH_5717VENDOR_ATMEL_ADB021B: | |
11767 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
11768 | case FLASH_5717VENDOR_ATMEL_45USPT: | |
11769 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11770 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11771 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11772 | ||
11773 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11774 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
11775 | case FLASH_5717VENDOR_ATMEL_ADB021B: | |
11776 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
11777 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11778 | break; | |
11779 | default: | |
11780 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11781 | break; | |
11782 | } | |
321d32a0 | 11783 | break; |
a1b950d5 MC |
11784 | case FLASH_5717VENDOR_ST_M_M25PE10: |
11785 | case FLASH_5717VENDOR_ST_A_M25PE10: | |
11786 | case FLASH_5717VENDOR_ST_M_M45PE10: | |
11787 | case FLASH_5717VENDOR_ST_A_M45PE10: | |
11788 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
11789 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
11790 | case FLASH_5717VENDOR_ST_M_M45PE20: | |
11791 | case FLASH_5717VENDOR_ST_A_M45PE20: | |
11792 | case FLASH_5717VENDOR_ST_25USPT: | |
11793 | case FLASH_5717VENDOR_ST_45USPT: | |
11794 | tp->nvram_jedecnum = JEDEC_ST; | |
11795 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11796 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11797 | ||
11798 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11799 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
11800 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
11801 | case FLASH_5717VENDOR_ST_M_M45PE20: | |
11802 | case FLASH_5717VENDOR_ST_A_M45PE20: | |
11803 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11804 | break; | |
11805 | default: | |
11806 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11807 | break; | |
11808 | } | |
321d32a0 | 11809 | break; |
a1b950d5 MC |
11810 | default: |
11811 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM; | |
11812 | return; | |
321d32a0 | 11813 | } |
a1b950d5 MC |
11814 | |
11815 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
11816 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
11817 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
321d32a0 MC |
11818 | } |
11819 | ||
1da177e4 LT |
11820 | /* Chips other than 5700/5701 use the NVRAM for fetching info. */ |
11821 | static void __devinit tg3_nvram_init(struct tg3 *tp) | |
11822 | { | |
1da177e4 LT |
11823 | tw32_f(GRC_EEPROM_ADDR, |
11824 | (EEPROM_ADDR_FSM_RESET | | |
11825 | (EEPROM_DEFAULT_CLOCK_PERIOD << | |
11826 | EEPROM_ADDR_CLKPERD_SHIFT))); | |
11827 | ||
9d57f01c | 11828 | msleep(1); |
1da177e4 LT |
11829 | |
11830 | /* Enable seeprom accesses. */ | |
11831 | tw32_f(GRC_LOCAL_CTRL, | |
11832 | tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); | |
11833 | udelay(100); | |
11834 | ||
11835 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
11836 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
11837 | tp->tg3_flags |= TG3_FLAG_NVRAM; | |
11838 | ||
ec41c7df | 11839 | if (tg3_nvram_lock(tp)) { |
5129c3a3 MC |
11840 | netdev_warn(tp->dev, |
11841 | "Cannot get nvram lock, %s failed\n", | |
05dbe005 | 11842 | __func__); |
ec41c7df MC |
11843 | return; |
11844 | } | |
e6af301b | 11845 | tg3_enable_nvram_access(tp); |
1da177e4 | 11846 | |
989a9d23 MC |
11847 | tp->nvram_size = 0; |
11848 | ||
361b4ac2 MC |
11849 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) |
11850 | tg3_get_5752_nvram_info(tp); | |
d3c7b886 MC |
11851 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
11852 | tg3_get_5755_nvram_info(tp); | |
d30cdd28 | 11853 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
57e6983c MC |
11854 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
11855 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1b27777a | 11856 | tg3_get_5787_nvram_info(tp); |
6b91fa02 MC |
11857 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
11858 | tg3_get_5761_nvram_info(tp); | |
b5d3772c MC |
11859 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
11860 | tg3_get_5906_nvram_info(tp); | |
b703df6f MC |
11861 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
11862 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
321d32a0 | 11863 | tg3_get_57780_nvram_info(tp); |
a50d0796 MC |
11864 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
11865 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
a1b950d5 | 11866 | tg3_get_5717_nvram_info(tp); |
361b4ac2 MC |
11867 | else |
11868 | tg3_get_nvram_info(tp); | |
11869 | ||
989a9d23 MC |
11870 | if (tp->nvram_size == 0) |
11871 | tg3_get_nvram_size(tp); | |
1da177e4 | 11872 | |
e6af301b | 11873 | tg3_disable_nvram_access(tp); |
381291b7 | 11874 | tg3_nvram_unlock(tp); |
1da177e4 LT |
11875 | |
11876 | } else { | |
11877 | tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED); | |
11878 | ||
11879 | tg3_get_eeprom_size(tp); | |
11880 | } | |
11881 | } | |
11882 | ||
1da177e4 LT |
11883 | static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, |
11884 | u32 offset, u32 len, u8 *buf) | |
11885 | { | |
11886 | int i, j, rc = 0; | |
11887 | u32 val; | |
11888 | ||
11889 | for (i = 0; i < len; i += 4) { | |
b9fc7dc5 | 11890 | u32 addr; |
a9dc529d | 11891 | __be32 data; |
1da177e4 LT |
11892 | |
11893 | addr = offset + i; | |
11894 | ||
11895 | memcpy(&data, buf + i, 4); | |
11896 | ||
62cedd11 MC |
11897 | /* |
11898 | * The SEEPROM interface expects the data to always be opposite | |
11899 | * the native endian format. We accomplish this by reversing | |
11900 | * all the operations that would have been performed on the | |
11901 | * data from a call to tg3_nvram_read_be32(). | |
11902 | */ | |
11903 | tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data))); | |
1da177e4 LT |
11904 | |
11905 | val = tr32(GRC_EEPROM_ADDR); | |
11906 | tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE); | |
11907 | ||
11908 | val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK | | |
11909 | EEPROM_ADDR_READ); | |
11910 | tw32(GRC_EEPROM_ADDR, val | | |
11911 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
11912 | (addr & EEPROM_ADDR_ADDR_MASK) | | |
11913 | EEPROM_ADDR_START | | |
11914 | EEPROM_ADDR_WRITE); | |
6aa20a22 | 11915 | |
9d57f01c | 11916 | for (j = 0; j < 1000; j++) { |
1da177e4 LT |
11917 | val = tr32(GRC_EEPROM_ADDR); |
11918 | ||
11919 | if (val & EEPROM_ADDR_COMPLETE) | |
11920 | break; | |
9d57f01c | 11921 | msleep(1); |
1da177e4 LT |
11922 | } |
11923 | if (!(val & EEPROM_ADDR_COMPLETE)) { | |
11924 | rc = -EBUSY; | |
11925 | break; | |
11926 | } | |
11927 | } | |
11928 | ||
11929 | return rc; | |
11930 | } | |
11931 | ||
11932 | /* offset and length are dword aligned */ | |
11933 | static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, | |
11934 | u8 *buf) | |
11935 | { | |
11936 | int ret = 0; | |
11937 | u32 pagesize = tp->nvram_pagesize; | |
11938 | u32 pagemask = pagesize - 1; | |
11939 | u32 nvram_cmd; | |
11940 | u8 *tmp; | |
11941 | ||
11942 | tmp = kmalloc(pagesize, GFP_KERNEL); | |
11943 | if (tmp == NULL) | |
11944 | return -ENOMEM; | |
11945 | ||
11946 | while (len) { | |
11947 | int j; | |
e6af301b | 11948 | u32 phy_addr, page_off, size; |
1da177e4 LT |
11949 | |
11950 | phy_addr = offset & ~pagemask; | |
6aa20a22 | 11951 | |
1da177e4 | 11952 | for (j = 0; j < pagesize; j += 4) { |
a9dc529d MC |
11953 | ret = tg3_nvram_read_be32(tp, phy_addr + j, |
11954 | (__be32 *) (tmp + j)); | |
11955 | if (ret) | |
1da177e4 LT |
11956 | break; |
11957 | } | |
11958 | if (ret) | |
11959 | break; | |
11960 | ||
c6cdf436 | 11961 | page_off = offset & pagemask; |
1da177e4 LT |
11962 | size = pagesize; |
11963 | if (len < size) | |
11964 | size = len; | |
11965 | ||
11966 | len -= size; | |
11967 | ||
11968 | memcpy(tmp + page_off, buf, size); | |
11969 | ||
11970 | offset = offset + (pagesize - page_off); | |
11971 | ||
e6af301b | 11972 | tg3_enable_nvram_access(tp); |
1da177e4 LT |
11973 | |
11974 | /* | |
11975 | * Before we can erase the flash page, we need | |
11976 | * to issue a special "write enable" command. | |
11977 | */ | |
11978 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
11979 | ||
11980 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
11981 | break; | |
11982 | ||
11983 | /* Erase the target page */ | |
11984 | tw32(NVRAM_ADDR, phy_addr); | |
11985 | ||
11986 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR | | |
11987 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE; | |
11988 | ||
c6cdf436 | 11989 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) |
1da177e4 LT |
11990 | break; |
11991 | ||
11992 | /* Issue another write enable to start the write. */ | |
11993 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
11994 | ||
11995 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
11996 | break; | |
11997 | ||
11998 | for (j = 0; j < pagesize; j += 4) { | |
b9fc7dc5 | 11999 | __be32 data; |
1da177e4 | 12000 | |
b9fc7dc5 | 12001 | data = *((__be32 *) (tmp + j)); |
a9dc529d | 12002 | |
b9fc7dc5 | 12003 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 LT |
12004 | |
12005 | tw32(NVRAM_ADDR, phy_addr + j); | |
12006 | ||
12007 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | | |
12008 | NVRAM_CMD_WR; | |
12009 | ||
12010 | if (j == 0) | |
12011 | nvram_cmd |= NVRAM_CMD_FIRST; | |
12012 | else if (j == (pagesize - 4)) | |
12013 | nvram_cmd |= NVRAM_CMD_LAST; | |
12014 | ||
12015 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
12016 | break; | |
12017 | } | |
12018 | if (ret) | |
12019 | break; | |
12020 | } | |
12021 | ||
12022 | nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12023 | tg3_nvram_exec_cmd(tp, nvram_cmd); | |
12024 | ||
12025 | kfree(tmp); | |
12026 | ||
12027 | return ret; | |
12028 | } | |
12029 | ||
12030 | /* offset and length are dword aligned */ | |
12031 | static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, | |
12032 | u8 *buf) | |
12033 | { | |
12034 | int i, ret = 0; | |
12035 | ||
12036 | for (i = 0; i < len; i += 4, offset += 4) { | |
b9fc7dc5 AV |
12037 | u32 page_off, phy_addr, nvram_cmd; |
12038 | __be32 data; | |
1da177e4 LT |
12039 | |
12040 | memcpy(&data, buf + i, 4); | |
b9fc7dc5 | 12041 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 | 12042 | |
c6cdf436 | 12043 | page_off = offset % tp->nvram_pagesize; |
1da177e4 | 12044 | |
1820180b | 12045 | phy_addr = tg3_nvram_phys_addr(tp, offset); |
1da177e4 LT |
12046 | |
12047 | tw32(NVRAM_ADDR, phy_addr); | |
12048 | ||
12049 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR; | |
12050 | ||
c6cdf436 | 12051 | if (page_off == 0 || i == 0) |
1da177e4 | 12052 | nvram_cmd |= NVRAM_CMD_FIRST; |
f6d9a256 | 12053 | if (page_off == (tp->nvram_pagesize - 4)) |
1da177e4 LT |
12054 | nvram_cmd |= NVRAM_CMD_LAST; |
12055 | ||
12056 | if (i == (len - 4)) | |
12057 | nvram_cmd |= NVRAM_CMD_LAST; | |
12058 | ||
321d32a0 MC |
12059 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 && |
12060 | !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) && | |
4c987487 MC |
12061 | (tp->nvram_jedecnum == JEDEC_ST) && |
12062 | (nvram_cmd & NVRAM_CMD_FIRST)) { | |
1da177e4 LT |
12063 | |
12064 | if ((ret = tg3_nvram_exec_cmd(tp, | |
12065 | NVRAM_CMD_WREN | NVRAM_CMD_GO | | |
12066 | NVRAM_CMD_DONE))) | |
12067 | ||
12068 | break; | |
12069 | } | |
12070 | if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) { | |
12071 | /* We always do complete word writes to eeprom. */ | |
12072 | nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST); | |
12073 | } | |
12074 | ||
12075 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
12076 | break; | |
12077 | } | |
12078 | return ret; | |
12079 | } | |
12080 | ||
12081 | /* offset and length are dword aligned */ | |
12082 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) | |
12083 | { | |
12084 | int ret; | |
12085 | ||
1da177e4 | 12086 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { |
314fba34 MC |
12087 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & |
12088 | ~GRC_LCLCTRL_GPIO_OUTPUT1); | |
1da177e4 LT |
12089 | udelay(40); |
12090 | } | |
12091 | ||
12092 | if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) { | |
12093 | ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); | |
859a5887 | 12094 | } else { |
1da177e4 LT |
12095 | u32 grc_mode; |
12096 | ||
ec41c7df MC |
12097 | ret = tg3_nvram_lock(tp); |
12098 | if (ret) | |
12099 | return ret; | |
1da177e4 | 12100 | |
e6af301b MC |
12101 | tg3_enable_nvram_access(tp); |
12102 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
f66a29b0 | 12103 | !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) |
1da177e4 | 12104 | tw32(NVRAM_WRITE1, 0x406); |
1da177e4 LT |
12105 | |
12106 | grc_mode = tr32(GRC_MODE); | |
12107 | tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE); | |
12108 | ||
12109 | if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) || | |
12110 | !(tp->tg3_flags2 & TG3_FLG2_FLASH)) { | |
12111 | ||
12112 | ret = tg3_nvram_write_block_buffered(tp, offset, len, | |
12113 | buf); | |
859a5887 | 12114 | } else { |
1da177e4 LT |
12115 | ret = tg3_nvram_write_block_unbuffered(tp, offset, len, |
12116 | buf); | |
12117 | } | |
12118 | ||
12119 | grc_mode = tr32(GRC_MODE); | |
12120 | tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE); | |
12121 | ||
e6af301b | 12122 | tg3_disable_nvram_access(tp); |
1da177e4 LT |
12123 | tg3_nvram_unlock(tp); |
12124 | } | |
12125 | ||
12126 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { | |
314fba34 | 12127 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
1da177e4 LT |
12128 | udelay(40); |
12129 | } | |
12130 | ||
12131 | return ret; | |
12132 | } | |
12133 | ||
12134 | struct subsys_tbl_ent { | |
12135 | u16 subsys_vendor, subsys_devid; | |
12136 | u32 phy_id; | |
12137 | }; | |
12138 | ||
24daf2b0 | 12139 | static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = { |
1da177e4 | 12140 | /* Broadcom boards. */ |
24daf2b0 | 12141 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12142 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12143 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12144 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12145 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12146 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 }, |
24daf2b0 MC |
12147 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
12148 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 }, | |
12149 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 12150 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12151 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12152 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12153 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
12154 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 }, | |
12155 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 12156 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12157 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12158 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12159 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12160 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 }, |
24daf2b0 | 12161 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12162 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 }, |
1da177e4 LT |
12163 | |
12164 | /* 3com boards. */ | |
24daf2b0 | 12165 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12166 | TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12167 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12168 | TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12169 | { TG3PCI_SUBVENDOR_ID_3COM, |
12170 | TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 }, | |
12171 | { TG3PCI_SUBVENDOR_ID_3COM, | |
79eb6904 | 12172 | TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12173 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12174 | TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
12175 | |
12176 | /* DELL boards. */ | |
24daf2b0 | 12177 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12178 | TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12179 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12180 | TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12181 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12182 | TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 }, |
24daf2b0 | 12183 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12184 | TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 }, |
1da177e4 LT |
12185 | |
12186 | /* Compaq boards. */ | |
24daf2b0 | 12187 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12188 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12189 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12190 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12191 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
12192 | TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 }, | |
12193 | { TG3PCI_SUBVENDOR_ID_COMPAQ, | |
79eb6904 | 12194 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12195 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12196 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
12197 | |
12198 | /* IBM boards. */ | |
24daf2b0 MC |
12199 | { TG3PCI_SUBVENDOR_ID_IBM, |
12200 | TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 } | |
1da177e4 LT |
12201 | }; |
12202 | ||
24daf2b0 | 12203 | static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp) |
1da177e4 LT |
12204 | { |
12205 | int i; | |
12206 | ||
12207 | for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) { | |
12208 | if ((subsys_id_to_phy_id[i].subsys_vendor == | |
12209 | tp->pdev->subsystem_vendor) && | |
12210 | (subsys_id_to_phy_id[i].subsys_devid == | |
12211 | tp->pdev->subsystem_device)) | |
12212 | return &subsys_id_to_phy_id[i]; | |
12213 | } | |
12214 | return NULL; | |
12215 | } | |
12216 | ||
7d0c41ef | 12217 | static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) |
1da177e4 | 12218 | { |
1da177e4 | 12219 | u32 val; |
caf636c7 MC |
12220 | u16 pmcsr; |
12221 | ||
12222 | /* On some early chips the SRAM cannot be accessed in D3hot state, | |
12223 | * so need make sure we're in D0. | |
12224 | */ | |
12225 | pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr); | |
12226 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
12227 | pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr); | |
12228 | msleep(1); | |
7d0c41ef MC |
12229 | |
12230 | /* Make sure register accesses (indirect or otherwise) | |
12231 | * will function correctly. | |
12232 | */ | |
12233 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
12234 | tp->misc_host_ctrl); | |
1da177e4 | 12235 | |
f49639e6 DM |
12236 | /* The memory arbiter has to be enabled in order for SRAM accesses |
12237 | * to succeed. Normally on powerup the tg3 chip firmware will make | |
12238 | * sure it is enabled, but other entities such as system netboot | |
12239 | * code might disable it. | |
12240 | */ | |
12241 | val = tr32(MEMARB_MODE); | |
12242 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); | |
12243 | ||
79eb6904 | 12244 | tp->phy_id = TG3_PHY_ID_INVALID; |
7d0c41ef MC |
12245 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; |
12246 | ||
a85feb8c GZ |
12247 | /* Assume an onboard device and WOL capable by default. */ |
12248 | tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP; | |
72b845e0 | 12249 | |
b5d3772c | 12250 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
9d26e213 | 12251 | if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { |
b5d3772c | 12252 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; |
9d26e213 MC |
12253 | tp->tg3_flags2 |= TG3_FLG2_IS_NIC; |
12254 | } | |
0527ba35 MC |
12255 | val = tr32(VCPU_CFGSHDW); |
12256 | if (val & VCPU_CFGSHDW_ASPM_DBNC) | |
8ed5d97e | 12257 | tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; |
0527ba35 | 12258 | if ((val & VCPU_CFGSHDW_WOL_ENABLE) && |
2023276e | 12259 | (val & VCPU_CFGSHDW_WOL_MAGPKT)) |
0527ba35 | 12260 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; |
05ac4cb7 | 12261 | goto done; |
b5d3772c MC |
12262 | } |
12263 | ||
1da177e4 LT |
12264 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
12265 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
12266 | u32 nic_cfg, led_cfg; | |
a9daf367 | 12267 | u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id; |
7d0c41ef | 12268 | int eeprom_phy_serdes = 0; |
1da177e4 LT |
12269 | |
12270 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
12271 | tp->nic_sram_data_cfg = nic_cfg; | |
12272 | ||
12273 | tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); | |
12274 | ver >>= NIC_SRAM_DATA_VER_SHIFT; | |
12275 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) && | |
12276 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) && | |
12277 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) && | |
12278 | (ver > 0) && (ver < 0x100)) | |
12279 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); | |
12280 | ||
a9daf367 MC |
12281 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
12282 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); | |
12283 | ||
1da177e4 LT |
12284 | if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == |
12285 | NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) | |
12286 | eeprom_phy_serdes = 1; | |
12287 | ||
12288 | tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); | |
12289 | if (nic_phy_id != 0) { | |
12290 | u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK; | |
12291 | u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK; | |
12292 | ||
12293 | eeprom_phy_id = (id1 >> 16) << 10; | |
12294 | eeprom_phy_id |= (id2 & 0xfc00) << 16; | |
12295 | eeprom_phy_id |= (id2 & 0x03ff) << 0; | |
12296 | } else | |
12297 | eeprom_phy_id = 0; | |
12298 | ||
7d0c41ef | 12299 | tp->phy_id = eeprom_phy_id; |
747e8f8b | 12300 | if (eeprom_phy_serdes) { |
a50d0796 | 12301 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) |
f07e9af3 | 12302 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
a50d0796 | 12303 | else |
f07e9af3 | 12304 | tp->phy_flags |= TG3_PHYFLG_MII_SERDES; |
747e8f8b | 12305 | } |
7d0c41ef | 12306 | |
cbf46853 | 12307 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
1da177e4 LT |
12308 | led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | |
12309 | SHASTA_EXT_LED_MODE_MASK); | |
cbf46853 | 12310 | else |
1da177e4 LT |
12311 | led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK; |
12312 | ||
12313 | switch (led_cfg) { | |
12314 | default: | |
12315 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1: | |
12316 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12317 | break; | |
12318 | ||
12319 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2: | |
12320 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
12321 | break; | |
12322 | ||
12323 | case NIC_SRAM_DATA_CFG_LED_MODE_MAC: | |
12324 | tp->led_ctrl = LED_CTRL_MODE_MAC; | |
9ba27794 MC |
12325 | |
12326 | /* Default to PHY_1_MODE if 0 (MAC_MODE) is | |
12327 | * read on some older 5700/5701 bootcode. | |
12328 | */ | |
12329 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
12330 | ASIC_REV_5700 || | |
12331 | GET_ASIC_REV(tp->pci_chip_rev_id) == | |
12332 | ASIC_REV_5701) | |
12333 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12334 | ||
1da177e4 LT |
12335 | break; |
12336 | ||
12337 | case SHASTA_EXT_LED_SHARED: | |
12338 | tp->led_ctrl = LED_CTRL_MODE_SHARED; | |
12339 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && | |
12340 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A1) | |
12341 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
12342 | LED_CTRL_MODE_PHY_2); | |
12343 | break; | |
12344 | ||
12345 | case SHASTA_EXT_LED_MAC: | |
12346 | tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; | |
12347 | break; | |
12348 | ||
12349 | case SHASTA_EXT_LED_COMBO: | |
12350 | tp->led_ctrl = LED_CTRL_MODE_COMBO; | |
12351 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) | |
12352 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
12353 | LED_CTRL_MODE_PHY_2); | |
12354 | break; | |
12355 | ||
855e1111 | 12356 | } |
1da177e4 LT |
12357 | |
12358 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
12359 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && | |
12360 | tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
12361 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
12362 | ||
b2a5c19c MC |
12363 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) |
12364 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
5f60891b | 12365 | |
9d26e213 | 12366 | if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) { |
1da177e4 | 12367 | tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT; |
9d26e213 MC |
12368 | if ((tp->pdev->subsystem_vendor == |
12369 | PCI_VENDOR_ID_ARIMA) && | |
12370 | (tp->pdev->subsystem_device == 0x205a || | |
12371 | tp->pdev->subsystem_device == 0x2063)) | |
12372 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; | |
12373 | } else { | |
f49639e6 | 12374 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; |
9d26e213 MC |
12375 | tp->tg3_flags2 |= TG3_FLG2_IS_NIC; |
12376 | } | |
1da177e4 LT |
12377 | |
12378 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
12379 | tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; | |
cbf46853 | 12380 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
1da177e4 LT |
12381 | tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; |
12382 | } | |
b2b98d4a MC |
12383 | |
12384 | if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) && | |
12385 | (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) | |
0d3031d9 | 12386 | tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE; |
b2b98d4a | 12387 | |
f07e9af3 | 12388 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && |
a85feb8c GZ |
12389 | !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)) |
12390 | tp->tg3_flags &= ~TG3_FLAG_WOL_CAP; | |
1da177e4 | 12391 | |
12dac075 | 12392 | if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) && |
05ac4cb7 | 12393 | (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) |
0527ba35 MC |
12394 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; |
12395 | ||
1da177e4 | 12396 | if (cfg2 & (1 << 17)) |
f07e9af3 | 12397 | tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; |
1da177e4 LT |
12398 | |
12399 | /* serdes signal pre-emphasis in register 0x590 set by */ | |
12400 | /* bootcode if bit 18 is set */ | |
12401 | if (cfg2 & (1 << 18)) | |
f07e9af3 | 12402 | tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; |
8ed5d97e | 12403 | |
2e1e3291 MC |
12404 | if (((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) || |
12405 | ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
12406 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX))) && | |
6833c043 | 12407 | (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) |
f07e9af3 | 12408 | tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; |
6833c043 | 12409 | |
8c69b1e7 MC |
12410 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && |
12411 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
12412 | !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) { | |
8ed5d97e MC |
12413 | u32 cfg3; |
12414 | ||
12415 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); | |
12416 | if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) | |
12417 | tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; | |
12418 | } | |
a9daf367 | 12419 | |
14417063 MC |
12420 | if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE) |
12421 | tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE; | |
a9daf367 MC |
12422 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN) |
12423 | tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN; | |
12424 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN) | |
12425 | tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN; | |
1da177e4 | 12426 | } |
05ac4cb7 MC |
12427 | done: |
12428 | device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP); | |
12429 | device_set_wakeup_enable(&tp->pdev->dev, | |
12430 | tp->tg3_flags & TG3_FLAG_WOL_ENABLE); | |
7d0c41ef MC |
12431 | } |
12432 | ||
b2a5c19c MC |
12433 | static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd) |
12434 | { | |
12435 | int i; | |
12436 | u32 val; | |
12437 | ||
12438 | tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START); | |
12439 | tw32(OTP_CTRL, cmd); | |
12440 | ||
12441 | /* Wait for up to 1 ms for command to execute. */ | |
12442 | for (i = 0; i < 100; i++) { | |
12443 | val = tr32(OTP_STATUS); | |
12444 | if (val & OTP_STATUS_CMD_DONE) | |
12445 | break; | |
12446 | udelay(10); | |
12447 | } | |
12448 | ||
12449 | return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; | |
12450 | } | |
12451 | ||
12452 | /* Read the gphy configuration from the OTP region of the chip. The gphy | |
12453 | * configuration is a 32-bit value that straddles the alignment boundary. | |
12454 | * We do two 32-bit reads and then shift and merge the results. | |
12455 | */ | |
12456 | static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp) | |
12457 | { | |
12458 | u32 bhalf_otp, thalf_otp; | |
12459 | ||
12460 | tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC); | |
12461 | ||
12462 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) | |
12463 | return 0; | |
12464 | ||
12465 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1); | |
12466 | ||
12467 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
12468 | return 0; | |
12469 | ||
12470 | thalf_otp = tr32(OTP_READ_DATA); | |
12471 | ||
12472 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2); | |
12473 | ||
12474 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
12475 | return 0; | |
12476 | ||
12477 | bhalf_otp = tr32(OTP_READ_DATA); | |
12478 | ||
12479 | return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16); | |
12480 | } | |
12481 | ||
7d0c41ef MC |
12482 | static int __devinit tg3_phy_probe(struct tg3 *tp) |
12483 | { | |
12484 | u32 hw_phy_id_1, hw_phy_id_2; | |
12485 | u32 hw_phy_id, hw_phy_id_masked; | |
12486 | int err; | |
1da177e4 | 12487 | |
b02fd9e3 MC |
12488 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) |
12489 | return tg3_phy_init(tp); | |
12490 | ||
1da177e4 | 12491 | /* Reading the PHY ID register can conflict with ASF |
877d0310 | 12492 | * firmware access to the PHY hardware. |
1da177e4 LT |
12493 | */ |
12494 | err = 0; | |
0d3031d9 MC |
12495 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || |
12496 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
79eb6904 | 12497 | hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID; |
1da177e4 LT |
12498 | } else { |
12499 | /* Now read the physical PHY_ID from the chip and verify | |
12500 | * that it is sane. If it doesn't look good, we fall back | |
12501 | * to either the hard-coded table based PHY_ID and failing | |
12502 | * that the value found in the eeprom area. | |
12503 | */ | |
12504 | err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); | |
12505 | err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); | |
12506 | ||
12507 | hw_phy_id = (hw_phy_id_1 & 0xffff) << 10; | |
12508 | hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16; | |
12509 | hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0; | |
12510 | ||
79eb6904 | 12511 | hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK; |
1da177e4 LT |
12512 | } |
12513 | ||
79eb6904 | 12514 | if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) { |
1da177e4 | 12515 | tp->phy_id = hw_phy_id; |
79eb6904 | 12516 | if (hw_phy_id_masked == TG3_PHY_ID_BCM8002) |
f07e9af3 | 12517 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
da6b2d01 | 12518 | else |
f07e9af3 | 12519 | tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; |
1da177e4 | 12520 | } else { |
79eb6904 | 12521 | if (tp->phy_id != TG3_PHY_ID_INVALID) { |
7d0c41ef MC |
12522 | /* Do nothing, phy ID already set up in |
12523 | * tg3_get_eeprom_hw_cfg(). | |
12524 | */ | |
1da177e4 LT |
12525 | } else { |
12526 | struct subsys_tbl_ent *p; | |
12527 | ||
12528 | /* No eeprom signature? Try the hardcoded | |
12529 | * subsys device table. | |
12530 | */ | |
24daf2b0 | 12531 | p = tg3_lookup_by_subsys(tp); |
1da177e4 LT |
12532 | if (!p) |
12533 | return -ENODEV; | |
12534 | ||
12535 | tp->phy_id = p->phy_id; | |
12536 | if (!tp->phy_id || | |
79eb6904 | 12537 | tp->phy_id == TG3_PHY_ID_BCM8002) |
f07e9af3 | 12538 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
1da177e4 LT |
12539 | } |
12540 | } | |
12541 | ||
a6b68dab MC |
12542 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
12543 | ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 && | |
12544 | tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) || | |
12545 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 && | |
12546 | tp->pci_chip_rev_id != CHIPREV_ID_57765_A0))) | |
52b02d04 MC |
12547 | tp->phy_flags |= TG3_PHYFLG_EEE_CAP; |
12548 | ||
f07e9af3 | 12549 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
0d3031d9 | 12550 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) && |
1da177e4 | 12551 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { |
3600d918 | 12552 | u32 bmsr, adv_reg, tg3_ctrl, mask; |
1da177e4 LT |
12553 | |
12554 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
12555 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
12556 | (bmsr & BMSR_LSTATUS)) | |
12557 | goto skip_phy_reset; | |
6aa20a22 | 12558 | |
1da177e4 LT |
12559 | err = tg3_phy_reset(tp); |
12560 | if (err) | |
12561 | return err; | |
12562 | ||
12563 | adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL | | |
12564 | ADVERTISE_100HALF | ADVERTISE_100FULL | | |
12565 | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
12566 | tg3_ctrl = 0; | |
f07e9af3 | 12567 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
1da177e4 LT |
12568 | tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF | |
12569 | MII_TG3_CTRL_ADV_1000_FULL); | |
12570 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
12571 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
12572 | tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER | | |
12573 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
12574 | } | |
12575 | ||
3600d918 MC |
12576 | mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
12577 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
12578 | ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full); | |
12579 | if (!tg3_copper_is_advertising_all(tp, mask)) { | |
1da177e4 LT |
12580 | tg3_writephy(tp, MII_ADVERTISE, adv_reg); |
12581 | ||
f07e9af3 | 12582 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
1da177e4 LT |
12583 | tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl); |
12584 | ||
12585 | tg3_writephy(tp, MII_BMCR, | |
12586 | BMCR_ANENABLE | BMCR_ANRESTART); | |
12587 | } | |
12588 | tg3_phy_set_wirespeed(tp); | |
12589 | ||
12590 | tg3_writephy(tp, MII_ADVERTISE, adv_reg); | |
f07e9af3 | 12591 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
1da177e4 LT |
12592 | tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl); |
12593 | } | |
12594 | ||
12595 | skip_phy_reset: | |
79eb6904 | 12596 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
12597 | err = tg3_init_5401phy_dsp(tp); |
12598 | if (err) | |
12599 | return err; | |
1da177e4 | 12600 | |
1da177e4 LT |
12601 | err = tg3_init_5401phy_dsp(tp); |
12602 | } | |
12603 | ||
f07e9af3 | 12604 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
1da177e4 LT |
12605 | tp->link_config.advertising = |
12606 | (ADVERTISED_1000baseT_Half | | |
12607 | ADVERTISED_1000baseT_Full | | |
12608 | ADVERTISED_Autoneg | | |
12609 | ADVERTISED_FIBRE); | |
f07e9af3 | 12610 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) |
1da177e4 LT |
12611 | tp->link_config.advertising &= |
12612 | ~(ADVERTISED_1000baseT_Half | | |
12613 | ADVERTISED_1000baseT_Full); | |
12614 | ||
12615 | return err; | |
12616 | } | |
12617 | ||
184b8904 | 12618 | static void __devinit tg3_read_vpd(struct tg3 *tp) |
1da177e4 | 12619 | { |
a4a8bb15 | 12620 | u8 *vpd_data; |
4181b2c8 | 12621 | unsigned int block_end, rosize, len; |
184b8904 | 12622 | int j, i = 0; |
1b27777a | 12623 | u32 magic; |
1da177e4 | 12624 | |
df259d8c MC |
12625 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || |
12626 | tg3_nvram_read(tp, 0x0, &magic)) | |
a4a8bb15 MC |
12627 | goto out_no_vpd; |
12628 | ||
12629 | vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL); | |
12630 | if (!vpd_data) | |
12631 | goto out_no_vpd; | |
1da177e4 | 12632 | |
1820180b | 12633 | if (magic == TG3_EEPROM_MAGIC) { |
141518c9 | 12634 | for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) { |
1b27777a | 12635 | u32 tmp; |
1da177e4 | 12636 | |
6d348f2c MC |
12637 | /* The data is in little-endian format in NVRAM. |
12638 | * Use the big-endian read routines to preserve | |
12639 | * the byte order as it exists in NVRAM. | |
12640 | */ | |
141518c9 | 12641 | if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp)) |
1b27777a MC |
12642 | goto out_not_found; |
12643 | ||
6d348f2c | 12644 | memcpy(&vpd_data[i], &tmp, sizeof(tmp)); |
1b27777a MC |
12645 | } |
12646 | } else { | |
94c982bd | 12647 | ssize_t cnt; |
4181b2c8 | 12648 | unsigned int pos = 0; |
94c982bd MC |
12649 | |
12650 | for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) { | |
12651 | cnt = pci_read_vpd(tp->pdev, pos, | |
12652 | TG3_NVM_VPD_LEN - pos, | |
12653 | &vpd_data[pos]); | |
824f5f38 | 12654 | if (cnt == -ETIMEDOUT || cnt == -EINTR) |
94c982bd MC |
12655 | cnt = 0; |
12656 | else if (cnt < 0) | |
f49639e6 | 12657 | goto out_not_found; |
1b27777a | 12658 | } |
94c982bd MC |
12659 | if (pos != TG3_NVM_VPD_LEN) |
12660 | goto out_not_found; | |
1da177e4 LT |
12661 | } |
12662 | ||
4181b2c8 MC |
12663 | i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN, |
12664 | PCI_VPD_LRDT_RO_DATA); | |
12665 | if (i < 0) | |
12666 | goto out_not_found; | |
1da177e4 | 12667 | |
4181b2c8 MC |
12668 | rosize = pci_vpd_lrdt_size(&vpd_data[i]); |
12669 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize; | |
12670 | i += PCI_VPD_LRDT_TAG_SIZE; | |
1da177e4 | 12671 | |
4181b2c8 MC |
12672 | if (block_end > TG3_NVM_VPD_LEN) |
12673 | goto out_not_found; | |
af2c6a4a | 12674 | |
184b8904 MC |
12675 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
12676 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
12677 | if (j > 0) { | |
12678 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
12679 | ||
12680 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
12681 | if (j + len > block_end || len != 4 || | |
12682 | memcmp(&vpd_data[j], "1028", 4)) | |
12683 | goto partno; | |
12684 | ||
12685 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, | |
12686 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
12687 | if (j < 0) | |
12688 | goto partno; | |
12689 | ||
12690 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
12691 | ||
12692 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
12693 | if (j + len > block_end) | |
12694 | goto partno; | |
12695 | ||
12696 | memcpy(tp->fw_ver, &vpd_data[j], len); | |
12697 | strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1); | |
12698 | } | |
12699 | ||
12700 | partno: | |
4181b2c8 MC |
12701 | i = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
12702 | PCI_VPD_RO_KEYWORD_PARTNO); | |
12703 | if (i < 0) | |
12704 | goto out_not_found; | |
af2c6a4a | 12705 | |
4181b2c8 | 12706 | len = pci_vpd_info_field_size(&vpd_data[i]); |
1da177e4 | 12707 | |
4181b2c8 MC |
12708 | i += PCI_VPD_INFO_FLD_HDR_SIZE; |
12709 | if (len > TG3_BPN_SIZE || | |
12710 | (len + i) > TG3_NVM_VPD_LEN) | |
12711 | goto out_not_found; | |
1da177e4 | 12712 | |
4181b2c8 | 12713 | memcpy(tp->board_part_number, &vpd_data[i], len); |
1da177e4 | 12714 | |
1da177e4 | 12715 | out_not_found: |
a4a8bb15 | 12716 | kfree(vpd_data); |
37a949c5 | 12717 | if (tp->board_part_number[0]) |
a4a8bb15 MC |
12718 | return; |
12719 | ||
12720 | out_no_vpd: | |
37a949c5 MC |
12721 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { |
12722 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717) | |
12723 | strcpy(tp->board_part_number, "BCM5717"); | |
12724 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) | |
12725 | strcpy(tp->board_part_number, "BCM5718"); | |
12726 | else | |
12727 | goto nomatch; | |
12728 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { | |
12729 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) | |
12730 | strcpy(tp->board_part_number, "BCM57780"); | |
12731 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) | |
12732 | strcpy(tp->board_part_number, "BCM57760"); | |
12733 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) | |
12734 | strcpy(tp->board_part_number, "BCM57790"); | |
12735 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) | |
12736 | strcpy(tp->board_part_number, "BCM57788"); | |
12737 | else | |
12738 | goto nomatch; | |
12739 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
12740 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) | |
12741 | strcpy(tp->board_part_number, "BCM57761"); | |
12742 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) | |
12743 | strcpy(tp->board_part_number, "BCM57765"); | |
12744 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) | |
12745 | strcpy(tp->board_part_number, "BCM57781"); | |
12746 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) | |
12747 | strcpy(tp->board_part_number, "BCM57785"); | |
12748 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) | |
12749 | strcpy(tp->board_part_number, "BCM57791"); | |
12750 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
12751 | strcpy(tp->board_part_number, "BCM57795"); | |
12752 | else | |
12753 | goto nomatch; | |
12754 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
b5d3772c | 12755 | strcpy(tp->board_part_number, "BCM95906"); |
37a949c5 MC |
12756 | } else { |
12757 | nomatch: | |
b5d3772c | 12758 | strcpy(tp->board_part_number, "none"); |
37a949c5 | 12759 | } |
1da177e4 LT |
12760 | } |
12761 | ||
9c8a620e MC |
12762 | static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) |
12763 | { | |
12764 | u32 val; | |
12765 | ||
e4f34110 | 12766 | if (tg3_nvram_read(tp, offset, &val) || |
9c8a620e | 12767 | (val & 0xfc000000) != 0x0c000000 || |
e4f34110 | 12768 | tg3_nvram_read(tp, offset + 4, &val) || |
9c8a620e MC |
12769 | val != 0) |
12770 | return 0; | |
12771 | ||
12772 | return 1; | |
12773 | } | |
12774 | ||
acd9c119 MC |
12775 | static void __devinit tg3_read_bc_ver(struct tg3 *tp) |
12776 | { | |
ff3a7cb2 | 12777 | u32 val, offset, start, ver_offset; |
75f9936e | 12778 | int i, dst_off; |
ff3a7cb2 | 12779 | bool newver = false; |
acd9c119 MC |
12780 | |
12781 | if (tg3_nvram_read(tp, 0xc, &offset) || | |
12782 | tg3_nvram_read(tp, 0x4, &start)) | |
12783 | return; | |
12784 | ||
12785 | offset = tg3_nvram_logical_addr(tp, offset); | |
12786 | ||
ff3a7cb2 | 12787 | if (tg3_nvram_read(tp, offset, &val)) |
acd9c119 MC |
12788 | return; |
12789 | ||
ff3a7cb2 MC |
12790 | if ((val & 0xfc000000) == 0x0c000000) { |
12791 | if (tg3_nvram_read(tp, offset + 4, &val)) | |
acd9c119 MC |
12792 | return; |
12793 | ||
ff3a7cb2 MC |
12794 | if (val == 0) |
12795 | newver = true; | |
12796 | } | |
12797 | ||
75f9936e MC |
12798 | dst_off = strlen(tp->fw_ver); |
12799 | ||
ff3a7cb2 | 12800 | if (newver) { |
75f9936e MC |
12801 | if (TG3_VER_SIZE - dst_off < 16 || |
12802 | tg3_nvram_read(tp, offset + 8, &ver_offset)) | |
ff3a7cb2 MC |
12803 | return; |
12804 | ||
12805 | offset = offset + ver_offset - start; | |
12806 | for (i = 0; i < 16; i += 4) { | |
12807 | __be32 v; | |
12808 | if (tg3_nvram_read_be32(tp, offset + i, &v)) | |
12809 | return; | |
12810 | ||
75f9936e | 12811 | memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); |
ff3a7cb2 MC |
12812 | } |
12813 | } else { | |
12814 | u32 major, minor; | |
12815 | ||
12816 | if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) | |
12817 | return; | |
12818 | ||
12819 | major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >> | |
12820 | TG3_NVM_BCVER_MAJSFT; | |
12821 | minor = ver_offset & TG3_NVM_BCVER_MINMSK; | |
75f9936e MC |
12822 | snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, |
12823 | "v%d.%02d", major, minor); | |
acd9c119 MC |
12824 | } |
12825 | } | |
12826 | ||
a6f6cb1c MC |
12827 | static void __devinit tg3_read_hwsb_ver(struct tg3 *tp) |
12828 | { | |
12829 | u32 val, major, minor; | |
12830 | ||
12831 | /* Use native endian representation */ | |
12832 | if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) | |
12833 | return; | |
12834 | ||
12835 | major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >> | |
12836 | TG3_NVM_HWSB_CFG1_MAJSFT; | |
12837 | minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >> | |
12838 | TG3_NVM_HWSB_CFG1_MINSFT; | |
12839 | ||
12840 | snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); | |
12841 | } | |
12842 | ||
dfe00d7d MC |
12843 | static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) |
12844 | { | |
12845 | u32 offset, major, minor, build; | |
12846 | ||
75f9936e | 12847 | strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); |
dfe00d7d MC |
12848 | |
12849 | if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1) | |
12850 | return; | |
12851 | ||
12852 | switch (val & TG3_EEPROM_SB_REVISION_MASK) { | |
12853 | case TG3_EEPROM_SB_REVISION_0: | |
12854 | offset = TG3_EEPROM_SB_F1R0_EDH_OFF; | |
12855 | break; | |
12856 | case TG3_EEPROM_SB_REVISION_2: | |
12857 | offset = TG3_EEPROM_SB_F1R2_EDH_OFF; | |
12858 | break; | |
12859 | case TG3_EEPROM_SB_REVISION_3: | |
12860 | offset = TG3_EEPROM_SB_F1R3_EDH_OFF; | |
12861 | break; | |
a4153d40 MC |
12862 | case TG3_EEPROM_SB_REVISION_4: |
12863 | offset = TG3_EEPROM_SB_F1R4_EDH_OFF; | |
12864 | break; | |
12865 | case TG3_EEPROM_SB_REVISION_5: | |
12866 | offset = TG3_EEPROM_SB_F1R5_EDH_OFF; | |
12867 | break; | |
bba226ac MC |
12868 | case TG3_EEPROM_SB_REVISION_6: |
12869 | offset = TG3_EEPROM_SB_F1R6_EDH_OFF; | |
12870 | break; | |
dfe00d7d MC |
12871 | default: |
12872 | return; | |
12873 | } | |
12874 | ||
e4f34110 | 12875 | if (tg3_nvram_read(tp, offset, &val)) |
dfe00d7d MC |
12876 | return; |
12877 | ||
12878 | build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >> | |
12879 | TG3_EEPROM_SB_EDH_BLD_SHFT; | |
12880 | major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >> | |
12881 | TG3_EEPROM_SB_EDH_MAJ_SHFT; | |
12882 | minor = val & TG3_EEPROM_SB_EDH_MIN_MASK; | |
12883 | ||
12884 | if (minor > 99 || build > 26) | |
12885 | return; | |
12886 | ||
75f9936e MC |
12887 | offset = strlen(tp->fw_ver); |
12888 | snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, | |
12889 | " v%d.%02d", major, minor); | |
dfe00d7d MC |
12890 | |
12891 | if (build > 0) { | |
75f9936e MC |
12892 | offset = strlen(tp->fw_ver); |
12893 | if (offset < TG3_VER_SIZE - 1) | |
12894 | tp->fw_ver[offset] = 'a' + build - 1; | |
dfe00d7d MC |
12895 | } |
12896 | } | |
12897 | ||
acd9c119 | 12898 | static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp) |
c4e6575c MC |
12899 | { |
12900 | u32 val, offset, start; | |
acd9c119 | 12901 | int i, vlen; |
9c8a620e MC |
12902 | |
12903 | for (offset = TG3_NVM_DIR_START; | |
12904 | offset < TG3_NVM_DIR_END; | |
12905 | offset += TG3_NVM_DIRENT_SIZE) { | |
e4f34110 | 12906 | if (tg3_nvram_read(tp, offset, &val)) |
c4e6575c MC |
12907 | return; |
12908 | ||
9c8a620e MC |
12909 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) |
12910 | break; | |
12911 | } | |
12912 | ||
12913 | if (offset == TG3_NVM_DIR_END) | |
12914 | return; | |
12915 | ||
12916 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
12917 | start = 0x08000000; | |
e4f34110 | 12918 | else if (tg3_nvram_read(tp, offset - 4, &start)) |
9c8a620e MC |
12919 | return; |
12920 | ||
e4f34110 | 12921 | if (tg3_nvram_read(tp, offset + 4, &offset) || |
9c8a620e | 12922 | !tg3_fw_img_is_valid(tp, offset) || |
e4f34110 | 12923 | tg3_nvram_read(tp, offset + 8, &val)) |
9c8a620e MC |
12924 | return; |
12925 | ||
12926 | offset += val - start; | |
12927 | ||
acd9c119 | 12928 | vlen = strlen(tp->fw_ver); |
9c8a620e | 12929 | |
acd9c119 MC |
12930 | tp->fw_ver[vlen++] = ','; |
12931 | tp->fw_ver[vlen++] = ' '; | |
9c8a620e MC |
12932 | |
12933 | for (i = 0; i < 4; i++) { | |
a9dc529d MC |
12934 | __be32 v; |
12935 | if (tg3_nvram_read_be32(tp, offset, &v)) | |
c4e6575c MC |
12936 | return; |
12937 | ||
b9fc7dc5 | 12938 | offset += sizeof(v); |
c4e6575c | 12939 | |
acd9c119 MC |
12940 | if (vlen > TG3_VER_SIZE - sizeof(v)) { |
12941 | memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); | |
9c8a620e | 12942 | break; |
c4e6575c | 12943 | } |
9c8a620e | 12944 | |
acd9c119 MC |
12945 | memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); |
12946 | vlen += sizeof(v); | |
c4e6575c | 12947 | } |
acd9c119 MC |
12948 | } |
12949 | ||
7fd76445 MC |
12950 | static void __devinit tg3_read_dash_ver(struct tg3 *tp) |
12951 | { | |
12952 | int vlen; | |
12953 | u32 apedata; | |
ecc79648 | 12954 | char *fwtype; |
7fd76445 MC |
12955 | |
12956 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || | |
12957 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
12958 | return; | |
12959 | ||
12960 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
12961 | if (apedata != APE_SEG_SIG_MAGIC) | |
12962 | return; | |
12963 | ||
12964 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
12965 | if (!(apedata & APE_FW_STATUS_READY)) | |
12966 | return; | |
12967 | ||
12968 | apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); | |
12969 | ||
dc6d0744 MC |
12970 | if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) { |
12971 | tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI; | |
ecc79648 | 12972 | fwtype = "NCSI"; |
dc6d0744 | 12973 | } else { |
ecc79648 | 12974 | fwtype = "DASH"; |
dc6d0744 | 12975 | } |
ecc79648 | 12976 | |
7fd76445 MC |
12977 | vlen = strlen(tp->fw_ver); |
12978 | ||
ecc79648 MC |
12979 | snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", |
12980 | fwtype, | |
7fd76445 MC |
12981 | (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT, |
12982 | (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT, | |
12983 | (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT, | |
12984 | (apedata & APE_FW_VERSION_BLDMSK)); | |
12985 | } | |
12986 | ||
acd9c119 MC |
12987 | static void __devinit tg3_read_fw_ver(struct tg3 *tp) |
12988 | { | |
12989 | u32 val; | |
75f9936e | 12990 | bool vpd_vers = false; |
acd9c119 | 12991 | |
75f9936e MC |
12992 | if (tp->fw_ver[0] != 0) |
12993 | vpd_vers = true; | |
df259d8c | 12994 | |
75f9936e MC |
12995 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) { |
12996 | strcat(tp->fw_ver, "sb"); | |
df259d8c MC |
12997 | return; |
12998 | } | |
12999 | ||
acd9c119 MC |
13000 | if (tg3_nvram_read(tp, 0, &val)) |
13001 | return; | |
13002 | ||
13003 | if (val == TG3_EEPROM_MAGIC) | |
13004 | tg3_read_bc_ver(tp); | |
13005 | else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) | |
13006 | tg3_read_sb_ver(tp, val); | |
a6f6cb1c MC |
13007 | else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
13008 | tg3_read_hwsb_ver(tp); | |
acd9c119 MC |
13009 | else |
13010 | return; | |
13011 | ||
13012 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
75f9936e MC |
13013 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers) |
13014 | goto done; | |
acd9c119 MC |
13015 | |
13016 | tg3_read_mgmtfw_ver(tp); | |
9c8a620e | 13017 | |
75f9936e | 13018 | done: |
9c8a620e | 13019 | tp->fw_ver[TG3_VER_SIZE - 1] = 0; |
c4e6575c MC |
13020 | } |
13021 | ||
7544b097 MC |
13022 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *); |
13023 | ||
7fe876af ED |
13024 | static void inline vlan_features_add(struct net_device *dev, unsigned long flags) |
13025 | { | |
7fe876af | 13026 | dev->vlan_features |= flags; |
7fe876af ED |
13027 | } |
13028 | ||
7cb32cf2 MC |
13029 | static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) |
13030 | { | |
13031 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
13032 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
13033 | return 4096; | |
13034 | else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && | |
13035 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
13036 | return 1024; | |
13037 | else | |
13038 | return 512; | |
13039 | } | |
13040 | ||
895950c2 JP |
13041 | DEFINE_PCI_DEVICE_TABLE(write_reorder_chipsets) = { |
13042 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) }, | |
13043 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) }, | |
13044 | { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) }, | |
13045 | { }, | |
13046 | }; | |
13047 | ||
1da177e4 LT |
13048 | static int __devinit tg3_get_invariants(struct tg3 *tp) |
13049 | { | |
1da177e4 | 13050 | u32 misc_ctrl_reg; |
1da177e4 LT |
13051 | u32 pci_state_reg, grc_misc_cfg; |
13052 | u32 val; | |
13053 | u16 pci_cmd; | |
5e7dfd0f | 13054 | int err; |
1da177e4 | 13055 | |
1da177e4 LT |
13056 | /* Force memory write invalidate off. If we leave it on, |
13057 | * then on 5700_BX chips we have to enable a workaround. | |
13058 | * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary | |
13059 | * to match the cacheline size. The Broadcom driver have this | |
13060 | * workaround but turns MWI off all the times so never uses | |
13061 | * it. This seems to suggest that the workaround is insufficient. | |
13062 | */ | |
13063 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13064 | pci_cmd &= ~PCI_COMMAND_INVALIDATE; | |
13065 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13066 | ||
13067 | /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL | |
13068 | * has the register indirect write enable bit set before | |
13069 | * we try to access any of the MMIO registers. It is also | |
13070 | * critical that the PCI-X hw workaround situation is decided | |
13071 | * before that as well. | |
13072 | */ | |
13073 | pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13074 | &misc_ctrl_reg); | |
13075 | ||
13076 | tp->pci_chip_rev_id = (misc_ctrl_reg >> | |
13077 | MISC_HOST_CTRL_CHIPREV_SHIFT); | |
795d01c5 MC |
13078 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) { |
13079 | u32 prod_id_asic_rev; | |
13080 | ||
5001e2f6 MC |
13081 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || |
13082 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || | |
a50d0796 | 13083 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719) |
f6eb9b1f MC |
13084 | pci_read_config_dword(tp->pdev, |
13085 | TG3PCI_GEN2_PRODID_ASICREV, | |
13086 | &prod_id_asic_rev); | |
b703df6f MC |
13087 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || |
13088 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || | |
13089 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || | |
13090 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || | |
13091 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || | |
13092 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
13093 | pci_read_config_dword(tp->pdev, | |
13094 | TG3PCI_GEN15_PRODID_ASICREV, | |
13095 | &prod_id_asic_rev); | |
f6eb9b1f MC |
13096 | else |
13097 | pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV, | |
13098 | &prod_id_asic_rev); | |
13099 | ||
321d32a0 | 13100 | tp->pci_chip_rev_id = prod_id_asic_rev; |
795d01c5 | 13101 | } |
1da177e4 | 13102 | |
ff645bec MC |
13103 | /* Wrong chip ID in 5752 A0. This code can be removed later |
13104 | * as A0 is not in production. | |
13105 | */ | |
13106 | if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) | |
13107 | tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; | |
13108 | ||
6892914f MC |
13109 | /* If we have 5702/03 A1 or A2 on certain ICH chipsets, |
13110 | * we need to disable memory and use config. cycles | |
13111 | * only to access all registers. The 5702/03 chips | |
13112 | * can mistakenly decode the special cycles from the | |
13113 | * ICH chipsets as memory write cycles, causing corruption | |
13114 | * of register and memory space. Only certain ICH bridges | |
13115 | * will drive special cycles with non-zero data during the | |
13116 | * address phase which can fall within the 5703's address | |
13117 | * range. This is not an ICH bug as the PCI spec allows | |
13118 | * non-zero address during special cycles. However, only | |
13119 | * these ICH bridges are known to drive non-zero addresses | |
13120 | * during special cycles. | |
13121 | * | |
13122 | * Since special cycles do not cross PCI bridges, we only | |
13123 | * enable this workaround if the 5703 is on the secondary | |
13124 | * bus of these ICH bridges. | |
13125 | */ | |
13126 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) || | |
13127 | (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) { | |
13128 | static struct tg3_dev_id { | |
13129 | u32 vendor; | |
13130 | u32 device; | |
13131 | u32 rev; | |
13132 | } ich_chipsets[] = { | |
13133 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8, | |
13134 | PCI_ANY_ID }, | |
13135 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8, | |
13136 | PCI_ANY_ID }, | |
13137 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11, | |
13138 | 0xa }, | |
13139 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6, | |
13140 | PCI_ANY_ID }, | |
13141 | { }, | |
13142 | }; | |
13143 | struct tg3_dev_id *pci_id = &ich_chipsets[0]; | |
13144 | struct pci_dev *bridge = NULL; | |
13145 | ||
13146 | while (pci_id->vendor != 0) { | |
13147 | bridge = pci_get_device(pci_id->vendor, pci_id->device, | |
13148 | bridge); | |
13149 | if (!bridge) { | |
13150 | pci_id++; | |
13151 | continue; | |
13152 | } | |
13153 | if (pci_id->rev != PCI_ANY_ID) { | |
44c10138 | 13154 | if (bridge->revision > pci_id->rev) |
6892914f MC |
13155 | continue; |
13156 | } | |
13157 | if (bridge->subordinate && | |
13158 | (bridge->subordinate->number == | |
13159 | tp->pdev->bus->number)) { | |
13160 | ||
13161 | tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND; | |
13162 | pci_dev_put(bridge); | |
13163 | break; | |
13164 | } | |
13165 | } | |
13166 | } | |
13167 | ||
41588ba1 MC |
13168 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { |
13169 | static struct tg3_dev_id { | |
13170 | u32 vendor; | |
13171 | u32 device; | |
13172 | } bridge_chipsets[] = { | |
13173 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 }, | |
13174 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 }, | |
13175 | { }, | |
13176 | }; | |
13177 | struct tg3_dev_id *pci_id = &bridge_chipsets[0]; | |
13178 | struct pci_dev *bridge = NULL; | |
13179 | ||
13180 | while (pci_id->vendor != 0) { | |
13181 | bridge = pci_get_device(pci_id->vendor, | |
13182 | pci_id->device, | |
13183 | bridge); | |
13184 | if (!bridge) { | |
13185 | pci_id++; | |
13186 | continue; | |
13187 | } | |
13188 | if (bridge->subordinate && | |
13189 | (bridge->subordinate->number <= | |
13190 | tp->pdev->bus->number) && | |
13191 | (bridge->subordinate->subordinate >= | |
13192 | tp->pdev->bus->number)) { | |
13193 | tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG; | |
13194 | pci_dev_put(bridge); | |
13195 | break; | |
13196 | } | |
13197 | } | |
13198 | } | |
13199 | ||
4a29cc2e MC |
13200 | /* The EPB bridge inside 5714, 5715, and 5780 cannot support |
13201 | * DMA addresses > 40-bit. This bridge may have other additional | |
13202 | * 57xx devices behind it in some 4-port NIC designs for example. | |
13203 | * Any tg3 device found behind the bridge will also need the 40-bit | |
13204 | * DMA workaround. | |
13205 | */ | |
a4e2b347 MC |
13206 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || |
13207 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
13208 | tp->tg3_flags2 |= TG3_FLG2_5780_CLASS; | |
4a29cc2e | 13209 | tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG; |
4cf78e4f | 13210 | tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI); |
859a5887 | 13211 | } else { |
4a29cc2e MC |
13212 | struct pci_dev *bridge = NULL; |
13213 | ||
13214 | do { | |
13215 | bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, | |
13216 | PCI_DEVICE_ID_SERVERWORKS_EPB, | |
13217 | bridge); | |
13218 | if (bridge && bridge->subordinate && | |
13219 | (bridge->subordinate->number <= | |
13220 | tp->pdev->bus->number) && | |
13221 | (bridge->subordinate->subordinate >= | |
13222 | tp->pdev->bus->number)) { | |
13223 | tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG; | |
13224 | pci_dev_put(bridge); | |
13225 | break; | |
13226 | } | |
13227 | } while (bridge); | |
13228 | } | |
4cf78e4f | 13229 | |
1da177e4 LT |
13230 | /* Initialize misc host control in PCI block. */ |
13231 | tp->misc_host_ctrl |= (misc_ctrl_reg & | |
13232 | MISC_HOST_CTRL_CHIPREV); | |
13233 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13234 | tp->misc_host_ctrl); | |
13235 | ||
f6eb9b1f MC |
13236 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
13237 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 || | |
13238 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) | |
7544b097 MC |
13239 | tp->pdev_peer = tg3_find_peer(tp); |
13240 | ||
c885e824 MC |
13241 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
13242 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
13243 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
13244 | tp->tg3_flags3 |= TG3_FLG3_5717_PLUS; | |
13245 | ||
321d32a0 MC |
13246 | /* Intentionally exclude ASIC_REV_5906 */ |
13247 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
d9ab5ad1 | 13248 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
d30cdd28 | 13249 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
9936bcf6 | 13250 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
57e6983c | 13251 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
f6eb9b1f | 13252 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
c885e824 | 13253 | (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) |
321d32a0 MC |
13254 | tp->tg3_flags3 |= TG3_FLG3_5755_PLUS; |
13255 | ||
13256 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
13257 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
b5d3772c | 13258 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || |
321d32a0 | 13259 | (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || |
a4e2b347 | 13260 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) |
6708e5cc JL |
13261 | tp->tg3_flags2 |= TG3_FLG2_5750_PLUS; |
13262 | ||
1b440c56 JL |
13263 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) || |
13264 | (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) | |
13265 | tp->tg3_flags2 |= TG3_FLG2_5705_PLUS; | |
13266 | ||
027455ad MC |
13267 | /* 5700 B0 chips do not support checksumming correctly due |
13268 | * to hardware bugs. | |
13269 | */ | |
13270 | if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0) | |
13271 | tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS; | |
13272 | else { | |
7fe876af ED |
13273 | unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO; |
13274 | ||
027455ad | 13275 | tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS; |
027455ad | 13276 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
7fe876af ED |
13277 | features |= NETIF_F_IPV6_CSUM; |
13278 | tp->dev->features |= features; | |
13279 | vlan_features_add(tp->dev, features); | |
027455ad MC |
13280 | } |
13281 | ||
507399f1 | 13282 | /* Determine TSO capabilities */ |
4d163b75 MC |
13283 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) |
13284 | ; /* Do nothing. HW bug. */ | |
13285 | else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) | |
e849cdc3 MC |
13286 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3; |
13287 | else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || | |
13288 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
507399f1 MC |
13289 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2; |
13290 | else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { | |
13291 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG; | |
13292 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 && | |
13293 | tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2) | |
13294 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG; | |
13295 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
13296 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
13297 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
13298 | tp->tg3_flags2 |= TG3_FLG2_TSO_BUG; | |
13299 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) | |
13300 | tp->fw_needed = FIRMWARE_TG3TSO5; | |
13301 | else | |
13302 | tp->fw_needed = FIRMWARE_TG3TSO; | |
13303 | } | |
13304 | ||
13305 | tp->irq_max = 1; | |
13306 | ||
5a6f3074 | 13307 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { |
7544b097 MC |
13308 | tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI; |
13309 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX || | |
13310 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX || | |
13311 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 && | |
13312 | tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 && | |
13313 | tp->pdev_peer == tp->pdev)) | |
13314 | tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI; | |
13315 | ||
321d32a0 | 13316 | if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || |
b5d3772c | 13317 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
fcfa0a32 | 13318 | tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI; |
52c0fd83 | 13319 | } |
4f125f42 | 13320 | |
c885e824 | 13321 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) { |
507399f1 MC |
13322 | tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX; |
13323 | tp->irq_max = TG3_IRQ_MAX_VECS; | |
13324 | } | |
f6eb9b1f | 13325 | } |
0e1406dd | 13326 | |
615774fe | 13327 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
a50d0796 | 13328 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
615774fe MC |
13329 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
13330 | tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG; | |
13331 | else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) { | |
13332 | tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG; | |
13333 | tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG; | |
0e1406dd | 13334 | } |
f6eb9b1f | 13335 | |
4d163b75 MC |
13336 | if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) && |
13337 | tp->pci_chip_rev_id != CHIPREV_ID_5719_A0) | |
b703df6f MC |
13338 | tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG; |
13339 | ||
f51f3562 | 13340 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || |
c6cdf436 MC |
13341 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || |
13342 | (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG)) | |
8f666b07 | 13343 | tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE; |
0f893dc6 | 13344 | |
52f4490c MC |
13345 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, |
13346 | &pci_state_reg); | |
13347 | ||
5e7dfd0f MC |
13348 | tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP); |
13349 | if (tp->pcie_cap != 0) { | |
13350 | u16 lnkctl; | |
13351 | ||
1da177e4 | 13352 | tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; |
5f5c51e3 | 13353 | |
cf79003d | 13354 | tp->pcie_readrq = 4096; |
b4495ed8 MC |
13355 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) |
13356 | tp->pcie_readrq = 2048; | |
cf79003d MC |
13357 | |
13358 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); | |
5f5c51e3 | 13359 | |
5e7dfd0f MC |
13360 | pci_read_config_word(tp->pdev, |
13361 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
13362 | &lnkctl); | |
13363 | if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { | |
13364 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
c7835a77 | 13365 | tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2; |
5e7dfd0f | 13366 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 | 13367 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
9cf74ebb MC |
13368 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 || |
13369 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A1) | |
5e7dfd0f | 13370 | tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG; |
614b0590 MC |
13371 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) { |
13372 | tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN; | |
c7835a77 | 13373 | } |
52f4490c | 13374 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
fcb389df | 13375 | tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; |
52f4490c MC |
13376 | } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || |
13377 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { | |
13378 | tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); | |
13379 | if (!tp->pcix_cap) { | |
2445e461 MC |
13380 | dev_err(&tp->pdev->dev, |
13381 | "Cannot find PCI-X capability, aborting\n"); | |
52f4490c MC |
13382 | return -EIO; |
13383 | } | |
13384 | ||
13385 | if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE)) | |
13386 | tp->tg3_flags |= TG3_FLAG_PCIX_MODE; | |
13387 | } | |
1da177e4 | 13388 | |
399de50b MC |
13389 | /* If we have an AMD 762 or VIA K8T800 chipset, write |
13390 | * reordering to the mailbox registers done by the host | |
13391 | * controller can cause major troubles. We read back from | |
13392 | * every mailbox register write to force the writes to be | |
13393 | * posted to the chip in order. | |
13394 | */ | |
13395 | if (pci_dev_present(write_reorder_chipsets) && | |
13396 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
13397 | tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; | |
13398 | ||
69fc4053 MC |
13399 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, |
13400 | &tp->pci_cacheline_sz); | |
13401 | pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
13402 | &tp->pci_lat_timer); | |
1da177e4 LT |
13403 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && |
13404 | tp->pci_lat_timer < 64) { | |
13405 | tp->pci_lat_timer = 64; | |
69fc4053 MC |
13406 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, |
13407 | tp->pci_lat_timer); | |
1da177e4 LT |
13408 | } |
13409 | ||
52f4490c MC |
13410 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { |
13411 | /* 5700 BX chips need to have their TX producer index | |
13412 | * mailboxes written twice to workaround a bug. | |
13413 | */ | |
13414 | tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG; | |
1da177e4 | 13415 | |
52f4490c | 13416 | /* If we are in PCI-X mode, enable register write workaround. |
1da177e4 LT |
13417 | * |
13418 | * The workaround is to use indirect register accesses | |
13419 | * for all chip writes not to mailbox registers. | |
13420 | */ | |
52f4490c | 13421 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { |
1da177e4 | 13422 | u32 pm_reg; |
1da177e4 LT |
13423 | |
13424 | tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG; | |
13425 | ||
13426 | /* The chip can have it's power management PCI config | |
13427 | * space registers clobbered due to this bug. | |
13428 | * So explicitly force the chip into D0 here. | |
13429 | */ | |
9974a356 MC |
13430 | pci_read_config_dword(tp->pdev, |
13431 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
13432 | &pm_reg); |
13433 | pm_reg &= ~PCI_PM_CTRL_STATE_MASK; | |
13434 | pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */; | |
9974a356 MC |
13435 | pci_write_config_dword(tp->pdev, |
13436 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
13437 | pm_reg); |
13438 | ||
13439 | /* Also, force SERR#/PERR# in PCI command. */ | |
13440 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13441 | pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; | |
13442 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13443 | } | |
13444 | } | |
13445 | ||
1da177e4 LT |
13446 | if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) |
13447 | tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED; | |
13448 | if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) | |
13449 | tp->tg3_flags |= TG3_FLAG_PCI_32BIT; | |
13450 | ||
13451 | /* Chip-specific fixup from Broadcom driver */ | |
13452 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && | |
13453 | (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) { | |
13454 | pci_state_reg |= PCISTATE_RETRY_SAME_DMA; | |
13455 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); | |
13456 | } | |
13457 | ||
1ee582d8 | 13458 | /* Default fast path register access methods */ |
20094930 | 13459 | tp->read32 = tg3_read32; |
1ee582d8 | 13460 | tp->write32 = tg3_write32; |
09ee929c | 13461 | tp->read32_mbox = tg3_read32; |
20094930 | 13462 | tp->write32_mbox = tg3_write32; |
1ee582d8 MC |
13463 | tp->write32_tx_mbox = tg3_write32; |
13464 | tp->write32_rx_mbox = tg3_write32; | |
13465 | ||
13466 | /* Various workaround register access methods */ | |
13467 | if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) | |
13468 | tp->write32 = tg3_write_indirect_reg32; | |
98efd8a6 MC |
13469 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || |
13470 | ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && | |
13471 | tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) { | |
13472 | /* | |
13473 | * Back to back register writes can cause problems on these | |
13474 | * chips, the workaround is to read back all reg writes | |
13475 | * except those to mailbox regs. | |
13476 | * | |
13477 | * See tg3_write_indirect_reg32(). | |
13478 | */ | |
1ee582d8 | 13479 | tp->write32 = tg3_write_flush_reg32; |
98efd8a6 MC |
13480 | } |
13481 | ||
1ee582d8 MC |
13482 | if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) || |
13483 | (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) { | |
13484 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | |
13485 | if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) | |
13486 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
13487 | } | |
20094930 | 13488 | |
6892914f MC |
13489 | if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) { |
13490 | tp->read32 = tg3_read_indirect_reg32; | |
13491 | tp->write32 = tg3_write_indirect_reg32; | |
13492 | tp->read32_mbox = tg3_read_indirect_mbox; | |
13493 | tp->write32_mbox = tg3_write_indirect_mbox; | |
13494 | tp->write32_tx_mbox = tg3_write_indirect_mbox; | |
13495 | tp->write32_rx_mbox = tg3_write_indirect_mbox; | |
13496 | ||
13497 | iounmap(tp->regs); | |
22abe310 | 13498 | tp->regs = NULL; |
6892914f MC |
13499 | |
13500 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13501 | pci_cmd &= ~PCI_COMMAND_MEMORY; | |
13502 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13503 | } | |
b5d3772c MC |
13504 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
13505 | tp->read32_mbox = tg3_read32_mbox_5906; | |
13506 | tp->write32_mbox = tg3_write32_mbox_5906; | |
13507 | tp->write32_tx_mbox = tg3_write32_mbox_5906; | |
13508 | tp->write32_rx_mbox = tg3_write32_mbox_5906; | |
13509 | } | |
6892914f | 13510 | |
bbadf503 MC |
13511 | if (tp->write32 == tg3_write_indirect_reg32 || |
13512 | ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) && | |
13513 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
f49639e6 | 13514 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) |
bbadf503 MC |
13515 | tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG; |
13516 | ||
7d0c41ef | 13517 | /* Get eeprom hw config before calling tg3_set_power_state(). |
9d26e213 | 13518 | * In particular, the TG3_FLG2_IS_NIC flag must be |
7d0c41ef MC |
13519 | * determined before calling tg3_set_power_state() so that |
13520 | * we know whether or not to switch out of Vaux power. | |
13521 | * When the flag is set, it means that GPIO1 is used for eeprom | |
13522 | * write protect and also implies that it is a LOM where GPIOs | |
13523 | * are not used to switch power. | |
6aa20a22 | 13524 | */ |
7d0c41ef MC |
13525 | tg3_get_eeprom_hw_cfg(tp); |
13526 | ||
0d3031d9 MC |
13527 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
13528 | /* Allow reads and writes to the | |
13529 | * APE register and memory space. | |
13530 | */ | |
13531 | pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
13532 | PCISTATE_ALLOW_APE_SHMEM_WR | |
13533 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
13534 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, |
13535 | pci_state_reg); | |
13536 | } | |
13537 | ||
9936bcf6 | 13538 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
57e6983c | 13539 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
321d32a0 | 13540 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
f6eb9b1f | 13541 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
c885e824 | 13542 | (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) |
d30cdd28 MC |
13543 | tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT; |
13544 | ||
c866b7ea | 13545 | /* Set up tp->grc_local_ctrl before calling tg_power_up(). |
314fba34 MC |
13546 | * GPIO1 driven high will bring 5700's external PHY out of reset. |
13547 | * It is also used as eeprom write protect on LOMs. | |
13548 | */ | |
13549 | tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; | |
13550 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || | |
13551 | (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) | |
13552 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | | |
13553 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
3e7d83bc MC |
13554 | /* Unused GPIO3 must be driven as output on 5752 because there |
13555 | * are no pull-up resistors on unused GPIO pins. | |
13556 | */ | |
13557 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
13558 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
314fba34 | 13559 | |
321d32a0 | 13560 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
cb4ed1fd MC |
13561 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
13562 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
af36e6b6 MC |
13563 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; |
13564 | ||
8d519ab2 MC |
13565 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
13566 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
5f0c4a3c MC |
13567 | /* Turn off the debug UART. */ |
13568 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; | |
13569 | if (tp->tg3_flags2 & TG3_FLG2_IS_NIC) | |
13570 | /* Keep VMain power. */ | |
13571 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
13572 | GRC_LCLCTRL_GPIO_OUTPUT0; | |
13573 | } | |
13574 | ||
1da177e4 | 13575 | /* Force the chip into D0. */ |
c866b7ea | 13576 | err = tg3_power_up(tp); |
1da177e4 | 13577 | if (err) { |
2445e461 | 13578 | dev_err(&tp->pdev->dev, "Transition to D0 failed\n"); |
1da177e4 LT |
13579 | return err; |
13580 | } | |
13581 | ||
1da177e4 LT |
13582 | /* Derive initial jumbo mode from MTU assigned in |
13583 | * ether_setup() via the alloc_etherdev() call | |
13584 | */ | |
0f893dc6 | 13585 | if (tp->dev->mtu > ETH_DATA_LEN && |
a4e2b347 | 13586 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) |
0f893dc6 | 13587 | tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE; |
1da177e4 LT |
13588 | |
13589 | /* Determine WakeOnLan speed to use. */ | |
13590 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
13591 | tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
13592 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 || | |
13593 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) { | |
13594 | tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB); | |
13595 | } else { | |
13596 | tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB; | |
13597 | } | |
13598 | ||
7f97a4bd | 13599 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
f07e9af3 | 13600 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
7f97a4bd | 13601 | |
1da177e4 LT |
13602 | /* A few boards don't want Ethernet@WireSpeed phy feature */ |
13603 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || | |
13604 | ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
13605 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && | |
747e8f8b | 13606 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) || |
f07e9af3 MC |
13607 | (tp->phy_flags & TG3_PHYFLG_IS_FET) || |
13608 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
13609 | tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; | |
1da177e4 LT |
13610 | |
13611 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX || | |
13612 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX) | |
f07e9af3 | 13613 | tp->phy_flags |= TG3_PHYFLG_ADC_BUG; |
1da177e4 | 13614 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) |
f07e9af3 | 13615 | tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; |
1da177e4 | 13616 | |
321d32a0 | 13617 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && |
f07e9af3 | 13618 | !(tp->phy_flags & TG3_PHYFLG_IS_FET) && |
321d32a0 | 13619 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
f6eb9b1f | 13620 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 && |
c885e824 | 13621 | !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) { |
c424cb24 | 13622 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
d30cdd28 | 13623 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
9936bcf6 MC |
13624 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
13625 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { | |
d4011ada MC |
13626 | if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && |
13627 | tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) | |
f07e9af3 | 13628 | tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; |
c1d2a196 | 13629 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) |
f07e9af3 | 13630 | tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; |
321d32a0 | 13631 | } else |
f07e9af3 | 13632 | tp->phy_flags |= TG3_PHYFLG_BER_BUG; |
c424cb24 | 13633 | } |
1da177e4 | 13634 | |
b2a5c19c MC |
13635 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
13636 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
13637 | tp->phy_otp = tg3_read_otp_phycfg(tp); | |
13638 | if (tp->phy_otp == 0) | |
13639 | tp->phy_otp = TG3_OTP_DEFAULT; | |
13640 | } | |
13641 | ||
f51f3562 | 13642 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) |
8ef21428 MC |
13643 | tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; |
13644 | else | |
13645 | tp->mi_mode = MAC_MI_MODE_BASE; | |
13646 | ||
1da177e4 | 13647 | tp->coalesce_mode = 0; |
1da177e4 LT |
13648 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && |
13649 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) | |
13650 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; | |
13651 | ||
321d32a0 MC |
13652 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
13653 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
57e6983c MC |
13654 | tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB; |
13655 | ||
158d7abd MC |
13656 | err = tg3_mdio_init(tp); |
13657 | if (err) | |
13658 | return err; | |
1da177e4 LT |
13659 | |
13660 | /* Initialize data/descriptor byte/word swapping. */ | |
13661 | val = tr32(GRC_MODE); | |
13662 | val &= GRC_MODE_HOST_STACKUP; | |
13663 | tw32(GRC_MODE, val | tp->grc_mode); | |
13664 | ||
13665 | tg3_switch_clocks(tp); | |
13666 | ||
13667 | /* Clear this out for sanity. */ | |
13668 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
13669 | ||
13670 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
13671 | &pci_state_reg); | |
13672 | if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && | |
13673 | (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) { | |
13674 | u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl); | |
13675 | ||
13676 | if (chiprevid == CHIPREV_ID_5701_A0 || | |
13677 | chiprevid == CHIPREV_ID_5701_B0 || | |
13678 | chiprevid == CHIPREV_ID_5701_B2 || | |
13679 | chiprevid == CHIPREV_ID_5701_B5) { | |
13680 | void __iomem *sram_base; | |
13681 | ||
13682 | /* Write some dummy words into the SRAM status block | |
13683 | * area, see if it reads back correctly. If the return | |
13684 | * value is bad, force enable the PCIX workaround. | |
13685 | */ | |
13686 | sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; | |
13687 | ||
13688 | writel(0x00000000, sram_base); | |
13689 | writel(0x00000000, sram_base + 4); | |
13690 | writel(0xffffffff, sram_base + 4); | |
13691 | if (readl(sram_base) != 0x00000000) | |
13692 | tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG; | |
13693 | } | |
13694 | } | |
13695 | ||
13696 | udelay(50); | |
13697 | tg3_nvram_init(tp); | |
13698 | ||
13699 | grc_misc_cfg = tr32(GRC_MISC_CFG); | |
13700 | grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; | |
13701 | ||
1da177e4 LT |
13702 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
13703 | (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 || | |
13704 | grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) | |
13705 | tp->tg3_flags2 |= TG3_FLG2_IS_5788; | |
13706 | ||
fac9b83e DM |
13707 | if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) && |
13708 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)) | |
13709 | tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS; | |
13710 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) { | |
13711 | tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | | |
13712 | HOSTCC_MODE_CLRTICK_TXBD); | |
13713 | ||
13714 | tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; | |
13715 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13716 | tp->misc_host_ctrl); | |
13717 | } | |
13718 | ||
3bda1258 MC |
13719 | /* Preserve the APE MAC_MODE bits */ |
13720 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
d2394e6b | 13721 | tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; |
3bda1258 MC |
13722 | else |
13723 | tp->mac_mode = TG3_DEF_MAC_MODE; | |
13724 | ||
1da177e4 LT |
13725 | /* these are limited to 10/100 only */ |
13726 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | |
13727 | (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || | |
13728 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
13729 | tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
13730 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 || | |
13731 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 || | |
13732 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) || | |
13733 | (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
13734 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F || | |
676917d4 MC |
13735 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F || |
13736 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) || | |
321d32a0 | 13737 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 || |
d1101142 MC |
13738 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || |
13739 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || | |
f07e9af3 MC |
13740 | (tp->phy_flags & TG3_PHYFLG_IS_FET)) |
13741 | tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; | |
1da177e4 LT |
13742 | |
13743 | err = tg3_phy_probe(tp); | |
13744 | if (err) { | |
2445e461 | 13745 | dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); |
1da177e4 | 13746 | /* ... but do not return immediately ... */ |
b02fd9e3 | 13747 | tg3_mdio_fini(tp); |
1da177e4 LT |
13748 | } |
13749 | ||
184b8904 | 13750 | tg3_read_vpd(tp); |
c4e6575c | 13751 | tg3_read_fw_ver(tp); |
1da177e4 | 13752 | |
f07e9af3 MC |
13753 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
13754 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; | |
1da177e4 LT |
13755 | } else { |
13756 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
f07e9af3 | 13757 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 | 13758 | else |
f07e9af3 | 13759 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 LT |
13760 | } |
13761 | ||
13762 | /* 5700 {AX,BX} chips have a broken status block link | |
13763 | * change bit implementation, so we must use the | |
13764 | * status register in those cases. | |
13765 | */ | |
13766 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
13767 | tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG; | |
13768 | else | |
13769 | tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG; | |
13770 | ||
13771 | /* The led_ctrl is set during tg3_phy_probe, here we might | |
13772 | * have to force the link status polling mechanism based | |
13773 | * upon subsystem IDs. | |
13774 | */ | |
13775 | if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && | |
007a880d | 13776 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
f07e9af3 MC |
13777 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
13778 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; | |
13779 | tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG; | |
1da177e4 LT |
13780 | } |
13781 | ||
13782 | /* For all SERDES we poll the MAC status register. */ | |
f07e9af3 | 13783 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
13784 | tp->tg3_flags |= TG3_FLAG_POLL_SERDES; |
13785 | else | |
13786 | tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES; | |
13787 | ||
bf933c80 | 13788 | tp->rx_offset = NET_IP_ALIGN; |
d2757fc4 | 13789 | tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; |
1da177e4 | 13790 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
d2757fc4 | 13791 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) { |
bf933c80 | 13792 | tp->rx_offset = 0; |
d2757fc4 | 13793 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
9dc7a113 | 13794 | tp->rx_copy_thresh = ~(u16)0; |
d2757fc4 MC |
13795 | #endif |
13796 | } | |
1da177e4 | 13797 | |
2c49a44d MC |
13798 | tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; |
13799 | tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; | |
7cb32cf2 MC |
13800 | tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; |
13801 | ||
2c49a44d | 13802 | tp->rx_std_max_post = tp->rx_std_ring_mask + 1; |
f92905de MC |
13803 | |
13804 | /* Increment the rx prod index on the rx std ring by at most | |
13805 | * 8 for these chips to workaround hw errata. | |
13806 | */ | |
13807 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
13808 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
13809 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
13810 | tp->rx_std_max_post = 8; | |
13811 | ||
8ed5d97e MC |
13812 | if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) |
13813 | tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & | |
13814 | PCIE_PWR_MGMT_L1_THRESH_MSK; | |
13815 | ||
1da177e4 LT |
13816 | return err; |
13817 | } | |
13818 | ||
49b6e95f | 13819 | #ifdef CONFIG_SPARC |
1da177e4 LT |
13820 | static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp) |
13821 | { | |
13822 | struct net_device *dev = tp->dev; | |
13823 | struct pci_dev *pdev = tp->pdev; | |
49b6e95f | 13824 | struct device_node *dp = pci_device_to_OF_node(pdev); |
374d4cac | 13825 | const unsigned char *addr; |
49b6e95f DM |
13826 | int len; |
13827 | ||
13828 | addr = of_get_property(dp, "local-mac-address", &len); | |
13829 | if (addr && len == 6) { | |
13830 | memcpy(dev->dev_addr, addr, 6); | |
13831 | memcpy(dev->perm_addr, dev->dev_addr, 6); | |
13832 | return 0; | |
1da177e4 LT |
13833 | } |
13834 | return -ENODEV; | |
13835 | } | |
13836 | ||
13837 | static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp) | |
13838 | { | |
13839 | struct net_device *dev = tp->dev; | |
13840 | ||
13841 | memcpy(dev->dev_addr, idprom->id_ethaddr, 6); | |
2ff43697 | 13842 | memcpy(dev->perm_addr, idprom->id_ethaddr, 6); |
1da177e4 LT |
13843 | return 0; |
13844 | } | |
13845 | #endif | |
13846 | ||
13847 | static int __devinit tg3_get_device_address(struct tg3 *tp) | |
13848 | { | |
13849 | struct net_device *dev = tp->dev; | |
13850 | u32 hi, lo, mac_offset; | |
008652b3 | 13851 | int addr_ok = 0; |
1da177e4 | 13852 | |
49b6e95f | 13853 | #ifdef CONFIG_SPARC |
1da177e4 LT |
13854 | if (!tg3_get_macaddr_sparc(tp)) |
13855 | return 0; | |
13856 | #endif | |
13857 | ||
13858 | mac_offset = 0x7c; | |
f49639e6 | 13859 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || |
a4e2b347 | 13860 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
1da177e4 LT |
13861 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) |
13862 | mac_offset = 0xcc; | |
13863 | if (tg3_nvram_lock(tp)) | |
13864 | tw32_f(NVRAM_CMD, NVRAM_CMD_RESET); | |
13865 | else | |
13866 | tg3_nvram_unlock(tp); | |
a50d0796 MC |
13867 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
13868 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) { | |
13869 | if (PCI_FUNC(tp->pdev->devfn) & 1) | |
a1b950d5 | 13870 | mac_offset = 0xcc; |
a50d0796 MC |
13871 | if (PCI_FUNC(tp->pdev->devfn) > 1) |
13872 | mac_offset += 0x18c; | |
a1b950d5 | 13873 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
b5d3772c | 13874 | mac_offset = 0x10; |
1da177e4 LT |
13875 | |
13876 | /* First try to get it from MAC address mailbox. */ | |
13877 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); | |
13878 | if ((hi >> 16) == 0x484b) { | |
13879 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
13880 | dev->dev_addr[1] = (hi >> 0) & 0xff; | |
13881 | ||
13882 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); | |
13883 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
13884 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
13885 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
13886 | dev->dev_addr[5] = (lo >> 0) & 0xff; | |
1da177e4 | 13887 | |
008652b3 MC |
13888 | /* Some old bootcode may report a 0 MAC address in SRAM */ |
13889 | addr_ok = is_valid_ether_addr(&dev->dev_addr[0]); | |
13890 | } | |
13891 | if (!addr_ok) { | |
13892 | /* Next, try NVRAM. */ | |
df259d8c MC |
13893 | if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) && |
13894 | !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && | |
6d348f2c | 13895 | !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { |
62cedd11 MC |
13896 | memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2); |
13897 | memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo)); | |
008652b3 MC |
13898 | } |
13899 | /* Finally just fetch it out of the MAC control regs. */ | |
13900 | else { | |
13901 | hi = tr32(MAC_ADDR_0_HIGH); | |
13902 | lo = tr32(MAC_ADDR_0_LOW); | |
13903 | ||
13904 | dev->dev_addr[5] = lo & 0xff; | |
13905 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
13906 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
13907 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
13908 | dev->dev_addr[1] = hi & 0xff; | |
13909 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
13910 | } | |
1da177e4 LT |
13911 | } |
13912 | ||
13913 | if (!is_valid_ether_addr(&dev->dev_addr[0])) { | |
7582a335 | 13914 | #ifdef CONFIG_SPARC |
1da177e4 LT |
13915 | if (!tg3_get_default_macaddr_sparc(tp)) |
13916 | return 0; | |
13917 | #endif | |
13918 | return -EINVAL; | |
13919 | } | |
2ff43697 | 13920 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 LT |
13921 | return 0; |
13922 | } | |
13923 | ||
59e6b434 DM |
13924 | #define BOUNDARY_SINGLE_CACHELINE 1 |
13925 | #define BOUNDARY_MULTI_CACHELINE 2 | |
13926 | ||
13927 | static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |
13928 | { | |
13929 | int cacheline_size; | |
13930 | u8 byte; | |
13931 | int goal; | |
13932 | ||
13933 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); | |
13934 | if (byte == 0) | |
13935 | cacheline_size = 1024; | |
13936 | else | |
13937 | cacheline_size = (int) byte * 4; | |
13938 | ||
13939 | /* On 5703 and later chips, the boundary bits have no | |
13940 | * effect. | |
13941 | */ | |
13942 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
13943 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
13944 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
13945 | goto out; | |
13946 | ||
13947 | #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC) | |
13948 | goal = BOUNDARY_MULTI_CACHELINE; | |
13949 | #else | |
13950 | #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA) | |
13951 | goal = BOUNDARY_SINGLE_CACHELINE; | |
13952 | #else | |
13953 | goal = 0; | |
13954 | #endif | |
13955 | #endif | |
13956 | ||
c885e824 | 13957 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) { |
cbf9ca6c MC |
13958 | val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT; |
13959 | goto out; | |
13960 | } | |
13961 | ||
59e6b434 DM |
13962 | if (!goal) |
13963 | goto out; | |
13964 | ||
13965 | /* PCI controllers on most RISC systems tend to disconnect | |
13966 | * when a device tries to burst across a cache-line boundary. | |
13967 | * Therefore, letting tg3 do so just wastes PCI bandwidth. | |
13968 | * | |
13969 | * Unfortunately, for PCI-E there are only limited | |
13970 | * write-side controls for this, and thus for reads | |
13971 | * we will still get the disconnects. We'll also waste | |
13972 | * these PCI cycles for both read and write for chips | |
13973 | * other than 5700 and 5701 which do not implement the | |
13974 | * boundary bits. | |
13975 | */ | |
13976 | if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) && | |
13977 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) { | |
13978 | switch (cacheline_size) { | |
13979 | case 16: | |
13980 | case 32: | |
13981 | case 64: | |
13982 | case 128: | |
13983 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
13984 | val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX | | |
13985 | DMA_RWCTRL_WRITE_BNDRY_128_PCIX); | |
13986 | } else { | |
13987 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
13988 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
13989 | } | |
13990 | break; | |
13991 | ||
13992 | case 256: | |
13993 | val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX | | |
13994 | DMA_RWCTRL_WRITE_BNDRY_256_PCIX); | |
13995 | break; | |
13996 | ||
13997 | default: | |
13998 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
13999 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
14000 | break; | |
855e1111 | 14001 | } |
59e6b434 DM |
14002 | } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { |
14003 | switch (cacheline_size) { | |
14004 | case 16: | |
14005 | case 32: | |
14006 | case 64: | |
14007 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14008 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
14009 | val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE; | |
14010 | break; | |
14011 | } | |
14012 | /* fallthrough */ | |
14013 | case 128: | |
14014 | default: | |
14015 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
14016 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; | |
14017 | break; | |
855e1111 | 14018 | } |
59e6b434 DM |
14019 | } else { |
14020 | switch (cacheline_size) { | |
14021 | case 16: | |
14022 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14023 | val |= (DMA_RWCTRL_READ_BNDRY_16 | | |
14024 | DMA_RWCTRL_WRITE_BNDRY_16); | |
14025 | break; | |
14026 | } | |
14027 | /* fallthrough */ | |
14028 | case 32: | |
14029 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14030 | val |= (DMA_RWCTRL_READ_BNDRY_32 | | |
14031 | DMA_RWCTRL_WRITE_BNDRY_32); | |
14032 | break; | |
14033 | } | |
14034 | /* fallthrough */ | |
14035 | case 64: | |
14036 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14037 | val |= (DMA_RWCTRL_READ_BNDRY_64 | | |
14038 | DMA_RWCTRL_WRITE_BNDRY_64); | |
14039 | break; | |
14040 | } | |
14041 | /* fallthrough */ | |
14042 | case 128: | |
14043 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14044 | val |= (DMA_RWCTRL_READ_BNDRY_128 | | |
14045 | DMA_RWCTRL_WRITE_BNDRY_128); | |
14046 | break; | |
14047 | } | |
14048 | /* fallthrough */ | |
14049 | case 256: | |
14050 | val |= (DMA_RWCTRL_READ_BNDRY_256 | | |
14051 | DMA_RWCTRL_WRITE_BNDRY_256); | |
14052 | break; | |
14053 | case 512: | |
14054 | val |= (DMA_RWCTRL_READ_BNDRY_512 | | |
14055 | DMA_RWCTRL_WRITE_BNDRY_512); | |
14056 | break; | |
14057 | case 1024: | |
14058 | default: | |
14059 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | | |
14060 | DMA_RWCTRL_WRITE_BNDRY_1024); | |
14061 | break; | |
855e1111 | 14062 | } |
59e6b434 DM |
14063 | } |
14064 | ||
14065 | out: | |
14066 | return val; | |
14067 | } | |
14068 | ||
1da177e4 LT |
14069 | static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device) |
14070 | { | |
14071 | struct tg3_internal_buffer_desc test_desc; | |
14072 | u32 sram_dma_descs; | |
14073 | int i, ret; | |
14074 | ||
14075 | sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE; | |
14076 | ||
14077 | tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0); | |
14078 | tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0); | |
14079 | tw32(RDMAC_STATUS, 0); | |
14080 | tw32(WDMAC_STATUS, 0); | |
14081 | ||
14082 | tw32(BUFMGR_MODE, 0); | |
14083 | tw32(FTQ_RESET, 0); | |
14084 | ||
14085 | test_desc.addr_hi = ((u64) buf_dma) >> 32; | |
14086 | test_desc.addr_lo = buf_dma & 0xffffffff; | |
14087 | test_desc.nic_mbuf = 0x00002100; | |
14088 | test_desc.len = size; | |
14089 | ||
14090 | /* | |
14091 | * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz | |
14092 | * the *second* time the tg3 driver was getting loaded after an | |
14093 | * initial scan. | |
14094 | * | |
14095 | * Broadcom tells me: | |
14096 | * ...the DMA engine is connected to the GRC block and a DMA | |
14097 | * reset may affect the GRC block in some unpredictable way... | |
14098 | * The behavior of resets to individual blocks has not been tested. | |
14099 | * | |
14100 | * Broadcom noted the GRC reset will also reset all sub-components. | |
14101 | */ | |
14102 | if (to_device) { | |
14103 | test_desc.cqid_sqid = (13 << 8) | 2; | |
14104 | ||
14105 | tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE); | |
14106 | udelay(40); | |
14107 | } else { | |
14108 | test_desc.cqid_sqid = (16 << 8) | 7; | |
14109 | ||
14110 | tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE); | |
14111 | udelay(40); | |
14112 | } | |
14113 | test_desc.flags = 0x00000005; | |
14114 | ||
14115 | for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) { | |
14116 | u32 val; | |
14117 | ||
14118 | val = *(((u32 *)&test_desc) + i); | |
14119 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, | |
14120 | sram_dma_descs + (i * sizeof(u32))); | |
14121 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
14122 | } | |
14123 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
14124 | ||
859a5887 | 14125 | if (to_device) |
1da177e4 | 14126 | tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs); |
859a5887 | 14127 | else |
1da177e4 | 14128 | tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs); |
1da177e4 LT |
14129 | |
14130 | ret = -ENODEV; | |
14131 | for (i = 0; i < 40; i++) { | |
14132 | u32 val; | |
14133 | ||
14134 | if (to_device) | |
14135 | val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); | |
14136 | else | |
14137 | val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); | |
14138 | if ((val & 0xffff) == sram_dma_descs) { | |
14139 | ret = 0; | |
14140 | break; | |
14141 | } | |
14142 | ||
14143 | udelay(100); | |
14144 | } | |
14145 | ||
14146 | return ret; | |
14147 | } | |
14148 | ||
ded7340d | 14149 | #define TEST_BUFFER_SIZE 0x2000 |
1da177e4 | 14150 | |
895950c2 JP |
14151 | DEFINE_PCI_DEVICE_TABLE(dma_wait_state_chipsets) = { |
14152 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) }, | |
14153 | { }, | |
14154 | }; | |
14155 | ||
1da177e4 LT |
14156 | static int __devinit tg3_test_dma(struct tg3 *tp) |
14157 | { | |
14158 | dma_addr_t buf_dma; | |
59e6b434 | 14159 | u32 *buf, saved_dma_rwctrl; |
cbf9ca6c | 14160 | int ret = 0; |
1da177e4 | 14161 | |
4bae65c8 MC |
14162 | buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, |
14163 | &buf_dma, GFP_KERNEL); | |
1da177e4 LT |
14164 | if (!buf) { |
14165 | ret = -ENOMEM; | |
14166 | goto out_nofree; | |
14167 | } | |
14168 | ||
14169 | tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | | |
14170 | (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT)); | |
14171 | ||
59e6b434 | 14172 | tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); |
1da177e4 | 14173 | |
c885e824 | 14174 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) |
cbf9ca6c MC |
14175 | goto out; |
14176 | ||
1da177e4 LT |
14177 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { |
14178 | /* DMA read watermark not used on PCIE */ | |
14179 | tp->dma_rwctrl |= 0x00180000; | |
14180 | } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { | |
85e94ced MC |
14181 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || |
14182 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) | |
1da177e4 LT |
14183 | tp->dma_rwctrl |= 0x003f0000; |
14184 | else | |
14185 | tp->dma_rwctrl |= 0x003f000f; | |
14186 | } else { | |
14187 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
14188 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
14189 | u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); | |
49afdeb6 | 14190 | u32 read_water = 0x7; |
1da177e4 | 14191 | |
4a29cc2e MC |
14192 | /* If the 5704 is behind the EPB bridge, we can |
14193 | * do the less restrictive ONE_DMA workaround for | |
14194 | * better performance. | |
14195 | */ | |
14196 | if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) && | |
14197 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
14198 | tp->dma_rwctrl |= 0x8000; | |
14199 | else if (ccval == 0x6 || ccval == 0x7) | |
1da177e4 LT |
14200 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; |
14201 | ||
49afdeb6 MC |
14202 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) |
14203 | read_water = 4; | |
59e6b434 | 14204 | /* Set bit 23 to enable PCIX hw bug fix */ |
49afdeb6 MC |
14205 | tp->dma_rwctrl |= |
14206 | (read_water << DMA_RWCTRL_READ_WATER_SHIFT) | | |
14207 | (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | | |
14208 | (1 << 23); | |
4cf78e4f MC |
14209 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) { |
14210 | /* 5780 always in PCIX mode */ | |
14211 | tp->dma_rwctrl |= 0x00144000; | |
a4e2b347 MC |
14212 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
14213 | /* 5714 always in PCIX mode */ | |
14214 | tp->dma_rwctrl |= 0x00148000; | |
1da177e4 LT |
14215 | } else { |
14216 | tp->dma_rwctrl |= 0x001b000f; | |
14217 | } | |
14218 | } | |
14219 | ||
14220 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
14221 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
14222 | tp->dma_rwctrl &= 0xfffffff0; | |
14223 | ||
14224 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
14225 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
14226 | /* Remove this if it causes problems for some boards. */ | |
14227 | tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; | |
14228 | ||
14229 | /* On 5700/5701 chips, we need to set this bit. | |
14230 | * Otherwise the chip will issue cacheline transactions | |
14231 | * to streamable DMA memory with not all the byte | |
14232 | * enables turned on. This is an error on several | |
14233 | * RISC PCI controllers, in particular sparc64. | |
14234 | * | |
14235 | * On 5703/5704 chips, this bit has been reassigned | |
14236 | * a different meaning. In particular, it is used | |
14237 | * on those chips to enable a PCI-X workaround. | |
14238 | */ | |
14239 | tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; | |
14240 | } | |
14241 | ||
14242 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14243 | ||
14244 | #if 0 | |
14245 | /* Unneeded, already done by tg3_get_invariants. */ | |
14246 | tg3_switch_clocks(tp); | |
14247 | #endif | |
14248 | ||
1da177e4 LT |
14249 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
14250 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | |
14251 | goto out; | |
14252 | ||
59e6b434 DM |
14253 | /* It is best to perform DMA test with maximum write burst size |
14254 | * to expose the 5700/5701 write DMA bug. | |
14255 | */ | |
14256 | saved_dma_rwctrl = tp->dma_rwctrl; | |
14257 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
14258 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14259 | ||
1da177e4 LT |
14260 | while (1) { |
14261 | u32 *p = buf, i; | |
14262 | ||
14263 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) | |
14264 | p[i] = i; | |
14265 | ||
14266 | /* Send the buffer to the chip. */ | |
14267 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1); | |
14268 | if (ret) { | |
2445e461 MC |
14269 | dev_err(&tp->pdev->dev, |
14270 | "%s: Buffer write failed. err = %d\n", | |
14271 | __func__, ret); | |
1da177e4 LT |
14272 | break; |
14273 | } | |
14274 | ||
14275 | #if 0 | |
14276 | /* validate data reached card RAM correctly. */ | |
14277 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
14278 | u32 val; | |
14279 | tg3_read_mem(tp, 0x2100 + (i*4), &val); | |
14280 | if (le32_to_cpu(val) != p[i]) { | |
2445e461 MC |
14281 | dev_err(&tp->pdev->dev, |
14282 | "%s: Buffer corrupted on device! " | |
14283 | "(%d != %d)\n", __func__, val, i); | |
1da177e4 LT |
14284 | /* ret = -ENODEV here? */ |
14285 | } | |
14286 | p[i] = 0; | |
14287 | } | |
14288 | #endif | |
14289 | /* Now read it back. */ | |
14290 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0); | |
14291 | if (ret) { | |
5129c3a3 MC |
14292 | dev_err(&tp->pdev->dev, "%s: Buffer read failed. " |
14293 | "err = %d\n", __func__, ret); | |
1da177e4 LT |
14294 | break; |
14295 | } | |
14296 | ||
14297 | /* Verify it. */ | |
14298 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
14299 | if (p[i] == i) | |
14300 | continue; | |
14301 | ||
59e6b434 DM |
14302 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
14303 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
14304 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
1da177e4 LT |
14305 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; |
14306 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14307 | break; | |
14308 | } else { | |
2445e461 MC |
14309 | dev_err(&tp->pdev->dev, |
14310 | "%s: Buffer corrupted on read back! " | |
14311 | "(%d != %d)\n", __func__, p[i], i); | |
1da177e4 LT |
14312 | ret = -ENODEV; |
14313 | goto out; | |
14314 | } | |
14315 | } | |
14316 | ||
14317 | if (i == (TEST_BUFFER_SIZE / sizeof(u32))) { | |
14318 | /* Success. */ | |
14319 | ret = 0; | |
14320 | break; | |
14321 | } | |
14322 | } | |
59e6b434 DM |
14323 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
14324 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
6d1cfbab | 14325 | |
59e6b434 | 14326 | /* DMA test passed without adjusting DMA boundary, |
6d1cfbab MC |
14327 | * now look for chipsets that are known to expose the |
14328 | * DMA bug without failing the test. | |
59e6b434 | 14329 | */ |
6d1cfbab MC |
14330 | if (pci_dev_present(dma_wait_state_chipsets)) { |
14331 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
14332 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; | |
859a5887 | 14333 | } else { |
6d1cfbab MC |
14334 | /* Safe to use the calculated DMA boundary. */ |
14335 | tp->dma_rwctrl = saved_dma_rwctrl; | |
859a5887 | 14336 | } |
6d1cfbab | 14337 | |
59e6b434 DM |
14338 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); |
14339 | } | |
1da177e4 LT |
14340 | |
14341 | out: | |
4bae65c8 | 14342 | dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); |
1da177e4 LT |
14343 | out_nofree: |
14344 | return ret; | |
14345 | } | |
14346 | ||
14347 | static void __devinit tg3_init_link_config(struct tg3 *tp) | |
14348 | { | |
14349 | tp->link_config.advertising = | |
14350 | (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
14351 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
14352 | ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full | | |
14353 | ADVERTISED_Autoneg | ADVERTISED_MII); | |
14354 | tp->link_config.speed = SPEED_INVALID; | |
14355 | tp->link_config.duplex = DUPLEX_INVALID; | |
14356 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
1da177e4 LT |
14357 | tp->link_config.active_speed = SPEED_INVALID; |
14358 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
1da177e4 LT |
14359 | tp->link_config.orig_speed = SPEED_INVALID; |
14360 | tp->link_config.orig_duplex = DUPLEX_INVALID; | |
14361 | tp->link_config.orig_autoneg = AUTONEG_INVALID; | |
14362 | } | |
14363 | ||
14364 | static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) | |
14365 | { | |
c885e824 | 14366 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) { |
666bc831 MC |
14367 | tp->bufmgr_config.mbuf_read_dma_low_water = |
14368 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14369 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14370 | DEFAULT_MB_MACRX_LOW_WATER_57765; | |
14371 | tp->bufmgr_config.mbuf_high_water = | |
14372 | DEFAULT_MB_HIGH_WATER_57765; | |
14373 | ||
14374 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14375 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14376 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14377 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765; | |
14378 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14379 | DEFAULT_MB_HIGH_WATER_JUMBO_57765; | |
14380 | } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
fdfec172 MC |
14381 | tp->bufmgr_config.mbuf_read_dma_low_water = |
14382 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14383 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14384 | DEFAULT_MB_MACRX_LOW_WATER_5705; | |
14385 | tp->bufmgr_config.mbuf_high_water = | |
14386 | DEFAULT_MB_HIGH_WATER_5705; | |
b5d3772c MC |
14387 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
14388 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14389 | DEFAULT_MB_MACRX_LOW_WATER_5906; | |
14390 | tp->bufmgr_config.mbuf_high_water = | |
14391 | DEFAULT_MB_HIGH_WATER_5906; | |
14392 | } | |
fdfec172 MC |
14393 | |
14394 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14395 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780; | |
14396 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14397 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780; | |
14398 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14399 | DEFAULT_MB_HIGH_WATER_JUMBO_5780; | |
14400 | } else { | |
14401 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
14402 | DEFAULT_MB_RDMA_LOW_WATER; | |
14403 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14404 | DEFAULT_MB_MACRX_LOW_WATER; | |
14405 | tp->bufmgr_config.mbuf_high_water = | |
14406 | DEFAULT_MB_HIGH_WATER; | |
14407 | ||
14408 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14409 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO; | |
14410 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14411 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO; | |
14412 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14413 | DEFAULT_MB_HIGH_WATER_JUMBO; | |
14414 | } | |
1da177e4 LT |
14415 | |
14416 | tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; | |
14417 | tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; | |
14418 | } | |
14419 | ||
14420 | static char * __devinit tg3_phy_string(struct tg3 *tp) | |
14421 | { | |
79eb6904 MC |
14422 | switch (tp->phy_id & TG3_PHY_ID_MASK) { |
14423 | case TG3_PHY_ID_BCM5400: return "5400"; | |
14424 | case TG3_PHY_ID_BCM5401: return "5401"; | |
14425 | case TG3_PHY_ID_BCM5411: return "5411"; | |
14426 | case TG3_PHY_ID_BCM5701: return "5701"; | |
14427 | case TG3_PHY_ID_BCM5703: return "5703"; | |
14428 | case TG3_PHY_ID_BCM5704: return "5704"; | |
14429 | case TG3_PHY_ID_BCM5705: return "5705"; | |
14430 | case TG3_PHY_ID_BCM5750: return "5750"; | |
14431 | case TG3_PHY_ID_BCM5752: return "5752"; | |
14432 | case TG3_PHY_ID_BCM5714: return "5714"; | |
14433 | case TG3_PHY_ID_BCM5780: return "5780"; | |
14434 | case TG3_PHY_ID_BCM5755: return "5755"; | |
14435 | case TG3_PHY_ID_BCM5787: return "5787"; | |
14436 | case TG3_PHY_ID_BCM5784: return "5784"; | |
14437 | case TG3_PHY_ID_BCM5756: return "5722/5756"; | |
14438 | case TG3_PHY_ID_BCM5906: return "5906"; | |
14439 | case TG3_PHY_ID_BCM5761: return "5761"; | |
14440 | case TG3_PHY_ID_BCM5718C: return "5718C"; | |
14441 | case TG3_PHY_ID_BCM5718S: return "5718S"; | |
14442 | case TG3_PHY_ID_BCM57765: return "57765"; | |
302b500b | 14443 | case TG3_PHY_ID_BCM5719C: return "5719C"; |
79eb6904 | 14444 | case TG3_PHY_ID_BCM8002: return "8002/serdes"; |
1da177e4 LT |
14445 | case 0: return "serdes"; |
14446 | default: return "unknown"; | |
855e1111 | 14447 | } |
1da177e4 LT |
14448 | } |
14449 | ||
f9804ddb MC |
14450 | static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) |
14451 | { | |
14452 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
14453 | strcpy(str, "PCI Express"); | |
14454 | return str; | |
14455 | } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { | |
14456 | u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; | |
14457 | ||
14458 | strcpy(str, "PCIX:"); | |
14459 | ||
14460 | if ((clock_ctrl == 7) || | |
14461 | ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == | |
14462 | GRC_MISC_CFG_BOARD_ID_5704CIOBE)) | |
14463 | strcat(str, "133MHz"); | |
14464 | else if (clock_ctrl == 0) | |
14465 | strcat(str, "33MHz"); | |
14466 | else if (clock_ctrl == 2) | |
14467 | strcat(str, "50MHz"); | |
14468 | else if (clock_ctrl == 4) | |
14469 | strcat(str, "66MHz"); | |
14470 | else if (clock_ctrl == 6) | |
14471 | strcat(str, "100MHz"); | |
f9804ddb MC |
14472 | } else { |
14473 | strcpy(str, "PCI:"); | |
14474 | if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) | |
14475 | strcat(str, "66MHz"); | |
14476 | else | |
14477 | strcat(str, "33MHz"); | |
14478 | } | |
14479 | if (tp->tg3_flags & TG3_FLAG_PCI_32BIT) | |
14480 | strcat(str, ":32-bit"); | |
14481 | else | |
14482 | strcat(str, ":64-bit"); | |
14483 | return str; | |
14484 | } | |
14485 | ||
8c2dc7e1 | 14486 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp) |
1da177e4 LT |
14487 | { |
14488 | struct pci_dev *peer; | |
14489 | unsigned int func, devnr = tp->pdev->devfn & ~7; | |
14490 | ||
14491 | for (func = 0; func < 8; func++) { | |
14492 | peer = pci_get_slot(tp->pdev->bus, devnr | func); | |
14493 | if (peer && peer != tp->pdev) | |
14494 | break; | |
14495 | pci_dev_put(peer); | |
14496 | } | |
16fe9d74 MC |
14497 | /* 5704 can be configured in single-port mode, set peer to |
14498 | * tp->pdev in that case. | |
14499 | */ | |
14500 | if (!peer) { | |
14501 | peer = tp->pdev; | |
14502 | return peer; | |
14503 | } | |
1da177e4 LT |
14504 | |
14505 | /* | |
14506 | * We don't need to keep the refcount elevated; there's no way | |
14507 | * to remove one half of this device without removing the other | |
14508 | */ | |
14509 | pci_dev_put(peer); | |
14510 | ||
14511 | return peer; | |
14512 | } | |
14513 | ||
15f9850d DM |
14514 | static void __devinit tg3_init_coal(struct tg3 *tp) |
14515 | { | |
14516 | struct ethtool_coalesce *ec = &tp->coal; | |
14517 | ||
14518 | memset(ec, 0, sizeof(*ec)); | |
14519 | ec->cmd = ETHTOOL_GCOALESCE; | |
14520 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; | |
14521 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; | |
14522 | ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; | |
14523 | ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; | |
14524 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; | |
14525 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; | |
14526 | ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; | |
14527 | ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; | |
14528 | ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; | |
14529 | ||
14530 | if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | | |
14531 | HOSTCC_MODE_CLRTICK_TXBD)) { | |
14532 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; | |
14533 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; | |
14534 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; | |
14535 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; | |
14536 | } | |
d244c892 MC |
14537 | |
14538 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
14539 | ec->rx_coalesce_usecs_irq = 0; | |
14540 | ec->tx_coalesce_usecs_irq = 0; | |
14541 | ec->stats_block_coalesce_usecs = 0; | |
14542 | } | |
15f9850d DM |
14543 | } |
14544 | ||
7c7d64b8 SH |
14545 | static const struct net_device_ops tg3_netdev_ops = { |
14546 | .ndo_open = tg3_open, | |
14547 | .ndo_stop = tg3_close, | |
00829823 | 14548 | .ndo_start_xmit = tg3_start_xmit, |
511d2224 | 14549 | .ndo_get_stats64 = tg3_get_stats64, |
00829823 SH |
14550 | .ndo_validate_addr = eth_validate_addr, |
14551 | .ndo_set_multicast_list = tg3_set_rx_mode, | |
14552 | .ndo_set_mac_address = tg3_set_mac_addr, | |
14553 | .ndo_do_ioctl = tg3_ioctl, | |
14554 | .ndo_tx_timeout = tg3_tx_timeout, | |
14555 | .ndo_change_mtu = tg3_change_mtu, | |
00829823 SH |
14556 | #ifdef CONFIG_NET_POLL_CONTROLLER |
14557 | .ndo_poll_controller = tg3_poll_controller, | |
14558 | #endif | |
14559 | }; | |
14560 | ||
14561 | static const struct net_device_ops tg3_netdev_ops_dma_bug = { | |
14562 | .ndo_open = tg3_open, | |
14563 | .ndo_stop = tg3_close, | |
14564 | .ndo_start_xmit = tg3_start_xmit_dma_bug, | |
511d2224 | 14565 | .ndo_get_stats64 = tg3_get_stats64, |
7c7d64b8 SH |
14566 | .ndo_validate_addr = eth_validate_addr, |
14567 | .ndo_set_multicast_list = tg3_set_rx_mode, | |
14568 | .ndo_set_mac_address = tg3_set_mac_addr, | |
14569 | .ndo_do_ioctl = tg3_ioctl, | |
14570 | .ndo_tx_timeout = tg3_tx_timeout, | |
14571 | .ndo_change_mtu = tg3_change_mtu, | |
7c7d64b8 SH |
14572 | #ifdef CONFIG_NET_POLL_CONTROLLER |
14573 | .ndo_poll_controller = tg3_poll_controller, | |
14574 | #endif | |
14575 | }; | |
14576 | ||
1da177e4 LT |
14577 | static int __devinit tg3_init_one(struct pci_dev *pdev, |
14578 | const struct pci_device_id *ent) | |
14579 | { | |
1da177e4 LT |
14580 | struct net_device *dev; |
14581 | struct tg3 *tp; | |
646c9edd MC |
14582 | int i, err, pm_cap; |
14583 | u32 sndmbx, rcvmbx, intmbx; | |
f9804ddb | 14584 | char str[40]; |
72f2afb8 | 14585 | u64 dma_mask, persist_dma_mask; |
1da177e4 | 14586 | |
05dbe005 | 14587 | printk_once(KERN_INFO "%s\n", version); |
1da177e4 LT |
14588 | |
14589 | err = pci_enable_device(pdev); | |
14590 | if (err) { | |
2445e461 | 14591 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
1da177e4 LT |
14592 | return err; |
14593 | } | |
14594 | ||
1da177e4 LT |
14595 | err = pci_request_regions(pdev, DRV_MODULE_NAME); |
14596 | if (err) { | |
2445e461 | 14597 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); |
1da177e4 LT |
14598 | goto err_out_disable_pdev; |
14599 | } | |
14600 | ||
14601 | pci_set_master(pdev); | |
14602 | ||
14603 | /* Find power-management capability. */ | |
14604 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
14605 | if (pm_cap == 0) { | |
2445e461 MC |
14606 | dev_err(&pdev->dev, |
14607 | "Cannot find Power Management capability, aborting\n"); | |
1da177e4 LT |
14608 | err = -EIO; |
14609 | goto err_out_free_res; | |
14610 | } | |
14611 | ||
fe5f5787 | 14612 | dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); |
1da177e4 | 14613 | if (!dev) { |
2445e461 | 14614 | dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n"); |
1da177e4 LT |
14615 | err = -ENOMEM; |
14616 | goto err_out_free_res; | |
14617 | } | |
14618 | ||
1da177e4 LT |
14619 | SET_NETDEV_DEV(dev, &pdev->dev); |
14620 | ||
1da177e4 | 14621 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
1da177e4 LT |
14622 | |
14623 | tp = netdev_priv(dev); | |
14624 | tp->pdev = pdev; | |
14625 | tp->dev = dev; | |
14626 | tp->pm_cap = pm_cap; | |
1da177e4 LT |
14627 | tp->rx_mode = TG3_DEF_RX_MODE; |
14628 | tp->tx_mode = TG3_DEF_TX_MODE; | |
8ef21428 | 14629 | |
1da177e4 LT |
14630 | if (tg3_debug > 0) |
14631 | tp->msg_enable = tg3_debug; | |
14632 | else | |
14633 | tp->msg_enable = TG3_DEF_MSG_ENABLE; | |
14634 | ||
14635 | /* The word/byte swap controls here control register access byte | |
14636 | * swapping. DMA data byte swapping is controlled in the GRC_MODE | |
14637 | * setting below. | |
14638 | */ | |
14639 | tp->misc_host_ctrl = | |
14640 | MISC_HOST_CTRL_MASK_PCI_INT | | |
14641 | MISC_HOST_CTRL_WORD_SWAP | | |
14642 | MISC_HOST_CTRL_INDIR_ACCESS | | |
14643 | MISC_HOST_CTRL_PCISTATE_RW; | |
14644 | ||
14645 | /* The NONFRM (non-frame) byte/word swap controls take effect | |
14646 | * on descriptor entries, anything which isn't packet data. | |
14647 | * | |
14648 | * The StrongARM chips on the board (one for tx, one for rx) | |
14649 | * are running in big-endian mode. | |
14650 | */ | |
14651 | tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | | |
14652 | GRC_MODE_WSWAP_NONFRM_DATA); | |
14653 | #ifdef __BIG_ENDIAN | |
14654 | tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; | |
14655 | #endif | |
14656 | spin_lock_init(&tp->lock); | |
1da177e4 | 14657 | spin_lock_init(&tp->indirect_lock); |
c4028958 | 14658 | INIT_WORK(&tp->reset_task, tg3_reset_task); |
1da177e4 | 14659 | |
d5fe488a | 14660 | tp->regs = pci_ioremap_bar(pdev, BAR_0); |
ab0049b4 | 14661 | if (!tp->regs) { |
ab96b241 | 14662 | dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); |
1da177e4 LT |
14663 | err = -ENOMEM; |
14664 | goto err_out_free_dev; | |
14665 | } | |
14666 | ||
14667 | tg3_init_link_config(tp); | |
14668 | ||
1da177e4 LT |
14669 | tp->rx_pending = TG3_DEF_RX_RING_PENDING; |
14670 | tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; | |
1da177e4 | 14671 | |
1da177e4 | 14672 | dev->ethtool_ops = &tg3_ethtool_ops; |
1da177e4 | 14673 | dev->watchdog_timeo = TG3_TX_TIMEOUT; |
1da177e4 | 14674 | dev->irq = pdev->irq; |
1da177e4 LT |
14675 | |
14676 | err = tg3_get_invariants(tp); | |
14677 | if (err) { | |
ab96b241 MC |
14678 | dev_err(&pdev->dev, |
14679 | "Problem fetching invariants of chip, aborting\n"); | |
1da177e4 LT |
14680 | goto err_out_iounmap; |
14681 | } | |
14682 | ||
615774fe | 14683 | if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) && |
2e9f7a74 | 14684 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && |
a50d0796 | 14685 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719) |
00829823 SH |
14686 | dev->netdev_ops = &tg3_netdev_ops; |
14687 | else | |
14688 | dev->netdev_ops = &tg3_netdev_ops_dma_bug; | |
14689 | ||
14690 | ||
4a29cc2e MC |
14691 | /* The EPB bridge inside 5714, 5715, and 5780 and any |
14692 | * device behind the EPB cannot support DMA addresses > 40-bit. | |
72f2afb8 MC |
14693 | * On 64-bit systems with IOMMU, use 40-bit dma_mask. |
14694 | * On 64-bit systems without IOMMU, use 64-bit dma_mask and | |
14695 | * do DMA address check in tg3_start_xmit(). | |
14696 | */ | |
4a29cc2e | 14697 | if (tp->tg3_flags2 & TG3_FLG2_IS_5788) |
284901a9 | 14698 | persist_dma_mask = dma_mask = DMA_BIT_MASK(32); |
4a29cc2e | 14699 | else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) { |
50cf156a | 14700 | persist_dma_mask = dma_mask = DMA_BIT_MASK(40); |
72f2afb8 | 14701 | #ifdef CONFIG_HIGHMEM |
6a35528a | 14702 | dma_mask = DMA_BIT_MASK(64); |
72f2afb8 | 14703 | #endif |
4a29cc2e | 14704 | } else |
6a35528a | 14705 | persist_dma_mask = dma_mask = DMA_BIT_MASK(64); |
72f2afb8 MC |
14706 | |
14707 | /* Configure DMA attributes. */ | |
284901a9 | 14708 | if (dma_mask > DMA_BIT_MASK(32)) { |
72f2afb8 MC |
14709 | err = pci_set_dma_mask(pdev, dma_mask); |
14710 | if (!err) { | |
14711 | dev->features |= NETIF_F_HIGHDMA; | |
14712 | err = pci_set_consistent_dma_mask(pdev, | |
14713 | persist_dma_mask); | |
14714 | if (err < 0) { | |
ab96b241 MC |
14715 | dev_err(&pdev->dev, "Unable to obtain 64 bit " |
14716 | "DMA for consistent allocations\n"); | |
72f2afb8 MC |
14717 | goto err_out_iounmap; |
14718 | } | |
14719 | } | |
14720 | } | |
284901a9 YH |
14721 | if (err || dma_mask == DMA_BIT_MASK(32)) { |
14722 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
72f2afb8 | 14723 | if (err) { |
ab96b241 MC |
14724 | dev_err(&pdev->dev, |
14725 | "No usable DMA configuration, aborting\n"); | |
72f2afb8 MC |
14726 | goto err_out_iounmap; |
14727 | } | |
14728 | } | |
14729 | ||
fdfec172 | 14730 | tg3_init_bufmgr_config(tp); |
1da177e4 | 14731 | |
507399f1 MC |
14732 | /* Selectively allow TSO based on operating conditions */ |
14733 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) || | |
14734 | (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) | |
1da177e4 | 14735 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; |
507399f1 MC |
14736 | else { |
14737 | tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG); | |
14738 | tp->fw_needed = NULL; | |
1da177e4 | 14739 | } |
507399f1 MC |
14740 | |
14741 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) | |
14742 | tp->fw_needed = FIRMWARE_TG3; | |
1da177e4 | 14743 | |
4e3a7aaa MC |
14744 | /* TSO is on by default on chips that support hardware TSO. |
14745 | * Firmware TSO on older chips gives lower performance, so it | |
14746 | * is off by default, but can be enabled using ethtool. | |
14747 | */ | |
e849cdc3 | 14748 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) && |
7fe876af | 14749 | (dev->features & NETIF_F_IP_CSUM)) { |
e849cdc3 | 14750 | dev->features |= NETIF_F_TSO; |
7fe876af ED |
14751 | vlan_features_add(dev, NETIF_F_TSO); |
14752 | } | |
e849cdc3 MC |
14753 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) || |
14754 | (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) { | |
7fe876af | 14755 | if (dev->features & NETIF_F_IPV6_CSUM) { |
b0026624 | 14756 | dev->features |= NETIF_F_TSO6; |
7fe876af ED |
14757 | vlan_features_add(dev, NETIF_F_TSO6); |
14758 | } | |
e849cdc3 MC |
14759 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) || |
14760 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
57e6983c MC |
14761 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
14762 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
321d32a0 | 14763 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
7fe876af | 14764 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
9936bcf6 | 14765 | dev->features |= NETIF_F_TSO_ECN; |
7fe876af ED |
14766 | vlan_features_add(dev, NETIF_F_TSO_ECN); |
14767 | } | |
b0026624 | 14768 | } |
1da177e4 | 14769 | |
1da177e4 LT |
14770 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 && |
14771 | !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) && | |
14772 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { | |
14773 | tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64; | |
14774 | tp->rx_pending = 63; | |
14775 | } | |
14776 | ||
1da177e4 LT |
14777 | err = tg3_get_device_address(tp); |
14778 | if (err) { | |
ab96b241 MC |
14779 | dev_err(&pdev->dev, |
14780 | "Could not obtain valid ethernet address, aborting\n"); | |
026a6c21 | 14781 | goto err_out_iounmap; |
1da177e4 LT |
14782 | } |
14783 | ||
c88864df | 14784 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
63532394 | 14785 | tp->aperegs = pci_ioremap_bar(pdev, BAR_2); |
79ea13ce | 14786 | if (!tp->aperegs) { |
ab96b241 MC |
14787 | dev_err(&pdev->dev, |
14788 | "Cannot map APE registers, aborting\n"); | |
c88864df | 14789 | err = -ENOMEM; |
026a6c21 | 14790 | goto err_out_iounmap; |
c88864df MC |
14791 | } |
14792 | ||
14793 | tg3_ape_lock_init(tp); | |
7fd76445 MC |
14794 | |
14795 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) | |
14796 | tg3_read_dash_ver(tp); | |
c88864df MC |
14797 | } |
14798 | ||
1da177e4 LT |
14799 | /* |
14800 | * Reset chip in case UNDI or EFI driver did not shutdown | |
14801 | * DMA self test will enable WDMAC and we'll see (spurious) | |
14802 | * pending DMA on the PCI bus at that point. | |
14803 | */ | |
14804 | if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || | |
14805 | (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { | |
1da177e4 | 14806 | tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); |
944d980e | 14807 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
14808 | } |
14809 | ||
14810 | err = tg3_test_dma(tp); | |
14811 | if (err) { | |
ab96b241 | 14812 | dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); |
c88864df | 14813 | goto err_out_apeunmap; |
1da177e4 LT |
14814 | } |
14815 | ||
1da177e4 LT |
14816 | /* flow control autonegotiation is default behavior */ |
14817 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | |
e18ce346 | 14818 | tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; |
1da177e4 | 14819 | |
78f90dcf MC |
14820 | intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; |
14821 | rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW; | |
14822 | sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
6fd45cb8 | 14823 | for (i = 0; i < tp->irq_max; i++) { |
78f90dcf MC |
14824 | struct tg3_napi *tnapi = &tp->napi[i]; |
14825 | ||
14826 | tnapi->tp = tp; | |
14827 | tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; | |
14828 | ||
14829 | tnapi->int_mbox = intmbx; | |
14830 | if (i < 4) | |
14831 | intmbx += 0x8; | |
14832 | else | |
14833 | intmbx += 0x4; | |
14834 | ||
14835 | tnapi->consmbox = rcvmbx; | |
14836 | tnapi->prodmbox = sndmbx; | |
14837 | ||
66cfd1bd | 14838 | if (i) |
78f90dcf | 14839 | tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); |
66cfd1bd | 14840 | else |
78f90dcf | 14841 | tnapi->coal_now = HOSTCC_MODE_NOW; |
78f90dcf MC |
14842 | |
14843 | if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX)) | |
14844 | break; | |
14845 | ||
14846 | /* | |
14847 | * If we support MSIX, we'll be using RSS. If we're using | |
14848 | * RSS, the first vector only handles link interrupts and the | |
14849 | * remaining vectors handle rx and tx interrupts. Reuse the | |
14850 | * mailbox values for the next iteration. The values we setup | |
14851 | * above are still useful for the single vectored mode. | |
14852 | */ | |
14853 | if (!i) | |
14854 | continue; | |
14855 | ||
14856 | rcvmbx += 0x8; | |
14857 | ||
14858 | if (sndmbx & 0x4) | |
14859 | sndmbx -= 0x4; | |
14860 | else | |
14861 | sndmbx += 0xc; | |
14862 | } | |
14863 | ||
15f9850d DM |
14864 | tg3_init_coal(tp); |
14865 | ||
c49a1561 MC |
14866 | pci_set_drvdata(pdev, dev); |
14867 | ||
1da177e4 LT |
14868 | err = register_netdev(dev); |
14869 | if (err) { | |
ab96b241 | 14870 | dev_err(&pdev->dev, "Cannot register net device, aborting\n"); |
0d3031d9 | 14871 | goto err_out_apeunmap; |
1da177e4 LT |
14872 | } |
14873 | ||
05dbe005 JP |
14874 | netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n", |
14875 | tp->board_part_number, | |
14876 | tp->pci_chip_rev_id, | |
14877 | tg3_bus_string(tp, str), | |
14878 | dev->dev_addr); | |
1da177e4 | 14879 | |
f07e9af3 | 14880 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 MC |
14881 | struct phy_device *phydev; |
14882 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
5129c3a3 MC |
14883 | netdev_info(dev, |
14884 | "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", | |
05dbe005 | 14885 | phydev->drv->name, dev_name(&phydev->dev)); |
f07e9af3 MC |
14886 | } else { |
14887 | char *ethtype; | |
14888 | ||
14889 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
14890 | ethtype = "10/100Base-TX"; | |
14891 | else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) | |
14892 | ethtype = "1000Base-SX"; | |
14893 | else | |
14894 | ethtype = "10/100/1000Base-T"; | |
14895 | ||
5129c3a3 | 14896 | netdev_info(dev, "attached PHY is %s (%s Ethernet) " |
f07e9af3 MC |
14897 | "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype, |
14898 | (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0); | |
14899 | } | |
05dbe005 JP |
14900 | |
14901 | netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n", | |
14902 | (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0, | |
14903 | (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0, | |
f07e9af3 | 14904 | (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, |
05dbe005 JP |
14905 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0, |
14906 | (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0); | |
14907 | netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", | |
14908 | tp->dma_rwctrl, | |
14909 | pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : | |
14910 | ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64); | |
1da177e4 LT |
14911 | |
14912 | return 0; | |
14913 | ||
0d3031d9 MC |
14914 | err_out_apeunmap: |
14915 | if (tp->aperegs) { | |
14916 | iounmap(tp->aperegs); | |
14917 | tp->aperegs = NULL; | |
14918 | } | |
14919 | ||
1da177e4 | 14920 | err_out_iounmap: |
6892914f MC |
14921 | if (tp->regs) { |
14922 | iounmap(tp->regs); | |
22abe310 | 14923 | tp->regs = NULL; |
6892914f | 14924 | } |
1da177e4 LT |
14925 | |
14926 | err_out_free_dev: | |
14927 | free_netdev(dev); | |
14928 | ||
14929 | err_out_free_res: | |
14930 | pci_release_regions(pdev); | |
14931 | ||
14932 | err_out_disable_pdev: | |
14933 | pci_disable_device(pdev); | |
14934 | pci_set_drvdata(pdev, NULL); | |
14935 | return err; | |
14936 | } | |
14937 | ||
14938 | static void __devexit tg3_remove_one(struct pci_dev *pdev) | |
14939 | { | |
14940 | struct net_device *dev = pci_get_drvdata(pdev); | |
14941 | ||
14942 | if (dev) { | |
14943 | struct tg3 *tp = netdev_priv(dev); | |
14944 | ||
077f849d JSR |
14945 | if (tp->fw) |
14946 | release_firmware(tp->fw); | |
14947 | ||
23f333a2 | 14948 | cancel_work_sync(&tp->reset_task); |
158d7abd | 14949 | |
b02fd9e3 MC |
14950 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
14951 | tg3_phy_fini(tp); | |
158d7abd | 14952 | tg3_mdio_fini(tp); |
b02fd9e3 | 14953 | } |
158d7abd | 14954 | |
1da177e4 | 14955 | unregister_netdev(dev); |
0d3031d9 MC |
14956 | if (tp->aperegs) { |
14957 | iounmap(tp->aperegs); | |
14958 | tp->aperegs = NULL; | |
14959 | } | |
6892914f MC |
14960 | if (tp->regs) { |
14961 | iounmap(tp->regs); | |
22abe310 | 14962 | tp->regs = NULL; |
6892914f | 14963 | } |
1da177e4 LT |
14964 | free_netdev(dev); |
14965 | pci_release_regions(pdev); | |
14966 | pci_disable_device(pdev); | |
14967 | pci_set_drvdata(pdev, NULL); | |
14968 | } | |
14969 | } | |
14970 | ||
aa6027ca | 14971 | #ifdef CONFIG_PM_SLEEP |
c866b7ea | 14972 | static int tg3_suspend(struct device *device) |
1da177e4 | 14973 | { |
c866b7ea | 14974 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
14975 | struct net_device *dev = pci_get_drvdata(pdev); |
14976 | struct tg3 *tp = netdev_priv(dev); | |
14977 | int err; | |
14978 | ||
14979 | if (!netif_running(dev)) | |
14980 | return 0; | |
14981 | ||
23f333a2 | 14982 | flush_work_sync(&tp->reset_task); |
b02fd9e3 | 14983 | tg3_phy_stop(tp); |
1da177e4 LT |
14984 | tg3_netif_stop(tp); |
14985 | ||
14986 | del_timer_sync(&tp->timer); | |
14987 | ||
f47c11ee | 14988 | tg3_full_lock(tp, 1); |
1da177e4 | 14989 | tg3_disable_ints(tp); |
f47c11ee | 14990 | tg3_full_unlock(tp); |
1da177e4 LT |
14991 | |
14992 | netif_device_detach(dev); | |
14993 | ||
f47c11ee | 14994 | tg3_full_lock(tp, 0); |
944d980e | 14995 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
6a9eba15 | 14996 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; |
f47c11ee | 14997 | tg3_full_unlock(tp); |
1da177e4 | 14998 | |
c866b7ea | 14999 | err = tg3_power_down_prepare(tp); |
1da177e4 | 15000 | if (err) { |
b02fd9e3 MC |
15001 | int err2; |
15002 | ||
f47c11ee | 15003 | tg3_full_lock(tp, 0); |
1da177e4 | 15004 | |
6a9eba15 | 15005 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; |
b02fd9e3 MC |
15006 | err2 = tg3_restart_hw(tp, 1); |
15007 | if (err2) | |
b9ec6c1b | 15008 | goto out; |
1da177e4 LT |
15009 | |
15010 | tp->timer.expires = jiffies + tp->timer_offset; | |
15011 | add_timer(&tp->timer); | |
15012 | ||
15013 | netif_device_attach(dev); | |
15014 | tg3_netif_start(tp); | |
15015 | ||
b9ec6c1b | 15016 | out: |
f47c11ee | 15017 | tg3_full_unlock(tp); |
b02fd9e3 MC |
15018 | |
15019 | if (!err2) | |
15020 | tg3_phy_start(tp); | |
1da177e4 LT |
15021 | } |
15022 | ||
15023 | return err; | |
15024 | } | |
15025 | ||
c866b7ea | 15026 | static int tg3_resume(struct device *device) |
1da177e4 | 15027 | { |
c866b7ea | 15028 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
15029 | struct net_device *dev = pci_get_drvdata(pdev); |
15030 | struct tg3 *tp = netdev_priv(dev); | |
15031 | int err; | |
15032 | ||
15033 | if (!netif_running(dev)) | |
15034 | return 0; | |
15035 | ||
1da177e4 LT |
15036 | netif_device_attach(dev); |
15037 | ||
f47c11ee | 15038 | tg3_full_lock(tp, 0); |
1da177e4 | 15039 | |
6a9eba15 | 15040 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; |
b9ec6c1b MC |
15041 | err = tg3_restart_hw(tp, 1); |
15042 | if (err) | |
15043 | goto out; | |
1da177e4 LT |
15044 | |
15045 | tp->timer.expires = jiffies + tp->timer_offset; | |
15046 | add_timer(&tp->timer); | |
15047 | ||
1da177e4 LT |
15048 | tg3_netif_start(tp); |
15049 | ||
b9ec6c1b | 15050 | out: |
f47c11ee | 15051 | tg3_full_unlock(tp); |
1da177e4 | 15052 | |
b02fd9e3 MC |
15053 | if (!err) |
15054 | tg3_phy_start(tp); | |
15055 | ||
b9ec6c1b | 15056 | return err; |
1da177e4 LT |
15057 | } |
15058 | ||
c866b7ea | 15059 | static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume); |
aa6027ca ED |
15060 | #define TG3_PM_OPS (&tg3_pm_ops) |
15061 | ||
15062 | #else | |
15063 | ||
15064 | #define TG3_PM_OPS NULL | |
15065 | ||
15066 | #endif /* CONFIG_PM_SLEEP */ | |
c866b7ea | 15067 | |
1da177e4 LT |
15068 | static struct pci_driver tg3_driver = { |
15069 | .name = DRV_MODULE_NAME, | |
15070 | .id_table = tg3_pci_tbl, | |
15071 | .probe = tg3_init_one, | |
15072 | .remove = __devexit_p(tg3_remove_one), | |
aa6027ca | 15073 | .driver.pm = TG3_PM_OPS, |
1da177e4 LT |
15074 | }; |
15075 | ||
15076 | static int __init tg3_init(void) | |
15077 | { | |
29917620 | 15078 | return pci_register_driver(&tg3_driver); |
1da177e4 LT |
15079 | } |
15080 | ||
15081 | static void __exit tg3_cleanup(void) | |
15082 | { | |
15083 | pci_unregister_driver(&tg3_driver); | |
15084 | } | |
15085 | ||
15086 | module_init(tg3_init); | |
15087 | module_exit(tg3_cleanup); |