Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * tg3.c: Broadcom Tigon3 ethernet driver. | |
3 | * | |
4 | * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) | |
5 | * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com) | |
6 | * Copyright (C) 2004 Sun Microsystems Inc. | |
0d2a5068 | 7 | * Copyright (C) 2005-2009 Broadcom Corporation. |
1da177e4 LT |
8 | * |
9 | * Firmware is: | |
49cabf49 MC |
10 | * Derived from proprietary unpublished source code, |
11 | * Copyright (C) 2000-2003 Broadcom Corporation. | |
12 | * | |
13 | * Permission is hereby granted for the distribution of this firmware | |
14 | * data in hexadecimal or equivalent format, provided this copyright | |
15 | * notice is accompanying it. | |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | |
19 | #include <linux/module.h> | |
20 | #include <linux/moduleparam.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/types.h> | |
23 | #include <linux/compiler.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/delay.h> | |
14c85021 | 26 | #include <linux/in.h> |
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/ioport.h> | |
29 | #include <linux/pci.h> | |
30 | #include <linux/netdevice.h> | |
31 | #include <linux/etherdevice.h> | |
32 | #include <linux/skbuff.h> | |
33 | #include <linux/ethtool.h> | |
34 | #include <linux/mii.h> | |
158d7abd | 35 | #include <linux/phy.h> |
a9daf367 | 36 | #include <linux/brcmphy.h> |
1da177e4 LT |
37 | #include <linux/if_vlan.h> |
38 | #include <linux/ip.h> | |
39 | #include <linux/tcp.h> | |
40 | #include <linux/workqueue.h> | |
61487480 | 41 | #include <linux/prefetch.h> |
f9a5f7d3 | 42 | #include <linux/dma-mapping.h> |
077f849d | 43 | #include <linux/firmware.h> |
1da177e4 LT |
44 | |
45 | #include <net/checksum.h> | |
c9bdd4b5 | 46 | #include <net/ip.h> |
1da177e4 LT |
47 | |
48 | #include <asm/system.h> | |
49 | #include <asm/io.h> | |
50 | #include <asm/byteorder.h> | |
51 | #include <asm/uaccess.h> | |
52 | ||
49b6e95f | 53 | #ifdef CONFIG_SPARC |
1da177e4 | 54 | #include <asm/idprom.h> |
49b6e95f | 55 | #include <asm/prom.h> |
1da177e4 LT |
56 | #endif |
57 | ||
63532394 MC |
58 | #define BAR_0 0 |
59 | #define BAR_2 2 | |
60 | ||
1da177e4 LT |
61 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) |
62 | #define TG3_VLAN_TAG_USED 1 | |
63 | #else | |
64 | #define TG3_VLAN_TAG_USED 0 | |
65 | #endif | |
66 | ||
1da177e4 LT |
67 | #include "tg3.h" |
68 | ||
69 | #define DRV_MODULE_NAME "tg3" | |
70 | #define PFX DRV_MODULE_NAME ": " | |
f656f398 MC |
71 | #define DRV_MODULE_VERSION "3.100" |
72 | #define DRV_MODULE_RELDATE "August 25, 2009" | |
1da177e4 LT |
73 | |
74 | #define TG3_DEF_MAC_MODE 0 | |
75 | #define TG3_DEF_RX_MODE 0 | |
76 | #define TG3_DEF_TX_MODE 0 | |
77 | #define TG3_DEF_MSG_ENABLE \ | |
78 | (NETIF_MSG_DRV | \ | |
79 | NETIF_MSG_PROBE | \ | |
80 | NETIF_MSG_LINK | \ | |
81 | NETIF_MSG_TIMER | \ | |
82 | NETIF_MSG_IFDOWN | \ | |
83 | NETIF_MSG_IFUP | \ | |
84 | NETIF_MSG_RX_ERR | \ | |
85 | NETIF_MSG_TX_ERR) | |
86 | ||
87 | /* length of time before we decide the hardware is borked, | |
88 | * and dev->tx_timeout() should be called to fix the problem | |
89 | */ | |
90 | #define TG3_TX_TIMEOUT (5 * HZ) | |
91 | ||
92 | /* hardware minimum and maximum for a single frame's data payload */ | |
93 | #define TG3_MIN_MTU 60 | |
94 | #define TG3_MAX_MTU(tp) \ | |
8f666b07 | 95 | ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500) |
1da177e4 LT |
96 | |
97 | /* These numbers seem to be hard coded in the NIC firmware somehow. | |
98 | * You can't change the ring sizes, but you can change where you place | |
99 | * them in the NIC onboard memory. | |
100 | */ | |
101 | #define TG3_RX_RING_SIZE 512 | |
102 | #define TG3_DEF_RX_RING_PENDING 200 | |
103 | #define TG3_RX_JUMBO_RING_SIZE 256 | |
104 | #define TG3_DEF_RX_JUMBO_RING_PENDING 100 | |
105 | ||
106 | /* Do not place this n-ring entries value into the tp struct itself, | |
107 | * we really want to expose these constants to GCC so that modulo et | |
108 | * al. operations are done with shifts and masks instead of with | |
109 | * hw multiply/modulo instructions. Another solution would be to | |
110 | * replace things like '% foo' with '& (foo - 1)'. | |
111 | */ | |
112 | #define TG3_RX_RCB_RING_SIZE(tp) \ | |
113 | ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024) | |
114 | ||
115 | #define TG3_TX_RING_SIZE 512 | |
116 | #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1) | |
117 | ||
118 | #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \ | |
119 | TG3_RX_RING_SIZE) | |
79ed5ac7 MC |
120 | #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \ |
121 | TG3_RX_JUMBO_RING_SIZE) | |
1da177e4 | 122 | #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \ |
79ed5ac7 | 123 | TG3_RX_RCB_RING_SIZE(tp)) |
1da177e4 LT |
124 | #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \ |
125 | TG3_TX_RING_SIZE) | |
1da177e4 LT |
126 | #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1)) |
127 | ||
287be12e MC |
128 | #define TG3_DMA_BYTE_ENAB 64 |
129 | ||
130 | #define TG3_RX_STD_DMA_SZ 1536 | |
131 | #define TG3_RX_JMB_DMA_SZ 9046 | |
132 | ||
133 | #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB) | |
134 | ||
135 | #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ) | |
136 | #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ) | |
1da177e4 LT |
137 | |
138 | /* minimum number of free TX descriptors required to wake up TX process */ | |
f3f3f27e | 139 | #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4) |
1da177e4 | 140 | |
ad829268 MC |
141 | #define TG3_RAW_IP_ALIGN 2 |
142 | ||
1da177e4 LT |
143 | /* number of ETHTOOL_GSTATS u64's */ |
144 | #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64)) | |
145 | ||
4cafd3f5 MC |
146 | #define TG3_NUM_TEST 6 |
147 | ||
077f849d JSR |
148 | #define FIRMWARE_TG3 "tigon/tg3.bin" |
149 | #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" | |
150 | #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" | |
151 | ||
1da177e4 LT |
152 | static char version[] __devinitdata = |
153 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; | |
154 | ||
155 | MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)"); | |
156 | MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver"); | |
157 | MODULE_LICENSE("GPL"); | |
158 | MODULE_VERSION(DRV_MODULE_VERSION); | |
077f849d JSR |
159 | MODULE_FIRMWARE(FIRMWARE_TG3); |
160 | MODULE_FIRMWARE(FIRMWARE_TG3TSO); | |
161 | MODULE_FIRMWARE(FIRMWARE_TG3TSO5); | |
162 | ||
1da177e4 LT |
163 | |
164 | static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */ | |
165 | module_param(tg3_debug, int, 0); | |
166 | MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value"); | |
167 | ||
168 | static struct pci_device_id tg3_pci_tbl[] = { | |
13185217 HK |
169 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)}, |
170 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)}, | |
171 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)}, | |
172 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)}, | |
173 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)}, | |
174 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)}, | |
175 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)}, | |
176 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)}, | |
177 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)}, | |
178 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)}, | |
179 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)}, | |
180 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)}, | |
181 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)}, | |
182 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)}, | |
183 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)}, | |
184 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)}, | |
185 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)}, | |
186 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)}, | |
187 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)}, | |
188 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)}, | |
189 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)}, | |
190 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)}, | |
191 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)}, | |
192 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)}, | |
126a3368 | 193 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)}, |
13185217 HK |
194 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)}, |
195 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)}, | |
196 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)}, | |
197 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)}, | |
198 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)}, | |
199 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)}, | |
200 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)}, | |
201 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)}, | |
202 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)}, | |
203 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)}, | |
204 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)}, | |
205 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)}, | |
206 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)}, | |
207 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)}, | |
126a3368 | 208 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)}, |
13185217 HK |
209 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)}, |
210 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)}, | |
211 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)}, | |
676917d4 | 212 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)}, |
13185217 HK |
213 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)}, |
214 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)}, | |
215 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)}, | |
216 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)}, | |
217 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)}, | |
218 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)}, | |
219 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)}, | |
b5d3772c MC |
220 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)}, |
221 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)}, | |
d30cdd28 MC |
222 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)}, |
223 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)}, | |
6c7af27c | 224 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)}, |
9936bcf6 MC |
225 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)}, |
226 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)}, | |
c88e668b MC |
227 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)}, |
228 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)}, | |
2befdcea MC |
229 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)}, |
230 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)}, | |
321d32a0 MC |
231 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)}, |
232 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)}, | |
233 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)}, | |
5e7ccf20 | 234 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)}, |
13185217 HK |
235 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, |
236 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, | |
237 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)}, | |
238 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)}, | |
239 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)}, | |
240 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)}, | |
241 | {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)}, | |
242 | {} | |
1da177e4 LT |
243 | }; |
244 | ||
245 | MODULE_DEVICE_TABLE(pci, tg3_pci_tbl); | |
246 | ||
50da859d | 247 | static const struct { |
1da177e4 LT |
248 | const char string[ETH_GSTRING_LEN]; |
249 | } ethtool_stats_keys[TG3_NUM_STATS] = { | |
250 | { "rx_octets" }, | |
251 | { "rx_fragments" }, | |
252 | { "rx_ucast_packets" }, | |
253 | { "rx_mcast_packets" }, | |
254 | { "rx_bcast_packets" }, | |
255 | { "rx_fcs_errors" }, | |
256 | { "rx_align_errors" }, | |
257 | { "rx_xon_pause_rcvd" }, | |
258 | { "rx_xoff_pause_rcvd" }, | |
259 | { "rx_mac_ctrl_rcvd" }, | |
260 | { "rx_xoff_entered" }, | |
261 | { "rx_frame_too_long_errors" }, | |
262 | { "rx_jabbers" }, | |
263 | { "rx_undersize_packets" }, | |
264 | { "rx_in_length_errors" }, | |
265 | { "rx_out_length_errors" }, | |
266 | { "rx_64_or_less_octet_packets" }, | |
267 | { "rx_65_to_127_octet_packets" }, | |
268 | { "rx_128_to_255_octet_packets" }, | |
269 | { "rx_256_to_511_octet_packets" }, | |
270 | { "rx_512_to_1023_octet_packets" }, | |
271 | { "rx_1024_to_1522_octet_packets" }, | |
272 | { "rx_1523_to_2047_octet_packets" }, | |
273 | { "rx_2048_to_4095_octet_packets" }, | |
274 | { "rx_4096_to_8191_octet_packets" }, | |
275 | { "rx_8192_to_9022_octet_packets" }, | |
276 | ||
277 | { "tx_octets" }, | |
278 | { "tx_collisions" }, | |
279 | ||
280 | { "tx_xon_sent" }, | |
281 | { "tx_xoff_sent" }, | |
282 | { "tx_flow_control" }, | |
283 | { "tx_mac_errors" }, | |
284 | { "tx_single_collisions" }, | |
285 | { "tx_mult_collisions" }, | |
286 | { "tx_deferred" }, | |
287 | { "tx_excessive_collisions" }, | |
288 | { "tx_late_collisions" }, | |
289 | { "tx_collide_2times" }, | |
290 | { "tx_collide_3times" }, | |
291 | { "tx_collide_4times" }, | |
292 | { "tx_collide_5times" }, | |
293 | { "tx_collide_6times" }, | |
294 | { "tx_collide_7times" }, | |
295 | { "tx_collide_8times" }, | |
296 | { "tx_collide_9times" }, | |
297 | { "tx_collide_10times" }, | |
298 | { "tx_collide_11times" }, | |
299 | { "tx_collide_12times" }, | |
300 | { "tx_collide_13times" }, | |
301 | { "tx_collide_14times" }, | |
302 | { "tx_collide_15times" }, | |
303 | { "tx_ucast_packets" }, | |
304 | { "tx_mcast_packets" }, | |
305 | { "tx_bcast_packets" }, | |
306 | { "tx_carrier_sense_errors" }, | |
307 | { "tx_discards" }, | |
308 | { "tx_errors" }, | |
309 | ||
310 | { "dma_writeq_full" }, | |
311 | { "dma_write_prioq_full" }, | |
312 | { "rxbds_empty" }, | |
313 | { "rx_discards" }, | |
314 | { "rx_errors" }, | |
315 | { "rx_threshold_hit" }, | |
316 | ||
317 | { "dma_readq_full" }, | |
318 | { "dma_read_prioq_full" }, | |
319 | { "tx_comp_queue_full" }, | |
320 | ||
321 | { "ring_set_send_prod_index" }, | |
322 | { "ring_status_update" }, | |
323 | { "nic_irqs" }, | |
324 | { "nic_avoided_irqs" }, | |
325 | { "nic_tx_threshold_hit" } | |
326 | }; | |
327 | ||
50da859d | 328 | static const struct { |
4cafd3f5 MC |
329 | const char string[ETH_GSTRING_LEN]; |
330 | } ethtool_test_keys[TG3_NUM_TEST] = { | |
331 | { "nvram test (online) " }, | |
332 | { "link test (online) " }, | |
333 | { "register test (offline)" }, | |
334 | { "memory test (offline)" }, | |
335 | { "loopback test (offline)" }, | |
336 | { "interrupt test (offline)" }, | |
337 | }; | |
338 | ||
b401e9e2 MC |
339 | static void tg3_write32(struct tg3 *tp, u32 off, u32 val) |
340 | { | |
341 | writel(val, tp->regs + off); | |
342 | } | |
343 | ||
344 | static u32 tg3_read32(struct tg3 *tp, u32 off) | |
345 | { | |
6aa20a22 | 346 | return (readl(tp->regs + off)); |
b401e9e2 MC |
347 | } |
348 | ||
0d3031d9 MC |
349 | static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) |
350 | { | |
351 | writel(val, tp->aperegs + off); | |
352 | } | |
353 | ||
354 | static u32 tg3_ape_read32(struct tg3 *tp, u32 off) | |
355 | { | |
356 | return (readl(tp->aperegs + off)); | |
357 | } | |
358 | ||
1da177e4 LT |
359 | static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) |
360 | { | |
6892914f MC |
361 | unsigned long flags; |
362 | ||
363 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
1ee582d8 MC |
364 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); |
365 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
6892914f | 366 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1ee582d8 MC |
367 | } |
368 | ||
369 | static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) | |
370 | { | |
371 | writel(val, tp->regs + off); | |
372 | readl(tp->regs + off); | |
1da177e4 LT |
373 | } |
374 | ||
6892914f | 375 | static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) |
1da177e4 | 376 | { |
6892914f MC |
377 | unsigned long flags; |
378 | u32 val; | |
379 | ||
380 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
381 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); | |
382 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
383 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
384 | return val; | |
385 | } | |
386 | ||
387 | static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) | |
388 | { | |
389 | unsigned long flags; | |
390 | ||
391 | if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) { | |
392 | pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + | |
393 | TG3_64BIT_REG_LOW, val); | |
394 | return; | |
395 | } | |
396 | if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) { | |
397 | pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + | |
398 | TG3_64BIT_REG_LOW, val); | |
399 | return; | |
1da177e4 | 400 | } |
6892914f MC |
401 | |
402 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
403 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
404 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
405 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
406 | ||
407 | /* In indirect mode when disabling interrupts, we also need | |
408 | * to clear the interrupt bit in the GRC local ctrl register. | |
409 | */ | |
410 | if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) && | |
411 | (val == 0x1)) { | |
412 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, | |
413 | tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); | |
414 | } | |
415 | } | |
416 | ||
417 | static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) | |
418 | { | |
419 | unsigned long flags; | |
420 | u32 val; | |
421 | ||
422 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
423 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
424 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
425 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
426 | return val; | |
427 | } | |
428 | ||
b401e9e2 MC |
429 | /* usec_wait specifies the wait time in usec when writing to certain registers |
430 | * where it is unsafe to read back the register without some delay. | |
431 | * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power. | |
432 | * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed. | |
433 | */ | |
434 | static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) | |
6892914f | 435 | { |
b401e9e2 MC |
436 | if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) || |
437 | (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)) | |
438 | /* Non-posted methods */ | |
439 | tp->write32(tp, off, val); | |
440 | else { | |
441 | /* Posted method */ | |
442 | tg3_write32(tp, off, val); | |
443 | if (usec_wait) | |
444 | udelay(usec_wait); | |
445 | tp->read32(tp, off); | |
446 | } | |
447 | /* Wait again after the read for the posted method to guarantee that | |
448 | * the wait time is met. | |
449 | */ | |
450 | if (usec_wait) | |
451 | udelay(usec_wait); | |
1da177e4 LT |
452 | } |
453 | ||
09ee929c MC |
454 | static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) |
455 | { | |
456 | tp->write32_mbox(tp, off, val); | |
6892914f MC |
457 | if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) && |
458 | !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)) | |
459 | tp->read32_mbox(tp, off); | |
09ee929c MC |
460 | } |
461 | ||
20094930 | 462 | static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) |
1da177e4 LT |
463 | { |
464 | void __iomem *mbox = tp->regs + off; | |
465 | writel(val, mbox); | |
466 | if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) | |
467 | writel(val, mbox); | |
468 | if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) | |
469 | readl(mbox); | |
470 | } | |
471 | ||
b5d3772c MC |
472 | static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) |
473 | { | |
474 | return (readl(tp->regs + off + GRCMBOX_BASE)); | |
475 | } | |
476 | ||
477 | static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) | |
478 | { | |
479 | writel(val, tp->regs + off + GRCMBOX_BASE); | |
480 | } | |
481 | ||
20094930 | 482 | #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) |
09ee929c | 483 | #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) |
20094930 MC |
484 | #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) |
485 | #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) | |
09ee929c | 486 | #define tr32_mailbox(reg) tp->read32_mbox(tp, reg) |
20094930 MC |
487 | |
488 | #define tw32(reg,val) tp->write32(tp, reg, val) | |
b401e9e2 MC |
489 | #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0) |
490 | #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us)) | |
20094930 | 491 | #define tr32(reg) tp->read32(tp, reg) |
1da177e4 LT |
492 | |
493 | static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) | |
494 | { | |
6892914f MC |
495 | unsigned long flags; |
496 | ||
b5d3772c MC |
497 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) && |
498 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) | |
499 | return; | |
500 | ||
6892914f | 501 | spin_lock_irqsave(&tp->indirect_lock, flags); |
bbadf503 MC |
502 | if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) { |
503 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); | |
504 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 505 | |
bbadf503 MC |
506 | /* Always leave this as zero. */ |
507 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
508 | } else { | |
509 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
510 | tw32_f(TG3PCI_MEM_WIN_DATA, val); | |
28fbef78 | 511 | |
bbadf503 MC |
512 | /* Always leave this as zero. */ |
513 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
514 | } | |
515 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
758a6139 DM |
516 | } |
517 | ||
1da177e4 LT |
518 | static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) |
519 | { | |
6892914f MC |
520 | unsigned long flags; |
521 | ||
b5d3772c MC |
522 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) && |
523 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) { | |
524 | *val = 0; | |
525 | return; | |
526 | } | |
527 | ||
6892914f | 528 | spin_lock_irqsave(&tp->indirect_lock, flags); |
bbadf503 MC |
529 | if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) { |
530 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); | |
531 | pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 532 | |
bbadf503 MC |
533 | /* Always leave this as zero. */ |
534 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
535 | } else { | |
536 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
537 | *val = tr32(TG3PCI_MEM_WIN_DATA); | |
538 | ||
539 | /* Always leave this as zero. */ | |
540 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
541 | } | |
6892914f | 542 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1da177e4 LT |
543 | } |
544 | ||
0d3031d9 MC |
545 | static void tg3_ape_lock_init(struct tg3 *tp) |
546 | { | |
547 | int i; | |
548 | ||
549 | /* Make sure the driver hasn't any stale locks. */ | |
550 | for (i = 0; i < 8; i++) | |
551 | tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i, | |
552 | APE_LOCK_GRANT_DRIVER); | |
553 | } | |
554 | ||
555 | static int tg3_ape_lock(struct tg3 *tp, int locknum) | |
556 | { | |
557 | int i, off; | |
558 | int ret = 0; | |
559 | u32 status; | |
560 | ||
561 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
562 | return 0; | |
563 | ||
564 | switch (locknum) { | |
77b483f1 | 565 | case TG3_APE_LOCK_GRC: |
0d3031d9 MC |
566 | case TG3_APE_LOCK_MEM: |
567 | break; | |
568 | default: | |
569 | return -EINVAL; | |
570 | } | |
571 | ||
572 | off = 4 * locknum; | |
573 | ||
574 | tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER); | |
575 | ||
576 | /* Wait for up to 1 millisecond to acquire lock. */ | |
577 | for (i = 0; i < 100; i++) { | |
578 | status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off); | |
579 | if (status == APE_LOCK_GRANT_DRIVER) | |
580 | break; | |
581 | udelay(10); | |
582 | } | |
583 | ||
584 | if (status != APE_LOCK_GRANT_DRIVER) { | |
585 | /* Revoke the lock request. */ | |
586 | tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, | |
587 | APE_LOCK_GRANT_DRIVER); | |
588 | ||
589 | ret = -EBUSY; | |
590 | } | |
591 | ||
592 | return ret; | |
593 | } | |
594 | ||
595 | static void tg3_ape_unlock(struct tg3 *tp, int locknum) | |
596 | { | |
597 | int off; | |
598 | ||
599 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
600 | return; | |
601 | ||
602 | switch (locknum) { | |
77b483f1 | 603 | case TG3_APE_LOCK_GRC: |
0d3031d9 MC |
604 | case TG3_APE_LOCK_MEM: |
605 | break; | |
606 | default: | |
607 | return; | |
608 | } | |
609 | ||
610 | off = 4 * locknum; | |
611 | tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER); | |
612 | } | |
613 | ||
1da177e4 LT |
614 | static void tg3_disable_ints(struct tg3 *tp) |
615 | { | |
616 | tw32(TG3PCI_MISC_HOST_CTRL, | |
617 | (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); | |
898a56f8 | 618 | tw32_mailbox_f(tp->napi[0].int_mbox, 0x00000001); |
1da177e4 LT |
619 | } |
620 | ||
621 | static inline void tg3_cond_int(struct tg3 *tp) | |
622 | { | |
38f3843e | 623 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && |
898a56f8 | 624 | (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) |
1da177e4 | 625 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); |
b5d3772c MC |
626 | else |
627 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
628 | (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW)); | |
1da177e4 LT |
629 | } |
630 | ||
631 | static void tg3_enable_ints(struct tg3 *tp) | |
632 | { | |
898a56f8 | 633 | struct tg3_napi *tnapi = &tp->napi[0]; |
bbe832c0 MC |
634 | tp->irq_sync = 0; |
635 | wmb(); | |
636 | ||
1da177e4 LT |
637 | tw32(TG3PCI_MISC_HOST_CTRL, |
638 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); | |
898a56f8 | 639 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
fcfa0a32 | 640 | if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) |
898a56f8 | 641 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
1da177e4 LT |
642 | tg3_cond_int(tp); |
643 | } | |
644 | ||
17375d25 | 645 | static inline unsigned int tg3_has_work(struct tg3_napi *tnapi) |
04237ddd | 646 | { |
17375d25 | 647 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 648 | struct tg3_hw_status *sblk = tnapi->hw_status; |
04237ddd MC |
649 | unsigned int work_exists = 0; |
650 | ||
651 | /* check for phy events */ | |
652 | if (!(tp->tg3_flags & | |
653 | (TG3_FLAG_USE_LINKCHG_REG | | |
654 | TG3_FLAG_POLL_SERDES))) { | |
655 | if (sblk->status & SD_STATUS_LINK_CHG) | |
656 | work_exists = 1; | |
657 | } | |
658 | /* check for RX/TX work to do */ | |
f3f3f27e | 659 | if (sblk->idx[0].tx_consumer != tnapi->tx_cons || |
72334482 | 660 | sblk->idx[0].rx_producer != tnapi->rx_rcb_ptr) |
04237ddd MC |
661 | work_exists = 1; |
662 | ||
663 | return work_exists; | |
664 | } | |
665 | ||
17375d25 | 666 | /* tg3_int_reenable |
04237ddd MC |
667 | * similar to tg3_enable_ints, but it accurately determines whether there |
668 | * is new work pending and can return without flushing the PIO write | |
6aa20a22 | 669 | * which reenables interrupts |
1da177e4 | 670 | */ |
17375d25 | 671 | static void tg3_int_reenable(struct tg3_napi *tnapi) |
1da177e4 | 672 | { |
17375d25 MC |
673 | struct tg3 *tp = tnapi->tp; |
674 | ||
898a56f8 | 675 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); |
1da177e4 LT |
676 | mmiowb(); |
677 | ||
fac9b83e DM |
678 | /* When doing tagged status, this work check is unnecessary. |
679 | * The last_tag we write above tells the chip which piece of | |
680 | * work we've completed. | |
681 | */ | |
682 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && | |
17375d25 | 683 | tg3_has_work(tnapi)) |
04237ddd MC |
684 | tw32(HOSTCC_MODE, tp->coalesce_mode | |
685 | (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW)); | |
1da177e4 LT |
686 | } |
687 | ||
688 | static inline void tg3_netif_stop(struct tg3 *tp) | |
689 | { | |
bbe832c0 | 690 | tp->dev->trans_start = jiffies; /* prevent tx timeout */ |
8ef0442f | 691 | napi_disable(&tp->napi[0].napi); |
1da177e4 LT |
692 | netif_tx_disable(tp->dev); |
693 | } | |
694 | ||
695 | static inline void tg3_netif_start(struct tg3 *tp) | |
696 | { | |
898a56f8 | 697 | struct tg3_napi *tnapi = &tp->napi[0]; |
1da177e4 LT |
698 | netif_wake_queue(tp->dev); |
699 | /* NOTE: unconditional netif_wake_queue is only appropriate | |
700 | * so long as all callers are assured to have free tx slots | |
701 | * (such as after tg3_init_hw) | |
702 | */ | |
898a56f8 MC |
703 | napi_enable(&tnapi->napi); |
704 | tnapi->hw_status->status |= SD_STATUS_UPDATED; | |
f47c11ee | 705 | tg3_enable_ints(tp); |
1da177e4 LT |
706 | } |
707 | ||
708 | static void tg3_switch_clocks(struct tg3 *tp) | |
709 | { | |
710 | u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); | |
711 | u32 orig_clock_ctrl; | |
712 | ||
795d01c5 MC |
713 | if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || |
714 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
4cf78e4f MC |
715 | return; |
716 | ||
1da177e4 LT |
717 | orig_clock_ctrl = clock_ctrl; |
718 | clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | | |
719 | CLOCK_CTRL_CLKRUN_OENABLE | | |
720 | 0x1f); | |
721 | tp->pci_clock_ctrl = clock_ctrl; | |
722 | ||
723 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
724 | if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) { | |
b401e9e2 MC |
725 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
726 | clock_ctrl | CLOCK_CTRL_625_CORE, 40); | |
1da177e4 LT |
727 | } |
728 | } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { | |
b401e9e2 MC |
729 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
730 | clock_ctrl | | |
731 | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK), | |
732 | 40); | |
733 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
734 | clock_ctrl | (CLOCK_CTRL_ALTCLK), | |
735 | 40); | |
1da177e4 | 736 | } |
b401e9e2 | 737 | tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40); |
1da177e4 LT |
738 | } |
739 | ||
740 | #define PHY_BUSY_LOOPS 5000 | |
741 | ||
742 | static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) | |
743 | { | |
744 | u32 frame_val; | |
745 | unsigned int loops; | |
746 | int ret; | |
747 | ||
748 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
749 | tw32_f(MAC_MI_MODE, | |
750 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
751 | udelay(80); | |
752 | } | |
753 | ||
754 | *val = 0x0; | |
755 | ||
756 | frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) & | |
757 | MI_COM_PHY_ADDR_MASK); | |
758 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
759 | MI_COM_REG_ADDR_MASK); | |
760 | frame_val |= (MI_COM_CMD_READ | MI_COM_START); | |
6aa20a22 | 761 | |
1da177e4 LT |
762 | tw32_f(MAC_MI_COM, frame_val); |
763 | ||
764 | loops = PHY_BUSY_LOOPS; | |
765 | while (loops != 0) { | |
766 | udelay(10); | |
767 | frame_val = tr32(MAC_MI_COM); | |
768 | ||
769 | if ((frame_val & MI_COM_BUSY) == 0) { | |
770 | udelay(5); | |
771 | frame_val = tr32(MAC_MI_COM); | |
772 | break; | |
773 | } | |
774 | loops -= 1; | |
775 | } | |
776 | ||
777 | ret = -EBUSY; | |
778 | if (loops != 0) { | |
779 | *val = frame_val & MI_COM_DATA_MASK; | |
780 | ret = 0; | |
781 | } | |
782 | ||
783 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
784 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
785 | udelay(80); | |
786 | } | |
787 | ||
788 | return ret; | |
789 | } | |
790 | ||
791 | static int tg3_writephy(struct tg3 *tp, int reg, u32 val) | |
792 | { | |
793 | u32 frame_val; | |
794 | unsigned int loops; | |
795 | int ret; | |
796 | ||
7f97a4bd | 797 | if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) && |
b5d3772c MC |
798 | (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL)) |
799 | return 0; | |
800 | ||
1da177e4 LT |
801 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
802 | tw32_f(MAC_MI_MODE, | |
803 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
804 | udelay(80); | |
805 | } | |
806 | ||
807 | frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) & | |
808 | MI_COM_PHY_ADDR_MASK); | |
809 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
810 | MI_COM_REG_ADDR_MASK); | |
811 | frame_val |= (val & MI_COM_DATA_MASK); | |
812 | frame_val |= (MI_COM_CMD_WRITE | MI_COM_START); | |
6aa20a22 | 813 | |
1da177e4 LT |
814 | tw32_f(MAC_MI_COM, frame_val); |
815 | ||
816 | loops = PHY_BUSY_LOOPS; | |
817 | while (loops != 0) { | |
818 | udelay(10); | |
819 | frame_val = tr32(MAC_MI_COM); | |
820 | if ((frame_val & MI_COM_BUSY) == 0) { | |
821 | udelay(5); | |
822 | frame_val = tr32(MAC_MI_COM); | |
823 | break; | |
824 | } | |
825 | loops -= 1; | |
826 | } | |
827 | ||
828 | ret = -EBUSY; | |
829 | if (loops != 0) | |
830 | ret = 0; | |
831 | ||
832 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
833 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
834 | udelay(80); | |
835 | } | |
836 | ||
837 | return ret; | |
838 | } | |
839 | ||
95e2869a MC |
840 | static int tg3_bmcr_reset(struct tg3 *tp) |
841 | { | |
842 | u32 phy_control; | |
843 | int limit, err; | |
844 | ||
845 | /* OK, reset it, and poll the BMCR_RESET bit until it | |
846 | * clears or we time out. | |
847 | */ | |
848 | phy_control = BMCR_RESET; | |
849 | err = tg3_writephy(tp, MII_BMCR, phy_control); | |
850 | if (err != 0) | |
851 | return -EBUSY; | |
852 | ||
853 | limit = 5000; | |
854 | while (limit--) { | |
855 | err = tg3_readphy(tp, MII_BMCR, &phy_control); | |
856 | if (err != 0) | |
857 | return -EBUSY; | |
858 | ||
859 | if ((phy_control & BMCR_RESET) == 0) { | |
860 | udelay(40); | |
861 | break; | |
862 | } | |
863 | udelay(10); | |
864 | } | |
d4675b52 | 865 | if (limit < 0) |
95e2869a MC |
866 | return -EBUSY; |
867 | ||
868 | return 0; | |
869 | } | |
870 | ||
158d7abd MC |
871 | static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg) |
872 | { | |
3d16543d | 873 | struct tg3 *tp = bp->priv; |
158d7abd MC |
874 | u32 val; |
875 | ||
876 | if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED) | |
877 | return -EAGAIN; | |
878 | ||
879 | if (tg3_readphy(tp, reg, &val)) | |
880 | return -EIO; | |
881 | ||
882 | return val; | |
883 | } | |
884 | ||
885 | static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val) | |
886 | { | |
3d16543d | 887 | struct tg3 *tp = bp->priv; |
158d7abd MC |
888 | |
889 | if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED) | |
890 | return -EAGAIN; | |
891 | ||
892 | if (tg3_writephy(tp, reg, val)) | |
893 | return -EIO; | |
894 | ||
895 | return 0; | |
896 | } | |
897 | ||
898 | static int tg3_mdio_reset(struct mii_bus *bp) | |
899 | { | |
900 | return 0; | |
901 | } | |
902 | ||
9c61d6bc | 903 | static void tg3_mdio_config_5785(struct tg3 *tp) |
a9daf367 MC |
904 | { |
905 | u32 val; | |
fcb389df | 906 | struct phy_device *phydev; |
a9daf367 | 907 | |
fcb389df MC |
908 | phydev = tp->mdio_bus->phy_map[PHY_ADDR]; |
909 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { | |
910 | case TG3_PHY_ID_BCM50610: | |
911 | val = MAC_PHYCFG2_50610_LED_MODES; | |
912 | break; | |
913 | case TG3_PHY_ID_BCMAC131: | |
914 | val = MAC_PHYCFG2_AC131_LED_MODES; | |
915 | break; | |
916 | case TG3_PHY_ID_RTL8211C: | |
917 | val = MAC_PHYCFG2_RTL8211C_LED_MODES; | |
918 | break; | |
919 | case TG3_PHY_ID_RTL8201E: | |
920 | val = MAC_PHYCFG2_RTL8201E_LED_MODES; | |
921 | break; | |
922 | default: | |
a9daf367 | 923 | return; |
fcb389df MC |
924 | } |
925 | ||
926 | if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { | |
927 | tw32(MAC_PHYCFG2, val); | |
928 | ||
929 | val = tr32(MAC_PHYCFG1); | |
bb85fbb6 MC |
930 | val &= ~(MAC_PHYCFG1_RGMII_INT | |
931 | MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK); | |
932 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT; | |
fcb389df MC |
933 | tw32(MAC_PHYCFG1, val); |
934 | ||
935 | return; | |
936 | } | |
937 | ||
938 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) | |
939 | val |= MAC_PHYCFG2_EMODE_MASK_MASK | | |
940 | MAC_PHYCFG2_FMODE_MASK_MASK | | |
941 | MAC_PHYCFG2_GMODE_MASK_MASK | | |
942 | MAC_PHYCFG2_ACT_MASK_MASK | | |
943 | MAC_PHYCFG2_QUAL_MASK_MASK | | |
944 | MAC_PHYCFG2_INBAND_ENABLE; | |
945 | ||
946 | tw32(MAC_PHYCFG2, val); | |
a9daf367 | 947 | |
bb85fbb6 MC |
948 | val = tr32(MAC_PHYCFG1); |
949 | val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK | | |
950 | MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN); | |
951 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) { | |
a9daf367 MC |
952 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) |
953 | val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC; | |
954 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
955 | val |= MAC_PHYCFG1_RGMII_SND_STAT_EN; | |
956 | } | |
bb85fbb6 MC |
957 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT | |
958 | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV; | |
959 | tw32(MAC_PHYCFG1, val); | |
a9daf367 | 960 | |
a9daf367 MC |
961 | val = tr32(MAC_EXT_RGMII_MODE); |
962 | val &= ~(MAC_RGMII_MODE_RX_INT_B | | |
963 | MAC_RGMII_MODE_RX_QUALITY | | |
964 | MAC_RGMII_MODE_RX_ACTIVITY | | |
965 | MAC_RGMII_MODE_RX_ENG_DET | | |
966 | MAC_RGMII_MODE_TX_ENABLE | | |
967 | MAC_RGMII_MODE_TX_LOWPWR | | |
968 | MAC_RGMII_MODE_TX_RESET); | |
fcb389df | 969 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) { |
a9daf367 MC |
970 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) |
971 | val |= MAC_RGMII_MODE_RX_INT_B | | |
972 | MAC_RGMII_MODE_RX_QUALITY | | |
973 | MAC_RGMII_MODE_RX_ACTIVITY | | |
974 | MAC_RGMII_MODE_RX_ENG_DET; | |
975 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
976 | val |= MAC_RGMII_MODE_TX_ENABLE | | |
977 | MAC_RGMII_MODE_TX_LOWPWR | | |
978 | MAC_RGMII_MODE_TX_RESET; | |
979 | } | |
980 | tw32(MAC_EXT_RGMII_MODE, val); | |
981 | } | |
982 | ||
158d7abd MC |
983 | static void tg3_mdio_start(struct tg3 *tp) |
984 | { | |
985 | if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) { | |
298cf9be | 986 | mutex_lock(&tp->mdio_bus->mdio_lock); |
158d7abd | 987 | tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED; |
298cf9be | 988 | mutex_unlock(&tp->mdio_bus->mdio_lock); |
158d7abd MC |
989 | } |
990 | ||
991 | tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; | |
992 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
993 | udelay(80); | |
a9daf367 | 994 | |
9c61d6bc MC |
995 | if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) && |
996 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
997 | tg3_mdio_config_5785(tp); | |
158d7abd MC |
998 | } |
999 | ||
1000 | static void tg3_mdio_stop(struct tg3 *tp) | |
1001 | { | |
1002 | if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) { | |
298cf9be | 1003 | mutex_lock(&tp->mdio_bus->mdio_lock); |
158d7abd | 1004 | tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED; |
298cf9be | 1005 | mutex_unlock(&tp->mdio_bus->mdio_lock); |
158d7abd MC |
1006 | } |
1007 | } | |
1008 | ||
1009 | static int tg3_mdio_init(struct tg3 *tp) | |
1010 | { | |
1011 | int i; | |
1012 | u32 reg; | |
a9daf367 | 1013 | struct phy_device *phydev; |
158d7abd MC |
1014 | |
1015 | tg3_mdio_start(tp); | |
1016 | ||
1017 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) || | |
1018 | (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED)) | |
1019 | return 0; | |
1020 | ||
298cf9be LB |
1021 | tp->mdio_bus = mdiobus_alloc(); |
1022 | if (tp->mdio_bus == NULL) | |
1023 | return -ENOMEM; | |
158d7abd | 1024 | |
298cf9be LB |
1025 | tp->mdio_bus->name = "tg3 mdio bus"; |
1026 | snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", | |
158d7abd | 1027 | (tp->pdev->bus->number << 8) | tp->pdev->devfn); |
298cf9be LB |
1028 | tp->mdio_bus->priv = tp; |
1029 | tp->mdio_bus->parent = &tp->pdev->dev; | |
1030 | tp->mdio_bus->read = &tg3_mdio_read; | |
1031 | tp->mdio_bus->write = &tg3_mdio_write; | |
1032 | tp->mdio_bus->reset = &tg3_mdio_reset; | |
1033 | tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR); | |
1034 | tp->mdio_bus->irq = &tp->mdio_irq[0]; | |
158d7abd MC |
1035 | |
1036 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
298cf9be | 1037 | tp->mdio_bus->irq[i] = PHY_POLL; |
158d7abd MC |
1038 | |
1039 | /* The bus registration will look for all the PHYs on the mdio bus. | |
1040 | * Unfortunately, it does not ensure the PHY is powered up before | |
1041 | * accessing the PHY ID registers. A chip reset is the | |
1042 | * quickest way to bring the device back to an operational state.. | |
1043 | */ | |
1044 | if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) | |
1045 | tg3_bmcr_reset(tp); | |
1046 | ||
298cf9be | 1047 | i = mdiobus_register(tp->mdio_bus); |
a9daf367 | 1048 | if (i) { |
158d7abd MC |
1049 | printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n", |
1050 | tp->dev->name, i); | |
9c61d6bc | 1051 | mdiobus_free(tp->mdio_bus); |
a9daf367 MC |
1052 | return i; |
1053 | } | |
158d7abd | 1054 | |
298cf9be | 1055 | phydev = tp->mdio_bus->phy_map[PHY_ADDR]; |
a9daf367 | 1056 | |
9c61d6bc MC |
1057 | if (!phydev || !phydev->drv) { |
1058 | printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name); | |
1059 | mdiobus_unregister(tp->mdio_bus); | |
1060 | mdiobus_free(tp->mdio_bus); | |
1061 | return -ENODEV; | |
1062 | } | |
1063 | ||
1064 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { | |
321d32a0 MC |
1065 | case TG3_PHY_ID_BCM57780: |
1066 | phydev->interface = PHY_INTERFACE_MODE_GMII; | |
1067 | break; | |
a9daf367 | 1068 | case TG3_PHY_ID_BCM50610: |
a9daf367 MC |
1069 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) |
1070 | phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; | |
1071 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) | |
1072 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE; | |
1073 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
1074 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; | |
fcb389df MC |
1075 | /* fallthru */ |
1076 | case TG3_PHY_ID_RTL8211C: | |
1077 | phydev->interface = PHY_INTERFACE_MODE_RGMII; | |
a9daf367 | 1078 | break; |
fcb389df | 1079 | case TG3_PHY_ID_RTL8201E: |
a9daf367 MC |
1080 | case TG3_PHY_ID_BCMAC131: |
1081 | phydev->interface = PHY_INTERFACE_MODE_MII; | |
7f97a4bd | 1082 | tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET; |
a9daf367 MC |
1083 | break; |
1084 | } | |
1085 | ||
9c61d6bc MC |
1086 | tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED; |
1087 | ||
1088 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1089 | tg3_mdio_config_5785(tp); | |
a9daf367 MC |
1090 | |
1091 | return 0; | |
158d7abd MC |
1092 | } |
1093 | ||
1094 | static void tg3_mdio_fini(struct tg3 *tp) | |
1095 | { | |
1096 | if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) { | |
1097 | tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED; | |
298cf9be LB |
1098 | mdiobus_unregister(tp->mdio_bus); |
1099 | mdiobus_free(tp->mdio_bus); | |
158d7abd MC |
1100 | tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED; |
1101 | } | |
1102 | } | |
1103 | ||
4ba526ce MC |
1104 | /* tp->lock is held. */ |
1105 | static inline void tg3_generate_fw_event(struct tg3 *tp) | |
1106 | { | |
1107 | u32 val; | |
1108 | ||
1109 | val = tr32(GRC_RX_CPU_EVENT); | |
1110 | val |= GRC_RX_CPU_DRIVER_EVENT; | |
1111 | tw32_f(GRC_RX_CPU_EVENT, val); | |
1112 | ||
1113 | tp->last_event_jiffies = jiffies; | |
1114 | } | |
1115 | ||
1116 | #define TG3_FW_EVENT_TIMEOUT_USEC 2500 | |
1117 | ||
95e2869a MC |
1118 | /* tp->lock is held. */ |
1119 | static void tg3_wait_for_event_ack(struct tg3 *tp) | |
1120 | { | |
1121 | int i; | |
4ba526ce MC |
1122 | unsigned int delay_cnt; |
1123 | long time_remain; | |
1124 | ||
1125 | /* If enough time has passed, no wait is necessary. */ | |
1126 | time_remain = (long)(tp->last_event_jiffies + 1 + | |
1127 | usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - | |
1128 | (long)jiffies; | |
1129 | if (time_remain < 0) | |
1130 | return; | |
1131 | ||
1132 | /* Check if we can shorten the wait time. */ | |
1133 | delay_cnt = jiffies_to_usecs(time_remain); | |
1134 | if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC) | |
1135 | delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC; | |
1136 | delay_cnt = (delay_cnt >> 3) + 1; | |
95e2869a | 1137 | |
4ba526ce | 1138 | for (i = 0; i < delay_cnt; i++) { |
95e2869a MC |
1139 | if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) |
1140 | break; | |
4ba526ce | 1141 | udelay(8); |
95e2869a MC |
1142 | } |
1143 | } | |
1144 | ||
1145 | /* tp->lock is held. */ | |
1146 | static void tg3_ump_link_report(struct tg3 *tp) | |
1147 | { | |
1148 | u32 reg; | |
1149 | u32 val; | |
1150 | ||
1151 | if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || | |
1152 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
1153 | return; | |
1154 | ||
1155 | tg3_wait_for_event_ack(tp); | |
1156 | ||
1157 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); | |
1158 | ||
1159 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); | |
1160 | ||
1161 | val = 0; | |
1162 | if (!tg3_readphy(tp, MII_BMCR, ®)) | |
1163 | val = reg << 16; | |
1164 | if (!tg3_readphy(tp, MII_BMSR, ®)) | |
1165 | val |= (reg & 0xffff); | |
1166 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val); | |
1167 | ||
1168 | val = 0; | |
1169 | if (!tg3_readphy(tp, MII_ADVERTISE, ®)) | |
1170 | val = reg << 16; | |
1171 | if (!tg3_readphy(tp, MII_LPA, ®)) | |
1172 | val |= (reg & 0xffff); | |
1173 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val); | |
1174 | ||
1175 | val = 0; | |
1176 | if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) { | |
1177 | if (!tg3_readphy(tp, MII_CTRL1000, ®)) | |
1178 | val = reg << 16; | |
1179 | if (!tg3_readphy(tp, MII_STAT1000, ®)) | |
1180 | val |= (reg & 0xffff); | |
1181 | } | |
1182 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val); | |
1183 | ||
1184 | if (!tg3_readphy(tp, MII_PHYADDR, ®)) | |
1185 | val = reg << 16; | |
1186 | else | |
1187 | val = 0; | |
1188 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val); | |
1189 | ||
4ba526ce | 1190 | tg3_generate_fw_event(tp); |
95e2869a MC |
1191 | } |
1192 | ||
1193 | static void tg3_link_report(struct tg3 *tp) | |
1194 | { | |
1195 | if (!netif_carrier_ok(tp->dev)) { | |
1196 | if (netif_msg_link(tp)) | |
1197 | printk(KERN_INFO PFX "%s: Link is down.\n", | |
1198 | tp->dev->name); | |
1199 | tg3_ump_link_report(tp); | |
1200 | } else if (netif_msg_link(tp)) { | |
1201 | printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n", | |
1202 | tp->dev->name, | |
1203 | (tp->link_config.active_speed == SPEED_1000 ? | |
1204 | 1000 : | |
1205 | (tp->link_config.active_speed == SPEED_100 ? | |
1206 | 100 : 10)), | |
1207 | (tp->link_config.active_duplex == DUPLEX_FULL ? | |
1208 | "full" : "half")); | |
1209 | ||
1210 | printk(KERN_INFO PFX | |
1211 | "%s: Flow control is %s for TX and %s for RX.\n", | |
1212 | tp->dev->name, | |
e18ce346 | 1213 | (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? |
95e2869a | 1214 | "on" : "off", |
e18ce346 | 1215 | (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? |
95e2869a MC |
1216 | "on" : "off"); |
1217 | tg3_ump_link_report(tp); | |
1218 | } | |
1219 | } | |
1220 | ||
1221 | static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl) | |
1222 | { | |
1223 | u16 miireg; | |
1224 | ||
e18ce346 | 1225 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1226 | miireg = ADVERTISE_PAUSE_CAP; |
e18ce346 | 1227 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1228 | miireg = ADVERTISE_PAUSE_ASYM; |
e18ce346 | 1229 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1230 | miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1231 | else | |
1232 | miireg = 0; | |
1233 | ||
1234 | return miireg; | |
1235 | } | |
1236 | ||
1237 | static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) | |
1238 | { | |
1239 | u16 miireg; | |
1240 | ||
e18ce346 | 1241 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1242 | miireg = ADVERTISE_1000XPAUSE; |
e18ce346 | 1243 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1244 | miireg = ADVERTISE_1000XPSE_ASYM; |
e18ce346 | 1245 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1246 | miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; |
1247 | else | |
1248 | miireg = 0; | |
1249 | ||
1250 | return miireg; | |
1251 | } | |
1252 | ||
95e2869a MC |
1253 | static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) |
1254 | { | |
1255 | u8 cap = 0; | |
1256 | ||
1257 | if (lcladv & ADVERTISE_1000XPAUSE) { | |
1258 | if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1259 | if (rmtadv & LPA_1000XPAUSE) | |
e18ce346 | 1260 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; |
95e2869a | 1261 | else if (rmtadv & LPA_1000XPAUSE_ASYM) |
e18ce346 | 1262 | cap = FLOW_CTRL_RX; |
95e2869a MC |
1263 | } else { |
1264 | if (rmtadv & LPA_1000XPAUSE) | |
e18ce346 | 1265 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; |
95e2869a MC |
1266 | } |
1267 | } else if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1268 | if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM)) | |
e18ce346 | 1269 | cap = FLOW_CTRL_TX; |
95e2869a MC |
1270 | } |
1271 | ||
1272 | return cap; | |
1273 | } | |
1274 | ||
f51f3562 | 1275 | static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) |
95e2869a | 1276 | { |
b02fd9e3 | 1277 | u8 autoneg; |
f51f3562 | 1278 | u8 flowctrl = 0; |
95e2869a MC |
1279 | u32 old_rx_mode = tp->rx_mode; |
1280 | u32 old_tx_mode = tp->tx_mode; | |
1281 | ||
b02fd9e3 | 1282 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) |
298cf9be | 1283 | autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg; |
b02fd9e3 MC |
1284 | else |
1285 | autoneg = tp->link_config.autoneg; | |
1286 | ||
1287 | if (autoneg == AUTONEG_ENABLE && | |
95e2869a MC |
1288 | (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) { |
1289 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) | |
f51f3562 | 1290 | flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv); |
95e2869a | 1291 | else |
bc02ff95 | 1292 | flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
f51f3562 MC |
1293 | } else |
1294 | flowctrl = tp->link_config.flowctrl; | |
95e2869a | 1295 | |
f51f3562 | 1296 | tp->link_config.active_flowctrl = flowctrl; |
95e2869a | 1297 | |
e18ce346 | 1298 | if (flowctrl & FLOW_CTRL_RX) |
95e2869a MC |
1299 | tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; |
1300 | else | |
1301 | tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; | |
1302 | ||
f51f3562 | 1303 | if (old_rx_mode != tp->rx_mode) |
95e2869a | 1304 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
95e2869a | 1305 | |
e18ce346 | 1306 | if (flowctrl & FLOW_CTRL_TX) |
95e2869a MC |
1307 | tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; |
1308 | else | |
1309 | tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; | |
1310 | ||
f51f3562 | 1311 | if (old_tx_mode != tp->tx_mode) |
95e2869a | 1312 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
95e2869a MC |
1313 | } |
1314 | ||
b02fd9e3 MC |
1315 | static void tg3_adjust_link(struct net_device *dev) |
1316 | { | |
1317 | u8 oldflowctrl, linkmesg = 0; | |
1318 | u32 mac_mode, lcl_adv, rmt_adv; | |
1319 | struct tg3 *tp = netdev_priv(dev); | |
298cf9be | 1320 | struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR]; |
b02fd9e3 MC |
1321 | |
1322 | spin_lock(&tp->lock); | |
1323 | ||
1324 | mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | | |
1325 | MAC_MODE_HALF_DUPLEX); | |
1326 | ||
1327 | oldflowctrl = tp->link_config.active_flowctrl; | |
1328 | ||
1329 | if (phydev->link) { | |
1330 | lcl_adv = 0; | |
1331 | rmt_adv = 0; | |
1332 | ||
1333 | if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) | |
1334 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
1335 | else | |
1336 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
1337 | ||
1338 | if (phydev->duplex == DUPLEX_HALF) | |
1339 | mac_mode |= MAC_MODE_HALF_DUPLEX; | |
1340 | else { | |
1341 | lcl_adv = tg3_advert_flowctrl_1000T( | |
1342 | tp->link_config.flowctrl); | |
1343 | ||
1344 | if (phydev->pause) | |
1345 | rmt_adv = LPA_PAUSE_CAP; | |
1346 | if (phydev->asym_pause) | |
1347 | rmt_adv |= LPA_PAUSE_ASYM; | |
1348 | } | |
1349 | ||
1350 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1351 | } else | |
1352 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
1353 | ||
1354 | if (mac_mode != tp->mac_mode) { | |
1355 | tp->mac_mode = mac_mode; | |
1356 | tw32_f(MAC_MODE, tp->mac_mode); | |
1357 | udelay(40); | |
1358 | } | |
1359 | ||
fcb389df MC |
1360 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
1361 | if (phydev->speed == SPEED_10) | |
1362 | tw32(MAC_MI_STAT, | |
1363 | MAC_MI_STAT_10MBPS_MODE | | |
1364 | MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1365 | else | |
1366 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1367 | } | |
1368 | ||
b02fd9e3 MC |
1369 | if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) |
1370 | tw32(MAC_TX_LENGTHS, | |
1371 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1372 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1373 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1374 | else | |
1375 | tw32(MAC_TX_LENGTHS, | |
1376 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1377 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1378 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1379 | ||
1380 | if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) || | |
1381 | (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) || | |
1382 | phydev->speed != tp->link_config.active_speed || | |
1383 | phydev->duplex != tp->link_config.active_duplex || | |
1384 | oldflowctrl != tp->link_config.active_flowctrl) | |
1385 | linkmesg = 1; | |
1386 | ||
1387 | tp->link_config.active_speed = phydev->speed; | |
1388 | tp->link_config.active_duplex = phydev->duplex; | |
1389 | ||
1390 | spin_unlock(&tp->lock); | |
1391 | ||
1392 | if (linkmesg) | |
1393 | tg3_link_report(tp); | |
1394 | } | |
1395 | ||
1396 | static int tg3_phy_init(struct tg3 *tp) | |
1397 | { | |
1398 | struct phy_device *phydev; | |
1399 | ||
1400 | if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) | |
1401 | return 0; | |
1402 | ||
1403 | /* Bring the PHY back to a known state. */ | |
1404 | tg3_bmcr_reset(tp); | |
1405 | ||
298cf9be | 1406 | phydev = tp->mdio_bus->phy_map[PHY_ADDR]; |
b02fd9e3 MC |
1407 | |
1408 | /* Attach the MAC to the PHY. */ | |
fb28ad35 | 1409 | phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link, |
a9daf367 | 1410 | phydev->dev_flags, phydev->interface); |
b02fd9e3 MC |
1411 | if (IS_ERR(phydev)) { |
1412 | printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name); | |
1413 | return PTR_ERR(phydev); | |
1414 | } | |
1415 | ||
b02fd9e3 | 1416 | /* Mask with MAC supported features. */ |
9c61d6bc MC |
1417 | switch (phydev->interface) { |
1418 | case PHY_INTERFACE_MODE_GMII: | |
1419 | case PHY_INTERFACE_MODE_RGMII: | |
321d32a0 MC |
1420 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) { |
1421 | phydev->supported &= (PHY_GBIT_FEATURES | | |
1422 | SUPPORTED_Pause | | |
1423 | SUPPORTED_Asym_Pause); | |
1424 | break; | |
1425 | } | |
1426 | /* fallthru */ | |
9c61d6bc MC |
1427 | case PHY_INTERFACE_MODE_MII: |
1428 | phydev->supported &= (PHY_BASIC_FEATURES | | |
1429 | SUPPORTED_Pause | | |
1430 | SUPPORTED_Asym_Pause); | |
1431 | break; | |
1432 | default: | |
1433 | phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]); | |
1434 | return -EINVAL; | |
1435 | } | |
1436 | ||
1437 | tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED; | |
b02fd9e3 MC |
1438 | |
1439 | phydev->advertising = phydev->supported; | |
1440 | ||
b02fd9e3 MC |
1441 | return 0; |
1442 | } | |
1443 | ||
1444 | static void tg3_phy_start(struct tg3 *tp) | |
1445 | { | |
1446 | struct phy_device *phydev; | |
1447 | ||
1448 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
1449 | return; | |
1450 | ||
298cf9be | 1451 | phydev = tp->mdio_bus->phy_map[PHY_ADDR]; |
b02fd9e3 MC |
1452 | |
1453 | if (tp->link_config.phy_is_low_power) { | |
1454 | tp->link_config.phy_is_low_power = 0; | |
1455 | phydev->speed = tp->link_config.orig_speed; | |
1456 | phydev->duplex = tp->link_config.orig_duplex; | |
1457 | phydev->autoneg = tp->link_config.orig_autoneg; | |
1458 | phydev->advertising = tp->link_config.orig_advertising; | |
1459 | } | |
1460 | ||
1461 | phy_start(phydev); | |
1462 | ||
1463 | phy_start_aneg(phydev); | |
1464 | } | |
1465 | ||
1466 | static void tg3_phy_stop(struct tg3 *tp) | |
1467 | { | |
1468 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
1469 | return; | |
1470 | ||
298cf9be | 1471 | phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]); |
b02fd9e3 MC |
1472 | } |
1473 | ||
1474 | static void tg3_phy_fini(struct tg3 *tp) | |
1475 | { | |
1476 | if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) { | |
298cf9be | 1477 | phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]); |
b02fd9e3 MC |
1478 | tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED; |
1479 | } | |
1480 | } | |
1481 | ||
b2a5c19c MC |
1482 | static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) |
1483 | { | |
1484 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
1485 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); | |
1486 | } | |
1487 | ||
7f97a4bd MC |
1488 | static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) |
1489 | { | |
1490 | u32 phytest; | |
1491 | ||
1492 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
1493 | u32 phy; | |
1494 | ||
1495 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1496 | phytest | MII_TG3_FET_SHADOW_EN); | |
1497 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { | |
1498 | if (enable) | |
1499 | phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1500 | else | |
1501 | phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1502 | tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); | |
1503 | } | |
1504 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
1505 | } | |
1506 | } | |
1507 | ||
6833c043 MC |
1508 | static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) |
1509 | { | |
1510 | u32 reg; | |
1511 | ||
7f97a4bd | 1512 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) |
6833c043 MC |
1513 | return; |
1514 | ||
7f97a4bd MC |
1515 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { |
1516 | tg3_phy_fet_toggle_apd(tp, enable); | |
1517 | return; | |
1518 | } | |
1519 | ||
6833c043 MC |
1520 | reg = MII_TG3_MISC_SHDW_WREN | |
1521 | MII_TG3_MISC_SHDW_SCR5_SEL | | |
1522 | MII_TG3_MISC_SHDW_SCR5_LPED | | |
1523 | MII_TG3_MISC_SHDW_SCR5_DLPTLM | | |
1524 | MII_TG3_MISC_SHDW_SCR5_SDTL | | |
1525 | MII_TG3_MISC_SHDW_SCR5_C125OE; | |
1526 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable) | |
1527 | reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; | |
1528 | ||
1529 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1530 | ||
1531 | ||
1532 | reg = MII_TG3_MISC_SHDW_WREN | | |
1533 | MII_TG3_MISC_SHDW_APD_SEL | | |
1534 | MII_TG3_MISC_SHDW_APD_WKTM_84MS; | |
1535 | if (enable) | |
1536 | reg |= MII_TG3_MISC_SHDW_APD_ENABLE; | |
1537 | ||
1538 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1539 | } | |
1540 | ||
9ef8ca99 MC |
1541 | static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable) |
1542 | { | |
1543 | u32 phy; | |
1544 | ||
1545 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || | |
1546 | (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) | |
1547 | return; | |
1548 | ||
7f97a4bd | 1549 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { |
9ef8ca99 MC |
1550 | u32 ephy; |
1551 | ||
535ef6e1 MC |
1552 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { |
1553 | u32 reg = MII_TG3_FET_SHDW_MISCCTRL; | |
1554 | ||
1555 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1556 | ephy | MII_TG3_FET_SHADOW_EN); | |
1557 | if (!tg3_readphy(tp, reg, &phy)) { | |
9ef8ca99 | 1558 | if (enable) |
535ef6e1 | 1559 | phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
9ef8ca99 | 1560 | else |
535ef6e1 MC |
1561 | phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
1562 | tg3_writephy(tp, reg, phy); | |
9ef8ca99 | 1563 | } |
535ef6e1 | 1564 | tg3_writephy(tp, MII_TG3_FET_TEST, ephy); |
9ef8ca99 MC |
1565 | } |
1566 | } else { | |
1567 | phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC | | |
1568 | MII_TG3_AUXCTL_SHDWSEL_MISC; | |
1569 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) && | |
1570 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) { | |
1571 | if (enable) | |
1572 | phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
1573 | else | |
1574 | phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
1575 | phy |= MII_TG3_AUXCTL_MISC_WREN; | |
1576 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1577 | } | |
1578 | } | |
1579 | } | |
1580 | ||
1da177e4 LT |
1581 | static void tg3_phy_set_wirespeed(struct tg3 *tp) |
1582 | { | |
1583 | u32 val; | |
1584 | ||
1585 | if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) | |
1586 | return; | |
1587 | ||
1588 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) && | |
1589 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val)) | |
1590 | tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
1591 | (val | (1 << 15) | (1 << 4))); | |
1592 | } | |
1593 | ||
b2a5c19c MC |
1594 | static void tg3_phy_apply_otp(struct tg3 *tp) |
1595 | { | |
1596 | u32 otp, phy; | |
1597 | ||
1598 | if (!tp->phy_otp) | |
1599 | return; | |
1600 | ||
1601 | otp = tp->phy_otp; | |
1602 | ||
1603 | /* Enable SM_DSP clock and tx 6dB coding. */ | |
1604 | phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
1605 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | | |
1606 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
1607 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1608 | ||
1609 | phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT); | |
1610 | phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT; | |
1611 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); | |
1612 | ||
1613 | phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) | | |
1614 | ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT); | |
1615 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); | |
1616 | ||
1617 | phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT); | |
1618 | phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ; | |
1619 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); | |
1620 | ||
1621 | phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT); | |
1622 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); | |
1623 | ||
1624 | phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT); | |
1625 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); | |
1626 | ||
1627 | phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) | | |
1628 | ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT); | |
1629 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); | |
1630 | ||
1631 | /* Turn off SM_DSP clock. */ | |
1632 | phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
1633 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
1634 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1635 | } | |
1636 | ||
1da177e4 LT |
1637 | static int tg3_wait_macro_done(struct tg3 *tp) |
1638 | { | |
1639 | int limit = 100; | |
1640 | ||
1641 | while (limit--) { | |
1642 | u32 tmp32; | |
1643 | ||
1644 | if (!tg3_readphy(tp, 0x16, &tmp32)) { | |
1645 | if ((tmp32 & 0x1000) == 0) | |
1646 | break; | |
1647 | } | |
1648 | } | |
d4675b52 | 1649 | if (limit < 0) |
1da177e4 LT |
1650 | return -EBUSY; |
1651 | ||
1652 | return 0; | |
1653 | } | |
1654 | ||
1655 | static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) | |
1656 | { | |
1657 | static const u32 test_pat[4][6] = { | |
1658 | { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 }, | |
1659 | { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 }, | |
1660 | { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 }, | |
1661 | { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 } | |
1662 | }; | |
1663 | int chan; | |
1664 | ||
1665 | for (chan = 0; chan < 4; chan++) { | |
1666 | int i; | |
1667 | ||
1668 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1669 | (chan * 0x2000) | 0x0200); | |
1670 | tg3_writephy(tp, 0x16, 0x0002); | |
1671 | ||
1672 | for (i = 0; i < 6; i++) | |
1673 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, | |
1674 | test_pat[chan][i]); | |
1675 | ||
1676 | tg3_writephy(tp, 0x16, 0x0202); | |
1677 | if (tg3_wait_macro_done(tp)) { | |
1678 | *resetp = 1; | |
1679 | return -EBUSY; | |
1680 | } | |
1681 | ||
1682 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1683 | (chan * 0x2000) | 0x0200); | |
1684 | tg3_writephy(tp, 0x16, 0x0082); | |
1685 | if (tg3_wait_macro_done(tp)) { | |
1686 | *resetp = 1; | |
1687 | return -EBUSY; | |
1688 | } | |
1689 | ||
1690 | tg3_writephy(tp, 0x16, 0x0802); | |
1691 | if (tg3_wait_macro_done(tp)) { | |
1692 | *resetp = 1; | |
1693 | return -EBUSY; | |
1694 | } | |
1695 | ||
1696 | for (i = 0; i < 6; i += 2) { | |
1697 | u32 low, high; | |
1698 | ||
1699 | if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || | |
1700 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || | |
1701 | tg3_wait_macro_done(tp)) { | |
1702 | *resetp = 1; | |
1703 | return -EBUSY; | |
1704 | } | |
1705 | low &= 0x7fff; | |
1706 | high &= 0x000f; | |
1707 | if (low != test_pat[chan][i] || | |
1708 | high != test_pat[chan][i+1]) { | |
1709 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); | |
1710 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); | |
1711 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); | |
1712 | ||
1713 | return -EBUSY; | |
1714 | } | |
1715 | } | |
1716 | } | |
1717 | ||
1718 | return 0; | |
1719 | } | |
1720 | ||
1721 | static int tg3_phy_reset_chanpat(struct tg3 *tp) | |
1722 | { | |
1723 | int chan; | |
1724 | ||
1725 | for (chan = 0; chan < 4; chan++) { | |
1726 | int i; | |
1727 | ||
1728 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1729 | (chan * 0x2000) | 0x0200); | |
1730 | tg3_writephy(tp, 0x16, 0x0002); | |
1731 | for (i = 0; i < 6; i++) | |
1732 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); | |
1733 | tg3_writephy(tp, 0x16, 0x0202); | |
1734 | if (tg3_wait_macro_done(tp)) | |
1735 | return -EBUSY; | |
1736 | } | |
1737 | ||
1738 | return 0; | |
1739 | } | |
1740 | ||
1741 | static int tg3_phy_reset_5703_4_5(struct tg3 *tp) | |
1742 | { | |
1743 | u32 reg32, phy9_orig; | |
1744 | int retries, do_phy_reset, err; | |
1745 | ||
1746 | retries = 10; | |
1747 | do_phy_reset = 1; | |
1748 | do { | |
1749 | if (do_phy_reset) { | |
1750 | err = tg3_bmcr_reset(tp); | |
1751 | if (err) | |
1752 | return err; | |
1753 | do_phy_reset = 0; | |
1754 | } | |
1755 | ||
1756 | /* Disable transmitter and interrupt. */ | |
1757 | if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) | |
1758 | continue; | |
1759 | ||
1760 | reg32 |= 0x3000; | |
1761 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
1762 | ||
1763 | /* Set full-duplex, 1000 mbps. */ | |
1764 | tg3_writephy(tp, MII_BMCR, | |
1765 | BMCR_FULLDPLX | TG3_BMCR_SPEED1000); | |
1766 | ||
1767 | /* Set to master mode. */ | |
1768 | if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig)) | |
1769 | continue; | |
1770 | ||
1771 | tg3_writephy(tp, MII_TG3_CTRL, | |
1772 | (MII_TG3_CTRL_AS_MASTER | | |
1773 | MII_TG3_CTRL_ENABLE_AS_MASTER)); | |
1774 | ||
1775 | /* Enable SM_DSP_CLOCK and 6dB. */ | |
1776 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); | |
1777 | ||
1778 | /* Block the PHY control access. */ | |
1779 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005); | |
1780 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800); | |
1781 | ||
1782 | err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); | |
1783 | if (!err) | |
1784 | break; | |
1785 | } while (--retries); | |
1786 | ||
1787 | err = tg3_phy_reset_chanpat(tp); | |
1788 | if (err) | |
1789 | return err; | |
1790 | ||
1791 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005); | |
1792 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000); | |
1793 | ||
1794 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); | |
1795 | tg3_writephy(tp, 0x16, 0x0000); | |
1796 | ||
1797 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
1798 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
1799 | /* Set Extended packet length bit for jumbo frames */ | |
1800 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400); | |
1801 | } | |
1802 | else { | |
1803 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); | |
1804 | } | |
1805 | ||
1806 | tg3_writephy(tp, MII_TG3_CTRL, phy9_orig); | |
1807 | ||
1808 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) { | |
1809 | reg32 &= ~0x3000; | |
1810 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
1811 | } else if (!err) | |
1812 | err = -EBUSY; | |
1813 | ||
1814 | return err; | |
1815 | } | |
1816 | ||
1817 | /* This will reset the tigon3 PHY if there is no valid | |
1818 | * link unless the FORCE argument is non-zero. | |
1819 | */ | |
1820 | static int tg3_phy_reset(struct tg3 *tp) | |
1821 | { | |
b2a5c19c | 1822 | u32 cpmuctrl; |
1da177e4 LT |
1823 | u32 phy_status; |
1824 | int err; | |
1825 | ||
60189ddf MC |
1826 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
1827 | u32 val; | |
1828 | ||
1829 | val = tr32(GRC_MISC_CFG); | |
1830 | tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ); | |
1831 | udelay(40); | |
1832 | } | |
1da177e4 LT |
1833 | err = tg3_readphy(tp, MII_BMSR, &phy_status); |
1834 | err |= tg3_readphy(tp, MII_BMSR, &phy_status); | |
1835 | if (err != 0) | |
1836 | return -EBUSY; | |
1837 | ||
c8e1e82b MC |
1838 | if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) { |
1839 | netif_carrier_off(tp->dev); | |
1840 | tg3_link_report(tp); | |
1841 | } | |
1842 | ||
1da177e4 LT |
1843 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || |
1844 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
1845 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
1846 | err = tg3_phy_reset_5703_4_5(tp); | |
1847 | if (err) | |
1848 | return err; | |
1849 | goto out; | |
1850 | } | |
1851 | ||
b2a5c19c MC |
1852 | cpmuctrl = 0; |
1853 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
1854 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
1855 | cpmuctrl = tr32(TG3_CPMU_CTRL); | |
1856 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) | |
1857 | tw32(TG3_CPMU_CTRL, | |
1858 | cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY); | |
1859 | } | |
1860 | ||
1da177e4 LT |
1861 | err = tg3_bmcr_reset(tp); |
1862 | if (err) | |
1863 | return err; | |
1864 | ||
b2a5c19c MC |
1865 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) { |
1866 | u32 phy; | |
1867 | ||
1868 | phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz; | |
1869 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy); | |
1870 | ||
1871 | tw32(TG3_CPMU_CTRL, cpmuctrl); | |
1872 | } | |
1873 | ||
bcb37f6c MC |
1874 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
1875 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
1876 | u32 val; |
1877 | ||
1878 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); | |
1879 | if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) == | |
1880 | CPMU_LSPD_1000MB_MACCLK_12_5) { | |
1881 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
1882 | udelay(40); | |
1883 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
1884 | } | |
1885 | } | |
1886 | ||
b2a5c19c MC |
1887 | tg3_phy_apply_otp(tp); |
1888 | ||
6833c043 MC |
1889 | if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD) |
1890 | tg3_phy_toggle_apd(tp, true); | |
1891 | else | |
1892 | tg3_phy_toggle_apd(tp, false); | |
1893 | ||
1da177e4 LT |
1894 | out: |
1895 | if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) { | |
1896 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); | |
1897 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f); | |
1898 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa); | |
1899 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
1900 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323); | |
1901 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); | |
1902 | } | |
1903 | if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) { | |
1904 | tg3_writephy(tp, 0x1c, 0x8d68); | |
1905 | tg3_writephy(tp, 0x1c, 0x8d68); | |
1906 | } | |
1907 | if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) { | |
1908 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); | |
1909 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
1910 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b); | |
1911 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f); | |
1912 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506); | |
1913 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f); | |
1914 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2); | |
1915 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); | |
1916 | } | |
c424cb24 MC |
1917 | else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) { |
1918 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); | |
1919 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
c1d2a196 MC |
1920 | if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) { |
1921 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); | |
1922 | tg3_writephy(tp, MII_TG3_TEST1, | |
1923 | MII_TG3_TEST1_TRIM_EN | 0x4); | |
1924 | } else | |
1925 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); | |
c424cb24 MC |
1926 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); |
1927 | } | |
1da177e4 LT |
1928 | /* Set Extended packet length bit (bit 14) on all chips that */ |
1929 | /* support jumbo frames */ | |
1930 | if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { | |
1931 | /* Cannot do read-modify-write on 5401 */ | |
1932 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20); | |
8f666b07 | 1933 | } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { |
1da177e4 LT |
1934 | u32 phy_reg; |
1935 | ||
1936 | /* Set bit 14 with read-modify-write to preserve other bits */ | |
1937 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) && | |
1938 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg)) | |
1939 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000); | |
1940 | } | |
1941 | ||
1942 | /* Set phy register 0x10 bit 0 to high fifo elasticity to support | |
1943 | * jumbo frames transmission. | |
1944 | */ | |
8f666b07 | 1945 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { |
1da177e4 LT |
1946 | u32 phy_reg; |
1947 | ||
1948 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg)) | |
1949 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
1950 | phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC); | |
1951 | } | |
1952 | ||
715116a1 | 1953 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
715116a1 | 1954 | /* adjust output voltage */ |
535ef6e1 | 1955 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); |
715116a1 MC |
1956 | } |
1957 | ||
9ef8ca99 | 1958 | tg3_phy_toggle_automdix(tp, 1); |
1da177e4 LT |
1959 | tg3_phy_set_wirespeed(tp); |
1960 | return 0; | |
1961 | } | |
1962 | ||
1963 | static void tg3_frob_aux_power(struct tg3 *tp) | |
1964 | { | |
1965 | struct tg3 *tp_peer = tp; | |
1966 | ||
9d26e213 | 1967 | if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0) |
1da177e4 LT |
1968 | return; |
1969 | ||
8c2dc7e1 MC |
1970 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || |
1971 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) { | |
1972 | struct net_device *dev_peer; | |
1973 | ||
1974 | dev_peer = pci_get_drvdata(tp->pdev_peer); | |
bc1c7567 | 1975 | /* remove_one() may have been run on the peer. */ |
8c2dc7e1 | 1976 | if (!dev_peer) |
bc1c7567 MC |
1977 | tp_peer = tp; |
1978 | else | |
1979 | tp_peer = netdev_priv(dev_peer); | |
1da177e4 LT |
1980 | } |
1981 | ||
1da177e4 | 1982 | if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 || |
6921d201 MC |
1983 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 || |
1984 | (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 || | |
1985 | (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) { | |
1da177e4 LT |
1986 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
1987 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
b401e9e2 MC |
1988 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
1989 | (GRC_LCLCTRL_GPIO_OE0 | | |
1990 | GRC_LCLCTRL_GPIO_OE1 | | |
1991 | GRC_LCLCTRL_GPIO_OE2 | | |
1992 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
1993 | GRC_LCLCTRL_GPIO_OUTPUT1), | |
1994 | 100); | |
8d519ab2 MC |
1995 | } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
1996 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
5f0c4a3c MC |
1997 | /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ |
1998 | u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 | | |
1999 | GRC_LCLCTRL_GPIO_OE1 | | |
2000 | GRC_LCLCTRL_GPIO_OE2 | | |
2001 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2002 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2003 | tp->grc_local_ctrl; | |
2004 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
2005 | ||
2006 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2; | |
2007 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
2008 | ||
2009 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0; | |
2010 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
1da177e4 LT |
2011 | } else { |
2012 | u32 no_gpio2; | |
dc56b7d4 | 2013 | u32 grc_local_ctrl = 0; |
1da177e4 LT |
2014 | |
2015 | if (tp_peer != tp && | |
2016 | (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0) | |
2017 | return; | |
2018 | ||
dc56b7d4 MC |
2019 | /* Workaround to prevent overdrawing Amps. */ |
2020 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
2021 | ASIC_REV_5714) { | |
2022 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
b401e9e2 MC |
2023 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2024 | grc_local_ctrl, 100); | |
dc56b7d4 MC |
2025 | } |
2026 | ||
1da177e4 LT |
2027 | /* On 5753 and variants, GPIO2 cannot be used. */ |
2028 | no_gpio2 = tp->nic_sram_data_cfg & | |
2029 | NIC_SRAM_DATA_CFG_NO_GPIO2; | |
2030 | ||
dc56b7d4 | 2031 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | |
1da177e4 LT |
2032 | GRC_LCLCTRL_GPIO_OE1 | |
2033 | GRC_LCLCTRL_GPIO_OE2 | | |
2034 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2035 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
2036 | if (no_gpio2) { | |
2037 | grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 | | |
2038 | GRC_LCLCTRL_GPIO_OUTPUT2); | |
2039 | } | |
b401e9e2 MC |
2040 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2041 | grc_local_ctrl, 100); | |
1da177e4 LT |
2042 | |
2043 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0; | |
2044 | ||
b401e9e2 MC |
2045 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2046 | grc_local_ctrl, 100); | |
1da177e4 LT |
2047 | |
2048 | if (!no_gpio2) { | |
2049 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2; | |
b401e9e2 MC |
2050 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2051 | grc_local_ctrl, 100); | |
1da177e4 LT |
2052 | } |
2053 | } | |
2054 | } else { | |
2055 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
2056 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
2057 | if (tp_peer != tp && | |
2058 | (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0) | |
2059 | return; | |
2060 | ||
b401e9e2 MC |
2061 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2062 | (GRC_LCLCTRL_GPIO_OE1 | | |
2063 | GRC_LCLCTRL_GPIO_OUTPUT1), 100); | |
1da177e4 | 2064 | |
b401e9e2 MC |
2065 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2066 | GRC_LCLCTRL_GPIO_OE1, 100); | |
1da177e4 | 2067 | |
b401e9e2 MC |
2068 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2069 | (GRC_LCLCTRL_GPIO_OE1 | | |
2070 | GRC_LCLCTRL_GPIO_OUTPUT1), 100); | |
1da177e4 LT |
2071 | } |
2072 | } | |
2073 | } | |
2074 | ||
e8f3f6ca MC |
2075 | static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) |
2076 | { | |
2077 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) | |
2078 | return 1; | |
2079 | else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) { | |
2080 | if (speed != SPEED_10) | |
2081 | return 1; | |
2082 | } else if (speed == SPEED_10) | |
2083 | return 1; | |
2084 | ||
2085 | return 0; | |
2086 | } | |
2087 | ||
1da177e4 LT |
2088 | static int tg3_setup_phy(struct tg3 *, int); |
2089 | ||
2090 | #define RESET_KIND_SHUTDOWN 0 | |
2091 | #define RESET_KIND_INIT 1 | |
2092 | #define RESET_KIND_SUSPEND 2 | |
2093 | ||
2094 | static void tg3_write_sig_post_reset(struct tg3 *, int); | |
2095 | static int tg3_halt_cpu(struct tg3 *, u32); | |
2096 | ||
0a459aac | 2097 | static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) |
15c3b696 | 2098 | { |
ce057f01 MC |
2099 | u32 val; |
2100 | ||
5129724a MC |
2101 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { |
2102 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
2103 | u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
2104 | u32 serdes_cfg = tr32(MAC_SERDES_CFG); | |
2105 | ||
2106 | sg_dig_ctrl |= | |
2107 | SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET; | |
2108 | tw32(SG_DIG_CTRL, sg_dig_ctrl); | |
2109 | tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15)); | |
2110 | } | |
3f7045c1 | 2111 | return; |
5129724a | 2112 | } |
3f7045c1 | 2113 | |
60189ddf | 2114 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2115 | tg3_bmcr_reset(tp); |
2116 | val = tr32(GRC_MISC_CFG); | |
2117 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); | |
2118 | udelay(40); | |
2119 | return; | |
0a459aac | 2120 | } else if (do_low_power) { |
715116a1 MC |
2121 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
2122 | MII_TG3_EXT_CTRL_FORCE_LED_OFF); | |
0a459aac MC |
2123 | |
2124 | tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
2125 | MII_TG3_AUXCTL_SHDWSEL_PWRCTL | | |
2126 | MII_TG3_AUXCTL_PCTL_100TX_LPWR | | |
2127 | MII_TG3_AUXCTL_PCTL_SPR_ISOLATE | | |
2128 | MII_TG3_AUXCTL_PCTL_VREG_11V); | |
715116a1 | 2129 | } |
3f7045c1 | 2130 | |
15c3b696 MC |
2131 | /* The PHY should not be powered down on some chips because |
2132 | * of bugs. | |
2133 | */ | |
2134 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2135 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2136 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 && | |
2137 | (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))) | |
2138 | return; | |
ce057f01 | 2139 | |
bcb37f6c MC |
2140 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2141 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2142 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2143 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2144 | val |= CPMU_LSPD_1000MB_MACCLK_12_5; | |
2145 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2146 | } | |
2147 | ||
15c3b696 MC |
2148 | tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); |
2149 | } | |
2150 | ||
ffbcfed4 MC |
2151 | /* tp->lock is held. */ |
2152 | static int tg3_nvram_lock(struct tg3 *tp) | |
2153 | { | |
2154 | if (tp->tg3_flags & TG3_FLAG_NVRAM) { | |
2155 | int i; | |
2156 | ||
2157 | if (tp->nvram_lock_cnt == 0) { | |
2158 | tw32(NVRAM_SWARB, SWARB_REQ_SET1); | |
2159 | for (i = 0; i < 8000; i++) { | |
2160 | if (tr32(NVRAM_SWARB) & SWARB_GNT1) | |
2161 | break; | |
2162 | udelay(20); | |
2163 | } | |
2164 | if (i == 8000) { | |
2165 | tw32(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2166 | return -ENODEV; | |
2167 | } | |
2168 | } | |
2169 | tp->nvram_lock_cnt++; | |
2170 | } | |
2171 | return 0; | |
2172 | } | |
2173 | ||
2174 | /* tp->lock is held. */ | |
2175 | static void tg3_nvram_unlock(struct tg3 *tp) | |
2176 | { | |
2177 | if (tp->tg3_flags & TG3_FLAG_NVRAM) { | |
2178 | if (tp->nvram_lock_cnt > 0) | |
2179 | tp->nvram_lock_cnt--; | |
2180 | if (tp->nvram_lock_cnt == 0) | |
2181 | tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2182 | } | |
2183 | } | |
2184 | ||
2185 | /* tp->lock is held. */ | |
2186 | static void tg3_enable_nvram_access(struct tg3 *tp) | |
2187 | { | |
2188 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
2189 | !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) { | |
2190 | u32 nvaccess = tr32(NVRAM_ACCESS); | |
2191 | ||
2192 | tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); | |
2193 | } | |
2194 | } | |
2195 | ||
2196 | /* tp->lock is held. */ | |
2197 | static void tg3_disable_nvram_access(struct tg3 *tp) | |
2198 | { | |
2199 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
2200 | !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) { | |
2201 | u32 nvaccess = tr32(NVRAM_ACCESS); | |
2202 | ||
2203 | tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); | |
2204 | } | |
2205 | } | |
2206 | ||
2207 | static int tg3_nvram_read_using_eeprom(struct tg3 *tp, | |
2208 | u32 offset, u32 *val) | |
2209 | { | |
2210 | u32 tmp; | |
2211 | int i; | |
2212 | ||
2213 | if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0) | |
2214 | return -EINVAL; | |
2215 | ||
2216 | tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | | |
2217 | EEPROM_ADDR_DEVID_MASK | | |
2218 | EEPROM_ADDR_READ); | |
2219 | tw32(GRC_EEPROM_ADDR, | |
2220 | tmp | | |
2221 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
2222 | ((offset << EEPROM_ADDR_ADDR_SHIFT) & | |
2223 | EEPROM_ADDR_ADDR_MASK) | | |
2224 | EEPROM_ADDR_READ | EEPROM_ADDR_START); | |
2225 | ||
2226 | for (i = 0; i < 1000; i++) { | |
2227 | tmp = tr32(GRC_EEPROM_ADDR); | |
2228 | ||
2229 | if (tmp & EEPROM_ADDR_COMPLETE) | |
2230 | break; | |
2231 | msleep(1); | |
2232 | } | |
2233 | if (!(tmp & EEPROM_ADDR_COMPLETE)) | |
2234 | return -EBUSY; | |
2235 | ||
62cedd11 MC |
2236 | tmp = tr32(GRC_EEPROM_DATA); |
2237 | ||
2238 | /* | |
2239 | * The data will always be opposite the native endian | |
2240 | * format. Perform a blind byteswap to compensate. | |
2241 | */ | |
2242 | *val = swab32(tmp); | |
2243 | ||
ffbcfed4 MC |
2244 | return 0; |
2245 | } | |
2246 | ||
2247 | #define NVRAM_CMD_TIMEOUT 10000 | |
2248 | ||
2249 | static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) | |
2250 | { | |
2251 | int i; | |
2252 | ||
2253 | tw32(NVRAM_CMD, nvram_cmd); | |
2254 | for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { | |
2255 | udelay(10); | |
2256 | if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { | |
2257 | udelay(10); | |
2258 | break; | |
2259 | } | |
2260 | } | |
2261 | ||
2262 | if (i == NVRAM_CMD_TIMEOUT) | |
2263 | return -EBUSY; | |
2264 | ||
2265 | return 0; | |
2266 | } | |
2267 | ||
2268 | static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) | |
2269 | { | |
2270 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | |
2271 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | |
2272 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | |
2273 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | |
2274 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | |
2275 | ||
2276 | addr = ((addr / tp->nvram_pagesize) << | |
2277 | ATMEL_AT45DB0X1B_PAGE_POS) + | |
2278 | (addr % tp->nvram_pagesize); | |
2279 | ||
2280 | return addr; | |
2281 | } | |
2282 | ||
2283 | static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) | |
2284 | { | |
2285 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | |
2286 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | |
2287 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | |
2288 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | |
2289 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | |
2290 | ||
2291 | addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * | |
2292 | tp->nvram_pagesize) + | |
2293 | (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); | |
2294 | ||
2295 | return addr; | |
2296 | } | |
2297 | ||
e4f34110 MC |
2298 | /* NOTE: Data read in from NVRAM is byteswapped according to |
2299 | * the byteswapping settings for all other register accesses. | |
2300 | * tg3 devices are BE devices, so on a BE machine, the data | |
2301 | * returned will be exactly as it is seen in NVRAM. On a LE | |
2302 | * machine, the 32-bit value will be byteswapped. | |
2303 | */ | |
ffbcfed4 MC |
2304 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) |
2305 | { | |
2306 | int ret; | |
2307 | ||
2308 | if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) | |
2309 | return tg3_nvram_read_using_eeprom(tp, offset, val); | |
2310 | ||
2311 | offset = tg3_nvram_phys_addr(tp, offset); | |
2312 | ||
2313 | if (offset > NVRAM_ADDR_MSK) | |
2314 | return -EINVAL; | |
2315 | ||
2316 | ret = tg3_nvram_lock(tp); | |
2317 | if (ret) | |
2318 | return ret; | |
2319 | ||
2320 | tg3_enable_nvram_access(tp); | |
2321 | ||
2322 | tw32(NVRAM_ADDR, offset); | |
2323 | ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | | |
2324 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); | |
2325 | ||
2326 | if (ret == 0) | |
e4f34110 | 2327 | *val = tr32(NVRAM_RDDATA); |
ffbcfed4 MC |
2328 | |
2329 | tg3_disable_nvram_access(tp); | |
2330 | ||
2331 | tg3_nvram_unlock(tp); | |
2332 | ||
2333 | return ret; | |
2334 | } | |
2335 | ||
a9dc529d MC |
2336 | /* Ensures NVRAM data is in bytestream format. */ |
2337 | static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) | |
ffbcfed4 MC |
2338 | { |
2339 | u32 v; | |
a9dc529d | 2340 | int res = tg3_nvram_read(tp, offset, &v); |
ffbcfed4 | 2341 | if (!res) |
a9dc529d | 2342 | *val = cpu_to_be32(v); |
ffbcfed4 MC |
2343 | return res; |
2344 | } | |
2345 | ||
3f007891 MC |
2346 | /* tp->lock is held. */ |
2347 | static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) | |
2348 | { | |
2349 | u32 addr_high, addr_low; | |
2350 | int i; | |
2351 | ||
2352 | addr_high = ((tp->dev->dev_addr[0] << 8) | | |
2353 | tp->dev->dev_addr[1]); | |
2354 | addr_low = ((tp->dev->dev_addr[2] << 24) | | |
2355 | (tp->dev->dev_addr[3] << 16) | | |
2356 | (tp->dev->dev_addr[4] << 8) | | |
2357 | (tp->dev->dev_addr[5] << 0)); | |
2358 | for (i = 0; i < 4; i++) { | |
2359 | if (i == 1 && skip_mac_1) | |
2360 | continue; | |
2361 | tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high); | |
2362 | tw32(MAC_ADDR_0_LOW + (i * 8), addr_low); | |
2363 | } | |
2364 | ||
2365 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
2366 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
2367 | for (i = 0; i < 12; i++) { | |
2368 | tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high); | |
2369 | tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low); | |
2370 | } | |
2371 | } | |
2372 | ||
2373 | addr_high = (tp->dev->dev_addr[0] + | |
2374 | tp->dev->dev_addr[1] + | |
2375 | tp->dev->dev_addr[2] + | |
2376 | tp->dev->dev_addr[3] + | |
2377 | tp->dev->dev_addr[4] + | |
2378 | tp->dev->dev_addr[5]) & | |
2379 | TX_BACKOFF_SEED_MASK; | |
2380 | tw32(MAC_TX_BACKOFF_SEED, addr_high); | |
2381 | } | |
2382 | ||
bc1c7567 | 2383 | static int tg3_set_power_state(struct tg3 *tp, pci_power_t state) |
1da177e4 LT |
2384 | { |
2385 | u32 misc_host_ctrl; | |
0a459aac | 2386 | bool device_should_wake, do_low_power; |
1da177e4 LT |
2387 | |
2388 | /* Make sure register accesses (indirect or otherwise) | |
2389 | * will function correctly. | |
2390 | */ | |
2391 | pci_write_config_dword(tp->pdev, | |
2392 | TG3PCI_MISC_HOST_CTRL, | |
2393 | tp->misc_host_ctrl); | |
2394 | ||
1da177e4 | 2395 | switch (state) { |
bc1c7567 | 2396 | case PCI_D0: |
12dac075 RW |
2397 | pci_enable_wake(tp->pdev, state, false); |
2398 | pci_set_power_state(tp->pdev, PCI_D0); | |
8c6bda1a | 2399 | |
9d26e213 MC |
2400 | /* Switch out of Vaux if it is a NIC */ |
2401 | if (tp->tg3_flags2 & TG3_FLG2_IS_NIC) | |
b401e9e2 | 2402 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100); |
1da177e4 LT |
2403 | |
2404 | return 0; | |
2405 | ||
bc1c7567 | 2406 | case PCI_D1: |
bc1c7567 | 2407 | case PCI_D2: |
bc1c7567 | 2408 | case PCI_D3hot: |
1da177e4 LT |
2409 | break; |
2410 | ||
2411 | default: | |
12dac075 RW |
2412 | printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n", |
2413 | tp->dev->name, state); | |
1da177e4 | 2414 | return -EINVAL; |
855e1111 | 2415 | } |
5e7dfd0f MC |
2416 | |
2417 | /* Restore the CLKREQ setting. */ | |
2418 | if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) { | |
2419 | u16 lnkctl; | |
2420 | ||
2421 | pci_read_config_word(tp->pdev, | |
2422 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
2423 | &lnkctl); | |
2424 | lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
2425 | pci_write_config_word(tp->pdev, | |
2426 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
2427 | lnkctl); | |
2428 | } | |
2429 | ||
1da177e4 LT |
2430 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
2431 | tw32(TG3PCI_MISC_HOST_CTRL, | |
2432 | misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); | |
2433 | ||
05ac4cb7 MC |
2434 | device_should_wake = pci_pme_capable(tp->pdev, state) && |
2435 | device_may_wakeup(&tp->pdev->dev) && | |
2436 | (tp->tg3_flags & TG3_FLAG_WOL_ENABLE); | |
2437 | ||
dd477003 | 2438 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
0a459aac | 2439 | do_low_power = false; |
b02fd9e3 MC |
2440 | if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) && |
2441 | !tp->link_config.phy_is_low_power) { | |
2442 | struct phy_device *phydev; | |
0a459aac | 2443 | u32 phyid, advertising; |
b02fd9e3 | 2444 | |
298cf9be | 2445 | phydev = tp->mdio_bus->phy_map[PHY_ADDR]; |
b02fd9e3 MC |
2446 | |
2447 | tp->link_config.phy_is_low_power = 1; | |
2448 | ||
2449 | tp->link_config.orig_speed = phydev->speed; | |
2450 | tp->link_config.orig_duplex = phydev->duplex; | |
2451 | tp->link_config.orig_autoneg = phydev->autoneg; | |
2452 | tp->link_config.orig_advertising = phydev->advertising; | |
2453 | ||
2454 | advertising = ADVERTISED_TP | | |
2455 | ADVERTISED_Pause | | |
2456 | ADVERTISED_Autoneg | | |
2457 | ADVERTISED_10baseT_Half; | |
2458 | ||
2459 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
05ac4cb7 | 2460 | device_should_wake) { |
b02fd9e3 MC |
2461 | if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) |
2462 | advertising |= | |
2463 | ADVERTISED_100baseT_Half | | |
2464 | ADVERTISED_100baseT_Full | | |
2465 | ADVERTISED_10baseT_Full; | |
2466 | else | |
2467 | advertising |= ADVERTISED_10baseT_Full; | |
2468 | } | |
2469 | ||
2470 | phydev->advertising = advertising; | |
2471 | ||
2472 | phy_start_aneg(phydev); | |
0a459aac MC |
2473 | |
2474 | phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; | |
2475 | if (phyid != TG3_PHY_ID_BCMAC131) { | |
2476 | phyid &= TG3_PHY_OUI_MASK; | |
f72b5349 RK |
2477 | if (phyid == TG3_PHY_OUI_1 || |
2478 | phyid == TG3_PHY_OUI_2 || | |
0a459aac MC |
2479 | phyid == TG3_PHY_OUI_3) |
2480 | do_low_power = true; | |
2481 | } | |
b02fd9e3 | 2482 | } |
dd477003 | 2483 | } else { |
2023276e | 2484 | do_low_power = true; |
0a459aac | 2485 | |
dd477003 MC |
2486 | if (tp->link_config.phy_is_low_power == 0) { |
2487 | tp->link_config.phy_is_low_power = 1; | |
2488 | tp->link_config.orig_speed = tp->link_config.speed; | |
2489 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
2490 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
2491 | } | |
1da177e4 | 2492 | |
dd477003 MC |
2493 | if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) { |
2494 | tp->link_config.speed = SPEED_10; | |
2495 | tp->link_config.duplex = DUPLEX_HALF; | |
2496 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
2497 | tg3_setup_phy(tp, 0); | |
2498 | } | |
1da177e4 LT |
2499 | } |
2500 | ||
b5d3772c MC |
2501 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
2502 | u32 val; | |
2503 | ||
2504 | val = tr32(GRC_VCPU_EXT_CTRL); | |
2505 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL); | |
2506 | } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { | |
6921d201 MC |
2507 | int i; |
2508 | u32 val; | |
2509 | ||
2510 | for (i = 0; i < 200; i++) { | |
2511 | tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); | |
2512 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
2513 | break; | |
2514 | msleep(1); | |
2515 | } | |
2516 | } | |
a85feb8c GZ |
2517 | if (tp->tg3_flags & TG3_FLAG_WOL_CAP) |
2518 | tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | | |
2519 | WOL_DRV_STATE_SHUTDOWN | | |
2520 | WOL_DRV_WOL | | |
2521 | WOL_SET_MAGIC_PKT); | |
6921d201 | 2522 | |
05ac4cb7 | 2523 | if (device_should_wake) { |
1da177e4 LT |
2524 | u32 mac_mode; |
2525 | ||
2526 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { | |
0a459aac | 2527 | if (do_low_power) { |
dd477003 MC |
2528 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a); |
2529 | udelay(40); | |
2530 | } | |
1da177e4 | 2531 | |
3f7045c1 MC |
2532 | if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) |
2533 | mac_mode = MAC_MODE_PORT_MODE_GMII; | |
2534 | else | |
2535 | mac_mode = MAC_MODE_PORT_MODE_MII; | |
1da177e4 | 2536 | |
e8f3f6ca MC |
2537 | mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; |
2538 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
2539 | ASIC_REV_5700) { | |
2540 | u32 speed = (tp->tg3_flags & | |
2541 | TG3_FLAG_WOL_SPEED_100MB) ? | |
2542 | SPEED_100 : SPEED_10; | |
2543 | if (tg3_5700_link_polarity(tp, speed)) | |
2544 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
2545 | else | |
2546 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
2547 | } | |
1da177e4 LT |
2548 | } else { |
2549 | mac_mode = MAC_MODE_PORT_MODE_TBI; | |
2550 | } | |
2551 | ||
cbf46853 | 2552 | if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) |
1da177e4 LT |
2553 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
2554 | ||
05ac4cb7 MC |
2555 | mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; |
2556 | if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && | |
2557 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) && | |
2558 | ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
2559 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))) | |
2560 | mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL; | |
1da177e4 | 2561 | |
3bda1258 MC |
2562 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
2563 | mac_mode |= tp->mac_mode & | |
2564 | (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN); | |
2565 | if (mac_mode & MAC_MODE_APE_TX_EN) | |
2566 | mac_mode |= MAC_MODE_TDE_ENABLE; | |
2567 | } | |
2568 | ||
1da177e4 LT |
2569 | tw32_f(MAC_MODE, mac_mode); |
2570 | udelay(100); | |
2571 | ||
2572 | tw32_f(MAC_RX_MODE, RX_MODE_ENABLE); | |
2573 | udelay(10); | |
2574 | } | |
2575 | ||
2576 | if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) && | |
2577 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2578 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
2579 | u32 base_val; | |
2580 | ||
2581 | base_val = tp->pci_clock_ctrl; | |
2582 | base_val |= (CLOCK_CTRL_RXCLK_DISABLE | | |
2583 | CLOCK_CTRL_TXCLK_DISABLE); | |
2584 | ||
b401e9e2 MC |
2585 | tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK | |
2586 | CLOCK_CTRL_PWRDOWN_PLL133, 40); | |
d7b0a857 | 2587 | } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || |
795d01c5 | 2588 | (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || |
d7b0a857 | 2589 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) { |
4cf78e4f | 2590 | /* do nothing */ |
85e94ced | 2591 | } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && |
1da177e4 LT |
2592 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) { |
2593 | u32 newbits1, newbits2; | |
2594 | ||
2595 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2596 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2597 | newbits1 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2598 | CLOCK_CTRL_TXCLK_DISABLE | | |
2599 | CLOCK_CTRL_ALTCLK); | |
2600 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
2601 | } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
2602 | newbits1 = CLOCK_CTRL_625_CORE; | |
2603 | newbits2 = newbits1 | CLOCK_CTRL_ALTCLK; | |
2604 | } else { | |
2605 | newbits1 = CLOCK_CTRL_ALTCLK; | |
2606 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
2607 | } | |
2608 | ||
b401e9e2 MC |
2609 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, |
2610 | 40); | |
1da177e4 | 2611 | |
b401e9e2 MC |
2612 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, |
2613 | 40); | |
1da177e4 LT |
2614 | |
2615 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
2616 | u32 newbits3; | |
2617 | ||
2618 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2619 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2620 | newbits3 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2621 | CLOCK_CTRL_TXCLK_DISABLE | | |
2622 | CLOCK_CTRL_44MHZ_CORE); | |
2623 | } else { | |
2624 | newbits3 = CLOCK_CTRL_44MHZ_CORE; | |
2625 | } | |
2626 | ||
b401e9e2 MC |
2627 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
2628 | tp->pci_clock_ctrl | newbits3, 40); | |
1da177e4 LT |
2629 | } |
2630 | } | |
2631 | ||
05ac4cb7 | 2632 | if (!(device_should_wake) && |
22435849 | 2633 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) |
0a459aac | 2634 | tg3_power_down_phy(tp, do_low_power); |
6921d201 | 2635 | |
1da177e4 LT |
2636 | tg3_frob_aux_power(tp); |
2637 | ||
2638 | /* Workaround for unstable PLL clock */ | |
2639 | if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || | |
2640 | (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) { | |
2641 | u32 val = tr32(0x7d00); | |
2642 | ||
2643 | val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); | |
2644 | tw32(0x7d00, val); | |
6921d201 | 2645 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { |
ec41c7df MC |
2646 | int err; |
2647 | ||
2648 | err = tg3_nvram_lock(tp); | |
1da177e4 | 2649 | tg3_halt_cpu(tp, RX_CPU_BASE); |
ec41c7df MC |
2650 | if (!err) |
2651 | tg3_nvram_unlock(tp); | |
6921d201 | 2652 | } |
1da177e4 LT |
2653 | } |
2654 | ||
bbadf503 MC |
2655 | tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); |
2656 | ||
05ac4cb7 | 2657 | if (device_should_wake) |
12dac075 RW |
2658 | pci_enable_wake(tp->pdev, state, true); |
2659 | ||
1da177e4 | 2660 | /* Finally, set the new power state. */ |
12dac075 | 2661 | pci_set_power_state(tp->pdev, state); |
1da177e4 | 2662 | |
1da177e4 LT |
2663 | return 0; |
2664 | } | |
2665 | ||
1da177e4 LT |
2666 | static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex) |
2667 | { | |
2668 | switch (val & MII_TG3_AUX_STAT_SPDMASK) { | |
2669 | case MII_TG3_AUX_STAT_10HALF: | |
2670 | *speed = SPEED_10; | |
2671 | *duplex = DUPLEX_HALF; | |
2672 | break; | |
2673 | ||
2674 | case MII_TG3_AUX_STAT_10FULL: | |
2675 | *speed = SPEED_10; | |
2676 | *duplex = DUPLEX_FULL; | |
2677 | break; | |
2678 | ||
2679 | case MII_TG3_AUX_STAT_100HALF: | |
2680 | *speed = SPEED_100; | |
2681 | *duplex = DUPLEX_HALF; | |
2682 | break; | |
2683 | ||
2684 | case MII_TG3_AUX_STAT_100FULL: | |
2685 | *speed = SPEED_100; | |
2686 | *duplex = DUPLEX_FULL; | |
2687 | break; | |
2688 | ||
2689 | case MII_TG3_AUX_STAT_1000HALF: | |
2690 | *speed = SPEED_1000; | |
2691 | *duplex = DUPLEX_HALF; | |
2692 | break; | |
2693 | ||
2694 | case MII_TG3_AUX_STAT_1000FULL: | |
2695 | *speed = SPEED_1000; | |
2696 | *duplex = DUPLEX_FULL; | |
2697 | break; | |
2698 | ||
2699 | default: | |
7f97a4bd | 2700 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { |
715116a1 MC |
2701 | *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 : |
2702 | SPEED_10; | |
2703 | *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL : | |
2704 | DUPLEX_HALF; | |
2705 | break; | |
2706 | } | |
1da177e4 LT |
2707 | *speed = SPEED_INVALID; |
2708 | *duplex = DUPLEX_INVALID; | |
2709 | break; | |
855e1111 | 2710 | } |
1da177e4 LT |
2711 | } |
2712 | ||
2713 | static void tg3_phy_copper_begin(struct tg3 *tp) | |
2714 | { | |
2715 | u32 new_adv; | |
2716 | int i; | |
2717 | ||
2718 | if (tp->link_config.phy_is_low_power) { | |
2719 | /* Entering low power mode. Disable gigabit and | |
2720 | * 100baseT advertisements. | |
2721 | */ | |
2722 | tg3_writephy(tp, MII_TG3_CTRL, 0); | |
2723 | ||
2724 | new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL | | |
2725 | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
2726 | if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) | |
2727 | new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL); | |
2728 | ||
2729 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
2730 | } else if (tp->link_config.speed == SPEED_INVALID) { | |
1da177e4 LT |
2731 | if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) |
2732 | tp->link_config.advertising &= | |
2733 | ~(ADVERTISED_1000baseT_Half | | |
2734 | ADVERTISED_1000baseT_Full); | |
2735 | ||
ba4d07a8 | 2736 | new_adv = ADVERTISE_CSMA; |
1da177e4 LT |
2737 | if (tp->link_config.advertising & ADVERTISED_10baseT_Half) |
2738 | new_adv |= ADVERTISE_10HALF; | |
2739 | if (tp->link_config.advertising & ADVERTISED_10baseT_Full) | |
2740 | new_adv |= ADVERTISE_10FULL; | |
2741 | if (tp->link_config.advertising & ADVERTISED_100baseT_Half) | |
2742 | new_adv |= ADVERTISE_100HALF; | |
2743 | if (tp->link_config.advertising & ADVERTISED_100baseT_Full) | |
2744 | new_adv |= ADVERTISE_100FULL; | |
ba4d07a8 MC |
2745 | |
2746 | new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
2747 | ||
1da177e4 LT |
2748 | tg3_writephy(tp, MII_ADVERTISE, new_adv); |
2749 | ||
2750 | if (tp->link_config.advertising & | |
2751 | (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) { | |
2752 | new_adv = 0; | |
2753 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) | |
2754 | new_adv |= MII_TG3_CTRL_ADV_1000_HALF; | |
2755 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) | |
2756 | new_adv |= MII_TG3_CTRL_ADV_1000_FULL; | |
2757 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) && | |
2758 | (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
2759 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) | |
2760 | new_adv |= (MII_TG3_CTRL_AS_MASTER | | |
2761 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
2762 | tg3_writephy(tp, MII_TG3_CTRL, new_adv); | |
2763 | } else { | |
2764 | tg3_writephy(tp, MII_TG3_CTRL, 0); | |
2765 | } | |
2766 | } else { | |
ba4d07a8 MC |
2767 | new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); |
2768 | new_adv |= ADVERTISE_CSMA; | |
2769 | ||
1da177e4 LT |
2770 | /* Asking for a specific link mode. */ |
2771 | if (tp->link_config.speed == SPEED_1000) { | |
1da177e4 LT |
2772 | tg3_writephy(tp, MII_ADVERTISE, new_adv); |
2773 | ||
2774 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2775 | new_adv = MII_TG3_CTRL_ADV_1000_FULL; | |
2776 | else | |
2777 | new_adv = MII_TG3_CTRL_ADV_1000_HALF; | |
2778 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
2779 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
2780 | new_adv |= (MII_TG3_CTRL_AS_MASTER | | |
2781 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
1da177e4 | 2782 | } else { |
1da177e4 LT |
2783 | if (tp->link_config.speed == SPEED_100) { |
2784 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2785 | new_adv |= ADVERTISE_100FULL; | |
2786 | else | |
2787 | new_adv |= ADVERTISE_100HALF; | |
2788 | } else { | |
2789 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2790 | new_adv |= ADVERTISE_10FULL; | |
2791 | else | |
2792 | new_adv |= ADVERTISE_10HALF; | |
2793 | } | |
2794 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
ba4d07a8 MC |
2795 | |
2796 | new_adv = 0; | |
1da177e4 | 2797 | } |
ba4d07a8 MC |
2798 | |
2799 | tg3_writephy(tp, MII_TG3_CTRL, new_adv); | |
1da177e4 LT |
2800 | } |
2801 | ||
2802 | if (tp->link_config.autoneg == AUTONEG_DISABLE && | |
2803 | tp->link_config.speed != SPEED_INVALID) { | |
2804 | u32 bmcr, orig_bmcr; | |
2805 | ||
2806 | tp->link_config.active_speed = tp->link_config.speed; | |
2807 | tp->link_config.active_duplex = tp->link_config.duplex; | |
2808 | ||
2809 | bmcr = 0; | |
2810 | switch (tp->link_config.speed) { | |
2811 | default: | |
2812 | case SPEED_10: | |
2813 | break; | |
2814 | ||
2815 | case SPEED_100: | |
2816 | bmcr |= BMCR_SPEED100; | |
2817 | break; | |
2818 | ||
2819 | case SPEED_1000: | |
2820 | bmcr |= TG3_BMCR_SPEED1000; | |
2821 | break; | |
855e1111 | 2822 | } |
1da177e4 LT |
2823 | |
2824 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2825 | bmcr |= BMCR_FULLDPLX; | |
2826 | ||
2827 | if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && | |
2828 | (bmcr != orig_bmcr)) { | |
2829 | tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); | |
2830 | for (i = 0; i < 1500; i++) { | |
2831 | u32 tmp; | |
2832 | ||
2833 | udelay(10); | |
2834 | if (tg3_readphy(tp, MII_BMSR, &tmp) || | |
2835 | tg3_readphy(tp, MII_BMSR, &tmp)) | |
2836 | continue; | |
2837 | if (!(tmp & BMSR_LSTATUS)) { | |
2838 | udelay(40); | |
2839 | break; | |
2840 | } | |
2841 | } | |
2842 | tg3_writephy(tp, MII_BMCR, bmcr); | |
2843 | udelay(40); | |
2844 | } | |
2845 | } else { | |
2846 | tg3_writephy(tp, MII_BMCR, | |
2847 | BMCR_ANENABLE | BMCR_ANRESTART); | |
2848 | } | |
2849 | } | |
2850 | ||
2851 | static int tg3_init_5401phy_dsp(struct tg3 *tp) | |
2852 | { | |
2853 | int err; | |
2854 | ||
2855 | /* Turn off tap power management. */ | |
2856 | /* Set Extended packet length bit */ | |
2857 | err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20); | |
2858 | ||
2859 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012); | |
2860 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804); | |
2861 | ||
2862 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013); | |
2863 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204); | |
2864 | ||
2865 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006); | |
2866 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132); | |
2867 | ||
2868 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006); | |
2869 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232); | |
2870 | ||
2871 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f); | |
2872 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20); | |
2873 | ||
2874 | udelay(40); | |
2875 | ||
2876 | return err; | |
2877 | } | |
2878 | ||
3600d918 | 2879 | static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask) |
1da177e4 | 2880 | { |
3600d918 MC |
2881 | u32 adv_reg, all_mask = 0; |
2882 | ||
2883 | if (mask & ADVERTISED_10baseT_Half) | |
2884 | all_mask |= ADVERTISE_10HALF; | |
2885 | if (mask & ADVERTISED_10baseT_Full) | |
2886 | all_mask |= ADVERTISE_10FULL; | |
2887 | if (mask & ADVERTISED_100baseT_Half) | |
2888 | all_mask |= ADVERTISE_100HALF; | |
2889 | if (mask & ADVERTISED_100baseT_Full) | |
2890 | all_mask |= ADVERTISE_100FULL; | |
1da177e4 LT |
2891 | |
2892 | if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg)) | |
2893 | return 0; | |
2894 | ||
1da177e4 LT |
2895 | if ((adv_reg & all_mask) != all_mask) |
2896 | return 0; | |
2897 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) { | |
2898 | u32 tg3_ctrl; | |
2899 | ||
3600d918 MC |
2900 | all_mask = 0; |
2901 | if (mask & ADVERTISED_1000baseT_Half) | |
2902 | all_mask |= ADVERTISE_1000HALF; | |
2903 | if (mask & ADVERTISED_1000baseT_Full) | |
2904 | all_mask |= ADVERTISE_1000FULL; | |
2905 | ||
1da177e4 LT |
2906 | if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl)) |
2907 | return 0; | |
2908 | ||
1da177e4 LT |
2909 | if ((tg3_ctrl & all_mask) != all_mask) |
2910 | return 0; | |
2911 | } | |
2912 | return 1; | |
2913 | } | |
2914 | ||
ef167e27 MC |
2915 | static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv) |
2916 | { | |
2917 | u32 curadv, reqadv; | |
2918 | ||
2919 | if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) | |
2920 | return 1; | |
2921 | ||
2922 | curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); | |
2923 | reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
2924 | ||
2925 | if (tp->link_config.active_duplex == DUPLEX_FULL) { | |
2926 | if (curadv != reqadv) | |
2927 | return 0; | |
2928 | ||
2929 | if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) | |
2930 | tg3_readphy(tp, MII_LPA, rmtadv); | |
2931 | } else { | |
2932 | /* Reprogram the advertisement register, even if it | |
2933 | * does not affect the current link. If the link | |
2934 | * gets renegotiated in the future, we can save an | |
2935 | * additional renegotiation cycle by advertising | |
2936 | * it correctly in the first place. | |
2937 | */ | |
2938 | if (curadv != reqadv) { | |
2939 | *lcladv &= ~(ADVERTISE_PAUSE_CAP | | |
2940 | ADVERTISE_PAUSE_ASYM); | |
2941 | tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv); | |
2942 | } | |
2943 | } | |
2944 | ||
2945 | return 1; | |
2946 | } | |
2947 | ||
1da177e4 LT |
2948 | static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) |
2949 | { | |
2950 | int current_link_up; | |
2951 | u32 bmsr, dummy; | |
ef167e27 | 2952 | u32 lcl_adv, rmt_adv; |
1da177e4 LT |
2953 | u16 current_speed; |
2954 | u8 current_duplex; | |
2955 | int i, err; | |
2956 | ||
2957 | tw32(MAC_EVENT, 0); | |
2958 | ||
2959 | tw32_f(MAC_STATUS, | |
2960 | (MAC_STATUS_SYNC_CHANGED | | |
2961 | MAC_STATUS_CFG_CHANGED | | |
2962 | MAC_STATUS_MI_COMPLETION | | |
2963 | MAC_STATUS_LNKSTATE_CHANGED)); | |
2964 | udelay(40); | |
2965 | ||
8ef21428 MC |
2966 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
2967 | tw32_f(MAC_MI_MODE, | |
2968 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
2969 | udelay(80); | |
2970 | } | |
1da177e4 LT |
2971 | |
2972 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02); | |
2973 | ||
2974 | /* Some third-party PHYs need to be reset on link going | |
2975 | * down. | |
2976 | */ | |
2977 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
2978 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2979 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
2980 | netif_carrier_ok(tp->dev)) { | |
2981 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
2982 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
2983 | !(bmsr & BMSR_LSTATUS)) | |
2984 | force_reset = 1; | |
2985 | } | |
2986 | if (force_reset) | |
2987 | tg3_phy_reset(tp); | |
2988 | ||
2989 | if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { | |
2990 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
2991 | if (tg3_readphy(tp, MII_BMSR, &bmsr) || | |
2992 | !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) | |
2993 | bmsr = 0; | |
2994 | ||
2995 | if (!(bmsr & BMSR_LSTATUS)) { | |
2996 | err = tg3_init_5401phy_dsp(tp); | |
2997 | if (err) | |
2998 | return err; | |
2999 | ||
3000 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3001 | for (i = 0; i < 1000; i++) { | |
3002 | udelay(10); | |
3003 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3004 | (bmsr & BMSR_LSTATUS)) { | |
3005 | udelay(40); | |
3006 | break; | |
3007 | } | |
3008 | } | |
3009 | ||
3010 | if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 && | |
3011 | !(bmsr & BMSR_LSTATUS) && | |
3012 | tp->link_config.active_speed == SPEED_1000) { | |
3013 | err = tg3_phy_reset(tp); | |
3014 | if (!err) | |
3015 | err = tg3_init_5401phy_dsp(tp); | |
3016 | if (err) | |
3017 | return err; | |
3018 | } | |
3019 | } | |
3020 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
3021 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { | |
3022 | /* 5701 {A0,B0} CRC bug workaround */ | |
3023 | tg3_writephy(tp, 0x15, 0x0a75); | |
3024 | tg3_writephy(tp, 0x1c, 0x8c68); | |
3025 | tg3_writephy(tp, 0x1c, 0x8d68); | |
3026 | tg3_writephy(tp, 0x1c, 0x8c68); | |
3027 | } | |
3028 | ||
3029 | /* Clear pending interrupts... */ | |
3030 | tg3_readphy(tp, MII_TG3_ISTAT, &dummy); | |
3031 | tg3_readphy(tp, MII_TG3_ISTAT, &dummy); | |
3032 | ||
3033 | if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) | |
3034 | tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); | |
7f97a4bd | 3035 | else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) |
1da177e4 LT |
3036 | tg3_writephy(tp, MII_TG3_IMASK, ~0); |
3037 | ||
3038 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3039 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3040 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) | |
3041 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
3042 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
3043 | else | |
3044 | tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); | |
3045 | } | |
3046 | ||
3047 | current_link_up = 0; | |
3048 | current_speed = SPEED_INVALID; | |
3049 | current_duplex = DUPLEX_INVALID; | |
3050 | ||
3051 | if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) { | |
3052 | u32 val; | |
3053 | ||
3054 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007); | |
3055 | tg3_readphy(tp, MII_TG3_AUX_CTRL, &val); | |
3056 | if (!(val & (1 << 10))) { | |
3057 | val |= (1 << 10); | |
3058 | tg3_writephy(tp, MII_TG3_AUX_CTRL, val); | |
3059 | goto relink; | |
3060 | } | |
3061 | } | |
3062 | ||
3063 | bmsr = 0; | |
3064 | for (i = 0; i < 100; i++) { | |
3065 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3066 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3067 | (bmsr & BMSR_LSTATUS)) | |
3068 | break; | |
3069 | udelay(40); | |
3070 | } | |
3071 | ||
3072 | if (bmsr & BMSR_LSTATUS) { | |
3073 | u32 aux_stat, bmcr; | |
3074 | ||
3075 | tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); | |
3076 | for (i = 0; i < 2000; i++) { | |
3077 | udelay(10); | |
3078 | if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && | |
3079 | aux_stat) | |
3080 | break; | |
3081 | } | |
3082 | ||
3083 | tg3_aux_stat_to_speed_duplex(tp, aux_stat, | |
3084 | ¤t_speed, | |
3085 | ¤t_duplex); | |
3086 | ||
3087 | bmcr = 0; | |
3088 | for (i = 0; i < 200; i++) { | |
3089 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
3090 | if (tg3_readphy(tp, MII_BMCR, &bmcr)) | |
3091 | continue; | |
3092 | if (bmcr && bmcr != 0x7fff) | |
3093 | break; | |
3094 | udelay(10); | |
3095 | } | |
3096 | ||
ef167e27 MC |
3097 | lcl_adv = 0; |
3098 | rmt_adv = 0; | |
1da177e4 | 3099 | |
ef167e27 MC |
3100 | tp->link_config.active_speed = current_speed; |
3101 | tp->link_config.active_duplex = current_duplex; | |
3102 | ||
3103 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
3104 | if ((bmcr & BMCR_ANENABLE) && | |
3105 | tg3_copper_is_advertising_all(tp, | |
3106 | tp->link_config.advertising)) { | |
3107 | if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv, | |
3108 | &rmt_adv)) | |
3109 | current_link_up = 1; | |
1da177e4 LT |
3110 | } |
3111 | } else { | |
3112 | if (!(bmcr & BMCR_ANENABLE) && | |
3113 | tp->link_config.speed == current_speed && | |
ef167e27 MC |
3114 | tp->link_config.duplex == current_duplex && |
3115 | tp->link_config.flowctrl == | |
3116 | tp->link_config.active_flowctrl) { | |
1da177e4 | 3117 | current_link_up = 1; |
1da177e4 LT |
3118 | } |
3119 | } | |
3120 | ||
ef167e27 MC |
3121 | if (current_link_up == 1 && |
3122 | tp->link_config.active_duplex == DUPLEX_FULL) | |
3123 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1da177e4 LT |
3124 | } |
3125 | ||
1da177e4 | 3126 | relink: |
6921d201 | 3127 | if (current_link_up == 0 || tp->link_config.phy_is_low_power) { |
1da177e4 LT |
3128 | u32 tmp; |
3129 | ||
3130 | tg3_phy_copper_begin(tp); | |
3131 | ||
3132 | tg3_readphy(tp, MII_BMSR, &tmp); | |
3133 | if (!tg3_readphy(tp, MII_BMSR, &tmp) && | |
3134 | (tmp & BMSR_LSTATUS)) | |
3135 | current_link_up = 1; | |
3136 | } | |
3137 | ||
3138 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; | |
3139 | if (current_link_up == 1) { | |
3140 | if (tp->link_config.active_speed == SPEED_100 || | |
3141 | tp->link_config.active_speed == SPEED_10) | |
3142 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
3143 | else | |
3144 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
7f97a4bd MC |
3145 | } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) |
3146 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
3147 | else | |
1da177e4 LT |
3148 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
3149 | ||
3150 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
3151 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
3152 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
3153 | ||
1da177e4 | 3154 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
e8f3f6ca MC |
3155 | if (current_link_up == 1 && |
3156 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) | |
1da177e4 | 3157 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; |
e8f3f6ca MC |
3158 | else |
3159 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
3160 | } |
3161 | ||
3162 | /* ??? Without this setting Netgear GA302T PHY does not | |
3163 | * ??? send/receive packets... | |
3164 | */ | |
3165 | if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 && | |
3166 | tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { | |
3167 | tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; | |
3168 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
3169 | udelay(80); | |
3170 | } | |
3171 | ||
3172 | tw32_f(MAC_MODE, tp->mac_mode); | |
3173 | udelay(40); | |
3174 | ||
3175 | if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) { | |
3176 | /* Polled via timer. */ | |
3177 | tw32_f(MAC_EVENT, 0); | |
3178 | } else { | |
3179 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3180 | } | |
3181 | udelay(40); | |
3182 | ||
3183 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && | |
3184 | current_link_up == 1 && | |
3185 | tp->link_config.active_speed == SPEED_1000 && | |
3186 | ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) || | |
3187 | (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) { | |
3188 | udelay(120); | |
3189 | tw32_f(MAC_STATUS, | |
3190 | (MAC_STATUS_SYNC_CHANGED | | |
3191 | MAC_STATUS_CFG_CHANGED)); | |
3192 | udelay(40); | |
3193 | tg3_write_mem(tp, | |
3194 | NIC_SRAM_FIRMWARE_MBOX, | |
3195 | NIC_SRAM_FIRMWARE_MBOX_MAGIC2); | |
3196 | } | |
3197 | ||
5e7dfd0f MC |
3198 | /* Prevent send BD corruption. */ |
3199 | if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) { | |
3200 | u16 oldlnkctl, newlnkctl; | |
3201 | ||
3202 | pci_read_config_word(tp->pdev, | |
3203 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
3204 | &oldlnkctl); | |
3205 | if (tp->link_config.active_speed == SPEED_100 || | |
3206 | tp->link_config.active_speed == SPEED_10) | |
3207 | newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
3208 | else | |
3209 | newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN; | |
3210 | if (newlnkctl != oldlnkctl) | |
3211 | pci_write_config_word(tp->pdev, | |
3212 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
3213 | newlnkctl); | |
255ca311 MC |
3214 | } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) { |
3215 | u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL); | |
3216 | if (tp->link_config.active_speed == SPEED_100 || | |
3217 | tp->link_config.active_speed == SPEED_10) | |
3218 | newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; | |
3219 | else | |
3220 | newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN; | |
3221 | if (newreg != oldreg) | |
3222 | tw32(TG3_PCIE_LNKCTL, newreg); | |
5e7dfd0f MC |
3223 | } |
3224 | ||
1da177e4 LT |
3225 | if (current_link_up != netif_carrier_ok(tp->dev)) { |
3226 | if (current_link_up) | |
3227 | netif_carrier_on(tp->dev); | |
3228 | else | |
3229 | netif_carrier_off(tp->dev); | |
3230 | tg3_link_report(tp); | |
3231 | } | |
3232 | ||
3233 | return 0; | |
3234 | } | |
3235 | ||
3236 | struct tg3_fiber_aneginfo { | |
3237 | int state; | |
3238 | #define ANEG_STATE_UNKNOWN 0 | |
3239 | #define ANEG_STATE_AN_ENABLE 1 | |
3240 | #define ANEG_STATE_RESTART_INIT 2 | |
3241 | #define ANEG_STATE_RESTART 3 | |
3242 | #define ANEG_STATE_DISABLE_LINK_OK 4 | |
3243 | #define ANEG_STATE_ABILITY_DETECT_INIT 5 | |
3244 | #define ANEG_STATE_ABILITY_DETECT 6 | |
3245 | #define ANEG_STATE_ACK_DETECT_INIT 7 | |
3246 | #define ANEG_STATE_ACK_DETECT 8 | |
3247 | #define ANEG_STATE_COMPLETE_ACK_INIT 9 | |
3248 | #define ANEG_STATE_COMPLETE_ACK 10 | |
3249 | #define ANEG_STATE_IDLE_DETECT_INIT 11 | |
3250 | #define ANEG_STATE_IDLE_DETECT 12 | |
3251 | #define ANEG_STATE_LINK_OK 13 | |
3252 | #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14 | |
3253 | #define ANEG_STATE_NEXT_PAGE_WAIT 15 | |
3254 | ||
3255 | u32 flags; | |
3256 | #define MR_AN_ENABLE 0x00000001 | |
3257 | #define MR_RESTART_AN 0x00000002 | |
3258 | #define MR_AN_COMPLETE 0x00000004 | |
3259 | #define MR_PAGE_RX 0x00000008 | |
3260 | #define MR_NP_LOADED 0x00000010 | |
3261 | #define MR_TOGGLE_TX 0x00000020 | |
3262 | #define MR_LP_ADV_FULL_DUPLEX 0x00000040 | |
3263 | #define MR_LP_ADV_HALF_DUPLEX 0x00000080 | |
3264 | #define MR_LP_ADV_SYM_PAUSE 0x00000100 | |
3265 | #define MR_LP_ADV_ASYM_PAUSE 0x00000200 | |
3266 | #define MR_LP_ADV_REMOTE_FAULT1 0x00000400 | |
3267 | #define MR_LP_ADV_REMOTE_FAULT2 0x00000800 | |
3268 | #define MR_LP_ADV_NEXT_PAGE 0x00001000 | |
3269 | #define MR_TOGGLE_RX 0x00002000 | |
3270 | #define MR_NP_RX 0x00004000 | |
3271 | ||
3272 | #define MR_LINK_OK 0x80000000 | |
3273 | ||
3274 | unsigned long link_time, cur_time; | |
3275 | ||
3276 | u32 ability_match_cfg; | |
3277 | int ability_match_count; | |
3278 | ||
3279 | char ability_match, idle_match, ack_match; | |
3280 | ||
3281 | u32 txconfig, rxconfig; | |
3282 | #define ANEG_CFG_NP 0x00000080 | |
3283 | #define ANEG_CFG_ACK 0x00000040 | |
3284 | #define ANEG_CFG_RF2 0x00000020 | |
3285 | #define ANEG_CFG_RF1 0x00000010 | |
3286 | #define ANEG_CFG_PS2 0x00000001 | |
3287 | #define ANEG_CFG_PS1 0x00008000 | |
3288 | #define ANEG_CFG_HD 0x00004000 | |
3289 | #define ANEG_CFG_FD 0x00002000 | |
3290 | #define ANEG_CFG_INVAL 0x00001f06 | |
3291 | ||
3292 | }; | |
3293 | #define ANEG_OK 0 | |
3294 | #define ANEG_DONE 1 | |
3295 | #define ANEG_TIMER_ENAB 2 | |
3296 | #define ANEG_FAILED -1 | |
3297 | ||
3298 | #define ANEG_STATE_SETTLE_TIME 10000 | |
3299 | ||
3300 | static int tg3_fiber_aneg_smachine(struct tg3 *tp, | |
3301 | struct tg3_fiber_aneginfo *ap) | |
3302 | { | |
5be73b47 | 3303 | u16 flowctrl; |
1da177e4 LT |
3304 | unsigned long delta; |
3305 | u32 rx_cfg_reg; | |
3306 | int ret; | |
3307 | ||
3308 | if (ap->state == ANEG_STATE_UNKNOWN) { | |
3309 | ap->rxconfig = 0; | |
3310 | ap->link_time = 0; | |
3311 | ap->cur_time = 0; | |
3312 | ap->ability_match_cfg = 0; | |
3313 | ap->ability_match_count = 0; | |
3314 | ap->ability_match = 0; | |
3315 | ap->idle_match = 0; | |
3316 | ap->ack_match = 0; | |
3317 | } | |
3318 | ap->cur_time++; | |
3319 | ||
3320 | if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { | |
3321 | rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); | |
3322 | ||
3323 | if (rx_cfg_reg != ap->ability_match_cfg) { | |
3324 | ap->ability_match_cfg = rx_cfg_reg; | |
3325 | ap->ability_match = 0; | |
3326 | ap->ability_match_count = 0; | |
3327 | } else { | |
3328 | if (++ap->ability_match_count > 1) { | |
3329 | ap->ability_match = 1; | |
3330 | ap->ability_match_cfg = rx_cfg_reg; | |
3331 | } | |
3332 | } | |
3333 | if (rx_cfg_reg & ANEG_CFG_ACK) | |
3334 | ap->ack_match = 1; | |
3335 | else | |
3336 | ap->ack_match = 0; | |
3337 | ||
3338 | ap->idle_match = 0; | |
3339 | } else { | |
3340 | ap->idle_match = 1; | |
3341 | ap->ability_match_cfg = 0; | |
3342 | ap->ability_match_count = 0; | |
3343 | ap->ability_match = 0; | |
3344 | ap->ack_match = 0; | |
3345 | ||
3346 | rx_cfg_reg = 0; | |
3347 | } | |
3348 | ||
3349 | ap->rxconfig = rx_cfg_reg; | |
3350 | ret = ANEG_OK; | |
3351 | ||
3352 | switch(ap->state) { | |
3353 | case ANEG_STATE_UNKNOWN: | |
3354 | if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) | |
3355 | ap->state = ANEG_STATE_AN_ENABLE; | |
3356 | ||
3357 | /* fallthru */ | |
3358 | case ANEG_STATE_AN_ENABLE: | |
3359 | ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); | |
3360 | if (ap->flags & MR_AN_ENABLE) { | |
3361 | ap->link_time = 0; | |
3362 | ap->cur_time = 0; | |
3363 | ap->ability_match_cfg = 0; | |
3364 | ap->ability_match_count = 0; | |
3365 | ap->ability_match = 0; | |
3366 | ap->idle_match = 0; | |
3367 | ap->ack_match = 0; | |
3368 | ||
3369 | ap->state = ANEG_STATE_RESTART_INIT; | |
3370 | } else { | |
3371 | ap->state = ANEG_STATE_DISABLE_LINK_OK; | |
3372 | } | |
3373 | break; | |
3374 | ||
3375 | case ANEG_STATE_RESTART_INIT: | |
3376 | ap->link_time = ap->cur_time; | |
3377 | ap->flags &= ~(MR_NP_LOADED); | |
3378 | ap->txconfig = 0; | |
3379 | tw32(MAC_TX_AUTO_NEG, 0); | |
3380 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3381 | tw32_f(MAC_MODE, tp->mac_mode); | |
3382 | udelay(40); | |
3383 | ||
3384 | ret = ANEG_TIMER_ENAB; | |
3385 | ap->state = ANEG_STATE_RESTART; | |
3386 | ||
3387 | /* fallthru */ | |
3388 | case ANEG_STATE_RESTART: | |
3389 | delta = ap->cur_time - ap->link_time; | |
3390 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3391 | ap->state = ANEG_STATE_ABILITY_DETECT_INIT; | |
3392 | } else { | |
3393 | ret = ANEG_TIMER_ENAB; | |
3394 | } | |
3395 | break; | |
3396 | ||
3397 | case ANEG_STATE_DISABLE_LINK_OK: | |
3398 | ret = ANEG_DONE; | |
3399 | break; | |
3400 | ||
3401 | case ANEG_STATE_ABILITY_DETECT_INIT: | |
3402 | ap->flags &= ~(MR_TOGGLE_TX); | |
5be73b47 MC |
3403 | ap->txconfig = ANEG_CFG_FD; |
3404 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
3405 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
3406 | ap->txconfig |= ANEG_CFG_PS1; | |
3407 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
3408 | ap->txconfig |= ANEG_CFG_PS2; | |
1da177e4 LT |
3409 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); |
3410 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3411 | tw32_f(MAC_MODE, tp->mac_mode); | |
3412 | udelay(40); | |
3413 | ||
3414 | ap->state = ANEG_STATE_ABILITY_DETECT; | |
3415 | break; | |
3416 | ||
3417 | case ANEG_STATE_ABILITY_DETECT: | |
3418 | if (ap->ability_match != 0 && ap->rxconfig != 0) { | |
3419 | ap->state = ANEG_STATE_ACK_DETECT_INIT; | |
3420 | } | |
3421 | break; | |
3422 | ||
3423 | case ANEG_STATE_ACK_DETECT_INIT: | |
3424 | ap->txconfig |= ANEG_CFG_ACK; | |
3425 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); | |
3426 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3427 | tw32_f(MAC_MODE, tp->mac_mode); | |
3428 | udelay(40); | |
3429 | ||
3430 | ap->state = ANEG_STATE_ACK_DETECT; | |
3431 | ||
3432 | /* fallthru */ | |
3433 | case ANEG_STATE_ACK_DETECT: | |
3434 | if (ap->ack_match != 0) { | |
3435 | if ((ap->rxconfig & ~ANEG_CFG_ACK) == | |
3436 | (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { | |
3437 | ap->state = ANEG_STATE_COMPLETE_ACK_INIT; | |
3438 | } else { | |
3439 | ap->state = ANEG_STATE_AN_ENABLE; | |
3440 | } | |
3441 | } else if (ap->ability_match != 0 && | |
3442 | ap->rxconfig == 0) { | |
3443 | ap->state = ANEG_STATE_AN_ENABLE; | |
3444 | } | |
3445 | break; | |
3446 | ||
3447 | case ANEG_STATE_COMPLETE_ACK_INIT: | |
3448 | if (ap->rxconfig & ANEG_CFG_INVAL) { | |
3449 | ret = ANEG_FAILED; | |
3450 | break; | |
3451 | } | |
3452 | ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | | |
3453 | MR_LP_ADV_HALF_DUPLEX | | |
3454 | MR_LP_ADV_SYM_PAUSE | | |
3455 | MR_LP_ADV_ASYM_PAUSE | | |
3456 | MR_LP_ADV_REMOTE_FAULT1 | | |
3457 | MR_LP_ADV_REMOTE_FAULT2 | | |
3458 | MR_LP_ADV_NEXT_PAGE | | |
3459 | MR_TOGGLE_RX | | |
3460 | MR_NP_RX); | |
3461 | if (ap->rxconfig & ANEG_CFG_FD) | |
3462 | ap->flags |= MR_LP_ADV_FULL_DUPLEX; | |
3463 | if (ap->rxconfig & ANEG_CFG_HD) | |
3464 | ap->flags |= MR_LP_ADV_HALF_DUPLEX; | |
3465 | if (ap->rxconfig & ANEG_CFG_PS1) | |
3466 | ap->flags |= MR_LP_ADV_SYM_PAUSE; | |
3467 | if (ap->rxconfig & ANEG_CFG_PS2) | |
3468 | ap->flags |= MR_LP_ADV_ASYM_PAUSE; | |
3469 | if (ap->rxconfig & ANEG_CFG_RF1) | |
3470 | ap->flags |= MR_LP_ADV_REMOTE_FAULT1; | |
3471 | if (ap->rxconfig & ANEG_CFG_RF2) | |
3472 | ap->flags |= MR_LP_ADV_REMOTE_FAULT2; | |
3473 | if (ap->rxconfig & ANEG_CFG_NP) | |
3474 | ap->flags |= MR_LP_ADV_NEXT_PAGE; | |
3475 | ||
3476 | ap->link_time = ap->cur_time; | |
3477 | ||
3478 | ap->flags ^= (MR_TOGGLE_TX); | |
3479 | if (ap->rxconfig & 0x0008) | |
3480 | ap->flags |= MR_TOGGLE_RX; | |
3481 | if (ap->rxconfig & ANEG_CFG_NP) | |
3482 | ap->flags |= MR_NP_RX; | |
3483 | ap->flags |= MR_PAGE_RX; | |
3484 | ||
3485 | ap->state = ANEG_STATE_COMPLETE_ACK; | |
3486 | ret = ANEG_TIMER_ENAB; | |
3487 | break; | |
3488 | ||
3489 | case ANEG_STATE_COMPLETE_ACK: | |
3490 | if (ap->ability_match != 0 && | |
3491 | ap->rxconfig == 0) { | |
3492 | ap->state = ANEG_STATE_AN_ENABLE; | |
3493 | break; | |
3494 | } | |
3495 | delta = ap->cur_time - ap->link_time; | |
3496 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3497 | if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { | |
3498 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3499 | } else { | |
3500 | if ((ap->txconfig & ANEG_CFG_NP) == 0 && | |
3501 | !(ap->flags & MR_NP_RX)) { | |
3502 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3503 | } else { | |
3504 | ret = ANEG_FAILED; | |
3505 | } | |
3506 | } | |
3507 | } | |
3508 | break; | |
3509 | ||
3510 | case ANEG_STATE_IDLE_DETECT_INIT: | |
3511 | ap->link_time = ap->cur_time; | |
3512 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3513 | tw32_f(MAC_MODE, tp->mac_mode); | |
3514 | udelay(40); | |
3515 | ||
3516 | ap->state = ANEG_STATE_IDLE_DETECT; | |
3517 | ret = ANEG_TIMER_ENAB; | |
3518 | break; | |
3519 | ||
3520 | case ANEG_STATE_IDLE_DETECT: | |
3521 | if (ap->ability_match != 0 && | |
3522 | ap->rxconfig == 0) { | |
3523 | ap->state = ANEG_STATE_AN_ENABLE; | |
3524 | break; | |
3525 | } | |
3526 | delta = ap->cur_time - ap->link_time; | |
3527 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3528 | /* XXX another gem from the Broadcom driver :( */ | |
3529 | ap->state = ANEG_STATE_LINK_OK; | |
3530 | } | |
3531 | break; | |
3532 | ||
3533 | case ANEG_STATE_LINK_OK: | |
3534 | ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); | |
3535 | ret = ANEG_DONE; | |
3536 | break; | |
3537 | ||
3538 | case ANEG_STATE_NEXT_PAGE_WAIT_INIT: | |
3539 | /* ??? unimplemented */ | |
3540 | break; | |
3541 | ||
3542 | case ANEG_STATE_NEXT_PAGE_WAIT: | |
3543 | /* ??? unimplemented */ | |
3544 | break; | |
3545 | ||
3546 | default: | |
3547 | ret = ANEG_FAILED; | |
3548 | break; | |
855e1111 | 3549 | } |
1da177e4 LT |
3550 | |
3551 | return ret; | |
3552 | } | |
3553 | ||
5be73b47 | 3554 | static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) |
1da177e4 LT |
3555 | { |
3556 | int res = 0; | |
3557 | struct tg3_fiber_aneginfo aninfo; | |
3558 | int status = ANEG_FAILED; | |
3559 | unsigned int tick; | |
3560 | u32 tmp; | |
3561 | ||
3562 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
3563 | ||
3564 | tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; | |
3565 | tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII); | |
3566 | udelay(40); | |
3567 | ||
3568 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); | |
3569 | udelay(40); | |
3570 | ||
3571 | memset(&aninfo, 0, sizeof(aninfo)); | |
3572 | aninfo.flags |= MR_AN_ENABLE; | |
3573 | aninfo.state = ANEG_STATE_UNKNOWN; | |
3574 | aninfo.cur_time = 0; | |
3575 | tick = 0; | |
3576 | while (++tick < 195000) { | |
3577 | status = tg3_fiber_aneg_smachine(tp, &aninfo); | |
3578 | if (status == ANEG_DONE || status == ANEG_FAILED) | |
3579 | break; | |
3580 | ||
3581 | udelay(1); | |
3582 | } | |
3583 | ||
3584 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3585 | tw32_f(MAC_MODE, tp->mac_mode); | |
3586 | udelay(40); | |
3587 | ||
5be73b47 MC |
3588 | *txflags = aninfo.txconfig; |
3589 | *rxflags = aninfo.flags; | |
1da177e4 LT |
3590 | |
3591 | if (status == ANEG_DONE && | |
3592 | (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK | | |
3593 | MR_LP_ADV_FULL_DUPLEX))) | |
3594 | res = 1; | |
3595 | ||
3596 | return res; | |
3597 | } | |
3598 | ||
3599 | static void tg3_init_bcm8002(struct tg3 *tp) | |
3600 | { | |
3601 | u32 mac_status = tr32(MAC_STATUS); | |
3602 | int i; | |
3603 | ||
3604 | /* Reset when initting first time or we have a link. */ | |
3605 | if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) && | |
3606 | !(mac_status & MAC_STATUS_PCS_SYNCED)) | |
3607 | return; | |
3608 | ||
3609 | /* Set PLL lock range. */ | |
3610 | tg3_writephy(tp, 0x16, 0x8007); | |
3611 | ||
3612 | /* SW reset */ | |
3613 | tg3_writephy(tp, MII_BMCR, BMCR_RESET); | |
3614 | ||
3615 | /* Wait for reset to complete. */ | |
3616 | /* XXX schedule_timeout() ... */ | |
3617 | for (i = 0; i < 500; i++) | |
3618 | udelay(10); | |
3619 | ||
3620 | /* Config mode; select PMA/Ch 1 regs. */ | |
3621 | tg3_writephy(tp, 0x10, 0x8411); | |
3622 | ||
3623 | /* Enable auto-lock and comdet, select txclk for tx. */ | |
3624 | tg3_writephy(tp, 0x11, 0x0a10); | |
3625 | ||
3626 | tg3_writephy(tp, 0x18, 0x00a0); | |
3627 | tg3_writephy(tp, 0x16, 0x41ff); | |
3628 | ||
3629 | /* Assert and deassert POR. */ | |
3630 | tg3_writephy(tp, 0x13, 0x0400); | |
3631 | udelay(40); | |
3632 | tg3_writephy(tp, 0x13, 0x0000); | |
3633 | ||
3634 | tg3_writephy(tp, 0x11, 0x0a50); | |
3635 | udelay(40); | |
3636 | tg3_writephy(tp, 0x11, 0x0a10); | |
3637 | ||
3638 | /* Wait for signal to stabilize */ | |
3639 | /* XXX schedule_timeout() ... */ | |
3640 | for (i = 0; i < 15000; i++) | |
3641 | udelay(10); | |
3642 | ||
3643 | /* Deselect the channel register so we can read the PHYID | |
3644 | * later. | |
3645 | */ | |
3646 | tg3_writephy(tp, 0x10, 0x8011); | |
3647 | } | |
3648 | ||
3649 | static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) | |
3650 | { | |
82cd3d11 | 3651 | u16 flowctrl; |
1da177e4 LT |
3652 | u32 sg_dig_ctrl, sg_dig_status; |
3653 | u32 serdes_cfg, expected_sg_dig_ctrl; | |
3654 | int workaround, port_a; | |
3655 | int current_link_up; | |
3656 | ||
3657 | serdes_cfg = 0; | |
3658 | expected_sg_dig_ctrl = 0; | |
3659 | workaround = 0; | |
3660 | port_a = 1; | |
3661 | current_link_up = 0; | |
3662 | ||
3663 | if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 && | |
3664 | tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) { | |
3665 | workaround = 1; | |
3666 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) | |
3667 | port_a = 0; | |
3668 | ||
3669 | /* preserve bits 0-11,13,14 for signal pre-emphasis */ | |
3670 | /* preserve bits 20-23 for voltage regulator */ | |
3671 | serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; | |
3672 | } | |
3673 | ||
3674 | sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
3675 | ||
3676 | if (tp->link_config.autoneg != AUTONEG_ENABLE) { | |
c98f6e3b | 3677 | if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) { |
1da177e4 LT |
3678 | if (workaround) { |
3679 | u32 val = serdes_cfg; | |
3680 | ||
3681 | if (port_a) | |
3682 | val |= 0xc010000; | |
3683 | else | |
3684 | val |= 0x4010000; | |
3685 | tw32_f(MAC_SERDES_CFG, val); | |
3686 | } | |
c98f6e3b MC |
3687 | |
3688 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); | |
1da177e4 LT |
3689 | } |
3690 | if (mac_status & MAC_STATUS_PCS_SYNCED) { | |
3691 | tg3_setup_flow_control(tp, 0, 0); | |
3692 | current_link_up = 1; | |
3693 | } | |
3694 | goto out; | |
3695 | } | |
3696 | ||
3697 | /* Want auto-negotiation. */ | |
c98f6e3b | 3698 | expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP; |
1da177e4 | 3699 | |
82cd3d11 MC |
3700 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
3701 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
3702 | expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP; | |
3703 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
3704 | expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE; | |
1da177e4 LT |
3705 | |
3706 | if (sg_dig_ctrl != expected_sg_dig_ctrl) { | |
3d3ebe74 MC |
3707 | if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) && |
3708 | tp->serdes_counter && | |
3709 | ((mac_status & (MAC_STATUS_PCS_SYNCED | | |
3710 | MAC_STATUS_RCVD_CFG)) == | |
3711 | MAC_STATUS_PCS_SYNCED)) { | |
3712 | tp->serdes_counter--; | |
3713 | current_link_up = 1; | |
3714 | goto out; | |
3715 | } | |
3716 | restart_autoneg: | |
1da177e4 LT |
3717 | if (workaround) |
3718 | tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000); | |
c98f6e3b | 3719 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET); |
1da177e4 LT |
3720 | udelay(5); |
3721 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl); | |
3722 | ||
3d3ebe74 MC |
3723 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; |
3724 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
1da177e4 LT |
3725 | } else if (mac_status & (MAC_STATUS_PCS_SYNCED | |
3726 | MAC_STATUS_SIGNAL_DET)) { | |
3d3ebe74 | 3727 | sg_dig_status = tr32(SG_DIG_STATUS); |
1da177e4 LT |
3728 | mac_status = tr32(MAC_STATUS); |
3729 | ||
c98f6e3b | 3730 | if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) && |
1da177e4 | 3731 | (mac_status & MAC_STATUS_PCS_SYNCED)) { |
82cd3d11 MC |
3732 | u32 local_adv = 0, remote_adv = 0; |
3733 | ||
3734 | if (sg_dig_ctrl & SG_DIG_PAUSE_CAP) | |
3735 | local_adv |= ADVERTISE_1000XPAUSE; | |
3736 | if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE) | |
3737 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
1da177e4 | 3738 | |
c98f6e3b | 3739 | if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE) |
82cd3d11 | 3740 | remote_adv |= LPA_1000XPAUSE; |
c98f6e3b | 3741 | if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE) |
82cd3d11 | 3742 | remote_adv |= LPA_1000XPAUSE_ASYM; |
1da177e4 LT |
3743 | |
3744 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
3745 | current_link_up = 1; | |
3d3ebe74 MC |
3746 | tp->serdes_counter = 0; |
3747 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
c98f6e3b | 3748 | } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { |
3d3ebe74 MC |
3749 | if (tp->serdes_counter) |
3750 | tp->serdes_counter--; | |
1da177e4 LT |
3751 | else { |
3752 | if (workaround) { | |
3753 | u32 val = serdes_cfg; | |
3754 | ||
3755 | if (port_a) | |
3756 | val |= 0xc010000; | |
3757 | else | |
3758 | val |= 0x4010000; | |
3759 | ||
3760 | tw32_f(MAC_SERDES_CFG, val); | |
3761 | } | |
3762 | ||
c98f6e3b | 3763 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); |
1da177e4 LT |
3764 | udelay(40); |
3765 | ||
3766 | /* Link parallel detection - link is up */ | |
3767 | /* only if we have PCS_SYNC and not */ | |
3768 | /* receiving config code words */ | |
3769 | mac_status = tr32(MAC_STATUS); | |
3770 | if ((mac_status & MAC_STATUS_PCS_SYNCED) && | |
3771 | !(mac_status & MAC_STATUS_RCVD_CFG)) { | |
3772 | tg3_setup_flow_control(tp, 0, 0); | |
3773 | current_link_up = 1; | |
3d3ebe74 MC |
3774 | tp->tg3_flags2 |= |
3775 | TG3_FLG2_PARALLEL_DETECT; | |
3776 | tp->serdes_counter = | |
3777 | SERDES_PARALLEL_DET_TIMEOUT; | |
3778 | } else | |
3779 | goto restart_autoneg; | |
1da177e4 LT |
3780 | } |
3781 | } | |
3d3ebe74 MC |
3782 | } else { |
3783 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; | |
3784 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
1da177e4 LT |
3785 | } |
3786 | ||
3787 | out: | |
3788 | return current_link_up; | |
3789 | } | |
3790 | ||
3791 | static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) | |
3792 | { | |
3793 | int current_link_up = 0; | |
3794 | ||
5cf64b8a | 3795 | if (!(mac_status & MAC_STATUS_PCS_SYNCED)) |
1da177e4 | 3796 | goto out; |
1da177e4 LT |
3797 | |
3798 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
5be73b47 | 3799 | u32 txflags, rxflags; |
1da177e4 | 3800 | int i; |
6aa20a22 | 3801 | |
5be73b47 MC |
3802 | if (fiber_autoneg(tp, &txflags, &rxflags)) { |
3803 | u32 local_adv = 0, remote_adv = 0; | |
1da177e4 | 3804 | |
5be73b47 MC |
3805 | if (txflags & ANEG_CFG_PS1) |
3806 | local_adv |= ADVERTISE_1000XPAUSE; | |
3807 | if (txflags & ANEG_CFG_PS2) | |
3808 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
3809 | ||
3810 | if (rxflags & MR_LP_ADV_SYM_PAUSE) | |
3811 | remote_adv |= LPA_1000XPAUSE; | |
3812 | if (rxflags & MR_LP_ADV_ASYM_PAUSE) | |
3813 | remote_adv |= LPA_1000XPAUSE_ASYM; | |
1da177e4 LT |
3814 | |
3815 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
3816 | ||
1da177e4 LT |
3817 | current_link_up = 1; |
3818 | } | |
3819 | for (i = 0; i < 30; i++) { | |
3820 | udelay(20); | |
3821 | tw32_f(MAC_STATUS, | |
3822 | (MAC_STATUS_SYNC_CHANGED | | |
3823 | MAC_STATUS_CFG_CHANGED)); | |
3824 | udelay(40); | |
3825 | if ((tr32(MAC_STATUS) & | |
3826 | (MAC_STATUS_SYNC_CHANGED | | |
3827 | MAC_STATUS_CFG_CHANGED)) == 0) | |
3828 | break; | |
3829 | } | |
3830 | ||
3831 | mac_status = tr32(MAC_STATUS); | |
3832 | if (current_link_up == 0 && | |
3833 | (mac_status & MAC_STATUS_PCS_SYNCED) && | |
3834 | !(mac_status & MAC_STATUS_RCVD_CFG)) | |
3835 | current_link_up = 1; | |
3836 | } else { | |
5be73b47 MC |
3837 | tg3_setup_flow_control(tp, 0, 0); |
3838 | ||
1da177e4 LT |
3839 | /* Forcing 1000FD link up. */ |
3840 | current_link_up = 1; | |
1da177e4 LT |
3841 | |
3842 | tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); | |
3843 | udelay(40); | |
e8f3f6ca MC |
3844 | |
3845 | tw32_f(MAC_MODE, tp->mac_mode); | |
3846 | udelay(40); | |
1da177e4 LT |
3847 | } |
3848 | ||
3849 | out: | |
3850 | return current_link_up; | |
3851 | } | |
3852 | ||
3853 | static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | |
3854 | { | |
3855 | u32 orig_pause_cfg; | |
3856 | u16 orig_active_speed; | |
3857 | u8 orig_active_duplex; | |
3858 | u32 mac_status; | |
3859 | int current_link_up; | |
3860 | int i; | |
3861 | ||
8d018621 | 3862 | orig_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
3863 | orig_active_speed = tp->link_config.active_speed; |
3864 | orig_active_duplex = tp->link_config.active_duplex; | |
3865 | ||
3866 | if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) && | |
3867 | netif_carrier_ok(tp->dev) && | |
3868 | (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) { | |
3869 | mac_status = tr32(MAC_STATUS); | |
3870 | mac_status &= (MAC_STATUS_PCS_SYNCED | | |
3871 | MAC_STATUS_SIGNAL_DET | | |
3872 | MAC_STATUS_CFG_CHANGED | | |
3873 | MAC_STATUS_RCVD_CFG); | |
3874 | if (mac_status == (MAC_STATUS_PCS_SYNCED | | |
3875 | MAC_STATUS_SIGNAL_DET)) { | |
3876 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
3877 | MAC_STATUS_CFG_CHANGED)); | |
3878 | return 0; | |
3879 | } | |
3880 | } | |
3881 | ||
3882 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
3883 | ||
3884 | tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
3885 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; | |
3886 | tw32_f(MAC_MODE, tp->mac_mode); | |
3887 | udelay(40); | |
3888 | ||
3889 | if (tp->phy_id == PHY_ID_BCM8002) | |
3890 | tg3_init_bcm8002(tp); | |
3891 | ||
3892 | /* Enable link change event even when serdes polling. */ | |
3893 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3894 | udelay(40); | |
3895 | ||
3896 | current_link_up = 0; | |
3897 | mac_status = tr32(MAC_STATUS); | |
3898 | ||
3899 | if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) | |
3900 | current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); | |
3901 | else | |
3902 | current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); | |
3903 | ||
898a56f8 | 3904 | tp->napi[0].hw_status->status = |
1da177e4 | 3905 | (SD_STATUS_UPDATED | |
898a56f8 | 3906 | (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); |
1da177e4 LT |
3907 | |
3908 | for (i = 0; i < 100; i++) { | |
3909 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
3910 | MAC_STATUS_CFG_CHANGED)); | |
3911 | udelay(5); | |
3912 | if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | | |
3d3ebe74 MC |
3913 | MAC_STATUS_CFG_CHANGED | |
3914 | MAC_STATUS_LNKSTATE_CHANGED)) == 0) | |
1da177e4 LT |
3915 | break; |
3916 | } | |
3917 | ||
3918 | mac_status = tr32(MAC_STATUS); | |
3919 | if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { | |
3920 | current_link_up = 0; | |
3d3ebe74 MC |
3921 | if (tp->link_config.autoneg == AUTONEG_ENABLE && |
3922 | tp->serdes_counter == 0) { | |
1da177e4 LT |
3923 | tw32_f(MAC_MODE, (tp->mac_mode | |
3924 | MAC_MODE_SEND_CONFIGS)); | |
3925 | udelay(1); | |
3926 | tw32_f(MAC_MODE, tp->mac_mode); | |
3927 | } | |
3928 | } | |
3929 | ||
3930 | if (current_link_up == 1) { | |
3931 | tp->link_config.active_speed = SPEED_1000; | |
3932 | tp->link_config.active_duplex = DUPLEX_FULL; | |
3933 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
3934 | LED_CTRL_LNKLED_OVERRIDE | | |
3935 | LED_CTRL_1000MBPS_ON)); | |
3936 | } else { | |
3937 | tp->link_config.active_speed = SPEED_INVALID; | |
3938 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
3939 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
3940 | LED_CTRL_LNKLED_OVERRIDE | | |
3941 | LED_CTRL_TRAFFIC_OVERRIDE)); | |
3942 | } | |
3943 | ||
3944 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
3945 | if (current_link_up) | |
3946 | netif_carrier_on(tp->dev); | |
3947 | else | |
3948 | netif_carrier_off(tp->dev); | |
3949 | tg3_link_report(tp); | |
3950 | } else { | |
8d018621 | 3951 | u32 now_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
3952 | if (orig_pause_cfg != now_pause_cfg || |
3953 | orig_active_speed != tp->link_config.active_speed || | |
3954 | orig_active_duplex != tp->link_config.active_duplex) | |
3955 | tg3_link_report(tp); | |
3956 | } | |
3957 | ||
3958 | return 0; | |
3959 | } | |
3960 | ||
747e8f8b MC |
3961 | static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) |
3962 | { | |
3963 | int current_link_up, err = 0; | |
3964 | u32 bmsr, bmcr; | |
3965 | u16 current_speed; | |
3966 | u8 current_duplex; | |
ef167e27 | 3967 | u32 local_adv, remote_adv; |
747e8f8b MC |
3968 | |
3969 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
3970 | tw32_f(MAC_MODE, tp->mac_mode); | |
3971 | udelay(40); | |
3972 | ||
3973 | tw32(MAC_EVENT, 0); | |
3974 | ||
3975 | tw32_f(MAC_STATUS, | |
3976 | (MAC_STATUS_SYNC_CHANGED | | |
3977 | MAC_STATUS_CFG_CHANGED | | |
3978 | MAC_STATUS_MI_COMPLETION | | |
3979 | MAC_STATUS_LNKSTATE_CHANGED)); | |
3980 | udelay(40); | |
3981 | ||
3982 | if (force_reset) | |
3983 | tg3_phy_reset(tp); | |
3984 | ||
3985 | current_link_up = 0; | |
3986 | current_speed = SPEED_INVALID; | |
3987 | current_duplex = DUPLEX_INVALID; | |
3988 | ||
3989 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
3990 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
3991 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
3992 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
3993 | bmsr |= BMSR_LSTATUS; | |
3994 | else | |
3995 | bmsr &= ~BMSR_LSTATUS; | |
3996 | } | |
747e8f8b MC |
3997 | |
3998 | err |= tg3_readphy(tp, MII_BMCR, &bmcr); | |
3999 | ||
4000 | if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && | |
2bd3ed04 | 4001 | (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) { |
747e8f8b MC |
4002 | /* do nothing, just check for link up at the end */ |
4003 | } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
4004 | u32 adv, new_adv; | |
4005 | ||
4006 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4007 | new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF | | |
4008 | ADVERTISE_1000XPAUSE | | |
4009 | ADVERTISE_1000XPSE_ASYM | | |
4010 | ADVERTISE_SLCT); | |
4011 | ||
ba4d07a8 | 4012 | new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
747e8f8b MC |
4013 | |
4014 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) | |
4015 | new_adv |= ADVERTISE_1000XHALF; | |
4016 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) | |
4017 | new_adv |= ADVERTISE_1000XFULL; | |
4018 | ||
4019 | if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) { | |
4020 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
4021 | bmcr |= BMCR_ANENABLE | BMCR_ANRESTART; | |
4022 | tg3_writephy(tp, MII_BMCR, bmcr); | |
4023 | ||
4024 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3d3ebe74 | 4025 | tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; |
747e8f8b MC |
4026 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; |
4027 | ||
4028 | return err; | |
4029 | } | |
4030 | } else { | |
4031 | u32 new_bmcr; | |
4032 | ||
4033 | bmcr &= ~BMCR_SPEED1000; | |
4034 | new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX); | |
4035 | ||
4036 | if (tp->link_config.duplex == DUPLEX_FULL) | |
4037 | new_bmcr |= BMCR_FULLDPLX; | |
4038 | ||
4039 | if (new_bmcr != bmcr) { | |
4040 | /* BMCR_SPEED1000 is a reserved bit that needs | |
4041 | * to be set on write. | |
4042 | */ | |
4043 | new_bmcr |= BMCR_SPEED1000; | |
4044 | ||
4045 | /* Force a linkdown */ | |
4046 | if (netif_carrier_ok(tp->dev)) { | |
4047 | u32 adv; | |
4048 | ||
4049 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4050 | adv &= ~(ADVERTISE_1000XFULL | | |
4051 | ADVERTISE_1000XHALF | | |
4052 | ADVERTISE_SLCT); | |
4053 | tg3_writephy(tp, MII_ADVERTISE, adv); | |
4054 | tg3_writephy(tp, MII_BMCR, bmcr | | |
4055 | BMCR_ANRESTART | | |
4056 | BMCR_ANENABLE); | |
4057 | udelay(10); | |
4058 | netif_carrier_off(tp->dev); | |
4059 | } | |
4060 | tg3_writephy(tp, MII_BMCR, new_bmcr); | |
4061 | bmcr = new_bmcr; | |
4062 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4063 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
4064 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
4065 | ASIC_REV_5714) { | |
4066 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4067 | bmsr |= BMSR_LSTATUS; | |
4068 | else | |
4069 | bmsr &= ~BMSR_LSTATUS; | |
4070 | } | |
747e8f8b MC |
4071 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; |
4072 | } | |
4073 | } | |
4074 | ||
4075 | if (bmsr & BMSR_LSTATUS) { | |
4076 | current_speed = SPEED_1000; | |
4077 | current_link_up = 1; | |
4078 | if (bmcr & BMCR_FULLDPLX) | |
4079 | current_duplex = DUPLEX_FULL; | |
4080 | else | |
4081 | current_duplex = DUPLEX_HALF; | |
4082 | ||
ef167e27 MC |
4083 | local_adv = 0; |
4084 | remote_adv = 0; | |
4085 | ||
747e8f8b | 4086 | if (bmcr & BMCR_ANENABLE) { |
ef167e27 | 4087 | u32 common; |
747e8f8b MC |
4088 | |
4089 | err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); | |
4090 | err |= tg3_readphy(tp, MII_LPA, &remote_adv); | |
4091 | common = local_adv & remote_adv; | |
4092 | if (common & (ADVERTISE_1000XHALF | | |
4093 | ADVERTISE_1000XFULL)) { | |
4094 | if (common & ADVERTISE_1000XFULL) | |
4095 | current_duplex = DUPLEX_FULL; | |
4096 | else | |
4097 | current_duplex = DUPLEX_HALF; | |
747e8f8b MC |
4098 | } |
4099 | else | |
4100 | current_link_up = 0; | |
4101 | } | |
4102 | } | |
4103 | ||
ef167e27 MC |
4104 | if (current_link_up == 1 && current_duplex == DUPLEX_FULL) |
4105 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4106 | ||
747e8f8b MC |
4107 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; |
4108 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
4109 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
4110 | ||
4111 | tw32_f(MAC_MODE, tp->mac_mode); | |
4112 | udelay(40); | |
4113 | ||
4114 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4115 | ||
4116 | tp->link_config.active_speed = current_speed; | |
4117 | tp->link_config.active_duplex = current_duplex; | |
4118 | ||
4119 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4120 | if (current_link_up) | |
4121 | netif_carrier_on(tp->dev); | |
4122 | else { | |
4123 | netif_carrier_off(tp->dev); | |
4124 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
4125 | } | |
4126 | tg3_link_report(tp); | |
4127 | } | |
4128 | return err; | |
4129 | } | |
4130 | ||
4131 | static void tg3_serdes_parallel_detect(struct tg3 *tp) | |
4132 | { | |
3d3ebe74 | 4133 | if (tp->serdes_counter) { |
747e8f8b | 4134 | /* Give autoneg time to complete. */ |
3d3ebe74 | 4135 | tp->serdes_counter--; |
747e8f8b MC |
4136 | return; |
4137 | } | |
4138 | if (!netif_carrier_ok(tp->dev) && | |
4139 | (tp->link_config.autoneg == AUTONEG_ENABLE)) { | |
4140 | u32 bmcr; | |
4141 | ||
4142 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4143 | if (bmcr & BMCR_ANENABLE) { | |
4144 | u32 phy1, phy2; | |
4145 | ||
4146 | /* Select shadow register 0x1f */ | |
4147 | tg3_writephy(tp, 0x1c, 0x7c00); | |
4148 | tg3_readphy(tp, 0x1c, &phy1); | |
4149 | ||
4150 | /* Select expansion interrupt status register */ | |
4151 | tg3_writephy(tp, 0x17, 0x0f01); | |
4152 | tg3_readphy(tp, 0x15, &phy2); | |
4153 | tg3_readphy(tp, 0x15, &phy2); | |
4154 | ||
4155 | if ((phy1 & 0x10) && !(phy2 & 0x20)) { | |
4156 | /* We have signal detect and not receiving | |
4157 | * config code words, link is up by parallel | |
4158 | * detection. | |
4159 | */ | |
4160 | ||
4161 | bmcr &= ~BMCR_ANENABLE; | |
4162 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; | |
4163 | tg3_writephy(tp, MII_BMCR, bmcr); | |
4164 | tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT; | |
4165 | } | |
4166 | } | |
4167 | } | |
4168 | else if (netif_carrier_ok(tp->dev) && | |
4169 | (tp->link_config.autoneg == AUTONEG_ENABLE) && | |
4170 | (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) { | |
4171 | u32 phy2; | |
4172 | ||
4173 | /* Select expansion interrupt status register */ | |
4174 | tg3_writephy(tp, 0x17, 0x0f01); | |
4175 | tg3_readphy(tp, 0x15, &phy2); | |
4176 | if (phy2 & 0x20) { | |
4177 | u32 bmcr; | |
4178 | ||
4179 | /* Config code words received, turn on autoneg. */ | |
4180 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4181 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); | |
4182 | ||
4183 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
4184 | ||
4185 | } | |
4186 | } | |
4187 | } | |
4188 | ||
1da177e4 LT |
4189 | static int tg3_setup_phy(struct tg3 *tp, int force_reset) |
4190 | { | |
4191 | int err; | |
4192 | ||
4193 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { | |
4194 | err = tg3_setup_fiber_phy(tp, force_reset); | |
747e8f8b MC |
4195 | } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { |
4196 | err = tg3_setup_fiber_mii_phy(tp, force_reset); | |
1da177e4 LT |
4197 | } else { |
4198 | err = tg3_setup_copper_phy(tp, force_reset); | |
4199 | } | |
4200 | ||
bcb37f6c | 4201 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
aa6c91fe MC |
4202 | u32 val, scale; |
4203 | ||
4204 | val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; | |
4205 | if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5) | |
4206 | scale = 65; | |
4207 | else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25) | |
4208 | scale = 6; | |
4209 | else | |
4210 | scale = 12; | |
4211 | ||
4212 | val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; | |
4213 | val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
4214 | tw32(GRC_MISC_CFG, val); | |
4215 | } | |
4216 | ||
1da177e4 LT |
4217 | if (tp->link_config.active_speed == SPEED_1000 && |
4218 | tp->link_config.active_duplex == DUPLEX_HALF) | |
4219 | tw32(MAC_TX_LENGTHS, | |
4220 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
4221 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
4222 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
4223 | else | |
4224 | tw32(MAC_TX_LENGTHS, | |
4225 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
4226 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
4227 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
4228 | ||
4229 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
4230 | if (netif_carrier_ok(tp->dev)) { | |
4231 | tw32(HOSTCC_STAT_COAL_TICKS, | |
15f9850d | 4232 | tp->coal.stats_block_coalesce_usecs); |
1da177e4 LT |
4233 | } else { |
4234 | tw32(HOSTCC_STAT_COAL_TICKS, 0); | |
4235 | } | |
4236 | } | |
4237 | ||
8ed5d97e MC |
4238 | if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) { |
4239 | u32 val = tr32(PCIE_PWR_MGMT_THRESH); | |
4240 | if (!netif_carrier_ok(tp->dev)) | |
4241 | val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) | | |
4242 | tp->pwrmgmt_thresh; | |
4243 | else | |
4244 | val |= PCIE_PWR_MGMT_L1_THRESH_MSK; | |
4245 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
4246 | } | |
4247 | ||
1da177e4 LT |
4248 | return err; |
4249 | } | |
4250 | ||
df3e6548 MC |
4251 | /* This is called whenever we suspect that the system chipset is re- |
4252 | * ordering the sequence of MMIO to the tx send mailbox. The symptom | |
4253 | * is bogus tx completions. We try to recover by setting the | |
4254 | * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later | |
4255 | * in the workqueue. | |
4256 | */ | |
4257 | static void tg3_tx_recover(struct tg3 *tp) | |
4258 | { | |
4259 | BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) || | |
4260 | tp->write32_tx_mbox == tg3_write_indirect_mbox); | |
4261 | ||
4262 | printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-" | |
4263 | "mapped I/O cycles to the network device, attempting to " | |
4264 | "recover. Please report the problem to the driver maintainer " | |
4265 | "and include system chipset information.\n", tp->dev->name); | |
4266 | ||
4267 | spin_lock(&tp->lock); | |
df3e6548 | 4268 | tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING; |
df3e6548 MC |
4269 | spin_unlock(&tp->lock); |
4270 | } | |
4271 | ||
f3f3f27e | 4272 | static inline u32 tg3_tx_avail(struct tg3_napi *tnapi) |
1b2a7205 MC |
4273 | { |
4274 | smp_mb(); | |
f3f3f27e MC |
4275 | return tnapi->tx_pending - |
4276 | ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); | |
1b2a7205 MC |
4277 | } |
4278 | ||
1da177e4 LT |
4279 | /* Tigon3 never reports partial packet sends. So we do not |
4280 | * need special logic to handle SKBs that have not had all | |
4281 | * of their frags sent yet, like SunGEM does. | |
4282 | */ | |
17375d25 | 4283 | static void tg3_tx(struct tg3_napi *tnapi) |
1da177e4 | 4284 | { |
17375d25 | 4285 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 4286 | u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; |
f3f3f27e | 4287 | u32 sw_idx = tnapi->tx_cons; |
1da177e4 LT |
4288 | |
4289 | while (sw_idx != hw_idx) { | |
f3f3f27e | 4290 | struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx]; |
1da177e4 | 4291 | struct sk_buff *skb = ri->skb; |
df3e6548 MC |
4292 | int i, tx_bug = 0; |
4293 | ||
4294 | if (unlikely(skb == NULL)) { | |
4295 | tg3_tx_recover(tp); | |
4296 | return; | |
4297 | } | |
1da177e4 | 4298 | |
90079ce8 | 4299 | skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE); |
1da177e4 LT |
4300 | |
4301 | ri->skb = NULL; | |
4302 | ||
4303 | sw_idx = NEXT_TX(sw_idx); | |
4304 | ||
4305 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
f3f3f27e | 4306 | ri = &tnapi->tx_buffers[sw_idx]; |
df3e6548 MC |
4307 | if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) |
4308 | tx_bug = 1; | |
1da177e4 LT |
4309 | sw_idx = NEXT_TX(sw_idx); |
4310 | } | |
4311 | ||
f47c11ee | 4312 | dev_kfree_skb(skb); |
df3e6548 MC |
4313 | |
4314 | if (unlikely(tx_bug)) { | |
4315 | tg3_tx_recover(tp); | |
4316 | return; | |
4317 | } | |
1da177e4 LT |
4318 | } |
4319 | ||
f3f3f27e | 4320 | tnapi->tx_cons = sw_idx; |
1da177e4 | 4321 | |
1b2a7205 MC |
4322 | /* Need to make the tx_cons update visible to tg3_start_xmit() |
4323 | * before checking for netif_queue_stopped(). Without the | |
4324 | * memory barrier, there is a small possibility that tg3_start_xmit() | |
4325 | * will miss it and cause the queue to be stopped forever. | |
4326 | */ | |
4327 | smp_mb(); | |
4328 | ||
4329 | if (unlikely(netif_queue_stopped(tp->dev) && | |
f3f3f27e | 4330 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) { |
1b2a7205 | 4331 | netif_tx_lock(tp->dev); |
51b91468 | 4332 | if (netif_queue_stopped(tp->dev) && |
f3f3f27e | 4333 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))) |
51b91468 | 4334 | netif_wake_queue(tp->dev); |
1b2a7205 | 4335 | netif_tx_unlock(tp->dev); |
51b91468 | 4336 | } |
1da177e4 LT |
4337 | } |
4338 | ||
4339 | /* Returns size of skb allocated or < 0 on error. | |
4340 | * | |
4341 | * We only need to fill in the address because the other members | |
4342 | * of the RX descriptor are invariant, see tg3_init_rings. | |
4343 | * | |
4344 | * Note the purposeful assymetry of cpu vs. chip accesses. For | |
4345 | * posting buffers we only dirty the first cache line of the RX | |
4346 | * descriptor (containing the address). Whereas for the RX status | |
4347 | * buffers the cpu only reads the last cacheline of the RX descriptor | |
4348 | * (to fetch the error flags, vlan tag, checksum, and opaque cookie). | |
4349 | */ | |
17375d25 | 4350 | static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key, |
1da177e4 LT |
4351 | int src_idx, u32 dest_idx_unmasked) |
4352 | { | |
17375d25 | 4353 | struct tg3 *tp = tnapi->tp; |
1da177e4 LT |
4354 | struct tg3_rx_buffer_desc *desc; |
4355 | struct ring_info *map, *src_map; | |
4356 | struct sk_buff *skb; | |
4357 | dma_addr_t mapping; | |
4358 | int skb_size, dest_idx; | |
21f581a5 | 4359 | struct tg3_rx_prodring_set *tpr = &tp->prodring[0]; |
1da177e4 LT |
4360 | |
4361 | src_map = NULL; | |
4362 | switch (opaque_key) { | |
4363 | case RXD_OPAQUE_RING_STD: | |
4364 | dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE; | |
21f581a5 MC |
4365 | desc = &tpr->rx_std[dest_idx]; |
4366 | map = &tpr->rx_std_buffers[dest_idx]; | |
1da177e4 | 4367 | if (src_idx >= 0) |
21f581a5 | 4368 | src_map = &tpr->rx_std_buffers[src_idx]; |
287be12e | 4369 | skb_size = tp->rx_pkt_map_sz; |
1da177e4 LT |
4370 | break; |
4371 | ||
4372 | case RXD_OPAQUE_RING_JUMBO: | |
4373 | dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE; | |
79ed5ac7 | 4374 | desc = &tpr->rx_jmb[dest_idx].std; |
21f581a5 | 4375 | map = &tpr->rx_jmb_buffers[dest_idx]; |
1da177e4 | 4376 | if (src_idx >= 0) |
21f581a5 | 4377 | src_map = &tpr->rx_jmb_buffers[src_idx]; |
287be12e | 4378 | skb_size = TG3_RX_JMB_MAP_SZ; |
1da177e4 LT |
4379 | break; |
4380 | ||
4381 | default: | |
4382 | return -EINVAL; | |
855e1111 | 4383 | } |
1da177e4 LT |
4384 | |
4385 | /* Do not overwrite any of the map or rp information | |
4386 | * until we are sure we can commit to a new buffer. | |
4387 | * | |
4388 | * Callers depend upon this behavior and assume that | |
4389 | * we leave everything unchanged if we fail. | |
4390 | */ | |
287be12e | 4391 | skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset); |
1da177e4 LT |
4392 | if (skb == NULL) |
4393 | return -ENOMEM; | |
4394 | ||
1da177e4 LT |
4395 | skb_reserve(skb, tp->rx_offset); |
4396 | ||
287be12e | 4397 | mapping = pci_map_single(tp->pdev, skb->data, skb_size, |
1da177e4 LT |
4398 | PCI_DMA_FROMDEVICE); |
4399 | ||
4400 | map->skb = skb; | |
4401 | pci_unmap_addr_set(map, mapping, mapping); | |
4402 | ||
4403 | if (src_map != NULL) | |
4404 | src_map->skb = NULL; | |
4405 | ||
4406 | desc->addr_hi = ((u64)mapping >> 32); | |
4407 | desc->addr_lo = ((u64)mapping & 0xffffffff); | |
4408 | ||
4409 | return skb_size; | |
4410 | } | |
4411 | ||
4412 | /* We only need to move over in the address because the other | |
4413 | * members of the RX descriptor are invariant. See notes above | |
4414 | * tg3_alloc_rx_skb for full details. | |
4415 | */ | |
17375d25 | 4416 | static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key, |
1da177e4 LT |
4417 | int src_idx, u32 dest_idx_unmasked) |
4418 | { | |
17375d25 | 4419 | struct tg3 *tp = tnapi->tp; |
1da177e4 LT |
4420 | struct tg3_rx_buffer_desc *src_desc, *dest_desc; |
4421 | struct ring_info *src_map, *dest_map; | |
4422 | int dest_idx; | |
21f581a5 | 4423 | struct tg3_rx_prodring_set *tpr = &tp->prodring[0]; |
1da177e4 LT |
4424 | |
4425 | switch (opaque_key) { | |
4426 | case RXD_OPAQUE_RING_STD: | |
4427 | dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE; | |
21f581a5 MC |
4428 | dest_desc = &tpr->rx_std[dest_idx]; |
4429 | dest_map = &tpr->rx_std_buffers[dest_idx]; | |
4430 | src_desc = &tpr->rx_std[src_idx]; | |
4431 | src_map = &tpr->rx_std_buffers[src_idx]; | |
1da177e4 LT |
4432 | break; |
4433 | ||
4434 | case RXD_OPAQUE_RING_JUMBO: | |
4435 | dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE; | |
79ed5ac7 | 4436 | dest_desc = &tpr->rx_jmb[dest_idx].std; |
21f581a5 | 4437 | dest_map = &tpr->rx_jmb_buffers[dest_idx]; |
79ed5ac7 | 4438 | src_desc = &tpr->rx_jmb[src_idx].std; |
21f581a5 | 4439 | src_map = &tpr->rx_jmb_buffers[src_idx]; |
1da177e4 LT |
4440 | break; |
4441 | ||
4442 | default: | |
4443 | return; | |
855e1111 | 4444 | } |
1da177e4 LT |
4445 | |
4446 | dest_map->skb = src_map->skb; | |
4447 | pci_unmap_addr_set(dest_map, mapping, | |
4448 | pci_unmap_addr(src_map, mapping)); | |
4449 | dest_desc->addr_hi = src_desc->addr_hi; | |
4450 | dest_desc->addr_lo = src_desc->addr_lo; | |
4451 | ||
4452 | src_map->skb = NULL; | |
4453 | } | |
4454 | ||
1da177e4 LT |
4455 | /* The RX ring scheme is composed of multiple rings which post fresh |
4456 | * buffers to the chip, and one special ring the chip uses to report | |
4457 | * status back to the host. | |
4458 | * | |
4459 | * The special ring reports the status of received packets to the | |
4460 | * host. The chip does not write into the original descriptor the | |
4461 | * RX buffer was obtained from. The chip simply takes the original | |
4462 | * descriptor as provided by the host, updates the status and length | |
4463 | * field, then writes this into the next status ring entry. | |
4464 | * | |
4465 | * Each ring the host uses to post buffers to the chip is described | |
4466 | * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives, | |
4467 | * it is first placed into the on-chip ram. When the packet's length | |
4468 | * is known, it walks down the TG3_BDINFO entries to select the ring. | |
4469 | * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO | |
4470 | * which is within the range of the new packet's length is chosen. | |
4471 | * | |
4472 | * The "separate ring for rx status" scheme may sound queer, but it makes | |
4473 | * sense from a cache coherency perspective. If only the host writes | |
4474 | * to the buffer post rings, and only the chip writes to the rx status | |
4475 | * rings, then cache lines never move beyond shared-modified state. | |
4476 | * If both the host and chip were to write into the same ring, cache line | |
4477 | * eviction could occur since both entities want it in an exclusive state. | |
4478 | */ | |
17375d25 | 4479 | static int tg3_rx(struct tg3_napi *tnapi, int budget) |
1da177e4 | 4480 | { |
17375d25 | 4481 | struct tg3 *tp = tnapi->tp; |
f92905de | 4482 | u32 work_mask, rx_std_posted = 0; |
72334482 | 4483 | u32 sw_idx = tnapi->rx_rcb_ptr; |
483ba50b | 4484 | u16 hw_idx; |
1da177e4 | 4485 | int received; |
21f581a5 | 4486 | struct tg3_rx_prodring_set *tpr = &tp->prodring[0]; |
1da177e4 | 4487 | |
898a56f8 | 4488 | hw_idx = tnapi->hw_status->idx[0].rx_producer; |
1da177e4 LT |
4489 | /* |
4490 | * We need to order the read of hw_idx and the read of | |
4491 | * the opaque cookie. | |
4492 | */ | |
4493 | rmb(); | |
1da177e4 LT |
4494 | work_mask = 0; |
4495 | received = 0; | |
4496 | while (sw_idx != hw_idx && budget > 0) { | |
72334482 | 4497 | struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; |
1da177e4 LT |
4498 | unsigned int len; |
4499 | struct sk_buff *skb; | |
4500 | dma_addr_t dma_addr; | |
4501 | u32 opaque_key, desc_idx, *post_ptr; | |
4502 | ||
4503 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
4504 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
4505 | if (opaque_key == RXD_OPAQUE_RING_STD) { | |
21f581a5 MC |
4506 | struct ring_info *ri = &tpr->rx_std_buffers[desc_idx]; |
4507 | dma_addr = pci_unmap_addr(ri, mapping); | |
4508 | skb = ri->skb; | |
4509 | post_ptr = &tpr->rx_std_ptr; | |
f92905de | 4510 | rx_std_posted++; |
1da177e4 | 4511 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { |
21f581a5 MC |
4512 | struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx]; |
4513 | dma_addr = pci_unmap_addr(ri, mapping); | |
4514 | skb = ri->skb; | |
4515 | post_ptr = &tpr->rx_jmb_ptr; | |
4516 | } else | |
1da177e4 | 4517 | goto next_pkt_nopost; |
1da177e4 LT |
4518 | |
4519 | work_mask |= opaque_key; | |
4520 | ||
4521 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
4522 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) { | |
4523 | drop_it: | |
17375d25 | 4524 | tg3_recycle_rx(tnapi, opaque_key, |
1da177e4 LT |
4525 | desc_idx, *post_ptr); |
4526 | drop_it_no_recycle: | |
4527 | /* Other statistics kept track of by card. */ | |
4528 | tp->net_stats.rx_dropped++; | |
4529 | goto next_pkt; | |
4530 | } | |
4531 | ||
ad829268 MC |
4532 | len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - |
4533 | ETH_FCS_LEN; | |
1da177e4 | 4534 | |
6aa20a22 | 4535 | if (len > RX_COPY_THRESHOLD |
ad829268 MC |
4536 | && tp->rx_offset == NET_IP_ALIGN |
4537 | /* rx_offset will likely not equal NET_IP_ALIGN | |
4538 | * if this is a 5701 card running in PCI-X mode | |
4539 | * [see tg3_get_invariants()] | |
4540 | */ | |
1da177e4 LT |
4541 | ) { |
4542 | int skb_size; | |
4543 | ||
17375d25 | 4544 | skb_size = tg3_alloc_rx_skb(tnapi, opaque_key, |
1da177e4 LT |
4545 | desc_idx, *post_ptr); |
4546 | if (skb_size < 0) | |
4547 | goto drop_it; | |
4548 | ||
287be12e | 4549 | pci_unmap_single(tp->pdev, dma_addr, skb_size, |
1da177e4 LT |
4550 | PCI_DMA_FROMDEVICE); |
4551 | ||
4552 | skb_put(skb, len); | |
4553 | } else { | |
4554 | struct sk_buff *copy_skb; | |
4555 | ||
17375d25 | 4556 | tg3_recycle_rx(tnapi, opaque_key, |
1da177e4 LT |
4557 | desc_idx, *post_ptr); |
4558 | ||
ad829268 MC |
4559 | copy_skb = netdev_alloc_skb(tp->dev, |
4560 | len + TG3_RAW_IP_ALIGN); | |
1da177e4 LT |
4561 | if (copy_skb == NULL) |
4562 | goto drop_it_no_recycle; | |
4563 | ||
ad829268 | 4564 | skb_reserve(copy_skb, TG3_RAW_IP_ALIGN); |
1da177e4 LT |
4565 | skb_put(copy_skb, len); |
4566 | pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); | |
d626f62b | 4567 | skb_copy_from_linear_data(skb, copy_skb->data, len); |
1da177e4 LT |
4568 | pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); |
4569 | ||
4570 | /* We'll reuse the original ring buffer. */ | |
4571 | skb = copy_skb; | |
4572 | } | |
4573 | ||
4574 | if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) && | |
4575 | (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && | |
4576 | (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
4577 | >> RXD_TCPCSUM_SHIFT) == 0xffff)) | |
4578 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
4579 | else | |
4580 | skb->ip_summed = CHECKSUM_NONE; | |
4581 | ||
4582 | skb->protocol = eth_type_trans(skb, tp->dev); | |
f7b493e0 MC |
4583 | |
4584 | if (len > (tp->dev->mtu + ETH_HLEN) && | |
4585 | skb->protocol != htons(ETH_P_8021Q)) { | |
4586 | dev_kfree_skb(skb); | |
4587 | goto next_pkt; | |
4588 | } | |
4589 | ||
1da177e4 LT |
4590 | #if TG3_VLAN_TAG_USED |
4591 | if (tp->vlgrp != NULL && | |
4592 | desc->type_flags & RXD_FLAG_VLAN) { | |
17375d25 | 4593 | vlan_gro_receive(&tnapi->napi, tp->vlgrp, |
8ef0442f | 4594 | desc->err_vlan & RXD_VLAN_MASK, skb); |
1da177e4 LT |
4595 | } else |
4596 | #endif | |
17375d25 | 4597 | napi_gro_receive(&tnapi->napi, skb); |
1da177e4 | 4598 | |
1da177e4 LT |
4599 | received++; |
4600 | budget--; | |
4601 | ||
4602 | next_pkt: | |
4603 | (*post_ptr)++; | |
f92905de MC |
4604 | |
4605 | if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { | |
4606 | u32 idx = *post_ptr % TG3_RX_RING_SIZE; | |
4607 | ||
4608 | tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + | |
4609 | TG3_64BIT_REG_LOW, idx); | |
4610 | work_mask &= ~RXD_OPAQUE_RING_STD; | |
4611 | rx_std_posted = 0; | |
4612 | } | |
1da177e4 | 4613 | next_pkt_nopost: |
483ba50b | 4614 | sw_idx++; |
6b31a515 | 4615 | sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1); |
52f6d697 MC |
4616 | |
4617 | /* Refresh hw_idx to see if there is new work */ | |
4618 | if (sw_idx == hw_idx) { | |
898a56f8 | 4619 | hw_idx = tnapi->hw_status->idx[0].rx_producer; |
52f6d697 MC |
4620 | rmb(); |
4621 | } | |
1da177e4 LT |
4622 | } |
4623 | ||
4624 | /* ACK the status ring. */ | |
72334482 MC |
4625 | tnapi->rx_rcb_ptr = sw_idx; |
4626 | tw32_rx_mbox(tnapi->consmbox, sw_idx); | |
1da177e4 LT |
4627 | |
4628 | /* Refill RX ring(s). */ | |
4629 | if (work_mask & RXD_OPAQUE_RING_STD) { | |
21f581a5 | 4630 | sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE; |
1da177e4 LT |
4631 | tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW, |
4632 | sw_idx); | |
4633 | } | |
4634 | if (work_mask & RXD_OPAQUE_RING_JUMBO) { | |
21f581a5 | 4635 | sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE; |
1da177e4 LT |
4636 | tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW, |
4637 | sw_idx); | |
4638 | } | |
4639 | mmiowb(); | |
4640 | ||
4641 | return received; | |
4642 | } | |
4643 | ||
17375d25 | 4644 | static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget) |
1da177e4 | 4645 | { |
17375d25 | 4646 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 4647 | struct tg3_hw_status *sblk = tnapi->hw_status; |
1da177e4 | 4648 | |
1da177e4 LT |
4649 | /* handle link change and other phy events */ |
4650 | if (!(tp->tg3_flags & | |
4651 | (TG3_FLAG_USE_LINKCHG_REG | | |
4652 | TG3_FLAG_POLL_SERDES))) { | |
4653 | if (sblk->status & SD_STATUS_LINK_CHG) { | |
4654 | sblk->status = SD_STATUS_UPDATED | | |
4655 | (sblk->status & ~SD_STATUS_LINK_CHG); | |
f47c11ee | 4656 | spin_lock(&tp->lock); |
dd477003 MC |
4657 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
4658 | tw32_f(MAC_STATUS, | |
4659 | (MAC_STATUS_SYNC_CHANGED | | |
4660 | MAC_STATUS_CFG_CHANGED | | |
4661 | MAC_STATUS_MI_COMPLETION | | |
4662 | MAC_STATUS_LNKSTATE_CHANGED)); | |
4663 | udelay(40); | |
4664 | } else | |
4665 | tg3_setup_phy(tp, 0); | |
f47c11ee | 4666 | spin_unlock(&tp->lock); |
1da177e4 LT |
4667 | } |
4668 | } | |
4669 | ||
4670 | /* run TX completion thread */ | |
f3f3f27e | 4671 | if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { |
17375d25 | 4672 | tg3_tx(tnapi); |
6f535763 | 4673 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) |
4fd7ab59 | 4674 | return work_done; |
1da177e4 LT |
4675 | } |
4676 | ||
1da177e4 LT |
4677 | /* run RX thread, within the bounds set by NAPI. |
4678 | * All RX "locking" is done by ensuring outside | |
bea3348e | 4679 | * code synchronizes with tg3->napi.poll() |
1da177e4 | 4680 | */ |
72334482 | 4681 | if (sblk->idx[0].rx_producer != tnapi->rx_rcb_ptr) |
17375d25 | 4682 | work_done += tg3_rx(tnapi, budget - work_done); |
1da177e4 | 4683 | |
6f535763 DM |
4684 | return work_done; |
4685 | } | |
4686 | ||
4687 | static int tg3_poll(struct napi_struct *napi, int budget) | |
4688 | { | |
8ef0442f MC |
4689 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); |
4690 | struct tg3 *tp = tnapi->tp; | |
6f535763 | 4691 | int work_done = 0; |
898a56f8 | 4692 | struct tg3_hw_status *sblk = tnapi->hw_status; |
6f535763 DM |
4693 | |
4694 | while (1) { | |
17375d25 | 4695 | work_done = tg3_poll_work(tnapi, work_done, budget); |
6f535763 DM |
4696 | |
4697 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) | |
4698 | goto tx_recovery; | |
4699 | ||
4700 | if (unlikely(work_done >= budget)) | |
4701 | break; | |
4702 | ||
4fd7ab59 | 4703 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) { |
17375d25 | 4704 | /* tp->last_tag is used in tg3_int_reenable() below |
4fd7ab59 MC |
4705 | * to tell the hw how much work has been processed, |
4706 | * so we must read it before checking for more work. | |
4707 | */ | |
898a56f8 MC |
4708 | tnapi->last_tag = sblk->status_tag; |
4709 | tnapi->last_irq_tag = tnapi->last_tag; | |
4fd7ab59 MC |
4710 | rmb(); |
4711 | } else | |
4712 | sblk->status &= ~SD_STATUS_UPDATED; | |
6f535763 | 4713 | |
17375d25 | 4714 | if (likely(!tg3_has_work(tnapi))) { |
288379f0 | 4715 | napi_complete(napi); |
17375d25 | 4716 | tg3_int_reenable(tnapi); |
6f535763 DM |
4717 | break; |
4718 | } | |
1da177e4 LT |
4719 | } |
4720 | ||
bea3348e | 4721 | return work_done; |
6f535763 DM |
4722 | |
4723 | tx_recovery: | |
4fd7ab59 | 4724 | /* work_done is guaranteed to be less than budget. */ |
288379f0 | 4725 | napi_complete(napi); |
6f535763 | 4726 | schedule_work(&tp->reset_task); |
4fd7ab59 | 4727 | return work_done; |
1da177e4 LT |
4728 | } |
4729 | ||
f47c11ee DM |
4730 | static void tg3_irq_quiesce(struct tg3 *tp) |
4731 | { | |
4732 | BUG_ON(tp->irq_sync); | |
4733 | ||
4734 | tp->irq_sync = 1; | |
4735 | smp_mb(); | |
4736 | ||
4737 | synchronize_irq(tp->pdev->irq); | |
4738 | } | |
4739 | ||
4740 | static inline int tg3_irq_sync(struct tg3 *tp) | |
4741 | { | |
4742 | return tp->irq_sync; | |
4743 | } | |
4744 | ||
4745 | /* Fully shutdown all tg3 driver activity elsewhere in the system. | |
4746 | * If irq_sync is non-zero, then the IRQ handler must be synchronized | |
4747 | * with as well. Most of the time, this is not necessary except when | |
4748 | * shutting down the device. | |
4749 | */ | |
4750 | static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) | |
4751 | { | |
46966545 | 4752 | spin_lock_bh(&tp->lock); |
f47c11ee DM |
4753 | if (irq_sync) |
4754 | tg3_irq_quiesce(tp); | |
f47c11ee DM |
4755 | } |
4756 | ||
4757 | static inline void tg3_full_unlock(struct tg3 *tp) | |
4758 | { | |
f47c11ee DM |
4759 | spin_unlock_bh(&tp->lock); |
4760 | } | |
4761 | ||
fcfa0a32 MC |
4762 | /* One-shot MSI handler - Chip automatically disables interrupt |
4763 | * after sending MSI so driver doesn't have to do it. | |
4764 | */ | |
7d12e780 | 4765 | static irqreturn_t tg3_msi_1shot(int irq, void *dev_id) |
fcfa0a32 | 4766 | { |
09943a18 MC |
4767 | struct tg3_napi *tnapi = dev_id; |
4768 | struct tg3 *tp = tnapi->tp; | |
fcfa0a32 | 4769 | |
898a56f8 | 4770 | prefetch(tnapi->hw_status); |
72334482 | 4771 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
fcfa0a32 MC |
4772 | |
4773 | if (likely(!tg3_irq_sync(tp))) | |
09943a18 | 4774 | napi_schedule(&tnapi->napi); |
fcfa0a32 MC |
4775 | |
4776 | return IRQ_HANDLED; | |
4777 | } | |
4778 | ||
88b06bc2 MC |
4779 | /* MSI ISR - No need to check for interrupt sharing and no need to |
4780 | * flush status block and interrupt mailbox. PCI ordering rules | |
4781 | * guarantee that MSI will arrive after the status block. | |
4782 | */ | |
7d12e780 | 4783 | static irqreturn_t tg3_msi(int irq, void *dev_id) |
88b06bc2 | 4784 | { |
09943a18 MC |
4785 | struct tg3_napi *tnapi = dev_id; |
4786 | struct tg3 *tp = tnapi->tp; | |
88b06bc2 | 4787 | |
898a56f8 | 4788 | prefetch(tnapi->hw_status); |
72334482 | 4789 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
88b06bc2 | 4790 | /* |
fac9b83e | 4791 | * Writing any value to intr-mbox-0 clears PCI INTA# and |
88b06bc2 | 4792 | * chip-internal interrupt pending events. |
fac9b83e | 4793 | * Writing non-zero to intr-mbox-0 additional tells the |
88b06bc2 MC |
4794 | * NIC to stop sending us irqs, engaging "in-intr-handler" |
4795 | * event coalescing. | |
4796 | */ | |
4797 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); | |
61487480 | 4798 | if (likely(!tg3_irq_sync(tp))) |
09943a18 | 4799 | napi_schedule(&tnapi->napi); |
61487480 | 4800 | |
88b06bc2 MC |
4801 | return IRQ_RETVAL(1); |
4802 | } | |
4803 | ||
7d12e780 | 4804 | static irqreturn_t tg3_interrupt(int irq, void *dev_id) |
1da177e4 | 4805 | { |
09943a18 MC |
4806 | struct tg3_napi *tnapi = dev_id; |
4807 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 4808 | struct tg3_hw_status *sblk = tnapi->hw_status; |
1da177e4 LT |
4809 | unsigned int handled = 1; |
4810 | ||
1da177e4 LT |
4811 | /* In INTx mode, it is possible for the interrupt to arrive at |
4812 | * the CPU before the status block posted prior to the interrupt. | |
4813 | * Reading the PCI State register will confirm whether the | |
4814 | * interrupt is ours and will flush the status block. | |
4815 | */ | |
d18edcb2 MC |
4816 | if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { |
4817 | if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) || | |
4818 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
4819 | handled = 0; | |
f47c11ee | 4820 | goto out; |
fac9b83e | 4821 | } |
d18edcb2 MC |
4822 | } |
4823 | ||
4824 | /* | |
4825 | * Writing any value to intr-mbox-0 clears PCI INTA# and | |
4826 | * chip-internal interrupt pending events. | |
4827 | * Writing non-zero to intr-mbox-0 additional tells the | |
4828 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
4829 | * event coalescing. | |
c04cb347 MC |
4830 | * |
4831 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
4832 | * spurious interrupts. The flush impacts performance but | |
4833 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 4834 | */ |
c04cb347 | 4835 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
d18edcb2 MC |
4836 | if (tg3_irq_sync(tp)) |
4837 | goto out; | |
4838 | sblk->status &= ~SD_STATUS_UPDATED; | |
17375d25 | 4839 | if (likely(tg3_has_work(tnapi))) { |
72334482 | 4840 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
09943a18 | 4841 | napi_schedule(&tnapi->napi); |
d18edcb2 MC |
4842 | } else { |
4843 | /* No work, shared interrupt perhaps? re-enable | |
4844 | * interrupts, and flush that PCI write | |
4845 | */ | |
4846 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | |
4847 | 0x00000000); | |
fac9b83e | 4848 | } |
f47c11ee | 4849 | out: |
fac9b83e DM |
4850 | return IRQ_RETVAL(handled); |
4851 | } | |
4852 | ||
7d12e780 | 4853 | static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) |
fac9b83e | 4854 | { |
09943a18 MC |
4855 | struct tg3_napi *tnapi = dev_id; |
4856 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 4857 | struct tg3_hw_status *sblk = tnapi->hw_status; |
fac9b83e DM |
4858 | unsigned int handled = 1; |
4859 | ||
fac9b83e DM |
4860 | /* In INTx mode, it is possible for the interrupt to arrive at |
4861 | * the CPU before the status block posted prior to the interrupt. | |
4862 | * Reading the PCI State register will confirm whether the | |
4863 | * interrupt is ours and will flush the status block. | |
4864 | */ | |
898a56f8 | 4865 | if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { |
d18edcb2 MC |
4866 | if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) || |
4867 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
4868 | handled = 0; | |
f47c11ee | 4869 | goto out; |
1da177e4 | 4870 | } |
d18edcb2 MC |
4871 | } |
4872 | ||
4873 | /* | |
4874 | * writing any value to intr-mbox-0 clears PCI INTA# and | |
4875 | * chip-internal interrupt pending events. | |
4876 | * writing non-zero to intr-mbox-0 additional tells the | |
4877 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
4878 | * event coalescing. | |
c04cb347 MC |
4879 | * |
4880 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
4881 | * spurious interrupts. The flush impacts performance but | |
4882 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 4883 | */ |
c04cb347 | 4884 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
624f8e50 MC |
4885 | |
4886 | /* | |
4887 | * In a shared interrupt configuration, sometimes other devices' | |
4888 | * interrupts will scream. We record the current status tag here | |
4889 | * so that the above check can report that the screaming interrupts | |
4890 | * are unhandled. Eventually they will be silenced. | |
4891 | */ | |
898a56f8 | 4892 | tnapi->last_irq_tag = sblk->status_tag; |
624f8e50 | 4893 | |
d18edcb2 MC |
4894 | if (tg3_irq_sync(tp)) |
4895 | goto out; | |
624f8e50 | 4896 | |
72334482 | 4897 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
624f8e50 | 4898 | |
09943a18 | 4899 | napi_schedule(&tnapi->napi); |
624f8e50 | 4900 | |
f47c11ee | 4901 | out: |
1da177e4 LT |
4902 | return IRQ_RETVAL(handled); |
4903 | } | |
4904 | ||
7938109f | 4905 | /* ISR for interrupt test */ |
7d12e780 | 4906 | static irqreturn_t tg3_test_isr(int irq, void *dev_id) |
7938109f | 4907 | { |
09943a18 MC |
4908 | struct tg3_napi *tnapi = dev_id; |
4909 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 4910 | struct tg3_hw_status *sblk = tnapi->hw_status; |
7938109f | 4911 | |
f9804ddb MC |
4912 | if ((sblk->status & SD_STATUS_UPDATED) || |
4913 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
b16250e3 | 4914 | tg3_disable_ints(tp); |
7938109f MC |
4915 | return IRQ_RETVAL(1); |
4916 | } | |
4917 | return IRQ_RETVAL(0); | |
4918 | } | |
4919 | ||
8e7a22e3 | 4920 | static int tg3_init_hw(struct tg3 *, int); |
944d980e | 4921 | static int tg3_halt(struct tg3 *, int, int); |
1da177e4 | 4922 | |
b9ec6c1b MC |
4923 | /* Restart hardware after configuration changes, self-test, etc. |
4924 | * Invoked with tp->lock held. | |
4925 | */ | |
4926 | static int tg3_restart_hw(struct tg3 *tp, int reset_phy) | |
78c6146f ED |
4927 | __releases(tp->lock) |
4928 | __acquires(tp->lock) | |
b9ec6c1b MC |
4929 | { |
4930 | int err; | |
4931 | ||
4932 | err = tg3_init_hw(tp, reset_phy); | |
4933 | if (err) { | |
4934 | printk(KERN_ERR PFX "%s: Failed to re-initialize device, " | |
4935 | "aborting.\n", tp->dev->name); | |
4936 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
4937 | tg3_full_unlock(tp); | |
4938 | del_timer_sync(&tp->timer); | |
4939 | tp->irq_sync = 0; | |
8ef0442f | 4940 | napi_enable(&tp->napi[0].napi); |
b9ec6c1b MC |
4941 | dev_close(tp->dev); |
4942 | tg3_full_lock(tp, 0); | |
4943 | } | |
4944 | return err; | |
4945 | } | |
4946 | ||
1da177e4 LT |
4947 | #ifdef CONFIG_NET_POLL_CONTROLLER |
4948 | static void tg3_poll_controller(struct net_device *dev) | |
4949 | { | |
88b06bc2 MC |
4950 | struct tg3 *tp = netdev_priv(dev); |
4951 | ||
7d12e780 | 4952 | tg3_interrupt(tp->pdev->irq, dev); |
1da177e4 LT |
4953 | } |
4954 | #endif | |
4955 | ||
c4028958 | 4956 | static void tg3_reset_task(struct work_struct *work) |
1da177e4 | 4957 | { |
c4028958 | 4958 | struct tg3 *tp = container_of(work, struct tg3, reset_task); |
b02fd9e3 | 4959 | int err; |
1da177e4 LT |
4960 | unsigned int restart_timer; |
4961 | ||
7faa006f | 4962 | tg3_full_lock(tp, 0); |
7faa006f MC |
4963 | |
4964 | if (!netif_running(tp->dev)) { | |
7faa006f MC |
4965 | tg3_full_unlock(tp); |
4966 | return; | |
4967 | } | |
4968 | ||
4969 | tg3_full_unlock(tp); | |
4970 | ||
b02fd9e3 MC |
4971 | tg3_phy_stop(tp); |
4972 | ||
1da177e4 LT |
4973 | tg3_netif_stop(tp); |
4974 | ||
f47c11ee | 4975 | tg3_full_lock(tp, 1); |
1da177e4 LT |
4976 | |
4977 | restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER; | |
4978 | tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER; | |
4979 | ||
df3e6548 MC |
4980 | if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) { |
4981 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | |
4982 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
4983 | tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; | |
4984 | tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING; | |
4985 | } | |
4986 | ||
944d980e | 4987 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); |
b02fd9e3 MC |
4988 | err = tg3_init_hw(tp, 1); |
4989 | if (err) | |
b9ec6c1b | 4990 | goto out; |
1da177e4 LT |
4991 | |
4992 | tg3_netif_start(tp); | |
4993 | ||
1da177e4 LT |
4994 | if (restart_timer) |
4995 | mod_timer(&tp->timer, jiffies + 1); | |
7faa006f | 4996 | |
b9ec6c1b | 4997 | out: |
7faa006f | 4998 | tg3_full_unlock(tp); |
b02fd9e3 MC |
4999 | |
5000 | if (!err) | |
5001 | tg3_phy_start(tp); | |
1da177e4 LT |
5002 | } |
5003 | ||
b0408751 MC |
5004 | static void tg3_dump_short_state(struct tg3 *tp) |
5005 | { | |
5006 | printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n", | |
5007 | tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS)); | |
5008 | printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n", | |
5009 | tr32(RDMAC_STATUS), tr32(WDMAC_STATUS)); | |
5010 | } | |
5011 | ||
1da177e4 LT |
5012 | static void tg3_tx_timeout(struct net_device *dev) |
5013 | { | |
5014 | struct tg3 *tp = netdev_priv(dev); | |
5015 | ||
b0408751 | 5016 | if (netif_msg_tx_err(tp)) { |
9f88f29f MC |
5017 | printk(KERN_ERR PFX "%s: transmit timed out, resetting\n", |
5018 | dev->name); | |
b0408751 MC |
5019 | tg3_dump_short_state(tp); |
5020 | } | |
1da177e4 LT |
5021 | |
5022 | schedule_work(&tp->reset_task); | |
5023 | } | |
5024 | ||
c58ec932 MC |
5025 | /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */ |
5026 | static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len) | |
5027 | { | |
5028 | u32 base = (u32) mapping & 0xffffffff; | |
5029 | ||
5030 | return ((base > 0xffffdcc0) && | |
5031 | (base + len + 8 < base)); | |
5032 | } | |
5033 | ||
72f2afb8 MC |
5034 | /* Test for DMA addresses > 40-bit */ |
5035 | static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, | |
5036 | int len) | |
5037 | { | |
5038 | #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) | |
6728a8e2 | 5039 | if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) |
50cf156a | 5040 | return (((u64) mapping + len) > DMA_BIT_MASK(40)); |
72f2afb8 MC |
5041 | return 0; |
5042 | #else | |
5043 | return 0; | |
5044 | #endif | |
5045 | } | |
5046 | ||
f3f3f27e | 5047 | static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32); |
1da177e4 | 5048 | |
72f2afb8 MC |
5049 | /* Workaround 4GB and 40-bit hardware DMA bugs. */ |
5050 | static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb, | |
c58ec932 MC |
5051 | u32 last_plus_one, u32 *start, |
5052 | u32 base_flags, u32 mss) | |
1da177e4 | 5053 | { |
f3f3f27e | 5054 | struct tg3_napi *tnapi = &tp->napi[0]; |
41588ba1 | 5055 | struct sk_buff *new_skb; |
c58ec932 | 5056 | dma_addr_t new_addr = 0; |
1da177e4 | 5057 | u32 entry = *start; |
c58ec932 | 5058 | int i, ret = 0; |
1da177e4 | 5059 | |
41588ba1 MC |
5060 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) |
5061 | new_skb = skb_copy(skb, GFP_ATOMIC); | |
5062 | else { | |
5063 | int more_headroom = 4 - ((unsigned long)skb->data & 3); | |
5064 | ||
5065 | new_skb = skb_copy_expand(skb, | |
5066 | skb_headroom(skb) + more_headroom, | |
5067 | skb_tailroom(skb), GFP_ATOMIC); | |
5068 | } | |
5069 | ||
1da177e4 | 5070 | if (!new_skb) { |
c58ec932 MC |
5071 | ret = -1; |
5072 | } else { | |
5073 | /* New SKB is guaranteed to be linear. */ | |
5074 | entry = *start; | |
90079ce8 | 5075 | ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE); |
042a53a9 | 5076 | new_addr = skb_shinfo(new_skb)->dma_head; |
90079ce8 | 5077 | |
c58ec932 MC |
5078 | /* Make sure new skb does not cross any 4G boundaries. |
5079 | * Drop the packet if it does. | |
5080 | */ | |
90079ce8 | 5081 | if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) { |
638266f7 DM |
5082 | if (!ret) |
5083 | skb_dma_unmap(&tp->pdev->dev, new_skb, | |
5084 | DMA_TO_DEVICE); | |
c58ec932 MC |
5085 | ret = -1; |
5086 | dev_kfree_skb(new_skb); | |
5087 | new_skb = NULL; | |
5088 | } else { | |
f3f3f27e | 5089 | tg3_set_txd(tnapi, entry, new_addr, new_skb->len, |
c58ec932 MC |
5090 | base_flags, 1 | (mss << 1)); |
5091 | *start = NEXT_TX(entry); | |
5092 | } | |
1da177e4 LT |
5093 | } |
5094 | ||
1da177e4 LT |
5095 | /* Now clean up the sw ring entries. */ |
5096 | i = 0; | |
5097 | while (entry != last_plus_one) { | |
f3f3f27e MC |
5098 | if (i == 0) |
5099 | tnapi->tx_buffers[entry].skb = new_skb; | |
5100 | else | |
5101 | tnapi->tx_buffers[entry].skb = NULL; | |
1da177e4 LT |
5102 | entry = NEXT_TX(entry); |
5103 | i++; | |
5104 | } | |
5105 | ||
90079ce8 | 5106 | skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE); |
1da177e4 LT |
5107 | dev_kfree_skb(skb); |
5108 | ||
c58ec932 | 5109 | return ret; |
1da177e4 LT |
5110 | } |
5111 | ||
f3f3f27e | 5112 | static void tg3_set_txd(struct tg3_napi *tnapi, int entry, |
1da177e4 LT |
5113 | dma_addr_t mapping, int len, u32 flags, |
5114 | u32 mss_and_is_end) | |
5115 | { | |
f3f3f27e | 5116 | struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry]; |
1da177e4 LT |
5117 | int is_end = (mss_and_is_end & 0x1); |
5118 | u32 mss = (mss_and_is_end >> 1); | |
5119 | u32 vlan_tag = 0; | |
5120 | ||
5121 | if (is_end) | |
5122 | flags |= TXD_FLAG_END; | |
5123 | if (flags & TXD_FLAG_VLAN) { | |
5124 | vlan_tag = flags >> 16; | |
5125 | flags &= 0xffff; | |
5126 | } | |
5127 | vlan_tag |= (mss << TXD_MSS_SHIFT); | |
5128 | ||
5129 | txd->addr_hi = ((u64) mapping >> 32); | |
5130 | txd->addr_lo = ((u64) mapping & 0xffffffff); | |
5131 | txd->len_flags = (len << TXD_LEN_SHIFT) | flags; | |
5132 | txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT; | |
5133 | } | |
5134 | ||
5a6f3074 MC |
5135 | /* hard_start_xmit for devices that don't have any bugs and |
5136 | * support TG3_FLG2_HW_TSO_2 only. | |
5137 | */ | |
1da177e4 | 5138 | static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev) |
5a6f3074 MC |
5139 | { |
5140 | struct tg3 *tp = netdev_priv(dev); | |
5a6f3074 | 5141 | u32 len, entry, base_flags, mss; |
90079ce8 DM |
5142 | struct skb_shared_info *sp; |
5143 | dma_addr_t mapping; | |
f3f3f27e | 5144 | struct tg3_napi *tnapi = &tp->napi[0]; |
5a6f3074 MC |
5145 | |
5146 | len = skb_headlen(skb); | |
5147 | ||
00b70504 | 5148 | /* We are running in BH disabled context with netif_tx_lock |
bea3348e | 5149 | * and TX reclaim runs via tp->napi.poll inside of a software |
5a6f3074 MC |
5150 | * interrupt. Furthermore, IRQ processing runs lockless so we have |
5151 | * no IRQ context deadlocks to worry about either. Rejoice! | |
5152 | */ | |
f3f3f27e | 5153 | if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) { |
5a6f3074 MC |
5154 | if (!netif_queue_stopped(dev)) { |
5155 | netif_stop_queue(dev); | |
5156 | ||
5157 | /* This is a hard error, log it. */ | |
5158 | printk(KERN_ERR PFX "%s: BUG! Tx Ring full when " | |
5159 | "queue awake!\n", dev->name); | |
5160 | } | |
5a6f3074 MC |
5161 | return NETDEV_TX_BUSY; |
5162 | } | |
5163 | ||
f3f3f27e | 5164 | entry = tnapi->tx_prod; |
5a6f3074 | 5165 | base_flags = 0; |
5a6f3074 | 5166 | mss = 0; |
c13e3713 | 5167 | if ((mss = skb_shinfo(skb)->gso_size) != 0) { |
5a6f3074 MC |
5168 | int tcp_opt_len, ip_tcp_len; |
5169 | ||
5170 | if (skb_header_cloned(skb) && | |
5171 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
5172 | dev_kfree_skb(skb); | |
5173 | goto out_unlock; | |
5174 | } | |
5175 | ||
b0026624 MC |
5176 | if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) |
5177 | mss |= (skb_headlen(skb) - ETH_HLEN) << 9; | |
5178 | else { | |
eddc9ec5 ACM |
5179 | struct iphdr *iph = ip_hdr(skb); |
5180 | ||
ab6a5bb6 | 5181 | tcp_opt_len = tcp_optlen(skb); |
c9bdd4b5 | 5182 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); |
b0026624 | 5183 | |
eddc9ec5 ACM |
5184 | iph->check = 0; |
5185 | iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len); | |
b0026624 MC |
5186 | mss |= (ip_tcp_len + tcp_opt_len) << 9; |
5187 | } | |
5a6f3074 MC |
5188 | |
5189 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | | |
5190 | TXD_FLAG_CPU_POST_DMA); | |
5191 | ||
aa8223c7 | 5192 | tcp_hdr(skb)->check = 0; |
5a6f3074 | 5193 | |
5a6f3074 | 5194 | } |
84fa7933 | 5195 | else if (skb->ip_summed == CHECKSUM_PARTIAL) |
5a6f3074 | 5196 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
5a6f3074 MC |
5197 | #if TG3_VLAN_TAG_USED |
5198 | if (tp->vlgrp != NULL && vlan_tx_tag_present(skb)) | |
5199 | base_flags |= (TXD_FLAG_VLAN | | |
5200 | (vlan_tx_tag_get(skb) << 16)); | |
5201 | #endif | |
5202 | ||
90079ce8 DM |
5203 | if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) { |
5204 | dev_kfree_skb(skb); | |
5205 | goto out_unlock; | |
5206 | } | |
5207 | ||
5208 | sp = skb_shinfo(skb); | |
5209 | ||
042a53a9 | 5210 | mapping = sp->dma_head; |
5a6f3074 | 5211 | |
f3f3f27e | 5212 | tnapi->tx_buffers[entry].skb = skb; |
5a6f3074 | 5213 | |
f3f3f27e | 5214 | tg3_set_txd(tnapi, entry, mapping, len, base_flags, |
5a6f3074 MC |
5215 | (skb_shinfo(skb)->nr_frags == 0) | (mss << 1)); |
5216 | ||
5217 | entry = NEXT_TX(entry); | |
5218 | ||
5219 | /* Now loop through additional data fragments, and queue them. */ | |
5220 | if (skb_shinfo(skb)->nr_frags > 0) { | |
5221 | unsigned int i, last; | |
5222 | ||
5223 | last = skb_shinfo(skb)->nr_frags - 1; | |
5224 | for (i = 0; i <= last; i++) { | |
5225 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5226 | ||
5227 | len = frag->size; | |
042a53a9 | 5228 | mapping = sp->dma_maps[i]; |
f3f3f27e | 5229 | tnapi->tx_buffers[entry].skb = NULL; |
5a6f3074 | 5230 | |
f3f3f27e | 5231 | tg3_set_txd(tnapi, entry, mapping, len, |
5a6f3074 MC |
5232 | base_flags, (i == last) | (mss << 1)); |
5233 | ||
5234 | entry = NEXT_TX(entry); | |
5235 | } | |
5236 | } | |
5237 | ||
5238 | /* Packets are ready, update Tx producer idx local and on card. */ | |
f3f3f27e | 5239 | tw32_tx_mbox(tnapi->prodmbox, entry); |
5a6f3074 | 5240 | |
f3f3f27e MC |
5241 | tnapi->tx_prod = entry; |
5242 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
5a6f3074 | 5243 | netif_stop_queue(dev); |
f3f3f27e | 5244 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) |
5a6f3074 MC |
5245 | netif_wake_queue(tp->dev); |
5246 | } | |
5247 | ||
5248 | out_unlock: | |
cdd0db05 | 5249 | mmiowb(); |
5a6f3074 MC |
5250 | |
5251 | return NETDEV_TX_OK; | |
5252 | } | |
5253 | ||
52c0fd83 MC |
5254 | static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *); |
5255 | ||
5256 | /* Use GSO to workaround a rare TSO bug that may be triggered when the | |
5257 | * TSO header is greater than 80 bytes. | |
5258 | */ | |
5259 | static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb) | |
5260 | { | |
5261 | struct sk_buff *segs, *nskb; | |
f3f3f27e | 5262 | u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; |
52c0fd83 MC |
5263 | |
5264 | /* Estimate the number of fragments in the worst case */ | |
f3f3f27e | 5265 | if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) { |
52c0fd83 | 5266 | netif_stop_queue(tp->dev); |
f3f3f27e | 5267 | if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est) |
7f62ad5d MC |
5268 | return NETDEV_TX_BUSY; |
5269 | ||
5270 | netif_wake_queue(tp->dev); | |
52c0fd83 MC |
5271 | } |
5272 | ||
5273 | segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO); | |
801678c5 | 5274 | if (IS_ERR(segs)) |
52c0fd83 MC |
5275 | goto tg3_tso_bug_end; |
5276 | ||
5277 | do { | |
5278 | nskb = segs; | |
5279 | segs = segs->next; | |
5280 | nskb->next = NULL; | |
5281 | tg3_start_xmit_dma_bug(nskb, tp->dev); | |
5282 | } while (segs); | |
5283 | ||
5284 | tg3_tso_bug_end: | |
5285 | dev_kfree_skb(skb); | |
5286 | ||
5287 | return NETDEV_TX_OK; | |
5288 | } | |
52c0fd83 | 5289 | |
5a6f3074 MC |
5290 | /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and |
5291 | * support TG3_FLG2_HW_TSO_1 or firmware TSO only. | |
5292 | */ | |
5293 | static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev) | |
1da177e4 LT |
5294 | { |
5295 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 | 5296 | u32 len, entry, base_flags, mss; |
90079ce8 | 5297 | struct skb_shared_info *sp; |
1da177e4 | 5298 | int would_hit_hwbug; |
90079ce8 | 5299 | dma_addr_t mapping; |
f3f3f27e | 5300 | struct tg3_napi *tnapi = &tp->napi[0]; |
1da177e4 LT |
5301 | |
5302 | len = skb_headlen(skb); | |
5303 | ||
00b70504 | 5304 | /* We are running in BH disabled context with netif_tx_lock |
bea3348e | 5305 | * and TX reclaim runs via tp->napi.poll inside of a software |
f47c11ee DM |
5306 | * interrupt. Furthermore, IRQ processing runs lockless so we have |
5307 | * no IRQ context deadlocks to worry about either. Rejoice! | |
1da177e4 | 5308 | */ |
f3f3f27e | 5309 | if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) { |
1f064a87 SH |
5310 | if (!netif_queue_stopped(dev)) { |
5311 | netif_stop_queue(dev); | |
5312 | ||
5313 | /* This is a hard error, log it. */ | |
5314 | printk(KERN_ERR PFX "%s: BUG! Tx Ring full when " | |
5315 | "queue awake!\n", dev->name); | |
5316 | } | |
1da177e4 LT |
5317 | return NETDEV_TX_BUSY; |
5318 | } | |
5319 | ||
f3f3f27e | 5320 | entry = tnapi->tx_prod; |
1da177e4 | 5321 | base_flags = 0; |
84fa7933 | 5322 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
1da177e4 | 5323 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
1da177e4 | 5324 | mss = 0; |
c13e3713 | 5325 | if ((mss = skb_shinfo(skb)->gso_size) != 0) { |
eddc9ec5 | 5326 | struct iphdr *iph; |
52c0fd83 | 5327 | int tcp_opt_len, ip_tcp_len, hdr_len; |
1da177e4 LT |
5328 | |
5329 | if (skb_header_cloned(skb) && | |
5330 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
5331 | dev_kfree_skb(skb); | |
5332 | goto out_unlock; | |
5333 | } | |
5334 | ||
ab6a5bb6 | 5335 | tcp_opt_len = tcp_optlen(skb); |
c9bdd4b5 | 5336 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); |
1da177e4 | 5337 | |
52c0fd83 MC |
5338 | hdr_len = ip_tcp_len + tcp_opt_len; |
5339 | if (unlikely((ETH_HLEN + hdr_len) > 80) && | |
7f62ad5d | 5340 | (tp->tg3_flags2 & TG3_FLG2_TSO_BUG)) |
52c0fd83 MC |
5341 | return (tg3_tso_bug(tp, skb)); |
5342 | ||
1da177e4 LT |
5343 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | |
5344 | TXD_FLAG_CPU_POST_DMA); | |
5345 | ||
eddc9ec5 ACM |
5346 | iph = ip_hdr(skb); |
5347 | iph->check = 0; | |
5348 | iph->tot_len = htons(mss + hdr_len); | |
1da177e4 | 5349 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) { |
aa8223c7 | 5350 | tcp_hdr(skb)->check = 0; |
1da177e4 | 5351 | base_flags &= ~TXD_FLAG_TCPUDP_CSUM; |
aa8223c7 ACM |
5352 | } else |
5353 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
5354 | iph->daddr, 0, | |
5355 | IPPROTO_TCP, | |
5356 | 0); | |
1da177e4 LT |
5357 | |
5358 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) || | |
5359 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) { | |
eddc9ec5 | 5360 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
5361 | int tsflags; |
5362 | ||
eddc9ec5 | 5363 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
5364 | mss |= (tsflags << 11); |
5365 | } | |
5366 | } else { | |
eddc9ec5 | 5367 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
5368 | int tsflags; |
5369 | ||
eddc9ec5 | 5370 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
5371 | base_flags |= tsflags << 12; |
5372 | } | |
5373 | } | |
5374 | } | |
1da177e4 LT |
5375 | #if TG3_VLAN_TAG_USED |
5376 | if (tp->vlgrp != NULL && vlan_tx_tag_present(skb)) | |
5377 | base_flags |= (TXD_FLAG_VLAN | | |
5378 | (vlan_tx_tag_get(skb) << 16)); | |
5379 | #endif | |
5380 | ||
90079ce8 DM |
5381 | if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) { |
5382 | dev_kfree_skb(skb); | |
5383 | goto out_unlock; | |
5384 | } | |
5385 | ||
5386 | sp = skb_shinfo(skb); | |
5387 | ||
042a53a9 | 5388 | mapping = sp->dma_head; |
1da177e4 | 5389 | |
f3f3f27e | 5390 | tnapi->tx_buffers[entry].skb = skb; |
1da177e4 LT |
5391 | |
5392 | would_hit_hwbug = 0; | |
5393 | ||
41588ba1 MC |
5394 | if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG) |
5395 | would_hit_hwbug = 1; | |
5396 | else if (tg3_4g_overflow_test(mapping, len)) | |
c58ec932 | 5397 | would_hit_hwbug = 1; |
1da177e4 | 5398 | |
f3f3f27e | 5399 | tg3_set_txd(tnapi, entry, mapping, len, base_flags, |
1da177e4 LT |
5400 | (skb_shinfo(skb)->nr_frags == 0) | (mss << 1)); |
5401 | ||
5402 | entry = NEXT_TX(entry); | |
5403 | ||
5404 | /* Now loop through additional data fragments, and queue them. */ | |
5405 | if (skb_shinfo(skb)->nr_frags > 0) { | |
5406 | unsigned int i, last; | |
5407 | ||
5408 | last = skb_shinfo(skb)->nr_frags - 1; | |
5409 | for (i = 0; i <= last; i++) { | |
5410 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5411 | ||
5412 | len = frag->size; | |
042a53a9 | 5413 | mapping = sp->dma_maps[i]; |
1da177e4 | 5414 | |
f3f3f27e | 5415 | tnapi->tx_buffers[entry].skb = NULL; |
1da177e4 | 5416 | |
c58ec932 MC |
5417 | if (tg3_4g_overflow_test(mapping, len)) |
5418 | would_hit_hwbug = 1; | |
1da177e4 | 5419 | |
72f2afb8 MC |
5420 | if (tg3_40bit_overflow_test(tp, mapping, len)) |
5421 | would_hit_hwbug = 1; | |
5422 | ||
1da177e4 | 5423 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) |
f3f3f27e | 5424 | tg3_set_txd(tnapi, entry, mapping, len, |
1da177e4 LT |
5425 | base_flags, (i == last)|(mss << 1)); |
5426 | else | |
f3f3f27e | 5427 | tg3_set_txd(tnapi, entry, mapping, len, |
1da177e4 LT |
5428 | base_flags, (i == last)); |
5429 | ||
5430 | entry = NEXT_TX(entry); | |
5431 | } | |
5432 | } | |
5433 | ||
5434 | if (would_hit_hwbug) { | |
5435 | u32 last_plus_one = entry; | |
5436 | u32 start; | |
1da177e4 | 5437 | |
c58ec932 MC |
5438 | start = entry - 1 - skb_shinfo(skb)->nr_frags; |
5439 | start &= (TG3_TX_RING_SIZE - 1); | |
1da177e4 LT |
5440 | |
5441 | /* If the workaround fails due to memory/mapping | |
5442 | * failure, silently drop this packet. | |
5443 | */ | |
72f2afb8 | 5444 | if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one, |
c58ec932 | 5445 | &start, base_flags, mss)) |
1da177e4 LT |
5446 | goto out_unlock; |
5447 | ||
5448 | entry = start; | |
5449 | } | |
5450 | ||
5451 | /* Packets are ready, update Tx producer idx local and on card. */ | |
f3f3f27e | 5452 | tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry); |
1da177e4 | 5453 | |
f3f3f27e MC |
5454 | tnapi->tx_prod = entry; |
5455 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
1da177e4 | 5456 | netif_stop_queue(dev); |
f3f3f27e | 5457 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) |
51b91468 MC |
5458 | netif_wake_queue(tp->dev); |
5459 | } | |
1da177e4 LT |
5460 | |
5461 | out_unlock: | |
cdd0db05 | 5462 | mmiowb(); |
1da177e4 LT |
5463 | |
5464 | return NETDEV_TX_OK; | |
5465 | } | |
5466 | ||
5467 | static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, | |
5468 | int new_mtu) | |
5469 | { | |
5470 | dev->mtu = new_mtu; | |
5471 | ||
ef7f5ec0 | 5472 | if (new_mtu > ETH_DATA_LEN) { |
a4e2b347 | 5473 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { |
ef7f5ec0 MC |
5474 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; |
5475 | ethtool_op_set_tso(dev, 0); | |
5476 | } | |
5477 | else | |
5478 | tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE; | |
5479 | } else { | |
a4e2b347 | 5480 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) |
ef7f5ec0 | 5481 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; |
0f893dc6 | 5482 | tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE; |
ef7f5ec0 | 5483 | } |
1da177e4 LT |
5484 | } |
5485 | ||
5486 | static int tg3_change_mtu(struct net_device *dev, int new_mtu) | |
5487 | { | |
5488 | struct tg3 *tp = netdev_priv(dev); | |
b9ec6c1b | 5489 | int err; |
1da177e4 LT |
5490 | |
5491 | if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) | |
5492 | return -EINVAL; | |
5493 | ||
5494 | if (!netif_running(dev)) { | |
5495 | /* We'll just catch it later when the | |
5496 | * device is up'd. | |
5497 | */ | |
5498 | tg3_set_mtu(dev, tp, new_mtu); | |
5499 | return 0; | |
5500 | } | |
5501 | ||
b02fd9e3 MC |
5502 | tg3_phy_stop(tp); |
5503 | ||
1da177e4 | 5504 | tg3_netif_stop(tp); |
f47c11ee DM |
5505 | |
5506 | tg3_full_lock(tp, 1); | |
1da177e4 | 5507 | |
944d980e | 5508 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
5509 | |
5510 | tg3_set_mtu(dev, tp, new_mtu); | |
5511 | ||
b9ec6c1b | 5512 | err = tg3_restart_hw(tp, 0); |
1da177e4 | 5513 | |
b9ec6c1b MC |
5514 | if (!err) |
5515 | tg3_netif_start(tp); | |
1da177e4 | 5516 | |
f47c11ee | 5517 | tg3_full_unlock(tp); |
1da177e4 | 5518 | |
b02fd9e3 MC |
5519 | if (!err) |
5520 | tg3_phy_start(tp); | |
5521 | ||
b9ec6c1b | 5522 | return err; |
1da177e4 LT |
5523 | } |
5524 | ||
21f581a5 MC |
5525 | static void tg3_rx_prodring_free(struct tg3 *tp, |
5526 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 5527 | { |
1da177e4 | 5528 | int i; |
f3f3f27e | 5529 | struct ring_info *rxp; |
1da177e4 LT |
5530 | |
5531 | for (i = 0; i < TG3_RX_RING_SIZE; i++) { | |
21f581a5 | 5532 | rxp = &tpr->rx_std_buffers[i]; |
1da177e4 LT |
5533 | |
5534 | if (rxp->skb == NULL) | |
5535 | continue; | |
1da177e4 | 5536 | |
1da177e4 LT |
5537 | pci_unmap_single(tp->pdev, |
5538 | pci_unmap_addr(rxp, mapping), | |
cf7a7298 | 5539 | tp->rx_pkt_map_sz, |
1da177e4 LT |
5540 | PCI_DMA_FROMDEVICE); |
5541 | dev_kfree_skb_any(rxp->skb); | |
5542 | rxp->skb = NULL; | |
5543 | } | |
5544 | ||
cf7a7298 MC |
5545 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { |
5546 | for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) { | |
21f581a5 | 5547 | rxp = &tpr->rx_jmb_buffers[i]; |
1da177e4 | 5548 | |
cf7a7298 MC |
5549 | if (rxp->skb == NULL) |
5550 | continue; | |
1da177e4 | 5551 | |
cf7a7298 MC |
5552 | pci_unmap_single(tp->pdev, |
5553 | pci_unmap_addr(rxp, mapping), | |
5554 | TG3_RX_JMB_MAP_SZ, | |
5555 | PCI_DMA_FROMDEVICE); | |
5556 | dev_kfree_skb_any(rxp->skb); | |
5557 | rxp->skb = NULL; | |
1da177e4 | 5558 | } |
1da177e4 LT |
5559 | } |
5560 | } | |
5561 | ||
5562 | /* Initialize tx/rx rings for packet processing. | |
5563 | * | |
5564 | * The chip has been shut down and the driver detached from | |
5565 | * the networking, so no interrupts or new tx packets will | |
5566 | * end up in the driver. tp->{tx,}lock are held and thus | |
5567 | * we may not sleep. | |
5568 | */ | |
21f581a5 MC |
5569 | static int tg3_rx_prodring_alloc(struct tg3 *tp, |
5570 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 5571 | { |
287be12e | 5572 | u32 i, rx_pkt_dma_sz; |
17375d25 | 5573 | struct tg3_napi *tnapi = &tp->napi[0]; |
1da177e4 | 5574 | |
1da177e4 | 5575 | /* Zero out all descriptors. */ |
21f581a5 | 5576 | memset(tpr->rx_std, 0, TG3_RX_RING_BYTES); |
1da177e4 | 5577 | |
287be12e | 5578 | rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ; |
a4e2b347 | 5579 | if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) && |
287be12e MC |
5580 | tp->dev->mtu > ETH_DATA_LEN) |
5581 | rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ; | |
5582 | tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); | |
7e72aad4 | 5583 | |
1da177e4 LT |
5584 | /* Initialize invariants of the rings, we only set this |
5585 | * stuff once. This works because the card does not | |
5586 | * write into the rx buffer posting rings. | |
5587 | */ | |
5588 | for (i = 0; i < TG3_RX_RING_SIZE; i++) { | |
5589 | struct tg3_rx_buffer_desc *rxd; | |
5590 | ||
21f581a5 | 5591 | rxd = &tpr->rx_std[i]; |
287be12e | 5592 | rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; |
1da177e4 LT |
5593 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); |
5594 | rxd->opaque = (RXD_OPAQUE_RING_STD | | |
5595 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
5596 | } | |
5597 | ||
1da177e4 LT |
5598 | /* Now allocate fresh SKBs for each rx ring. */ |
5599 | for (i = 0; i < tp->rx_pending; i++) { | |
17375d25 | 5600 | if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) { |
32d8c572 MC |
5601 | printk(KERN_WARNING PFX |
5602 | "%s: Using a smaller RX standard ring, " | |
5603 | "only %d out of %d buffers were allocated " | |
5604 | "successfully.\n", | |
5605 | tp->dev->name, i, tp->rx_pending); | |
5606 | if (i == 0) | |
cf7a7298 | 5607 | goto initfail; |
32d8c572 | 5608 | tp->rx_pending = i; |
1da177e4 | 5609 | break; |
32d8c572 | 5610 | } |
1da177e4 LT |
5611 | } |
5612 | ||
cf7a7298 MC |
5613 | if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)) |
5614 | goto done; | |
5615 | ||
21f581a5 | 5616 | memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES); |
cf7a7298 | 5617 | |
0f893dc6 | 5618 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) { |
cf7a7298 MC |
5619 | for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) { |
5620 | struct tg3_rx_buffer_desc *rxd; | |
5621 | ||
79ed5ac7 | 5622 | rxd = &tpr->rx_jmb[i].std; |
cf7a7298 MC |
5623 | rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; |
5624 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | | |
5625 | RXD_FLAG_JUMBO; | |
5626 | rxd->opaque = (RXD_OPAQUE_RING_JUMBO | | |
5627 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
5628 | } | |
5629 | ||
1da177e4 | 5630 | for (i = 0; i < tp->rx_jumbo_pending; i++) { |
17375d25 | 5631 | if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO, |
32d8c572 MC |
5632 | -1, i) < 0) { |
5633 | printk(KERN_WARNING PFX | |
5634 | "%s: Using a smaller RX jumbo ring, " | |
5635 | "only %d out of %d buffers were " | |
5636 | "allocated successfully.\n", | |
5637 | tp->dev->name, i, tp->rx_jumbo_pending); | |
cf7a7298 MC |
5638 | if (i == 0) |
5639 | goto initfail; | |
32d8c572 | 5640 | tp->rx_jumbo_pending = i; |
1da177e4 | 5641 | break; |
32d8c572 | 5642 | } |
1da177e4 LT |
5643 | } |
5644 | } | |
cf7a7298 MC |
5645 | |
5646 | done: | |
32d8c572 | 5647 | return 0; |
cf7a7298 MC |
5648 | |
5649 | initfail: | |
21f581a5 | 5650 | tg3_rx_prodring_free(tp, tpr); |
cf7a7298 | 5651 | return -ENOMEM; |
1da177e4 LT |
5652 | } |
5653 | ||
21f581a5 MC |
5654 | static void tg3_rx_prodring_fini(struct tg3 *tp, |
5655 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 5656 | { |
21f581a5 MC |
5657 | kfree(tpr->rx_std_buffers); |
5658 | tpr->rx_std_buffers = NULL; | |
5659 | kfree(tpr->rx_jmb_buffers); | |
5660 | tpr->rx_jmb_buffers = NULL; | |
5661 | if (tpr->rx_std) { | |
1da177e4 | 5662 | pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES, |
21f581a5 MC |
5663 | tpr->rx_std, tpr->rx_std_mapping); |
5664 | tpr->rx_std = NULL; | |
1da177e4 | 5665 | } |
21f581a5 | 5666 | if (tpr->rx_jmb) { |
1da177e4 | 5667 | pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES, |
21f581a5 MC |
5668 | tpr->rx_jmb, tpr->rx_jmb_mapping); |
5669 | tpr->rx_jmb = NULL; | |
1da177e4 | 5670 | } |
cf7a7298 MC |
5671 | } |
5672 | ||
21f581a5 MC |
5673 | static int tg3_rx_prodring_init(struct tg3 *tp, |
5674 | struct tg3_rx_prodring_set *tpr) | |
cf7a7298 | 5675 | { |
21f581a5 MC |
5676 | tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) * |
5677 | TG3_RX_RING_SIZE, GFP_KERNEL); | |
5678 | if (!tpr->rx_std_buffers) | |
cf7a7298 MC |
5679 | return -ENOMEM; |
5680 | ||
21f581a5 MC |
5681 | tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES, |
5682 | &tpr->rx_std_mapping); | |
5683 | if (!tpr->rx_std) | |
cf7a7298 MC |
5684 | goto err_out; |
5685 | ||
5686 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { | |
21f581a5 MC |
5687 | tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) * |
5688 | TG3_RX_JUMBO_RING_SIZE, | |
5689 | GFP_KERNEL); | |
5690 | if (!tpr->rx_jmb_buffers) | |
cf7a7298 MC |
5691 | goto err_out; |
5692 | ||
21f581a5 MC |
5693 | tpr->rx_jmb = pci_alloc_consistent(tp->pdev, |
5694 | TG3_RX_JUMBO_RING_BYTES, | |
5695 | &tpr->rx_jmb_mapping); | |
5696 | if (!tpr->rx_jmb) | |
cf7a7298 MC |
5697 | goto err_out; |
5698 | } | |
5699 | ||
5700 | return 0; | |
5701 | ||
5702 | err_out: | |
21f581a5 | 5703 | tg3_rx_prodring_fini(tp, tpr); |
cf7a7298 MC |
5704 | return -ENOMEM; |
5705 | } | |
5706 | ||
5707 | /* Free up pending packets in all rx/tx rings. | |
5708 | * | |
5709 | * The chip has been shut down and the driver detached from | |
5710 | * the networking, so no interrupts or new tx packets will | |
5711 | * end up in the driver. tp->{tx,}lock is not held and we are not | |
5712 | * in an interrupt context and thus may sleep. | |
5713 | */ | |
5714 | static void tg3_free_rings(struct tg3 *tp) | |
5715 | { | |
f3f3f27e | 5716 | struct tg3_napi *tnapi = &tp->napi[0]; |
cf7a7298 MC |
5717 | int i; |
5718 | ||
5719 | for (i = 0; i < TG3_TX_RING_SIZE; ) { | |
5720 | struct tx_ring_info *txp; | |
5721 | struct sk_buff *skb; | |
5722 | ||
f3f3f27e | 5723 | txp = &tnapi->tx_buffers[i]; |
cf7a7298 MC |
5724 | skb = txp->skb; |
5725 | ||
5726 | if (skb == NULL) { | |
5727 | i++; | |
5728 | continue; | |
5729 | } | |
5730 | ||
5731 | skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE); | |
5732 | ||
5733 | txp->skb = NULL; | |
5734 | ||
5735 | i += skb_shinfo(skb)->nr_frags + 1; | |
5736 | ||
5737 | dev_kfree_skb_any(skb); | |
5738 | } | |
5739 | ||
21f581a5 | 5740 | tg3_rx_prodring_free(tp, &tp->prodring[0]); |
cf7a7298 MC |
5741 | } |
5742 | ||
5743 | /* Initialize tx/rx rings for packet processing. | |
5744 | * | |
5745 | * The chip has been shut down and the driver detached from | |
5746 | * the networking, so no interrupts or new tx packets will | |
5747 | * end up in the driver. tp->{tx,}lock are held and thus | |
5748 | * we may not sleep. | |
5749 | */ | |
5750 | static int tg3_init_rings(struct tg3 *tp) | |
5751 | { | |
72334482 MC |
5752 | struct tg3_napi *tnapi = &tp->napi[0]; |
5753 | ||
cf7a7298 MC |
5754 | /* Free up all the SKBs. */ |
5755 | tg3_free_rings(tp); | |
5756 | ||
5757 | /* Zero out all descriptors. */ | |
f3f3f27e | 5758 | memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); |
cf7a7298 | 5759 | |
72334482 MC |
5760 | tnapi->rx_rcb_ptr = 0; |
5761 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | |
5762 | ||
21f581a5 | 5763 | return tg3_rx_prodring_alloc(tp, &tp->prodring[0]); |
cf7a7298 MC |
5764 | } |
5765 | ||
5766 | /* | |
5767 | * Must not be invoked with interrupt sources disabled and | |
5768 | * the hardware shutdown down. | |
5769 | */ | |
5770 | static void tg3_free_consistent(struct tg3 *tp) | |
5771 | { | |
898a56f8 MC |
5772 | struct tg3_napi *tnapi = &tp->napi[0]; |
5773 | ||
f3f3f27e MC |
5774 | kfree(tnapi->tx_buffers); |
5775 | tnapi->tx_buffers = NULL; | |
5776 | if (tnapi->tx_ring) { | |
1da177e4 | 5777 | pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES, |
f3f3f27e MC |
5778 | tnapi->tx_ring, tnapi->tx_desc_mapping); |
5779 | tnapi->tx_ring = NULL; | |
1da177e4 | 5780 | } |
72334482 MC |
5781 | if (tnapi->rx_rcb) { |
5782 | pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp), | |
5783 | tnapi->rx_rcb, tnapi->rx_rcb_mapping); | |
5784 | tnapi->rx_rcb = NULL; | |
5785 | } | |
898a56f8 | 5786 | if (tnapi->hw_status) { |
1da177e4 | 5787 | pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE, |
898a56f8 MC |
5788 | tnapi->hw_status, |
5789 | tnapi->status_mapping); | |
5790 | tnapi->hw_status = NULL; | |
1da177e4 LT |
5791 | } |
5792 | if (tp->hw_stats) { | |
5793 | pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats), | |
5794 | tp->hw_stats, tp->stats_mapping); | |
5795 | tp->hw_stats = NULL; | |
5796 | } | |
21f581a5 | 5797 | tg3_rx_prodring_fini(tp, &tp->prodring[0]); |
1da177e4 LT |
5798 | } |
5799 | ||
5800 | /* | |
5801 | * Must not be invoked with interrupt sources disabled and | |
5802 | * the hardware shutdown down. Can sleep. | |
5803 | */ | |
5804 | static int tg3_alloc_consistent(struct tg3 *tp) | |
5805 | { | |
898a56f8 MC |
5806 | struct tg3_napi *tnapi = &tp->napi[0]; |
5807 | ||
21f581a5 | 5808 | if (tg3_rx_prodring_init(tp, &tp->prodring[0])) |
1da177e4 LT |
5809 | return -ENOMEM; |
5810 | ||
f3f3f27e MC |
5811 | tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) * |
5812 | TG3_TX_RING_SIZE, GFP_KERNEL); | |
5813 | if (!tnapi->tx_buffers) | |
1da177e4 LT |
5814 | goto err_out; |
5815 | ||
f3f3f27e MC |
5816 | tnapi->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES, |
5817 | &tnapi->tx_desc_mapping); | |
5818 | if (!tnapi->tx_ring) | |
1da177e4 LT |
5819 | goto err_out; |
5820 | ||
898a56f8 MC |
5821 | tnapi->hw_status = pci_alloc_consistent(tp->pdev, |
5822 | TG3_HW_STATUS_SIZE, | |
5823 | &tnapi->status_mapping); | |
5824 | if (!tnapi->hw_status) | |
1da177e4 LT |
5825 | goto err_out; |
5826 | ||
898a56f8 MC |
5827 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); |
5828 | ||
72334482 MC |
5829 | tnapi->rx_rcb = pci_alloc_consistent(tp->pdev, |
5830 | TG3_RX_RCB_RING_BYTES(tp), | |
5831 | &tnapi->rx_rcb_mapping); | |
5832 | if (!tnapi->rx_rcb) | |
5833 | goto err_out; | |
5834 | ||
5835 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | |
5836 | ||
1da177e4 LT |
5837 | tp->hw_stats = pci_alloc_consistent(tp->pdev, |
5838 | sizeof(struct tg3_hw_stats), | |
5839 | &tp->stats_mapping); | |
5840 | if (!tp->hw_stats) | |
5841 | goto err_out; | |
5842 | ||
1da177e4 LT |
5843 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); |
5844 | ||
5845 | return 0; | |
5846 | ||
5847 | err_out: | |
5848 | tg3_free_consistent(tp); | |
5849 | return -ENOMEM; | |
5850 | } | |
5851 | ||
5852 | #define MAX_WAIT_CNT 1000 | |
5853 | ||
5854 | /* To stop a block, clear the enable bit and poll till it | |
5855 | * clears. tp->lock is held. | |
5856 | */ | |
b3b7d6be | 5857 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent) |
1da177e4 LT |
5858 | { |
5859 | unsigned int i; | |
5860 | u32 val; | |
5861 | ||
5862 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
5863 | switch (ofs) { | |
5864 | case RCVLSC_MODE: | |
5865 | case DMAC_MODE: | |
5866 | case MBFREE_MODE: | |
5867 | case BUFMGR_MODE: | |
5868 | case MEMARB_MODE: | |
5869 | /* We can't enable/disable these bits of the | |
5870 | * 5705/5750, just say success. | |
5871 | */ | |
5872 | return 0; | |
5873 | ||
5874 | default: | |
5875 | break; | |
855e1111 | 5876 | } |
1da177e4 LT |
5877 | } |
5878 | ||
5879 | val = tr32(ofs); | |
5880 | val &= ~enable_bit; | |
5881 | tw32_f(ofs, val); | |
5882 | ||
5883 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
5884 | udelay(100); | |
5885 | val = tr32(ofs); | |
5886 | if ((val & enable_bit) == 0) | |
5887 | break; | |
5888 | } | |
5889 | ||
b3b7d6be | 5890 | if (i == MAX_WAIT_CNT && !silent) { |
1da177e4 LT |
5891 | printk(KERN_ERR PFX "tg3_stop_block timed out, " |
5892 | "ofs=%lx enable_bit=%x\n", | |
5893 | ofs, enable_bit); | |
5894 | return -ENODEV; | |
5895 | } | |
5896 | ||
5897 | return 0; | |
5898 | } | |
5899 | ||
5900 | /* tp->lock is held. */ | |
b3b7d6be | 5901 | static int tg3_abort_hw(struct tg3 *tp, int silent) |
1da177e4 LT |
5902 | { |
5903 | int i, err; | |
898a56f8 | 5904 | struct tg3_napi *tnapi = &tp->napi[0]; |
1da177e4 LT |
5905 | |
5906 | tg3_disable_ints(tp); | |
5907 | ||
5908 | tp->rx_mode &= ~RX_MODE_ENABLE; | |
5909 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
5910 | udelay(10); | |
5911 | ||
b3b7d6be DM |
5912 | err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); |
5913 | err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); | |
5914 | err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); | |
5915 | err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); | |
5916 | err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); | |
5917 | err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); | |
5918 | ||
5919 | err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); | |
5920 | err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); | |
5921 | err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); | |
5922 | err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); | |
5923 | err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); | |
5924 | err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); | |
5925 | err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); | |
1da177e4 LT |
5926 | |
5927 | tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; | |
5928 | tw32_f(MAC_MODE, tp->mac_mode); | |
5929 | udelay(40); | |
5930 | ||
5931 | tp->tx_mode &= ~TX_MODE_ENABLE; | |
5932 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
5933 | ||
5934 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
5935 | udelay(100); | |
5936 | if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) | |
5937 | break; | |
5938 | } | |
5939 | if (i >= MAX_WAIT_CNT) { | |
5940 | printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, " | |
5941 | "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n", | |
5942 | tp->dev->name, tr32(MAC_TX_MODE)); | |
e6de8ad1 | 5943 | err |= -ENODEV; |
1da177e4 LT |
5944 | } |
5945 | ||
e6de8ad1 | 5946 | err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); |
b3b7d6be DM |
5947 | err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); |
5948 | err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); | |
1da177e4 LT |
5949 | |
5950 | tw32(FTQ_RESET, 0xffffffff); | |
5951 | tw32(FTQ_RESET, 0x00000000); | |
5952 | ||
b3b7d6be DM |
5953 | err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); |
5954 | err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); | |
1da177e4 | 5955 | |
898a56f8 MC |
5956 | if (tnapi->hw_status) |
5957 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
1da177e4 LT |
5958 | if (tp->hw_stats) |
5959 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); | |
5960 | ||
1da177e4 LT |
5961 | return err; |
5962 | } | |
5963 | ||
0d3031d9 MC |
5964 | static void tg3_ape_send_event(struct tg3 *tp, u32 event) |
5965 | { | |
5966 | int i; | |
5967 | u32 apedata; | |
5968 | ||
5969 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
5970 | if (apedata != APE_SEG_SIG_MAGIC) | |
5971 | return; | |
5972 | ||
5973 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
731fd79c | 5974 | if (!(apedata & APE_FW_STATUS_READY)) |
0d3031d9 MC |
5975 | return; |
5976 | ||
5977 | /* Wait for up to 1 millisecond for APE to service previous event. */ | |
5978 | for (i = 0; i < 10; i++) { | |
5979 | if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) | |
5980 | return; | |
5981 | ||
5982 | apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); | |
5983 | ||
5984 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
5985 | tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, | |
5986 | event | APE_EVENT_STATUS_EVENT_PENDING); | |
5987 | ||
5988 | tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); | |
5989 | ||
5990 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
5991 | break; | |
5992 | ||
5993 | udelay(100); | |
5994 | } | |
5995 | ||
5996 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
5997 | tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); | |
5998 | } | |
5999 | ||
6000 | static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) | |
6001 | { | |
6002 | u32 event; | |
6003 | u32 apedata; | |
6004 | ||
6005 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
6006 | return; | |
6007 | ||
6008 | switch (kind) { | |
6009 | case RESET_KIND_INIT: | |
6010 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, | |
6011 | APE_HOST_SEG_SIG_MAGIC); | |
6012 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, | |
6013 | APE_HOST_SEG_LEN_MAGIC); | |
6014 | apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); | |
6015 | tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); | |
6016 | tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, | |
6017 | APE_HOST_DRIVER_ID_MAGIC); | |
6018 | tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, | |
6019 | APE_HOST_BEHAV_NO_PHYLOCK); | |
6020 | ||
6021 | event = APE_EVENT_STATUS_STATE_START; | |
6022 | break; | |
6023 | case RESET_KIND_SHUTDOWN: | |
b2aee154 MC |
6024 | /* With the interface we are currently using, |
6025 | * APE does not track driver state. Wiping | |
6026 | * out the HOST SEGMENT SIGNATURE forces | |
6027 | * the APE to assume OS absent status. | |
6028 | */ | |
6029 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0); | |
6030 | ||
0d3031d9 MC |
6031 | event = APE_EVENT_STATUS_STATE_UNLOAD; |
6032 | break; | |
6033 | case RESET_KIND_SUSPEND: | |
6034 | event = APE_EVENT_STATUS_STATE_SUSPEND; | |
6035 | break; | |
6036 | default: | |
6037 | return; | |
6038 | } | |
6039 | ||
6040 | event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; | |
6041 | ||
6042 | tg3_ape_send_event(tp, event); | |
6043 | } | |
6044 | ||
1da177e4 LT |
6045 | /* tp->lock is held. */ |
6046 | static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) | |
6047 | { | |
f49639e6 DM |
6048 | tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, |
6049 | NIC_SRAM_FIRMWARE_MBOX_MAGIC1); | |
1da177e4 LT |
6050 | |
6051 | if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) { | |
6052 | switch (kind) { | |
6053 | case RESET_KIND_INIT: | |
6054 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6055 | DRV_STATE_START); | |
6056 | break; | |
6057 | ||
6058 | case RESET_KIND_SHUTDOWN: | |
6059 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6060 | DRV_STATE_UNLOAD); | |
6061 | break; | |
6062 | ||
6063 | case RESET_KIND_SUSPEND: | |
6064 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6065 | DRV_STATE_SUSPEND); | |
6066 | break; | |
6067 | ||
6068 | default: | |
6069 | break; | |
855e1111 | 6070 | } |
1da177e4 | 6071 | } |
0d3031d9 MC |
6072 | |
6073 | if (kind == RESET_KIND_INIT || | |
6074 | kind == RESET_KIND_SUSPEND) | |
6075 | tg3_ape_driver_state_change(tp, kind); | |
1da177e4 LT |
6076 | } |
6077 | ||
6078 | /* tp->lock is held. */ | |
6079 | static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) | |
6080 | { | |
6081 | if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) { | |
6082 | switch (kind) { | |
6083 | case RESET_KIND_INIT: | |
6084 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6085 | DRV_STATE_START_DONE); | |
6086 | break; | |
6087 | ||
6088 | case RESET_KIND_SHUTDOWN: | |
6089 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6090 | DRV_STATE_UNLOAD_DONE); | |
6091 | break; | |
6092 | ||
6093 | default: | |
6094 | break; | |
855e1111 | 6095 | } |
1da177e4 | 6096 | } |
0d3031d9 MC |
6097 | |
6098 | if (kind == RESET_KIND_SHUTDOWN) | |
6099 | tg3_ape_driver_state_change(tp, kind); | |
1da177e4 LT |
6100 | } |
6101 | ||
6102 | /* tp->lock is held. */ | |
6103 | static void tg3_write_sig_legacy(struct tg3 *tp, int kind) | |
6104 | { | |
6105 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { | |
6106 | switch (kind) { | |
6107 | case RESET_KIND_INIT: | |
6108 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6109 | DRV_STATE_START); | |
6110 | break; | |
6111 | ||
6112 | case RESET_KIND_SHUTDOWN: | |
6113 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6114 | DRV_STATE_UNLOAD); | |
6115 | break; | |
6116 | ||
6117 | case RESET_KIND_SUSPEND: | |
6118 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6119 | DRV_STATE_SUSPEND); | |
6120 | break; | |
6121 | ||
6122 | default: | |
6123 | break; | |
855e1111 | 6124 | } |
1da177e4 LT |
6125 | } |
6126 | } | |
6127 | ||
7a6f4369 MC |
6128 | static int tg3_poll_fw(struct tg3 *tp) |
6129 | { | |
6130 | int i; | |
6131 | u32 val; | |
6132 | ||
b5d3772c | 6133 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
0ccead18 GZ |
6134 | /* Wait up to 20ms for init done. */ |
6135 | for (i = 0; i < 200; i++) { | |
b5d3772c MC |
6136 | if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) |
6137 | return 0; | |
0ccead18 | 6138 | udelay(100); |
b5d3772c MC |
6139 | } |
6140 | return -ENODEV; | |
6141 | } | |
6142 | ||
7a6f4369 MC |
6143 | /* Wait for firmware initialization to complete. */ |
6144 | for (i = 0; i < 100000; i++) { | |
6145 | tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); | |
6146 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
6147 | break; | |
6148 | udelay(10); | |
6149 | } | |
6150 | ||
6151 | /* Chip might not be fitted with firmware. Some Sun onboard | |
6152 | * parts are configured like that. So don't signal the timeout | |
6153 | * of the above loop as an error, but do report the lack of | |
6154 | * running firmware once. | |
6155 | */ | |
6156 | if (i >= 100000 && | |
6157 | !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) { | |
6158 | tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED; | |
6159 | ||
6160 | printk(KERN_INFO PFX "%s: No firmware running.\n", | |
6161 | tp->dev->name); | |
6162 | } | |
6163 | ||
6164 | return 0; | |
6165 | } | |
6166 | ||
ee6a99b5 MC |
6167 | /* Save PCI command register before chip reset */ |
6168 | static void tg3_save_pci_state(struct tg3 *tp) | |
6169 | { | |
8a6eac90 | 6170 | pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); |
ee6a99b5 MC |
6171 | } |
6172 | ||
6173 | /* Restore PCI state after chip reset */ | |
6174 | static void tg3_restore_pci_state(struct tg3 *tp) | |
6175 | { | |
6176 | u32 val; | |
6177 | ||
6178 | /* Re-enable indirect register accesses. */ | |
6179 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
6180 | tp->misc_host_ctrl); | |
6181 | ||
6182 | /* Set MAX PCI retry to zero. */ | |
6183 | val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); | |
6184 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
6185 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) | |
6186 | val |= PCISTATE_RETRY_SAME_DMA; | |
0d3031d9 MC |
6187 | /* Allow reads and writes to the APE register and memory space. */ |
6188 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
6189 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
6190 | PCISTATE_ALLOW_APE_SHMEM_WR; | |
ee6a99b5 MC |
6191 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); |
6192 | ||
8a6eac90 | 6193 | pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); |
ee6a99b5 | 6194 | |
fcb389df MC |
6195 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) { |
6196 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) | |
6197 | pcie_set_readrq(tp->pdev, 4096); | |
6198 | else { | |
6199 | pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, | |
6200 | tp->pci_cacheline_sz); | |
6201 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
6202 | tp->pci_lat_timer); | |
6203 | } | |
114342f2 | 6204 | } |
5f5c51e3 | 6205 | |
ee6a99b5 | 6206 | /* Make sure PCI-X relaxed ordering bit is clear. */ |
52f4490c | 6207 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { |
9974a356 MC |
6208 | u16 pcix_cmd; |
6209 | ||
6210 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
6211 | &pcix_cmd); | |
6212 | pcix_cmd &= ~PCI_X_CMD_ERO; | |
6213 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
6214 | pcix_cmd); | |
6215 | } | |
ee6a99b5 MC |
6216 | |
6217 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { | |
ee6a99b5 MC |
6218 | |
6219 | /* Chip reset on 5780 will reset MSI enable bit, | |
6220 | * so need to restore it. | |
6221 | */ | |
6222 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | |
6223 | u16 ctrl; | |
6224 | ||
6225 | pci_read_config_word(tp->pdev, | |
6226 | tp->msi_cap + PCI_MSI_FLAGS, | |
6227 | &ctrl); | |
6228 | pci_write_config_word(tp->pdev, | |
6229 | tp->msi_cap + PCI_MSI_FLAGS, | |
6230 | ctrl | PCI_MSI_FLAGS_ENABLE); | |
6231 | val = tr32(MSGINT_MODE); | |
6232 | tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE); | |
6233 | } | |
6234 | } | |
6235 | } | |
6236 | ||
1da177e4 LT |
6237 | static void tg3_stop_fw(struct tg3 *); |
6238 | ||
6239 | /* tp->lock is held. */ | |
6240 | static int tg3_chip_reset(struct tg3 *tp) | |
6241 | { | |
6242 | u32 val; | |
1ee582d8 | 6243 | void (*write_op)(struct tg3 *, u32, u32); |
7a6f4369 | 6244 | int err; |
1da177e4 | 6245 | |
f49639e6 DM |
6246 | tg3_nvram_lock(tp); |
6247 | ||
158d7abd MC |
6248 | tg3_mdio_stop(tp); |
6249 | ||
77b483f1 MC |
6250 | tg3_ape_lock(tp, TG3_APE_LOCK_GRC); |
6251 | ||
f49639e6 DM |
6252 | /* No matching tg3_nvram_unlock() after this because |
6253 | * chip reset below will undo the nvram lock. | |
6254 | */ | |
6255 | tp->nvram_lock_cnt = 0; | |
1da177e4 | 6256 | |
ee6a99b5 MC |
6257 | /* GRC_MISC_CFG core clock reset will clear the memory |
6258 | * enable bit in PCI register 4 and the MSI enable bit | |
6259 | * on some chips, so we save relevant registers here. | |
6260 | */ | |
6261 | tg3_save_pci_state(tp); | |
6262 | ||
d9ab5ad1 | 6263 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || |
321d32a0 | 6264 | (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) |
d9ab5ad1 MC |
6265 | tw32(GRC_FASTBOOT_PC, 0); |
6266 | ||
1da177e4 LT |
6267 | /* |
6268 | * We must avoid the readl() that normally takes place. | |
6269 | * It locks machines, causes machine checks, and other | |
6270 | * fun things. So, temporarily disable the 5701 | |
6271 | * hardware workaround, while we do the reset. | |
6272 | */ | |
1ee582d8 MC |
6273 | write_op = tp->write32; |
6274 | if (write_op == tg3_write_flush_reg32) | |
6275 | tp->write32 = tg3_write32; | |
1da177e4 | 6276 | |
d18edcb2 MC |
6277 | /* Prevent the irq handler from reading or writing PCI registers |
6278 | * during chip reset when the memory enable bit in the PCI command | |
6279 | * register may be cleared. The chip does not generate interrupt | |
6280 | * at this time, but the irq handler may still be called due to irq | |
6281 | * sharing or irqpoll. | |
6282 | */ | |
6283 | tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING; | |
898a56f8 MC |
6284 | if (tp->napi[0].hw_status) { |
6285 | tp->napi[0].hw_status->status = 0; | |
6286 | tp->napi[0].hw_status->status_tag = 0; | |
b8fa2f3a | 6287 | } |
898a56f8 MC |
6288 | tp->napi[0].last_tag = 0; |
6289 | tp->napi[0].last_irq_tag = 0; | |
d18edcb2 MC |
6290 | smp_mb(); |
6291 | synchronize_irq(tp->pdev->irq); | |
6292 | ||
255ca311 MC |
6293 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
6294 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; | |
6295 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
6296 | } | |
6297 | ||
1da177e4 LT |
6298 | /* do the reset */ |
6299 | val = GRC_MISC_CFG_CORECLK_RESET; | |
6300 | ||
6301 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
6302 | if (tr32(0x7e2c) == 0x60) { | |
6303 | tw32(0x7e2c, 0x20); | |
6304 | } | |
6305 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { | |
6306 | tw32(GRC_MISC_CFG, (1 << 29)); | |
6307 | val |= (1 << 29); | |
6308 | } | |
6309 | } | |
6310 | ||
b5d3772c MC |
6311 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
6312 | tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); | |
6313 | tw32(GRC_VCPU_EXT_CTRL, | |
6314 | tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); | |
6315 | } | |
6316 | ||
1da177e4 LT |
6317 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) |
6318 | val |= GRC_MISC_CFG_KEEP_GPHY_POWER; | |
6319 | tw32(GRC_MISC_CFG, val); | |
6320 | ||
1ee582d8 MC |
6321 | /* restore 5701 hardware bug workaround write method */ |
6322 | tp->write32 = write_op; | |
1da177e4 LT |
6323 | |
6324 | /* Unfortunately, we have to delay before the PCI read back. | |
6325 | * Some 575X chips even will not respond to a PCI cfg access | |
6326 | * when the reset command is given to the chip. | |
6327 | * | |
6328 | * How do these hardware designers expect things to work | |
6329 | * properly if the PCI write is posted for a long period | |
6330 | * of time? It is always necessary to have some method by | |
6331 | * which a register read back can occur to push the write | |
6332 | * out which does the reset. | |
6333 | * | |
6334 | * For most tg3 variants the trick below was working. | |
6335 | * Ho hum... | |
6336 | */ | |
6337 | udelay(120); | |
6338 | ||
6339 | /* Flush PCI posted writes. The normal MMIO registers | |
6340 | * are inaccessible at this time so this is the only | |
6341 | * way to make this reliably (actually, this is no longer | |
6342 | * the case, see above). I tried to use indirect | |
6343 | * register read/write but this upset some 5701 variants. | |
6344 | */ | |
6345 | pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); | |
6346 | ||
6347 | udelay(120); | |
6348 | ||
5e7dfd0f | 6349 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) { |
e7126997 MC |
6350 | u16 val16; |
6351 | ||
1da177e4 LT |
6352 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { |
6353 | int i; | |
6354 | u32 cfg_val; | |
6355 | ||
6356 | /* Wait for link training to complete. */ | |
6357 | for (i = 0; i < 5000; i++) | |
6358 | udelay(100); | |
6359 | ||
6360 | pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); | |
6361 | pci_write_config_dword(tp->pdev, 0xc4, | |
6362 | cfg_val | (1 << 15)); | |
6363 | } | |
5e7dfd0f | 6364 | |
e7126997 MC |
6365 | /* Clear the "no snoop" and "relaxed ordering" bits. */ |
6366 | pci_read_config_word(tp->pdev, | |
6367 | tp->pcie_cap + PCI_EXP_DEVCTL, | |
6368 | &val16); | |
6369 | val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN | | |
6370 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
6371 | /* | |
6372 | * Older PCIe devices only support the 128 byte | |
6373 | * MPS setting. Enforce the restriction. | |
5e7dfd0f | 6374 | */ |
e7126997 MC |
6375 | if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || |
6376 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)) | |
6377 | val16 &= ~PCI_EXP_DEVCTL_PAYLOAD; | |
5e7dfd0f MC |
6378 | pci_write_config_word(tp->pdev, |
6379 | tp->pcie_cap + PCI_EXP_DEVCTL, | |
e7126997 | 6380 | val16); |
5e7dfd0f MC |
6381 | |
6382 | pcie_set_readrq(tp->pdev, 4096); | |
6383 | ||
6384 | /* Clear error status */ | |
6385 | pci_write_config_word(tp->pdev, | |
6386 | tp->pcie_cap + PCI_EXP_DEVSTA, | |
6387 | PCI_EXP_DEVSTA_CED | | |
6388 | PCI_EXP_DEVSTA_NFED | | |
6389 | PCI_EXP_DEVSTA_FED | | |
6390 | PCI_EXP_DEVSTA_URD); | |
1da177e4 LT |
6391 | } |
6392 | ||
ee6a99b5 | 6393 | tg3_restore_pci_state(tp); |
1da177e4 | 6394 | |
d18edcb2 MC |
6395 | tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING; |
6396 | ||
ee6a99b5 MC |
6397 | val = 0; |
6398 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) | |
4cf78e4f | 6399 | val = tr32(MEMARB_MODE); |
ee6a99b5 | 6400 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); |
1da177e4 LT |
6401 | |
6402 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) { | |
6403 | tg3_stop_fw(tp); | |
6404 | tw32(0x5000, 0x400); | |
6405 | } | |
6406 | ||
6407 | tw32(GRC_MODE, tp->grc_mode); | |
6408 | ||
6409 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { | |
ab0049b4 | 6410 | val = tr32(0xc4); |
1da177e4 LT |
6411 | |
6412 | tw32(0xc4, val | (1 << 15)); | |
6413 | } | |
6414 | ||
6415 | if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && | |
6416 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
6417 | tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; | |
6418 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) | |
6419 | tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; | |
6420 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
6421 | } | |
6422 | ||
6423 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { | |
6424 | tp->mac_mode = MAC_MODE_PORT_MODE_TBI; | |
6425 | tw32_f(MAC_MODE, tp->mac_mode); | |
747e8f8b MC |
6426 | } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { |
6427 | tp->mac_mode = MAC_MODE_PORT_MODE_GMII; | |
6428 | tw32_f(MAC_MODE, tp->mac_mode); | |
3bda1258 MC |
6429 | } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
6430 | tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN); | |
6431 | if (tp->mac_mode & MAC_MODE_APE_TX_EN) | |
6432 | tp->mac_mode |= MAC_MODE_TDE_ENABLE; | |
6433 | tw32_f(MAC_MODE, tp->mac_mode); | |
1da177e4 LT |
6434 | } else |
6435 | tw32_f(MAC_MODE, 0); | |
6436 | udelay(40); | |
6437 | ||
77b483f1 MC |
6438 | tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); |
6439 | ||
7a6f4369 MC |
6440 | err = tg3_poll_fw(tp); |
6441 | if (err) | |
6442 | return err; | |
1da177e4 | 6443 | |
0a9140cf MC |
6444 | tg3_mdio_start(tp); |
6445 | ||
1da177e4 LT |
6446 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && |
6447 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { | |
ab0049b4 | 6448 | val = tr32(0x7c00); |
1da177e4 LT |
6449 | |
6450 | tw32(0x7c00, val | (1 << 25)); | |
6451 | } | |
6452 | ||
6453 | /* Reprobe ASF enable state. */ | |
6454 | tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF; | |
6455 | tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE; | |
6456 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); | |
6457 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
6458 | u32 nic_cfg; | |
6459 | ||
6460 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
6461 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
6462 | tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; | |
4ba526ce | 6463 | tp->last_event_jiffies = jiffies; |
cbf46853 | 6464 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
1da177e4 LT |
6465 | tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; |
6466 | } | |
6467 | } | |
6468 | ||
6469 | return 0; | |
6470 | } | |
6471 | ||
6472 | /* tp->lock is held. */ | |
6473 | static void tg3_stop_fw(struct tg3 *tp) | |
6474 | { | |
0d3031d9 MC |
6475 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && |
6476 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
7c5026aa MC |
6477 | /* Wait for RX cpu to ACK the previous event. */ |
6478 | tg3_wait_for_event_ack(tp); | |
1da177e4 LT |
6479 | |
6480 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); | |
4ba526ce MC |
6481 | |
6482 | tg3_generate_fw_event(tp); | |
1da177e4 | 6483 | |
7c5026aa MC |
6484 | /* Wait for RX cpu to ACK this event. */ |
6485 | tg3_wait_for_event_ack(tp); | |
1da177e4 LT |
6486 | } |
6487 | } | |
6488 | ||
6489 | /* tp->lock is held. */ | |
944d980e | 6490 | static int tg3_halt(struct tg3 *tp, int kind, int silent) |
1da177e4 LT |
6491 | { |
6492 | int err; | |
6493 | ||
6494 | tg3_stop_fw(tp); | |
6495 | ||
944d980e | 6496 | tg3_write_sig_pre_reset(tp, kind); |
1da177e4 | 6497 | |
b3b7d6be | 6498 | tg3_abort_hw(tp, silent); |
1da177e4 LT |
6499 | err = tg3_chip_reset(tp); |
6500 | ||
daba2a63 MC |
6501 | __tg3_set_mac_addr(tp, 0); |
6502 | ||
944d980e MC |
6503 | tg3_write_sig_legacy(tp, kind); |
6504 | tg3_write_sig_post_reset(tp, kind); | |
1da177e4 LT |
6505 | |
6506 | if (err) | |
6507 | return err; | |
6508 | ||
6509 | return 0; | |
6510 | } | |
6511 | ||
1da177e4 LT |
6512 | #define RX_CPU_SCRATCH_BASE 0x30000 |
6513 | #define RX_CPU_SCRATCH_SIZE 0x04000 | |
6514 | #define TX_CPU_SCRATCH_BASE 0x34000 | |
6515 | #define TX_CPU_SCRATCH_SIZE 0x04000 | |
6516 | ||
6517 | /* tp->lock is held. */ | |
6518 | static int tg3_halt_cpu(struct tg3 *tp, u32 offset) | |
6519 | { | |
6520 | int i; | |
6521 | ||
5d9428de ES |
6522 | BUG_ON(offset == TX_CPU_BASE && |
6523 | (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)); | |
1da177e4 | 6524 | |
b5d3772c MC |
6525 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
6526 | u32 val = tr32(GRC_VCPU_EXT_CTRL); | |
6527 | ||
6528 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); | |
6529 | return 0; | |
6530 | } | |
1da177e4 LT |
6531 | if (offset == RX_CPU_BASE) { |
6532 | for (i = 0; i < 10000; i++) { | |
6533 | tw32(offset + CPU_STATE, 0xffffffff); | |
6534 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
6535 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
6536 | break; | |
6537 | } | |
6538 | ||
6539 | tw32(offset + CPU_STATE, 0xffffffff); | |
6540 | tw32_f(offset + CPU_MODE, CPU_MODE_HALT); | |
6541 | udelay(10); | |
6542 | } else { | |
6543 | for (i = 0; i < 10000; i++) { | |
6544 | tw32(offset + CPU_STATE, 0xffffffff); | |
6545 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
6546 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
6547 | break; | |
6548 | } | |
6549 | } | |
6550 | ||
6551 | if (i >= 10000) { | |
6552 | printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, " | |
6553 | "and %s CPU\n", | |
6554 | tp->dev->name, | |
6555 | (offset == RX_CPU_BASE ? "RX" : "TX")); | |
6556 | return -ENODEV; | |
6557 | } | |
ec41c7df MC |
6558 | |
6559 | /* Clear firmware's nvram arbitration. */ | |
6560 | if (tp->tg3_flags & TG3_FLAG_NVRAM) | |
6561 | tw32(NVRAM_SWARB, SWARB_REQ_CLR0); | |
1da177e4 LT |
6562 | return 0; |
6563 | } | |
6564 | ||
6565 | struct fw_info { | |
077f849d JSR |
6566 | unsigned int fw_base; |
6567 | unsigned int fw_len; | |
6568 | const __be32 *fw_data; | |
1da177e4 LT |
6569 | }; |
6570 | ||
6571 | /* tp->lock is held. */ | |
6572 | static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base, | |
6573 | int cpu_scratch_size, struct fw_info *info) | |
6574 | { | |
ec41c7df | 6575 | int err, lock_err, i; |
1da177e4 LT |
6576 | void (*write_op)(struct tg3 *, u32, u32); |
6577 | ||
6578 | if (cpu_base == TX_CPU_BASE && | |
6579 | (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
6580 | printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load " | |
6581 | "TX cpu firmware on %s which is 5705.\n", | |
6582 | tp->dev->name); | |
6583 | return -EINVAL; | |
6584 | } | |
6585 | ||
6586 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | |
6587 | write_op = tg3_write_mem; | |
6588 | else | |
6589 | write_op = tg3_write_indirect_reg32; | |
6590 | ||
1b628151 MC |
6591 | /* It is possible that bootcode is still loading at this point. |
6592 | * Get the nvram lock first before halting the cpu. | |
6593 | */ | |
ec41c7df | 6594 | lock_err = tg3_nvram_lock(tp); |
1da177e4 | 6595 | err = tg3_halt_cpu(tp, cpu_base); |
ec41c7df MC |
6596 | if (!lock_err) |
6597 | tg3_nvram_unlock(tp); | |
1da177e4 LT |
6598 | if (err) |
6599 | goto out; | |
6600 | ||
6601 | for (i = 0; i < cpu_scratch_size; i += sizeof(u32)) | |
6602 | write_op(tp, cpu_scratch_base + i, 0); | |
6603 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
6604 | tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT); | |
077f849d | 6605 | for (i = 0; i < (info->fw_len / sizeof(u32)); i++) |
1da177e4 | 6606 | write_op(tp, (cpu_scratch_base + |
077f849d | 6607 | (info->fw_base & 0xffff) + |
1da177e4 | 6608 | (i * sizeof(u32))), |
077f849d | 6609 | be32_to_cpu(info->fw_data[i])); |
1da177e4 LT |
6610 | |
6611 | err = 0; | |
6612 | ||
6613 | out: | |
1da177e4 LT |
6614 | return err; |
6615 | } | |
6616 | ||
6617 | /* tp->lock is held. */ | |
6618 | static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) | |
6619 | { | |
6620 | struct fw_info info; | |
077f849d | 6621 | const __be32 *fw_data; |
1da177e4 LT |
6622 | int err, i; |
6623 | ||
077f849d JSR |
6624 | fw_data = (void *)tp->fw->data; |
6625 | ||
6626 | /* Firmware blob starts with version numbers, followed by | |
6627 | start address and length. We are setting complete length. | |
6628 | length = end_address_of_bss - start_address_of_text. | |
6629 | Remainder is the blob to be loaded contiguously | |
6630 | from start address. */ | |
6631 | ||
6632 | info.fw_base = be32_to_cpu(fw_data[1]); | |
6633 | info.fw_len = tp->fw->size - 12; | |
6634 | info.fw_data = &fw_data[3]; | |
1da177e4 LT |
6635 | |
6636 | err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, | |
6637 | RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE, | |
6638 | &info); | |
6639 | if (err) | |
6640 | return err; | |
6641 | ||
6642 | err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, | |
6643 | TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE, | |
6644 | &info); | |
6645 | if (err) | |
6646 | return err; | |
6647 | ||
6648 | /* Now startup only the RX cpu. */ | |
6649 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
077f849d | 6650 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); |
1da177e4 LT |
6651 | |
6652 | for (i = 0; i < 5; i++) { | |
077f849d | 6653 | if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base) |
1da177e4 LT |
6654 | break; |
6655 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
6656 | tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT); | |
077f849d | 6657 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); |
1da177e4 LT |
6658 | udelay(1000); |
6659 | } | |
6660 | if (i >= 5) { | |
6661 | printk(KERN_ERR PFX "tg3_load_firmware fails for %s " | |
6662 | "to set RX CPU PC, is %08x should be %08x\n", | |
6663 | tp->dev->name, tr32(RX_CPU_BASE + CPU_PC), | |
077f849d | 6664 | info.fw_base); |
1da177e4 LT |
6665 | return -ENODEV; |
6666 | } | |
6667 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
6668 | tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000); | |
6669 | ||
6670 | return 0; | |
6671 | } | |
6672 | ||
1da177e4 | 6673 | /* 5705 needs a special version of the TSO firmware. */ |
1da177e4 LT |
6674 | |
6675 | /* tp->lock is held. */ | |
6676 | static int tg3_load_tso_firmware(struct tg3 *tp) | |
6677 | { | |
6678 | struct fw_info info; | |
077f849d | 6679 | const __be32 *fw_data; |
1da177e4 LT |
6680 | unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; |
6681 | int err, i; | |
6682 | ||
6683 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) | |
6684 | return 0; | |
6685 | ||
077f849d JSR |
6686 | fw_data = (void *)tp->fw->data; |
6687 | ||
6688 | /* Firmware blob starts with version numbers, followed by | |
6689 | start address and length. We are setting complete length. | |
6690 | length = end_address_of_bss - start_address_of_text. | |
6691 | Remainder is the blob to be loaded contiguously | |
6692 | from start address. */ | |
6693 | ||
6694 | info.fw_base = be32_to_cpu(fw_data[1]); | |
6695 | cpu_scratch_size = tp->fw_len; | |
6696 | info.fw_len = tp->fw->size - 12; | |
6697 | info.fw_data = &fw_data[3]; | |
6698 | ||
1da177e4 | 6699 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
6700 | cpu_base = RX_CPU_BASE; |
6701 | cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705; | |
1da177e4 | 6702 | } else { |
1da177e4 LT |
6703 | cpu_base = TX_CPU_BASE; |
6704 | cpu_scratch_base = TX_CPU_SCRATCH_BASE; | |
6705 | cpu_scratch_size = TX_CPU_SCRATCH_SIZE; | |
6706 | } | |
6707 | ||
6708 | err = tg3_load_firmware_cpu(tp, cpu_base, | |
6709 | cpu_scratch_base, cpu_scratch_size, | |
6710 | &info); | |
6711 | if (err) | |
6712 | return err; | |
6713 | ||
6714 | /* Now startup the cpu. */ | |
6715 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
077f849d | 6716 | tw32_f(cpu_base + CPU_PC, info.fw_base); |
1da177e4 LT |
6717 | |
6718 | for (i = 0; i < 5; i++) { | |
077f849d | 6719 | if (tr32(cpu_base + CPU_PC) == info.fw_base) |
1da177e4 LT |
6720 | break; |
6721 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
6722 | tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); | |
077f849d | 6723 | tw32_f(cpu_base + CPU_PC, info.fw_base); |
1da177e4 LT |
6724 | udelay(1000); |
6725 | } | |
6726 | if (i >= 5) { | |
6727 | printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s " | |
6728 | "to set CPU PC, is %08x should be %08x\n", | |
6729 | tp->dev->name, tr32(cpu_base + CPU_PC), | |
077f849d | 6730 | info.fw_base); |
1da177e4 LT |
6731 | return -ENODEV; |
6732 | } | |
6733 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
6734 | tw32_f(cpu_base + CPU_MODE, 0x00000000); | |
6735 | return 0; | |
6736 | } | |
6737 | ||
1da177e4 | 6738 | |
1da177e4 LT |
6739 | static int tg3_set_mac_addr(struct net_device *dev, void *p) |
6740 | { | |
6741 | struct tg3 *tp = netdev_priv(dev); | |
6742 | struct sockaddr *addr = p; | |
986e0aeb | 6743 | int err = 0, skip_mac_1 = 0; |
1da177e4 | 6744 | |
f9804ddb MC |
6745 | if (!is_valid_ether_addr(addr->sa_data)) |
6746 | return -EINVAL; | |
6747 | ||
1da177e4 LT |
6748 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
6749 | ||
e75f7c90 MC |
6750 | if (!netif_running(dev)) |
6751 | return 0; | |
6752 | ||
58712ef9 | 6753 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { |
986e0aeb | 6754 | u32 addr0_high, addr0_low, addr1_high, addr1_low; |
58712ef9 | 6755 | |
986e0aeb MC |
6756 | addr0_high = tr32(MAC_ADDR_0_HIGH); |
6757 | addr0_low = tr32(MAC_ADDR_0_LOW); | |
6758 | addr1_high = tr32(MAC_ADDR_1_HIGH); | |
6759 | addr1_low = tr32(MAC_ADDR_1_LOW); | |
6760 | ||
6761 | /* Skip MAC addr 1 if ASF is using it. */ | |
6762 | if ((addr0_high != addr1_high || addr0_low != addr1_low) && | |
6763 | !(addr1_high == 0 && addr1_low == 0)) | |
6764 | skip_mac_1 = 1; | |
58712ef9 | 6765 | } |
986e0aeb MC |
6766 | spin_lock_bh(&tp->lock); |
6767 | __tg3_set_mac_addr(tp, skip_mac_1); | |
6768 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 6769 | |
b9ec6c1b | 6770 | return err; |
1da177e4 LT |
6771 | } |
6772 | ||
6773 | /* tp->lock is held. */ | |
6774 | static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, | |
6775 | dma_addr_t mapping, u32 maxlen_flags, | |
6776 | u32 nic_addr) | |
6777 | { | |
6778 | tg3_write_mem(tp, | |
6779 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
6780 | ((u64) mapping >> 32)); | |
6781 | tg3_write_mem(tp, | |
6782 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW), | |
6783 | ((u64) mapping & 0xffffffff)); | |
6784 | tg3_write_mem(tp, | |
6785 | (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS), | |
6786 | maxlen_flags); | |
6787 | ||
6788 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
6789 | tg3_write_mem(tp, | |
6790 | (bdinfo_addr + TG3_BDINFO_NIC_ADDR), | |
6791 | nic_addr); | |
6792 | } | |
6793 | ||
6794 | static void __tg3_set_rx_mode(struct net_device *); | |
d244c892 | 6795 | static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) |
15f9850d DM |
6796 | { |
6797 | tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); | |
6798 | tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); | |
6799 | tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); | |
6800 | tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); | |
6801 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
6802 | tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); | |
6803 | tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); | |
6804 | } | |
6805 | tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); | |
6806 | tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); | |
6807 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
6808 | u32 val = ec->stats_block_coalesce_usecs; | |
6809 | ||
6810 | if (!netif_carrier_ok(tp->dev)) | |
6811 | val = 0; | |
6812 | ||
6813 | tw32(HOSTCC_STAT_COAL_TICKS, val); | |
6814 | } | |
6815 | } | |
1da177e4 LT |
6816 | |
6817 | /* tp->lock is held. */ | |
8e7a22e3 | 6818 | static int tg3_reset_hw(struct tg3 *tp, int reset_phy) |
1da177e4 LT |
6819 | { |
6820 | u32 val, rdmac_mode; | |
6821 | int i, err, limit; | |
21f581a5 | 6822 | struct tg3_rx_prodring_set *tpr = &tp->prodring[0]; |
1da177e4 LT |
6823 | |
6824 | tg3_disable_ints(tp); | |
6825 | ||
6826 | tg3_stop_fw(tp); | |
6827 | ||
6828 | tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); | |
6829 | ||
6830 | if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) { | |
e6de8ad1 | 6831 | tg3_abort_hw(tp, 1); |
1da177e4 LT |
6832 | } |
6833 | ||
dd477003 MC |
6834 | if (reset_phy && |
6835 | !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) | |
d4d2c558 MC |
6836 | tg3_phy_reset(tp); |
6837 | ||
1da177e4 LT |
6838 | err = tg3_chip_reset(tp); |
6839 | if (err) | |
6840 | return err; | |
6841 | ||
6842 | tg3_write_sig_legacy(tp, RESET_KIND_INIT); | |
6843 | ||
bcb37f6c | 6844 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
d30cdd28 MC |
6845 | val = tr32(TG3_CPMU_CTRL); |
6846 | val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); | |
6847 | tw32(TG3_CPMU_CTRL, val); | |
9acb961e MC |
6848 | |
6849 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
6850 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
6851 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
6852 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
6853 | ||
6854 | val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); | |
6855 | val &= ~CPMU_LNK_AWARE_MACCLK_MASK; | |
6856 | val |= CPMU_LNK_AWARE_MACCLK_6_25; | |
6857 | tw32(TG3_CPMU_LNK_AWARE_PWRMD, val); | |
6858 | ||
6859 | val = tr32(TG3_CPMU_HST_ACC); | |
6860 | val &= ~CPMU_HST_ACC_MACCLK_MASK; | |
6861 | val |= CPMU_HST_ACC_MACCLK_6_25; | |
6862 | tw32(TG3_CPMU_HST_ACC, val); | |
d30cdd28 MC |
6863 | } |
6864 | ||
33466d93 MC |
6865 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
6866 | val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; | |
6867 | val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | | |
6868 | PCIE_PWR_MGMT_L1_THRESH_4MS; | |
6869 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
521e6b90 MC |
6870 | |
6871 | val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; | |
6872 | tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS); | |
6873 | ||
6874 | tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR); | |
33466d93 MC |
6875 | } |
6876 | ||
255ca311 MC |
6877 | if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) { |
6878 | val = tr32(TG3_PCIE_LNKCTL); | |
6879 | if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) | |
6880 | val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS; | |
6881 | else | |
6882 | val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS; | |
6883 | tw32(TG3_PCIE_LNKCTL, val); | |
6884 | } | |
6885 | ||
1da177e4 LT |
6886 | /* This works around an issue with Athlon chipsets on |
6887 | * B3 tigon3 silicon. This bit has no effect on any | |
6888 | * other revision. But do not set this on PCI Express | |
795d01c5 | 6889 | * chips and don't even touch the clocks if the CPMU is present. |
1da177e4 | 6890 | */ |
795d01c5 MC |
6891 | if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) { |
6892 | if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
6893 | tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; | |
6894 | tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
6895 | } | |
1da177e4 LT |
6896 | |
6897 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
6898 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { | |
6899 | val = tr32(TG3PCI_PCISTATE); | |
6900 | val |= PCISTATE_RETRY_SAME_DMA; | |
6901 | tw32(TG3PCI_PCISTATE, val); | |
6902 | } | |
6903 | ||
0d3031d9 MC |
6904 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
6905 | /* Allow reads and writes to the | |
6906 | * APE register and memory space. | |
6907 | */ | |
6908 | val = tr32(TG3PCI_PCISTATE); | |
6909 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
6910 | PCISTATE_ALLOW_APE_SHMEM_WR; | |
6911 | tw32(TG3PCI_PCISTATE, val); | |
6912 | } | |
6913 | ||
1da177e4 LT |
6914 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) { |
6915 | /* Enable some hw fixes. */ | |
6916 | val = tr32(TG3PCI_MSI_DATA); | |
6917 | val |= (1 << 26) | (1 << 28) | (1 << 29); | |
6918 | tw32(TG3PCI_MSI_DATA, val); | |
6919 | } | |
6920 | ||
6921 | /* Descriptor ring init may make accesses to the | |
6922 | * NIC SRAM area to setup the TX descriptors, so we | |
6923 | * can only do this after the hardware has been | |
6924 | * successfully reset. | |
6925 | */ | |
32d8c572 MC |
6926 | err = tg3_init_rings(tp); |
6927 | if (err) | |
6928 | return err; | |
1da177e4 | 6929 | |
9936bcf6 | 6930 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && |
fcb389df | 6931 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { |
d30cdd28 MC |
6932 | /* This value is determined during the probe time DMA |
6933 | * engine test, tg3_test_dma. | |
6934 | */ | |
6935 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
6936 | } | |
1da177e4 LT |
6937 | |
6938 | tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | | |
6939 | GRC_MODE_4X_NIC_SEND_RINGS | | |
6940 | GRC_MODE_NO_TX_PHDR_CSUM | | |
6941 | GRC_MODE_NO_RX_PHDR_CSUM); | |
6942 | tp->grc_mode |= GRC_MODE_HOST_SENDBDS; | |
d2d746f8 MC |
6943 | |
6944 | /* Pseudo-header checksum is done by hardware logic and not | |
6945 | * the offload processers, so make the chip do the pseudo- | |
6946 | * header checksums on receive. For transmit it is more | |
6947 | * convenient to do the pseudo-header checksum in software | |
6948 | * as Linux does that on transmit for us in all cases. | |
6949 | */ | |
6950 | tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; | |
1da177e4 LT |
6951 | |
6952 | tw32(GRC_MODE, | |
6953 | tp->grc_mode | | |
6954 | (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP)); | |
6955 | ||
6956 | /* Setup the timer prescalar register. Clock is always 66Mhz. */ | |
6957 | val = tr32(GRC_MISC_CFG); | |
6958 | val &= ~0xff; | |
6959 | val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
6960 | tw32(GRC_MISC_CFG, val); | |
6961 | ||
6962 | /* Initialize MBUF/DESC pool. */ | |
cbf46853 | 6963 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { |
1da177e4 LT |
6964 | /* Do nothing. */ |
6965 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { | |
6966 | tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); | |
6967 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
6968 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); | |
6969 | else | |
6970 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); | |
6971 | tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); | |
6972 | tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); | |
6973 | } | |
1da177e4 LT |
6974 | else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) { |
6975 | int fw_len; | |
6976 | ||
077f849d | 6977 | fw_len = tp->fw_len; |
1da177e4 LT |
6978 | fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); |
6979 | tw32(BUFMGR_MB_POOL_ADDR, | |
6980 | NIC_SRAM_MBUF_POOL_BASE5705 + fw_len); | |
6981 | tw32(BUFMGR_MB_POOL_SIZE, | |
6982 | NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); | |
6983 | } | |
1da177e4 | 6984 | |
0f893dc6 | 6985 | if (tp->dev->mtu <= ETH_DATA_LEN) { |
1da177e4 LT |
6986 | tw32(BUFMGR_MB_RDMA_LOW_WATER, |
6987 | tp->bufmgr_config.mbuf_read_dma_low_water); | |
6988 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
6989 | tp->bufmgr_config.mbuf_mac_rx_low_water); | |
6990 | tw32(BUFMGR_MB_HIGH_WATER, | |
6991 | tp->bufmgr_config.mbuf_high_water); | |
6992 | } else { | |
6993 | tw32(BUFMGR_MB_RDMA_LOW_WATER, | |
6994 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); | |
6995 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
6996 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); | |
6997 | tw32(BUFMGR_MB_HIGH_WATER, | |
6998 | tp->bufmgr_config.mbuf_high_water_jumbo); | |
6999 | } | |
7000 | tw32(BUFMGR_DMA_LOW_WATER, | |
7001 | tp->bufmgr_config.dma_low_water); | |
7002 | tw32(BUFMGR_DMA_HIGH_WATER, | |
7003 | tp->bufmgr_config.dma_high_water); | |
7004 | ||
7005 | tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE); | |
7006 | for (i = 0; i < 2000; i++) { | |
7007 | if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) | |
7008 | break; | |
7009 | udelay(10); | |
7010 | } | |
7011 | if (i >= 2000) { | |
7012 | printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n", | |
7013 | tp->dev->name); | |
7014 | return -ENODEV; | |
7015 | } | |
7016 | ||
7017 | /* Setup replenish threshold. */ | |
f92905de MC |
7018 | val = tp->rx_pending / 8; |
7019 | if (val == 0) | |
7020 | val = 1; | |
7021 | else if (val > tp->rx_std_max_post) | |
7022 | val = tp->rx_std_max_post; | |
b5d3772c MC |
7023 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
7024 | if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1) | |
7025 | tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); | |
7026 | ||
7027 | if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2)) | |
7028 | val = TG3_RX_INTERNAL_RING_SZ_5906 / 2; | |
7029 | } | |
f92905de MC |
7030 | |
7031 | tw32(RCVBDI_STD_THRESH, val); | |
1da177e4 LT |
7032 | |
7033 | /* Initialize TG3_BDINFO's at: | |
7034 | * RCVDBDI_STD_BD: standard eth size rx ring | |
7035 | * RCVDBDI_JUMBO_BD: jumbo frame rx ring | |
7036 | * RCVDBDI_MINI_BD: small frame rx ring (??? does not work) | |
7037 | * | |
7038 | * like so: | |
7039 | * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring | |
7040 | * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) | | |
7041 | * ring attribute flags | |
7042 | * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM | |
7043 | * | |
7044 | * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries. | |
7045 | * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries. | |
7046 | * | |
7047 | * The size of each ring is fixed in the firmware, but the location is | |
7048 | * configurable. | |
7049 | */ | |
7050 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
21f581a5 | 7051 | ((u64) tpr->rx_std_mapping >> 32)); |
1da177e4 | 7052 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 7053 | ((u64) tpr->rx_std_mapping & 0xffffffff)); |
1da177e4 LT |
7054 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, |
7055 | NIC_SRAM_RX_BUFFER_DESC); | |
7056 | ||
fdb72b38 MC |
7057 | /* Disable the mini ring */ |
7058 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
1da177e4 LT |
7059 | tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, |
7060 | BDINFO_FLAGS_DISABLED); | |
7061 | ||
fdb72b38 MC |
7062 | /* Program the jumbo buffer descriptor ring control |
7063 | * blocks on those devices that have them. | |
7064 | */ | |
8f666b07 | 7065 | if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && |
fdb72b38 | 7066 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
1da177e4 LT |
7067 | /* Setup replenish threshold. */ |
7068 | tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8); | |
7069 | ||
0f893dc6 | 7070 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) { |
1da177e4 | 7071 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, |
21f581a5 | 7072 | ((u64) tpr->rx_jmb_mapping >> 32)); |
1da177e4 | 7073 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 7074 | ((u64) tpr->rx_jmb_mapping & 0xffffffff)); |
1da177e4 | 7075 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, |
79ed5ac7 MC |
7076 | (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) | |
7077 | BDINFO_FLAGS_USE_EXT_RECV); | |
1da177e4 LT |
7078 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, |
7079 | NIC_SRAM_RX_JUMBO_BUFFER_DESC); | |
7080 | } else { | |
7081 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
7082 | BDINFO_FLAGS_DISABLED); | |
7083 | } | |
7084 | ||
fdb72b38 MC |
7085 | val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT; |
7086 | } else | |
7087 | val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT; | |
7088 | ||
7089 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val); | |
1da177e4 LT |
7090 | |
7091 | /* There is only one send ring on 5705/5750, no need to explicitly | |
7092 | * disable the others. | |
7093 | */ | |
7094 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
7095 | /* Clear out send RCB ring in SRAM. */ | |
7096 | for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE) | |
7097 | tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS, | |
7098 | BDINFO_FLAGS_DISABLED); | |
7099 | } | |
7100 | ||
f3f3f27e MC |
7101 | tp->napi[0].tx_prod = 0; |
7102 | tp->napi[0].tx_cons = 0; | |
1da177e4 LT |
7103 | tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0); |
7104 | ||
f3f3f27e MC |
7105 | val = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW; |
7106 | tw32_mailbox(val, 0); | |
7107 | ||
1da177e4 | 7108 | tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB, |
f3f3f27e | 7109 | tp->napi[0].tx_desc_mapping, |
1da177e4 LT |
7110 | (TG3_TX_RING_SIZE << |
7111 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
7112 | NIC_SRAM_TX_BUFFER_DESC); | |
7113 | ||
7114 | /* There is only one receive return ring on 5705/5750, no need | |
7115 | * to explicitly disable the others. | |
7116 | */ | |
7117 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
7118 | for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK; | |
7119 | i += TG3_BDINFO_SIZE) { | |
7120 | tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS, | |
7121 | BDINFO_FLAGS_DISABLED); | |
7122 | } | |
7123 | } | |
7124 | ||
72334482 | 7125 | tw32_rx_mbox(tp->napi[0].consmbox, 0); |
1da177e4 LT |
7126 | |
7127 | tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB, | |
72334482 | 7128 | tp->napi[0].rx_rcb_mapping, |
1da177e4 LT |
7129 | (TG3_RX_RCB_RING_SIZE(tp) << |
7130 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
7131 | 0); | |
7132 | ||
21f581a5 | 7133 | tpr->rx_std_ptr = tp->rx_pending; |
1da177e4 | 7134 | tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW, |
21f581a5 | 7135 | tpr->rx_std_ptr); |
1da177e4 | 7136 | |
21f581a5 MC |
7137 | tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ? |
7138 | tp->rx_jumbo_pending : 0; | |
1da177e4 | 7139 | tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW, |
21f581a5 | 7140 | tpr->rx_jmb_ptr); |
1da177e4 LT |
7141 | |
7142 | /* Initialize MAC address and backoff seed. */ | |
986e0aeb | 7143 | __tg3_set_mac_addr(tp, 0); |
1da177e4 LT |
7144 | |
7145 | /* MTU + ethernet header + FCS + optional VLAN tag */ | |
f7b493e0 MC |
7146 | tw32(MAC_RX_MTU_SIZE, |
7147 | tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); | |
1da177e4 LT |
7148 | |
7149 | /* The slot time is changed by tg3_setup_phy if we | |
7150 | * run at gigabit with half duplex. | |
7151 | */ | |
7152 | tw32(MAC_TX_LENGTHS, | |
7153 | (2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
7154 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
7155 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
7156 | ||
7157 | /* Receive rules. */ | |
7158 | tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS); | |
7159 | tw32(RCVLPC_CONFIG, 0x0181); | |
7160 | ||
7161 | /* Calculate RDMAC_MODE setting early, we need it to determine | |
7162 | * the RCVLPC_STATE_ENABLE mask. | |
7163 | */ | |
7164 | rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB | | |
7165 | RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB | | |
7166 | RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB | | |
7167 | RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | | |
7168 | RDMAC_MODE_LNGREAD_ENAB); | |
85e94ced | 7169 | |
57e6983c | 7170 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 MC |
7171 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
7172 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
d30cdd28 MC |
7173 | rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | |
7174 | RDMAC_MODE_MBUF_RBD_CRPT_ENAB | | |
7175 | RDMAC_MODE_MBUF_SBD_CRPT_ENAB; | |
7176 | ||
85e94ced MC |
7177 | /* If statement applies to 5705 and 5750 PCI devices only */ |
7178 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
7179 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) || | |
7180 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) { | |
1da177e4 | 7181 | if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE && |
c13e3713 | 7182 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
7183 | rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128; |
7184 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
7185 | !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) { | |
7186 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; | |
7187 | } | |
7188 | } | |
7189 | ||
85e94ced MC |
7190 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) |
7191 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; | |
7192 | ||
1da177e4 | 7193 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) |
027455ad MC |
7194 | rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN; |
7195 | ||
7196 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
7197 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
7198 | rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN; | |
1da177e4 LT |
7199 | |
7200 | /* Receive/send statistics. */ | |
1661394e MC |
7201 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { |
7202 | val = tr32(RCVLPC_STATS_ENABLE); | |
7203 | val &= ~RCVLPC_STATSENAB_DACK_FIX; | |
7204 | tw32(RCVLPC_STATS_ENABLE, val); | |
7205 | } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) && | |
7206 | (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
1da177e4 LT |
7207 | val = tr32(RCVLPC_STATS_ENABLE); |
7208 | val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX; | |
7209 | tw32(RCVLPC_STATS_ENABLE, val); | |
7210 | } else { | |
7211 | tw32(RCVLPC_STATS_ENABLE, 0xffffff); | |
7212 | } | |
7213 | tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE); | |
7214 | tw32(SNDDATAI_STATSENAB, 0xffffff); | |
7215 | tw32(SNDDATAI_STATSCTRL, | |
7216 | (SNDDATAI_SCTRL_ENABLE | | |
7217 | SNDDATAI_SCTRL_FASTUPD)); | |
7218 | ||
7219 | /* Setup host coalescing engine. */ | |
7220 | tw32(HOSTCC_MODE, 0); | |
7221 | for (i = 0; i < 2000; i++) { | |
7222 | if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) | |
7223 | break; | |
7224 | udelay(10); | |
7225 | } | |
7226 | ||
d244c892 | 7227 | __tg3_set_coalesce(tp, &tp->coal); |
1da177e4 LT |
7228 | |
7229 | /* set status block DMA address */ | |
7230 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
898a56f8 | 7231 | ((u64) tp->napi[0].status_mapping >> 32)); |
1da177e4 | 7232 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, |
898a56f8 | 7233 | ((u64) tp->napi[0].status_mapping & 0xffffffff)); |
1da177e4 LT |
7234 | |
7235 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
7236 | /* Status/statistics block address. See tg3_timer, | |
7237 | * the tg3_periodic_fetch_stats call there, and | |
7238 | * tg3_get_stats to see how this works for 5705/5750 chips. | |
7239 | */ | |
1da177e4 LT |
7240 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, |
7241 | ((u64) tp->stats_mapping >> 32)); | |
7242 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
7243 | ((u64) tp->stats_mapping & 0xffffffff)); | |
7244 | tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK); | |
7245 | tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK); | |
7246 | } | |
7247 | ||
7248 | tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); | |
7249 | ||
7250 | tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE); | |
7251 | tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE); | |
7252 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
7253 | tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE); | |
7254 | ||
7255 | /* Clear statistics/status block in chip, and status block in ram. */ | |
7256 | for (i = NIC_SRAM_STATS_BLK; | |
7257 | i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE; | |
7258 | i += sizeof(u32)) { | |
7259 | tg3_write_mem(tp, i, 0); | |
7260 | udelay(40); | |
7261 | } | |
898a56f8 | 7262 | memset(tp->napi[0].hw_status, 0, TG3_HW_STATUS_SIZE); |
1da177e4 | 7263 | |
c94e3941 MC |
7264 | if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { |
7265 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
7266 | /* reset to prevent losing 1st rx packet intermittently */ | |
7267 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
7268 | udelay(10); | |
7269 | } | |
7270 | ||
3bda1258 MC |
7271 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
7272 | tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | |
7273 | else | |
7274 | tp->mac_mode = 0; | |
7275 | tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | | |
1da177e4 | 7276 | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE; |
e8f3f6ca MC |
7277 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && |
7278 | !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && | |
7279 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) | |
7280 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
7281 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); |
7282 | udelay(40); | |
7283 | ||
314fba34 | 7284 | /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). |
9d26e213 | 7285 | * If TG3_FLG2_IS_NIC is zero, we should read the |
314fba34 MC |
7286 | * register to preserve the GPIO settings for LOMs. The GPIOs, |
7287 | * whether used as inputs or outputs, are set by boot code after | |
7288 | * reset. | |
7289 | */ | |
9d26e213 | 7290 | if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) { |
314fba34 MC |
7291 | u32 gpio_mask; |
7292 | ||
9d26e213 MC |
7293 | gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 | |
7294 | GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
7295 | GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
3e7d83bc MC |
7296 | |
7297 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
7298 | gpio_mask |= GRC_LCLCTRL_GPIO_OE3 | | |
7299 | GRC_LCLCTRL_GPIO_OUTPUT3; | |
7300 | ||
af36e6b6 MC |
7301 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
7302 | gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL; | |
7303 | ||
aaf84465 | 7304 | tp->grc_local_ctrl &= ~gpio_mask; |
314fba34 MC |
7305 | tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; |
7306 | ||
7307 | /* GPIO1 must be driven high for eeprom write protect */ | |
9d26e213 MC |
7308 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) |
7309 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | | |
7310 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
314fba34 | 7311 | } |
1da177e4 LT |
7312 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
7313 | udelay(100); | |
7314 | ||
898a56f8 | 7315 | tw32_mailbox_f(tp->napi[0].int_mbox, 0); |
1da177e4 LT |
7316 | |
7317 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
7318 | tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); | |
7319 | udelay(40); | |
7320 | } | |
7321 | ||
7322 | val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB | | |
7323 | WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB | | |
7324 | WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB | | |
7325 | WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | | |
7326 | WDMAC_MODE_LNGREAD_ENAB); | |
7327 | ||
85e94ced MC |
7328 | /* If statement applies to 5705 and 5750 PCI devices only */ |
7329 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
7330 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) || | |
7331 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) { | |
29ea095f | 7332 | if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) && |
1da177e4 LT |
7333 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || |
7334 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { | |
7335 | /* nothing */ | |
7336 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
7337 | !(tp->tg3_flags2 & TG3_FLG2_IS_5788) && | |
7338 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) { | |
7339 | val |= WDMAC_MODE_RX_ACCEL; | |
7340 | } | |
7341 | } | |
7342 | ||
d9ab5ad1 | 7343 | /* Enable host coalescing bug fix */ |
321d32a0 | 7344 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
f51f3562 | 7345 | val |= WDMAC_MODE_STATUS_TAG_FIX; |
d9ab5ad1 | 7346 | |
1da177e4 LT |
7347 | tw32_f(WDMAC_MODE, val); |
7348 | udelay(40); | |
7349 | ||
9974a356 MC |
7350 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { |
7351 | u16 pcix_cmd; | |
7352 | ||
7353 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7354 | &pcix_cmd); | |
1da177e4 | 7355 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { |
9974a356 MC |
7356 | pcix_cmd &= ~PCI_X_CMD_MAX_READ; |
7357 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 7358 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
9974a356 MC |
7359 | pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ); |
7360 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 7361 | } |
9974a356 MC |
7362 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, |
7363 | pcix_cmd); | |
1da177e4 LT |
7364 | } |
7365 | ||
7366 | tw32_f(RDMAC_MODE, rdmac_mode); | |
7367 | udelay(40); | |
7368 | ||
7369 | tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE); | |
7370 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
7371 | tw32(MBFREE_MODE, MBFREE_MODE_ENABLE); | |
9936bcf6 MC |
7372 | |
7373 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
7374 | tw32(SNDDATAC_MODE, | |
7375 | SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY); | |
7376 | else | |
7377 | tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE); | |
7378 | ||
1da177e4 LT |
7379 | tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE); |
7380 | tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB); | |
7381 | tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ); | |
7382 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); | |
1da177e4 LT |
7383 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) |
7384 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8); | |
1da177e4 LT |
7385 | tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE); |
7386 | tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); | |
7387 | ||
7388 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
7389 | err = tg3_load_5701_a0_firmware_fix(tp); | |
7390 | if (err) | |
7391 | return err; | |
7392 | } | |
7393 | ||
1da177e4 LT |
7394 | if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) { |
7395 | err = tg3_load_tso_firmware(tp); | |
7396 | if (err) | |
7397 | return err; | |
7398 | } | |
1da177e4 LT |
7399 | |
7400 | tp->tx_mode = TX_MODE_ENABLE; | |
7401 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
7402 | udelay(100); | |
7403 | ||
7404 | tp->rx_mode = RX_MODE_ENABLE; | |
321d32a0 | 7405 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
af36e6b6 MC |
7406 | tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; |
7407 | ||
1da177e4 LT |
7408 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
7409 | udelay(10); | |
7410 | ||
1da177e4 LT |
7411 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
7412 | ||
7413 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
c94e3941 | 7414 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { |
1da177e4 LT |
7415 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
7416 | udelay(10); | |
7417 | } | |
7418 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
7419 | udelay(10); | |
7420 | ||
7421 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { | |
7422 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) && | |
7423 | !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) { | |
7424 | /* Set drive transmission level to 1.2V */ | |
7425 | /* only if the signal pre-emphasis bit is not set */ | |
7426 | val = tr32(MAC_SERDES_CFG); | |
7427 | val &= 0xfffff000; | |
7428 | val |= 0x880; | |
7429 | tw32(MAC_SERDES_CFG, val); | |
7430 | } | |
7431 | if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) | |
7432 | tw32(MAC_SERDES_CFG, 0x616000); | |
7433 | } | |
7434 | ||
7435 | /* Prevent chip from dropping frames when flow control | |
7436 | * is enabled. | |
7437 | */ | |
7438 | tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2); | |
7439 | ||
7440 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && | |
7441 | (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { | |
7442 | /* Use hardware link auto-negotiation */ | |
7443 | tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG; | |
7444 | } | |
7445 | ||
d4d2c558 MC |
7446 | if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) && |
7447 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) { | |
7448 | u32 tmp; | |
7449 | ||
7450 | tmp = tr32(SERDES_RX_CTRL); | |
7451 | tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT); | |
7452 | tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; | |
7453 | tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; | |
7454 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
7455 | } | |
7456 | ||
dd477003 MC |
7457 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { |
7458 | if (tp->link_config.phy_is_low_power) { | |
7459 | tp->link_config.phy_is_low_power = 0; | |
7460 | tp->link_config.speed = tp->link_config.orig_speed; | |
7461 | tp->link_config.duplex = tp->link_config.orig_duplex; | |
7462 | tp->link_config.autoneg = tp->link_config.orig_autoneg; | |
7463 | } | |
1da177e4 | 7464 | |
dd477003 MC |
7465 | err = tg3_setup_phy(tp, 0); |
7466 | if (err) | |
7467 | return err; | |
1da177e4 | 7468 | |
dd477003 | 7469 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && |
7f97a4bd | 7470 | !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) { |
dd477003 MC |
7471 | u32 tmp; |
7472 | ||
7473 | /* Clear CRC stats. */ | |
7474 | if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { | |
7475 | tg3_writephy(tp, MII_TG3_TEST1, | |
7476 | tmp | MII_TG3_TEST1_CRC_EN); | |
7477 | tg3_readphy(tp, 0x14, &tmp); | |
7478 | } | |
1da177e4 LT |
7479 | } |
7480 | } | |
7481 | ||
7482 | __tg3_set_rx_mode(tp->dev); | |
7483 | ||
7484 | /* Initialize receive rules. */ | |
7485 | tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK); | |
7486 | tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
7487 | tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); | |
7488 | tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
7489 | ||
4cf78e4f | 7490 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && |
a4e2b347 | 7491 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) |
1da177e4 LT |
7492 | limit = 8; |
7493 | else | |
7494 | limit = 16; | |
7495 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) | |
7496 | limit -= 4; | |
7497 | switch (limit) { | |
7498 | case 16: | |
7499 | tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0); | |
7500 | case 15: | |
7501 | tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0); | |
7502 | case 14: | |
7503 | tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0); | |
7504 | case 13: | |
7505 | tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0); | |
7506 | case 12: | |
7507 | tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0); | |
7508 | case 11: | |
7509 | tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0); | |
7510 | case 10: | |
7511 | tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0); | |
7512 | case 9: | |
7513 | tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0); | |
7514 | case 8: | |
7515 | tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0); | |
7516 | case 7: | |
7517 | tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0); | |
7518 | case 6: | |
7519 | tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0); | |
7520 | case 5: | |
7521 | tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0); | |
7522 | case 4: | |
7523 | /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */ | |
7524 | case 3: | |
7525 | /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */ | |
7526 | case 2: | |
7527 | case 1: | |
7528 | ||
7529 | default: | |
7530 | break; | |
855e1111 | 7531 | } |
1da177e4 | 7532 | |
9ce768ea MC |
7533 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
7534 | /* Write our heartbeat update interval to APE. */ | |
7535 | tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, | |
7536 | APE_HOST_HEARTBEAT_INT_DISABLE); | |
0d3031d9 | 7537 | |
1da177e4 LT |
7538 | tg3_write_sig_post_reset(tp, RESET_KIND_INIT); |
7539 | ||
1da177e4 LT |
7540 | return 0; |
7541 | } | |
7542 | ||
7543 | /* Called at device open time to get the chip ready for | |
7544 | * packet processing. Invoked with tp->lock held. | |
7545 | */ | |
8e7a22e3 | 7546 | static int tg3_init_hw(struct tg3 *tp, int reset_phy) |
1da177e4 | 7547 | { |
1da177e4 LT |
7548 | tg3_switch_clocks(tp); |
7549 | ||
7550 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
7551 | ||
2f751b67 | 7552 | return tg3_reset_hw(tp, reset_phy); |
1da177e4 LT |
7553 | } |
7554 | ||
7555 | #define TG3_STAT_ADD32(PSTAT, REG) \ | |
7556 | do { u32 __val = tr32(REG); \ | |
7557 | (PSTAT)->low += __val; \ | |
7558 | if ((PSTAT)->low < __val) \ | |
7559 | (PSTAT)->high += 1; \ | |
7560 | } while (0) | |
7561 | ||
7562 | static void tg3_periodic_fetch_stats(struct tg3 *tp) | |
7563 | { | |
7564 | struct tg3_hw_stats *sp = tp->hw_stats; | |
7565 | ||
7566 | if (!netif_carrier_ok(tp->dev)) | |
7567 | return; | |
7568 | ||
7569 | TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); | |
7570 | TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); | |
7571 | TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); | |
7572 | TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); | |
7573 | TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); | |
7574 | TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); | |
7575 | TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); | |
7576 | TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); | |
7577 | TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); | |
7578 | TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); | |
7579 | TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); | |
7580 | TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); | |
7581 | TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); | |
7582 | ||
7583 | TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); | |
7584 | TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); | |
7585 | TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); | |
7586 | TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); | |
7587 | TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); | |
7588 | TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); | |
7589 | TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); | |
7590 | TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); | |
7591 | TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); | |
7592 | TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); | |
7593 | TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); | |
7594 | TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); | |
7595 | TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); | |
7596 | TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); | |
463d305b MC |
7597 | |
7598 | TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); | |
7599 | TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); | |
7600 | TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); | |
1da177e4 LT |
7601 | } |
7602 | ||
7603 | static void tg3_timer(unsigned long __opaque) | |
7604 | { | |
7605 | struct tg3 *tp = (struct tg3 *) __opaque; | |
1da177e4 | 7606 | |
f475f163 MC |
7607 | if (tp->irq_sync) |
7608 | goto restart_timer; | |
7609 | ||
f47c11ee | 7610 | spin_lock(&tp->lock); |
1da177e4 | 7611 | |
fac9b83e DM |
7612 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { |
7613 | /* All of this garbage is because when using non-tagged | |
7614 | * IRQ status the mailbox/status_block protocol the chip | |
7615 | * uses with the cpu is race prone. | |
7616 | */ | |
898a56f8 | 7617 | if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { |
fac9b83e DM |
7618 | tw32(GRC_LOCAL_CTRL, |
7619 | tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
7620 | } else { | |
7621 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
7622 | (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW)); | |
7623 | } | |
1da177e4 | 7624 | |
fac9b83e DM |
7625 | if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { |
7626 | tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER; | |
f47c11ee | 7627 | spin_unlock(&tp->lock); |
fac9b83e DM |
7628 | schedule_work(&tp->reset_task); |
7629 | return; | |
7630 | } | |
1da177e4 LT |
7631 | } |
7632 | ||
1da177e4 LT |
7633 | /* This part only runs once per second. */ |
7634 | if (!--tp->timer_counter) { | |
fac9b83e DM |
7635 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) |
7636 | tg3_periodic_fetch_stats(tp); | |
7637 | ||
1da177e4 LT |
7638 | if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) { |
7639 | u32 mac_stat; | |
7640 | int phy_event; | |
7641 | ||
7642 | mac_stat = tr32(MAC_STATUS); | |
7643 | ||
7644 | phy_event = 0; | |
7645 | if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) { | |
7646 | if (mac_stat & MAC_STATUS_MI_INTERRUPT) | |
7647 | phy_event = 1; | |
7648 | } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) | |
7649 | phy_event = 1; | |
7650 | ||
7651 | if (phy_event) | |
7652 | tg3_setup_phy(tp, 0); | |
7653 | } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) { | |
7654 | u32 mac_stat = tr32(MAC_STATUS); | |
7655 | int need_setup = 0; | |
7656 | ||
7657 | if (netif_carrier_ok(tp->dev) && | |
7658 | (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) { | |
7659 | need_setup = 1; | |
7660 | } | |
7661 | if (! netif_carrier_ok(tp->dev) && | |
7662 | (mac_stat & (MAC_STATUS_PCS_SYNCED | | |
7663 | MAC_STATUS_SIGNAL_DET))) { | |
7664 | need_setup = 1; | |
7665 | } | |
7666 | if (need_setup) { | |
3d3ebe74 MC |
7667 | if (!tp->serdes_counter) { |
7668 | tw32_f(MAC_MODE, | |
7669 | (tp->mac_mode & | |
7670 | ~MAC_MODE_PORT_MODE_MASK)); | |
7671 | udelay(40); | |
7672 | tw32_f(MAC_MODE, tp->mac_mode); | |
7673 | udelay(40); | |
7674 | } | |
1da177e4 LT |
7675 | tg3_setup_phy(tp, 0); |
7676 | } | |
747e8f8b MC |
7677 | } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) |
7678 | tg3_serdes_parallel_detect(tp); | |
1da177e4 LT |
7679 | |
7680 | tp->timer_counter = tp->timer_multiplier; | |
7681 | } | |
7682 | ||
130b8e4d MC |
7683 | /* Heartbeat is only sent once every 2 seconds. |
7684 | * | |
7685 | * The heartbeat is to tell the ASF firmware that the host | |
7686 | * driver is still alive. In the event that the OS crashes, | |
7687 | * ASF needs to reset the hardware to free up the FIFO space | |
7688 | * that may be filled with rx packets destined for the host. | |
7689 | * If the FIFO is full, ASF will no longer function properly. | |
7690 | * | |
7691 | * Unintended resets have been reported on real time kernels | |
7692 | * where the timer doesn't run on time. Netpoll will also have | |
7693 | * same problem. | |
7694 | * | |
7695 | * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware | |
7696 | * to check the ring condition when the heartbeat is expiring | |
7697 | * before doing the reset. This will prevent most unintended | |
7698 | * resets. | |
7699 | */ | |
1da177e4 | 7700 | if (!--tp->asf_counter) { |
bc7959b2 MC |
7701 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && |
7702 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
7c5026aa MC |
7703 | tg3_wait_for_event_ack(tp); |
7704 | ||
bbadf503 | 7705 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, |
130b8e4d | 7706 | FWCMD_NICDRV_ALIVE3); |
bbadf503 | 7707 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); |
28fbef78 | 7708 | /* 5 seconds timeout */ |
bbadf503 | 7709 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5); |
4ba526ce MC |
7710 | |
7711 | tg3_generate_fw_event(tp); | |
1da177e4 LT |
7712 | } |
7713 | tp->asf_counter = tp->asf_multiplier; | |
7714 | } | |
7715 | ||
f47c11ee | 7716 | spin_unlock(&tp->lock); |
1da177e4 | 7717 | |
f475f163 | 7718 | restart_timer: |
1da177e4 LT |
7719 | tp->timer.expires = jiffies + tp->timer_offset; |
7720 | add_timer(&tp->timer); | |
7721 | } | |
7722 | ||
81789ef5 | 7723 | static int tg3_request_irq(struct tg3 *tp) |
fcfa0a32 | 7724 | { |
7d12e780 | 7725 | irq_handler_t fn; |
fcfa0a32 | 7726 | unsigned long flags; |
09943a18 | 7727 | char *name = tp->dev->name; |
fcfa0a32 MC |
7728 | |
7729 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | |
7730 | fn = tg3_msi; | |
7731 | if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) | |
7732 | fn = tg3_msi_1shot; | |
1fb9df5d | 7733 | flags = IRQF_SAMPLE_RANDOM; |
fcfa0a32 MC |
7734 | } else { |
7735 | fn = tg3_interrupt; | |
7736 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) | |
7737 | fn = tg3_interrupt_tagged; | |
1fb9df5d | 7738 | flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM; |
fcfa0a32 | 7739 | } |
09943a18 | 7740 | return request_irq(tp->pdev->irq, fn, flags, name, &tp->napi[0]); |
fcfa0a32 MC |
7741 | } |
7742 | ||
7938109f MC |
7743 | static int tg3_test_interrupt(struct tg3 *tp) |
7744 | { | |
09943a18 | 7745 | struct tg3_napi *tnapi = &tp->napi[0]; |
7938109f | 7746 | struct net_device *dev = tp->dev; |
b16250e3 | 7747 | int err, i, intr_ok = 0; |
7938109f | 7748 | |
d4bc3927 MC |
7749 | if (!netif_running(dev)) |
7750 | return -ENODEV; | |
7751 | ||
7938109f MC |
7752 | tg3_disable_ints(tp); |
7753 | ||
09943a18 | 7754 | free_irq(tp->pdev->irq, tnapi); |
7938109f MC |
7755 | |
7756 | err = request_irq(tp->pdev->irq, tg3_test_isr, | |
09943a18 | 7757 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi); |
7938109f MC |
7758 | if (err) |
7759 | return err; | |
7760 | ||
898a56f8 | 7761 | tnapi->hw_status->status &= ~SD_STATUS_UPDATED; |
7938109f MC |
7762 | tg3_enable_ints(tp); |
7763 | ||
7764 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
7765 | HOSTCC_MODE_NOW); | |
7766 | ||
7767 | for (i = 0; i < 5; i++) { | |
b16250e3 MC |
7768 | u32 int_mbox, misc_host_ctrl; |
7769 | ||
898a56f8 | 7770 | int_mbox = tr32_mailbox(tnapi->int_mbox); |
b16250e3 MC |
7771 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
7772 | ||
7773 | if ((int_mbox != 0) || | |
7774 | (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) { | |
7775 | intr_ok = 1; | |
7938109f | 7776 | break; |
b16250e3 MC |
7777 | } |
7778 | ||
7938109f MC |
7779 | msleep(10); |
7780 | } | |
7781 | ||
7782 | tg3_disable_ints(tp); | |
7783 | ||
09943a18 | 7784 | free_irq(tp->pdev->irq, tnapi); |
6aa20a22 | 7785 | |
fcfa0a32 | 7786 | err = tg3_request_irq(tp); |
7938109f MC |
7787 | |
7788 | if (err) | |
7789 | return err; | |
7790 | ||
b16250e3 | 7791 | if (intr_ok) |
7938109f MC |
7792 | return 0; |
7793 | ||
7794 | return -EIO; | |
7795 | } | |
7796 | ||
7797 | /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is | |
7798 | * successfully restored | |
7799 | */ | |
7800 | static int tg3_test_msi(struct tg3 *tp) | |
7801 | { | |
7938109f MC |
7802 | int err; |
7803 | u16 pci_cmd; | |
7804 | ||
7805 | if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI)) | |
7806 | return 0; | |
7807 | ||
7808 | /* Turn off SERR reporting in case MSI terminates with Master | |
7809 | * Abort. | |
7810 | */ | |
7811 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
7812 | pci_write_config_word(tp->pdev, PCI_COMMAND, | |
7813 | pci_cmd & ~PCI_COMMAND_SERR); | |
7814 | ||
7815 | err = tg3_test_interrupt(tp); | |
7816 | ||
7817 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
7818 | ||
7819 | if (!err) | |
7820 | return 0; | |
7821 | ||
7822 | /* other failures */ | |
7823 | if (err != -EIO) | |
7824 | return err; | |
7825 | ||
7826 | /* MSI test failed, go back to INTx mode */ | |
7827 | printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, " | |
7828 | "switching to INTx mode. Please report this failure to " | |
7829 | "the PCI maintainer and include system chipset information.\n", | |
7830 | tp->dev->name); | |
7831 | ||
09943a18 MC |
7832 | free_irq(tp->pdev->irq, &tp->napi[0]); |
7833 | ||
7938109f MC |
7834 | pci_disable_msi(tp->pdev); |
7835 | ||
7836 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI; | |
7837 | ||
fcfa0a32 | 7838 | err = tg3_request_irq(tp); |
7938109f MC |
7839 | if (err) |
7840 | return err; | |
7841 | ||
7842 | /* Need to reset the chip because the MSI cycle may have terminated | |
7843 | * with Master Abort. | |
7844 | */ | |
f47c11ee | 7845 | tg3_full_lock(tp, 1); |
7938109f | 7846 | |
944d980e | 7847 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
8e7a22e3 | 7848 | err = tg3_init_hw(tp, 1); |
7938109f | 7849 | |
f47c11ee | 7850 | tg3_full_unlock(tp); |
7938109f MC |
7851 | |
7852 | if (err) | |
09943a18 | 7853 | free_irq(tp->pdev->irq, &tp->napi[0]); |
7938109f MC |
7854 | |
7855 | return err; | |
7856 | } | |
7857 | ||
9e9fd12d MC |
7858 | static int tg3_request_firmware(struct tg3 *tp) |
7859 | { | |
7860 | const __be32 *fw_data; | |
7861 | ||
7862 | if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { | |
7863 | printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n", | |
7864 | tp->dev->name, tp->fw_needed); | |
7865 | return -ENOENT; | |
7866 | } | |
7867 | ||
7868 | fw_data = (void *)tp->fw->data; | |
7869 | ||
7870 | /* Firmware blob starts with version numbers, followed by | |
7871 | * start address and _full_ length including BSS sections | |
7872 | * (which must be longer than the actual data, of course | |
7873 | */ | |
7874 | ||
7875 | tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */ | |
7876 | if (tp->fw_len < (tp->fw->size - 12)) { | |
7877 | printk(KERN_ERR "%s: bogus length %d in \"%s\"\n", | |
7878 | tp->dev->name, tp->fw_len, tp->fw_needed); | |
7879 | release_firmware(tp->fw); | |
7880 | tp->fw = NULL; | |
7881 | return -EINVAL; | |
7882 | } | |
7883 | ||
7884 | /* We no longer need firmware; we have it. */ | |
7885 | tp->fw_needed = NULL; | |
7886 | return 0; | |
7887 | } | |
7888 | ||
07b0173c MC |
7889 | static void tg3_ints_init(struct tg3 *tp) |
7890 | { | |
7891 | if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) { | |
7892 | /* All MSI supporting chips should support tagged | |
7893 | * status. Assert that this is the case. | |
7894 | */ | |
7895 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { | |
7896 | printk(KERN_WARNING PFX "%s: MSI without TAGGED? " | |
7897 | "Not using MSI.\n", tp->dev->name); | |
7898 | } else if (pci_enable_msi(tp->pdev) == 0) { | |
7899 | u32 msi_mode; | |
7900 | ||
7901 | msi_mode = tr32(MSGINT_MODE); | |
7902 | tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE); | |
7903 | tp->tg3_flags2 |= TG3_FLG2_USING_MSI; | |
7904 | } | |
7905 | } | |
7906 | } | |
7907 | ||
7908 | static void tg3_ints_fini(struct tg3 *tp) | |
7909 | { | |
7910 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | |
7911 | pci_disable_msi(tp->pdev); | |
7912 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI; | |
7913 | } | |
7914 | } | |
7915 | ||
1da177e4 LT |
7916 | static int tg3_open(struct net_device *dev) |
7917 | { | |
7918 | struct tg3 *tp = netdev_priv(dev); | |
7919 | int err; | |
7920 | ||
9e9fd12d MC |
7921 | if (tp->fw_needed) { |
7922 | err = tg3_request_firmware(tp); | |
7923 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
7924 | if (err) | |
7925 | return err; | |
7926 | } else if (err) { | |
7927 | printk(KERN_WARNING "%s: TSO capability disabled.\n", | |
7928 | tp->dev->name); | |
7929 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; | |
7930 | } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
7931 | printk(KERN_NOTICE "%s: TSO capability restored.\n", | |
7932 | tp->dev->name); | |
7933 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; | |
7934 | } | |
7935 | } | |
7936 | ||
c49a1561 MC |
7937 | netif_carrier_off(tp->dev); |
7938 | ||
bc1c7567 | 7939 | err = tg3_set_power_state(tp, PCI_D0); |
2f751b67 | 7940 | if (err) |
bc1c7567 | 7941 | return err; |
2f751b67 MC |
7942 | |
7943 | tg3_full_lock(tp, 0); | |
bc1c7567 | 7944 | |
1da177e4 LT |
7945 | tg3_disable_ints(tp); |
7946 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; | |
7947 | ||
f47c11ee | 7948 | tg3_full_unlock(tp); |
1da177e4 LT |
7949 | |
7950 | /* The placement of this call is tied | |
7951 | * to the setup and use of Host TX descriptors. | |
7952 | */ | |
7953 | err = tg3_alloc_consistent(tp); | |
7954 | if (err) | |
7955 | return err; | |
7956 | ||
07b0173c | 7957 | tg3_ints_init(tp); |
88b06bc2 | 7958 | |
8ef0442f | 7959 | napi_enable(&tp->napi[0].napi); |
1da177e4 | 7960 | |
07b0173c | 7961 | err = tg3_request_irq(tp); |
1da177e4 | 7962 | |
07b0173c MC |
7963 | if (err) |
7964 | goto err_out1; | |
bea3348e | 7965 | |
f47c11ee | 7966 | tg3_full_lock(tp, 0); |
1da177e4 | 7967 | |
8e7a22e3 | 7968 | err = tg3_init_hw(tp, 1); |
1da177e4 | 7969 | if (err) { |
944d980e | 7970 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
7971 | tg3_free_rings(tp); |
7972 | } else { | |
fac9b83e DM |
7973 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) |
7974 | tp->timer_offset = HZ; | |
7975 | else | |
7976 | tp->timer_offset = HZ / 10; | |
7977 | ||
7978 | BUG_ON(tp->timer_offset > HZ); | |
7979 | tp->timer_counter = tp->timer_multiplier = | |
7980 | (HZ / tp->timer_offset); | |
7981 | tp->asf_counter = tp->asf_multiplier = | |
28fbef78 | 7982 | ((HZ / tp->timer_offset) * 2); |
1da177e4 LT |
7983 | |
7984 | init_timer(&tp->timer); | |
7985 | tp->timer.expires = jiffies + tp->timer_offset; | |
7986 | tp->timer.data = (unsigned long) tp; | |
7987 | tp->timer.function = tg3_timer; | |
1da177e4 LT |
7988 | } |
7989 | ||
f47c11ee | 7990 | tg3_full_unlock(tp); |
1da177e4 | 7991 | |
07b0173c MC |
7992 | if (err) |
7993 | goto err_out2; | |
1da177e4 | 7994 | |
7938109f MC |
7995 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { |
7996 | err = tg3_test_msi(tp); | |
fac9b83e | 7997 | |
7938109f | 7998 | if (err) { |
f47c11ee | 7999 | tg3_full_lock(tp, 0); |
944d980e | 8000 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
7938109f | 8001 | tg3_free_rings(tp); |
f47c11ee | 8002 | tg3_full_unlock(tp); |
7938109f | 8003 | |
07b0173c | 8004 | goto err_out1; |
7938109f | 8005 | } |
fcfa0a32 MC |
8006 | |
8007 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | |
8008 | if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) { | |
b5d3772c | 8009 | u32 val = tr32(PCIE_TRANSACTION_CFG); |
fcfa0a32 | 8010 | |
b5d3772c MC |
8011 | tw32(PCIE_TRANSACTION_CFG, |
8012 | val | PCIE_TRANS_CFG_1SHOT_MSI); | |
fcfa0a32 MC |
8013 | } |
8014 | } | |
7938109f MC |
8015 | } |
8016 | ||
b02fd9e3 MC |
8017 | tg3_phy_start(tp); |
8018 | ||
f47c11ee | 8019 | tg3_full_lock(tp, 0); |
1da177e4 | 8020 | |
7938109f MC |
8021 | add_timer(&tp->timer); |
8022 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; | |
1da177e4 LT |
8023 | tg3_enable_ints(tp); |
8024 | ||
f47c11ee | 8025 | tg3_full_unlock(tp); |
1da177e4 LT |
8026 | |
8027 | netif_start_queue(dev); | |
8028 | ||
8029 | return 0; | |
07b0173c MC |
8030 | |
8031 | err_out2: | |
09943a18 | 8032 | free_irq(tp->pdev->irq, &tp->napi[0]); |
07b0173c MC |
8033 | |
8034 | err_out1: | |
8ef0442f | 8035 | napi_disable(&tp->napi[0].napi); |
07b0173c MC |
8036 | tg3_ints_fini(tp); |
8037 | tg3_free_consistent(tp); | |
8038 | return err; | |
1da177e4 LT |
8039 | } |
8040 | ||
8041 | #if 0 | |
8042 | /*static*/ void tg3_dump_state(struct tg3 *tp) | |
8043 | { | |
8044 | u32 val32, val32_2, val32_3, val32_4, val32_5; | |
8045 | u16 val16; | |
8046 | int i; | |
898a56f8 | 8047 | struct tg3_hw_status *sblk = tp->napi[0]->hw_status; |
1da177e4 LT |
8048 | |
8049 | pci_read_config_word(tp->pdev, PCI_STATUS, &val16); | |
8050 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32); | |
8051 | printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n", | |
8052 | val16, val32); | |
8053 | ||
8054 | /* MAC block */ | |
8055 | printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n", | |
8056 | tr32(MAC_MODE), tr32(MAC_STATUS)); | |
8057 | printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n", | |
8058 | tr32(MAC_EVENT), tr32(MAC_LED_CTRL)); | |
8059 | printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n", | |
8060 | tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS)); | |
8061 | printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n", | |
8062 | tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS)); | |
8063 | ||
8064 | /* Send data initiator control block */ | |
8065 | printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n", | |
8066 | tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS)); | |
8067 | printk(" SNDDATAI_STATSCTRL[%08x]\n", | |
8068 | tr32(SNDDATAI_STATSCTRL)); | |
8069 | ||
8070 | /* Send data completion control block */ | |
8071 | printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE)); | |
8072 | ||
8073 | /* Send BD ring selector block */ | |
8074 | printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n", | |
8075 | tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS)); | |
8076 | ||
8077 | /* Send BD initiator control block */ | |
8078 | printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n", | |
8079 | tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS)); | |
8080 | ||
8081 | /* Send BD completion control block */ | |
8082 | printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE)); | |
8083 | ||
8084 | /* Receive list placement control block */ | |
8085 | printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n", | |
8086 | tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS)); | |
8087 | printk(" RCVLPC_STATSCTRL[%08x]\n", | |
8088 | tr32(RCVLPC_STATSCTRL)); | |
8089 | ||
8090 | /* Receive data and receive BD initiator control block */ | |
8091 | printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n", | |
8092 | tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS)); | |
8093 | ||
8094 | /* Receive data completion control block */ | |
8095 | printk("DEBUG: RCVDCC_MODE[%08x]\n", | |
8096 | tr32(RCVDCC_MODE)); | |
8097 | ||
8098 | /* Receive BD initiator control block */ | |
8099 | printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n", | |
8100 | tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS)); | |
8101 | ||
8102 | /* Receive BD completion control block */ | |
8103 | printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n", | |
8104 | tr32(RCVCC_MODE), tr32(RCVCC_STATUS)); | |
8105 | ||
8106 | /* Receive list selector control block */ | |
8107 | printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n", | |
8108 | tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS)); | |
8109 | ||
8110 | /* Mbuf cluster free block */ | |
8111 | printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n", | |
8112 | tr32(MBFREE_MODE), tr32(MBFREE_STATUS)); | |
8113 | ||
8114 | /* Host coalescing control block */ | |
8115 | printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n", | |
8116 | tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS)); | |
8117 | printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n", | |
8118 | tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
8119 | tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW)); | |
8120 | printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n", | |
8121 | tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
8122 | tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW)); | |
8123 | printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n", | |
8124 | tr32(HOSTCC_STATS_BLK_NIC_ADDR)); | |
8125 | printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n", | |
8126 | tr32(HOSTCC_STATUS_BLK_NIC_ADDR)); | |
8127 | ||
8128 | /* Memory arbiter control block */ | |
8129 | printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n", | |
8130 | tr32(MEMARB_MODE), tr32(MEMARB_STATUS)); | |
8131 | ||
8132 | /* Buffer manager control block */ | |
8133 | printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n", | |
8134 | tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS)); | |
8135 | printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n", | |
8136 | tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE)); | |
8137 | printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] " | |
8138 | "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n", | |
8139 | tr32(BUFMGR_DMA_DESC_POOL_ADDR), | |
8140 | tr32(BUFMGR_DMA_DESC_POOL_SIZE)); | |
8141 | ||
8142 | /* Read DMA control block */ | |
8143 | printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n", | |
8144 | tr32(RDMAC_MODE), tr32(RDMAC_STATUS)); | |
8145 | ||
8146 | /* Write DMA control block */ | |
8147 | printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n", | |
8148 | tr32(WDMAC_MODE), tr32(WDMAC_STATUS)); | |
8149 | ||
8150 | /* DMA completion block */ | |
8151 | printk("DEBUG: DMAC_MODE[%08x]\n", | |
8152 | tr32(DMAC_MODE)); | |
8153 | ||
8154 | /* GRC block */ | |
8155 | printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n", | |
8156 | tr32(GRC_MODE), tr32(GRC_MISC_CFG)); | |
8157 | printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n", | |
8158 | tr32(GRC_LOCAL_CTRL)); | |
8159 | ||
8160 | /* TG3_BDINFOs */ | |
8161 | printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n", | |
8162 | tr32(RCVDBDI_JUMBO_BD + 0x0), | |
8163 | tr32(RCVDBDI_JUMBO_BD + 0x4), | |
8164 | tr32(RCVDBDI_JUMBO_BD + 0x8), | |
8165 | tr32(RCVDBDI_JUMBO_BD + 0xc)); | |
8166 | printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n", | |
8167 | tr32(RCVDBDI_STD_BD + 0x0), | |
8168 | tr32(RCVDBDI_STD_BD + 0x4), | |
8169 | tr32(RCVDBDI_STD_BD + 0x8), | |
8170 | tr32(RCVDBDI_STD_BD + 0xc)); | |
8171 | printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n", | |
8172 | tr32(RCVDBDI_MINI_BD + 0x0), | |
8173 | tr32(RCVDBDI_MINI_BD + 0x4), | |
8174 | tr32(RCVDBDI_MINI_BD + 0x8), | |
8175 | tr32(RCVDBDI_MINI_BD + 0xc)); | |
8176 | ||
8177 | tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32); | |
8178 | tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2); | |
8179 | tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3); | |
8180 | tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4); | |
8181 | printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n", | |
8182 | val32, val32_2, val32_3, val32_4); | |
8183 | ||
8184 | tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32); | |
8185 | tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2); | |
8186 | tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3); | |
8187 | tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4); | |
8188 | printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n", | |
8189 | val32, val32_2, val32_3, val32_4); | |
8190 | ||
8191 | tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32); | |
8192 | tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2); | |
8193 | tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3); | |
8194 | tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4); | |
8195 | tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5); | |
8196 | printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n", | |
8197 | val32, val32_2, val32_3, val32_4, val32_5); | |
8198 | ||
8199 | /* SW status block */ | |
898a56f8 MC |
8200 | printk(KERN_DEBUG |
8201 | "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n", | |
8202 | sblk->status, | |
8203 | sblk->status_tag, | |
8204 | sblk->rx_jumbo_consumer, | |
8205 | sblk->rx_consumer, | |
8206 | sblk->rx_mini_consumer, | |
8207 | sblk->idx[0].rx_producer, | |
8208 | sblk->idx[0].tx_consumer); | |
1da177e4 LT |
8209 | |
8210 | /* SW statistics block */ | |
8211 | printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n", | |
8212 | ((u32 *)tp->hw_stats)[0], | |
8213 | ((u32 *)tp->hw_stats)[1], | |
8214 | ((u32 *)tp->hw_stats)[2], | |
8215 | ((u32 *)tp->hw_stats)[3]); | |
8216 | ||
8217 | /* Mailboxes */ | |
8218 | printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n", | |
09ee929c MC |
8219 | tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0), |
8220 | tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4), | |
8221 | tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0), | |
8222 | tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4)); | |
1da177e4 LT |
8223 | |
8224 | /* NIC side send descriptors. */ | |
8225 | for (i = 0; i < 6; i++) { | |
8226 | unsigned long txd; | |
8227 | ||
8228 | txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC | |
8229 | + (i * sizeof(struct tg3_tx_buffer_desc)); | |
8230 | printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n", | |
8231 | i, | |
8232 | readl(txd + 0x0), readl(txd + 0x4), | |
8233 | readl(txd + 0x8), readl(txd + 0xc)); | |
8234 | } | |
8235 | ||
8236 | /* NIC side RX descriptors. */ | |
8237 | for (i = 0; i < 6; i++) { | |
8238 | unsigned long rxd; | |
8239 | ||
8240 | rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC | |
8241 | + (i * sizeof(struct tg3_rx_buffer_desc)); | |
8242 | printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n", | |
8243 | i, | |
8244 | readl(rxd + 0x0), readl(rxd + 0x4), | |
8245 | readl(rxd + 0x8), readl(rxd + 0xc)); | |
8246 | rxd += (4 * sizeof(u32)); | |
8247 | printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n", | |
8248 | i, | |
8249 | readl(rxd + 0x0), readl(rxd + 0x4), | |
8250 | readl(rxd + 0x8), readl(rxd + 0xc)); | |
8251 | } | |
8252 | ||
8253 | for (i = 0; i < 6; i++) { | |
8254 | unsigned long rxd; | |
8255 | ||
8256 | rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC | |
8257 | + (i * sizeof(struct tg3_rx_buffer_desc)); | |
8258 | printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n", | |
8259 | i, | |
8260 | readl(rxd + 0x0), readl(rxd + 0x4), | |
8261 | readl(rxd + 0x8), readl(rxd + 0xc)); | |
8262 | rxd += (4 * sizeof(u32)); | |
8263 | printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n", | |
8264 | i, | |
8265 | readl(rxd + 0x0), readl(rxd + 0x4), | |
8266 | readl(rxd + 0x8), readl(rxd + 0xc)); | |
8267 | } | |
8268 | } | |
8269 | #endif | |
8270 | ||
8271 | static struct net_device_stats *tg3_get_stats(struct net_device *); | |
8272 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *); | |
8273 | ||
8274 | static int tg3_close(struct net_device *dev) | |
8275 | { | |
8276 | struct tg3 *tp = netdev_priv(dev); | |
8277 | ||
8ef0442f | 8278 | napi_disable(&tp->napi[0].napi); |
28e53bdd | 8279 | cancel_work_sync(&tp->reset_task); |
7faa006f | 8280 | |
1da177e4 LT |
8281 | netif_stop_queue(dev); |
8282 | ||
8283 | del_timer_sync(&tp->timer); | |
8284 | ||
f47c11ee | 8285 | tg3_full_lock(tp, 1); |
1da177e4 LT |
8286 | #if 0 |
8287 | tg3_dump_state(tp); | |
8288 | #endif | |
8289 | ||
8290 | tg3_disable_ints(tp); | |
8291 | ||
944d980e | 8292 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 | 8293 | tg3_free_rings(tp); |
5cf64b8a | 8294 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; |
1da177e4 | 8295 | |
f47c11ee | 8296 | tg3_full_unlock(tp); |
1da177e4 | 8297 | |
09943a18 | 8298 | free_irq(tp->pdev->irq, &tp->napi[0]); |
07b0173c MC |
8299 | |
8300 | tg3_ints_fini(tp); | |
1da177e4 LT |
8301 | |
8302 | memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev), | |
8303 | sizeof(tp->net_stats_prev)); | |
8304 | memcpy(&tp->estats_prev, tg3_get_estats(tp), | |
8305 | sizeof(tp->estats_prev)); | |
8306 | ||
8307 | tg3_free_consistent(tp); | |
8308 | ||
bc1c7567 MC |
8309 | tg3_set_power_state(tp, PCI_D3hot); |
8310 | ||
8311 | netif_carrier_off(tp->dev); | |
8312 | ||
1da177e4 LT |
8313 | return 0; |
8314 | } | |
8315 | ||
8316 | static inline unsigned long get_stat64(tg3_stat64_t *val) | |
8317 | { | |
8318 | unsigned long ret; | |
8319 | ||
8320 | #if (BITS_PER_LONG == 32) | |
8321 | ret = val->low; | |
8322 | #else | |
8323 | ret = ((u64)val->high << 32) | ((u64)val->low); | |
8324 | #endif | |
8325 | return ret; | |
8326 | } | |
8327 | ||
816f8b86 SB |
8328 | static inline u64 get_estat64(tg3_stat64_t *val) |
8329 | { | |
8330 | return ((u64)val->high << 32) | ((u64)val->low); | |
8331 | } | |
8332 | ||
1da177e4 LT |
8333 | static unsigned long calc_crc_errors(struct tg3 *tp) |
8334 | { | |
8335 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
8336 | ||
8337 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && | |
8338 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
8339 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
1da177e4 LT |
8340 | u32 val; |
8341 | ||
f47c11ee | 8342 | spin_lock_bh(&tp->lock); |
569a5df8 MC |
8343 | if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { |
8344 | tg3_writephy(tp, MII_TG3_TEST1, | |
8345 | val | MII_TG3_TEST1_CRC_EN); | |
1da177e4 LT |
8346 | tg3_readphy(tp, 0x14, &val); |
8347 | } else | |
8348 | val = 0; | |
f47c11ee | 8349 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
8350 | |
8351 | tp->phy_crc_errors += val; | |
8352 | ||
8353 | return tp->phy_crc_errors; | |
8354 | } | |
8355 | ||
8356 | return get_stat64(&hw_stats->rx_fcs_errors); | |
8357 | } | |
8358 | ||
8359 | #define ESTAT_ADD(member) \ | |
8360 | estats->member = old_estats->member + \ | |
816f8b86 | 8361 | get_estat64(&hw_stats->member) |
1da177e4 LT |
8362 | |
8363 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp) | |
8364 | { | |
8365 | struct tg3_ethtool_stats *estats = &tp->estats; | |
8366 | struct tg3_ethtool_stats *old_estats = &tp->estats_prev; | |
8367 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
8368 | ||
8369 | if (!hw_stats) | |
8370 | return old_estats; | |
8371 | ||
8372 | ESTAT_ADD(rx_octets); | |
8373 | ESTAT_ADD(rx_fragments); | |
8374 | ESTAT_ADD(rx_ucast_packets); | |
8375 | ESTAT_ADD(rx_mcast_packets); | |
8376 | ESTAT_ADD(rx_bcast_packets); | |
8377 | ESTAT_ADD(rx_fcs_errors); | |
8378 | ESTAT_ADD(rx_align_errors); | |
8379 | ESTAT_ADD(rx_xon_pause_rcvd); | |
8380 | ESTAT_ADD(rx_xoff_pause_rcvd); | |
8381 | ESTAT_ADD(rx_mac_ctrl_rcvd); | |
8382 | ESTAT_ADD(rx_xoff_entered); | |
8383 | ESTAT_ADD(rx_frame_too_long_errors); | |
8384 | ESTAT_ADD(rx_jabbers); | |
8385 | ESTAT_ADD(rx_undersize_packets); | |
8386 | ESTAT_ADD(rx_in_length_errors); | |
8387 | ESTAT_ADD(rx_out_length_errors); | |
8388 | ESTAT_ADD(rx_64_or_less_octet_packets); | |
8389 | ESTAT_ADD(rx_65_to_127_octet_packets); | |
8390 | ESTAT_ADD(rx_128_to_255_octet_packets); | |
8391 | ESTAT_ADD(rx_256_to_511_octet_packets); | |
8392 | ESTAT_ADD(rx_512_to_1023_octet_packets); | |
8393 | ESTAT_ADD(rx_1024_to_1522_octet_packets); | |
8394 | ESTAT_ADD(rx_1523_to_2047_octet_packets); | |
8395 | ESTAT_ADD(rx_2048_to_4095_octet_packets); | |
8396 | ESTAT_ADD(rx_4096_to_8191_octet_packets); | |
8397 | ESTAT_ADD(rx_8192_to_9022_octet_packets); | |
8398 | ||
8399 | ESTAT_ADD(tx_octets); | |
8400 | ESTAT_ADD(tx_collisions); | |
8401 | ESTAT_ADD(tx_xon_sent); | |
8402 | ESTAT_ADD(tx_xoff_sent); | |
8403 | ESTAT_ADD(tx_flow_control); | |
8404 | ESTAT_ADD(tx_mac_errors); | |
8405 | ESTAT_ADD(tx_single_collisions); | |
8406 | ESTAT_ADD(tx_mult_collisions); | |
8407 | ESTAT_ADD(tx_deferred); | |
8408 | ESTAT_ADD(tx_excessive_collisions); | |
8409 | ESTAT_ADD(tx_late_collisions); | |
8410 | ESTAT_ADD(tx_collide_2times); | |
8411 | ESTAT_ADD(tx_collide_3times); | |
8412 | ESTAT_ADD(tx_collide_4times); | |
8413 | ESTAT_ADD(tx_collide_5times); | |
8414 | ESTAT_ADD(tx_collide_6times); | |
8415 | ESTAT_ADD(tx_collide_7times); | |
8416 | ESTAT_ADD(tx_collide_8times); | |
8417 | ESTAT_ADD(tx_collide_9times); | |
8418 | ESTAT_ADD(tx_collide_10times); | |
8419 | ESTAT_ADD(tx_collide_11times); | |
8420 | ESTAT_ADD(tx_collide_12times); | |
8421 | ESTAT_ADD(tx_collide_13times); | |
8422 | ESTAT_ADD(tx_collide_14times); | |
8423 | ESTAT_ADD(tx_collide_15times); | |
8424 | ESTAT_ADD(tx_ucast_packets); | |
8425 | ESTAT_ADD(tx_mcast_packets); | |
8426 | ESTAT_ADD(tx_bcast_packets); | |
8427 | ESTAT_ADD(tx_carrier_sense_errors); | |
8428 | ESTAT_ADD(tx_discards); | |
8429 | ESTAT_ADD(tx_errors); | |
8430 | ||
8431 | ESTAT_ADD(dma_writeq_full); | |
8432 | ESTAT_ADD(dma_write_prioq_full); | |
8433 | ESTAT_ADD(rxbds_empty); | |
8434 | ESTAT_ADD(rx_discards); | |
8435 | ESTAT_ADD(rx_errors); | |
8436 | ESTAT_ADD(rx_threshold_hit); | |
8437 | ||
8438 | ESTAT_ADD(dma_readq_full); | |
8439 | ESTAT_ADD(dma_read_prioq_full); | |
8440 | ESTAT_ADD(tx_comp_queue_full); | |
8441 | ||
8442 | ESTAT_ADD(ring_set_send_prod_index); | |
8443 | ESTAT_ADD(ring_status_update); | |
8444 | ESTAT_ADD(nic_irqs); | |
8445 | ESTAT_ADD(nic_avoided_irqs); | |
8446 | ESTAT_ADD(nic_tx_threshold_hit); | |
8447 | ||
8448 | return estats; | |
8449 | } | |
8450 | ||
8451 | static struct net_device_stats *tg3_get_stats(struct net_device *dev) | |
8452 | { | |
8453 | struct tg3 *tp = netdev_priv(dev); | |
8454 | struct net_device_stats *stats = &tp->net_stats; | |
8455 | struct net_device_stats *old_stats = &tp->net_stats_prev; | |
8456 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
8457 | ||
8458 | if (!hw_stats) | |
8459 | return old_stats; | |
8460 | ||
8461 | stats->rx_packets = old_stats->rx_packets + | |
8462 | get_stat64(&hw_stats->rx_ucast_packets) + | |
8463 | get_stat64(&hw_stats->rx_mcast_packets) + | |
8464 | get_stat64(&hw_stats->rx_bcast_packets); | |
6aa20a22 | 8465 | |
1da177e4 LT |
8466 | stats->tx_packets = old_stats->tx_packets + |
8467 | get_stat64(&hw_stats->tx_ucast_packets) + | |
8468 | get_stat64(&hw_stats->tx_mcast_packets) + | |
8469 | get_stat64(&hw_stats->tx_bcast_packets); | |
8470 | ||
8471 | stats->rx_bytes = old_stats->rx_bytes + | |
8472 | get_stat64(&hw_stats->rx_octets); | |
8473 | stats->tx_bytes = old_stats->tx_bytes + | |
8474 | get_stat64(&hw_stats->tx_octets); | |
8475 | ||
8476 | stats->rx_errors = old_stats->rx_errors + | |
4f63b877 | 8477 | get_stat64(&hw_stats->rx_errors); |
1da177e4 LT |
8478 | stats->tx_errors = old_stats->tx_errors + |
8479 | get_stat64(&hw_stats->tx_errors) + | |
8480 | get_stat64(&hw_stats->tx_mac_errors) + | |
8481 | get_stat64(&hw_stats->tx_carrier_sense_errors) + | |
8482 | get_stat64(&hw_stats->tx_discards); | |
8483 | ||
8484 | stats->multicast = old_stats->multicast + | |
8485 | get_stat64(&hw_stats->rx_mcast_packets); | |
8486 | stats->collisions = old_stats->collisions + | |
8487 | get_stat64(&hw_stats->tx_collisions); | |
8488 | ||
8489 | stats->rx_length_errors = old_stats->rx_length_errors + | |
8490 | get_stat64(&hw_stats->rx_frame_too_long_errors) + | |
8491 | get_stat64(&hw_stats->rx_undersize_packets); | |
8492 | ||
8493 | stats->rx_over_errors = old_stats->rx_over_errors + | |
8494 | get_stat64(&hw_stats->rxbds_empty); | |
8495 | stats->rx_frame_errors = old_stats->rx_frame_errors + | |
8496 | get_stat64(&hw_stats->rx_align_errors); | |
8497 | stats->tx_aborted_errors = old_stats->tx_aborted_errors + | |
8498 | get_stat64(&hw_stats->tx_discards); | |
8499 | stats->tx_carrier_errors = old_stats->tx_carrier_errors + | |
8500 | get_stat64(&hw_stats->tx_carrier_sense_errors); | |
8501 | ||
8502 | stats->rx_crc_errors = old_stats->rx_crc_errors + | |
8503 | calc_crc_errors(tp); | |
8504 | ||
4f63b877 JL |
8505 | stats->rx_missed_errors = old_stats->rx_missed_errors + |
8506 | get_stat64(&hw_stats->rx_discards); | |
8507 | ||
1da177e4 LT |
8508 | return stats; |
8509 | } | |
8510 | ||
8511 | static inline u32 calc_crc(unsigned char *buf, int len) | |
8512 | { | |
8513 | u32 reg; | |
8514 | u32 tmp; | |
8515 | int j, k; | |
8516 | ||
8517 | reg = 0xffffffff; | |
8518 | ||
8519 | for (j = 0; j < len; j++) { | |
8520 | reg ^= buf[j]; | |
8521 | ||
8522 | for (k = 0; k < 8; k++) { | |
8523 | tmp = reg & 0x01; | |
8524 | ||
8525 | reg >>= 1; | |
8526 | ||
8527 | if (tmp) { | |
8528 | reg ^= 0xedb88320; | |
8529 | } | |
8530 | } | |
8531 | } | |
8532 | ||
8533 | return ~reg; | |
8534 | } | |
8535 | ||
8536 | static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) | |
8537 | { | |
8538 | /* accept or reject all multicast frames */ | |
8539 | tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0); | |
8540 | tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0); | |
8541 | tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0); | |
8542 | tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0); | |
8543 | } | |
8544 | ||
8545 | static void __tg3_set_rx_mode(struct net_device *dev) | |
8546 | { | |
8547 | struct tg3 *tp = netdev_priv(dev); | |
8548 | u32 rx_mode; | |
8549 | ||
8550 | rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | | |
8551 | RX_MODE_KEEP_VLAN_TAG); | |
8552 | ||
8553 | /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG | |
8554 | * flag clear. | |
8555 | */ | |
8556 | #if TG3_VLAN_TAG_USED | |
8557 | if (!tp->vlgrp && | |
8558 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
8559 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; | |
8560 | #else | |
8561 | /* By definition, VLAN is disabled always in this | |
8562 | * case. | |
8563 | */ | |
8564 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
8565 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; | |
8566 | #endif | |
8567 | ||
8568 | if (dev->flags & IFF_PROMISC) { | |
8569 | /* Promiscuous mode. */ | |
8570 | rx_mode |= RX_MODE_PROMISC; | |
8571 | } else if (dev->flags & IFF_ALLMULTI) { | |
8572 | /* Accept all multicast. */ | |
8573 | tg3_set_multi (tp, 1); | |
8574 | } else if (dev->mc_count < 1) { | |
8575 | /* Reject all multicast. */ | |
8576 | tg3_set_multi (tp, 0); | |
8577 | } else { | |
8578 | /* Accept one or more multicast(s). */ | |
8579 | struct dev_mc_list *mclist; | |
8580 | unsigned int i; | |
8581 | u32 mc_filter[4] = { 0, }; | |
8582 | u32 regidx; | |
8583 | u32 bit; | |
8584 | u32 crc; | |
8585 | ||
8586 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | |
8587 | i++, mclist = mclist->next) { | |
8588 | ||
8589 | crc = calc_crc (mclist->dmi_addr, ETH_ALEN); | |
8590 | bit = ~crc & 0x7f; | |
8591 | regidx = (bit & 0x60) >> 5; | |
8592 | bit &= 0x1f; | |
8593 | mc_filter[regidx] |= (1 << bit); | |
8594 | } | |
8595 | ||
8596 | tw32(MAC_HASH_REG_0, mc_filter[0]); | |
8597 | tw32(MAC_HASH_REG_1, mc_filter[1]); | |
8598 | tw32(MAC_HASH_REG_2, mc_filter[2]); | |
8599 | tw32(MAC_HASH_REG_3, mc_filter[3]); | |
8600 | } | |
8601 | ||
8602 | if (rx_mode != tp->rx_mode) { | |
8603 | tp->rx_mode = rx_mode; | |
8604 | tw32_f(MAC_RX_MODE, rx_mode); | |
8605 | udelay(10); | |
8606 | } | |
8607 | } | |
8608 | ||
8609 | static void tg3_set_rx_mode(struct net_device *dev) | |
8610 | { | |
8611 | struct tg3 *tp = netdev_priv(dev); | |
8612 | ||
e75f7c90 MC |
8613 | if (!netif_running(dev)) |
8614 | return; | |
8615 | ||
f47c11ee | 8616 | tg3_full_lock(tp, 0); |
1da177e4 | 8617 | __tg3_set_rx_mode(dev); |
f47c11ee | 8618 | tg3_full_unlock(tp); |
1da177e4 LT |
8619 | } |
8620 | ||
8621 | #define TG3_REGDUMP_LEN (32 * 1024) | |
8622 | ||
8623 | static int tg3_get_regs_len(struct net_device *dev) | |
8624 | { | |
8625 | return TG3_REGDUMP_LEN; | |
8626 | } | |
8627 | ||
8628 | static void tg3_get_regs(struct net_device *dev, | |
8629 | struct ethtool_regs *regs, void *_p) | |
8630 | { | |
8631 | u32 *p = _p; | |
8632 | struct tg3 *tp = netdev_priv(dev); | |
8633 | u8 *orig_p = _p; | |
8634 | int i; | |
8635 | ||
8636 | regs->version = 0; | |
8637 | ||
8638 | memset(p, 0, TG3_REGDUMP_LEN); | |
8639 | ||
bc1c7567 MC |
8640 | if (tp->link_config.phy_is_low_power) |
8641 | return; | |
8642 | ||
f47c11ee | 8643 | tg3_full_lock(tp, 0); |
1da177e4 LT |
8644 | |
8645 | #define __GET_REG32(reg) (*(p)++ = tr32(reg)) | |
8646 | #define GET_REG32_LOOP(base,len) \ | |
8647 | do { p = (u32 *)(orig_p + (base)); \ | |
8648 | for (i = 0; i < len; i += 4) \ | |
8649 | __GET_REG32((base) + i); \ | |
8650 | } while (0) | |
8651 | #define GET_REG32_1(reg) \ | |
8652 | do { p = (u32 *)(orig_p + (reg)); \ | |
8653 | __GET_REG32((reg)); \ | |
8654 | } while (0) | |
8655 | ||
8656 | GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0); | |
8657 | GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200); | |
8658 | GET_REG32_LOOP(MAC_MODE, 0x4f0); | |
8659 | GET_REG32_LOOP(SNDDATAI_MODE, 0xe0); | |
8660 | GET_REG32_1(SNDDATAC_MODE); | |
8661 | GET_REG32_LOOP(SNDBDS_MODE, 0x80); | |
8662 | GET_REG32_LOOP(SNDBDI_MODE, 0x48); | |
8663 | GET_REG32_1(SNDBDC_MODE); | |
8664 | GET_REG32_LOOP(RCVLPC_MODE, 0x20); | |
8665 | GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c); | |
8666 | GET_REG32_LOOP(RCVDBDI_MODE, 0x0c); | |
8667 | GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c); | |
8668 | GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44); | |
8669 | GET_REG32_1(RCVDCC_MODE); | |
8670 | GET_REG32_LOOP(RCVBDI_MODE, 0x20); | |
8671 | GET_REG32_LOOP(RCVCC_MODE, 0x14); | |
8672 | GET_REG32_LOOP(RCVLSC_MODE, 0x08); | |
8673 | GET_REG32_1(MBFREE_MODE); | |
8674 | GET_REG32_LOOP(HOSTCC_MODE, 0x100); | |
8675 | GET_REG32_LOOP(MEMARB_MODE, 0x10); | |
8676 | GET_REG32_LOOP(BUFMGR_MODE, 0x58); | |
8677 | GET_REG32_LOOP(RDMAC_MODE, 0x08); | |
8678 | GET_REG32_LOOP(WDMAC_MODE, 0x08); | |
091465d7 CE |
8679 | GET_REG32_1(RX_CPU_MODE); |
8680 | GET_REG32_1(RX_CPU_STATE); | |
8681 | GET_REG32_1(RX_CPU_PGMCTR); | |
8682 | GET_REG32_1(RX_CPU_HWBKPT); | |
8683 | GET_REG32_1(TX_CPU_MODE); | |
8684 | GET_REG32_1(TX_CPU_STATE); | |
8685 | GET_REG32_1(TX_CPU_PGMCTR); | |
1da177e4 LT |
8686 | GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110); |
8687 | GET_REG32_LOOP(FTQ_RESET, 0x120); | |
8688 | GET_REG32_LOOP(MSGINT_MODE, 0x0c); | |
8689 | GET_REG32_1(DMAC_MODE); | |
8690 | GET_REG32_LOOP(GRC_MODE, 0x4c); | |
8691 | if (tp->tg3_flags & TG3_FLAG_NVRAM) | |
8692 | GET_REG32_LOOP(NVRAM_CMD, 0x24); | |
8693 | ||
8694 | #undef __GET_REG32 | |
8695 | #undef GET_REG32_LOOP | |
8696 | #undef GET_REG32_1 | |
8697 | ||
f47c11ee | 8698 | tg3_full_unlock(tp); |
1da177e4 LT |
8699 | } |
8700 | ||
8701 | static int tg3_get_eeprom_len(struct net_device *dev) | |
8702 | { | |
8703 | struct tg3 *tp = netdev_priv(dev); | |
8704 | ||
8705 | return tp->nvram_size; | |
8706 | } | |
8707 | ||
1da177e4 LT |
8708 | static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) |
8709 | { | |
8710 | struct tg3 *tp = netdev_priv(dev); | |
8711 | int ret; | |
8712 | u8 *pd; | |
b9fc7dc5 | 8713 | u32 i, offset, len, b_offset, b_count; |
a9dc529d | 8714 | __be32 val; |
1da177e4 | 8715 | |
df259d8c MC |
8716 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) |
8717 | return -EINVAL; | |
8718 | ||
bc1c7567 MC |
8719 | if (tp->link_config.phy_is_low_power) |
8720 | return -EAGAIN; | |
8721 | ||
1da177e4 LT |
8722 | offset = eeprom->offset; |
8723 | len = eeprom->len; | |
8724 | eeprom->len = 0; | |
8725 | ||
8726 | eeprom->magic = TG3_EEPROM_MAGIC; | |
8727 | ||
8728 | if (offset & 3) { | |
8729 | /* adjustments to start on required 4 byte boundary */ | |
8730 | b_offset = offset & 3; | |
8731 | b_count = 4 - b_offset; | |
8732 | if (b_count > len) { | |
8733 | /* i.e. offset=1 len=2 */ | |
8734 | b_count = len; | |
8735 | } | |
a9dc529d | 8736 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); |
1da177e4 LT |
8737 | if (ret) |
8738 | return ret; | |
1da177e4 LT |
8739 | memcpy(data, ((char*)&val) + b_offset, b_count); |
8740 | len -= b_count; | |
8741 | offset += b_count; | |
8742 | eeprom->len += b_count; | |
8743 | } | |
8744 | ||
8745 | /* read bytes upto the last 4 byte boundary */ | |
8746 | pd = &data[eeprom->len]; | |
8747 | for (i = 0; i < (len - (len & 3)); i += 4) { | |
a9dc529d | 8748 | ret = tg3_nvram_read_be32(tp, offset + i, &val); |
1da177e4 LT |
8749 | if (ret) { |
8750 | eeprom->len += i; | |
8751 | return ret; | |
8752 | } | |
1da177e4 LT |
8753 | memcpy(pd + i, &val, 4); |
8754 | } | |
8755 | eeprom->len += i; | |
8756 | ||
8757 | if (len & 3) { | |
8758 | /* read last bytes not ending on 4 byte boundary */ | |
8759 | pd = &data[eeprom->len]; | |
8760 | b_count = len & 3; | |
8761 | b_offset = offset + len - b_count; | |
a9dc529d | 8762 | ret = tg3_nvram_read_be32(tp, b_offset, &val); |
1da177e4 LT |
8763 | if (ret) |
8764 | return ret; | |
b9fc7dc5 | 8765 | memcpy(pd, &val, b_count); |
1da177e4 LT |
8766 | eeprom->len += b_count; |
8767 | } | |
8768 | return 0; | |
8769 | } | |
8770 | ||
6aa20a22 | 8771 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf); |
1da177e4 LT |
8772 | |
8773 | static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) | |
8774 | { | |
8775 | struct tg3 *tp = netdev_priv(dev); | |
8776 | int ret; | |
b9fc7dc5 | 8777 | u32 offset, len, b_offset, odd_len; |
1da177e4 | 8778 | u8 *buf; |
a9dc529d | 8779 | __be32 start, end; |
1da177e4 | 8780 | |
bc1c7567 MC |
8781 | if (tp->link_config.phy_is_low_power) |
8782 | return -EAGAIN; | |
8783 | ||
df259d8c MC |
8784 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || |
8785 | eeprom->magic != TG3_EEPROM_MAGIC) | |
1da177e4 LT |
8786 | return -EINVAL; |
8787 | ||
8788 | offset = eeprom->offset; | |
8789 | len = eeprom->len; | |
8790 | ||
8791 | if ((b_offset = (offset & 3))) { | |
8792 | /* adjustments to start on required 4 byte boundary */ | |
a9dc529d | 8793 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); |
1da177e4 LT |
8794 | if (ret) |
8795 | return ret; | |
1da177e4 LT |
8796 | len += b_offset; |
8797 | offset &= ~3; | |
1c8594b4 MC |
8798 | if (len < 4) |
8799 | len = 4; | |
1da177e4 LT |
8800 | } |
8801 | ||
8802 | odd_len = 0; | |
1c8594b4 | 8803 | if (len & 3) { |
1da177e4 LT |
8804 | /* adjustments to end on required 4 byte boundary */ |
8805 | odd_len = 1; | |
8806 | len = (len + 3) & ~3; | |
a9dc529d | 8807 | ret = tg3_nvram_read_be32(tp, offset+len-4, &end); |
1da177e4 LT |
8808 | if (ret) |
8809 | return ret; | |
1da177e4 LT |
8810 | } |
8811 | ||
8812 | buf = data; | |
8813 | if (b_offset || odd_len) { | |
8814 | buf = kmalloc(len, GFP_KERNEL); | |
ab0049b4 | 8815 | if (!buf) |
1da177e4 LT |
8816 | return -ENOMEM; |
8817 | if (b_offset) | |
8818 | memcpy(buf, &start, 4); | |
8819 | if (odd_len) | |
8820 | memcpy(buf+len-4, &end, 4); | |
8821 | memcpy(buf + b_offset, data, eeprom->len); | |
8822 | } | |
8823 | ||
8824 | ret = tg3_nvram_write_block(tp, offset, len, buf); | |
8825 | ||
8826 | if (buf != data) | |
8827 | kfree(buf); | |
8828 | ||
8829 | return ret; | |
8830 | } | |
8831 | ||
8832 | static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
8833 | { | |
b02fd9e3 MC |
8834 | struct tg3 *tp = netdev_priv(dev); |
8835 | ||
8836 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { | |
8837 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
8838 | return -EAGAIN; | |
298cf9be | 8839 | return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd); |
b02fd9e3 | 8840 | } |
6aa20a22 | 8841 | |
1da177e4 LT |
8842 | cmd->supported = (SUPPORTED_Autoneg); |
8843 | ||
8844 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) | |
8845 | cmd->supported |= (SUPPORTED_1000baseT_Half | | |
8846 | SUPPORTED_1000baseT_Full); | |
8847 | ||
ef348144 | 8848 | if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) { |
1da177e4 LT |
8849 | cmd->supported |= (SUPPORTED_100baseT_Half | |
8850 | SUPPORTED_100baseT_Full | | |
8851 | SUPPORTED_10baseT_Half | | |
8852 | SUPPORTED_10baseT_Full | | |
3bebab59 | 8853 | SUPPORTED_TP); |
ef348144 KK |
8854 | cmd->port = PORT_TP; |
8855 | } else { | |
1da177e4 | 8856 | cmd->supported |= SUPPORTED_FIBRE; |
ef348144 KK |
8857 | cmd->port = PORT_FIBRE; |
8858 | } | |
6aa20a22 | 8859 | |
1da177e4 LT |
8860 | cmd->advertising = tp->link_config.advertising; |
8861 | if (netif_running(dev)) { | |
8862 | cmd->speed = tp->link_config.active_speed; | |
8863 | cmd->duplex = tp->link_config.active_duplex; | |
8864 | } | |
1da177e4 | 8865 | cmd->phy_address = PHY_ADDR; |
7e5856bd | 8866 | cmd->transceiver = XCVR_INTERNAL; |
1da177e4 LT |
8867 | cmd->autoneg = tp->link_config.autoneg; |
8868 | cmd->maxtxpkt = 0; | |
8869 | cmd->maxrxpkt = 0; | |
8870 | return 0; | |
8871 | } | |
6aa20a22 | 8872 | |
1da177e4 LT |
8873 | static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
8874 | { | |
8875 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 8876 | |
b02fd9e3 MC |
8877 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
8878 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
8879 | return -EAGAIN; | |
298cf9be | 8880 | return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd); |
b02fd9e3 MC |
8881 | } |
8882 | ||
7e5856bd MC |
8883 | if (cmd->autoneg != AUTONEG_ENABLE && |
8884 | cmd->autoneg != AUTONEG_DISABLE) | |
37ff238d | 8885 | return -EINVAL; |
7e5856bd MC |
8886 | |
8887 | if (cmd->autoneg == AUTONEG_DISABLE && | |
8888 | cmd->duplex != DUPLEX_FULL && | |
8889 | cmd->duplex != DUPLEX_HALF) | |
37ff238d | 8890 | return -EINVAL; |
1da177e4 | 8891 | |
7e5856bd MC |
8892 | if (cmd->autoneg == AUTONEG_ENABLE) { |
8893 | u32 mask = ADVERTISED_Autoneg | | |
8894 | ADVERTISED_Pause | | |
8895 | ADVERTISED_Asym_Pause; | |
8896 | ||
8897 | if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY)) | |
8898 | mask |= ADVERTISED_1000baseT_Half | | |
8899 | ADVERTISED_1000baseT_Full; | |
8900 | ||
8901 | if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) | |
8902 | mask |= ADVERTISED_100baseT_Half | | |
8903 | ADVERTISED_100baseT_Full | | |
8904 | ADVERTISED_10baseT_Half | | |
8905 | ADVERTISED_10baseT_Full | | |
8906 | ADVERTISED_TP; | |
8907 | else | |
8908 | mask |= ADVERTISED_FIBRE; | |
8909 | ||
8910 | if (cmd->advertising & ~mask) | |
8911 | return -EINVAL; | |
8912 | ||
8913 | mask &= (ADVERTISED_1000baseT_Half | | |
8914 | ADVERTISED_1000baseT_Full | | |
8915 | ADVERTISED_100baseT_Half | | |
8916 | ADVERTISED_100baseT_Full | | |
8917 | ADVERTISED_10baseT_Half | | |
8918 | ADVERTISED_10baseT_Full); | |
8919 | ||
8920 | cmd->advertising &= mask; | |
8921 | } else { | |
8922 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) { | |
8923 | if (cmd->speed != SPEED_1000) | |
8924 | return -EINVAL; | |
8925 | ||
8926 | if (cmd->duplex != DUPLEX_FULL) | |
8927 | return -EINVAL; | |
8928 | } else { | |
8929 | if (cmd->speed != SPEED_100 && | |
8930 | cmd->speed != SPEED_10) | |
8931 | return -EINVAL; | |
8932 | } | |
8933 | } | |
8934 | ||
f47c11ee | 8935 | tg3_full_lock(tp, 0); |
1da177e4 LT |
8936 | |
8937 | tp->link_config.autoneg = cmd->autoneg; | |
8938 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
405d8e5c AG |
8939 | tp->link_config.advertising = (cmd->advertising | |
8940 | ADVERTISED_Autoneg); | |
1da177e4 LT |
8941 | tp->link_config.speed = SPEED_INVALID; |
8942 | tp->link_config.duplex = DUPLEX_INVALID; | |
8943 | } else { | |
8944 | tp->link_config.advertising = 0; | |
8945 | tp->link_config.speed = cmd->speed; | |
8946 | tp->link_config.duplex = cmd->duplex; | |
b02fd9e3 | 8947 | } |
6aa20a22 | 8948 | |
24fcad6b MC |
8949 | tp->link_config.orig_speed = tp->link_config.speed; |
8950 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
8951 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
8952 | ||
1da177e4 LT |
8953 | if (netif_running(dev)) |
8954 | tg3_setup_phy(tp, 1); | |
8955 | ||
f47c11ee | 8956 | tg3_full_unlock(tp); |
6aa20a22 | 8957 | |
1da177e4 LT |
8958 | return 0; |
8959 | } | |
6aa20a22 | 8960 | |
1da177e4 LT |
8961 | static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
8962 | { | |
8963 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 8964 | |
1da177e4 LT |
8965 | strcpy(info->driver, DRV_MODULE_NAME); |
8966 | strcpy(info->version, DRV_MODULE_VERSION); | |
c4e6575c | 8967 | strcpy(info->fw_version, tp->fw_ver); |
1da177e4 LT |
8968 | strcpy(info->bus_info, pci_name(tp->pdev)); |
8969 | } | |
6aa20a22 | 8970 | |
1da177e4 LT |
8971 | static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
8972 | { | |
8973 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 8974 | |
12dac075 RW |
8975 | if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) && |
8976 | device_can_wakeup(&tp->pdev->dev)) | |
a85feb8c GZ |
8977 | wol->supported = WAKE_MAGIC; |
8978 | else | |
8979 | wol->supported = 0; | |
1da177e4 | 8980 | wol->wolopts = 0; |
05ac4cb7 MC |
8981 | if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) && |
8982 | device_can_wakeup(&tp->pdev->dev)) | |
1da177e4 LT |
8983 | wol->wolopts = WAKE_MAGIC; |
8984 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
8985 | } | |
6aa20a22 | 8986 | |
1da177e4 LT |
8987 | static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
8988 | { | |
8989 | struct tg3 *tp = netdev_priv(dev); | |
12dac075 | 8990 | struct device *dp = &tp->pdev->dev; |
6aa20a22 | 8991 | |
1da177e4 LT |
8992 | if (wol->wolopts & ~WAKE_MAGIC) |
8993 | return -EINVAL; | |
8994 | if ((wol->wolopts & WAKE_MAGIC) && | |
12dac075 | 8995 | !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp))) |
1da177e4 | 8996 | return -EINVAL; |
6aa20a22 | 8997 | |
f47c11ee | 8998 | spin_lock_bh(&tp->lock); |
12dac075 | 8999 | if (wol->wolopts & WAKE_MAGIC) { |
1da177e4 | 9000 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; |
12dac075 RW |
9001 | device_set_wakeup_enable(dp, true); |
9002 | } else { | |
1da177e4 | 9003 | tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE; |
12dac075 RW |
9004 | device_set_wakeup_enable(dp, false); |
9005 | } | |
f47c11ee | 9006 | spin_unlock_bh(&tp->lock); |
6aa20a22 | 9007 | |
1da177e4 LT |
9008 | return 0; |
9009 | } | |
6aa20a22 | 9010 | |
1da177e4 LT |
9011 | static u32 tg3_get_msglevel(struct net_device *dev) |
9012 | { | |
9013 | struct tg3 *tp = netdev_priv(dev); | |
9014 | return tp->msg_enable; | |
9015 | } | |
6aa20a22 | 9016 | |
1da177e4 LT |
9017 | static void tg3_set_msglevel(struct net_device *dev, u32 value) |
9018 | { | |
9019 | struct tg3 *tp = netdev_priv(dev); | |
9020 | tp->msg_enable = value; | |
9021 | } | |
6aa20a22 | 9022 | |
1da177e4 LT |
9023 | static int tg3_set_tso(struct net_device *dev, u32 value) |
9024 | { | |
9025 | struct tg3 *tp = netdev_priv(dev); | |
9026 | ||
9027 | if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
9028 | if (value) | |
9029 | return -EINVAL; | |
9030 | return 0; | |
9031 | } | |
027455ad MC |
9032 | if ((dev->features & NETIF_F_IPV6_CSUM) && |
9033 | (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) { | |
9936bcf6 | 9034 | if (value) { |
b0026624 | 9035 | dev->features |= NETIF_F_TSO6; |
57e6983c MC |
9036 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
9037 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
9038 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
321d32a0 MC |
9039 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
9040 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
9936bcf6 MC |
9041 | dev->features |= NETIF_F_TSO_ECN; |
9042 | } else | |
9043 | dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN); | |
b0026624 | 9044 | } |
1da177e4 LT |
9045 | return ethtool_op_set_tso(dev, value); |
9046 | } | |
6aa20a22 | 9047 | |
1da177e4 LT |
9048 | static int tg3_nway_reset(struct net_device *dev) |
9049 | { | |
9050 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 | 9051 | int r; |
6aa20a22 | 9052 | |
1da177e4 LT |
9053 | if (!netif_running(dev)) |
9054 | return -EAGAIN; | |
9055 | ||
c94e3941 MC |
9056 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) |
9057 | return -EINVAL; | |
9058 | ||
b02fd9e3 MC |
9059 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
9060 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
9061 | return -EAGAIN; | |
298cf9be | 9062 | r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]); |
b02fd9e3 MC |
9063 | } else { |
9064 | u32 bmcr; | |
9065 | ||
9066 | spin_lock_bh(&tp->lock); | |
9067 | r = -EINVAL; | |
9068 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
9069 | if (!tg3_readphy(tp, MII_BMCR, &bmcr) && | |
9070 | ((bmcr & BMCR_ANENABLE) || | |
9071 | (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) { | |
9072 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | | |
9073 | BMCR_ANENABLE); | |
9074 | r = 0; | |
9075 | } | |
9076 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 9077 | } |
6aa20a22 | 9078 | |
1da177e4 LT |
9079 | return r; |
9080 | } | |
6aa20a22 | 9081 | |
1da177e4 LT |
9082 | static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
9083 | { | |
9084 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 9085 | |
1da177e4 LT |
9086 | ering->rx_max_pending = TG3_RX_RING_SIZE - 1; |
9087 | ering->rx_mini_max_pending = 0; | |
4f81c32b MC |
9088 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) |
9089 | ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1; | |
9090 | else | |
9091 | ering->rx_jumbo_max_pending = 0; | |
9092 | ||
9093 | ering->tx_max_pending = TG3_TX_RING_SIZE - 1; | |
1da177e4 LT |
9094 | |
9095 | ering->rx_pending = tp->rx_pending; | |
9096 | ering->rx_mini_pending = 0; | |
4f81c32b MC |
9097 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) |
9098 | ering->rx_jumbo_pending = tp->rx_jumbo_pending; | |
9099 | else | |
9100 | ering->rx_jumbo_pending = 0; | |
9101 | ||
f3f3f27e | 9102 | ering->tx_pending = tp->napi[0].tx_pending; |
1da177e4 | 9103 | } |
6aa20a22 | 9104 | |
1da177e4 LT |
9105 | static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
9106 | { | |
9107 | struct tg3 *tp = netdev_priv(dev); | |
b9ec6c1b | 9108 | int irq_sync = 0, err = 0; |
6aa20a22 | 9109 | |
1da177e4 LT |
9110 | if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) || |
9111 | (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) || | |
bc3a9254 MC |
9112 | (ering->tx_pending > TG3_TX_RING_SIZE - 1) || |
9113 | (ering->tx_pending <= MAX_SKB_FRAGS) || | |
7f62ad5d | 9114 | ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) && |
bc3a9254 | 9115 | (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) |
1da177e4 | 9116 | return -EINVAL; |
6aa20a22 | 9117 | |
bbe832c0 | 9118 | if (netif_running(dev)) { |
b02fd9e3 | 9119 | tg3_phy_stop(tp); |
1da177e4 | 9120 | tg3_netif_stop(tp); |
bbe832c0 MC |
9121 | irq_sync = 1; |
9122 | } | |
1da177e4 | 9123 | |
bbe832c0 | 9124 | tg3_full_lock(tp, irq_sync); |
6aa20a22 | 9125 | |
1da177e4 LT |
9126 | tp->rx_pending = ering->rx_pending; |
9127 | ||
9128 | if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) && | |
9129 | tp->rx_pending > 63) | |
9130 | tp->rx_pending = 63; | |
9131 | tp->rx_jumbo_pending = ering->rx_jumbo_pending; | |
f3f3f27e | 9132 | tp->napi[0].tx_pending = ering->tx_pending; |
1da177e4 LT |
9133 | |
9134 | if (netif_running(dev)) { | |
944d980e | 9135 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
b9ec6c1b MC |
9136 | err = tg3_restart_hw(tp, 1); |
9137 | if (!err) | |
9138 | tg3_netif_start(tp); | |
1da177e4 LT |
9139 | } |
9140 | ||
f47c11ee | 9141 | tg3_full_unlock(tp); |
6aa20a22 | 9142 | |
b02fd9e3 MC |
9143 | if (irq_sync && !err) |
9144 | tg3_phy_start(tp); | |
9145 | ||
b9ec6c1b | 9146 | return err; |
1da177e4 | 9147 | } |
6aa20a22 | 9148 | |
1da177e4 LT |
9149 | static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
9150 | { | |
9151 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 9152 | |
1da177e4 | 9153 | epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0; |
8d018621 | 9154 | |
e18ce346 | 9155 | if (tp->link_config.active_flowctrl & FLOW_CTRL_RX) |
8d018621 MC |
9156 | epause->rx_pause = 1; |
9157 | else | |
9158 | epause->rx_pause = 0; | |
9159 | ||
e18ce346 | 9160 | if (tp->link_config.active_flowctrl & FLOW_CTRL_TX) |
8d018621 MC |
9161 | epause->tx_pause = 1; |
9162 | else | |
9163 | epause->tx_pause = 0; | |
1da177e4 | 9164 | } |
6aa20a22 | 9165 | |
1da177e4 LT |
9166 | static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
9167 | { | |
9168 | struct tg3 *tp = netdev_priv(dev); | |
b02fd9e3 | 9169 | int err = 0; |
6aa20a22 | 9170 | |
b02fd9e3 MC |
9171 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
9172 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
9173 | return -EAGAIN; | |
1da177e4 | 9174 | |
b02fd9e3 MC |
9175 | if (epause->autoneg) { |
9176 | u32 newadv; | |
9177 | struct phy_device *phydev; | |
f47c11ee | 9178 | |
298cf9be | 9179 | phydev = tp->mdio_bus->phy_map[PHY_ADDR]; |
1da177e4 | 9180 | |
b02fd9e3 MC |
9181 | if (epause->rx_pause) { |
9182 | if (epause->tx_pause) | |
9183 | newadv = ADVERTISED_Pause; | |
9184 | else | |
9185 | newadv = ADVERTISED_Pause | | |
9186 | ADVERTISED_Asym_Pause; | |
9187 | } else if (epause->tx_pause) { | |
9188 | newadv = ADVERTISED_Asym_Pause; | |
9189 | } else | |
9190 | newadv = 0; | |
9191 | ||
9192 | if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) { | |
9193 | u32 oldadv = phydev->advertising & | |
9194 | (ADVERTISED_Pause | | |
9195 | ADVERTISED_Asym_Pause); | |
9196 | if (oldadv != newadv) { | |
9197 | phydev->advertising &= | |
9198 | ~(ADVERTISED_Pause | | |
9199 | ADVERTISED_Asym_Pause); | |
9200 | phydev->advertising |= newadv; | |
9201 | err = phy_start_aneg(phydev); | |
9202 | } | |
9203 | } else { | |
9204 | tp->link_config.advertising &= | |
9205 | ~(ADVERTISED_Pause | | |
9206 | ADVERTISED_Asym_Pause); | |
9207 | tp->link_config.advertising |= newadv; | |
9208 | } | |
9209 | } else { | |
9210 | if (epause->rx_pause) | |
e18ce346 | 9211 | tp->link_config.flowctrl |= FLOW_CTRL_RX; |
b02fd9e3 | 9212 | else |
e18ce346 | 9213 | tp->link_config.flowctrl &= ~FLOW_CTRL_RX; |
f47c11ee | 9214 | |
b02fd9e3 | 9215 | if (epause->tx_pause) |
e18ce346 | 9216 | tp->link_config.flowctrl |= FLOW_CTRL_TX; |
b02fd9e3 | 9217 | else |
e18ce346 | 9218 | tp->link_config.flowctrl &= ~FLOW_CTRL_TX; |
b02fd9e3 MC |
9219 | |
9220 | if (netif_running(dev)) | |
9221 | tg3_setup_flow_control(tp, 0, 0); | |
9222 | } | |
9223 | } else { | |
9224 | int irq_sync = 0; | |
9225 | ||
9226 | if (netif_running(dev)) { | |
9227 | tg3_netif_stop(tp); | |
9228 | irq_sync = 1; | |
9229 | } | |
9230 | ||
9231 | tg3_full_lock(tp, irq_sync); | |
9232 | ||
9233 | if (epause->autoneg) | |
9234 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | |
9235 | else | |
9236 | tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG; | |
9237 | if (epause->rx_pause) | |
e18ce346 | 9238 | tp->link_config.flowctrl |= FLOW_CTRL_RX; |
b02fd9e3 | 9239 | else |
e18ce346 | 9240 | tp->link_config.flowctrl &= ~FLOW_CTRL_RX; |
b02fd9e3 | 9241 | if (epause->tx_pause) |
e18ce346 | 9242 | tp->link_config.flowctrl |= FLOW_CTRL_TX; |
b02fd9e3 | 9243 | else |
e18ce346 | 9244 | tp->link_config.flowctrl &= ~FLOW_CTRL_TX; |
b02fd9e3 MC |
9245 | |
9246 | if (netif_running(dev)) { | |
9247 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
9248 | err = tg3_restart_hw(tp, 1); | |
9249 | if (!err) | |
9250 | tg3_netif_start(tp); | |
9251 | } | |
9252 | ||
9253 | tg3_full_unlock(tp); | |
9254 | } | |
6aa20a22 | 9255 | |
b9ec6c1b | 9256 | return err; |
1da177e4 | 9257 | } |
6aa20a22 | 9258 | |
1da177e4 LT |
9259 | static u32 tg3_get_rx_csum(struct net_device *dev) |
9260 | { | |
9261 | struct tg3 *tp = netdev_priv(dev); | |
9262 | return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0; | |
9263 | } | |
6aa20a22 | 9264 | |
1da177e4 LT |
9265 | static int tg3_set_rx_csum(struct net_device *dev, u32 data) |
9266 | { | |
9267 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 9268 | |
1da177e4 LT |
9269 | if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) { |
9270 | if (data != 0) | |
9271 | return -EINVAL; | |
9272 | return 0; | |
9273 | } | |
6aa20a22 | 9274 | |
f47c11ee | 9275 | spin_lock_bh(&tp->lock); |
1da177e4 LT |
9276 | if (data) |
9277 | tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS; | |
9278 | else | |
9279 | tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS; | |
f47c11ee | 9280 | spin_unlock_bh(&tp->lock); |
6aa20a22 | 9281 | |
1da177e4 LT |
9282 | return 0; |
9283 | } | |
6aa20a22 | 9284 | |
1da177e4 LT |
9285 | static int tg3_set_tx_csum(struct net_device *dev, u32 data) |
9286 | { | |
9287 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 9288 | |
1da177e4 LT |
9289 | if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) { |
9290 | if (data != 0) | |
9291 | return -EINVAL; | |
9292 | return 0; | |
9293 | } | |
6aa20a22 | 9294 | |
321d32a0 | 9295 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
6460d948 | 9296 | ethtool_op_set_tx_ipv6_csum(dev, data); |
1da177e4 | 9297 | else |
9c27dbdf | 9298 | ethtool_op_set_tx_csum(dev, data); |
1da177e4 LT |
9299 | |
9300 | return 0; | |
9301 | } | |
9302 | ||
b9f2c044 | 9303 | static int tg3_get_sset_count (struct net_device *dev, int sset) |
1da177e4 | 9304 | { |
b9f2c044 JG |
9305 | switch (sset) { |
9306 | case ETH_SS_TEST: | |
9307 | return TG3_NUM_TEST; | |
9308 | case ETH_SS_STATS: | |
9309 | return TG3_NUM_STATS; | |
9310 | default: | |
9311 | return -EOPNOTSUPP; | |
9312 | } | |
4cafd3f5 MC |
9313 | } |
9314 | ||
1da177e4 LT |
9315 | static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf) |
9316 | { | |
9317 | switch (stringset) { | |
9318 | case ETH_SS_STATS: | |
9319 | memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys)); | |
9320 | break; | |
4cafd3f5 MC |
9321 | case ETH_SS_TEST: |
9322 | memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys)); | |
9323 | break; | |
1da177e4 LT |
9324 | default: |
9325 | WARN_ON(1); /* we need a WARN() */ | |
9326 | break; | |
9327 | } | |
9328 | } | |
9329 | ||
4009a93d MC |
9330 | static int tg3_phys_id(struct net_device *dev, u32 data) |
9331 | { | |
9332 | struct tg3 *tp = netdev_priv(dev); | |
9333 | int i; | |
9334 | ||
9335 | if (!netif_running(tp->dev)) | |
9336 | return -EAGAIN; | |
9337 | ||
9338 | if (data == 0) | |
759afc31 | 9339 | data = UINT_MAX / 2; |
4009a93d MC |
9340 | |
9341 | for (i = 0; i < (data * 2); i++) { | |
9342 | if ((i % 2) == 0) | |
9343 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
9344 | LED_CTRL_1000MBPS_ON | | |
9345 | LED_CTRL_100MBPS_ON | | |
9346 | LED_CTRL_10MBPS_ON | | |
9347 | LED_CTRL_TRAFFIC_OVERRIDE | | |
9348 | LED_CTRL_TRAFFIC_BLINK | | |
9349 | LED_CTRL_TRAFFIC_LED); | |
6aa20a22 | 9350 | |
4009a93d MC |
9351 | else |
9352 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
9353 | LED_CTRL_TRAFFIC_OVERRIDE); | |
9354 | ||
9355 | if (msleep_interruptible(500)) | |
9356 | break; | |
9357 | } | |
9358 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
9359 | return 0; | |
9360 | } | |
9361 | ||
1da177e4 LT |
9362 | static void tg3_get_ethtool_stats (struct net_device *dev, |
9363 | struct ethtool_stats *estats, u64 *tmp_stats) | |
9364 | { | |
9365 | struct tg3 *tp = netdev_priv(dev); | |
9366 | memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats)); | |
9367 | } | |
9368 | ||
566f86ad | 9369 | #define NVRAM_TEST_SIZE 0x100 |
a5767dec MC |
9370 | #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14 |
9371 | #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18 | |
9372 | #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c | |
b16250e3 MC |
9373 | #define NVRAM_SELFBOOT_HW_SIZE 0x20 |
9374 | #define NVRAM_SELFBOOT_DATA_SIZE 0x1c | |
566f86ad MC |
9375 | |
9376 | static int tg3_test_nvram(struct tg3 *tp) | |
9377 | { | |
b9fc7dc5 | 9378 | u32 csum, magic; |
a9dc529d | 9379 | __be32 *buf; |
ab0049b4 | 9380 | int i, j, k, err = 0, size; |
566f86ad | 9381 | |
df259d8c MC |
9382 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) |
9383 | return 0; | |
9384 | ||
e4f34110 | 9385 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1b27777a MC |
9386 | return -EIO; |
9387 | ||
1b27777a MC |
9388 | if (magic == TG3_EEPROM_MAGIC) |
9389 | size = NVRAM_TEST_SIZE; | |
b16250e3 | 9390 | else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) { |
a5767dec MC |
9391 | if ((magic & TG3_EEPROM_SB_FORMAT_MASK) == |
9392 | TG3_EEPROM_SB_FORMAT_1) { | |
9393 | switch (magic & TG3_EEPROM_SB_REVISION_MASK) { | |
9394 | case TG3_EEPROM_SB_REVISION_0: | |
9395 | size = NVRAM_SELFBOOT_FORMAT1_0_SIZE; | |
9396 | break; | |
9397 | case TG3_EEPROM_SB_REVISION_2: | |
9398 | size = NVRAM_SELFBOOT_FORMAT1_2_SIZE; | |
9399 | break; | |
9400 | case TG3_EEPROM_SB_REVISION_3: | |
9401 | size = NVRAM_SELFBOOT_FORMAT1_3_SIZE; | |
9402 | break; | |
9403 | default: | |
9404 | return 0; | |
9405 | } | |
9406 | } else | |
1b27777a | 9407 | return 0; |
b16250e3 MC |
9408 | } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
9409 | size = NVRAM_SELFBOOT_HW_SIZE; | |
9410 | else | |
1b27777a MC |
9411 | return -EIO; |
9412 | ||
9413 | buf = kmalloc(size, GFP_KERNEL); | |
566f86ad MC |
9414 | if (buf == NULL) |
9415 | return -ENOMEM; | |
9416 | ||
1b27777a MC |
9417 | err = -EIO; |
9418 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
a9dc529d MC |
9419 | err = tg3_nvram_read_be32(tp, i, &buf[j]); |
9420 | if (err) | |
566f86ad | 9421 | break; |
566f86ad | 9422 | } |
1b27777a | 9423 | if (i < size) |
566f86ad MC |
9424 | goto out; |
9425 | ||
1b27777a | 9426 | /* Selfboot format */ |
a9dc529d | 9427 | magic = be32_to_cpu(buf[0]); |
b9fc7dc5 | 9428 | if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == |
b16250e3 | 9429 | TG3_EEPROM_MAGIC_FW) { |
1b27777a MC |
9430 | u8 *buf8 = (u8 *) buf, csum8 = 0; |
9431 | ||
b9fc7dc5 | 9432 | if ((magic & TG3_EEPROM_SB_REVISION_MASK) == |
a5767dec MC |
9433 | TG3_EEPROM_SB_REVISION_2) { |
9434 | /* For rev 2, the csum doesn't include the MBA. */ | |
9435 | for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++) | |
9436 | csum8 += buf8[i]; | |
9437 | for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++) | |
9438 | csum8 += buf8[i]; | |
9439 | } else { | |
9440 | for (i = 0; i < size; i++) | |
9441 | csum8 += buf8[i]; | |
9442 | } | |
1b27777a | 9443 | |
ad96b485 AB |
9444 | if (csum8 == 0) { |
9445 | err = 0; | |
9446 | goto out; | |
9447 | } | |
9448 | ||
9449 | err = -EIO; | |
9450 | goto out; | |
1b27777a | 9451 | } |
566f86ad | 9452 | |
b9fc7dc5 | 9453 | if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == |
b16250e3 MC |
9454 | TG3_EEPROM_MAGIC_HW) { |
9455 | u8 data[NVRAM_SELFBOOT_DATA_SIZE]; | |
a9dc529d | 9456 | u8 parity[NVRAM_SELFBOOT_DATA_SIZE]; |
b16250e3 | 9457 | u8 *buf8 = (u8 *) buf; |
b16250e3 MC |
9458 | |
9459 | /* Separate the parity bits and the data bytes. */ | |
9460 | for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) { | |
9461 | if ((i == 0) || (i == 8)) { | |
9462 | int l; | |
9463 | u8 msk; | |
9464 | ||
9465 | for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1) | |
9466 | parity[k++] = buf8[i] & msk; | |
9467 | i++; | |
9468 | } | |
9469 | else if (i == 16) { | |
9470 | int l; | |
9471 | u8 msk; | |
9472 | ||
9473 | for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1) | |
9474 | parity[k++] = buf8[i] & msk; | |
9475 | i++; | |
9476 | ||
9477 | for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1) | |
9478 | parity[k++] = buf8[i] & msk; | |
9479 | i++; | |
9480 | } | |
9481 | data[j++] = buf8[i]; | |
9482 | } | |
9483 | ||
9484 | err = -EIO; | |
9485 | for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) { | |
9486 | u8 hw8 = hweight8(data[i]); | |
9487 | ||
9488 | if ((hw8 & 0x1) && parity[i]) | |
9489 | goto out; | |
9490 | else if (!(hw8 & 0x1) && !parity[i]) | |
9491 | goto out; | |
9492 | } | |
9493 | err = 0; | |
9494 | goto out; | |
9495 | } | |
9496 | ||
566f86ad MC |
9497 | /* Bootstrap checksum at offset 0x10 */ |
9498 | csum = calc_crc((unsigned char *) buf, 0x10); | |
a9dc529d | 9499 | if (csum != be32_to_cpu(buf[0x10/4])) |
566f86ad MC |
9500 | goto out; |
9501 | ||
9502 | /* Manufacturing block starts at offset 0x74, checksum at 0xfc */ | |
9503 | csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88); | |
a9dc529d MC |
9504 | if (csum != be32_to_cpu(buf[0xfc/4])) |
9505 | goto out; | |
566f86ad MC |
9506 | |
9507 | err = 0; | |
9508 | ||
9509 | out: | |
9510 | kfree(buf); | |
9511 | return err; | |
9512 | } | |
9513 | ||
ca43007a MC |
9514 | #define TG3_SERDES_TIMEOUT_SEC 2 |
9515 | #define TG3_COPPER_TIMEOUT_SEC 6 | |
9516 | ||
9517 | static int tg3_test_link(struct tg3 *tp) | |
9518 | { | |
9519 | int i, max; | |
9520 | ||
9521 | if (!netif_running(tp->dev)) | |
9522 | return -ENODEV; | |
9523 | ||
4c987487 | 9524 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) |
ca43007a MC |
9525 | max = TG3_SERDES_TIMEOUT_SEC; |
9526 | else | |
9527 | max = TG3_COPPER_TIMEOUT_SEC; | |
9528 | ||
9529 | for (i = 0; i < max; i++) { | |
9530 | if (netif_carrier_ok(tp->dev)) | |
9531 | return 0; | |
9532 | ||
9533 | if (msleep_interruptible(1000)) | |
9534 | break; | |
9535 | } | |
9536 | ||
9537 | return -EIO; | |
9538 | } | |
9539 | ||
a71116d1 | 9540 | /* Only test the commonly used registers */ |
30ca3e37 | 9541 | static int tg3_test_registers(struct tg3 *tp) |
a71116d1 | 9542 | { |
b16250e3 | 9543 | int i, is_5705, is_5750; |
a71116d1 MC |
9544 | u32 offset, read_mask, write_mask, val, save_val, read_val; |
9545 | static struct { | |
9546 | u16 offset; | |
9547 | u16 flags; | |
9548 | #define TG3_FL_5705 0x1 | |
9549 | #define TG3_FL_NOT_5705 0x2 | |
9550 | #define TG3_FL_NOT_5788 0x4 | |
b16250e3 | 9551 | #define TG3_FL_NOT_5750 0x8 |
a71116d1 MC |
9552 | u32 read_mask; |
9553 | u32 write_mask; | |
9554 | } reg_tbl[] = { | |
9555 | /* MAC Control Registers */ | |
9556 | { MAC_MODE, TG3_FL_NOT_5705, | |
9557 | 0x00000000, 0x00ef6f8c }, | |
9558 | { MAC_MODE, TG3_FL_5705, | |
9559 | 0x00000000, 0x01ef6b8c }, | |
9560 | { MAC_STATUS, TG3_FL_NOT_5705, | |
9561 | 0x03800107, 0x00000000 }, | |
9562 | { MAC_STATUS, TG3_FL_5705, | |
9563 | 0x03800100, 0x00000000 }, | |
9564 | { MAC_ADDR_0_HIGH, 0x0000, | |
9565 | 0x00000000, 0x0000ffff }, | |
9566 | { MAC_ADDR_0_LOW, 0x0000, | |
9567 | 0x00000000, 0xffffffff }, | |
9568 | { MAC_RX_MTU_SIZE, 0x0000, | |
9569 | 0x00000000, 0x0000ffff }, | |
9570 | { MAC_TX_MODE, 0x0000, | |
9571 | 0x00000000, 0x00000070 }, | |
9572 | { MAC_TX_LENGTHS, 0x0000, | |
9573 | 0x00000000, 0x00003fff }, | |
9574 | { MAC_RX_MODE, TG3_FL_NOT_5705, | |
9575 | 0x00000000, 0x000007fc }, | |
9576 | { MAC_RX_MODE, TG3_FL_5705, | |
9577 | 0x00000000, 0x000007dc }, | |
9578 | { MAC_HASH_REG_0, 0x0000, | |
9579 | 0x00000000, 0xffffffff }, | |
9580 | { MAC_HASH_REG_1, 0x0000, | |
9581 | 0x00000000, 0xffffffff }, | |
9582 | { MAC_HASH_REG_2, 0x0000, | |
9583 | 0x00000000, 0xffffffff }, | |
9584 | { MAC_HASH_REG_3, 0x0000, | |
9585 | 0x00000000, 0xffffffff }, | |
9586 | ||
9587 | /* Receive Data and Receive BD Initiator Control Registers. */ | |
9588 | { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705, | |
9589 | 0x00000000, 0xffffffff }, | |
9590 | { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705, | |
9591 | 0x00000000, 0xffffffff }, | |
9592 | { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705, | |
9593 | 0x00000000, 0x00000003 }, | |
9594 | { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705, | |
9595 | 0x00000000, 0xffffffff }, | |
9596 | { RCVDBDI_STD_BD+0, 0x0000, | |
9597 | 0x00000000, 0xffffffff }, | |
9598 | { RCVDBDI_STD_BD+4, 0x0000, | |
9599 | 0x00000000, 0xffffffff }, | |
9600 | { RCVDBDI_STD_BD+8, 0x0000, | |
9601 | 0x00000000, 0xffff0002 }, | |
9602 | { RCVDBDI_STD_BD+0xc, 0x0000, | |
9603 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 9604 | |
a71116d1 MC |
9605 | /* Receive BD Initiator Control Registers. */ |
9606 | { RCVBDI_STD_THRESH, TG3_FL_NOT_5705, | |
9607 | 0x00000000, 0xffffffff }, | |
9608 | { RCVBDI_STD_THRESH, TG3_FL_5705, | |
9609 | 0x00000000, 0x000003ff }, | |
9610 | { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705, | |
9611 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 9612 | |
a71116d1 MC |
9613 | /* Host Coalescing Control Registers. */ |
9614 | { HOSTCC_MODE, TG3_FL_NOT_5705, | |
9615 | 0x00000000, 0x00000004 }, | |
9616 | { HOSTCC_MODE, TG3_FL_5705, | |
9617 | 0x00000000, 0x000000f6 }, | |
9618 | { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705, | |
9619 | 0x00000000, 0xffffffff }, | |
9620 | { HOSTCC_RXCOL_TICKS, TG3_FL_5705, | |
9621 | 0x00000000, 0x000003ff }, | |
9622 | { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705, | |
9623 | 0x00000000, 0xffffffff }, | |
9624 | { HOSTCC_TXCOL_TICKS, TG3_FL_5705, | |
9625 | 0x00000000, 0x000003ff }, | |
9626 | { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705, | |
9627 | 0x00000000, 0xffffffff }, | |
9628 | { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
9629 | 0x00000000, 0x000000ff }, | |
9630 | { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705, | |
9631 | 0x00000000, 0xffffffff }, | |
9632 | { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
9633 | 0x00000000, 0x000000ff }, | |
9634 | { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
9635 | 0x00000000, 0xffffffff }, | |
9636 | { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
9637 | 0x00000000, 0xffffffff }, | |
9638 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
9639 | 0x00000000, 0xffffffff }, | |
9640 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
9641 | 0x00000000, 0x000000ff }, | |
9642 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
9643 | 0x00000000, 0xffffffff }, | |
9644 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
9645 | 0x00000000, 0x000000ff }, | |
9646 | { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705, | |
9647 | 0x00000000, 0xffffffff }, | |
9648 | { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705, | |
9649 | 0x00000000, 0xffffffff }, | |
9650 | { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705, | |
9651 | 0x00000000, 0xffffffff }, | |
9652 | { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000, | |
9653 | 0x00000000, 0xffffffff }, | |
9654 | { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000, | |
9655 | 0x00000000, 0xffffffff }, | |
9656 | { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000, | |
9657 | 0xffffffff, 0x00000000 }, | |
9658 | { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000, | |
9659 | 0xffffffff, 0x00000000 }, | |
9660 | ||
9661 | /* Buffer Manager Control Registers. */ | |
b16250e3 | 9662 | { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750, |
a71116d1 | 9663 | 0x00000000, 0x007fff80 }, |
b16250e3 | 9664 | { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750, |
a71116d1 MC |
9665 | 0x00000000, 0x007fffff }, |
9666 | { BUFMGR_MB_RDMA_LOW_WATER, 0x0000, | |
9667 | 0x00000000, 0x0000003f }, | |
9668 | { BUFMGR_MB_MACRX_LOW_WATER, 0x0000, | |
9669 | 0x00000000, 0x000001ff }, | |
9670 | { BUFMGR_MB_HIGH_WATER, 0x0000, | |
9671 | 0x00000000, 0x000001ff }, | |
9672 | { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705, | |
9673 | 0xffffffff, 0x00000000 }, | |
9674 | { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705, | |
9675 | 0xffffffff, 0x00000000 }, | |
6aa20a22 | 9676 | |
a71116d1 MC |
9677 | /* Mailbox Registers */ |
9678 | { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000, | |
9679 | 0x00000000, 0x000001ff }, | |
9680 | { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705, | |
9681 | 0x00000000, 0x000001ff }, | |
9682 | { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000, | |
9683 | 0x00000000, 0x000007ff }, | |
9684 | { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000, | |
9685 | 0x00000000, 0x000001ff }, | |
9686 | ||
9687 | { 0xffff, 0x0000, 0x00000000, 0x00000000 }, | |
9688 | }; | |
9689 | ||
b16250e3 MC |
9690 | is_5705 = is_5750 = 0; |
9691 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
a71116d1 | 9692 | is_5705 = 1; |
b16250e3 MC |
9693 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
9694 | is_5750 = 1; | |
9695 | } | |
a71116d1 MC |
9696 | |
9697 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { | |
9698 | if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) | |
9699 | continue; | |
9700 | ||
9701 | if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) | |
9702 | continue; | |
9703 | ||
9704 | if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) && | |
9705 | (reg_tbl[i].flags & TG3_FL_NOT_5788)) | |
9706 | continue; | |
9707 | ||
b16250e3 MC |
9708 | if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) |
9709 | continue; | |
9710 | ||
a71116d1 MC |
9711 | offset = (u32) reg_tbl[i].offset; |
9712 | read_mask = reg_tbl[i].read_mask; | |
9713 | write_mask = reg_tbl[i].write_mask; | |
9714 | ||
9715 | /* Save the original register content */ | |
9716 | save_val = tr32(offset); | |
9717 | ||
9718 | /* Determine the read-only value. */ | |
9719 | read_val = save_val & read_mask; | |
9720 | ||
9721 | /* Write zero to the register, then make sure the read-only bits | |
9722 | * are not changed and the read/write bits are all zeros. | |
9723 | */ | |
9724 | tw32(offset, 0); | |
9725 | ||
9726 | val = tr32(offset); | |
9727 | ||
9728 | /* Test the read-only and read/write bits. */ | |
9729 | if (((val & read_mask) != read_val) || (val & write_mask)) | |
9730 | goto out; | |
9731 | ||
9732 | /* Write ones to all the bits defined by RdMask and WrMask, then | |
9733 | * make sure the read-only bits are not changed and the | |
9734 | * read/write bits are all ones. | |
9735 | */ | |
9736 | tw32(offset, read_mask | write_mask); | |
9737 | ||
9738 | val = tr32(offset); | |
9739 | ||
9740 | /* Test the read-only bits. */ | |
9741 | if ((val & read_mask) != read_val) | |
9742 | goto out; | |
9743 | ||
9744 | /* Test the read/write bits. */ | |
9745 | if ((val & write_mask) != write_mask) | |
9746 | goto out; | |
9747 | ||
9748 | tw32(offset, save_val); | |
9749 | } | |
9750 | ||
9751 | return 0; | |
9752 | ||
9753 | out: | |
9f88f29f MC |
9754 | if (netif_msg_hw(tp)) |
9755 | printk(KERN_ERR PFX "Register test failed at offset %x\n", | |
9756 | offset); | |
a71116d1 MC |
9757 | tw32(offset, save_val); |
9758 | return -EIO; | |
9759 | } | |
9760 | ||
7942e1db MC |
9761 | static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) |
9762 | { | |
f71e1309 | 9763 | static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a }; |
7942e1db MC |
9764 | int i; |
9765 | u32 j; | |
9766 | ||
e9edda69 | 9767 | for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { |
7942e1db MC |
9768 | for (j = 0; j < len; j += 4) { |
9769 | u32 val; | |
9770 | ||
9771 | tg3_write_mem(tp, offset + j, test_pattern[i]); | |
9772 | tg3_read_mem(tp, offset + j, &val); | |
9773 | if (val != test_pattern[i]) | |
9774 | return -EIO; | |
9775 | } | |
9776 | } | |
9777 | return 0; | |
9778 | } | |
9779 | ||
9780 | static int tg3_test_memory(struct tg3 *tp) | |
9781 | { | |
9782 | static struct mem_entry { | |
9783 | u32 offset; | |
9784 | u32 len; | |
9785 | } mem_tbl_570x[] = { | |
38690194 | 9786 | { 0x00000000, 0x00b50}, |
7942e1db MC |
9787 | { 0x00002000, 0x1c000}, |
9788 | { 0xffffffff, 0x00000} | |
9789 | }, mem_tbl_5705[] = { | |
9790 | { 0x00000100, 0x0000c}, | |
9791 | { 0x00000200, 0x00008}, | |
7942e1db MC |
9792 | { 0x00004000, 0x00800}, |
9793 | { 0x00006000, 0x01000}, | |
9794 | { 0x00008000, 0x02000}, | |
9795 | { 0x00010000, 0x0e000}, | |
9796 | { 0xffffffff, 0x00000} | |
79f4d13a MC |
9797 | }, mem_tbl_5755[] = { |
9798 | { 0x00000200, 0x00008}, | |
9799 | { 0x00004000, 0x00800}, | |
9800 | { 0x00006000, 0x00800}, | |
9801 | { 0x00008000, 0x02000}, | |
9802 | { 0x00010000, 0x0c000}, | |
9803 | { 0xffffffff, 0x00000} | |
b16250e3 MC |
9804 | }, mem_tbl_5906[] = { |
9805 | { 0x00000200, 0x00008}, | |
9806 | { 0x00004000, 0x00400}, | |
9807 | { 0x00006000, 0x00400}, | |
9808 | { 0x00008000, 0x01000}, | |
9809 | { 0x00010000, 0x01000}, | |
9810 | { 0xffffffff, 0x00000} | |
7942e1db MC |
9811 | }; |
9812 | struct mem_entry *mem_tbl; | |
9813 | int err = 0; | |
9814 | int i; | |
9815 | ||
321d32a0 MC |
9816 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
9817 | mem_tbl = mem_tbl_5755; | |
9818 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
9819 | mem_tbl = mem_tbl_5906; | |
9820 | else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | |
9821 | mem_tbl = mem_tbl_5705; | |
9822 | else | |
7942e1db MC |
9823 | mem_tbl = mem_tbl_570x; |
9824 | ||
9825 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | |
9826 | if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset, | |
9827 | mem_tbl[i].len)) != 0) | |
9828 | break; | |
9829 | } | |
6aa20a22 | 9830 | |
7942e1db MC |
9831 | return err; |
9832 | } | |
9833 | ||
9f40dead MC |
9834 | #define TG3_MAC_LOOPBACK 0 |
9835 | #define TG3_PHY_LOOPBACK 1 | |
9836 | ||
9837 | static int tg3_run_loopback(struct tg3 *tp, int loopback_mode) | |
c76949a6 | 9838 | { |
9f40dead | 9839 | u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key; |
c76949a6 MC |
9840 | u32 desc_idx; |
9841 | struct sk_buff *skb, *rx_skb; | |
9842 | u8 *tx_data; | |
9843 | dma_addr_t map; | |
9844 | int num_pkts, tx_len, rx_len, i, err; | |
9845 | struct tg3_rx_buffer_desc *desc; | |
898a56f8 | 9846 | struct tg3_napi *tnapi, *rnapi; |
21f581a5 | 9847 | struct tg3_rx_prodring_set *tpr = &tp->prodring[0]; |
c76949a6 | 9848 | |
898a56f8 MC |
9849 | tnapi = &tp->napi[0]; |
9850 | rnapi = &tp->napi[0]; | |
9851 | ||
9f40dead | 9852 | if (loopback_mode == TG3_MAC_LOOPBACK) { |
c94e3941 MC |
9853 | /* HW errata - mac loopback fails in some cases on 5780. |
9854 | * Normal traffic and PHY loopback are not affected by | |
9855 | * errata. | |
9856 | */ | |
9857 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) | |
9858 | return 0; | |
9859 | ||
9f40dead | 9860 | mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) | |
e8f3f6ca MC |
9861 | MAC_MODE_PORT_INT_LPBACK; |
9862 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
9863 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
3f7045c1 MC |
9864 | if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) |
9865 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
9866 | else | |
9867 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
9f40dead MC |
9868 | tw32(MAC_MODE, mac_mode); |
9869 | } else if (loopback_mode == TG3_PHY_LOOPBACK) { | |
3f7045c1 MC |
9870 | u32 val; |
9871 | ||
7f97a4bd MC |
9872 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { |
9873 | tg3_phy_fet_toggle_apd(tp, false); | |
5d64ad34 MC |
9874 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100; |
9875 | } else | |
9876 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000; | |
3f7045c1 | 9877 | |
9ef8ca99 MC |
9878 | tg3_phy_toggle_automdix(tp, 0); |
9879 | ||
3f7045c1 | 9880 | tg3_writephy(tp, MII_BMCR, val); |
c94e3941 | 9881 | udelay(40); |
5d64ad34 | 9882 | |
e8f3f6ca | 9883 | mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; |
7f97a4bd MC |
9884 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { |
9885 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
9886 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800); | |
5d64ad34 MC |
9887 | mac_mode |= MAC_MODE_PORT_MODE_MII; |
9888 | } else | |
9889 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
b16250e3 | 9890 | |
c94e3941 MC |
9891 | /* reset to prevent losing 1st rx packet intermittently */ |
9892 | if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { | |
9893 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
9894 | udelay(10); | |
9895 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
9896 | } | |
e8f3f6ca MC |
9897 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
9898 | if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) | |
9899 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
9900 | else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) | |
9901 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
ff18ff02 MC |
9902 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
9903 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
9904 | } | |
9f40dead | 9905 | tw32(MAC_MODE, mac_mode); |
9f40dead MC |
9906 | } |
9907 | else | |
9908 | return -EINVAL; | |
c76949a6 MC |
9909 | |
9910 | err = -EIO; | |
9911 | ||
c76949a6 | 9912 | tx_len = 1514; |
a20e9c62 | 9913 | skb = netdev_alloc_skb(tp->dev, tx_len); |
a50bb7b9 JJ |
9914 | if (!skb) |
9915 | return -ENOMEM; | |
9916 | ||
c76949a6 MC |
9917 | tx_data = skb_put(skb, tx_len); |
9918 | memcpy(tx_data, tp->dev->dev_addr, 6); | |
9919 | memset(tx_data + 6, 0x0, 8); | |
9920 | ||
9921 | tw32(MAC_RX_MTU_SIZE, tx_len + 4); | |
9922 | ||
9923 | for (i = 14; i < tx_len; i++) | |
9924 | tx_data[i] = (u8) (i & 0xff); | |
9925 | ||
9926 | map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); | |
9927 | ||
9928 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
9929 | HOSTCC_MODE_NOW); | |
9930 | ||
9931 | udelay(10); | |
9932 | ||
898a56f8 | 9933 | rx_start_idx = rnapi->hw_status->idx[0].rx_producer; |
c76949a6 | 9934 | |
c76949a6 MC |
9935 | num_pkts = 0; |
9936 | ||
f3f3f27e | 9937 | tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1); |
c76949a6 | 9938 | |
f3f3f27e | 9939 | tnapi->tx_prod++; |
c76949a6 MC |
9940 | num_pkts++; |
9941 | ||
f3f3f27e MC |
9942 | tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); |
9943 | tr32_mailbox(tnapi->prodmbox); | |
c76949a6 MC |
9944 | |
9945 | udelay(10); | |
9946 | ||
3f7045c1 MC |
9947 | /* 250 usec to allow enough time on some 10/100 Mbps devices. */ |
9948 | for (i = 0; i < 25; i++) { | |
c76949a6 MC |
9949 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
9950 | HOSTCC_MODE_NOW); | |
9951 | ||
9952 | udelay(10); | |
9953 | ||
898a56f8 MC |
9954 | tx_idx = tnapi->hw_status->idx[0].tx_consumer; |
9955 | rx_idx = rnapi->hw_status->idx[0].rx_producer; | |
f3f3f27e | 9956 | if ((tx_idx == tnapi->tx_prod) && |
c76949a6 MC |
9957 | (rx_idx == (rx_start_idx + num_pkts))) |
9958 | break; | |
9959 | } | |
9960 | ||
9961 | pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE); | |
9962 | dev_kfree_skb(skb); | |
9963 | ||
f3f3f27e | 9964 | if (tx_idx != tnapi->tx_prod) |
c76949a6 MC |
9965 | goto out; |
9966 | ||
9967 | if (rx_idx != rx_start_idx + num_pkts) | |
9968 | goto out; | |
9969 | ||
72334482 | 9970 | desc = &rnapi->rx_rcb[rx_start_idx]; |
c76949a6 MC |
9971 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; |
9972 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
9973 | if (opaque_key != RXD_OPAQUE_RING_STD) | |
9974 | goto out; | |
9975 | ||
9976 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
9977 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) | |
9978 | goto out; | |
9979 | ||
9980 | rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; | |
9981 | if (rx_len != tx_len) | |
9982 | goto out; | |
9983 | ||
21f581a5 | 9984 | rx_skb = tpr->rx_std_buffers[desc_idx].skb; |
c76949a6 | 9985 | |
21f581a5 | 9986 | map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping); |
c76949a6 MC |
9987 | pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE); |
9988 | ||
9989 | for (i = 14; i < tx_len; i++) { | |
9990 | if (*(rx_skb->data + i) != (u8) (i & 0xff)) | |
9991 | goto out; | |
9992 | } | |
9993 | err = 0; | |
6aa20a22 | 9994 | |
c76949a6 MC |
9995 | /* tg3_free_rings will unmap and free the rx_skb */ |
9996 | out: | |
9997 | return err; | |
9998 | } | |
9999 | ||
9f40dead MC |
10000 | #define TG3_MAC_LOOPBACK_FAILED 1 |
10001 | #define TG3_PHY_LOOPBACK_FAILED 2 | |
10002 | #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \ | |
10003 | TG3_PHY_LOOPBACK_FAILED) | |
10004 | ||
10005 | static int tg3_test_loopback(struct tg3 *tp) | |
10006 | { | |
10007 | int err = 0; | |
9936bcf6 | 10008 | u32 cpmuctrl = 0; |
9f40dead MC |
10009 | |
10010 | if (!netif_running(tp->dev)) | |
10011 | return TG3_LOOPBACK_FAILED; | |
10012 | ||
b9ec6c1b MC |
10013 | err = tg3_reset_hw(tp, 1); |
10014 | if (err) | |
10015 | return TG3_LOOPBACK_FAILED; | |
9f40dead | 10016 | |
6833c043 MC |
10017 | /* Turn off gphy autopowerdown. */ |
10018 | if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD) | |
10019 | tg3_phy_toggle_apd(tp, false); | |
10020 | ||
321d32a0 | 10021 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) { |
9936bcf6 MC |
10022 | int i; |
10023 | u32 status; | |
10024 | ||
10025 | tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER); | |
10026 | ||
10027 | /* Wait for up to 40 microseconds to acquire lock. */ | |
10028 | for (i = 0; i < 4; i++) { | |
10029 | status = tr32(TG3_CPMU_MUTEX_GNT); | |
10030 | if (status == CPMU_MUTEX_GNT_DRIVER) | |
10031 | break; | |
10032 | udelay(10); | |
10033 | } | |
10034 | ||
10035 | if (status != CPMU_MUTEX_GNT_DRIVER) | |
10036 | return TG3_LOOPBACK_FAILED; | |
10037 | ||
b2a5c19c | 10038 | /* Turn off link-based power management. */ |
e875093c | 10039 | cpmuctrl = tr32(TG3_CPMU_CTRL); |
109115e1 MC |
10040 | tw32(TG3_CPMU_CTRL, |
10041 | cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE | | |
10042 | CPMU_CTRL_LINK_AWARE_MODE)); | |
9936bcf6 MC |
10043 | } |
10044 | ||
9f40dead MC |
10045 | if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK)) |
10046 | err |= TG3_MAC_LOOPBACK_FAILED; | |
9936bcf6 | 10047 | |
321d32a0 | 10048 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) { |
9936bcf6 MC |
10049 | tw32(TG3_CPMU_CTRL, cpmuctrl); |
10050 | ||
10051 | /* Release the mutex */ | |
10052 | tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER); | |
10053 | } | |
10054 | ||
dd477003 MC |
10055 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && |
10056 | !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { | |
9f40dead MC |
10057 | if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK)) |
10058 | err |= TG3_PHY_LOOPBACK_FAILED; | |
10059 | } | |
10060 | ||
6833c043 MC |
10061 | /* Re-enable gphy autopowerdown. */ |
10062 | if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD) | |
10063 | tg3_phy_toggle_apd(tp, true); | |
10064 | ||
9f40dead MC |
10065 | return err; |
10066 | } | |
10067 | ||
4cafd3f5 MC |
10068 | static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest, |
10069 | u64 *data) | |
10070 | { | |
566f86ad MC |
10071 | struct tg3 *tp = netdev_priv(dev); |
10072 | ||
bc1c7567 MC |
10073 | if (tp->link_config.phy_is_low_power) |
10074 | tg3_set_power_state(tp, PCI_D0); | |
10075 | ||
566f86ad MC |
10076 | memset(data, 0, sizeof(u64) * TG3_NUM_TEST); |
10077 | ||
10078 | if (tg3_test_nvram(tp) != 0) { | |
10079 | etest->flags |= ETH_TEST_FL_FAILED; | |
10080 | data[0] = 1; | |
10081 | } | |
ca43007a MC |
10082 | if (tg3_test_link(tp) != 0) { |
10083 | etest->flags |= ETH_TEST_FL_FAILED; | |
10084 | data[1] = 1; | |
10085 | } | |
a71116d1 | 10086 | if (etest->flags & ETH_TEST_FL_OFFLINE) { |
b02fd9e3 | 10087 | int err, err2 = 0, irq_sync = 0; |
bbe832c0 MC |
10088 | |
10089 | if (netif_running(dev)) { | |
b02fd9e3 | 10090 | tg3_phy_stop(tp); |
a71116d1 | 10091 | tg3_netif_stop(tp); |
bbe832c0 MC |
10092 | irq_sync = 1; |
10093 | } | |
a71116d1 | 10094 | |
bbe832c0 | 10095 | tg3_full_lock(tp, irq_sync); |
a71116d1 MC |
10096 | |
10097 | tg3_halt(tp, RESET_KIND_SUSPEND, 1); | |
ec41c7df | 10098 | err = tg3_nvram_lock(tp); |
a71116d1 MC |
10099 | tg3_halt_cpu(tp, RX_CPU_BASE); |
10100 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
10101 | tg3_halt_cpu(tp, TX_CPU_BASE); | |
ec41c7df MC |
10102 | if (!err) |
10103 | tg3_nvram_unlock(tp); | |
a71116d1 | 10104 | |
d9ab5ad1 MC |
10105 | if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) |
10106 | tg3_phy_reset(tp); | |
10107 | ||
a71116d1 MC |
10108 | if (tg3_test_registers(tp) != 0) { |
10109 | etest->flags |= ETH_TEST_FL_FAILED; | |
10110 | data[2] = 1; | |
10111 | } | |
7942e1db MC |
10112 | if (tg3_test_memory(tp) != 0) { |
10113 | etest->flags |= ETH_TEST_FL_FAILED; | |
10114 | data[3] = 1; | |
10115 | } | |
9f40dead | 10116 | if ((data[4] = tg3_test_loopback(tp)) != 0) |
c76949a6 | 10117 | etest->flags |= ETH_TEST_FL_FAILED; |
a71116d1 | 10118 | |
f47c11ee DM |
10119 | tg3_full_unlock(tp); |
10120 | ||
d4bc3927 MC |
10121 | if (tg3_test_interrupt(tp) != 0) { |
10122 | etest->flags |= ETH_TEST_FL_FAILED; | |
10123 | data[5] = 1; | |
10124 | } | |
f47c11ee DM |
10125 | |
10126 | tg3_full_lock(tp, 0); | |
d4bc3927 | 10127 | |
a71116d1 MC |
10128 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
10129 | if (netif_running(dev)) { | |
10130 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; | |
b02fd9e3 MC |
10131 | err2 = tg3_restart_hw(tp, 1); |
10132 | if (!err2) | |
b9ec6c1b | 10133 | tg3_netif_start(tp); |
a71116d1 | 10134 | } |
f47c11ee DM |
10135 | |
10136 | tg3_full_unlock(tp); | |
b02fd9e3 MC |
10137 | |
10138 | if (irq_sync && !err2) | |
10139 | tg3_phy_start(tp); | |
a71116d1 | 10140 | } |
bc1c7567 MC |
10141 | if (tp->link_config.phy_is_low_power) |
10142 | tg3_set_power_state(tp, PCI_D3hot); | |
10143 | ||
4cafd3f5 MC |
10144 | } |
10145 | ||
1da177e4 LT |
10146 | static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
10147 | { | |
10148 | struct mii_ioctl_data *data = if_mii(ifr); | |
10149 | struct tg3 *tp = netdev_priv(dev); | |
10150 | int err; | |
10151 | ||
b02fd9e3 MC |
10152 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
10153 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
10154 | return -EAGAIN; | |
298cf9be | 10155 | return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd); |
b02fd9e3 MC |
10156 | } |
10157 | ||
1da177e4 LT |
10158 | switch(cmd) { |
10159 | case SIOCGMIIPHY: | |
10160 | data->phy_id = PHY_ADDR; | |
10161 | ||
10162 | /* fallthru */ | |
10163 | case SIOCGMIIREG: { | |
10164 | u32 mii_regval; | |
10165 | ||
10166 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) | |
10167 | break; /* We have no PHY */ | |
10168 | ||
bc1c7567 MC |
10169 | if (tp->link_config.phy_is_low_power) |
10170 | return -EAGAIN; | |
10171 | ||
f47c11ee | 10172 | spin_lock_bh(&tp->lock); |
1da177e4 | 10173 | err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); |
f47c11ee | 10174 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
10175 | |
10176 | data->val_out = mii_regval; | |
10177 | ||
10178 | return err; | |
10179 | } | |
10180 | ||
10181 | case SIOCSMIIREG: | |
10182 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) | |
10183 | break; /* We have no PHY */ | |
10184 | ||
10185 | if (!capable(CAP_NET_ADMIN)) | |
10186 | return -EPERM; | |
10187 | ||
bc1c7567 MC |
10188 | if (tp->link_config.phy_is_low_power) |
10189 | return -EAGAIN; | |
10190 | ||
f47c11ee | 10191 | spin_lock_bh(&tp->lock); |
1da177e4 | 10192 | err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); |
f47c11ee | 10193 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
10194 | |
10195 | return err; | |
10196 | ||
10197 | default: | |
10198 | /* do nothing */ | |
10199 | break; | |
10200 | } | |
10201 | return -EOPNOTSUPP; | |
10202 | } | |
10203 | ||
10204 | #if TG3_VLAN_TAG_USED | |
10205 | static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) | |
10206 | { | |
10207 | struct tg3 *tp = netdev_priv(dev); | |
10208 | ||
844b3eed MC |
10209 | if (!netif_running(dev)) { |
10210 | tp->vlgrp = grp; | |
10211 | return; | |
10212 | } | |
10213 | ||
10214 | tg3_netif_stop(tp); | |
29315e87 | 10215 | |
f47c11ee | 10216 | tg3_full_lock(tp, 0); |
1da177e4 LT |
10217 | |
10218 | tp->vlgrp = grp; | |
10219 | ||
10220 | /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */ | |
10221 | __tg3_set_rx_mode(dev); | |
10222 | ||
844b3eed | 10223 | tg3_netif_start(tp); |
46966545 MC |
10224 | |
10225 | tg3_full_unlock(tp); | |
1da177e4 | 10226 | } |
1da177e4 LT |
10227 | #endif |
10228 | ||
15f9850d DM |
10229 | static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
10230 | { | |
10231 | struct tg3 *tp = netdev_priv(dev); | |
10232 | ||
10233 | memcpy(ec, &tp->coal, sizeof(*ec)); | |
10234 | return 0; | |
10235 | } | |
10236 | ||
d244c892 MC |
10237 | static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
10238 | { | |
10239 | struct tg3 *tp = netdev_priv(dev); | |
10240 | u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0; | |
10241 | u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0; | |
10242 | ||
10243 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
10244 | max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT; | |
10245 | max_txcoal_tick_int = MAX_TXCOAL_TICK_INT; | |
10246 | max_stat_coal_ticks = MAX_STAT_COAL_TICKS; | |
10247 | min_stat_coal_ticks = MIN_STAT_COAL_TICKS; | |
10248 | } | |
10249 | ||
10250 | if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || | |
10251 | (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || | |
10252 | (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || | |
10253 | (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || | |
10254 | (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || | |
10255 | (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || | |
10256 | (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || | |
10257 | (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || | |
10258 | (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || | |
10259 | (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) | |
10260 | return -EINVAL; | |
10261 | ||
10262 | /* No rx interrupts will be generated if both are zero */ | |
10263 | if ((ec->rx_coalesce_usecs == 0) && | |
10264 | (ec->rx_max_coalesced_frames == 0)) | |
10265 | return -EINVAL; | |
10266 | ||
10267 | /* No tx interrupts will be generated if both are zero */ | |
10268 | if ((ec->tx_coalesce_usecs == 0) && | |
10269 | (ec->tx_max_coalesced_frames == 0)) | |
10270 | return -EINVAL; | |
10271 | ||
10272 | /* Only copy relevant parameters, ignore all others. */ | |
10273 | tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; | |
10274 | tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; | |
10275 | tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; | |
10276 | tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; | |
10277 | tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; | |
10278 | tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; | |
10279 | tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; | |
10280 | tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; | |
10281 | tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; | |
10282 | ||
10283 | if (netif_running(dev)) { | |
10284 | tg3_full_lock(tp, 0); | |
10285 | __tg3_set_coalesce(tp, &tp->coal); | |
10286 | tg3_full_unlock(tp); | |
10287 | } | |
10288 | return 0; | |
10289 | } | |
10290 | ||
7282d491 | 10291 | static const struct ethtool_ops tg3_ethtool_ops = { |
1da177e4 LT |
10292 | .get_settings = tg3_get_settings, |
10293 | .set_settings = tg3_set_settings, | |
10294 | .get_drvinfo = tg3_get_drvinfo, | |
10295 | .get_regs_len = tg3_get_regs_len, | |
10296 | .get_regs = tg3_get_regs, | |
10297 | .get_wol = tg3_get_wol, | |
10298 | .set_wol = tg3_set_wol, | |
10299 | .get_msglevel = tg3_get_msglevel, | |
10300 | .set_msglevel = tg3_set_msglevel, | |
10301 | .nway_reset = tg3_nway_reset, | |
10302 | .get_link = ethtool_op_get_link, | |
10303 | .get_eeprom_len = tg3_get_eeprom_len, | |
10304 | .get_eeprom = tg3_get_eeprom, | |
10305 | .set_eeprom = tg3_set_eeprom, | |
10306 | .get_ringparam = tg3_get_ringparam, | |
10307 | .set_ringparam = tg3_set_ringparam, | |
10308 | .get_pauseparam = tg3_get_pauseparam, | |
10309 | .set_pauseparam = tg3_set_pauseparam, | |
10310 | .get_rx_csum = tg3_get_rx_csum, | |
10311 | .set_rx_csum = tg3_set_rx_csum, | |
1da177e4 | 10312 | .set_tx_csum = tg3_set_tx_csum, |
1da177e4 | 10313 | .set_sg = ethtool_op_set_sg, |
1da177e4 | 10314 | .set_tso = tg3_set_tso, |
4cafd3f5 | 10315 | .self_test = tg3_self_test, |
1da177e4 | 10316 | .get_strings = tg3_get_strings, |
4009a93d | 10317 | .phys_id = tg3_phys_id, |
1da177e4 | 10318 | .get_ethtool_stats = tg3_get_ethtool_stats, |
15f9850d | 10319 | .get_coalesce = tg3_get_coalesce, |
d244c892 | 10320 | .set_coalesce = tg3_set_coalesce, |
b9f2c044 | 10321 | .get_sset_count = tg3_get_sset_count, |
1da177e4 LT |
10322 | }; |
10323 | ||
10324 | static void __devinit tg3_get_eeprom_size(struct tg3 *tp) | |
10325 | { | |
1b27777a | 10326 | u32 cursize, val, magic; |
1da177e4 LT |
10327 | |
10328 | tp->nvram_size = EEPROM_CHIP_SIZE; | |
10329 | ||
e4f34110 | 10330 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1da177e4 LT |
10331 | return; |
10332 | ||
b16250e3 MC |
10333 | if ((magic != TG3_EEPROM_MAGIC) && |
10334 | ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) && | |
10335 | ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW)) | |
1da177e4 LT |
10336 | return; |
10337 | ||
10338 | /* | |
10339 | * Size the chip by reading offsets at increasing powers of two. | |
10340 | * When we encounter our validation signature, we know the addressing | |
10341 | * has wrapped around, and thus have our chip size. | |
10342 | */ | |
1b27777a | 10343 | cursize = 0x10; |
1da177e4 LT |
10344 | |
10345 | while (cursize < tp->nvram_size) { | |
e4f34110 | 10346 | if (tg3_nvram_read(tp, cursize, &val) != 0) |
1da177e4 LT |
10347 | return; |
10348 | ||
1820180b | 10349 | if (val == magic) |
1da177e4 LT |
10350 | break; |
10351 | ||
10352 | cursize <<= 1; | |
10353 | } | |
10354 | ||
10355 | tp->nvram_size = cursize; | |
10356 | } | |
6aa20a22 | 10357 | |
1da177e4 LT |
10358 | static void __devinit tg3_get_nvram_size(struct tg3 *tp) |
10359 | { | |
10360 | u32 val; | |
10361 | ||
df259d8c MC |
10362 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || |
10363 | tg3_nvram_read(tp, 0, &val) != 0) | |
1b27777a MC |
10364 | return; |
10365 | ||
10366 | /* Selfboot format */ | |
1820180b | 10367 | if (val != TG3_EEPROM_MAGIC) { |
1b27777a MC |
10368 | tg3_get_eeprom_size(tp); |
10369 | return; | |
10370 | } | |
10371 | ||
6d348f2c | 10372 | if (tg3_nvram_read(tp, 0xf0, &val) == 0) { |
1da177e4 | 10373 | if (val != 0) { |
6d348f2c MC |
10374 | /* This is confusing. We want to operate on the |
10375 | * 16-bit value at offset 0xf2. The tg3_nvram_read() | |
10376 | * call will read from NVRAM and byteswap the data | |
10377 | * according to the byteswapping settings for all | |
10378 | * other register accesses. This ensures the data we | |
10379 | * want will always reside in the lower 16-bits. | |
10380 | * However, the data in NVRAM is in LE format, which | |
10381 | * means the data from the NVRAM read will always be | |
10382 | * opposite the endianness of the CPU. The 16-bit | |
10383 | * byteswap then brings the data to CPU endianness. | |
10384 | */ | |
10385 | tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; | |
1da177e4 LT |
10386 | return; |
10387 | } | |
10388 | } | |
fd1122a2 | 10389 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; |
1da177e4 LT |
10390 | } |
10391 | ||
10392 | static void __devinit tg3_get_nvram_info(struct tg3 *tp) | |
10393 | { | |
10394 | u32 nvcfg1; | |
10395 | ||
10396 | nvcfg1 = tr32(NVRAM_CFG1); | |
10397 | if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) { | |
10398 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
8590a603 | 10399 | } else { |
1da177e4 LT |
10400 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
10401 | tw32(NVRAM_CFG1, nvcfg1); | |
10402 | } | |
10403 | ||
4c987487 | 10404 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) || |
a4e2b347 | 10405 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
1da177e4 | 10406 | switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { |
8590a603 MC |
10407 | case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: |
10408 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10409 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
10410 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10411 | break; | |
10412 | case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED: | |
10413 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10414 | tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; | |
10415 | break; | |
10416 | case FLASH_VENDOR_ATMEL_EEPROM: | |
10417 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10418 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
10419 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10420 | break; | |
10421 | case FLASH_VENDOR_ST: | |
10422 | tp->nvram_jedecnum = JEDEC_ST; | |
10423 | tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; | |
10424 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10425 | break; | |
10426 | case FLASH_VENDOR_SAIFUN: | |
10427 | tp->nvram_jedecnum = JEDEC_SAIFUN; | |
10428 | tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; | |
10429 | break; | |
10430 | case FLASH_VENDOR_SST_SMALL: | |
10431 | case FLASH_VENDOR_SST_LARGE: | |
10432 | tp->nvram_jedecnum = JEDEC_SST; | |
10433 | tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; | |
10434 | break; | |
1da177e4 | 10435 | } |
8590a603 | 10436 | } else { |
1da177e4 LT |
10437 | tp->nvram_jedecnum = JEDEC_ATMEL; |
10438 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
10439 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10440 | } | |
10441 | } | |
10442 | ||
361b4ac2 MC |
10443 | static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp) |
10444 | { | |
10445 | u32 nvcfg1; | |
10446 | ||
10447 | nvcfg1 = tr32(NVRAM_CFG1); | |
10448 | ||
e6af301b MC |
10449 | /* NVRAM protection for TPM */ |
10450 | if (nvcfg1 & (1 << 27)) | |
10451 | tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM; | |
10452 | ||
361b4ac2 | 10453 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { |
8590a603 MC |
10454 | case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: |
10455 | case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ: | |
10456 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10457 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10458 | break; | |
10459 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
10460 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10461 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10462 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
10463 | break; | |
10464 | case FLASH_5752VENDOR_ST_M45PE10: | |
10465 | case FLASH_5752VENDOR_ST_M45PE20: | |
10466 | case FLASH_5752VENDOR_ST_M45PE40: | |
10467 | tp->nvram_jedecnum = JEDEC_ST; | |
10468 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10469 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
10470 | break; | |
361b4ac2 MC |
10471 | } |
10472 | ||
10473 | if (tp->tg3_flags2 & TG3_FLG2_FLASH) { | |
10474 | switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) { | |
8590a603 MC |
10475 | case FLASH_5752PAGE_SIZE_256: |
10476 | tp->nvram_pagesize = 256; | |
10477 | break; | |
10478 | case FLASH_5752PAGE_SIZE_512: | |
10479 | tp->nvram_pagesize = 512; | |
10480 | break; | |
10481 | case FLASH_5752PAGE_SIZE_1K: | |
10482 | tp->nvram_pagesize = 1024; | |
10483 | break; | |
10484 | case FLASH_5752PAGE_SIZE_2K: | |
10485 | tp->nvram_pagesize = 2048; | |
10486 | break; | |
10487 | case FLASH_5752PAGE_SIZE_4K: | |
10488 | tp->nvram_pagesize = 4096; | |
10489 | break; | |
10490 | case FLASH_5752PAGE_SIZE_264: | |
10491 | tp->nvram_pagesize = 264; | |
10492 | break; | |
361b4ac2 | 10493 | } |
8590a603 | 10494 | } else { |
361b4ac2 MC |
10495 | /* For eeprom, set pagesize to maximum eeprom size */ |
10496 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
10497 | ||
10498 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
10499 | tw32(NVRAM_CFG1, nvcfg1); | |
10500 | } | |
10501 | } | |
10502 | ||
d3c7b886 MC |
10503 | static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp) |
10504 | { | |
989a9d23 | 10505 | u32 nvcfg1, protect = 0; |
d3c7b886 MC |
10506 | |
10507 | nvcfg1 = tr32(NVRAM_CFG1); | |
10508 | ||
10509 | /* NVRAM protection for TPM */ | |
989a9d23 | 10510 | if (nvcfg1 & (1 << 27)) { |
d3c7b886 | 10511 | tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM; |
989a9d23 MC |
10512 | protect = 1; |
10513 | } | |
d3c7b886 | 10514 | |
989a9d23 MC |
10515 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; |
10516 | switch (nvcfg1) { | |
8590a603 MC |
10517 | case FLASH_5755VENDOR_ATMEL_FLASH_1: |
10518 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
10519 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
10520 | case FLASH_5755VENDOR_ATMEL_FLASH_5: | |
10521 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10522 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10523 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
10524 | tp->nvram_pagesize = 264; | |
10525 | if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 || | |
10526 | nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5) | |
10527 | tp->nvram_size = (protect ? 0x3e200 : | |
10528 | TG3_NVRAM_SIZE_512KB); | |
10529 | else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2) | |
10530 | tp->nvram_size = (protect ? 0x1f200 : | |
10531 | TG3_NVRAM_SIZE_256KB); | |
10532 | else | |
10533 | tp->nvram_size = (protect ? 0x1f200 : | |
10534 | TG3_NVRAM_SIZE_128KB); | |
10535 | break; | |
10536 | case FLASH_5752VENDOR_ST_M45PE10: | |
10537 | case FLASH_5752VENDOR_ST_M45PE20: | |
10538 | case FLASH_5752VENDOR_ST_M45PE40: | |
10539 | tp->nvram_jedecnum = JEDEC_ST; | |
10540 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10541 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
10542 | tp->nvram_pagesize = 256; | |
10543 | if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10) | |
10544 | tp->nvram_size = (protect ? | |
10545 | TG3_NVRAM_SIZE_64KB : | |
10546 | TG3_NVRAM_SIZE_128KB); | |
10547 | else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20) | |
10548 | tp->nvram_size = (protect ? | |
10549 | TG3_NVRAM_SIZE_64KB : | |
10550 | TG3_NVRAM_SIZE_256KB); | |
10551 | else | |
10552 | tp->nvram_size = (protect ? | |
10553 | TG3_NVRAM_SIZE_128KB : | |
10554 | TG3_NVRAM_SIZE_512KB); | |
10555 | break; | |
d3c7b886 MC |
10556 | } |
10557 | } | |
10558 | ||
1b27777a MC |
10559 | static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp) |
10560 | { | |
10561 | u32 nvcfg1; | |
10562 | ||
10563 | nvcfg1 = tr32(NVRAM_CFG1); | |
10564 | ||
10565 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
8590a603 MC |
10566 | case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ: |
10567 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
10568 | case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ: | |
10569 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
10570 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10571 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10572 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
1b27777a | 10573 | |
8590a603 MC |
10574 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
10575 | tw32(NVRAM_CFG1, nvcfg1); | |
10576 | break; | |
10577 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
10578 | case FLASH_5755VENDOR_ATMEL_FLASH_1: | |
10579 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
10580 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
10581 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10582 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10583 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
10584 | tp->nvram_pagesize = 264; | |
10585 | break; | |
10586 | case FLASH_5752VENDOR_ST_M45PE10: | |
10587 | case FLASH_5752VENDOR_ST_M45PE20: | |
10588 | case FLASH_5752VENDOR_ST_M45PE40: | |
10589 | tp->nvram_jedecnum = JEDEC_ST; | |
10590 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10591 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
10592 | tp->nvram_pagesize = 256; | |
10593 | break; | |
1b27777a MC |
10594 | } |
10595 | } | |
10596 | ||
6b91fa02 MC |
10597 | static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp) |
10598 | { | |
10599 | u32 nvcfg1, protect = 0; | |
10600 | ||
10601 | nvcfg1 = tr32(NVRAM_CFG1); | |
10602 | ||
10603 | /* NVRAM protection for TPM */ | |
10604 | if (nvcfg1 & (1 << 27)) { | |
10605 | tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM; | |
10606 | protect = 1; | |
10607 | } | |
10608 | ||
10609 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; | |
10610 | switch (nvcfg1) { | |
8590a603 MC |
10611 | case FLASH_5761VENDOR_ATMEL_ADB021D: |
10612 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
10613 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
10614 | case FLASH_5761VENDOR_ATMEL_ADB161D: | |
10615 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
10616 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
10617 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
10618 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
10619 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10620 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10621 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
10622 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
10623 | tp->nvram_pagesize = 256; | |
10624 | break; | |
10625 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
10626 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
10627 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
10628 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
10629 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
10630 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
10631 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
10632 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
10633 | tp->nvram_jedecnum = JEDEC_ST; | |
10634 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10635 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
10636 | tp->nvram_pagesize = 256; | |
10637 | break; | |
6b91fa02 MC |
10638 | } |
10639 | ||
10640 | if (protect) { | |
10641 | tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); | |
10642 | } else { | |
10643 | switch (nvcfg1) { | |
8590a603 MC |
10644 | case FLASH_5761VENDOR_ATMEL_ADB161D: |
10645 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
10646 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
10647 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
10648 | tp->nvram_size = TG3_NVRAM_SIZE_2MB; | |
10649 | break; | |
10650 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
10651 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
10652 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
10653 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
10654 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
10655 | break; | |
10656 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
10657 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
10658 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
10659 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
10660 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
10661 | break; | |
10662 | case FLASH_5761VENDOR_ATMEL_ADB021D: | |
10663 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
10664 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
10665 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
10666 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
10667 | break; | |
6b91fa02 MC |
10668 | } |
10669 | } | |
10670 | } | |
10671 | ||
b5d3772c MC |
10672 | static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp) |
10673 | { | |
10674 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10675 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10676 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
10677 | } | |
10678 | ||
321d32a0 MC |
10679 | static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp) |
10680 | { | |
10681 | u32 nvcfg1; | |
10682 | ||
10683 | nvcfg1 = tr32(NVRAM_CFG1); | |
10684 | ||
10685 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
10686 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
10687 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
10688 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10689 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10690 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
10691 | ||
10692 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
10693 | tw32(NVRAM_CFG1, nvcfg1); | |
10694 | return; | |
10695 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
10696 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
10697 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
10698 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
10699 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
10700 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
10701 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
10702 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10703 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10704 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
10705 | ||
10706 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
10707 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
10708 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
10709 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
10710 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
10711 | break; | |
10712 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
10713 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
10714 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
10715 | break; | |
10716 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
10717 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
10718 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
10719 | break; | |
10720 | } | |
10721 | break; | |
10722 | case FLASH_5752VENDOR_ST_M45PE10: | |
10723 | case FLASH_5752VENDOR_ST_M45PE20: | |
10724 | case FLASH_5752VENDOR_ST_M45PE40: | |
10725 | tp->nvram_jedecnum = JEDEC_ST; | |
10726 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10727 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
10728 | ||
10729 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
10730 | case FLASH_5752VENDOR_ST_M45PE10: | |
10731 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
10732 | break; | |
10733 | case FLASH_5752VENDOR_ST_M45PE20: | |
10734 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
10735 | break; | |
10736 | case FLASH_5752VENDOR_ST_M45PE40: | |
10737 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
10738 | break; | |
10739 | } | |
10740 | break; | |
10741 | default: | |
df259d8c | 10742 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM; |
321d32a0 MC |
10743 | return; |
10744 | } | |
10745 | ||
10746 | switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) { | |
10747 | case FLASH_5752PAGE_SIZE_256: | |
10748 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
10749 | tp->nvram_pagesize = 256; | |
10750 | break; | |
10751 | case FLASH_5752PAGE_SIZE_512: | |
10752 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
10753 | tp->nvram_pagesize = 512; | |
10754 | break; | |
10755 | case FLASH_5752PAGE_SIZE_1K: | |
10756 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
10757 | tp->nvram_pagesize = 1024; | |
10758 | break; | |
10759 | case FLASH_5752PAGE_SIZE_2K: | |
10760 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
10761 | tp->nvram_pagesize = 2048; | |
10762 | break; | |
10763 | case FLASH_5752PAGE_SIZE_4K: | |
10764 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
10765 | tp->nvram_pagesize = 4096; | |
10766 | break; | |
10767 | case FLASH_5752PAGE_SIZE_264: | |
10768 | tp->nvram_pagesize = 264; | |
10769 | break; | |
10770 | case FLASH_5752PAGE_SIZE_528: | |
10771 | tp->nvram_pagesize = 528; | |
10772 | break; | |
10773 | } | |
10774 | } | |
10775 | ||
1da177e4 LT |
10776 | /* Chips other than 5700/5701 use the NVRAM for fetching info. */ |
10777 | static void __devinit tg3_nvram_init(struct tg3 *tp) | |
10778 | { | |
1da177e4 LT |
10779 | tw32_f(GRC_EEPROM_ADDR, |
10780 | (EEPROM_ADDR_FSM_RESET | | |
10781 | (EEPROM_DEFAULT_CLOCK_PERIOD << | |
10782 | EEPROM_ADDR_CLKPERD_SHIFT))); | |
10783 | ||
9d57f01c | 10784 | msleep(1); |
1da177e4 LT |
10785 | |
10786 | /* Enable seeprom accesses. */ | |
10787 | tw32_f(GRC_LOCAL_CTRL, | |
10788 | tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); | |
10789 | udelay(100); | |
10790 | ||
10791 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
10792 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
10793 | tp->tg3_flags |= TG3_FLAG_NVRAM; | |
10794 | ||
ec41c7df MC |
10795 | if (tg3_nvram_lock(tp)) { |
10796 | printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, " | |
10797 | "tg3_nvram_init failed.\n", tp->dev->name); | |
10798 | return; | |
10799 | } | |
e6af301b | 10800 | tg3_enable_nvram_access(tp); |
1da177e4 | 10801 | |
989a9d23 MC |
10802 | tp->nvram_size = 0; |
10803 | ||
361b4ac2 MC |
10804 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) |
10805 | tg3_get_5752_nvram_info(tp); | |
d3c7b886 MC |
10806 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
10807 | tg3_get_5755_nvram_info(tp); | |
d30cdd28 | 10808 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
57e6983c MC |
10809 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
10810 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1b27777a | 10811 | tg3_get_5787_nvram_info(tp); |
6b91fa02 MC |
10812 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
10813 | tg3_get_5761_nvram_info(tp); | |
b5d3772c MC |
10814 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
10815 | tg3_get_5906_nvram_info(tp); | |
321d32a0 MC |
10816 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
10817 | tg3_get_57780_nvram_info(tp); | |
361b4ac2 MC |
10818 | else |
10819 | tg3_get_nvram_info(tp); | |
10820 | ||
989a9d23 MC |
10821 | if (tp->nvram_size == 0) |
10822 | tg3_get_nvram_size(tp); | |
1da177e4 | 10823 | |
e6af301b | 10824 | tg3_disable_nvram_access(tp); |
381291b7 | 10825 | tg3_nvram_unlock(tp); |
1da177e4 LT |
10826 | |
10827 | } else { | |
10828 | tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED); | |
10829 | ||
10830 | tg3_get_eeprom_size(tp); | |
10831 | } | |
10832 | } | |
10833 | ||
1da177e4 LT |
10834 | static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, |
10835 | u32 offset, u32 len, u8 *buf) | |
10836 | { | |
10837 | int i, j, rc = 0; | |
10838 | u32 val; | |
10839 | ||
10840 | for (i = 0; i < len; i += 4) { | |
b9fc7dc5 | 10841 | u32 addr; |
a9dc529d | 10842 | __be32 data; |
1da177e4 LT |
10843 | |
10844 | addr = offset + i; | |
10845 | ||
10846 | memcpy(&data, buf + i, 4); | |
10847 | ||
62cedd11 MC |
10848 | /* |
10849 | * The SEEPROM interface expects the data to always be opposite | |
10850 | * the native endian format. We accomplish this by reversing | |
10851 | * all the operations that would have been performed on the | |
10852 | * data from a call to tg3_nvram_read_be32(). | |
10853 | */ | |
10854 | tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data))); | |
1da177e4 LT |
10855 | |
10856 | val = tr32(GRC_EEPROM_ADDR); | |
10857 | tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE); | |
10858 | ||
10859 | val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK | | |
10860 | EEPROM_ADDR_READ); | |
10861 | tw32(GRC_EEPROM_ADDR, val | | |
10862 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
10863 | (addr & EEPROM_ADDR_ADDR_MASK) | | |
10864 | EEPROM_ADDR_START | | |
10865 | EEPROM_ADDR_WRITE); | |
6aa20a22 | 10866 | |
9d57f01c | 10867 | for (j = 0; j < 1000; j++) { |
1da177e4 LT |
10868 | val = tr32(GRC_EEPROM_ADDR); |
10869 | ||
10870 | if (val & EEPROM_ADDR_COMPLETE) | |
10871 | break; | |
9d57f01c | 10872 | msleep(1); |
1da177e4 LT |
10873 | } |
10874 | if (!(val & EEPROM_ADDR_COMPLETE)) { | |
10875 | rc = -EBUSY; | |
10876 | break; | |
10877 | } | |
10878 | } | |
10879 | ||
10880 | return rc; | |
10881 | } | |
10882 | ||
10883 | /* offset and length are dword aligned */ | |
10884 | static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, | |
10885 | u8 *buf) | |
10886 | { | |
10887 | int ret = 0; | |
10888 | u32 pagesize = tp->nvram_pagesize; | |
10889 | u32 pagemask = pagesize - 1; | |
10890 | u32 nvram_cmd; | |
10891 | u8 *tmp; | |
10892 | ||
10893 | tmp = kmalloc(pagesize, GFP_KERNEL); | |
10894 | if (tmp == NULL) | |
10895 | return -ENOMEM; | |
10896 | ||
10897 | while (len) { | |
10898 | int j; | |
e6af301b | 10899 | u32 phy_addr, page_off, size; |
1da177e4 LT |
10900 | |
10901 | phy_addr = offset & ~pagemask; | |
6aa20a22 | 10902 | |
1da177e4 | 10903 | for (j = 0; j < pagesize; j += 4) { |
a9dc529d MC |
10904 | ret = tg3_nvram_read_be32(tp, phy_addr + j, |
10905 | (__be32 *) (tmp + j)); | |
10906 | if (ret) | |
1da177e4 LT |
10907 | break; |
10908 | } | |
10909 | if (ret) | |
10910 | break; | |
10911 | ||
10912 | page_off = offset & pagemask; | |
10913 | size = pagesize; | |
10914 | if (len < size) | |
10915 | size = len; | |
10916 | ||
10917 | len -= size; | |
10918 | ||
10919 | memcpy(tmp + page_off, buf, size); | |
10920 | ||
10921 | offset = offset + (pagesize - page_off); | |
10922 | ||
e6af301b | 10923 | tg3_enable_nvram_access(tp); |
1da177e4 LT |
10924 | |
10925 | /* | |
10926 | * Before we can erase the flash page, we need | |
10927 | * to issue a special "write enable" command. | |
10928 | */ | |
10929 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
10930 | ||
10931 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
10932 | break; | |
10933 | ||
10934 | /* Erase the target page */ | |
10935 | tw32(NVRAM_ADDR, phy_addr); | |
10936 | ||
10937 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR | | |
10938 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE; | |
10939 | ||
10940 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
10941 | break; | |
10942 | ||
10943 | /* Issue another write enable to start the write. */ | |
10944 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
10945 | ||
10946 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
10947 | break; | |
10948 | ||
10949 | for (j = 0; j < pagesize; j += 4) { | |
b9fc7dc5 | 10950 | __be32 data; |
1da177e4 | 10951 | |
b9fc7dc5 | 10952 | data = *((__be32 *) (tmp + j)); |
a9dc529d | 10953 | |
b9fc7dc5 | 10954 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 LT |
10955 | |
10956 | tw32(NVRAM_ADDR, phy_addr + j); | |
10957 | ||
10958 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | | |
10959 | NVRAM_CMD_WR; | |
10960 | ||
10961 | if (j == 0) | |
10962 | nvram_cmd |= NVRAM_CMD_FIRST; | |
10963 | else if (j == (pagesize - 4)) | |
10964 | nvram_cmd |= NVRAM_CMD_LAST; | |
10965 | ||
10966 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
10967 | break; | |
10968 | } | |
10969 | if (ret) | |
10970 | break; | |
10971 | } | |
10972 | ||
10973 | nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
10974 | tg3_nvram_exec_cmd(tp, nvram_cmd); | |
10975 | ||
10976 | kfree(tmp); | |
10977 | ||
10978 | return ret; | |
10979 | } | |
10980 | ||
10981 | /* offset and length are dword aligned */ | |
10982 | static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, | |
10983 | u8 *buf) | |
10984 | { | |
10985 | int i, ret = 0; | |
10986 | ||
10987 | for (i = 0; i < len; i += 4, offset += 4) { | |
b9fc7dc5 AV |
10988 | u32 page_off, phy_addr, nvram_cmd; |
10989 | __be32 data; | |
1da177e4 LT |
10990 | |
10991 | memcpy(&data, buf + i, 4); | |
b9fc7dc5 | 10992 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 LT |
10993 | |
10994 | page_off = offset % tp->nvram_pagesize; | |
10995 | ||
1820180b | 10996 | phy_addr = tg3_nvram_phys_addr(tp, offset); |
1da177e4 LT |
10997 | |
10998 | tw32(NVRAM_ADDR, phy_addr); | |
10999 | ||
11000 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR; | |
11001 | ||
11002 | if ((page_off == 0) || (i == 0)) | |
11003 | nvram_cmd |= NVRAM_CMD_FIRST; | |
f6d9a256 | 11004 | if (page_off == (tp->nvram_pagesize - 4)) |
1da177e4 LT |
11005 | nvram_cmd |= NVRAM_CMD_LAST; |
11006 | ||
11007 | if (i == (len - 4)) | |
11008 | nvram_cmd |= NVRAM_CMD_LAST; | |
11009 | ||
321d32a0 MC |
11010 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 && |
11011 | !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) && | |
4c987487 MC |
11012 | (tp->nvram_jedecnum == JEDEC_ST) && |
11013 | (nvram_cmd & NVRAM_CMD_FIRST)) { | |
1da177e4 LT |
11014 | |
11015 | if ((ret = tg3_nvram_exec_cmd(tp, | |
11016 | NVRAM_CMD_WREN | NVRAM_CMD_GO | | |
11017 | NVRAM_CMD_DONE))) | |
11018 | ||
11019 | break; | |
11020 | } | |
11021 | if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) { | |
11022 | /* We always do complete word writes to eeprom. */ | |
11023 | nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST); | |
11024 | } | |
11025 | ||
11026 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
11027 | break; | |
11028 | } | |
11029 | return ret; | |
11030 | } | |
11031 | ||
11032 | /* offset and length are dword aligned */ | |
11033 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) | |
11034 | { | |
11035 | int ret; | |
11036 | ||
1da177e4 | 11037 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { |
314fba34 MC |
11038 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & |
11039 | ~GRC_LCLCTRL_GPIO_OUTPUT1); | |
1da177e4 LT |
11040 | udelay(40); |
11041 | } | |
11042 | ||
11043 | if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) { | |
11044 | ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); | |
11045 | } | |
11046 | else { | |
11047 | u32 grc_mode; | |
11048 | ||
ec41c7df MC |
11049 | ret = tg3_nvram_lock(tp); |
11050 | if (ret) | |
11051 | return ret; | |
1da177e4 | 11052 | |
e6af301b MC |
11053 | tg3_enable_nvram_access(tp); |
11054 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
11055 | !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) | |
1da177e4 | 11056 | tw32(NVRAM_WRITE1, 0x406); |
1da177e4 LT |
11057 | |
11058 | grc_mode = tr32(GRC_MODE); | |
11059 | tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE); | |
11060 | ||
11061 | if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) || | |
11062 | !(tp->tg3_flags2 & TG3_FLG2_FLASH)) { | |
11063 | ||
11064 | ret = tg3_nvram_write_block_buffered(tp, offset, len, | |
11065 | buf); | |
11066 | } | |
11067 | else { | |
11068 | ret = tg3_nvram_write_block_unbuffered(tp, offset, len, | |
11069 | buf); | |
11070 | } | |
11071 | ||
11072 | grc_mode = tr32(GRC_MODE); | |
11073 | tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE); | |
11074 | ||
e6af301b | 11075 | tg3_disable_nvram_access(tp); |
1da177e4 LT |
11076 | tg3_nvram_unlock(tp); |
11077 | } | |
11078 | ||
11079 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { | |
314fba34 | 11080 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
1da177e4 LT |
11081 | udelay(40); |
11082 | } | |
11083 | ||
11084 | return ret; | |
11085 | } | |
11086 | ||
11087 | struct subsys_tbl_ent { | |
11088 | u16 subsys_vendor, subsys_devid; | |
11089 | u32 phy_id; | |
11090 | }; | |
11091 | ||
11092 | static struct subsys_tbl_ent subsys_id_to_phy_id[] = { | |
11093 | /* Broadcom boards. */ | |
11094 | { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */ | |
11095 | { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */ | |
11096 | { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */ | |
11097 | { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */ | |
11098 | { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */ | |
11099 | { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */ | |
11100 | { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */ | |
11101 | { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */ | |
11102 | { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */ | |
11103 | { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */ | |
11104 | { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */ | |
11105 | ||
11106 | /* 3com boards. */ | |
11107 | { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */ | |
11108 | { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */ | |
11109 | { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */ | |
11110 | { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */ | |
11111 | { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */ | |
11112 | ||
11113 | /* DELL boards. */ | |
11114 | { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */ | |
11115 | { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */ | |
11116 | { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */ | |
11117 | { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */ | |
11118 | ||
11119 | /* Compaq boards. */ | |
11120 | { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */ | |
11121 | { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */ | |
11122 | { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */ | |
11123 | { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */ | |
11124 | { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */ | |
11125 | ||
11126 | /* IBM boards. */ | |
11127 | { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */ | |
11128 | }; | |
11129 | ||
11130 | static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp) | |
11131 | { | |
11132 | int i; | |
11133 | ||
11134 | for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) { | |
11135 | if ((subsys_id_to_phy_id[i].subsys_vendor == | |
11136 | tp->pdev->subsystem_vendor) && | |
11137 | (subsys_id_to_phy_id[i].subsys_devid == | |
11138 | tp->pdev->subsystem_device)) | |
11139 | return &subsys_id_to_phy_id[i]; | |
11140 | } | |
11141 | return NULL; | |
11142 | } | |
11143 | ||
7d0c41ef | 11144 | static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) |
1da177e4 | 11145 | { |
1da177e4 | 11146 | u32 val; |
caf636c7 MC |
11147 | u16 pmcsr; |
11148 | ||
11149 | /* On some early chips the SRAM cannot be accessed in D3hot state, | |
11150 | * so need make sure we're in D0. | |
11151 | */ | |
11152 | pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr); | |
11153 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
11154 | pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr); | |
11155 | msleep(1); | |
7d0c41ef MC |
11156 | |
11157 | /* Make sure register accesses (indirect or otherwise) | |
11158 | * will function correctly. | |
11159 | */ | |
11160 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
11161 | tp->misc_host_ctrl); | |
1da177e4 | 11162 | |
f49639e6 DM |
11163 | /* The memory arbiter has to be enabled in order for SRAM accesses |
11164 | * to succeed. Normally on powerup the tg3 chip firmware will make | |
11165 | * sure it is enabled, but other entities such as system netboot | |
11166 | * code might disable it. | |
11167 | */ | |
11168 | val = tr32(MEMARB_MODE); | |
11169 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); | |
11170 | ||
1da177e4 | 11171 | tp->phy_id = PHY_ID_INVALID; |
7d0c41ef MC |
11172 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; |
11173 | ||
a85feb8c GZ |
11174 | /* Assume an onboard device and WOL capable by default. */ |
11175 | tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP; | |
72b845e0 | 11176 | |
b5d3772c | 11177 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
9d26e213 | 11178 | if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { |
b5d3772c | 11179 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; |
9d26e213 MC |
11180 | tp->tg3_flags2 |= TG3_FLG2_IS_NIC; |
11181 | } | |
0527ba35 MC |
11182 | val = tr32(VCPU_CFGSHDW); |
11183 | if (val & VCPU_CFGSHDW_ASPM_DBNC) | |
8ed5d97e | 11184 | tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; |
0527ba35 | 11185 | if ((val & VCPU_CFGSHDW_WOL_ENABLE) && |
2023276e | 11186 | (val & VCPU_CFGSHDW_WOL_MAGPKT)) |
0527ba35 | 11187 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; |
05ac4cb7 | 11188 | goto done; |
b5d3772c MC |
11189 | } |
11190 | ||
1da177e4 LT |
11191 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
11192 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
11193 | u32 nic_cfg, led_cfg; | |
a9daf367 | 11194 | u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id; |
7d0c41ef | 11195 | int eeprom_phy_serdes = 0; |
1da177e4 LT |
11196 | |
11197 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
11198 | tp->nic_sram_data_cfg = nic_cfg; | |
11199 | ||
11200 | tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); | |
11201 | ver >>= NIC_SRAM_DATA_VER_SHIFT; | |
11202 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) && | |
11203 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) && | |
11204 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) && | |
11205 | (ver > 0) && (ver < 0x100)) | |
11206 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); | |
11207 | ||
a9daf367 MC |
11208 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
11209 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); | |
11210 | ||
1da177e4 LT |
11211 | if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == |
11212 | NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) | |
11213 | eeprom_phy_serdes = 1; | |
11214 | ||
11215 | tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); | |
11216 | if (nic_phy_id != 0) { | |
11217 | u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK; | |
11218 | u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK; | |
11219 | ||
11220 | eeprom_phy_id = (id1 >> 16) << 10; | |
11221 | eeprom_phy_id |= (id2 & 0xfc00) << 16; | |
11222 | eeprom_phy_id |= (id2 & 0x03ff) << 0; | |
11223 | } else | |
11224 | eeprom_phy_id = 0; | |
11225 | ||
7d0c41ef | 11226 | tp->phy_id = eeprom_phy_id; |
747e8f8b | 11227 | if (eeprom_phy_serdes) { |
a4e2b347 | 11228 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) |
747e8f8b MC |
11229 | tp->tg3_flags2 |= TG3_FLG2_MII_SERDES; |
11230 | else | |
11231 | tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES; | |
11232 | } | |
7d0c41ef | 11233 | |
cbf46853 | 11234 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
1da177e4 LT |
11235 | led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | |
11236 | SHASTA_EXT_LED_MODE_MASK); | |
cbf46853 | 11237 | else |
1da177e4 LT |
11238 | led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK; |
11239 | ||
11240 | switch (led_cfg) { | |
11241 | default: | |
11242 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1: | |
11243 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
11244 | break; | |
11245 | ||
11246 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2: | |
11247 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
11248 | break; | |
11249 | ||
11250 | case NIC_SRAM_DATA_CFG_LED_MODE_MAC: | |
11251 | tp->led_ctrl = LED_CTRL_MODE_MAC; | |
9ba27794 MC |
11252 | |
11253 | /* Default to PHY_1_MODE if 0 (MAC_MODE) is | |
11254 | * read on some older 5700/5701 bootcode. | |
11255 | */ | |
11256 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
11257 | ASIC_REV_5700 || | |
11258 | GET_ASIC_REV(tp->pci_chip_rev_id) == | |
11259 | ASIC_REV_5701) | |
11260 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
11261 | ||
1da177e4 LT |
11262 | break; |
11263 | ||
11264 | case SHASTA_EXT_LED_SHARED: | |
11265 | tp->led_ctrl = LED_CTRL_MODE_SHARED; | |
11266 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && | |
11267 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A1) | |
11268 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
11269 | LED_CTRL_MODE_PHY_2); | |
11270 | break; | |
11271 | ||
11272 | case SHASTA_EXT_LED_MAC: | |
11273 | tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; | |
11274 | break; | |
11275 | ||
11276 | case SHASTA_EXT_LED_COMBO: | |
11277 | tp->led_ctrl = LED_CTRL_MODE_COMBO; | |
11278 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) | |
11279 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
11280 | LED_CTRL_MODE_PHY_2); | |
11281 | break; | |
11282 | ||
855e1111 | 11283 | } |
1da177e4 LT |
11284 | |
11285 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
11286 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && | |
11287 | tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
11288 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
11289 | ||
b2a5c19c MC |
11290 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) |
11291 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
5f60891b | 11292 | |
9d26e213 | 11293 | if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) { |
1da177e4 | 11294 | tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT; |
9d26e213 MC |
11295 | if ((tp->pdev->subsystem_vendor == |
11296 | PCI_VENDOR_ID_ARIMA) && | |
11297 | (tp->pdev->subsystem_device == 0x205a || | |
11298 | tp->pdev->subsystem_device == 0x2063)) | |
11299 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; | |
11300 | } else { | |
f49639e6 | 11301 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; |
9d26e213 MC |
11302 | tp->tg3_flags2 |= TG3_FLG2_IS_NIC; |
11303 | } | |
1da177e4 LT |
11304 | |
11305 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
11306 | tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; | |
cbf46853 | 11307 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
1da177e4 LT |
11308 | tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; |
11309 | } | |
b2b98d4a MC |
11310 | |
11311 | if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) && | |
11312 | (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) | |
0d3031d9 | 11313 | tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE; |
b2b98d4a | 11314 | |
a85feb8c GZ |
11315 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES && |
11316 | !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)) | |
11317 | tp->tg3_flags &= ~TG3_FLAG_WOL_CAP; | |
1da177e4 | 11318 | |
12dac075 | 11319 | if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) && |
05ac4cb7 | 11320 | (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) |
0527ba35 MC |
11321 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; |
11322 | ||
1da177e4 LT |
11323 | if (cfg2 & (1 << 17)) |
11324 | tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING; | |
11325 | ||
11326 | /* serdes signal pre-emphasis in register 0x590 set by */ | |
11327 | /* bootcode if bit 18 is set */ | |
11328 | if (cfg2 & (1 << 18)) | |
11329 | tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS; | |
8ed5d97e | 11330 | |
321d32a0 MC |
11331 | if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
11332 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) && | |
6833c043 MC |
11333 | (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) |
11334 | tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD; | |
11335 | ||
8ed5d97e MC |
11336 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { |
11337 | u32 cfg3; | |
11338 | ||
11339 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); | |
11340 | if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) | |
11341 | tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; | |
11342 | } | |
a9daf367 MC |
11343 | |
11344 | if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE) | |
11345 | tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE; | |
11346 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN) | |
11347 | tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN; | |
11348 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN) | |
11349 | tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN; | |
1da177e4 | 11350 | } |
05ac4cb7 MC |
11351 | done: |
11352 | device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP); | |
11353 | device_set_wakeup_enable(&tp->pdev->dev, | |
11354 | tp->tg3_flags & TG3_FLAG_WOL_ENABLE); | |
7d0c41ef MC |
11355 | } |
11356 | ||
b2a5c19c MC |
11357 | static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd) |
11358 | { | |
11359 | int i; | |
11360 | u32 val; | |
11361 | ||
11362 | tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START); | |
11363 | tw32(OTP_CTRL, cmd); | |
11364 | ||
11365 | /* Wait for up to 1 ms for command to execute. */ | |
11366 | for (i = 0; i < 100; i++) { | |
11367 | val = tr32(OTP_STATUS); | |
11368 | if (val & OTP_STATUS_CMD_DONE) | |
11369 | break; | |
11370 | udelay(10); | |
11371 | } | |
11372 | ||
11373 | return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; | |
11374 | } | |
11375 | ||
11376 | /* Read the gphy configuration from the OTP region of the chip. The gphy | |
11377 | * configuration is a 32-bit value that straddles the alignment boundary. | |
11378 | * We do two 32-bit reads and then shift and merge the results. | |
11379 | */ | |
11380 | static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp) | |
11381 | { | |
11382 | u32 bhalf_otp, thalf_otp; | |
11383 | ||
11384 | tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC); | |
11385 | ||
11386 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) | |
11387 | return 0; | |
11388 | ||
11389 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1); | |
11390 | ||
11391 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
11392 | return 0; | |
11393 | ||
11394 | thalf_otp = tr32(OTP_READ_DATA); | |
11395 | ||
11396 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2); | |
11397 | ||
11398 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
11399 | return 0; | |
11400 | ||
11401 | bhalf_otp = tr32(OTP_READ_DATA); | |
11402 | ||
11403 | return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16); | |
11404 | } | |
11405 | ||
7d0c41ef MC |
11406 | static int __devinit tg3_phy_probe(struct tg3 *tp) |
11407 | { | |
11408 | u32 hw_phy_id_1, hw_phy_id_2; | |
11409 | u32 hw_phy_id, hw_phy_id_masked; | |
11410 | int err; | |
1da177e4 | 11411 | |
b02fd9e3 MC |
11412 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) |
11413 | return tg3_phy_init(tp); | |
11414 | ||
1da177e4 | 11415 | /* Reading the PHY ID register can conflict with ASF |
877d0310 | 11416 | * firmware access to the PHY hardware. |
1da177e4 LT |
11417 | */ |
11418 | err = 0; | |
0d3031d9 MC |
11419 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || |
11420 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
1da177e4 LT |
11421 | hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID; |
11422 | } else { | |
11423 | /* Now read the physical PHY_ID from the chip and verify | |
11424 | * that it is sane. If it doesn't look good, we fall back | |
11425 | * to either the hard-coded table based PHY_ID and failing | |
11426 | * that the value found in the eeprom area. | |
11427 | */ | |
11428 | err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); | |
11429 | err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); | |
11430 | ||
11431 | hw_phy_id = (hw_phy_id_1 & 0xffff) << 10; | |
11432 | hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16; | |
11433 | hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0; | |
11434 | ||
11435 | hw_phy_id_masked = hw_phy_id & PHY_ID_MASK; | |
11436 | } | |
11437 | ||
11438 | if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) { | |
11439 | tp->phy_id = hw_phy_id; | |
11440 | if (hw_phy_id_masked == PHY_ID_BCM8002) | |
11441 | tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES; | |
da6b2d01 MC |
11442 | else |
11443 | tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES; | |
1da177e4 | 11444 | } else { |
7d0c41ef MC |
11445 | if (tp->phy_id != PHY_ID_INVALID) { |
11446 | /* Do nothing, phy ID already set up in | |
11447 | * tg3_get_eeprom_hw_cfg(). | |
11448 | */ | |
1da177e4 LT |
11449 | } else { |
11450 | struct subsys_tbl_ent *p; | |
11451 | ||
11452 | /* No eeprom signature? Try the hardcoded | |
11453 | * subsys device table. | |
11454 | */ | |
11455 | p = lookup_by_subsys(tp); | |
11456 | if (!p) | |
11457 | return -ENODEV; | |
11458 | ||
11459 | tp->phy_id = p->phy_id; | |
11460 | if (!tp->phy_id || | |
11461 | tp->phy_id == PHY_ID_BCM8002) | |
11462 | tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES; | |
11463 | } | |
11464 | } | |
11465 | ||
747e8f8b | 11466 | if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) && |
0d3031d9 | 11467 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) && |
1da177e4 | 11468 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { |
3600d918 | 11469 | u32 bmsr, adv_reg, tg3_ctrl, mask; |
1da177e4 LT |
11470 | |
11471 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
11472 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
11473 | (bmsr & BMSR_LSTATUS)) | |
11474 | goto skip_phy_reset; | |
6aa20a22 | 11475 | |
1da177e4 LT |
11476 | err = tg3_phy_reset(tp); |
11477 | if (err) | |
11478 | return err; | |
11479 | ||
11480 | adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL | | |
11481 | ADVERTISE_100HALF | ADVERTISE_100FULL | | |
11482 | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
11483 | tg3_ctrl = 0; | |
11484 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) { | |
11485 | tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF | | |
11486 | MII_TG3_CTRL_ADV_1000_FULL); | |
11487 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
11488 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
11489 | tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER | | |
11490 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
11491 | } | |
11492 | ||
3600d918 MC |
11493 | mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
11494 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
11495 | ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full); | |
11496 | if (!tg3_copper_is_advertising_all(tp, mask)) { | |
1da177e4 LT |
11497 | tg3_writephy(tp, MII_ADVERTISE, adv_reg); |
11498 | ||
11499 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) | |
11500 | tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl); | |
11501 | ||
11502 | tg3_writephy(tp, MII_BMCR, | |
11503 | BMCR_ANENABLE | BMCR_ANRESTART); | |
11504 | } | |
11505 | tg3_phy_set_wirespeed(tp); | |
11506 | ||
11507 | tg3_writephy(tp, MII_ADVERTISE, adv_reg); | |
11508 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) | |
11509 | tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl); | |
11510 | } | |
11511 | ||
11512 | skip_phy_reset: | |
11513 | if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { | |
11514 | err = tg3_init_5401phy_dsp(tp); | |
11515 | if (err) | |
11516 | return err; | |
11517 | } | |
11518 | ||
11519 | if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) { | |
11520 | err = tg3_init_5401phy_dsp(tp); | |
11521 | } | |
11522 | ||
747e8f8b | 11523 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) |
1da177e4 LT |
11524 | tp->link_config.advertising = |
11525 | (ADVERTISED_1000baseT_Half | | |
11526 | ADVERTISED_1000baseT_Full | | |
11527 | ADVERTISED_Autoneg | | |
11528 | ADVERTISED_FIBRE); | |
11529 | if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) | |
11530 | tp->link_config.advertising &= | |
11531 | ~(ADVERTISED_1000baseT_Half | | |
11532 | ADVERTISED_1000baseT_Full); | |
11533 | ||
11534 | return err; | |
11535 | } | |
11536 | ||
11537 | static void __devinit tg3_read_partno(struct tg3 *tp) | |
11538 | { | |
6d348f2c | 11539 | unsigned char vpd_data[256]; /* in little-endian format */ |
af2c6a4a | 11540 | unsigned int i; |
1b27777a | 11541 | u32 magic; |
1da177e4 | 11542 | |
df259d8c MC |
11543 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || |
11544 | tg3_nvram_read(tp, 0x0, &magic)) | |
f49639e6 | 11545 | goto out_not_found; |
1da177e4 | 11546 | |
1820180b | 11547 | if (magic == TG3_EEPROM_MAGIC) { |
1b27777a MC |
11548 | for (i = 0; i < 256; i += 4) { |
11549 | u32 tmp; | |
1da177e4 | 11550 | |
6d348f2c MC |
11551 | /* The data is in little-endian format in NVRAM. |
11552 | * Use the big-endian read routines to preserve | |
11553 | * the byte order as it exists in NVRAM. | |
11554 | */ | |
11555 | if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp)) | |
1b27777a MC |
11556 | goto out_not_found; |
11557 | ||
6d348f2c | 11558 | memcpy(&vpd_data[i], &tmp, sizeof(tmp)); |
1b27777a MC |
11559 | } |
11560 | } else { | |
11561 | int vpd_cap; | |
11562 | ||
11563 | vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD); | |
11564 | for (i = 0; i < 256; i += 4) { | |
11565 | u32 tmp, j = 0; | |
b9fc7dc5 | 11566 | __le32 v; |
1b27777a MC |
11567 | u16 tmp16; |
11568 | ||
11569 | pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR, | |
11570 | i); | |
11571 | while (j++ < 100) { | |
11572 | pci_read_config_word(tp->pdev, vpd_cap + | |
11573 | PCI_VPD_ADDR, &tmp16); | |
11574 | if (tmp16 & 0x8000) | |
11575 | break; | |
11576 | msleep(1); | |
11577 | } | |
f49639e6 DM |
11578 | if (!(tmp16 & 0x8000)) |
11579 | goto out_not_found; | |
11580 | ||
1b27777a MC |
11581 | pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA, |
11582 | &tmp); | |
b9fc7dc5 | 11583 | v = cpu_to_le32(tmp); |
6d348f2c | 11584 | memcpy(&vpd_data[i], &v, sizeof(v)); |
1b27777a | 11585 | } |
1da177e4 LT |
11586 | } |
11587 | ||
11588 | /* Now parse and find the part number. */ | |
af2c6a4a | 11589 | for (i = 0; i < 254; ) { |
1da177e4 | 11590 | unsigned char val = vpd_data[i]; |
af2c6a4a | 11591 | unsigned int block_end; |
1da177e4 LT |
11592 | |
11593 | if (val == 0x82 || val == 0x91) { | |
11594 | i = (i + 3 + | |
11595 | (vpd_data[i + 1] + | |
11596 | (vpd_data[i + 2] << 8))); | |
11597 | continue; | |
11598 | } | |
11599 | ||
11600 | if (val != 0x90) | |
11601 | goto out_not_found; | |
11602 | ||
11603 | block_end = (i + 3 + | |
11604 | (vpd_data[i + 1] + | |
11605 | (vpd_data[i + 2] << 8))); | |
11606 | i += 3; | |
af2c6a4a MC |
11607 | |
11608 | if (block_end > 256) | |
11609 | goto out_not_found; | |
11610 | ||
11611 | while (i < (block_end - 2)) { | |
1da177e4 LT |
11612 | if (vpd_data[i + 0] == 'P' && |
11613 | vpd_data[i + 1] == 'N') { | |
11614 | int partno_len = vpd_data[i + 2]; | |
11615 | ||
af2c6a4a MC |
11616 | i += 3; |
11617 | if (partno_len > 24 || (partno_len + i) > 256) | |
1da177e4 LT |
11618 | goto out_not_found; |
11619 | ||
11620 | memcpy(tp->board_part_number, | |
af2c6a4a | 11621 | &vpd_data[i], partno_len); |
1da177e4 LT |
11622 | |
11623 | /* Success. */ | |
11624 | return; | |
11625 | } | |
af2c6a4a | 11626 | i += 3 + vpd_data[i + 2]; |
1da177e4 LT |
11627 | } |
11628 | ||
11629 | /* Part number not found. */ | |
11630 | goto out_not_found; | |
11631 | } | |
11632 | ||
11633 | out_not_found: | |
b5d3772c MC |
11634 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
11635 | strcpy(tp->board_part_number, "BCM95906"); | |
df259d8c MC |
11636 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 && |
11637 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) | |
11638 | strcpy(tp->board_part_number, "BCM57780"); | |
11639 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 && | |
11640 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) | |
11641 | strcpy(tp->board_part_number, "BCM57760"); | |
11642 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 && | |
11643 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) | |
11644 | strcpy(tp->board_part_number, "BCM57790"); | |
5e7ccf20 MC |
11645 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 && |
11646 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) | |
11647 | strcpy(tp->board_part_number, "BCM57788"); | |
b5d3772c MC |
11648 | else |
11649 | strcpy(tp->board_part_number, "none"); | |
1da177e4 LT |
11650 | } |
11651 | ||
9c8a620e MC |
11652 | static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) |
11653 | { | |
11654 | u32 val; | |
11655 | ||
e4f34110 | 11656 | if (tg3_nvram_read(tp, offset, &val) || |
9c8a620e | 11657 | (val & 0xfc000000) != 0x0c000000 || |
e4f34110 | 11658 | tg3_nvram_read(tp, offset + 4, &val) || |
9c8a620e MC |
11659 | val != 0) |
11660 | return 0; | |
11661 | ||
11662 | return 1; | |
11663 | } | |
11664 | ||
acd9c119 MC |
11665 | static void __devinit tg3_read_bc_ver(struct tg3 *tp) |
11666 | { | |
ff3a7cb2 | 11667 | u32 val, offset, start, ver_offset; |
acd9c119 | 11668 | int i; |
ff3a7cb2 | 11669 | bool newver = false; |
acd9c119 MC |
11670 | |
11671 | if (tg3_nvram_read(tp, 0xc, &offset) || | |
11672 | tg3_nvram_read(tp, 0x4, &start)) | |
11673 | return; | |
11674 | ||
11675 | offset = tg3_nvram_logical_addr(tp, offset); | |
11676 | ||
ff3a7cb2 | 11677 | if (tg3_nvram_read(tp, offset, &val)) |
acd9c119 MC |
11678 | return; |
11679 | ||
ff3a7cb2 MC |
11680 | if ((val & 0xfc000000) == 0x0c000000) { |
11681 | if (tg3_nvram_read(tp, offset + 4, &val)) | |
acd9c119 MC |
11682 | return; |
11683 | ||
ff3a7cb2 MC |
11684 | if (val == 0) |
11685 | newver = true; | |
11686 | } | |
11687 | ||
11688 | if (newver) { | |
11689 | if (tg3_nvram_read(tp, offset + 8, &ver_offset)) | |
11690 | return; | |
11691 | ||
11692 | offset = offset + ver_offset - start; | |
11693 | for (i = 0; i < 16; i += 4) { | |
11694 | __be32 v; | |
11695 | if (tg3_nvram_read_be32(tp, offset + i, &v)) | |
11696 | return; | |
11697 | ||
11698 | memcpy(tp->fw_ver + i, &v, sizeof(v)); | |
11699 | } | |
11700 | } else { | |
11701 | u32 major, minor; | |
11702 | ||
11703 | if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) | |
11704 | return; | |
11705 | ||
11706 | major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >> | |
11707 | TG3_NVM_BCVER_MAJSFT; | |
11708 | minor = ver_offset & TG3_NVM_BCVER_MINMSK; | |
11709 | snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor); | |
acd9c119 MC |
11710 | } |
11711 | } | |
11712 | ||
a6f6cb1c MC |
11713 | static void __devinit tg3_read_hwsb_ver(struct tg3 *tp) |
11714 | { | |
11715 | u32 val, major, minor; | |
11716 | ||
11717 | /* Use native endian representation */ | |
11718 | if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) | |
11719 | return; | |
11720 | ||
11721 | major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >> | |
11722 | TG3_NVM_HWSB_CFG1_MAJSFT; | |
11723 | minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >> | |
11724 | TG3_NVM_HWSB_CFG1_MINSFT; | |
11725 | ||
11726 | snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); | |
11727 | } | |
11728 | ||
dfe00d7d MC |
11729 | static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) |
11730 | { | |
11731 | u32 offset, major, minor, build; | |
11732 | ||
11733 | tp->fw_ver[0] = 's'; | |
11734 | tp->fw_ver[1] = 'b'; | |
11735 | tp->fw_ver[2] = '\0'; | |
11736 | ||
11737 | if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1) | |
11738 | return; | |
11739 | ||
11740 | switch (val & TG3_EEPROM_SB_REVISION_MASK) { | |
11741 | case TG3_EEPROM_SB_REVISION_0: | |
11742 | offset = TG3_EEPROM_SB_F1R0_EDH_OFF; | |
11743 | break; | |
11744 | case TG3_EEPROM_SB_REVISION_2: | |
11745 | offset = TG3_EEPROM_SB_F1R2_EDH_OFF; | |
11746 | break; | |
11747 | case TG3_EEPROM_SB_REVISION_3: | |
11748 | offset = TG3_EEPROM_SB_F1R3_EDH_OFF; | |
11749 | break; | |
11750 | default: | |
11751 | return; | |
11752 | } | |
11753 | ||
e4f34110 | 11754 | if (tg3_nvram_read(tp, offset, &val)) |
dfe00d7d MC |
11755 | return; |
11756 | ||
11757 | build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >> | |
11758 | TG3_EEPROM_SB_EDH_BLD_SHFT; | |
11759 | major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >> | |
11760 | TG3_EEPROM_SB_EDH_MAJ_SHFT; | |
11761 | minor = val & TG3_EEPROM_SB_EDH_MIN_MASK; | |
11762 | ||
11763 | if (minor > 99 || build > 26) | |
11764 | return; | |
11765 | ||
11766 | snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor); | |
11767 | ||
11768 | if (build > 0) { | |
11769 | tp->fw_ver[8] = 'a' + build - 1; | |
11770 | tp->fw_ver[9] = '\0'; | |
11771 | } | |
11772 | } | |
11773 | ||
acd9c119 | 11774 | static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp) |
c4e6575c MC |
11775 | { |
11776 | u32 val, offset, start; | |
acd9c119 | 11777 | int i, vlen; |
9c8a620e MC |
11778 | |
11779 | for (offset = TG3_NVM_DIR_START; | |
11780 | offset < TG3_NVM_DIR_END; | |
11781 | offset += TG3_NVM_DIRENT_SIZE) { | |
e4f34110 | 11782 | if (tg3_nvram_read(tp, offset, &val)) |
c4e6575c MC |
11783 | return; |
11784 | ||
9c8a620e MC |
11785 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) |
11786 | break; | |
11787 | } | |
11788 | ||
11789 | if (offset == TG3_NVM_DIR_END) | |
11790 | return; | |
11791 | ||
11792 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
11793 | start = 0x08000000; | |
e4f34110 | 11794 | else if (tg3_nvram_read(tp, offset - 4, &start)) |
9c8a620e MC |
11795 | return; |
11796 | ||
e4f34110 | 11797 | if (tg3_nvram_read(tp, offset + 4, &offset) || |
9c8a620e | 11798 | !tg3_fw_img_is_valid(tp, offset) || |
e4f34110 | 11799 | tg3_nvram_read(tp, offset + 8, &val)) |
9c8a620e MC |
11800 | return; |
11801 | ||
11802 | offset += val - start; | |
11803 | ||
acd9c119 | 11804 | vlen = strlen(tp->fw_ver); |
9c8a620e | 11805 | |
acd9c119 MC |
11806 | tp->fw_ver[vlen++] = ','; |
11807 | tp->fw_ver[vlen++] = ' '; | |
9c8a620e MC |
11808 | |
11809 | for (i = 0; i < 4; i++) { | |
a9dc529d MC |
11810 | __be32 v; |
11811 | if (tg3_nvram_read_be32(tp, offset, &v)) | |
c4e6575c MC |
11812 | return; |
11813 | ||
b9fc7dc5 | 11814 | offset += sizeof(v); |
c4e6575c | 11815 | |
acd9c119 MC |
11816 | if (vlen > TG3_VER_SIZE - sizeof(v)) { |
11817 | memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); | |
9c8a620e | 11818 | break; |
c4e6575c | 11819 | } |
9c8a620e | 11820 | |
acd9c119 MC |
11821 | memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); |
11822 | vlen += sizeof(v); | |
c4e6575c | 11823 | } |
acd9c119 MC |
11824 | } |
11825 | ||
7fd76445 MC |
11826 | static void __devinit tg3_read_dash_ver(struct tg3 *tp) |
11827 | { | |
11828 | int vlen; | |
11829 | u32 apedata; | |
11830 | ||
11831 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || | |
11832 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
11833 | return; | |
11834 | ||
11835 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
11836 | if (apedata != APE_SEG_SIG_MAGIC) | |
11837 | return; | |
11838 | ||
11839 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
11840 | if (!(apedata & APE_FW_STATUS_READY)) | |
11841 | return; | |
11842 | ||
11843 | apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); | |
11844 | ||
11845 | vlen = strlen(tp->fw_ver); | |
11846 | ||
11847 | snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d", | |
11848 | (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT, | |
11849 | (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT, | |
11850 | (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT, | |
11851 | (apedata & APE_FW_VERSION_BLDMSK)); | |
11852 | } | |
11853 | ||
acd9c119 MC |
11854 | static void __devinit tg3_read_fw_ver(struct tg3 *tp) |
11855 | { | |
11856 | u32 val; | |
11857 | ||
df259d8c MC |
11858 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) { |
11859 | tp->fw_ver[0] = 's'; | |
11860 | tp->fw_ver[1] = 'b'; | |
11861 | tp->fw_ver[2] = '\0'; | |
11862 | ||
11863 | return; | |
11864 | } | |
11865 | ||
acd9c119 MC |
11866 | if (tg3_nvram_read(tp, 0, &val)) |
11867 | return; | |
11868 | ||
11869 | if (val == TG3_EEPROM_MAGIC) | |
11870 | tg3_read_bc_ver(tp); | |
11871 | else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) | |
11872 | tg3_read_sb_ver(tp, val); | |
a6f6cb1c MC |
11873 | else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
11874 | tg3_read_hwsb_ver(tp); | |
acd9c119 MC |
11875 | else |
11876 | return; | |
11877 | ||
11878 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
11879 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
11880 | return; | |
11881 | ||
11882 | tg3_read_mgmtfw_ver(tp); | |
9c8a620e MC |
11883 | |
11884 | tp->fw_ver[TG3_VER_SIZE - 1] = 0; | |
c4e6575c MC |
11885 | } |
11886 | ||
7544b097 MC |
11887 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *); |
11888 | ||
1da177e4 LT |
11889 | static int __devinit tg3_get_invariants(struct tg3 *tp) |
11890 | { | |
11891 | static struct pci_device_id write_reorder_chipsets[] = { | |
1da177e4 LT |
11892 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, |
11893 | PCI_DEVICE_ID_AMD_FE_GATE_700C) }, | |
c165b004 JL |
11894 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, |
11895 | PCI_DEVICE_ID_AMD_8131_BRIDGE) }, | |
399de50b MC |
11896 | { PCI_DEVICE(PCI_VENDOR_ID_VIA, |
11897 | PCI_DEVICE_ID_VIA_8385_0) }, | |
1da177e4 LT |
11898 | { }, |
11899 | }; | |
11900 | u32 misc_ctrl_reg; | |
1da177e4 LT |
11901 | u32 pci_state_reg, grc_misc_cfg; |
11902 | u32 val; | |
11903 | u16 pci_cmd; | |
5e7dfd0f | 11904 | int err; |
1da177e4 | 11905 | |
1da177e4 LT |
11906 | /* Force memory write invalidate off. If we leave it on, |
11907 | * then on 5700_BX chips we have to enable a workaround. | |
11908 | * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary | |
11909 | * to match the cacheline size. The Broadcom driver have this | |
11910 | * workaround but turns MWI off all the times so never uses | |
11911 | * it. This seems to suggest that the workaround is insufficient. | |
11912 | */ | |
11913 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
11914 | pci_cmd &= ~PCI_COMMAND_INVALIDATE; | |
11915 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
11916 | ||
11917 | /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL | |
11918 | * has the register indirect write enable bit set before | |
11919 | * we try to access any of the MMIO registers. It is also | |
11920 | * critical that the PCI-X hw workaround situation is decided | |
11921 | * before that as well. | |
11922 | */ | |
11923 | pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
11924 | &misc_ctrl_reg); | |
11925 | ||
11926 | tp->pci_chip_rev_id = (misc_ctrl_reg >> | |
11927 | MISC_HOST_CTRL_CHIPREV_SHIFT); | |
795d01c5 MC |
11928 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) { |
11929 | u32 prod_id_asic_rev; | |
11930 | ||
11931 | pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV, | |
11932 | &prod_id_asic_rev); | |
321d32a0 | 11933 | tp->pci_chip_rev_id = prod_id_asic_rev; |
795d01c5 | 11934 | } |
1da177e4 | 11935 | |
ff645bec MC |
11936 | /* Wrong chip ID in 5752 A0. This code can be removed later |
11937 | * as A0 is not in production. | |
11938 | */ | |
11939 | if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) | |
11940 | tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; | |
11941 | ||
6892914f MC |
11942 | /* If we have 5702/03 A1 or A2 on certain ICH chipsets, |
11943 | * we need to disable memory and use config. cycles | |
11944 | * only to access all registers. The 5702/03 chips | |
11945 | * can mistakenly decode the special cycles from the | |
11946 | * ICH chipsets as memory write cycles, causing corruption | |
11947 | * of register and memory space. Only certain ICH bridges | |
11948 | * will drive special cycles with non-zero data during the | |
11949 | * address phase which can fall within the 5703's address | |
11950 | * range. This is not an ICH bug as the PCI spec allows | |
11951 | * non-zero address during special cycles. However, only | |
11952 | * these ICH bridges are known to drive non-zero addresses | |
11953 | * during special cycles. | |
11954 | * | |
11955 | * Since special cycles do not cross PCI bridges, we only | |
11956 | * enable this workaround if the 5703 is on the secondary | |
11957 | * bus of these ICH bridges. | |
11958 | */ | |
11959 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) || | |
11960 | (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) { | |
11961 | static struct tg3_dev_id { | |
11962 | u32 vendor; | |
11963 | u32 device; | |
11964 | u32 rev; | |
11965 | } ich_chipsets[] = { | |
11966 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8, | |
11967 | PCI_ANY_ID }, | |
11968 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8, | |
11969 | PCI_ANY_ID }, | |
11970 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11, | |
11971 | 0xa }, | |
11972 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6, | |
11973 | PCI_ANY_ID }, | |
11974 | { }, | |
11975 | }; | |
11976 | struct tg3_dev_id *pci_id = &ich_chipsets[0]; | |
11977 | struct pci_dev *bridge = NULL; | |
11978 | ||
11979 | while (pci_id->vendor != 0) { | |
11980 | bridge = pci_get_device(pci_id->vendor, pci_id->device, | |
11981 | bridge); | |
11982 | if (!bridge) { | |
11983 | pci_id++; | |
11984 | continue; | |
11985 | } | |
11986 | if (pci_id->rev != PCI_ANY_ID) { | |
44c10138 | 11987 | if (bridge->revision > pci_id->rev) |
6892914f MC |
11988 | continue; |
11989 | } | |
11990 | if (bridge->subordinate && | |
11991 | (bridge->subordinate->number == | |
11992 | tp->pdev->bus->number)) { | |
11993 | ||
11994 | tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND; | |
11995 | pci_dev_put(bridge); | |
11996 | break; | |
11997 | } | |
11998 | } | |
11999 | } | |
12000 | ||
41588ba1 MC |
12001 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { |
12002 | static struct tg3_dev_id { | |
12003 | u32 vendor; | |
12004 | u32 device; | |
12005 | } bridge_chipsets[] = { | |
12006 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 }, | |
12007 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 }, | |
12008 | { }, | |
12009 | }; | |
12010 | struct tg3_dev_id *pci_id = &bridge_chipsets[0]; | |
12011 | struct pci_dev *bridge = NULL; | |
12012 | ||
12013 | while (pci_id->vendor != 0) { | |
12014 | bridge = pci_get_device(pci_id->vendor, | |
12015 | pci_id->device, | |
12016 | bridge); | |
12017 | if (!bridge) { | |
12018 | pci_id++; | |
12019 | continue; | |
12020 | } | |
12021 | if (bridge->subordinate && | |
12022 | (bridge->subordinate->number <= | |
12023 | tp->pdev->bus->number) && | |
12024 | (bridge->subordinate->subordinate >= | |
12025 | tp->pdev->bus->number)) { | |
12026 | tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG; | |
12027 | pci_dev_put(bridge); | |
12028 | break; | |
12029 | } | |
12030 | } | |
12031 | } | |
12032 | ||
4a29cc2e MC |
12033 | /* The EPB bridge inside 5714, 5715, and 5780 cannot support |
12034 | * DMA addresses > 40-bit. This bridge may have other additional | |
12035 | * 57xx devices behind it in some 4-port NIC designs for example. | |
12036 | * Any tg3 device found behind the bridge will also need the 40-bit | |
12037 | * DMA workaround. | |
12038 | */ | |
a4e2b347 MC |
12039 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || |
12040 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
12041 | tp->tg3_flags2 |= TG3_FLG2_5780_CLASS; | |
4a29cc2e | 12042 | tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG; |
4cf78e4f | 12043 | tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI); |
a4e2b347 | 12044 | } |
4a29cc2e MC |
12045 | else { |
12046 | struct pci_dev *bridge = NULL; | |
12047 | ||
12048 | do { | |
12049 | bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, | |
12050 | PCI_DEVICE_ID_SERVERWORKS_EPB, | |
12051 | bridge); | |
12052 | if (bridge && bridge->subordinate && | |
12053 | (bridge->subordinate->number <= | |
12054 | tp->pdev->bus->number) && | |
12055 | (bridge->subordinate->subordinate >= | |
12056 | tp->pdev->bus->number)) { | |
12057 | tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG; | |
12058 | pci_dev_put(bridge); | |
12059 | break; | |
12060 | } | |
12061 | } while (bridge); | |
12062 | } | |
4cf78e4f | 12063 | |
1da177e4 LT |
12064 | /* Initialize misc host control in PCI block. */ |
12065 | tp->misc_host_ctrl |= (misc_ctrl_reg & | |
12066 | MISC_HOST_CTRL_CHIPREV); | |
12067 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
12068 | tp->misc_host_ctrl); | |
12069 | ||
7544b097 MC |
12070 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || |
12071 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) | |
12072 | tp->pdev_peer = tg3_find_peer(tp); | |
12073 | ||
321d32a0 MC |
12074 | /* Intentionally exclude ASIC_REV_5906 */ |
12075 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
d9ab5ad1 | 12076 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
d30cdd28 | 12077 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
9936bcf6 | 12078 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
57e6983c | 12079 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
321d32a0 MC |
12080 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
12081 | tp->tg3_flags3 |= TG3_FLG3_5755_PLUS; | |
12082 | ||
12083 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
12084 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
b5d3772c | 12085 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || |
321d32a0 | 12086 | (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || |
a4e2b347 | 12087 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) |
6708e5cc JL |
12088 | tp->tg3_flags2 |= TG3_FLG2_5750_PLUS; |
12089 | ||
1b440c56 JL |
12090 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) || |
12091 | (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) | |
12092 | tp->tg3_flags2 |= TG3_FLG2_5705_PLUS; | |
12093 | ||
027455ad MC |
12094 | /* 5700 B0 chips do not support checksumming correctly due |
12095 | * to hardware bugs. | |
12096 | */ | |
12097 | if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0) | |
12098 | tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS; | |
12099 | else { | |
12100 | tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS; | |
12101 | tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; | |
12102 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) | |
12103 | tp->dev->features |= NETIF_F_IPV6_CSUM; | |
12104 | } | |
12105 | ||
5a6f3074 | 12106 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { |
7544b097 MC |
12107 | tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI; |
12108 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX || | |
12109 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX || | |
12110 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 && | |
12111 | tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 && | |
12112 | tp->pdev_peer == tp->pdev)) | |
12113 | tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI; | |
12114 | ||
321d32a0 | 12115 | if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || |
b5d3772c | 12116 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
5a6f3074 | 12117 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2; |
fcfa0a32 | 12118 | tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI; |
52c0fd83 | 12119 | } else { |
7f62ad5d | 12120 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG; |
52c0fd83 MC |
12121 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
12122 | ASIC_REV_5750 && | |
12123 | tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2) | |
7f62ad5d | 12124 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG; |
52c0fd83 | 12125 | } |
5a6f3074 | 12126 | } |
1da177e4 | 12127 | |
f51f3562 MC |
12128 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || |
12129 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
8f666b07 | 12130 | tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE; |
0f893dc6 | 12131 | |
52f4490c MC |
12132 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, |
12133 | &pci_state_reg); | |
12134 | ||
5e7dfd0f MC |
12135 | tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP); |
12136 | if (tp->pcie_cap != 0) { | |
12137 | u16 lnkctl; | |
12138 | ||
1da177e4 | 12139 | tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; |
5f5c51e3 MC |
12140 | |
12141 | pcie_set_readrq(tp->pdev, 4096); | |
12142 | ||
5e7dfd0f MC |
12143 | pci_read_config_word(tp->pdev, |
12144 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
12145 | &lnkctl); | |
12146 | if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { | |
12147 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
c7835a77 | 12148 | tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2; |
5e7dfd0f | 12149 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 | 12150 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
9cf74ebb MC |
12151 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 || |
12152 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A1) | |
5e7dfd0f | 12153 | tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG; |
c7835a77 | 12154 | } |
52f4490c | 12155 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
fcb389df | 12156 | tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; |
52f4490c MC |
12157 | } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || |
12158 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { | |
12159 | tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); | |
12160 | if (!tp->pcix_cap) { | |
12161 | printk(KERN_ERR PFX "Cannot find PCI-X " | |
12162 | "capability, aborting.\n"); | |
12163 | return -EIO; | |
12164 | } | |
12165 | ||
12166 | if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE)) | |
12167 | tp->tg3_flags |= TG3_FLAG_PCIX_MODE; | |
12168 | } | |
1da177e4 | 12169 | |
399de50b MC |
12170 | /* If we have an AMD 762 or VIA K8T800 chipset, write |
12171 | * reordering to the mailbox registers done by the host | |
12172 | * controller can cause major troubles. We read back from | |
12173 | * every mailbox register write to force the writes to be | |
12174 | * posted to the chip in order. | |
12175 | */ | |
12176 | if (pci_dev_present(write_reorder_chipsets) && | |
12177 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
12178 | tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; | |
12179 | ||
69fc4053 MC |
12180 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, |
12181 | &tp->pci_cacheline_sz); | |
12182 | pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
12183 | &tp->pci_lat_timer); | |
1da177e4 LT |
12184 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && |
12185 | tp->pci_lat_timer < 64) { | |
12186 | tp->pci_lat_timer = 64; | |
69fc4053 MC |
12187 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, |
12188 | tp->pci_lat_timer); | |
1da177e4 LT |
12189 | } |
12190 | ||
52f4490c MC |
12191 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { |
12192 | /* 5700 BX chips need to have their TX producer index | |
12193 | * mailboxes written twice to workaround a bug. | |
12194 | */ | |
12195 | tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG; | |
1da177e4 | 12196 | |
52f4490c | 12197 | /* If we are in PCI-X mode, enable register write workaround. |
1da177e4 LT |
12198 | * |
12199 | * The workaround is to use indirect register accesses | |
12200 | * for all chip writes not to mailbox registers. | |
12201 | */ | |
52f4490c | 12202 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { |
1da177e4 | 12203 | u32 pm_reg; |
1da177e4 LT |
12204 | |
12205 | tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG; | |
12206 | ||
12207 | /* The chip can have it's power management PCI config | |
12208 | * space registers clobbered due to this bug. | |
12209 | * So explicitly force the chip into D0 here. | |
12210 | */ | |
9974a356 MC |
12211 | pci_read_config_dword(tp->pdev, |
12212 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
12213 | &pm_reg); |
12214 | pm_reg &= ~PCI_PM_CTRL_STATE_MASK; | |
12215 | pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */; | |
9974a356 MC |
12216 | pci_write_config_dword(tp->pdev, |
12217 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
12218 | pm_reg); |
12219 | ||
12220 | /* Also, force SERR#/PERR# in PCI command. */ | |
12221 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
12222 | pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; | |
12223 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
12224 | } | |
12225 | } | |
12226 | ||
1da177e4 LT |
12227 | if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) |
12228 | tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED; | |
12229 | if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) | |
12230 | tp->tg3_flags |= TG3_FLAG_PCI_32BIT; | |
12231 | ||
12232 | /* Chip-specific fixup from Broadcom driver */ | |
12233 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && | |
12234 | (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) { | |
12235 | pci_state_reg |= PCISTATE_RETRY_SAME_DMA; | |
12236 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); | |
12237 | } | |
12238 | ||
1ee582d8 | 12239 | /* Default fast path register access methods */ |
20094930 | 12240 | tp->read32 = tg3_read32; |
1ee582d8 | 12241 | tp->write32 = tg3_write32; |
09ee929c | 12242 | tp->read32_mbox = tg3_read32; |
20094930 | 12243 | tp->write32_mbox = tg3_write32; |
1ee582d8 MC |
12244 | tp->write32_tx_mbox = tg3_write32; |
12245 | tp->write32_rx_mbox = tg3_write32; | |
12246 | ||
12247 | /* Various workaround register access methods */ | |
12248 | if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) | |
12249 | tp->write32 = tg3_write_indirect_reg32; | |
98efd8a6 MC |
12250 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || |
12251 | ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && | |
12252 | tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) { | |
12253 | /* | |
12254 | * Back to back register writes can cause problems on these | |
12255 | * chips, the workaround is to read back all reg writes | |
12256 | * except those to mailbox regs. | |
12257 | * | |
12258 | * See tg3_write_indirect_reg32(). | |
12259 | */ | |
1ee582d8 | 12260 | tp->write32 = tg3_write_flush_reg32; |
98efd8a6 MC |
12261 | } |
12262 | ||
1ee582d8 MC |
12263 | |
12264 | if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) || | |
12265 | (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) { | |
12266 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | |
12267 | if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) | |
12268 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
12269 | } | |
20094930 | 12270 | |
6892914f MC |
12271 | if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) { |
12272 | tp->read32 = tg3_read_indirect_reg32; | |
12273 | tp->write32 = tg3_write_indirect_reg32; | |
12274 | tp->read32_mbox = tg3_read_indirect_mbox; | |
12275 | tp->write32_mbox = tg3_write_indirect_mbox; | |
12276 | tp->write32_tx_mbox = tg3_write_indirect_mbox; | |
12277 | tp->write32_rx_mbox = tg3_write_indirect_mbox; | |
12278 | ||
12279 | iounmap(tp->regs); | |
22abe310 | 12280 | tp->regs = NULL; |
6892914f MC |
12281 | |
12282 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
12283 | pci_cmd &= ~PCI_COMMAND_MEMORY; | |
12284 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
12285 | } | |
b5d3772c MC |
12286 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
12287 | tp->read32_mbox = tg3_read32_mbox_5906; | |
12288 | tp->write32_mbox = tg3_write32_mbox_5906; | |
12289 | tp->write32_tx_mbox = tg3_write32_mbox_5906; | |
12290 | tp->write32_rx_mbox = tg3_write32_mbox_5906; | |
12291 | } | |
6892914f | 12292 | |
bbadf503 MC |
12293 | if (tp->write32 == tg3_write_indirect_reg32 || |
12294 | ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) && | |
12295 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
f49639e6 | 12296 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) |
bbadf503 MC |
12297 | tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG; |
12298 | ||
7d0c41ef | 12299 | /* Get eeprom hw config before calling tg3_set_power_state(). |
9d26e213 | 12300 | * In particular, the TG3_FLG2_IS_NIC flag must be |
7d0c41ef MC |
12301 | * determined before calling tg3_set_power_state() so that |
12302 | * we know whether or not to switch out of Vaux power. | |
12303 | * When the flag is set, it means that GPIO1 is used for eeprom | |
12304 | * write protect and also implies that it is a LOM where GPIOs | |
12305 | * are not used to switch power. | |
6aa20a22 | 12306 | */ |
7d0c41ef MC |
12307 | tg3_get_eeprom_hw_cfg(tp); |
12308 | ||
0d3031d9 MC |
12309 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
12310 | /* Allow reads and writes to the | |
12311 | * APE register and memory space. | |
12312 | */ | |
12313 | pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
12314 | PCISTATE_ALLOW_APE_SHMEM_WR; | |
12315 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
12316 | pci_state_reg); | |
12317 | } | |
12318 | ||
9936bcf6 | 12319 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
57e6983c | 12320 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
321d32a0 MC |
12321 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
12322 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
d30cdd28 MC |
12323 | tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT; |
12324 | ||
314fba34 MC |
12325 | /* Set up tp->grc_local_ctrl before calling tg3_set_power_state(). |
12326 | * GPIO1 driven high will bring 5700's external PHY out of reset. | |
12327 | * It is also used as eeprom write protect on LOMs. | |
12328 | */ | |
12329 | tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; | |
12330 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || | |
12331 | (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) | |
12332 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | | |
12333 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
3e7d83bc MC |
12334 | /* Unused GPIO3 must be driven as output on 5752 because there |
12335 | * are no pull-up resistors on unused GPIO pins. | |
12336 | */ | |
12337 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
12338 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
314fba34 | 12339 | |
321d32a0 MC |
12340 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
12341 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
af36e6b6 MC |
12342 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; |
12343 | ||
8d519ab2 MC |
12344 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
12345 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
5f0c4a3c MC |
12346 | /* Turn off the debug UART. */ |
12347 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; | |
12348 | if (tp->tg3_flags2 & TG3_FLG2_IS_NIC) | |
12349 | /* Keep VMain power. */ | |
12350 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
12351 | GRC_LCLCTRL_GPIO_OUTPUT0; | |
12352 | } | |
12353 | ||
1da177e4 | 12354 | /* Force the chip into D0. */ |
bc1c7567 | 12355 | err = tg3_set_power_state(tp, PCI_D0); |
1da177e4 LT |
12356 | if (err) { |
12357 | printk(KERN_ERR PFX "(%s) transition to D0 failed\n", | |
12358 | pci_name(tp->pdev)); | |
12359 | return err; | |
12360 | } | |
12361 | ||
1da177e4 LT |
12362 | /* Derive initial jumbo mode from MTU assigned in |
12363 | * ether_setup() via the alloc_etherdev() call | |
12364 | */ | |
0f893dc6 | 12365 | if (tp->dev->mtu > ETH_DATA_LEN && |
a4e2b347 | 12366 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) |
0f893dc6 | 12367 | tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE; |
1da177e4 LT |
12368 | |
12369 | /* Determine WakeOnLan speed to use. */ | |
12370 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
12371 | tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
12372 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 || | |
12373 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) { | |
12374 | tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB); | |
12375 | } else { | |
12376 | tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB; | |
12377 | } | |
12378 | ||
7f97a4bd MC |
12379 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
12380 | tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET; | |
12381 | ||
1da177e4 LT |
12382 | /* A few boards don't want Ethernet@WireSpeed phy feature */ |
12383 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || | |
12384 | ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
12385 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && | |
747e8f8b | 12386 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) || |
7f97a4bd | 12387 | (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) || |
747e8f8b | 12388 | (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) |
1da177e4 LT |
12389 | tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED; |
12390 | ||
12391 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX || | |
12392 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX) | |
12393 | tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG; | |
12394 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) | |
12395 | tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG; | |
12396 | ||
321d32a0 | 12397 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && |
7f97a4bd | 12398 | !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) && |
321d32a0 MC |
12399 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
12400 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) { | |
c424cb24 | 12401 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
d30cdd28 | 12402 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
9936bcf6 MC |
12403 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
12404 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { | |
d4011ada MC |
12405 | if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && |
12406 | tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) | |
12407 | tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG; | |
c1d2a196 MC |
12408 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) |
12409 | tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM; | |
321d32a0 | 12410 | } else |
c424cb24 MC |
12411 | tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG; |
12412 | } | |
1da177e4 | 12413 | |
b2a5c19c MC |
12414 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
12415 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
12416 | tp->phy_otp = tg3_read_otp_phycfg(tp); | |
12417 | if (tp->phy_otp == 0) | |
12418 | tp->phy_otp = TG3_OTP_DEFAULT; | |
12419 | } | |
12420 | ||
f51f3562 | 12421 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) |
8ef21428 MC |
12422 | tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; |
12423 | else | |
12424 | tp->mi_mode = MAC_MI_MODE_BASE; | |
12425 | ||
1da177e4 | 12426 | tp->coalesce_mode = 0; |
1da177e4 LT |
12427 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && |
12428 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) | |
12429 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; | |
12430 | ||
321d32a0 MC |
12431 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
12432 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
57e6983c MC |
12433 | tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB; |
12434 | ||
255ca311 MC |
12435 | if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 && |
12436 | tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) || | |
12437 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A0) | |
12438 | tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD; | |
12439 | ||
158d7abd MC |
12440 | err = tg3_mdio_init(tp); |
12441 | if (err) | |
12442 | return err; | |
1da177e4 LT |
12443 | |
12444 | /* Initialize data/descriptor byte/word swapping. */ | |
12445 | val = tr32(GRC_MODE); | |
12446 | val &= GRC_MODE_HOST_STACKUP; | |
12447 | tw32(GRC_MODE, val | tp->grc_mode); | |
12448 | ||
12449 | tg3_switch_clocks(tp); | |
12450 | ||
12451 | /* Clear this out for sanity. */ | |
12452 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
12453 | ||
12454 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
12455 | &pci_state_reg); | |
12456 | if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && | |
12457 | (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) { | |
12458 | u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl); | |
12459 | ||
12460 | if (chiprevid == CHIPREV_ID_5701_A0 || | |
12461 | chiprevid == CHIPREV_ID_5701_B0 || | |
12462 | chiprevid == CHIPREV_ID_5701_B2 || | |
12463 | chiprevid == CHIPREV_ID_5701_B5) { | |
12464 | void __iomem *sram_base; | |
12465 | ||
12466 | /* Write some dummy words into the SRAM status block | |
12467 | * area, see if it reads back correctly. If the return | |
12468 | * value is bad, force enable the PCIX workaround. | |
12469 | */ | |
12470 | sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; | |
12471 | ||
12472 | writel(0x00000000, sram_base); | |
12473 | writel(0x00000000, sram_base + 4); | |
12474 | writel(0xffffffff, sram_base + 4); | |
12475 | if (readl(sram_base) != 0x00000000) | |
12476 | tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG; | |
12477 | } | |
12478 | } | |
12479 | ||
12480 | udelay(50); | |
12481 | tg3_nvram_init(tp); | |
12482 | ||
12483 | grc_misc_cfg = tr32(GRC_MISC_CFG); | |
12484 | grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; | |
12485 | ||
1da177e4 LT |
12486 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
12487 | (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 || | |
12488 | grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) | |
12489 | tp->tg3_flags2 |= TG3_FLG2_IS_5788; | |
12490 | ||
fac9b83e DM |
12491 | if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) && |
12492 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)) | |
12493 | tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS; | |
12494 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) { | |
12495 | tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | | |
12496 | HOSTCC_MODE_CLRTICK_TXBD); | |
12497 | ||
12498 | tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; | |
12499 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
12500 | tp->misc_host_ctrl); | |
12501 | } | |
12502 | ||
3bda1258 MC |
12503 | /* Preserve the APE MAC_MODE bits */ |
12504 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
12505 | tp->mac_mode = tr32(MAC_MODE) | | |
12506 | MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | |
12507 | else | |
12508 | tp->mac_mode = TG3_DEF_MAC_MODE; | |
12509 | ||
1da177e4 LT |
12510 | /* these are limited to 10/100 only */ |
12511 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | |
12512 | (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || | |
12513 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
12514 | tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
12515 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 || | |
12516 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 || | |
12517 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) || | |
12518 | (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
12519 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F || | |
676917d4 MC |
12520 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F || |
12521 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) || | |
321d32a0 | 12522 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 || |
7f97a4bd | 12523 | (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) |
1da177e4 LT |
12524 | tp->tg3_flags |= TG3_FLAG_10_100_ONLY; |
12525 | ||
12526 | err = tg3_phy_probe(tp); | |
12527 | if (err) { | |
12528 | printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n", | |
12529 | pci_name(tp->pdev), err); | |
12530 | /* ... but do not return immediately ... */ | |
b02fd9e3 | 12531 | tg3_mdio_fini(tp); |
1da177e4 LT |
12532 | } |
12533 | ||
12534 | tg3_read_partno(tp); | |
c4e6575c | 12535 | tg3_read_fw_ver(tp); |
1da177e4 LT |
12536 | |
12537 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { | |
12538 | tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT; | |
12539 | } else { | |
12540 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
12541 | tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT; | |
12542 | else | |
12543 | tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT; | |
12544 | } | |
12545 | ||
12546 | /* 5700 {AX,BX} chips have a broken status block link | |
12547 | * change bit implementation, so we must use the | |
12548 | * status register in those cases. | |
12549 | */ | |
12550 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
12551 | tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG; | |
12552 | else | |
12553 | tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG; | |
12554 | ||
12555 | /* The led_ctrl is set during tg3_phy_probe, here we might | |
12556 | * have to force the link status polling mechanism based | |
12557 | * upon subsystem IDs. | |
12558 | */ | |
12559 | if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && | |
007a880d | 12560 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
1da177e4 LT |
12561 | !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { |
12562 | tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT | | |
12563 | TG3_FLAG_USE_LINKCHG_REG); | |
12564 | } | |
12565 | ||
12566 | /* For all SERDES we poll the MAC status register. */ | |
12567 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) | |
12568 | tp->tg3_flags |= TG3_FLAG_POLL_SERDES; | |
12569 | else | |
12570 | tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES; | |
12571 | ||
ad829268 | 12572 | tp->rx_offset = NET_IP_ALIGN; |
1da177e4 LT |
12573 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
12574 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) | |
12575 | tp->rx_offset = 0; | |
12576 | ||
f92905de MC |
12577 | tp->rx_std_max_post = TG3_RX_RING_SIZE; |
12578 | ||
12579 | /* Increment the rx prod index on the rx std ring by at most | |
12580 | * 8 for these chips to workaround hw errata. | |
12581 | */ | |
12582 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
12583 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
12584 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
12585 | tp->rx_std_max_post = 8; | |
12586 | ||
8ed5d97e MC |
12587 | if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) |
12588 | tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & | |
12589 | PCIE_PWR_MGMT_L1_THRESH_MSK; | |
12590 | ||
1da177e4 LT |
12591 | return err; |
12592 | } | |
12593 | ||
49b6e95f | 12594 | #ifdef CONFIG_SPARC |
1da177e4 LT |
12595 | static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp) |
12596 | { | |
12597 | struct net_device *dev = tp->dev; | |
12598 | struct pci_dev *pdev = tp->pdev; | |
49b6e95f | 12599 | struct device_node *dp = pci_device_to_OF_node(pdev); |
374d4cac | 12600 | const unsigned char *addr; |
49b6e95f DM |
12601 | int len; |
12602 | ||
12603 | addr = of_get_property(dp, "local-mac-address", &len); | |
12604 | if (addr && len == 6) { | |
12605 | memcpy(dev->dev_addr, addr, 6); | |
12606 | memcpy(dev->perm_addr, dev->dev_addr, 6); | |
12607 | return 0; | |
1da177e4 LT |
12608 | } |
12609 | return -ENODEV; | |
12610 | } | |
12611 | ||
12612 | static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp) | |
12613 | { | |
12614 | struct net_device *dev = tp->dev; | |
12615 | ||
12616 | memcpy(dev->dev_addr, idprom->id_ethaddr, 6); | |
2ff43697 | 12617 | memcpy(dev->perm_addr, idprom->id_ethaddr, 6); |
1da177e4 LT |
12618 | return 0; |
12619 | } | |
12620 | #endif | |
12621 | ||
12622 | static int __devinit tg3_get_device_address(struct tg3 *tp) | |
12623 | { | |
12624 | struct net_device *dev = tp->dev; | |
12625 | u32 hi, lo, mac_offset; | |
008652b3 | 12626 | int addr_ok = 0; |
1da177e4 | 12627 | |
49b6e95f | 12628 | #ifdef CONFIG_SPARC |
1da177e4 LT |
12629 | if (!tg3_get_macaddr_sparc(tp)) |
12630 | return 0; | |
12631 | #endif | |
12632 | ||
12633 | mac_offset = 0x7c; | |
f49639e6 | 12634 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || |
a4e2b347 | 12635 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
1da177e4 LT |
12636 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) |
12637 | mac_offset = 0xcc; | |
12638 | if (tg3_nvram_lock(tp)) | |
12639 | tw32_f(NVRAM_CMD, NVRAM_CMD_RESET); | |
12640 | else | |
12641 | tg3_nvram_unlock(tp); | |
12642 | } | |
b5d3772c MC |
12643 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
12644 | mac_offset = 0x10; | |
1da177e4 LT |
12645 | |
12646 | /* First try to get it from MAC address mailbox. */ | |
12647 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); | |
12648 | if ((hi >> 16) == 0x484b) { | |
12649 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
12650 | dev->dev_addr[1] = (hi >> 0) & 0xff; | |
12651 | ||
12652 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); | |
12653 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
12654 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
12655 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
12656 | dev->dev_addr[5] = (lo >> 0) & 0xff; | |
1da177e4 | 12657 | |
008652b3 MC |
12658 | /* Some old bootcode may report a 0 MAC address in SRAM */ |
12659 | addr_ok = is_valid_ether_addr(&dev->dev_addr[0]); | |
12660 | } | |
12661 | if (!addr_ok) { | |
12662 | /* Next, try NVRAM. */ | |
df259d8c MC |
12663 | if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) && |
12664 | !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && | |
6d348f2c | 12665 | !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { |
62cedd11 MC |
12666 | memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2); |
12667 | memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo)); | |
008652b3 MC |
12668 | } |
12669 | /* Finally just fetch it out of the MAC control regs. */ | |
12670 | else { | |
12671 | hi = tr32(MAC_ADDR_0_HIGH); | |
12672 | lo = tr32(MAC_ADDR_0_LOW); | |
12673 | ||
12674 | dev->dev_addr[5] = lo & 0xff; | |
12675 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
12676 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
12677 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
12678 | dev->dev_addr[1] = hi & 0xff; | |
12679 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
12680 | } | |
1da177e4 LT |
12681 | } |
12682 | ||
12683 | if (!is_valid_ether_addr(&dev->dev_addr[0])) { | |
7582a335 | 12684 | #ifdef CONFIG_SPARC |
1da177e4 LT |
12685 | if (!tg3_get_default_macaddr_sparc(tp)) |
12686 | return 0; | |
12687 | #endif | |
12688 | return -EINVAL; | |
12689 | } | |
2ff43697 | 12690 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 LT |
12691 | return 0; |
12692 | } | |
12693 | ||
59e6b434 DM |
12694 | #define BOUNDARY_SINGLE_CACHELINE 1 |
12695 | #define BOUNDARY_MULTI_CACHELINE 2 | |
12696 | ||
12697 | static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |
12698 | { | |
12699 | int cacheline_size; | |
12700 | u8 byte; | |
12701 | int goal; | |
12702 | ||
12703 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); | |
12704 | if (byte == 0) | |
12705 | cacheline_size = 1024; | |
12706 | else | |
12707 | cacheline_size = (int) byte * 4; | |
12708 | ||
12709 | /* On 5703 and later chips, the boundary bits have no | |
12710 | * effect. | |
12711 | */ | |
12712 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
12713 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
12714 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
12715 | goto out; | |
12716 | ||
12717 | #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC) | |
12718 | goal = BOUNDARY_MULTI_CACHELINE; | |
12719 | #else | |
12720 | #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA) | |
12721 | goal = BOUNDARY_SINGLE_CACHELINE; | |
12722 | #else | |
12723 | goal = 0; | |
12724 | #endif | |
12725 | #endif | |
12726 | ||
12727 | if (!goal) | |
12728 | goto out; | |
12729 | ||
12730 | /* PCI controllers on most RISC systems tend to disconnect | |
12731 | * when a device tries to burst across a cache-line boundary. | |
12732 | * Therefore, letting tg3 do so just wastes PCI bandwidth. | |
12733 | * | |
12734 | * Unfortunately, for PCI-E there are only limited | |
12735 | * write-side controls for this, and thus for reads | |
12736 | * we will still get the disconnects. We'll also waste | |
12737 | * these PCI cycles for both read and write for chips | |
12738 | * other than 5700 and 5701 which do not implement the | |
12739 | * boundary bits. | |
12740 | */ | |
12741 | if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) && | |
12742 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) { | |
12743 | switch (cacheline_size) { | |
12744 | case 16: | |
12745 | case 32: | |
12746 | case 64: | |
12747 | case 128: | |
12748 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
12749 | val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX | | |
12750 | DMA_RWCTRL_WRITE_BNDRY_128_PCIX); | |
12751 | } else { | |
12752 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
12753 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
12754 | } | |
12755 | break; | |
12756 | ||
12757 | case 256: | |
12758 | val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX | | |
12759 | DMA_RWCTRL_WRITE_BNDRY_256_PCIX); | |
12760 | break; | |
12761 | ||
12762 | default: | |
12763 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
12764 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
12765 | break; | |
855e1111 | 12766 | } |
59e6b434 DM |
12767 | } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { |
12768 | switch (cacheline_size) { | |
12769 | case 16: | |
12770 | case 32: | |
12771 | case 64: | |
12772 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
12773 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
12774 | val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE; | |
12775 | break; | |
12776 | } | |
12777 | /* fallthrough */ | |
12778 | case 128: | |
12779 | default: | |
12780 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
12781 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; | |
12782 | break; | |
855e1111 | 12783 | } |
59e6b434 DM |
12784 | } else { |
12785 | switch (cacheline_size) { | |
12786 | case 16: | |
12787 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
12788 | val |= (DMA_RWCTRL_READ_BNDRY_16 | | |
12789 | DMA_RWCTRL_WRITE_BNDRY_16); | |
12790 | break; | |
12791 | } | |
12792 | /* fallthrough */ | |
12793 | case 32: | |
12794 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
12795 | val |= (DMA_RWCTRL_READ_BNDRY_32 | | |
12796 | DMA_RWCTRL_WRITE_BNDRY_32); | |
12797 | break; | |
12798 | } | |
12799 | /* fallthrough */ | |
12800 | case 64: | |
12801 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
12802 | val |= (DMA_RWCTRL_READ_BNDRY_64 | | |
12803 | DMA_RWCTRL_WRITE_BNDRY_64); | |
12804 | break; | |
12805 | } | |
12806 | /* fallthrough */ | |
12807 | case 128: | |
12808 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
12809 | val |= (DMA_RWCTRL_READ_BNDRY_128 | | |
12810 | DMA_RWCTRL_WRITE_BNDRY_128); | |
12811 | break; | |
12812 | } | |
12813 | /* fallthrough */ | |
12814 | case 256: | |
12815 | val |= (DMA_RWCTRL_READ_BNDRY_256 | | |
12816 | DMA_RWCTRL_WRITE_BNDRY_256); | |
12817 | break; | |
12818 | case 512: | |
12819 | val |= (DMA_RWCTRL_READ_BNDRY_512 | | |
12820 | DMA_RWCTRL_WRITE_BNDRY_512); | |
12821 | break; | |
12822 | case 1024: | |
12823 | default: | |
12824 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | | |
12825 | DMA_RWCTRL_WRITE_BNDRY_1024); | |
12826 | break; | |
855e1111 | 12827 | } |
59e6b434 DM |
12828 | } |
12829 | ||
12830 | out: | |
12831 | return val; | |
12832 | } | |
12833 | ||
1da177e4 LT |
12834 | static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device) |
12835 | { | |
12836 | struct tg3_internal_buffer_desc test_desc; | |
12837 | u32 sram_dma_descs; | |
12838 | int i, ret; | |
12839 | ||
12840 | sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE; | |
12841 | ||
12842 | tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0); | |
12843 | tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0); | |
12844 | tw32(RDMAC_STATUS, 0); | |
12845 | tw32(WDMAC_STATUS, 0); | |
12846 | ||
12847 | tw32(BUFMGR_MODE, 0); | |
12848 | tw32(FTQ_RESET, 0); | |
12849 | ||
12850 | test_desc.addr_hi = ((u64) buf_dma) >> 32; | |
12851 | test_desc.addr_lo = buf_dma & 0xffffffff; | |
12852 | test_desc.nic_mbuf = 0x00002100; | |
12853 | test_desc.len = size; | |
12854 | ||
12855 | /* | |
12856 | * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz | |
12857 | * the *second* time the tg3 driver was getting loaded after an | |
12858 | * initial scan. | |
12859 | * | |
12860 | * Broadcom tells me: | |
12861 | * ...the DMA engine is connected to the GRC block and a DMA | |
12862 | * reset may affect the GRC block in some unpredictable way... | |
12863 | * The behavior of resets to individual blocks has not been tested. | |
12864 | * | |
12865 | * Broadcom noted the GRC reset will also reset all sub-components. | |
12866 | */ | |
12867 | if (to_device) { | |
12868 | test_desc.cqid_sqid = (13 << 8) | 2; | |
12869 | ||
12870 | tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE); | |
12871 | udelay(40); | |
12872 | } else { | |
12873 | test_desc.cqid_sqid = (16 << 8) | 7; | |
12874 | ||
12875 | tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE); | |
12876 | udelay(40); | |
12877 | } | |
12878 | test_desc.flags = 0x00000005; | |
12879 | ||
12880 | for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) { | |
12881 | u32 val; | |
12882 | ||
12883 | val = *(((u32 *)&test_desc) + i); | |
12884 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, | |
12885 | sram_dma_descs + (i * sizeof(u32))); | |
12886 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
12887 | } | |
12888 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
12889 | ||
12890 | if (to_device) { | |
12891 | tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs); | |
12892 | } else { | |
12893 | tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs); | |
12894 | } | |
12895 | ||
12896 | ret = -ENODEV; | |
12897 | for (i = 0; i < 40; i++) { | |
12898 | u32 val; | |
12899 | ||
12900 | if (to_device) | |
12901 | val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); | |
12902 | else | |
12903 | val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); | |
12904 | if ((val & 0xffff) == sram_dma_descs) { | |
12905 | ret = 0; | |
12906 | break; | |
12907 | } | |
12908 | ||
12909 | udelay(100); | |
12910 | } | |
12911 | ||
12912 | return ret; | |
12913 | } | |
12914 | ||
ded7340d | 12915 | #define TEST_BUFFER_SIZE 0x2000 |
1da177e4 LT |
12916 | |
12917 | static int __devinit tg3_test_dma(struct tg3 *tp) | |
12918 | { | |
12919 | dma_addr_t buf_dma; | |
59e6b434 | 12920 | u32 *buf, saved_dma_rwctrl; |
1da177e4 LT |
12921 | int ret; |
12922 | ||
12923 | buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma); | |
12924 | if (!buf) { | |
12925 | ret = -ENOMEM; | |
12926 | goto out_nofree; | |
12927 | } | |
12928 | ||
12929 | tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | | |
12930 | (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT)); | |
12931 | ||
59e6b434 | 12932 | tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); |
1da177e4 LT |
12933 | |
12934 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
12935 | /* DMA read watermark not used on PCIE */ | |
12936 | tp->dma_rwctrl |= 0x00180000; | |
12937 | } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { | |
85e94ced MC |
12938 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || |
12939 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) | |
1da177e4 LT |
12940 | tp->dma_rwctrl |= 0x003f0000; |
12941 | else | |
12942 | tp->dma_rwctrl |= 0x003f000f; | |
12943 | } else { | |
12944 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
12945 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
12946 | u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); | |
49afdeb6 | 12947 | u32 read_water = 0x7; |
1da177e4 | 12948 | |
4a29cc2e MC |
12949 | /* If the 5704 is behind the EPB bridge, we can |
12950 | * do the less restrictive ONE_DMA workaround for | |
12951 | * better performance. | |
12952 | */ | |
12953 | if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) && | |
12954 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
12955 | tp->dma_rwctrl |= 0x8000; | |
12956 | else if (ccval == 0x6 || ccval == 0x7) | |
1da177e4 LT |
12957 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; |
12958 | ||
49afdeb6 MC |
12959 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) |
12960 | read_water = 4; | |
59e6b434 | 12961 | /* Set bit 23 to enable PCIX hw bug fix */ |
49afdeb6 MC |
12962 | tp->dma_rwctrl |= |
12963 | (read_water << DMA_RWCTRL_READ_WATER_SHIFT) | | |
12964 | (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | | |
12965 | (1 << 23); | |
4cf78e4f MC |
12966 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) { |
12967 | /* 5780 always in PCIX mode */ | |
12968 | tp->dma_rwctrl |= 0x00144000; | |
a4e2b347 MC |
12969 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
12970 | /* 5714 always in PCIX mode */ | |
12971 | tp->dma_rwctrl |= 0x00148000; | |
1da177e4 LT |
12972 | } else { |
12973 | tp->dma_rwctrl |= 0x001b000f; | |
12974 | } | |
12975 | } | |
12976 | ||
12977 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
12978 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
12979 | tp->dma_rwctrl &= 0xfffffff0; | |
12980 | ||
12981 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
12982 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
12983 | /* Remove this if it causes problems for some boards. */ | |
12984 | tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; | |
12985 | ||
12986 | /* On 5700/5701 chips, we need to set this bit. | |
12987 | * Otherwise the chip will issue cacheline transactions | |
12988 | * to streamable DMA memory with not all the byte | |
12989 | * enables turned on. This is an error on several | |
12990 | * RISC PCI controllers, in particular sparc64. | |
12991 | * | |
12992 | * On 5703/5704 chips, this bit has been reassigned | |
12993 | * a different meaning. In particular, it is used | |
12994 | * on those chips to enable a PCI-X workaround. | |
12995 | */ | |
12996 | tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; | |
12997 | } | |
12998 | ||
12999 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
13000 | ||
13001 | #if 0 | |
13002 | /* Unneeded, already done by tg3_get_invariants. */ | |
13003 | tg3_switch_clocks(tp); | |
13004 | #endif | |
13005 | ||
13006 | ret = 0; | |
13007 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
13008 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | |
13009 | goto out; | |
13010 | ||
59e6b434 DM |
13011 | /* It is best to perform DMA test with maximum write burst size |
13012 | * to expose the 5700/5701 write DMA bug. | |
13013 | */ | |
13014 | saved_dma_rwctrl = tp->dma_rwctrl; | |
13015 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
13016 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
13017 | ||
1da177e4 LT |
13018 | while (1) { |
13019 | u32 *p = buf, i; | |
13020 | ||
13021 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) | |
13022 | p[i] = i; | |
13023 | ||
13024 | /* Send the buffer to the chip. */ | |
13025 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1); | |
13026 | if (ret) { | |
13027 | printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret); | |
13028 | break; | |
13029 | } | |
13030 | ||
13031 | #if 0 | |
13032 | /* validate data reached card RAM correctly. */ | |
13033 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
13034 | u32 val; | |
13035 | tg3_read_mem(tp, 0x2100 + (i*4), &val); | |
13036 | if (le32_to_cpu(val) != p[i]) { | |
13037 | printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i); | |
13038 | /* ret = -ENODEV here? */ | |
13039 | } | |
13040 | p[i] = 0; | |
13041 | } | |
13042 | #endif | |
13043 | /* Now read it back. */ | |
13044 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0); | |
13045 | if (ret) { | |
13046 | printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret); | |
13047 | ||
13048 | break; | |
13049 | } | |
13050 | ||
13051 | /* Verify it. */ | |
13052 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
13053 | if (p[i] == i) | |
13054 | continue; | |
13055 | ||
59e6b434 DM |
13056 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
13057 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
13058 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
1da177e4 LT |
13059 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; |
13060 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
13061 | break; | |
13062 | } else { | |
13063 | printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i); | |
13064 | ret = -ENODEV; | |
13065 | goto out; | |
13066 | } | |
13067 | } | |
13068 | ||
13069 | if (i == (TEST_BUFFER_SIZE / sizeof(u32))) { | |
13070 | /* Success. */ | |
13071 | ret = 0; | |
13072 | break; | |
13073 | } | |
13074 | } | |
59e6b434 DM |
13075 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
13076 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
6d1cfbab MC |
13077 | static struct pci_device_id dma_wait_state_chipsets[] = { |
13078 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, | |
13079 | PCI_DEVICE_ID_APPLE_UNI_N_PCI15) }, | |
13080 | { }, | |
13081 | }; | |
13082 | ||
59e6b434 | 13083 | /* DMA test passed without adjusting DMA boundary, |
6d1cfbab MC |
13084 | * now look for chipsets that are known to expose the |
13085 | * DMA bug without failing the test. | |
59e6b434 | 13086 | */ |
6d1cfbab MC |
13087 | if (pci_dev_present(dma_wait_state_chipsets)) { |
13088 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
13089 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; | |
13090 | } | |
13091 | else | |
13092 | /* Safe to use the calculated DMA boundary. */ | |
13093 | tp->dma_rwctrl = saved_dma_rwctrl; | |
13094 | ||
59e6b434 DM |
13095 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); |
13096 | } | |
1da177e4 LT |
13097 | |
13098 | out: | |
13099 | pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma); | |
13100 | out_nofree: | |
13101 | return ret; | |
13102 | } | |
13103 | ||
13104 | static void __devinit tg3_init_link_config(struct tg3 *tp) | |
13105 | { | |
13106 | tp->link_config.advertising = | |
13107 | (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
13108 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
13109 | ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full | | |
13110 | ADVERTISED_Autoneg | ADVERTISED_MII); | |
13111 | tp->link_config.speed = SPEED_INVALID; | |
13112 | tp->link_config.duplex = DUPLEX_INVALID; | |
13113 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
1da177e4 LT |
13114 | tp->link_config.active_speed = SPEED_INVALID; |
13115 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
13116 | tp->link_config.phy_is_low_power = 0; | |
13117 | tp->link_config.orig_speed = SPEED_INVALID; | |
13118 | tp->link_config.orig_duplex = DUPLEX_INVALID; | |
13119 | tp->link_config.orig_autoneg = AUTONEG_INVALID; | |
13120 | } | |
13121 | ||
13122 | static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) | |
13123 | { | |
fdfec172 MC |
13124 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { |
13125 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
13126 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
13127 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
13128 | DEFAULT_MB_MACRX_LOW_WATER_5705; | |
13129 | tp->bufmgr_config.mbuf_high_water = | |
13130 | DEFAULT_MB_HIGH_WATER_5705; | |
b5d3772c MC |
13131 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
13132 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
13133 | DEFAULT_MB_MACRX_LOW_WATER_5906; | |
13134 | tp->bufmgr_config.mbuf_high_water = | |
13135 | DEFAULT_MB_HIGH_WATER_5906; | |
13136 | } | |
fdfec172 MC |
13137 | |
13138 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
13139 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780; | |
13140 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
13141 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780; | |
13142 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
13143 | DEFAULT_MB_HIGH_WATER_JUMBO_5780; | |
13144 | } else { | |
13145 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
13146 | DEFAULT_MB_RDMA_LOW_WATER; | |
13147 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
13148 | DEFAULT_MB_MACRX_LOW_WATER; | |
13149 | tp->bufmgr_config.mbuf_high_water = | |
13150 | DEFAULT_MB_HIGH_WATER; | |
13151 | ||
13152 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
13153 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO; | |
13154 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
13155 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO; | |
13156 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
13157 | DEFAULT_MB_HIGH_WATER_JUMBO; | |
13158 | } | |
1da177e4 LT |
13159 | |
13160 | tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; | |
13161 | tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; | |
13162 | } | |
13163 | ||
13164 | static char * __devinit tg3_phy_string(struct tg3 *tp) | |
13165 | { | |
13166 | switch (tp->phy_id & PHY_ID_MASK) { | |
13167 | case PHY_ID_BCM5400: return "5400"; | |
13168 | case PHY_ID_BCM5401: return "5401"; | |
13169 | case PHY_ID_BCM5411: return "5411"; | |
13170 | case PHY_ID_BCM5701: return "5701"; | |
13171 | case PHY_ID_BCM5703: return "5703"; | |
13172 | case PHY_ID_BCM5704: return "5704"; | |
13173 | case PHY_ID_BCM5705: return "5705"; | |
13174 | case PHY_ID_BCM5750: return "5750"; | |
85e94ced | 13175 | case PHY_ID_BCM5752: return "5752"; |
a4e2b347 | 13176 | case PHY_ID_BCM5714: return "5714"; |
4cf78e4f | 13177 | case PHY_ID_BCM5780: return "5780"; |
af36e6b6 | 13178 | case PHY_ID_BCM5755: return "5755"; |
d9ab5ad1 | 13179 | case PHY_ID_BCM5787: return "5787"; |
d30cdd28 | 13180 | case PHY_ID_BCM5784: return "5784"; |
126a3368 | 13181 | case PHY_ID_BCM5756: return "5722/5756"; |
b5d3772c | 13182 | case PHY_ID_BCM5906: return "5906"; |
9936bcf6 | 13183 | case PHY_ID_BCM5761: return "5761"; |
1da177e4 LT |
13184 | case PHY_ID_BCM8002: return "8002/serdes"; |
13185 | case 0: return "serdes"; | |
13186 | default: return "unknown"; | |
855e1111 | 13187 | } |
1da177e4 LT |
13188 | } |
13189 | ||
f9804ddb MC |
13190 | static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) |
13191 | { | |
13192 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
13193 | strcpy(str, "PCI Express"); | |
13194 | return str; | |
13195 | } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { | |
13196 | u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; | |
13197 | ||
13198 | strcpy(str, "PCIX:"); | |
13199 | ||
13200 | if ((clock_ctrl == 7) || | |
13201 | ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == | |
13202 | GRC_MISC_CFG_BOARD_ID_5704CIOBE)) | |
13203 | strcat(str, "133MHz"); | |
13204 | else if (clock_ctrl == 0) | |
13205 | strcat(str, "33MHz"); | |
13206 | else if (clock_ctrl == 2) | |
13207 | strcat(str, "50MHz"); | |
13208 | else if (clock_ctrl == 4) | |
13209 | strcat(str, "66MHz"); | |
13210 | else if (clock_ctrl == 6) | |
13211 | strcat(str, "100MHz"); | |
f9804ddb MC |
13212 | } else { |
13213 | strcpy(str, "PCI:"); | |
13214 | if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) | |
13215 | strcat(str, "66MHz"); | |
13216 | else | |
13217 | strcat(str, "33MHz"); | |
13218 | } | |
13219 | if (tp->tg3_flags & TG3_FLAG_PCI_32BIT) | |
13220 | strcat(str, ":32-bit"); | |
13221 | else | |
13222 | strcat(str, ":64-bit"); | |
13223 | return str; | |
13224 | } | |
13225 | ||
8c2dc7e1 | 13226 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp) |
1da177e4 LT |
13227 | { |
13228 | struct pci_dev *peer; | |
13229 | unsigned int func, devnr = tp->pdev->devfn & ~7; | |
13230 | ||
13231 | for (func = 0; func < 8; func++) { | |
13232 | peer = pci_get_slot(tp->pdev->bus, devnr | func); | |
13233 | if (peer && peer != tp->pdev) | |
13234 | break; | |
13235 | pci_dev_put(peer); | |
13236 | } | |
16fe9d74 MC |
13237 | /* 5704 can be configured in single-port mode, set peer to |
13238 | * tp->pdev in that case. | |
13239 | */ | |
13240 | if (!peer) { | |
13241 | peer = tp->pdev; | |
13242 | return peer; | |
13243 | } | |
1da177e4 LT |
13244 | |
13245 | /* | |
13246 | * We don't need to keep the refcount elevated; there's no way | |
13247 | * to remove one half of this device without removing the other | |
13248 | */ | |
13249 | pci_dev_put(peer); | |
13250 | ||
13251 | return peer; | |
13252 | } | |
13253 | ||
15f9850d DM |
13254 | static void __devinit tg3_init_coal(struct tg3 *tp) |
13255 | { | |
13256 | struct ethtool_coalesce *ec = &tp->coal; | |
13257 | ||
13258 | memset(ec, 0, sizeof(*ec)); | |
13259 | ec->cmd = ETHTOOL_GCOALESCE; | |
13260 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; | |
13261 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; | |
13262 | ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; | |
13263 | ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; | |
13264 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; | |
13265 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; | |
13266 | ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; | |
13267 | ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; | |
13268 | ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; | |
13269 | ||
13270 | if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | | |
13271 | HOSTCC_MODE_CLRTICK_TXBD)) { | |
13272 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; | |
13273 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; | |
13274 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; | |
13275 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; | |
13276 | } | |
d244c892 MC |
13277 | |
13278 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
13279 | ec->rx_coalesce_usecs_irq = 0; | |
13280 | ec->tx_coalesce_usecs_irq = 0; | |
13281 | ec->stats_block_coalesce_usecs = 0; | |
13282 | } | |
15f9850d DM |
13283 | } |
13284 | ||
7c7d64b8 SH |
13285 | static const struct net_device_ops tg3_netdev_ops = { |
13286 | .ndo_open = tg3_open, | |
13287 | .ndo_stop = tg3_close, | |
00829823 SH |
13288 | .ndo_start_xmit = tg3_start_xmit, |
13289 | .ndo_get_stats = tg3_get_stats, | |
13290 | .ndo_validate_addr = eth_validate_addr, | |
13291 | .ndo_set_multicast_list = tg3_set_rx_mode, | |
13292 | .ndo_set_mac_address = tg3_set_mac_addr, | |
13293 | .ndo_do_ioctl = tg3_ioctl, | |
13294 | .ndo_tx_timeout = tg3_tx_timeout, | |
13295 | .ndo_change_mtu = tg3_change_mtu, | |
13296 | #if TG3_VLAN_TAG_USED | |
13297 | .ndo_vlan_rx_register = tg3_vlan_rx_register, | |
13298 | #endif | |
13299 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
13300 | .ndo_poll_controller = tg3_poll_controller, | |
13301 | #endif | |
13302 | }; | |
13303 | ||
13304 | static const struct net_device_ops tg3_netdev_ops_dma_bug = { | |
13305 | .ndo_open = tg3_open, | |
13306 | .ndo_stop = tg3_close, | |
13307 | .ndo_start_xmit = tg3_start_xmit_dma_bug, | |
7c7d64b8 SH |
13308 | .ndo_get_stats = tg3_get_stats, |
13309 | .ndo_validate_addr = eth_validate_addr, | |
13310 | .ndo_set_multicast_list = tg3_set_rx_mode, | |
13311 | .ndo_set_mac_address = tg3_set_mac_addr, | |
13312 | .ndo_do_ioctl = tg3_ioctl, | |
13313 | .ndo_tx_timeout = tg3_tx_timeout, | |
13314 | .ndo_change_mtu = tg3_change_mtu, | |
13315 | #if TG3_VLAN_TAG_USED | |
13316 | .ndo_vlan_rx_register = tg3_vlan_rx_register, | |
13317 | #endif | |
13318 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
13319 | .ndo_poll_controller = tg3_poll_controller, | |
13320 | #endif | |
13321 | }; | |
13322 | ||
1da177e4 LT |
13323 | static int __devinit tg3_init_one(struct pci_dev *pdev, |
13324 | const struct pci_device_id *ent) | |
13325 | { | |
13326 | static int tg3_version_printed = 0; | |
1da177e4 LT |
13327 | struct net_device *dev; |
13328 | struct tg3 *tp; | |
d6645372 | 13329 | int err, pm_cap; |
f9804ddb | 13330 | char str[40]; |
72f2afb8 | 13331 | u64 dma_mask, persist_dma_mask; |
1da177e4 LT |
13332 | |
13333 | if (tg3_version_printed++ == 0) | |
13334 | printk(KERN_INFO "%s", version); | |
13335 | ||
13336 | err = pci_enable_device(pdev); | |
13337 | if (err) { | |
13338 | printk(KERN_ERR PFX "Cannot enable PCI device, " | |
13339 | "aborting.\n"); | |
13340 | return err; | |
13341 | } | |
13342 | ||
1da177e4 LT |
13343 | err = pci_request_regions(pdev, DRV_MODULE_NAME); |
13344 | if (err) { | |
13345 | printk(KERN_ERR PFX "Cannot obtain PCI resources, " | |
13346 | "aborting.\n"); | |
13347 | goto err_out_disable_pdev; | |
13348 | } | |
13349 | ||
13350 | pci_set_master(pdev); | |
13351 | ||
13352 | /* Find power-management capability. */ | |
13353 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
13354 | if (pm_cap == 0) { | |
13355 | printk(KERN_ERR PFX "Cannot find PowerManagement capability, " | |
13356 | "aborting.\n"); | |
13357 | err = -EIO; | |
13358 | goto err_out_free_res; | |
13359 | } | |
13360 | ||
1da177e4 LT |
13361 | dev = alloc_etherdev(sizeof(*tp)); |
13362 | if (!dev) { | |
13363 | printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n"); | |
13364 | err = -ENOMEM; | |
13365 | goto err_out_free_res; | |
13366 | } | |
13367 | ||
1da177e4 LT |
13368 | SET_NETDEV_DEV(dev, &pdev->dev); |
13369 | ||
1da177e4 LT |
13370 | #if TG3_VLAN_TAG_USED |
13371 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
1da177e4 LT |
13372 | #endif |
13373 | ||
13374 | tp = netdev_priv(dev); | |
13375 | tp->pdev = pdev; | |
13376 | tp->dev = dev; | |
13377 | tp->pm_cap = pm_cap; | |
1da177e4 LT |
13378 | tp->rx_mode = TG3_DEF_RX_MODE; |
13379 | tp->tx_mode = TG3_DEF_TX_MODE; | |
8ef21428 | 13380 | |
1da177e4 LT |
13381 | if (tg3_debug > 0) |
13382 | tp->msg_enable = tg3_debug; | |
13383 | else | |
13384 | tp->msg_enable = TG3_DEF_MSG_ENABLE; | |
13385 | ||
13386 | /* The word/byte swap controls here control register access byte | |
13387 | * swapping. DMA data byte swapping is controlled in the GRC_MODE | |
13388 | * setting below. | |
13389 | */ | |
13390 | tp->misc_host_ctrl = | |
13391 | MISC_HOST_CTRL_MASK_PCI_INT | | |
13392 | MISC_HOST_CTRL_WORD_SWAP | | |
13393 | MISC_HOST_CTRL_INDIR_ACCESS | | |
13394 | MISC_HOST_CTRL_PCISTATE_RW; | |
13395 | ||
13396 | /* The NONFRM (non-frame) byte/word swap controls take effect | |
13397 | * on descriptor entries, anything which isn't packet data. | |
13398 | * | |
13399 | * The StrongARM chips on the board (one for tx, one for rx) | |
13400 | * are running in big-endian mode. | |
13401 | */ | |
13402 | tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | | |
13403 | GRC_MODE_WSWAP_NONFRM_DATA); | |
13404 | #ifdef __BIG_ENDIAN | |
13405 | tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; | |
13406 | #endif | |
13407 | spin_lock_init(&tp->lock); | |
1da177e4 | 13408 | spin_lock_init(&tp->indirect_lock); |
c4028958 | 13409 | INIT_WORK(&tp->reset_task, tg3_reset_task); |
1da177e4 | 13410 | |
d5fe488a | 13411 | tp->regs = pci_ioremap_bar(pdev, BAR_0); |
ab0049b4 | 13412 | if (!tp->regs) { |
1da177e4 LT |
13413 | printk(KERN_ERR PFX "Cannot map device registers, " |
13414 | "aborting.\n"); | |
13415 | err = -ENOMEM; | |
13416 | goto err_out_free_dev; | |
13417 | } | |
13418 | ||
13419 | tg3_init_link_config(tp); | |
13420 | ||
1da177e4 LT |
13421 | tp->rx_pending = TG3_DEF_RX_RING_PENDING; |
13422 | tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; | |
1da177e4 | 13423 | |
8ef0442f | 13424 | tp->napi[0].tp = tp; |
898a56f8 | 13425 | tp->napi[0].int_mbox = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; |
72334482 | 13426 | tp->napi[0].consmbox = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW; |
f3f3f27e MC |
13427 | tp->napi[0].prodmbox = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW; |
13428 | tp->napi[0].tx_pending = TG3_DEF_TX_RING_PENDING; | |
8ef0442f | 13429 | netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64); |
1da177e4 | 13430 | dev->ethtool_ops = &tg3_ethtool_ops; |
1da177e4 | 13431 | dev->watchdog_timeo = TG3_TX_TIMEOUT; |
1da177e4 | 13432 | dev->irq = pdev->irq; |
1da177e4 LT |
13433 | |
13434 | err = tg3_get_invariants(tp); | |
13435 | if (err) { | |
13436 | printk(KERN_ERR PFX "Problem fetching invariants of chip, " | |
13437 | "aborting.\n"); | |
13438 | goto err_out_iounmap; | |
13439 | } | |
13440 | ||
321d32a0 | 13441 | if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || |
00829823 SH |
13442 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
13443 | dev->netdev_ops = &tg3_netdev_ops; | |
13444 | else | |
13445 | dev->netdev_ops = &tg3_netdev_ops_dma_bug; | |
13446 | ||
13447 | ||
4a29cc2e MC |
13448 | /* The EPB bridge inside 5714, 5715, and 5780 and any |
13449 | * device behind the EPB cannot support DMA addresses > 40-bit. | |
72f2afb8 MC |
13450 | * On 64-bit systems with IOMMU, use 40-bit dma_mask. |
13451 | * On 64-bit systems without IOMMU, use 64-bit dma_mask and | |
13452 | * do DMA address check in tg3_start_xmit(). | |
13453 | */ | |
4a29cc2e | 13454 | if (tp->tg3_flags2 & TG3_FLG2_IS_5788) |
284901a9 | 13455 | persist_dma_mask = dma_mask = DMA_BIT_MASK(32); |
4a29cc2e | 13456 | else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) { |
50cf156a | 13457 | persist_dma_mask = dma_mask = DMA_BIT_MASK(40); |
72f2afb8 | 13458 | #ifdef CONFIG_HIGHMEM |
6a35528a | 13459 | dma_mask = DMA_BIT_MASK(64); |
72f2afb8 | 13460 | #endif |
4a29cc2e | 13461 | } else |
6a35528a | 13462 | persist_dma_mask = dma_mask = DMA_BIT_MASK(64); |
72f2afb8 MC |
13463 | |
13464 | /* Configure DMA attributes. */ | |
284901a9 | 13465 | if (dma_mask > DMA_BIT_MASK(32)) { |
72f2afb8 MC |
13466 | err = pci_set_dma_mask(pdev, dma_mask); |
13467 | if (!err) { | |
13468 | dev->features |= NETIF_F_HIGHDMA; | |
13469 | err = pci_set_consistent_dma_mask(pdev, | |
13470 | persist_dma_mask); | |
13471 | if (err < 0) { | |
13472 | printk(KERN_ERR PFX "Unable to obtain 64 bit " | |
13473 | "DMA for consistent allocations\n"); | |
13474 | goto err_out_iounmap; | |
13475 | } | |
13476 | } | |
13477 | } | |
284901a9 YH |
13478 | if (err || dma_mask == DMA_BIT_MASK(32)) { |
13479 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
72f2afb8 MC |
13480 | if (err) { |
13481 | printk(KERN_ERR PFX "No usable DMA configuration, " | |
13482 | "aborting.\n"); | |
13483 | goto err_out_iounmap; | |
13484 | } | |
13485 | } | |
13486 | ||
fdfec172 | 13487 | tg3_init_bufmgr_config(tp); |
1da177e4 | 13488 | |
077f849d | 13489 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) |
9e9fd12d | 13490 | tp->fw_needed = FIRMWARE_TG3; |
077f849d | 13491 | |
1da177e4 LT |
13492 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) { |
13493 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; | |
13494 | } | |
13495 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
13496 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || | |
13497 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 || | |
c7835a77 | 13498 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || |
1da177e4 LT |
13499 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) { |
13500 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; | |
13501 | } else { | |
7f62ad5d | 13502 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG; |
077f849d | 13503 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) |
9e9fd12d | 13504 | tp->fw_needed = FIRMWARE_TG3TSO5; |
077f849d | 13505 | else |
9e9fd12d | 13506 | tp->fw_needed = FIRMWARE_TG3TSO; |
077f849d | 13507 | } |
1da177e4 | 13508 | |
4e3a7aaa MC |
13509 | /* TSO is on by default on chips that support hardware TSO. |
13510 | * Firmware TSO on older chips gives lower performance, so it | |
13511 | * is off by default, but can be enabled using ethtool. | |
13512 | */ | |
b0026624 | 13513 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) { |
027455ad MC |
13514 | if (dev->features & NETIF_F_IP_CSUM) |
13515 | dev->features |= NETIF_F_TSO; | |
13516 | if ((dev->features & NETIF_F_IPV6_CSUM) && | |
13517 | (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) | |
b0026624 | 13518 | dev->features |= NETIF_F_TSO6; |
57e6983c MC |
13519 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
13520 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
13521 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
321d32a0 MC |
13522 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
13523 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
9936bcf6 | 13524 | dev->features |= NETIF_F_TSO_ECN; |
b0026624 | 13525 | } |
1da177e4 | 13526 | |
1da177e4 LT |
13527 | |
13528 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 && | |
13529 | !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) && | |
13530 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { | |
13531 | tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64; | |
13532 | tp->rx_pending = 63; | |
13533 | } | |
13534 | ||
1da177e4 LT |
13535 | err = tg3_get_device_address(tp); |
13536 | if (err) { | |
13537 | printk(KERN_ERR PFX "Could not obtain valid ethernet address, " | |
13538 | "aborting.\n"); | |
077f849d | 13539 | goto err_out_fw; |
1da177e4 LT |
13540 | } |
13541 | ||
c88864df | 13542 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
63532394 | 13543 | tp->aperegs = pci_ioremap_bar(pdev, BAR_2); |
79ea13ce | 13544 | if (!tp->aperegs) { |
c88864df MC |
13545 | printk(KERN_ERR PFX "Cannot map APE registers, " |
13546 | "aborting.\n"); | |
13547 | err = -ENOMEM; | |
077f849d | 13548 | goto err_out_fw; |
c88864df MC |
13549 | } |
13550 | ||
13551 | tg3_ape_lock_init(tp); | |
7fd76445 MC |
13552 | |
13553 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) | |
13554 | tg3_read_dash_ver(tp); | |
c88864df MC |
13555 | } |
13556 | ||
1da177e4 LT |
13557 | /* |
13558 | * Reset chip in case UNDI or EFI driver did not shutdown | |
13559 | * DMA self test will enable WDMAC and we'll see (spurious) | |
13560 | * pending DMA on the PCI bus at that point. | |
13561 | */ | |
13562 | if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || | |
13563 | (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { | |
1da177e4 | 13564 | tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); |
944d980e | 13565 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
13566 | } |
13567 | ||
13568 | err = tg3_test_dma(tp); | |
13569 | if (err) { | |
13570 | printk(KERN_ERR PFX "DMA engine test failed, aborting.\n"); | |
c88864df | 13571 | goto err_out_apeunmap; |
1da177e4 LT |
13572 | } |
13573 | ||
1da177e4 LT |
13574 | /* flow control autonegotiation is default behavior */ |
13575 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | |
e18ce346 | 13576 | tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; |
1da177e4 | 13577 | |
15f9850d DM |
13578 | tg3_init_coal(tp); |
13579 | ||
c49a1561 MC |
13580 | pci_set_drvdata(pdev, dev); |
13581 | ||
1da177e4 LT |
13582 | err = register_netdev(dev); |
13583 | if (err) { | |
13584 | printk(KERN_ERR PFX "Cannot register net device, " | |
13585 | "aborting.\n"); | |
0d3031d9 | 13586 | goto err_out_apeunmap; |
1da177e4 LT |
13587 | } |
13588 | ||
df59c940 | 13589 | printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n", |
1da177e4 LT |
13590 | dev->name, |
13591 | tp->board_part_number, | |
13592 | tp->pci_chip_rev_id, | |
f9804ddb | 13593 | tg3_bus_string(tp, str), |
e174961c | 13594 | dev->dev_addr); |
1da177e4 | 13595 | |
df59c940 MC |
13596 | if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) |
13597 | printk(KERN_INFO | |
13598 | "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", | |
13599 | tp->dev->name, | |
13600 | tp->mdio_bus->phy_map[PHY_ADDR]->drv->name, | |
fb28ad35 | 13601 | dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev)); |
df59c940 MC |
13602 | else |
13603 | printk(KERN_INFO | |
13604 | "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n", | |
13605 | tp->dev->name, tg3_phy_string(tp), | |
13606 | ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" : | |
13607 | ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" : | |
13608 | "10/100/1000Base-T")), | |
13609 | (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0); | |
13610 | ||
13611 | printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n", | |
1da177e4 LT |
13612 | dev->name, |
13613 | (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0, | |
13614 | (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0, | |
13615 | (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0, | |
13616 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0, | |
1da177e4 | 13617 | (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0); |
4a29cc2e MC |
13618 | printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n", |
13619 | dev->name, tp->dma_rwctrl, | |
284901a9 | 13620 | (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 : |
50cf156a | 13621 | (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64)); |
1da177e4 LT |
13622 | |
13623 | return 0; | |
13624 | ||
0d3031d9 MC |
13625 | err_out_apeunmap: |
13626 | if (tp->aperegs) { | |
13627 | iounmap(tp->aperegs); | |
13628 | tp->aperegs = NULL; | |
13629 | } | |
13630 | ||
077f849d JSR |
13631 | err_out_fw: |
13632 | if (tp->fw) | |
13633 | release_firmware(tp->fw); | |
13634 | ||
1da177e4 | 13635 | err_out_iounmap: |
6892914f MC |
13636 | if (tp->regs) { |
13637 | iounmap(tp->regs); | |
22abe310 | 13638 | tp->regs = NULL; |
6892914f | 13639 | } |
1da177e4 LT |
13640 | |
13641 | err_out_free_dev: | |
13642 | free_netdev(dev); | |
13643 | ||
13644 | err_out_free_res: | |
13645 | pci_release_regions(pdev); | |
13646 | ||
13647 | err_out_disable_pdev: | |
13648 | pci_disable_device(pdev); | |
13649 | pci_set_drvdata(pdev, NULL); | |
13650 | return err; | |
13651 | } | |
13652 | ||
13653 | static void __devexit tg3_remove_one(struct pci_dev *pdev) | |
13654 | { | |
13655 | struct net_device *dev = pci_get_drvdata(pdev); | |
13656 | ||
13657 | if (dev) { | |
13658 | struct tg3 *tp = netdev_priv(dev); | |
13659 | ||
077f849d JSR |
13660 | if (tp->fw) |
13661 | release_firmware(tp->fw); | |
13662 | ||
7faa006f | 13663 | flush_scheduled_work(); |
158d7abd | 13664 | |
b02fd9e3 MC |
13665 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
13666 | tg3_phy_fini(tp); | |
158d7abd | 13667 | tg3_mdio_fini(tp); |
b02fd9e3 | 13668 | } |
158d7abd | 13669 | |
1da177e4 | 13670 | unregister_netdev(dev); |
0d3031d9 MC |
13671 | if (tp->aperegs) { |
13672 | iounmap(tp->aperegs); | |
13673 | tp->aperegs = NULL; | |
13674 | } | |
6892914f MC |
13675 | if (tp->regs) { |
13676 | iounmap(tp->regs); | |
22abe310 | 13677 | tp->regs = NULL; |
6892914f | 13678 | } |
1da177e4 LT |
13679 | free_netdev(dev); |
13680 | pci_release_regions(pdev); | |
13681 | pci_disable_device(pdev); | |
13682 | pci_set_drvdata(pdev, NULL); | |
13683 | } | |
13684 | } | |
13685 | ||
13686 | static int tg3_suspend(struct pci_dev *pdev, pm_message_t state) | |
13687 | { | |
13688 | struct net_device *dev = pci_get_drvdata(pdev); | |
13689 | struct tg3 *tp = netdev_priv(dev); | |
12dac075 | 13690 | pci_power_t target_state; |
1da177e4 LT |
13691 | int err; |
13692 | ||
3e0c95fd MC |
13693 | /* PCI register 4 needs to be saved whether netif_running() or not. |
13694 | * MSI address and data need to be saved if using MSI and | |
13695 | * netif_running(). | |
13696 | */ | |
13697 | pci_save_state(pdev); | |
13698 | ||
1da177e4 LT |
13699 | if (!netif_running(dev)) |
13700 | return 0; | |
13701 | ||
7faa006f | 13702 | flush_scheduled_work(); |
b02fd9e3 | 13703 | tg3_phy_stop(tp); |
1da177e4 LT |
13704 | tg3_netif_stop(tp); |
13705 | ||
13706 | del_timer_sync(&tp->timer); | |
13707 | ||
f47c11ee | 13708 | tg3_full_lock(tp, 1); |
1da177e4 | 13709 | tg3_disable_ints(tp); |
f47c11ee | 13710 | tg3_full_unlock(tp); |
1da177e4 LT |
13711 | |
13712 | netif_device_detach(dev); | |
13713 | ||
f47c11ee | 13714 | tg3_full_lock(tp, 0); |
944d980e | 13715 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
6a9eba15 | 13716 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; |
f47c11ee | 13717 | tg3_full_unlock(tp); |
1da177e4 | 13718 | |
12dac075 RW |
13719 | target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot; |
13720 | ||
13721 | err = tg3_set_power_state(tp, target_state); | |
1da177e4 | 13722 | if (err) { |
b02fd9e3 MC |
13723 | int err2; |
13724 | ||
f47c11ee | 13725 | tg3_full_lock(tp, 0); |
1da177e4 | 13726 | |
6a9eba15 | 13727 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; |
b02fd9e3 MC |
13728 | err2 = tg3_restart_hw(tp, 1); |
13729 | if (err2) | |
b9ec6c1b | 13730 | goto out; |
1da177e4 LT |
13731 | |
13732 | tp->timer.expires = jiffies + tp->timer_offset; | |
13733 | add_timer(&tp->timer); | |
13734 | ||
13735 | netif_device_attach(dev); | |
13736 | tg3_netif_start(tp); | |
13737 | ||
b9ec6c1b | 13738 | out: |
f47c11ee | 13739 | tg3_full_unlock(tp); |
b02fd9e3 MC |
13740 | |
13741 | if (!err2) | |
13742 | tg3_phy_start(tp); | |
1da177e4 LT |
13743 | } |
13744 | ||
13745 | return err; | |
13746 | } | |
13747 | ||
13748 | static int tg3_resume(struct pci_dev *pdev) | |
13749 | { | |
13750 | struct net_device *dev = pci_get_drvdata(pdev); | |
13751 | struct tg3 *tp = netdev_priv(dev); | |
13752 | int err; | |
13753 | ||
3e0c95fd MC |
13754 | pci_restore_state(tp->pdev); |
13755 | ||
1da177e4 LT |
13756 | if (!netif_running(dev)) |
13757 | return 0; | |
13758 | ||
bc1c7567 | 13759 | err = tg3_set_power_state(tp, PCI_D0); |
1da177e4 LT |
13760 | if (err) |
13761 | return err; | |
13762 | ||
13763 | netif_device_attach(dev); | |
13764 | ||
f47c11ee | 13765 | tg3_full_lock(tp, 0); |
1da177e4 | 13766 | |
6a9eba15 | 13767 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; |
b9ec6c1b MC |
13768 | err = tg3_restart_hw(tp, 1); |
13769 | if (err) | |
13770 | goto out; | |
1da177e4 LT |
13771 | |
13772 | tp->timer.expires = jiffies + tp->timer_offset; | |
13773 | add_timer(&tp->timer); | |
13774 | ||
1da177e4 LT |
13775 | tg3_netif_start(tp); |
13776 | ||
b9ec6c1b | 13777 | out: |
f47c11ee | 13778 | tg3_full_unlock(tp); |
1da177e4 | 13779 | |
b02fd9e3 MC |
13780 | if (!err) |
13781 | tg3_phy_start(tp); | |
13782 | ||
b9ec6c1b | 13783 | return err; |
1da177e4 LT |
13784 | } |
13785 | ||
13786 | static struct pci_driver tg3_driver = { | |
13787 | .name = DRV_MODULE_NAME, | |
13788 | .id_table = tg3_pci_tbl, | |
13789 | .probe = tg3_init_one, | |
13790 | .remove = __devexit_p(tg3_remove_one), | |
13791 | .suspend = tg3_suspend, | |
13792 | .resume = tg3_resume | |
13793 | }; | |
13794 | ||
13795 | static int __init tg3_init(void) | |
13796 | { | |
29917620 | 13797 | return pci_register_driver(&tg3_driver); |
1da177e4 LT |
13798 | } |
13799 | ||
13800 | static void __exit tg3_cleanup(void) | |
13801 | { | |
13802 | pci_unregister_driver(&tg3_driver); | |
13803 | } | |
13804 | ||
13805 | module_init(tg3_init); | |
13806 | module_exit(tg3_cleanup); |