projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $ |
| 2 | * tg3.h: Definitions for Broadcom Tigon3 ethernet driver. | |
| 3 | * | |
| 4 | * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) | |
| 5 | * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com) | |
| 6 | * Copyright (C) 2004 Sun Microsystems Inc. | |
| b86fb2cf | 7 | * Copyright (C) 2007-2011 Broadcom Corporation. |
| 1da177e4 LT |
8 | */ |
| 9 | ||
| 10 | #ifndef _T3_H | |
| 11 | #define _T3_H | |
| 12 | ||
| 13 | #define TG3_64BIT_REG_HIGH 0x00UL | |
| 14 | #define TG3_64BIT_REG_LOW 0x04UL | |
| 15 | ||
| 16 | /* Descriptor block info. */ | |
| 17 | #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */ | |
| 18 | #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */ | |
| 19 | #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */ | |
| 20 | #define BDINFO_FLAGS_DISABLED 0x00000002 | |
| 21 | #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000 | |
| 22 | #define BDINFO_FLAGS_MAXLEN_SHIFT 16 | |
| 23 | #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */ | |
| 24 | #define TG3_BDINFO_SIZE 0x10UL | |
| 25 | ||
| b5d3772c MC |
26 | #define TG3_RX_INTERNAL_RING_SZ_5906 32 |
| 27 | ||
| de9f5230 MC |
28 | #define TG3_RX_STD_MAX_SIZE_5700 512 |
| 29 | #define TG3_RX_STD_MAX_SIZE_5717 2048 | |
| 30 | #define TG3_RX_JMB_MAX_SIZE_5700 256 | |
| 31 | #define TG3_RX_JMB_MAX_SIZE_5717 1024 | |
| 32 | #define TG3_RX_RET_MAX_SIZE_5700 1024 | |
| 33 | #define TG3_RX_RET_MAX_SIZE_5705 512 | |
| 34 | #define TG3_RX_RET_MAX_SIZE_5717 4096 | |
| 1da177e4 LT |
35 | |
| 36 | /* First 256 bytes are a mirror of PCI config space. */ | |
| 37 | #define TG3PCI_VENDOR 0x00000000 | |
| 38 | #define TG3PCI_VENDOR_BROADCOM 0x14e4 | |
| 39 | #define TG3PCI_DEVICE 0x00000002 | |
| 40 | #define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */ | |
| 41 | #define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */ | |
| 42 | #define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */ | |
| 43 | #define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */ | |
| c88e668b MC |
44 | #define TG3PCI_DEVICE_TIGON3_5761S 0x1688 |
| 45 | #define TG3PCI_DEVICE_TIGON3_5761SE 0x1689 | |
| 321d32a0 MC |
46 | #define TG3PCI_DEVICE_TIGON3_57780 0x1692 |
| 47 | #define TG3PCI_DEVICE_TIGON3_57760 0x1690 | |
| 48 | #define TG3PCI_DEVICE_TIGON3_57790 0x1694 | |
| 5e7ccf20 | 49 | #define TG3PCI_DEVICE_TIGON3_57788 0x1691 |
| 2befdcea MC |
50 | #define TG3PCI_DEVICE_TIGON3_5785_G 0x1699 /* GPHY */ |
| 51 | #define TG3PCI_DEVICE_TIGON3_5785_F 0x16a0 /* 10/100 only */ | |
| 5001e2f6 MC |
52 | #define TG3PCI_DEVICE_TIGON3_5717 0x1655 |
| 53 | #define TG3PCI_DEVICE_TIGON3_5718 0x1656 | |
| b703df6f MC |
54 | #define TG3PCI_DEVICE_TIGON3_57781 0x16b1 |
| 55 | #define TG3PCI_DEVICE_TIGON3_57785 0x16b5 | |
| 56 | #define TG3PCI_DEVICE_TIGON3_57761 0x16b0 | |
| 57 | #define TG3PCI_DEVICE_TIGON3_57765 0x16b4 | |
| 58 | #define TG3PCI_DEVICE_TIGON3_57791 0x16b2 | |
| 59 | #define TG3PCI_DEVICE_TIGON3_57795 0x16b6 | |
| a50d0796 | 60 | #define TG3PCI_DEVICE_TIGON3_5719 0x1657 |
| d78b59f5 | 61 | #define TG3PCI_DEVICE_TIGON3_5720 0x165f |
| 24daf2b0 MC |
62 | /* 0x04 --> 0x2c unused */ |
| 63 | #define TG3PCI_SUBVENDOR_ID_BROADCOM PCI_VENDOR_ID_BROADCOM | |
| 64 | #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6 0x1644 | |
| 65 | #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5 0x0001 | |
| 66 | #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6 0x0002 | |
| 67 | #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9 0x0003 | |
| 68 | #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1 0x0005 | |
| 69 | #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8 0x0006 | |
| 70 | #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7 0x0007 | |
| 71 | #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10 0x0008 | |
| 72 | #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12 0x8008 | |
| 73 | #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1 0x0009 | |
| 74 | #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2 0x8009 | |
| 75 | #define TG3PCI_SUBVENDOR_ID_3COM PCI_VENDOR_ID_3COM | |
| 76 | #define TG3PCI_SUBDEVICE_ID_3COM_3C996T 0x1000 | |
| 77 | #define TG3PCI_SUBDEVICE_ID_3COM_3C996BT 0x1006 | |
| 78 | #define TG3PCI_SUBDEVICE_ID_3COM_3C996SX 0x1004 | |
| 79 | #define TG3PCI_SUBDEVICE_ID_3COM_3C1000T 0x1007 | |
| 80 | #define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01 0x1008 | |
| 81 | #define TG3PCI_SUBVENDOR_ID_DELL PCI_VENDOR_ID_DELL | |
| 82 | #define TG3PCI_SUBDEVICE_ID_DELL_VIPER 0x00d1 | |
| 83 | #define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR 0x0106 | |
| 84 | #define TG3PCI_SUBDEVICE_ID_DELL_MERLOT 0x0109 | |
| 85 | #define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT 0x010a | |
| 86 | #define TG3PCI_SUBVENDOR_ID_COMPAQ PCI_VENDOR_ID_COMPAQ | |
| 87 | #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE 0x007c | |
| 88 | #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2 0x009a | |
| 89 | #define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING 0x007d | |
| 90 | #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780 0x0085 | |
| 91 | #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2 0x0099 | |
| 92 | #define TG3PCI_SUBVENDOR_ID_IBM PCI_VENDOR_ID_IBM | |
| 93 | #define TG3PCI_SUBDEVICE_ID_IBM_5703SAX2 0x0281 | |
| 94 | /* 0x30 --> 0x64 unused */ | |
| 1da177e4 LT |
95 | #define TG3PCI_MSI_DATA 0x00000064 |
| 96 | /* 0x66 --> 0x68 unused */ | |
| 97 | #define TG3PCI_MISC_HOST_CTRL 0x00000068 | |
| 98 | #define MISC_HOST_CTRL_CLEAR_INT 0x00000001 | |
| 99 | #define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002 | |
| 100 | #define MISC_HOST_CTRL_BYTE_SWAP 0x00000004 | |
| 101 | #define MISC_HOST_CTRL_WORD_SWAP 0x00000008 | |
| 102 | #define MISC_HOST_CTRL_PCISTATE_RW 0x00000010 | |
| 103 | #define MISC_HOST_CTRL_CLKREG_RW 0x00000020 | |
| 104 | #define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040 | |
| 105 | #define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080 | |
| 106 | #define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100 | |
| 107 | #define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200 | |
| 108 | #define MISC_HOST_CTRL_CHIPREV 0xffff0000 | |
| 109 | #define MISC_HOST_CTRL_CHIPREV_SHIFT 16 | |
| 110 | #define GET_CHIP_REV_ID(MISC_HOST_CTRL) \ | |
| 111 | (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \ | |
| 112 | MISC_HOST_CTRL_CHIPREV_SHIFT) | |
| 113 | #define CHIPREV_ID_5700_A0 0x7000 | |
| 114 | #define CHIPREV_ID_5700_A1 0x7001 | |
| 115 | #define CHIPREV_ID_5700_B0 0x7100 | |
| 116 | #define CHIPREV_ID_5700_B1 0x7101 | |
| 117 | #define CHIPREV_ID_5700_B3 0x7102 | |
| 118 | #define CHIPREV_ID_5700_ALTIMA 0x7104 | |
| 119 | #define CHIPREV_ID_5700_C0 0x7200 | |
| 120 | #define CHIPREV_ID_5701_A0 0x0000 | |
| 121 | #define CHIPREV_ID_5701_B0 0x0100 | |
| 122 | #define CHIPREV_ID_5701_B2 0x0102 | |
| 123 | #define CHIPREV_ID_5701_B5 0x0105 | |
| 124 | #define CHIPREV_ID_5703_A0 0x1000 | |
| 125 | #define CHIPREV_ID_5703_A1 0x1001 | |
| 126 | #define CHIPREV_ID_5703_A2 0x1002 | |
| 127 | #define CHIPREV_ID_5703_A3 0x1003 | |
| 128 | #define CHIPREV_ID_5704_A0 0x2000 | |
| 129 | #define CHIPREV_ID_5704_A1 0x2001 | |
| 130 | #define CHIPREV_ID_5704_A2 0x2002 | |
| 131 | #define CHIPREV_ID_5704_A3 0x2003 | |
| 132 | #define CHIPREV_ID_5705_A0 0x3000 | |
| 133 | #define CHIPREV_ID_5705_A1 0x3001 | |
| 134 | #define CHIPREV_ID_5705_A2 0x3002 | |
| 135 | #define CHIPREV_ID_5705_A3 0x3003 | |
| 136 | #define CHIPREV_ID_5750_A0 0x4000 | |
| 137 | #define CHIPREV_ID_5750_A1 0x4001 | |
| 138 | #define CHIPREV_ID_5750_A3 0x4003 | |
| 52c0fd83 | 139 | #define CHIPREV_ID_5750_C2 0x4202 |
| ff645bec MC |
140 | #define CHIPREV_ID_5752_A0_HW 0x5000 |
| 141 | #define CHIPREV_ID_5752_A0 0x6000 | |
| 053d7800 | 142 | #define CHIPREV_ID_5752_A1 0x6001 |
| 7544b097 | 143 | #define CHIPREV_ID_5714_A2 0x9002 |
| b5d3772c | 144 | #define CHIPREV_ID_5906_A1 0xc001 |
| 9cf74ebb MC |
145 | #define CHIPREV_ID_57780_A0 0x57780000 |
| 146 | #define CHIPREV_ID_57780_A1 0x57780001 | |
| 615774fe | 147 | #define CHIPREV_ID_5717_A0 0x05717000 |
| 6b10c165 | 148 | #define CHIPREV_ID_57765_A0 0x57785000 |
| 4d163b75 | 149 | #define CHIPREV_ID_5719_A0 0x05719000 |
| 1da177e4 LT |
150 | #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) |
| 151 | #define ASIC_REV_5700 0x07 | |
| 152 | #define ASIC_REV_5701 0x00 | |
| 153 | #define ASIC_REV_5703 0x01 | |
| 154 | #define ASIC_REV_5704 0x02 | |
| 155 | #define ASIC_REV_5705 0x03 | |
| 156 | #define ASIC_REV_5750 0x04 | |
| ff645bec | 157 | #define ASIC_REV_5752 0x06 |
| 4cf78e4f | 158 | #define ASIC_REV_5780 0x08 |
| a4e2b347 | 159 | #define ASIC_REV_5714 0x09 |
| af36e6b6 | 160 | #define ASIC_REV_5755 0x0a |
| d9ab5ad1 | 161 | #define ASIC_REV_5787 0x0b |
| b5d3772c | 162 | #define ASIC_REV_5906 0x0c |
| 795d01c5 | 163 | #define ASIC_REV_USE_PROD_ID_REG 0x0f |
| d30cdd28 | 164 | #define ASIC_REV_5784 0x5784 |
| 6b91fa02 | 165 | #define ASIC_REV_5761 0x5761 |
| 57e6983c | 166 | #define ASIC_REV_5785 0x5785 |
| 321d32a0 | 167 | #define ASIC_REV_57780 0x57780 |
| f6eb9b1f | 168 | #define ASIC_REV_5717 0x5717 |
| b703df6f | 169 | #define ASIC_REV_57765 0x57785 |
| a50d0796 | 170 | #define ASIC_REV_5719 0x5719 |
| d78b59f5 | 171 | #define ASIC_REV_5720 0x5720 |
| 1da177e4 LT |
172 | #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8) |
| 173 | #define CHIPREV_5700_AX 0x70 | |
| 174 | #define CHIPREV_5700_BX 0x71 | |
| 175 | #define CHIPREV_5700_CX 0x72 | |
| 176 | #define CHIPREV_5701_AX 0x00 | |
| 177 | #define CHIPREV_5703_AX 0x10 | |
| 178 | #define CHIPREV_5704_AX 0x20 | |
| 179 | #define CHIPREV_5704_BX 0x21 | |
| 180 | #define CHIPREV_5750_AX 0x40 | |
| 181 | #define CHIPREV_5750_BX 0x41 | |
| b2a5c19c MC |
182 | #define CHIPREV_5784_AX 0x57840 |
| 183 | #define CHIPREV_5761_AX 0x57610 | |
| 1da177e4 LT |
184 | #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff) |
| 185 | #define METAL_REV_A0 0x00 | |
| 186 | #define METAL_REV_A1 0x01 | |
| 187 | #define METAL_REV_B0 0x00 | |
| 188 | #define METAL_REV_B1 0x01 | |
| 189 | #define METAL_REV_B2 0x02 | |
| 190 | #define TG3PCI_DMA_RW_CTRL 0x0000006c | |
| cbf9ca6c | 191 | #define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001 |
| 1a319025 | 192 | #define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380 |
| 1da177e4 LT |
193 | #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700 |
| 194 | #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000 | |
| 195 | #define DMA_RWCTRL_READ_BNDRY_16 0x00000100 | |
| 196 | #define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100 | |
| 197 | #define DMA_RWCTRL_READ_BNDRY_32 0x00000200 | |
| 198 | #define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200 | |
| 199 | #define DMA_RWCTRL_READ_BNDRY_64 0x00000300 | |
| 200 | #define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300 | |
| 201 | #define DMA_RWCTRL_READ_BNDRY_128 0x00000400 | |
| 202 | #define DMA_RWCTRL_READ_BNDRY_256 0x00000500 | |
| 203 | #define DMA_RWCTRL_READ_BNDRY_512 0x00000600 | |
| 204 | #define DMA_RWCTRL_READ_BNDRY_1024 0x00000700 | |
| 205 | #define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800 | |
| 206 | #define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000 | |
| 207 | #define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800 | |
| 208 | #define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800 | |
| 209 | #define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000 | |
| 210 | #define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000 | |
| 211 | #define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800 | |
| 212 | #define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800 | |
| 213 | #define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000 | |
| 214 | #define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800 | |
| 215 | #define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000 | |
| 216 | #define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800 | |
| 217 | #define DMA_RWCTRL_ONE_DMA 0x00004000 | |
| 218 | #define DMA_RWCTRL_READ_WATER 0x00070000 | |
| 219 | #define DMA_RWCTRL_READ_WATER_SHIFT 16 | |
| 220 | #define DMA_RWCTRL_WRITE_WATER 0x00380000 | |
| 221 | #define DMA_RWCTRL_WRITE_WATER_SHIFT 19 | |
| 222 | #define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000 | |
| 223 | #define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000 | |
| 224 | #define DMA_RWCTRL_PCI_READ_CMD 0x0f000000 | |
| 225 | #define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24 | |
| 226 | #define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000 | |
| 227 | #define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28 | |
| 228 | #define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000 | |
| 229 | #define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000 | |
| 230 | #define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000 | |
| 231 | #define TG3PCI_PCISTATE 0x00000070 | |
| 232 | #define PCISTATE_FORCE_RESET 0x00000001 | |
| 233 | #define PCISTATE_INT_NOT_ACTIVE 0x00000002 | |
| 234 | #define PCISTATE_CONV_PCI_MODE 0x00000004 | |
| 235 | #define PCISTATE_BUS_SPEED_HIGH 0x00000008 | |
| 236 | #define PCISTATE_BUS_32BIT 0x00000010 | |
| 237 | #define PCISTATE_ROM_ENABLE 0x00000020 | |
| 238 | #define PCISTATE_ROM_RETRY_ENABLE 0x00000040 | |
| 239 | #define PCISTATE_FLAT_VIEW 0x00000100 | |
| 240 | #define PCISTATE_RETRY_SAME_DMA 0x00002000 | |
| 0d3031d9 MC |
241 | #define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000 |
| 242 | #define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000 | |
| f92d9dc1 | 243 | #define PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000 |
| 1da177e4 LT |
244 | #define TG3PCI_CLOCK_CTRL 0x00000074 |
| 245 | #define CLOCK_CTRL_CORECLK_DISABLE 0x00000200 | |
| 246 | #define CLOCK_CTRL_RXCLK_DISABLE 0x00000400 | |
| 247 | #define CLOCK_CTRL_TXCLK_DISABLE 0x00000800 | |
| 248 | #define CLOCK_CTRL_ALTCLK 0x00001000 | |
| 249 | #define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000 | |
| 250 | #define CLOCK_CTRL_44MHZ_CORE 0x00040000 | |
| 251 | #define CLOCK_CTRL_625_CORE 0x00100000 | |
| 252 | #define CLOCK_CTRL_FORCE_CLKRUN 0x00200000 | |
| 253 | #define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000 | |
| 254 | #define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000 | |
| 255 | #define TG3PCI_REG_BASE_ADDR 0x00000078 | |
| 256 | #define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c | |
| 257 | #define TG3PCI_REG_DATA 0x00000080 | |
| 258 | #define TG3PCI_MEM_WIN_DATA 0x00000084 | |
| 1da177e4 LT |
259 | #define TG3PCI_MISC_LOCAL_CTRL 0x00000090 |
| 260 | /* 0x94 --> 0x98 unused */ | |
| 261 | #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */ | |
| 262 | #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */ | |
| c6cdf436 | 263 | /* 0xa8 --> 0xb8 unused */ |
| 1da177e4 LT |
264 | #define TG3PCI_DUAL_MAC_CTRL 0x000000b8 |
| 265 | #define DUAL_MAC_CTRL_CH_MASK 0x00000003 | |
| 266 | #define DUAL_MAC_CTRL_ID 0x00000004 | |
| 795d01c5 MC |
267 | #define TG3PCI_PRODID_ASICREV 0x000000bc |
| 268 | #define PROD_ID_ASIC_REV_MASK 0x0fffffff | |
| f6eb9b1f MC |
269 | /* 0xc0 --> 0xf4 unused */ |
| 270 | ||
| 271 | #define TG3PCI_GEN2_PRODID_ASICREV 0x000000f4 | |
| b703df6f | 272 | #define TG3PCI_GEN15_PRODID_ASICREV 0x000000fc |
| f6eb9b1f | 273 | /* 0xf8 --> 0x200 unused */ |
| 1da177e4 | 274 | |
| 521e6b90 MC |
275 | #define TG3_CORR_ERR_STAT 0x00000110 |
| 276 | #define TG3_CORR_ERR_STAT_CLEAR 0xffffffff | |
| 277 | /* 0x114 --> 0x200 unused */ | |
| 1da177e4 LT |
278 | |
| 279 | /* Mailbox registers */ | |
| 280 | #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */ | |
| 281 | #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */ | |
| 282 | #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */ | |
| 283 | #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */ | |
| 284 | #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */ | |
| 285 | #define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */ | |
| 286 | #define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */ | |
| 287 | #define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */ | |
| 288 | #define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */ | |
| 289 | #define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */ | |
| 290 | #define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */ | |
| 291 | #define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */ | |
| 292 | #define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */ | |
| 293 | #define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */ | |
| 66711e66 MC |
294 | #define TG3_RX_STD_PROD_IDX_REG (MAILBOX_RCV_STD_PROD_IDX + \ |
| 295 | TG3_64BIT_REG_LOW) | |
| 1da177e4 | 296 | #define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */ |
| 66711e66 MC |
297 | #define TG3_RX_JMB_PROD_IDX_REG (MAILBOX_RCV_JUMBO_PROD_IDX + \ |
| 298 | TG3_64BIT_REG_LOW) | |
| 1da177e4 LT |
299 | #define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */ |
| 300 | #define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */ | |
| 301 | #define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */ | |
| 302 | #define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */ | |
| 303 | #define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */ | |
| 304 | #define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */ | |
| 305 | #define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */ | |
| 306 | #define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */ | |
| 307 | #define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */ | |
| 308 | #define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */ | |
| 309 | #define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */ | |
| 310 | #define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */ | |
| 311 | #define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */ | |
| 312 | #define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */ | |
| 313 | #define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */ | |
| 314 | #define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */ | |
| 315 | #define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */ | |
| 316 | #define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */ | |
| 317 | #define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */ | |
| 318 | #define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */ | |
| 319 | #define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */ | |
| 320 | #define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */ | |
| 321 | #define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */ | |
| 322 | #define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */ | |
| 323 | #define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */ | |
| 324 | #define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */ | |
| 325 | #define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */ | |
| 326 | #define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */ | |
| 327 | #define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */ | |
| 328 | #define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */ | |
| 329 | #define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */ | |
| 330 | #define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */ | |
| 331 | #define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */ | |
| 332 | #define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */ | |
| 333 | #define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */ | |
| 334 | #define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */ | |
| 335 | #define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */ | |
| 336 | #define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */ | |
| 337 | #define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */ | |
| 338 | #define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */ | |
| 339 | #define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */ | |
| 340 | #define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */ | |
| 341 | #define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */ | |
| 342 | #define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */ | |
| 343 | #define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */ | |
| 344 | #define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */ | |
| 345 | #define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */ | |
| 346 | #define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */ | |
| 347 | #define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */ | |
| 348 | ||
| 349 | /* MAC control registers */ | |
| 350 | #define MAC_MODE 0x00000400 | |
| 351 | #define MAC_MODE_RESET 0x00000001 | |
| 352 | #define MAC_MODE_HALF_DUPLEX 0x00000002 | |
| 353 | #define MAC_MODE_PORT_MODE_MASK 0x0000000c | |
| 354 | #define MAC_MODE_PORT_MODE_TBI 0x0000000c | |
| 355 | #define MAC_MODE_PORT_MODE_GMII 0x00000008 | |
| 356 | #define MAC_MODE_PORT_MODE_MII 0x00000004 | |
| 357 | #define MAC_MODE_PORT_MODE_NONE 0x00000000 | |
| 358 | #define MAC_MODE_PORT_INT_LPBACK 0x00000010 | |
| 359 | #define MAC_MODE_TAGGED_MAC_CTRL 0x00000080 | |
| 360 | #define MAC_MODE_TX_BURSTING 0x00000100 | |
| 361 | #define MAC_MODE_MAX_DEFER 0x00000200 | |
| 362 | #define MAC_MODE_LINK_POLARITY 0x00000400 | |
| 363 | #define MAC_MODE_RXSTAT_ENABLE 0x00000800 | |
| 364 | #define MAC_MODE_RXSTAT_CLEAR 0x00001000 | |
| 365 | #define MAC_MODE_RXSTAT_FLUSH 0x00002000 | |
| 366 | #define MAC_MODE_TXSTAT_ENABLE 0x00004000 | |
| 367 | #define MAC_MODE_TXSTAT_CLEAR 0x00008000 | |
| 368 | #define MAC_MODE_TXSTAT_FLUSH 0x00010000 | |
| 369 | #define MAC_MODE_SEND_CONFIGS 0x00020000 | |
| 370 | #define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000 | |
| 371 | #define MAC_MODE_ACPI_ENABLE 0x00080000 | |
| 372 | #define MAC_MODE_MIP_ENABLE 0x00100000 | |
| 373 | #define MAC_MODE_TDE_ENABLE 0x00200000 | |
| 374 | #define MAC_MODE_RDE_ENABLE 0x00400000 | |
| 375 | #define MAC_MODE_FHDE_ENABLE 0x00800000 | |
| b2aee154 | 376 | #define MAC_MODE_KEEP_FRAME_IN_WOL 0x01000000 |
| 3bda1258 MC |
377 | #define MAC_MODE_APE_RX_EN 0x08000000 |
| 378 | #define MAC_MODE_APE_TX_EN 0x10000000 | |
| 1da177e4 LT |
379 | #define MAC_STATUS 0x00000404 |
| 380 | #define MAC_STATUS_PCS_SYNCED 0x00000001 | |
| 381 | #define MAC_STATUS_SIGNAL_DET 0x00000002 | |
| 382 | #define MAC_STATUS_RCVD_CFG 0x00000004 | |
| 383 | #define MAC_STATUS_CFG_CHANGED 0x00000008 | |
| 384 | #define MAC_STATUS_SYNC_CHANGED 0x00000010 | |
| 385 | #define MAC_STATUS_PORT_DEC_ERR 0x00000400 | |
| 386 | #define MAC_STATUS_LNKSTATE_CHANGED 0x00001000 | |
| 387 | #define MAC_STATUS_MI_COMPLETION 0x00400000 | |
| 388 | #define MAC_STATUS_MI_INTERRUPT 0x00800000 | |
| 389 | #define MAC_STATUS_AP_ERROR 0x01000000 | |
| 390 | #define MAC_STATUS_ODI_ERROR 0x02000000 | |
| 391 | #define MAC_STATUS_RXSTAT_OVERRUN 0x04000000 | |
| 392 | #define MAC_STATUS_TXSTAT_OVERRUN 0x08000000 | |
| 393 | #define MAC_EVENT 0x00000408 | |
| 394 | #define MAC_EVENT_PORT_DECODE_ERR 0x00000400 | |
| 395 | #define MAC_EVENT_LNKSTATE_CHANGED 0x00001000 | |
| 396 | #define MAC_EVENT_MI_COMPLETION 0x00400000 | |
| 397 | #define MAC_EVENT_MI_INTERRUPT 0x00800000 | |
| 398 | #define MAC_EVENT_AP_ERROR 0x01000000 | |
| 399 | #define MAC_EVENT_ODI_ERROR 0x02000000 | |
| 400 | #define MAC_EVENT_RXSTAT_OVERRUN 0x04000000 | |
| 401 | #define MAC_EVENT_TXSTAT_OVERRUN 0x08000000 | |
| 402 | #define MAC_LED_CTRL 0x0000040c | |
| 403 | #define LED_CTRL_LNKLED_OVERRIDE 0x00000001 | |
| 404 | #define LED_CTRL_1000MBPS_ON 0x00000002 | |
| 405 | #define LED_CTRL_100MBPS_ON 0x00000004 | |
| 406 | #define LED_CTRL_10MBPS_ON 0x00000008 | |
| 407 | #define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010 | |
| 408 | #define LED_CTRL_TRAFFIC_BLINK 0x00000020 | |
| 409 | #define LED_CTRL_TRAFFIC_LED 0x00000040 | |
| 410 | #define LED_CTRL_1000MBPS_STATUS 0x00000080 | |
| 411 | #define LED_CTRL_100MBPS_STATUS 0x00000100 | |
| 412 | #define LED_CTRL_10MBPS_STATUS 0x00000200 | |
| 413 | #define LED_CTRL_TRAFFIC_STATUS 0x00000400 | |
| 414 | #define LED_CTRL_MODE_MAC 0x00000000 | |
| 415 | #define LED_CTRL_MODE_PHY_1 0x00000800 | |
| 416 | #define LED_CTRL_MODE_PHY_2 0x00001000 | |
| 417 | #define LED_CTRL_MODE_SHASTA_MAC 0x00002000 | |
| 418 | #define LED_CTRL_MODE_SHARED 0x00004000 | |
| 419 | #define LED_CTRL_MODE_COMBO 0x00008000 | |
| 420 | #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000 | |
| 421 | #define LED_CTRL_BLINK_RATE_SHIFT 19 | |
| 422 | #define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000 | |
| 423 | #define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000 | |
| 424 | #define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */ | |
| 425 | #define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */ | |
| 426 | #define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */ | |
| 427 | #define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */ | |
| 428 | #define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */ | |
| 429 | #define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */ | |
| 430 | #define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */ | |
| 431 | #define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */ | |
| 432 | #define MAC_ACPI_MBUF_PTR 0x00000430 | |
| 433 | #define MAC_ACPI_LEN_OFFSET 0x00000434 | |
| 434 | #define ACPI_LENOFF_LEN_MASK 0x0000ffff | |
| 435 | #define ACPI_LENOFF_LEN_SHIFT 0 | |
| 436 | #define ACPI_LENOFF_OFF_MASK 0x0fff0000 | |
| 437 | #define ACPI_LENOFF_OFF_SHIFT 16 | |
| 438 | #define MAC_TX_BACKOFF_SEED 0x00000438 | |
| 439 | #define TX_BACKOFF_SEED_MASK 0x000003ff | |
| 440 | #define MAC_RX_MTU_SIZE 0x0000043c | |
| 441 | #define RX_MTU_SIZE_MASK 0x0000ffff | |
| 442 | #define MAC_PCS_TEST 0x00000440 | |
| 443 | #define PCS_TEST_PATTERN_MASK 0x000fffff | |
| 444 | #define PCS_TEST_PATTERN_SHIFT 0 | |
| 445 | #define PCS_TEST_ENABLE 0x00100000 | |
| 446 | #define MAC_TX_AUTO_NEG 0x00000444 | |
| 447 | #define TX_AUTO_NEG_MASK 0x0000ffff | |
| 448 | #define TX_AUTO_NEG_SHIFT 0 | |
| 449 | #define MAC_RX_AUTO_NEG 0x00000448 | |
| 450 | #define RX_AUTO_NEG_MASK 0x0000ffff | |
| 451 | #define RX_AUTO_NEG_SHIFT 0 | |
| 452 | #define MAC_MI_COM 0x0000044c | |
| 453 | #define MI_COM_CMD_MASK 0x0c000000 | |
| 454 | #define MI_COM_CMD_WRITE 0x04000000 | |
| 455 | #define MI_COM_CMD_READ 0x08000000 | |
| 456 | #define MI_COM_READ_FAILED 0x10000000 | |
| 457 | #define MI_COM_START 0x20000000 | |
| 458 | #define MI_COM_BUSY 0x20000000 | |
| 459 | #define MI_COM_PHY_ADDR_MASK 0x03e00000 | |
| 460 | #define MI_COM_PHY_ADDR_SHIFT 21 | |
| 461 | #define MI_COM_REG_ADDR_MASK 0x001f0000 | |
| 462 | #define MI_COM_REG_ADDR_SHIFT 16 | |
| 463 | #define MI_COM_DATA_MASK 0x0000ffff | |
| 464 | #define MAC_MI_STAT 0x00000450 | |
| 465 | #define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001 | |
| fcb389df | 466 | #define MAC_MI_STAT_10MBPS_MODE 0x00000002 |
| 1da177e4 LT |
467 | #define MAC_MI_MODE 0x00000454 |
| 468 | #define MAC_MI_MODE_CLK_10MHZ 0x00000001 | |
| 469 | #define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002 | |
| 470 | #define MAC_MI_MODE_AUTO_POLL 0x00000010 | |
| 8ef21428 | 471 | #define MAC_MI_MODE_500KHZ_CONST 0x00008000 |
| 1da177e4 LT |
472 | #define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */ |
| 473 | #define MAC_AUTO_POLL_STATUS 0x00000458 | |
| 474 | #define MAC_AUTO_POLL_ERROR 0x00000001 | |
| 475 | #define MAC_TX_MODE 0x0000045c | |
| 476 | #define TX_MODE_RESET 0x00000001 | |
| 477 | #define TX_MODE_ENABLE 0x00000002 | |
| 478 | #define TX_MODE_FLOW_CTRL_ENABLE 0x00000010 | |
| 479 | #define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020 | |
| 480 | #define TX_MODE_LONG_PAUSE_ENABLE 0x00000040 | |
| b1d05210 | 481 | #define TX_MODE_MBUF_LOCKUP_FIX 0x00000100 |
| 1da177e4 LT |
482 | #define MAC_TX_STATUS 0x00000460 |
| 483 | #define TX_STATUS_XOFFED 0x00000001 | |
| 484 | #define TX_STATUS_SENT_XOFF 0x00000002 | |
| 485 | #define TX_STATUS_SENT_XON 0x00000004 | |
| 486 | #define TX_STATUS_LINK_UP 0x00000008 | |
| 487 | #define TX_STATUS_ODI_UNDERRUN 0x00000010 | |
| 488 | #define TX_STATUS_ODI_OVERRUN 0x00000020 | |
| 489 | #define MAC_TX_LENGTHS 0x00000464 | |
| 490 | #define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff | |
| 491 | #define TX_LENGTHS_SLOT_TIME_SHIFT 0 | |
| 492 | #define TX_LENGTHS_IPG_MASK 0x00000f00 | |
| 493 | #define TX_LENGTHS_IPG_SHIFT 8 | |
| 494 | #define TX_LENGTHS_IPG_CRS_MASK 0x00003000 | |
| 495 | #define TX_LENGTHS_IPG_CRS_SHIFT 12 | |
| 496 | #define MAC_RX_MODE 0x00000468 | |
| 497 | #define RX_MODE_RESET 0x00000001 | |
| 498 | #define RX_MODE_ENABLE 0x00000002 | |
| 499 | #define RX_MODE_FLOW_CTRL_ENABLE 0x00000004 | |
| 500 | #define RX_MODE_KEEP_MAC_CTRL 0x00000008 | |
| 501 | #define RX_MODE_KEEP_PAUSE 0x00000010 | |
| 502 | #define RX_MODE_ACCEPT_OVERSIZED 0x00000020 | |
| 503 | #define RX_MODE_ACCEPT_RUNTS 0x00000040 | |
| 504 | #define RX_MODE_LEN_CHECK 0x00000080 | |
| 505 | #define RX_MODE_PROMISC 0x00000100 | |
| 506 | #define RX_MODE_NO_CRC_CHECK 0x00000200 | |
| 507 | #define RX_MODE_KEEP_VLAN_TAG 0x00000400 | |
| baf8a94a MC |
508 | #define RX_MODE_RSS_IPV4_HASH_EN 0x00010000 |
| 509 | #define RX_MODE_RSS_TCP_IPV4_HASH_EN 0x00020000 | |
| 510 | #define RX_MODE_RSS_IPV6_HASH_EN 0x00040000 | |
| 511 | #define RX_MODE_RSS_TCP_IPV6_HASH_EN 0x00080000 | |
| 512 | #define RX_MODE_RSS_ITBL_HASH_BITS_7 0x00700000 | |
| 513 | #define RX_MODE_RSS_ENABLE 0x00800000 | |
| af36e6b6 | 514 | #define RX_MODE_IPV6_CSUM_ENABLE 0x01000000 |
| 1da177e4 LT |
515 | #define MAC_RX_STATUS 0x0000046c |
| 516 | #define RX_STATUS_REMOTE_TX_XOFFED 0x00000001 | |
| 517 | #define RX_STATUS_XOFF_RCVD 0x00000002 | |
| 518 | #define RX_STATUS_XON_RCVD 0x00000004 | |
| 519 | #define MAC_HASH_REG_0 0x00000470 | |
| 520 | #define MAC_HASH_REG_1 0x00000474 | |
| 521 | #define MAC_HASH_REG_2 0x00000478 | |
| 522 | #define MAC_HASH_REG_3 0x0000047c | |
| 523 | #define MAC_RCV_RULE_0 0x00000480 | |
| 524 | #define MAC_RCV_VALUE_0 0x00000484 | |
| 525 | #define MAC_RCV_RULE_1 0x00000488 | |
| 526 | #define MAC_RCV_VALUE_1 0x0000048c | |
| 527 | #define MAC_RCV_RULE_2 0x00000490 | |
| 528 | #define MAC_RCV_VALUE_2 0x00000494 | |
| 529 | #define MAC_RCV_RULE_3 0x00000498 | |
| 530 | #define MAC_RCV_VALUE_3 0x0000049c | |
| 531 | #define MAC_RCV_RULE_4 0x000004a0 | |
| 532 | #define MAC_RCV_VALUE_4 0x000004a4 | |
| 533 | #define MAC_RCV_RULE_5 0x000004a8 | |
| 534 | #define MAC_RCV_VALUE_5 0x000004ac | |
| 535 | #define MAC_RCV_RULE_6 0x000004b0 | |
| 536 | #define MAC_RCV_VALUE_6 0x000004b4 | |
| 537 | #define MAC_RCV_RULE_7 0x000004b8 | |
| 538 | #define MAC_RCV_VALUE_7 0x000004bc | |
| 539 | #define MAC_RCV_RULE_8 0x000004c0 | |
| 540 | #define MAC_RCV_VALUE_8 0x000004c4 | |
| 541 | #define MAC_RCV_RULE_9 0x000004c8 | |
| 542 | #define MAC_RCV_VALUE_9 0x000004cc | |
| 543 | #define MAC_RCV_RULE_10 0x000004d0 | |
| 544 | #define MAC_RCV_VALUE_10 0x000004d4 | |
| 545 | #define MAC_RCV_RULE_11 0x000004d8 | |
| 546 | #define MAC_RCV_VALUE_11 0x000004dc | |
| 547 | #define MAC_RCV_RULE_12 0x000004e0 | |
| 548 | #define MAC_RCV_VALUE_12 0x000004e4 | |
| 549 | #define MAC_RCV_RULE_13 0x000004e8 | |
| 550 | #define MAC_RCV_VALUE_13 0x000004ec | |
| 551 | #define MAC_RCV_RULE_14 0x000004f0 | |
| 552 | #define MAC_RCV_VALUE_14 0x000004f4 | |
| 553 | #define MAC_RCV_RULE_15 0x000004f8 | |
| 554 | #define MAC_RCV_VALUE_15 0x000004fc | |
| 555 | #define RCV_RULE_DISABLE_MASK 0x7fffffff | |
| 556 | #define MAC_RCV_RULE_CFG 0x00000500 | |
| 557 | #define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008 | |
| 558 | #define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504 | |
| 559 | /* 0x508 --> 0x520 unused */ | |
| 560 | #define MAC_HASHREGU_0 0x00000520 | |
| 561 | #define MAC_HASHREGU_1 0x00000524 | |
| 562 | #define MAC_HASHREGU_2 0x00000528 | |
| 563 | #define MAC_HASHREGU_3 0x0000052c | |
| 564 | #define MAC_EXTADDR_0_HIGH 0x00000530 | |
| 565 | #define MAC_EXTADDR_0_LOW 0x00000534 | |
| 566 | #define MAC_EXTADDR_1_HIGH 0x00000538 | |
| 567 | #define MAC_EXTADDR_1_LOW 0x0000053c | |
| 568 | #define MAC_EXTADDR_2_HIGH 0x00000540 | |
| 569 | #define MAC_EXTADDR_2_LOW 0x00000544 | |
| 570 | #define MAC_EXTADDR_3_HIGH 0x00000548 | |
| 571 | #define MAC_EXTADDR_3_LOW 0x0000054c | |
| 572 | #define MAC_EXTADDR_4_HIGH 0x00000550 | |
| 573 | #define MAC_EXTADDR_4_LOW 0x00000554 | |
| 574 | #define MAC_EXTADDR_5_HIGH 0x00000558 | |
| 575 | #define MAC_EXTADDR_5_LOW 0x0000055c | |
| 576 | #define MAC_EXTADDR_6_HIGH 0x00000560 | |
| 577 | #define MAC_EXTADDR_6_LOW 0x00000564 | |
| 578 | #define MAC_EXTADDR_7_HIGH 0x00000568 | |
| 579 | #define MAC_EXTADDR_7_LOW 0x0000056c | |
| 580 | #define MAC_EXTADDR_8_HIGH 0x00000570 | |
| 581 | #define MAC_EXTADDR_8_LOW 0x00000574 | |
| 582 | #define MAC_EXTADDR_9_HIGH 0x00000578 | |
| 583 | #define MAC_EXTADDR_9_LOW 0x0000057c | |
| 584 | #define MAC_EXTADDR_10_HIGH 0x00000580 | |
| 585 | #define MAC_EXTADDR_10_LOW 0x00000584 | |
| 586 | #define MAC_EXTADDR_11_HIGH 0x00000588 | |
| 587 | #define MAC_EXTADDR_11_LOW 0x0000058c | |
| 588 | #define MAC_SERDES_CFG 0x00000590 | |
| 589 | #define MAC_SERDES_CFG_EDGE_SELECT 0x00001000 | |
| 590 | #define MAC_SERDES_STAT 0x00000594 | |
| a9daf367 MC |
591 | /* 0x598 --> 0x5a0 unused */ |
| 592 | #define MAC_PHYCFG1 0x000005a0 | |
| 593 | #define MAC_PHYCFG1_RGMII_INT 0x00000001 | |
| bb85fbb6 MC |
594 | #define MAC_PHYCFG1_RXCLK_TO_MASK 0x00001ff0 |
| 595 | #define MAC_PHYCFG1_RXCLK_TIMEOUT 0x00001000 | |
| 596 | #define MAC_PHYCFG1_TXCLK_TO_MASK 0x01ff0000 | |
| 597 | #define MAC_PHYCFG1_TXCLK_TIMEOUT 0x01000000 | |
| a9daf367 MC |
598 | #define MAC_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000 |
| 599 | #define MAC_PHYCFG1_RGMII_SND_STAT_EN 0x04000000 | |
| 600 | #define MAC_PHYCFG1_TXC_DRV 0x20000000 | |
| 601 | #define MAC_PHYCFG2 0x000005a4 | |
| 602 | #define MAC_PHYCFG2_INBAND_ENABLE 0x00000001 | |
| fcb389df MC |
603 | #define MAC_PHYCFG2_EMODE_MASK_MASK 0x000001c0 |
| 604 | #define MAC_PHYCFG2_EMODE_MASK_AC131 0x000000c0 | |
| 605 | #define MAC_PHYCFG2_EMODE_MASK_50610 0x00000100 | |
| 606 | #define MAC_PHYCFG2_EMODE_MASK_RT8211 0x00000000 | |
| 607 | #define MAC_PHYCFG2_EMODE_MASK_RT8201 0x000001c0 | |
| 608 | #define MAC_PHYCFG2_EMODE_COMP_MASK 0x00000e00 | |
| 609 | #define MAC_PHYCFG2_EMODE_COMP_AC131 0x00000600 | |
| 610 | #define MAC_PHYCFG2_EMODE_COMP_50610 0x00000400 | |
| 611 | #define MAC_PHYCFG2_EMODE_COMP_RT8211 0x00000800 | |
| 612 | #define MAC_PHYCFG2_EMODE_COMP_RT8201 0x00000000 | |
| 613 | #define MAC_PHYCFG2_FMODE_MASK_MASK 0x00007000 | |
| 614 | #define MAC_PHYCFG2_FMODE_MASK_AC131 0x00006000 | |
| 615 | #define MAC_PHYCFG2_FMODE_MASK_50610 0x00004000 | |
| 616 | #define MAC_PHYCFG2_FMODE_MASK_RT8211 0x00000000 | |
| 617 | #define MAC_PHYCFG2_FMODE_MASK_RT8201 0x00007000 | |
| 618 | #define MAC_PHYCFG2_FMODE_COMP_MASK 0x00038000 | |
| 619 | #define MAC_PHYCFG2_FMODE_COMP_AC131 0x00030000 | |
| 620 | #define MAC_PHYCFG2_FMODE_COMP_50610 0x00008000 | |
| 621 | #define MAC_PHYCFG2_FMODE_COMP_RT8211 0x00038000 | |
| 622 | #define MAC_PHYCFG2_FMODE_COMP_RT8201 0x00000000 | |
| 623 | #define MAC_PHYCFG2_GMODE_MASK_MASK 0x001c0000 | |
| 624 | #define MAC_PHYCFG2_GMODE_MASK_AC131 0x001c0000 | |
| 625 | #define MAC_PHYCFG2_GMODE_MASK_50610 0x00100000 | |
| 626 | #define MAC_PHYCFG2_GMODE_MASK_RT8211 0x00000000 | |
| 627 | #define MAC_PHYCFG2_GMODE_MASK_RT8201 0x001c0000 | |
| 628 | #define MAC_PHYCFG2_GMODE_COMP_MASK 0x00e00000 | |
| 629 | #define MAC_PHYCFG2_GMODE_COMP_AC131 0x00e00000 | |
| 630 | #define MAC_PHYCFG2_GMODE_COMP_50610 0x00000000 | |
| 631 | #define MAC_PHYCFG2_GMODE_COMP_RT8211 0x00200000 | |
| 632 | #define MAC_PHYCFG2_GMODE_COMP_RT8201 0x00000000 | |
| 633 | #define MAC_PHYCFG2_ACT_MASK_MASK 0x03000000 | |
| 634 | #define MAC_PHYCFG2_ACT_MASK_AC131 0x03000000 | |
| 635 | #define MAC_PHYCFG2_ACT_MASK_50610 0x01000000 | |
| 636 | #define MAC_PHYCFG2_ACT_MASK_RT8211 0x03000000 | |
| 637 | #define MAC_PHYCFG2_ACT_MASK_RT8201 0x01000000 | |
| 638 | #define MAC_PHYCFG2_ACT_COMP_MASK 0x0c000000 | |
| 639 | #define MAC_PHYCFG2_ACT_COMP_AC131 0x00000000 | |
| 640 | #define MAC_PHYCFG2_ACT_COMP_50610 0x00000000 | |
| 641 | #define MAC_PHYCFG2_ACT_COMP_RT8211 0x00000000 | |
| 642 | #define MAC_PHYCFG2_ACT_COMP_RT8201 0x08000000 | |
| 643 | #define MAC_PHYCFG2_QUAL_MASK_MASK 0x30000000 | |
| 644 | #define MAC_PHYCFG2_QUAL_MASK_AC131 0x30000000 | |
| 645 | #define MAC_PHYCFG2_QUAL_MASK_50610 0x30000000 | |
| 646 | #define MAC_PHYCFG2_QUAL_MASK_RT8211 0x30000000 | |
| 647 | #define MAC_PHYCFG2_QUAL_MASK_RT8201 0x30000000 | |
| 648 | #define MAC_PHYCFG2_QUAL_COMP_MASK 0xc0000000 | |
| 649 | #define MAC_PHYCFG2_QUAL_COMP_AC131 0x00000000 | |
| 650 | #define MAC_PHYCFG2_QUAL_COMP_50610 0x00000000 | |
| 651 | #define MAC_PHYCFG2_QUAL_COMP_RT8211 0x00000000 | |
| 652 | #define MAC_PHYCFG2_QUAL_COMP_RT8201 0x00000000 | |
| 653 | #define MAC_PHYCFG2_50610_LED_MODES \ | |
| 654 | (MAC_PHYCFG2_EMODE_MASK_50610 | \ | |
| 655 | MAC_PHYCFG2_EMODE_COMP_50610 | \ | |
| 656 | MAC_PHYCFG2_FMODE_MASK_50610 | \ | |
| 657 | MAC_PHYCFG2_FMODE_COMP_50610 | \ | |
| 658 | MAC_PHYCFG2_GMODE_MASK_50610 | \ | |
| 659 | MAC_PHYCFG2_GMODE_COMP_50610 | \ | |
| 660 | MAC_PHYCFG2_ACT_MASK_50610 | \ | |
| 661 | MAC_PHYCFG2_ACT_COMP_50610 | \ | |
| 662 | MAC_PHYCFG2_QUAL_MASK_50610 | \ | |
| 663 | MAC_PHYCFG2_QUAL_COMP_50610) | |
| 664 | #define MAC_PHYCFG2_AC131_LED_MODES \ | |
| 665 | (MAC_PHYCFG2_EMODE_MASK_AC131 | \ | |
| 666 | MAC_PHYCFG2_EMODE_COMP_AC131 | \ | |
| 667 | MAC_PHYCFG2_FMODE_MASK_AC131 | \ | |
| 668 | MAC_PHYCFG2_FMODE_COMP_AC131 | \ | |
| 669 | MAC_PHYCFG2_GMODE_MASK_AC131 | \ | |
| 670 | MAC_PHYCFG2_GMODE_COMP_AC131 | \ | |
| 671 | MAC_PHYCFG2_ACT_MASK_AC131 | \ | |
| 672 | MAC_PHYCFG2_ACT_COMP_AC131 | \ | |
| 673 | MAC_PHYCFG2_QUAL_MASK_AC131 | \ | |
| 674 | MAC_PHYCFG2_QUAL_COMP_AC131) | |
| 675 | #define MAC_PHYCFG2_RTL8211C_LED_MODES \ | |
| 676 | (MAC_PHYCFG2_EMODE_MASK_RT8211 | \ | |
| 677 | MAC_PHYCFG2_EMODE_COMP_RT8211 | \ | |
| 678 | MAC_PHYCFG2_FMODE_MASK_RT8211 | \ | |
| 679 | MAC_PHYCFG2_FMODE_COMP_RT8211 | \ | |
| 680 | MAC_PHYCFG2_GMODE_MASK_RT8211 | \ | |
| 681 | MAC_PHYCFG2_GMODE_COMP_RT8211 | \ | |
| 682 | MAC_PHYCFG2_ACT_MASK_RT8211 | \ | |
| 683 | MAC_PHYCFG2_ACT_COMP_RT8211 | \ | |
| 684 | MAC_PHYCFG2_QUAL_MASK_RT8211 | \ | |
| 685 | MAC_PHYCFG2_QUAL_COMP_RT8211) | |
| 686 | #define MAC_PHYCFG2_RTL8201E_LED_MODES \ | |
| 687 | (MAC_PHYCFG2_EMODE_MASK_RT8201 | \ | |
| 688 | MAC_PHYCFG2_EMODE_COMP_RT8201 | \ | |
| 689 | MAC_PHYCFG2_FMODE_MASK_RT8201 | \ | |
| 690 | MAC_PHYCFG2_FMODE_COMP_RT8201 | \ | |
| 691 | MAC_PHYCFG2_GMODE_MASK_RT8201 | \ | |
| 692 | MAC_PHYCFG2_GMODE_COMP_RT8201 | \ | |
| 693 | MAC_PHYCFG2_ACT_MASK_RT8201 | \ | |
| 694 | MAC_PHYCFG2_ACT_COMP_RT8201 | \ | |
| 695 | MAC_PHYCFG2_QUAL_MASK_RT8201 | \ | |
| 696 | MAC_PHYCFG2_QUAL_COMP_RT8201) | |
| a9daf367 MC |
697 | #define MAC_EXT_RGMII_MODE 0x000005a8 |
| 698 | #define MAC_RGMII_MODE_TX_ENABLE 0x00000001 | |
| 699 | #define MAC_RGMII_MODE_TX_LOWPWR 0x00000002 | |
| 700 | #define MAC_RGMII_MODE_TX_RESET 0x00000004 | |
| 701 | #define MAC_RGMII_MODE_RX_INT_B 0x00000100 | |
| 702 | #define MAC_RGMII_MODE_RX_QUALITY 0x00000200 | |
| 703 | #define MAC_RGMII_MODE_RX_ACTIVITY 0x00000400 | |
| 704 | #define MAC_RGMII_MODE_RX_ENG_DET 0x00000800 | |
| 705 | /* 0x5ac --> 0x5b0 unused */ | |
| a4e2b347 MC |
706 | #define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */ |
| 707 | #define SERDES_RX_SIG_DETECT 0x00000400 | |
| 1da177e4 LT |
708 | #define SG_DIG_CTRL 0x000005b0 |
| 709 | #define SG_DIG_USING_HW_AUTONEG 0x80000000 | |
| 710 | #define SG_DIG_SOFT_RESET 0x40000000 | |
| 711 | #define SG_DIG_DISABLE_LINKRDY 0x20000000 | |
| 712 | #define SG_DIG_CRC16_CLEAR_N 0x01000000 | |
| 713 | #define SG_DIG_EN10B 0x00800000 | |
| 714 | #define SG_DIG_CLEAR_STATUS 0x00400000 | |
| 715 | #define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000 | |
| 716 | #define SG_DIG_LOCAL_LINK_STATUS 0x00100000 | |
| 717 | #define SG_DIG_SPEED_STATUS_MASK 0x000c0000 | |
| 718 | #define SG_DIG_SPEED_STATUS_SHIFT 18 | |
| 719 | #define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000 | |
| 720 | #define SG_DIG_RESTART_AUTONEG 0x00010000 | |
| 721 | #define SG_DIG_FIBER_MODE 0x00008000 | |
| 722 | #define SG_DIG_REMOTE_FAULT_MASK 0x00006000 | |
| 723 | #define SG_DIG_PAUSE_MASK 0x00001800 | |
| c98f6e3b MC |
724 | #define SG_DIG_PAUSE_CAP 0x00000800 |
| 725 | #define SG_DIG_ASYM_PAUSE 0x00001000 | |
| 1da177e4 LT |
726 | #define SG_DIG_GBIC_ENABLE 0x00000400 |
| 727 | #define SG_DIG_CHECK_END_ENABLE 0x00000200 | |
| 728 | #define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100 | |
| 729 | #define SG_DIG_CLOCK_PHASE_SELECT 0x00000080 | |
| 730 | #define SG_DIG_GMII_INPUT_SELECT 0x00000040 | |
| 731 | #define SG_DIG_MRADV_CRC16_SELECT 0x00000020 | |
| 732 | #define SG_DIG_COMMA_DETECT_ENABLE 0x00000010 | |
| 733 | #define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008 | |
| 734 | #define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004 | |
| 735 | #define SG_DIG_REMOTE_LOOPBACK 0x00000002 | |
| 736 | #define SG_DIG_LOOPBACK 0x00000001 | |
| c98f6e3b MC |
737 | #define SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \ |
| 738 | SG_DIG_LOCAL_DUPLEX_STATUS | \ | |
| 739 | SG_DIG_LOCAL_LINK_STATUS | \ | |
| 740 | (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \ | |
| 741 | SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE) | |
| 1da177e4 LT |
742 | #define SG_DIG_STATUS 0x000005b4 |
| 743 | #define SG_DIG_CRC16_BUS_MASK 0xffff0000 | |
| 744 | #define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */ | |
| 745 | #define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */ | |
| 746 | #define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */ | |
| 747 | #define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */ | |
| 748 | #define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */ | |
| 749 | #define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */ | |
| 750 | #define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0 | |
| 882e9793 | 751 | #define SG_DIG_IS_SERDES 0x00000100 |
| 1da177e4 LT |
752 | #define SG_DIG_COMMA_DETECTOR 0x00000008 |
| 753 | #define SG_DIG_MAC_ACK_STATUS 0x00000004 | |
| 754 | #define SG_DIG_AUTONEG_COMPLETE 0x00000002 | |
| 755 | #define SG_DIG_AUTONEG_ERROR 0x00000001 | |
| 756 | /* 0x5b8 --> 0x600 unused */ | |
| 757 | #define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */ | |
| 758 | #define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */ | |
| baf8a94a MC |
759 | /* 0x624 --> 0x670 unused */ |
| 760 | ||
| 761 | #define MAC_RSS_INDIR_TBL_0 0x00000630 | |
| 762 | ||
| 763 | #define MAC_RSS_HASH_KEY_0 0x00000670 | |
| 764 | #define MAC_RSS_HASH_KEY_1 0x00000674 | |
| 765 | #define MAC_RSS_HASH_KEY_2 0x00000678 | |
| 766 | #define MAC_RSS_HASH_KEY_3 0x0000067c | |
| 767 | #define MAC_RSS_HASH_KEY_4 0x00000680 | |
| 768 | #define MAC_RSS_HASH_KEY_5 0x00000684 | |
| 769 | #define MAC_RSS_HASH_KEY_6 0x00000688 | |
| 770 | #define MAC_RSS_HASH_KEY_7 0x0000068c | |
| 771 | #define MAC_RSS_HASH_KEY_8 0x00000690 | |
| 772 | #define MAC_RSS_HASH_KEY_9 0x00000694 | |
| 773 | /* 0x698 --> 0x800 unused */ | |
| 774 | ||
| 1da177e4 LT |
775 | #define MAC_TX_STATS_OCTETS 0x00000800 |
| 776 | #define MAC_TX_STATS_RESV1 0x00000804 | |
| 777 | #define MAC_TX_STATS_COLLISIONS 0x00000808 | |
| 778 | #define MAC_TX_STATS_XON_SENT 0x0000080c | |
| 779 | #define MAC_TX_STATS_XOFF_SENT 0x00000810 | |
| 780 | #define MAC_TX_STATS_RESV2 0x00000814 | |
| 781 | #define MAC_TX_STATS_MAC_ERRORS 0x00000818 | |
| 782 | #define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c | |
| 783 | #define MAC_TX_STATS_MULT_COLLISIONS 0x00000820 | |
| 784 | #define MAC_TX_STATS_DEFERRED 0x00000824 | |
| 785 | #define MAC_TX_STATS_RESV3 0x00000828 | |
| 786 | #define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c | |
| 787 | #define MAC_TX_STATS_LATE_COL 0x00000830 | |
| 788 | #define MAC_TX_STATS_RESV4_1 0x00000834 | |
| 789 | #define MAC_TX_STATS_RESV4_2 0x00000838 | |
| 790 | #define MAC_TX_STATS_RESV4_3 0x0000083c | |
| 791 | #define MAC_TX_STATS_RESV4_4 0x00000840 | |
| 792 | #define MAC_TX_STATS_RESV4_5 0x00000844 | |
| 793 | #define MAC_TX_STATS_RESV4_6 0x00000848 | |
| 794 | #define MAC_TX_STATS_RESV4_7 0x0000084c | |
| 795 | #define MAC_TX_STATS_RESV4_8 0x00000850 | |
| 796 | #define MAC_TX_STATS_RESV4_9 0x00000854 | |
| 797 | #define MAC_TX_STATS_RESV4_10 0x00000858 | |
| 798 | #define MAC_TX_STATS_RESV4_11 0x0000085c | |
| 799 | #define MAC_TX_STATS_RESV4_12 0x00000860 | |
| 800 | #define MAC_TX_STATS_RESV4_13 0x00000864 | |
| 801 | #define MAC_TX_STATS_RESV4_14 0x00000868 | |
| 802 | #define MAC_TX_STATS_UCAST 0x0000086c | |
| 803 | #define MAC_TX_STATS_MCAST 0x00000870 | |
| 804 | #define MAC_TX_STATS_BCAST 0x00000874 | |
| 805 | #define MAC_TX_STATS_RESV5_1 0x00000878 | |
| 806 | #define MAC_TX_STATS_RESV5_2 0x0000087c | |
| 807 | #define MAC_RX_STATS_OCTETS 0x00000880 | |
| 808 | #define MAC_RX_STATS_RESV1 0x00000884 | |
| 809 | #define MAC_RX_STATS_FRAGMENTS 0x00000888 | |
| 810 | #define MAC_RX_STATS_UCAST 0x0000088c | |
| 811 | #define MAC_RX_STATS_MCAST 0x00000890 | |
| 812 | #define MAC_RX_STATS_BCAST 0x00000894 | |
| 813 | #define MAC_RX_STATS_FCS_ERRORS 0x00000898 | |
| 814 | #define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c | |
| 815 | #define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0 | |
| 816 | #define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4 | |
| 817 | #define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8 | |
| 818 | #define MAC_RX_STATS_XOFF_ENTERED 0x000008ac | |
| 819 | #define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0 | |
| 820 | #define MAC_RX_STATS_JABBERS 0x000008b4 | |
| 821 | #define MAC_RX_STATS_UNDERSIZE 0x000008b8 | |
| 822 | /* 0x8bc --> 0xc00 unused */ | |
| 823 | ||
| 824 | /* Send data initiator control registers */ | |
| 825 | #define SNDDATAI_MODE 0x00000c00 | |
| 826 | #define SNDDATAI_MODE_RESET 0x00000001 | |
| 827 | #define SNDDATAI_MODE_ENABLE 0x00000002 | |
| 828 | #define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004 | |
| 829 | #define SNDDATAI_STATUS 0x00000c04 | |
| 830 | #define SNDDATAI_STATUS_STAT_OFLOW 0x00000004 | |
| 831 | #define SNDDATAI_STATSCTRL 0x00000c08 | |
| 832 | #define SNDDATAI_SCTRL_ENABLE 0x00000001 | |
| 833 | #define SNDDATAI_SCTRL_FASTUPD 0x00000002 | |
| 834 | #define SNDDATAI_SCTRL_CLEAR 0x00000004 | |
| 835 | #define SNDDATAI_SCTRL_FLUSH 0x00000008 | |
| 836 | #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010 | |
| 837 | #define SNDDATAI_STATSENAB 0x00000c0c | |
| 838 | #define SNDDATAI_STATSINCMASK 0x00000c10 | |
| b5d3772c MC |
839 | #define ISO_PKT_TX 0x00000c20 |
| 840 | /* 0xc24 --> 0xc80 unused */ | |
| 1da177e4 LT |
841 | #define SNDDATAI_COS_CNT_0 0x00000c80 |
| 842 | #define SNDDATAI_COS_CNT_1 0x00000c84 | |
| 843 | #define SNDDATAI_COS_CNT_2 0x00000c88 | |
| 844 | #define SNDDATAI_COS_CNT_3 0x00000c8c | |
| 845 | #define SNDDATAI_COS_CNT_4 0x00000c90 | |
| 846 | #define SNDDATAI_COS_CNT_5 0x00000c94 | |
| 847 | #define SNDDATAI_COS_CNT_6 0x00000c98 | |
| 848 | #define SNDDATAI_COS_CNT_7 0x00000c9c | |
| 849 | #define SNDDATAI_COS_CNT_8 0x00000ca0 | |
| 850 | #define SNDDATAI_COS_CNT_9 0x00000ca4 | |
| 851 | #define SNDDATAI_COS_CNT_10 0x00000ca8 | |
| 852 | #define SNDDATAI_COS_CNT_11 0x00000cac | |
| 853 | #define SNDDATAI_COS_CNT_12 0x00000cb0 | |
| 854 | #define SNDDATAI_COS_CNT_13 0x00000cb4 | |
| 855 | #define SNDDATAI_COS_CNT_14 0x00000cb8 | |
| 856 | #define SNDDATAI_COS_CNT_15 0x00000cbc | |
| 857 | #define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0 | |
| 858 | #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4 | |
| 859 | #define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8 | |
| 860 | #define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc | |
| 861 | #define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0 | |
| 862 | #define SNDDATAI_INTERRUPTS_CNT 0x00000cd4 | |
| 863 | #define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8 | |
| 864 | #define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc | |
| 865 | /* 0xce0 --> 0x1000 unused */ | |
| 866 | ||
| 867 | /* Send data completion control registers */ | |
| 868 | #define SNDDATAC_MODE 0x00001000 | |
| 869 | #define SNDDATAC_MODE_RESET 0x00000001 | |
| 870 | #define SNDDATAC_MODE_ENABLE 0x00000002 | |
| 9936bcf6 | 871 | #define SNDDATAC_MODE_CDELAY 0x00000010 |
| 1da177e4 LT |
872 | /* 0x1004 --> 0x1400 unused */ |
| 873 | ||
| 874 | /* Send BD ring selector */ | |
| 875 | #define SNDBDS_MODE 0x00001400 | |
| 876 | #define SNDBDS_MODE_RESET 0x00000001 | |
| 877 | #define SNDBDS_MODE_ENABLE 0x00000002 | |
| 878 | #define SNDBDS_MODE_ATTN_ENABLE 0x00000004 | |
| 879 | #define SNDBDS_STATUS 0x00001404 | |
| 880 | #define SNDBDS_STATUS_ERROR_ATTN 0x00000004 | |
| 881 | #define SNDBDS_HWDIAG 0x00001408 | |
| 882 | /* 0x140c --> 0x1440 */ | |
| 883 | #define SNDBDS_SEL_CON_IDX_0 0x00001440 | |
| 884 | #define SNDBDS_SEL_CON_IDX_1 0x00001444 | |
| 885 | #define SNDBDS_SEL_CON_IDX_2 0x00001448 | |
| 886 | #define SNDBDS_SEL_CON_IDX_3 0x0000144c | |
| 887 | #define SNDBDS_SEL_CON_IDX_4 0x00001450 | |
| 888 | #define SNDBDS_SEL_CON_IDX_5 0x00001454 | |
| 889 | #define SNDBDS_SEL_CON_IDX_6 0x00001458 | |
| 890 | #define SNDBDS_SEL_CON_IDX_7 0x0000145c | |
| 891 | #define SNDBDS_SEL_CON_IDX_8 0x00001460 | |
| 892 | #define SNDBDS_SEL_CON_IDX_9 0x00001464 | |
| 893 | #define SNDBDS_SEL_CON_IDX_10 0x00001468 | |
| 894 | #define SNDBDS_SEL_CON_IDX_11 0x0000146c | |
| 895 | #define SNDBDS_SEL_CON_IDX_12 0x00001470 | |
| 896 | #define SNDBDS_SEL_CON_IDX_13 0x00001474 | |
| 897 | #define SNDBDS_SEL_CON_IDX_14 0x00001478 | |
| 898 | #define SNDBDS_SEL_CON_IDX_15 0x0000147c | |
| 899 | /* 0x1480 --> 0x1800 unused */ | |
| 900 | ||
| 901 | /* Send BD initiator control registers */ | |
| 902 | #define SNDBDI_MODE 0x00001800 | |
| 903 | #define SNDBDI_MODE_RESET 0x00000001 | |
| 904 | #define SNDBDI_MODE_ENABLE 0x00000002 | |
| 905 | #define SNDBDI_MODE_ATTN_ENABLE 0x00000004 | |
| fe5f5787 | 906 | #define SNDBDI_MODE_MULTI_TXQ_EN 0x00000020 |
| 1da177e4 LT |
907 | #define SNDBDI_STATUS 0x00001804 |
| 908 | #define SNDBDI_STATUS_ERROR_ATTN 0x00000004 | |
| 909 | #define SNDBDI_IN_PROD_IDX_0 0x00001808 | |
| 910 | #define SNDBDI_IN_PROD_IDX_1 0x0000180c | |
| 911 | #define SNDBDI_IN_PROD_IDX_2 0x00001810 | |
| 912 | #define SNDBDI_IN_PROD_IDX_3 0x00001814 | |
| 913 | #define SNDBDI_IN_PROD_IDX_4 0x00001818 | |
| 914 | #define SNDBDI_IN_PROD_IDX_5 0x0000181c | |
| 915 | #define SNDBDI_IN_PROD_IDX_6 0x00001820 | |
| 916 | #define SNDBDI_IN_PROD_IDX_7 0x00001824 | |
| 917 | #define SNDBDI_IN_PROD_IDX_8 0x00001828 | |
| 918 | #define SNDBDI_IN_PROD_IDX_9 0x0000182c | |
| 919 | #define SNDBDI_IN_PROD_IDX_10 0x00001830 | |
| 920 | #define SNDBDI_IN_PROD_IDX_11 0x00001834 | |
| 921 | #define SNDBDI_IN_PROD_IDX_12 0x00001838 | |
| 922 | #define SNDBDI_IN_PROD_IDX_13 0x0000183c | |
| 923 | #define SNDBDI_IN_PROD_IDX_14 0x00001840 | |
| 924 | #define SNDBDI_IN_PROD_IDX_15 0x00001844 | |
| 925 | /* 0x1848 --> 0x1c00 unused */ | |
| 926 | ||
| 927 | /* Send BD completion control registers */ | |
| 928 | #define SNDBDC_MODE 0x00001c00 | |
| 929 | #define SNDBDC_MODE_RESET 0x00000001 | |
| 930 | #define SNDBDC_MODE_ENABLE 0x00000002 | |
| 931 | #define SNDBDC_MODE_ATTN_ENABLE 0x00000004 | |
| 932 | /* 0x1c04 --> 0x2000 unused */ | |
| 933 | ||
| 934 | /* Receive list placement control registers */ | |
| 935 | #define RCVLPC_MODE 0x00002000 | |
| 936 | #define RCVLPC_MODE_RESET 0x00000001 | |
| 937 | #define RCVLPC_MODE_ENABLE 0x00000002 | |
| 938 | #define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004 | |
| 939 | #define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008 | |
| 940 | #define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010 | |
| 941 | #define RCVLPC_STATUS 0x00002004 | |
| 942 | #define RCVLPC_STATUS_CLASS0 0x00000004 | |
| 943 | #define RCVLPC_STATUS_MAPOOR 0x00000008 | |
| 944 | #define RCVLPC_STATUS_STAT_OFLOW 0x00000010 | |
| 945 | #define RCVLPC_LOCK 0x00002008 | |
| 946 | #define RCVLPC_LOCK_REQ_MASK 0x0000ffff | |
| 947 | #define RCVLPC_LOCK_REQ_SHIFT 0 | |
| 948 | #define RCVLPC_LOCK_GRANT_MASK 0xffff0000 | |
| 949 | #define RCVLPC_LOCK_GRANT_SHIFT 16 | |
| 950 | #define RCVLPC_NON_EMPTY_BITS 0x0000200c | |
| 951 | #define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff | |
| 952 | #define RCVLPC_CONFIG 0x00002010 | |
| 953 | #define RCVLPC_STATSCTRL 0x00002014 | |
| 954 | #define RCVLPC_STATSCTRL_ENABLE 0x00000001 | |
| 955 | #define RCVLPC_STATSCTRL_FASTUPD 0x00000002 | |
| 956 | #define RCVLPC_STATS_ENABLE 0x00002018 | |
| 255ca311 | 957 | #define RCVLPC_STATSENAB_ASF_FIX 0x00000002 |
| 1661394e | 958 | #define RCVLPC_STATSENAB_DACK_FIX 0x00040000 |
| 1da177e4 LT |
959 | #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000 |
| 960 | #define RCVLPC_STATS_INCMASK 0x0000201c | |
| 961 | /* 0x2020 --> 0x2100 unused */ | |
| 962 | #define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */ | |
| 963 | #define SELLST_TAIL 0x00000004 | |
| 964 | #define SELLST_CONT 0x00000008 | |
| 965 | #define SELLST_UNUSED 0x0000000c | |
| 966 | #define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */ | |
| 967 | #define RCVLPC_DROP_FILTER_CNT 0x00002240 | |
| 968 | #define RCVLPC_DMA_WQ_FULL_CNT 0x00002244 | |
| 969 | #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248 | |
| 970 | #define RCVLPC_NO_RCV_BD_CNT 0x0000224c | |
| 971 | #define RCVLPC_IN_DISCARDS_CNT 0x00002250 | |
| 972 | #define RCVLPC_IN_ERRORS_CNT 0x00002254 | |
| 973 | #define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258 | |
| 974 | /* 0x225c --> 0x2400 unused */ | |
| 975 | ||
| 976 | /* Receive Data and Receive BD Initiator Control */ | |
| 977 | #define RCVDBDI_MODE 0x00002400 | |
| 978 | #define RCVDBDI_MODE_RESET 0x00000001 | |
| 979 | #define RCVDBDI_MODE_ENABLE 0x00000002 | |
| 980 | #define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004 | |
| 981 | #define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008 | |
| 982 | #define RCVDBDI_MODE_INV_RING_SZ 0x00000010 | |
| 7cb32cf2 | 983 | #define RCVDBDI_MODE_LRG_RING_SZ 0x00010000 |
| 1da177e4 LT |
984 | #define RCVDBDI_STATUS 0x00002404 |
| 985 | #define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004 | |
| 986 | #define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008 | |
| 987 | #define RCVDBDI_STATUS_INV_RING_SZ 0x00000010 | |
| 988 | #define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408 | |
| 989 | /* 0x240c --> 0x2440 unused */ | |
| 990 | #define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */ | |
| 991 | #define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */ | |
| 992 | #define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */ | |
| 993 | #define RCVDBDI_JUMBO_CON_IDX 0x00002470 | |
| 994 | #define RCVDBDI_STD_CON_IDX 0x00002474 | |
| 995 | #define RCVDBDI_MINI_CON_IDX 0x00002478 | |
| 996 | /* 0x247c --> 0x2480 unused */ | |
| 997 | #define RCVDBDI_BD_PROD_IDX_0 0x00002480 | |
| 998 | #define RCVDBDI_BD_PROD_IDX_1 0x00002484 | |
| 999 | #define RCVDBDI_BD_PROD_IDX_2 0x00002488 | |
| 1000 | #define RCVDBDI_BD_PROD_IDX_3 0x0000248c | |
| 1001 | #define RCVDBDI_BD_PROD_IDX_4 0x00002490 | |
| 1002 | #define RCVDBDI_BD_PROD_IDX_5 0x00002494 | |
| 1003 | #define RCVDBDI_BD_PROD_IDX_6 0x00002498 | |
| 1004 | #define RCVDBDI_BD_PROD_IDX_7 0x0000249c | |
| 1005 | #define RCVDBDI_BD_PROD_IDX_8 0x000024a0 | |
| 1006 | #define RCVDBDI_BD_PROD_IDX_9 0x000024a4 | |
| 1007 | #define RCVDBDI_BD_PROD_IDX_10 0x000024a8 | |
| 1008 | #define RCVDBDI_BD_PROD_IDX_11 0x000024ac | |
| 1009 | #define RCVDBDI_BD_PROD_IDX_12 0x000024b0 | |
| 1010 | #define RCVDBDI_BD_PROD_IDX_13 0x000024b4 | |
| 1011 | #define RCVDBDI_BD_PROD_IDX_14 0x000024b8 | |
| 1012 | #define RCVDBDI_BD_PROD_IDX_15 0x000024bc | |
| 1013 | #define RCVDBDI_HWDIAG 0x000024c0 | |
| 1014 | /* 0x24c4 --> 0x2800 unused */ | |
| 1015 | ||
| 1016 | /* Receive Data Completion Control */ | |
| 1017 | #define RCVDCC_MODE 0x00002800 | |
| 1018 | #define RCVDCC_MODE_RESET 0x00000001 | |
| 1019 | #define RCVDCC_MODE_ENABLE 0x00000002 | |
| 1020 | #define RCVDCC_MODE_ATTN_ENABLE 0x00000004 | |
| 1021 | /* 0x2804 --> 0x2c00 unused */ | |
| 1022 | ||
| 1023 | /* Receive BD Initiator Control Registers */ | |
| 1024 | #define RCVBDI_MODE 0x00002c00 | |
| 1025 | #define RCVBDI_MODE_RESET 0x00000001 | |
| 1026 | #define RCVBDI_MODE_ENABLE 0x00000002 | |
| 1027 | #define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004 | |
| 1028 | #define RCVBDI_STATUS 0x00002c04 | |
| 1029 | #define RCVBDI_STATUS_RCB_ATTN 0x00000004 | |
| 1030 | #define RCVBDI_JUMBO_PROD_IDX 0x00002c08 | |
| 1031 | #define RCVBDI_STD_PROD_IDX 0x00002c0c | |
| 1032 | #define RCVBDI_MINI_PROD_IDX 0x00002c10 | |
| 1033 | #define RCVBDI_MINI_THRESH 0x00002c14 | |
| 1034 | #define RCVBDI_STD_THRESH 0x00002c18 | |
| 1035 | #define RCVBDI_JUMBO_THRESH 0x00002c1c | |
| f6eb9b1f MC |
1036 | /* 0x2c20 --> 0x2d00 unused */ |
| 1037 | ||
| 1038 | #define STD_REPLENISH_LWM 0x00002d00 | |
| 1039 | #define JMB_REPLENISH_LWM 0x00002d04 | |
| 1040 | /* 0x2d08 --> 0x3000 unused */ | |
| 1da177e4 LT |
1041 | |
| 1042 | /* Receive BD Completion Control Registers */ | |
| 1043 | #define RCVCC_MODE 0x00003000 | |
| 1044 | #define RCVCC_MODE_RESET 0x00000001 | |
| 1045 | #define RCVCC_MODE_ENABLE 0x00000002 | |
| 1046 | #define RCVCC_MODE_ATTN_ENABLE 0x00000004 | |
| 1047 | #define RCVCC_STATUS 0x00003004 | |
| 1048 | #define RCVCC_STATUS_ERROR_ATTN 0x00000004 | |
| 1049 | #define RCVCC_JUMP_PROD_IDX 0x00003008 | |
| 1050 | #define RCVCC_STD_PROD_IDX 0x0000300c | |
| 1051 | #define RCVCC_MINI_PROD_IDX 0x00003010 | |
| 1052 | /* 0x3014 --> 0x3400 unused */ | |
| 1053 | ||
| 1054 | /* Receive list selector control registers */ | |
| 1055 | #define RCVLSC_MODE 0x00003400 | |
| 1056 | #define RCVLSC_MODE_RESET 0x00000001 | |
| 1057 | #define RCVLSC_MODE_ENABLE 0x00000002 | |
| 1058 | #define RCVLSC_MODE_ATTN_ENABLE 0x00000004 | |
| 1059 | #define RCVLSC_STATUS 0x00003404 | |
| 1060 | #define RCVLSC_STATUS_ERROR_ATTN 0x00000004 | |
| d30cdd28 MC |
1061 | /* 0x3408 --> 0x3600 unused */ |
| 1062 | ||
| 1063 | /* CPMU registers */ | |
| 1064 | #define TG3_CPMU_CTRL 0x00003600 | |
| 1065 | #define CPMU_CTRL_LINK_IDLE_MODE 0x00000200 | |
| 1066 | #define CPMU_CTRL_LINK_AWARE_MODE 0x00000400 | |
| 9936bcf6 | 1067 | #define CPMU_CTRL_LINK_SPEED_MODE 0x00004000 |
| b2a5c19c | 1068 | #define CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 |
| 9acb961e MC |
1069 | #define TG3_CPMU_LSPD_10MB_CLK 0x00003604 |
| 1070 | #define CPMU_LSPD_10MB_MACCLK_MASK 0x001f0000 | |
| 1071 | #define CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 | |
| 1072 | /* 0x3608 --> 0x360c unused */ | |
| ce057f01 MC |
1073 | |
| 1074 | #define TG3_CPMU_LSPD_1000MB_CLK 0x0000360c | |
| 1075 | #define CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 | |
| 1076 | #define CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 | |
| 1077 | #define CPMU_LSPD_1000MB_MACCLK_MASK 0x001f0000 | |
| 9acb961e MC |
1078 | #define TG3_CPMU_LNK_AWARE_PWRMD 0x00003610 |
| 1079 | #define CPMU_LNK_AWARE_MACCLK_MASK 0x001f0000 | |
| 1080 | #define CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 | |
| 1081 | /* 0x3614 --> 0x361c unused */ | |
| 1082 | ||
| 1083 | #define TG3_CPMU_HST_ACC 0x0000361c | |
| 1084 | #define CPMU_HST_ACC_MACCLK_MASK 0x001f0000 | |
| 1085 | #define CPMU_HST_ACC_MACCLK_6_25 0x00130000 | |
| 9c7df915 | 1086 | /* 0x3620 --> 0x3630 unused */ |
| aa6c91fe | 1087 | |
| d78b59f5 MC |
1088 | #define TG3_CPMU_CLCK_ORIDE 0x00003624 |
| 1089 | #define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 | |
| 1090 | ||
| aa6c91fe MC |
1091 | #define TG3_CPMU_CLCK_STAT 0x00003630 |
| 1092 | #define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000 | |
| 1093 | #define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 | |
| 1094 | #define CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 | |
| 1095 | #define CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 | |
| 1096 | /* 0x3634 --> 0x365c unused */ | |
| 9936bcf6 MC |
1097 | |
| 1098 | #define TG3_CPMU_MUTEX_REQ 0x0000365c | |
| 1099 | #define CPMU_MUTEX_REQ_DRIVER 0x00001000 | |
| 1100 | #define TG3_CPMU_MUTEX_GNT 0x00003660 | |
| 1101 | #define CPMU_MUTEX_GNT_DRIVER 0x00001000 | |
| d1ec96af MC |
1102 | #define TG3_CPMU_PHY_STRAP 0x00003664 |
| 1103 | #define TG3_CPMU_PHY_STRAP_IS_SERDES 0x00000020 | |
| 52b02d04 MC |
1104 | /* 0x3664 --> 0x36b0 unused */ |
| 1105 | ||
| 1106 | #define TG3_CPMU_EEE_MODE 0x000036b0 | |
| a386b901 MC |
1107 | #define TG3_CPMU_EEEMD_APE_TX_DET_EN 0x00000004 |
| 1108 | #define TG3_CPMU_EEEMD_ERLY_L1_XIT_DET 0x00000008 | |
| 1109 | #define TG3_CPMU_EEEMD_SND_IDX_DET_EN 0x00000040 | |
| 1110 | #define TG3_CPMU_EEEMD_LPI_ENABLE 0x00000080 | |
| 1111 | #define TG3_CPMU_EEEMD_LPI_IN_TX 0x00000100 | |
| 1112 | #define TG3_CPMU_EEEMD_LPI_IN_RX 0x00000200 | |
| 1113 | #define TG3_CPMU_EEEMD_EEE_ENABLE 0x00100000 | |
| 1114 | #define TG3_CPMU_EEE_DBTMR1 0x000036b4 | |
| 1115 | #define TG3_CPMU_DBTMR1_PCIEXIT_2047US 0x07ff0000 | |
| 1116 | #define TG3_CPMU_DBTMR1_LNKIDLE_2047US 0x000070ff | |
| 1117 | #define TG3_CPMU_EEE_DBTMR2 0x000036b8 | |
| d7f2ab20 | 1118 | #define TG3_CPMU_DBTMR2_APE_TX_2047US 0x07ff0000 |
| a386b901 | 1119 | #define TG3_CPMU_DBTMR2_TXIDXEQ_2047US 0x000070ff |
| 52b02d04 MC |
1120 | #define TG3_CPMU_EEE_LNKIDL_CTRL 0x000036bc |
| 1121 | #define TG3_CPMU_EEE_LNKIDL_PCIE_NL0 0x01000000 | |
| 1122 | #define TG3_CPMU_EEE_LNKIDL_UART_IDL 0x00000004 | |
| 1123 | /* 0x36c0 --> 0x36d0 unused */ | |
| 1124 | ||
| 1125 | #define TG3_CPMU_EEE_CTRL 0x000036d0 | |
| 1126 | #define TG3_CPMU_EEE_CTRL_EXIT_16_5_US 0x0000019d | |
| 1127 | #define TG3_CPMU_EEE_CTRL_EXIT_36_US 0x00000384 | |
| 1128 | #define TG3_CPMU_EEE_CTRL_EXIT_20_1_US 0x000001f8 | |
| 1129 | /* 0x36d4 --> 0x3800 unused */ | |
| 1da177e4 LT |
1130 | |
| 1131 | /* Mbuf cluster free registers */ | |
| 1132 | #define MBFREE_MODE 0x00003800 | |
| 1133 | #define MBFREE_MODE_RESET 0x00000001 | |
| 1134 | #define MBFREE_MODE_ENABLE 0x00000002 | |
| 1135 | #define MBFREE_STATUS 0x00003804 | |
| 1136 | /* 0x3808 --> 0x3c00 unused */ | |
| 1137 | ||
| 1138 | /* Host coalescing control registers */ | |
| 1139 | #define HOSTCC_MODE 0x00003c00 | |
| 1140 | #define HOSTCC_MODE_RESET 0x00000001 | |
| 1141 | #define HOSTCC_MODE_ENABLE 0x00000002 | |
| 1142 | #define HOSTCC_MODE_ATTN 0x00000004 | |
| 1143 | #define HOSTCC_MODE_NOW 0x00000008 | |
| 1144 | #define HOSTCC_MODE_FULL_STATUS 0x00000000 | |
| 1145 | #define HOSTCC_MODE_64BYTE 0x00000080 | |
| 1146 | #define HOSTCC_MODE_32BYTE 0x00000100 | |
| 1147 | #define HOSTCC_MODE_CLRTICK_RXBD 0x00000200 | |
| 1148 | #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400 | |
| 1149 | #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800 | |
| 1150 | #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000 | |
| fd2ce37f | 1151 | #define HOSTCC_MODE_COAL_VEC1_NOW 0x00002000 |
| 1da177e4 LT |
1152 | #define HOSTCC_STATUS 0x00003c04 |
| 1153 | #define HOSTCC_STATUS_ERROR_ATTN 0x00000004 | |
| 1154 | #define HOSTCC_RXCOL_TICKS 0x00003c08 | |
| 1155 | #define LOW_RXCOL_TICKS 0x00000032 | |
| 15f9850d | 1156 | #define LOW_RXCOL_TICKS_CLRTCKS 0x00000014 |
| 1da177e4 LT |
1157 | #define DEFAULT_RXCOL_TICKS 0x00000048 |
| 1158 | #define HIGH_RXCOL_TICKS 0x00000096 | |
| d244c892 | 1159 | #define MAX_RXCOL_TICKS 0x000003ff |
| 1da177e4 LT |
1160 | #define HOSTCC_TXCOL_TICKS 0x00003c0c |
| 1161 | #define LOW_TXCOL_TICKS 0x00000096 | |
| 15f9850d | 1162 | #define LOW_TXCOL_TICKS_CLRTCKS 0x00000048 |
| 1da177e4 LT |
1163 | #define DEFAULT_TXCOL_TICKS 0x0000012c |
| 1164 | #define HIGH_TXCOL_TICKS 0x00000145 | |
| d244c892 | 1165 | #define MAX_TXCOL_TICKS 0x000003ff |
| 1da177e4 LT |
1166 | #define HOSTCC_RXMAX_FRAMES 0x00003c10 |
| 1167 | #define LOW_RXMAX_FRAMES 0x00000005 | |
| 1168 | #define DEFAULT_RXMAX_FRAMES 0x00000008 | |
| 1169 | #define HIGH_RXMAX_FRAMES 0x00000012 | |
| d244c892 | 1170 | #define MAX_RXMAX_FRAMES 0x000000ff |
| 1da177e4 LT |
1171 | #define HOSTCC_TXMAX_FRAMES 0x00003c14 |
| 1172 | #define LOW_TXMAX_FRAMES 0x00000035 | |
| 1173 | #define DEFAULT_TXMAX_FRAMES 0x0000004b | |
| 1174 | #define HIGH_TXMAX_FRAMES 0x00000052 | |
| d244c892 | 1175 | #define MAX_TXMAX_FRAMES 0x000000ff |
| 1da177e4 LT |
1176 | #define HOSTCC_RXCOAL_TICK_INT 0x00003c18 |
| 1177 | #define DEFAULT_RXCOAL_TICK_INT 0x00000019 | |
| 15f9850d | 1178 | #define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014 |
| d244c892 | 1179 | #define MAX_RXCOAL_TICK_INT 0x000003ff |
| 1da177e4 LT |
1180 | #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c |
| 1181 | #define DEFAULT_TXCOAL_TICK_INT 0x00000019 | |
| 15f9850d | 1182 | #define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014 |
| d244c892 | 1183 | #define MAX_TXCOAL_TICK_INT 0x000003ff |
| 1da177e4 LT |
1184 | #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20 |
| 1185 | #define DEFAULT_RXCOAL_MAXF_INT 0x00000005 | |
| d244c892 | 1186 | #define MAX_RXCOAL_MAXF_INT 0x000000ff |
| 1da177e4 LT |
1187 | #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24 |
| 1188 | #define DEFAULT_TXCOAL_MAXF_INT 0x00000005 | |
| d244c892 | 1189 | #define MAX_TXCOAL_MAXF_INT 0x000000ff |
| 1da177e4 LT |
1190 | #define HOSTCC_STAT_COAL_TICKS 0x00003c28 |
| 1191 | #define DEFAULT_STAT_COAL_TICKS 0x000f4240 | |
| d244c892 MC |
1192 | #define MAX_STAT_COAL_TICKS 0xd693d400 |
| 1193 | #define MIN_STAT_COAL_TICKS 0x00000064 | |
| 1da177e4 LT |
1194 | /* 0x3c2c --> 0x3c30 unused */ |
| 1195 | #define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */ | |
| 1196 | #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ | |
| 1197 | #define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40 | |
| 1198 | #define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44 | |
| 1199 | #define HOSTCC_FLOW_ATTN 0x00003c48 | |
| 1200 | /* 0x3c4c --> 0x3c50 unused */ | |
| 1201 | #define HOSTCC_JUMBO_CON_IDX 0x00003c50 | |
| 1202 | #define HOSTCC_STD_CON_IDX 0x00003c54 | |
| 1203 | #define HOSTCC_MINI_CON_IDX 0x00003c58 | |
| 1204 | /* 0x3c5c --> 0x3c80 unused */ | |
| 1205 | #define HOSTCC_RET_PROD_IDX_0 0x00003c80 | |
| 1206 | #define HOSTCC_RET_PROD_IDX_1 0x00003c84 | |
| 1207 | #define HOSTCC_RET_PROD_IDX_2 0x00003c88 | |
| 1208 | #define HOSTCC_RET_PROD_IDX_3 0x00003c8c | |
| 1209 | #define HOSTCC_RET_PROD_IDX_4 0x00003c90 | |
| 1210 | #define HOSTCC_RET_PROD_IDX_5 0x00003c94 | |
| 1211 | #define HOSTCC_RET_PROD_IDX_6 0x00003c98 | |
| 1212 | #define HOSTCC_RET_PROD_IDX_7 0x00003c9c | |
| 1213 | #define HOSTCC_RET_PROD_IDX_8 0x00003ca0 | |
| 1214 | #define HOSTCC_RET_PROD_IDX_9 0x00003ca4 | |
| 1215 | #define HOSTCC_RET_PROD_IDX_10 0x00003ca8 | |
| 1216 | #define HOSTCC_RET_PROD_IDX_11 0x00003cac | |
| 1217 | #define HOSTCC_RET_PROD_IDX_12 0x00003cb0 | |
| 1218 | #define HOSTCC_RET_PROD_IDX_13 0x00003cb4 | |
| 1219 | #define HOSTCC_RET_PROD_IDX_14 0x00003cb8 | |
| 1220 | #define HOSTCC_RET_PROD_IDX_15 0x00003cbc | |
| 1221 | #define HOSTCC_SND_CON_IDX_0 0x00003cc0 | |
| 1222 | #define HOSTCC_SND_CON_IDX_1 0x00003cc4 | |
| 1223 | #define HOSTCC_SND_CON_IDX_2 0x00003cc8 | |
| 1224 | #define HOSTCC_SND_CON_IDX_3 0x00003ccc | |
| 1225 | #define HOSTCC_SND_CON_IDX_4 0x00003cd0 | |
| 1226 | #define HOSTCC_SND_CON_IDX_5 0x00003cd4 | |
| 1227 | #define HOSTCC_SND_CON_IDX_6 0x00003cd8 | |
| 1228 | #define HOSTCC_SND_CON_IDX_7 0x00003cdc | |
| 1229 | #define HOSTCC_SND_CON_IDX_8 0x00003ce0 | |
| 1230 | #define HOSTCC_SND_CON_IDX_9 0x00003ce4 | |
| 1231 | #define HOSTCC_SND_CON_IDX_10 0x00003ce8 | |
| 1232 | #define HOSTCC_SND_CON_IDX_11 0x00003cec | |
| 1233 | #define HOSTCC_SND_CON_IDX_12 0x00003cf0 | |
| 1234 | #define HOSTCC_SND_CON_IDX_13 0x00003cf4 | |
| 1235 | #define HOSTCC_SND_CON_IDX_14 0x00003cf8 | |
| 1236 | #define HOSTCC_SND_CON_IDX_15 0x00003cfc | |
| f77a6a8e | 1237 | #define HOSTCC_STATBLCK_RING1 0x00003d00 |
| b6080e12 MC |
1238 | /* 0x3d00 --> 0x3d80 unused */ |
| 1239 | ||
| 1240 | #define HOSTCC_RXCOL_TICKS_VEC1 0x00003d80 | |
| 1241 | #define HOSTCC_TXCOL_TICKS_VEC1 0x00003d84 | |
| 1242 | #define HOSTCC_RXMAX_FRAMES_VEC1 0x00003d88 | |
| 1243 | #define HOSTCC_TXMAX_FRAMES_VEC1 0x00003d8c | |
| 1244 | #define HOSTCC_RXCOAL_MAXF_INT_VEC1 0x00003d90 | |
| 1245 | #define HOSTCC_TXCOAL_MAXF_INT_VEC1 0x00003d94 | |
| 1246 | /* 0x3d98 --> 0x4000 unused */ | |
| 1da177e4 LT |
1247 | |
| 1248 | /* Memory arbiter control registers */ | |
| 1249 | #define MEMARB_MODE 0x00004000 | |
| 1250 | #define MEMARB_MODE_RESET 0x00000001 | |
| 1251 | #define MEMARB_MODE_ENABLE 0x00000002 | |
| 1252 | #define MEMARB_STATUS 0x00004004 | |
| 1253 | #define MEMARB_TRAP_ADDR_LOW 0x00004008 | |
| 1254 | #define MEMARB_TRAP_ADDR_HIGH 0x0000400c | |
| 1255 | /* 0x4010 --> 0x4400 unused */ | |
| 1256 | ||
| 1257 | /* Buffer manager control registers */ | |
| 1258 | #define BUFMGR_MODE 0x00004400 | |
| 1259 | #define BUFMGR_MODE_RESET 0x00000001 | |
| 1260 | #define BUFMGR_MODE_ENABLE 0x00000002 | |
| 1261 | #define BUFMGR_MODE_ATTN_ENABLE 0x00000004 | |
| 1262 | #define BUFMGR_MODE_BM_TEST 0x00000008 | |
| 1263 | #define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010 | |
| d309a46e | 1264 | #define BUFMGR_MODE_NO_TX_UNDERRUN 0x80000000 |
| 1da177e4 LT |
1265 | #define BUFMGR_STATUS 0x00004404 |
| 1266 | #define BUFMGR_STATUS_ERROR 0x00000004 | |
| 1267 | #define BUFMGR_STATUS_MBLOW 0x00000010 | |
| 1268 | #define BUFMGR_MB_POOL_ADDR 0x00004408 | |
| 1269 | #define BUFMGR_MB_POOL_SIZE 0x0000440c | |
| 1270 | #define BUFMGR_MB_RDMA_LOW_WATER 0x00004410 | |
| 1271 | #define DEFAULT_MB_RDMA_LOW_WATER 0x00000050 | |
| 1272 | #define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000 | |
| 1273 | #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130 | |
| fdfec172 | 1274 | #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000 |
| 1da177e4 LT |
1275 | #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414 |
| 1276 | #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020 | |
| 1277 | #define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010 | |
| b5d3772c | 1278 | #define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004 |
| 666bc831 | 1279 | #define DEFAULT_MB_MACRX_LOW_WATER_57765 0x0000002a |
| 1da177e4 | 1280 | #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098 |
| fdfec172 | 1281 | #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b |
| 666bc831 | 1282 | #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765 0x0000007e |
| 1da177e4 LT |
1283 | #define BUFMGR_MB_HIGH_WATER 0x00004418 |
| 1284 | #define DEFAULT_MB_HIGH_WATER 0x00000060 | |
| 1285 | #define DEFAULT_MB_HIGH_WATER_5705 0x00000060 | |
| b5d3772c | 1286 | #define DEFAULT_MB_HIGH_WATER_5906 0x00000010 |
| 666bc831 | 1287 | #define DEFAULT_MB_HIGH_WATER_57765 0x000000a0 |
| 1da177e4 | 1288 | #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c |
| fdfec172 | 1289 | #define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096 |
| 666bc831 | 1290 | #define DEFAULT_MB_HIGH_WATER_JUMBO_57765 0x000000ea |
| 1da177e4 LT |
1291 | #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c |
| 1292 | #define BUFMGR_MB_ALLOC_BIT 0x10000000 | |
| 1293 | #define BUFMGR_RX_MB_ALLOC_RESP 0x00004420 | |
| 1294 | #define BUFMGR_TX_MB_ALLOC_REQ 0x00004424 | |
| 1295 | #define BUFMGR_TX_MB_ALLOC_RESP 0x00004428 | |
| 1296 | #define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c | |
| 1297 | #define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430 | |
| 1298 | #define BUFMGR_DMA_LOW_WATER 0x00004434 | |
| 1299 | #define DEFAULT_DMA_LOW_WATER 0x00000005 | |
| 1300 | #define BUFMGR_DMA_HIGH_WATER 0x00004438 | |
| 1301 | #define DEFAULT_DMA_HIGH_WATER 0x0000000a | |
| 1302 | #define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c | |
| 1303 | #define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440 | |
| 1304 | #define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444 | |
| 1305 | #define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448 | |
| 1306 | #define BUFMGR_HWDIAG_0 0x0000444c | |
| 1307 | #define BUFMGR_HWDIAG_1 0x00004450 | |
| 1308 | #define BUFMGR_HWDIAG_2 0x00004454 | |
| 1309 | /* 0x4458 --> 0x4800 unused */ | |
| 1310 | ||
| 1311 | /* Read DMA control registers */ | |
| 1312 | #define RDMAC_MODE 0x00004800 | |
| 1313 | #define RDMAC_MODE_RESET 0x00000001 | |
| 1314 | #define RDMAC_MODE_ENABLE 0x00000002 | |
| 1315 | #define RDMAC_MODE_TGTABORT_ENAB 0x00000004 | |
| 1316 | #define RDMAC_MODE_MSTABORT_ENAB 0x00000008 | |
| 1317 | #define RDMAC_MODE_PARITYERR_ENAB 0x00000010 | |
| 1318 | #define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020 | |
| 1319 | #define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 | |
| 1320 | #define RDMAC_MODE_FIFOURUN_ENAB 0x00000080 | |
| 1321 | #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100 | |
| 1322 | #define RDMAC_MODE_LNGREAD_ENAB 0x00000200 | |
| 1323 | #define RDMAC_MODE_SPLIT_ENABLE 0x00000800 | |
| d30cdd28 | 1324 | #define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800 |
| 1da177e4 | 1325 | #define RDMAC_MODE_SPLIT_RESET 0x00001000 |
| d30cdd28 MC |
1326 | #define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000 |
| 1327 | #define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000 | |
| 1da177e4 LT |
1328 | #define RDMAC_MODE_FIFO_SIZE_128 0x00020000 |
| 1329 | #define RDMAC_MODE_FIFO_LONG_BURST 0x00030000 | |
| 0339e4e3 | 1330 | #define RDMAC_MODE_MULT_DMA_RD_DIS 0x01000000 |
| 027455ad MC |
1331 | #define RDMAC_MODE_IPV4_LSO_EN 0x08000000 |
| 1332 | #define RDMAC_MODE_IPV6_LSO_EN 0x10000000 | |
| 1da177e4 LT |
1333 | #define RDMAC_STATUS 0x00004804 |
| 1334 | #define RDMAC_STATUS_TGTABORT 0x00000004 | |
| 1335 | #define RDMAC_STATUS_MSTABORT 0x00000008 | |
| 1336 | #define RDMAC_STATUS_PARITYERR 0x00000010 | |
| 1337 | #define RDMAC_STATUS_ADDROFLOW 0x00000020 | |
| 1338 | #define RDMAC_STATUS_FIFOOFLOW 0x00000040 | |
| 1339 | #define RDMAC_STATUS_FIFOURUN 0x00000080 | |
| 1340 | #define RDMAC_STATUS_FIFOOREAD 0x00000100 | |
| 1341 | #define RDMAC_STATUS_LNGREAD 0x00000200 | |
| 41a8a7ee MC |
1342 | /* 0x4808 --> 0x4900 unused */ |
| 1343 | ||
| 1344 | #define TG3_RDMA_RSRVCTRL_REG 0x00004900 | |
| 1345 | #define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 | |
| b4495ed8 MC |
1346 | #define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000c00 |
| 1347 | #define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000ff0 | |
| 1348 | #define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000c0000 | |
| 1349 | #define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000ff000 | |
| b75cc0e4 MC |
1350 | #define TG3_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 |
| 1351 | #define TG3_RDMA_RSRVCTRL_TXMRGN_MASK 0xffe00000 | |
| d309a46e MC |
1352 | /* 0x4904 --> 0x4910 unused */ |
| 1353 | ||
| 1354 | #define TG3_LSO_RD_DMA_CRPTEN_CTRL 0x00004910 | |
| 1355 | #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 | |
| 1356 | #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K 0x000c0000 | |
| 1357 | /* 0x4914 --> 0x4c00 unused */ | |
| 1da177e4 LT |
1358 | |
| 1359 | /* Write DMA control registers */ | |
| 1360 | #define WDMAC_MODE 0x00004c00 | |
| 1361 | #define WDMAC_MODE_RESET 0x00000001 | |
| 1362 | #define WDMAC_MODE_ENABLE 0x00000002 | |
| 1363 | #define WDMAC_MODE_TGTABORT_ENAB 0x00000004 | |
| 1364 | #define WDMAC_MODE_MSTABORT_ENAB 0x00000008 | |
| 1365 | #define WDMAC_MODE_PARITYERR_ENAB 0x00000010 | |
| 1366 | #define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020 | |
| 1367 | #define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 | |
| 1368 | #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080 | |
| 1369 | #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100 | |
| 1370 | #define WDMAC_MODE_LNGREAD_ENAB 0x00000200 | |
| 788a035e | 1371 | #define WDMAC_MODE_RX_ACCEL 0x00000400 |
| f51f3562 | 1372 | #define WDMAC_MODE_STATUS_TAG_FIX 0x20000000 |
| 788a035e | 1373 | #define WDMAC_MODE_BURST_ALL_DATA 0xc0000000 |
| 1da177e4 LT |
1374 | #define WDMAC_STATUS 0x00004c04 |
| 1375 | #define WDMAC_STATUS_TGTABORT 0x00000004 | |
| 1376 | #define WDMAC_STATUS_MSTABORT 0x00000008 | |
| 1377 | #define WDMAC_STATUS_PARITYERR 0x00000010 | |
| 1378 | #define WDMAC_STATUS_ADDROFLOW 0x00000020 | |
| 1379 | #define WDMAC_STATUS_FIFOOFLOW 0x00000040 | |
| 1380 | #define WDMAC_STATUS_FIFOURUN 0x00000080 | |
| 1381 | #define WDMAC_STATUS_FIFOOREAD 0x00000100 | |
| 1382 | #define WDMAC_STATUS_LNGREAD 0x00000200 | |
| 1383 | /* 0x4c08 --> 0x5000 unused */ | |
| 1384 | ||
| 1385 | /* Per-cpu register offsets (arm9) */ | |
| 1386 | #define CPU_MODE 0x00000000 | |
| 1387 | #define CPU_MODE_RESET 0x00000001 | |
| 1388 | #define CPU_MODE_HALT 0x00000400 | |
| 1389 | #define CPU_STATE 0x00000004 | |
| 1390 | #define CPU_EVTMASK 0x00000008 | |
| 1391 | /* 0xc --> 0x1c reserved */ | |
| 1392 | #define CPU_PC 0x0000001c | |
| 1393 | #define CPU_INSN 0x00000020 | |
| 1394 | #define CPU_SPAD_UFLOW 0x00000024 | |
| 1395 | #define CPU_WDOG_CLEAR 0x00000028 | |
| 1396 | #define CPU_WDOG_VECTOR 0x0000002c | |
| 1397 | #define CPU_WDOG_PC 0x00000030 | |
| 1398 | #define CPU_HW_BP 0x00000034 | |
| 1399 | /* 0x38 --> 0x44 unused */ | |
| 1400 | #define CPU_WDOG_SAVED_STATE 0x00000044 | |
| 1401 | #define CPU_LAST_BRANCH_ADDR 0x00000048 | |
| 1402 | #define CPU_SPAD_UFLOW_SET 0x0000004c | |
| 1403 | /* 0x50 --> 0x200 unused */ | |
| 1404 | #define CPU_R0 0x00000200 | |
| 1405 | #define CPU_R1 0x00000204 | |
| 1406 | #define CPU_R2 0x00000208 | |
| 1407 | #define CPU_R3 0x0000020c | |
| 1408 | #define CPU_R4 0x00000210 | |
| 1409 | #define CPU_R5 0x00000214 | |
| 1410 | #define CPU_R6 0x00000218 | |
| 1411 | #define CPU_R7 0x0000021c | |
| 1412 | #define CPU_R8 0x00000220 | |
| 1413 | #define CPU_R9 0x00000224 | |
| 1414 | #define CPU_R10 0x00000228 | |
| 1415 | #define CPU_R11 0x0000022c | |
| 1416 | #define CPU_R12 0x00000230 | |
| 1417 | #define CPU_R13 0x00000234 | |
| 1418 | #define CPU_R14 0x00000238 | |
| 1419 | #define CPU_R15 0x0000023c | |
| 1420 | #define CPU_R16 0x00000240 | |
| 1421 | #define CPU_R17 0x00000244 | |
| 1422 | #define CPU_R18 0x00000248 | |
| 1423 | #define CPU_R19 0x0000024c | |
| 1424 | #define CPU_R20 0x00000250 | |
| 1425 | #define CPU_R21 0x00000254 | |
| 1426 | #define CPU_R22 0x00000258 | |
| 1427 | #define CPU_R23 0x0000025c | |
| 1428 | #define CPU_R24 0x00000260 | |
| 1429 | #define CPU_R25 0x00000264 | |
| 1430 | #define CPU_R26 0x00000268 | |
| 1431 | #define CPU_R27 0x0000026c | |
| 1432 | #define CPU_R28 0x00000270 | |
| 1433 | #define CPU_R29 0x00000274 | |
| 1434 | #define CPU_R30 0x00000278 | |
| 1435 | #define CPU_R31 0x0000027c | |
| 1436 | /* 0x280 --> 0x400 unused */ | |
| 1437 | ||
| 1438 | #define RX_CPU_BASE 0x00005000 | |
| 091465d7 CE |
1439 | #define RX_CPU_MODE 0x00005000 |
| 1440 | #define RX_CPU_STATE 0x00005004 | |
| 1441 | #define RX_CPU_PGMCTR 0x0000501c | |
| 1442 | #define RX_CPU_HWBKPT 0x00005034 | |
| 1da177e4 | 1443 | #define TX_CPU_BASE 0x00005400 |
| 091465d7 CE |
1444 | #define TX_CPU_MODE 0x00005400 |
| 1445 | #define TX_CPU_STATE 0x00005404 | |
| 1446 | #define TX_CPU_PGMCTR 0x0000541c | |
| 1da177e4 | 1447 | |
| b5d3772c MC |
1448 | #define VCPU_STATUS 0x00005100 |
| 1449 | #define VCPU_STATUS_INIT_DONE 0x04000000 | |
| 1450 | #define VCPU_STATUS_DRV_RESET 0x08000000 | |
| 1451 | ||
| 8ed5d97e | 1452 | #define VCPU_CFGSHDW 0x00005104 |
| 0527ba35 MC |
1453 | #define VCPU_CFGSHDW_WOL_ENABLE 0x00000001 |
| 1454 | #define VCPU_CFGSHDW_WOL_MAGPKT 0x00000004 | |
| 8ed5d97e MC |
1455 | #define VCPU_CFGSHDW_ASPM_DBNC 0x00001000 |
| 1456 | ||
| 1da177e4 | 1457 | /* Mailboxes */ |
| b5d3772c | 1458 | #define GRCMBOX_BASE 0x00005600 |
| 1da177e4 LT |
1459 | #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */ |
| 1460 | #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */ | |
| 1461 | #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */ | |
| 1462 | #define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */ | |
| 1463 | #define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */ | |
| 1464 | #define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */ | |
| 1465 | #define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */ | |
| 1466 | #define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */ | |
| 1467 | #define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */ | |
| 1468 | #define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */ | |
| 1469 | #define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */ | |
| 1470 | #define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */ | |
| 1471 | #define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */ | |
| 1472 | #define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */ | |
| 1473 | #define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */ | |
| 1474 | #define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */ | |
| 1475 | #define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */ | |
| 1476 | #define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */ | |
| 1477 | #define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */ | |
| 1478 | #define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */ | |
| 1479 | #define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */ | |
| 1480 | #define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */ | |
| 1481 | #define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */ | |
| 1482 | #define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */ | |
| 1483 | #define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */ | |
| 1484 | #define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */ | |
| 1485 | #define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */ | |
| 1486 | #define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */ | |
| 1487 | #define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */ | |
| 1488 | #define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */ | |
| 1489 | #define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */ | |
| 1490 | #define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */ | |
| 1491 | #define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */ | |
| 1492 | #define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */ | |
| 1493 | #define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */ | |
| 1494 | #define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */ | |
| 1495 | #define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */ | |
| 1496 | #define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */ | |
| 1497 | #define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */ | |
| 1498 | #define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */ | |
| 1499 | #define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */ | |
| 1500 | #define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */ | |
| 1501 | #define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */ | |
| 1502 | #define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */ | |
| 1503 | #define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */ | |
| 1504 | #define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */ | |
| 1505 | #define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */ | |
| 1506 | #define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */ | |
| 1507 | #define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */ | |
| 1508 | #define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */ | |
| 1509 | #define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */ | |
| 1510 | #define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */ | |
| 1511 | #define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */ | |
| 1512 | #define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */ | |
| 1513 | #define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */ | |
| 1514 | #define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */ | |
| 1515 | #define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */ | |
| 1516 | #define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */ | |
| 1517 | #define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */ | |
| 1518 | #define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */ | |
| 1519 | #define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */ | |
| 1520 | #define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */ | |
| 1521 | #define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */ | |
| 1522 | #define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */ | |
| 1523 | #define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00 | |
| 1524 | #define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04 | |
| 1525 | #define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08 | |
| 1526 | #define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c | |
| 1527 | /* 0x5a10 --> 0x5c00 */ | |
| 1528 | ||
| 1529 | /* Flow Through queues */ | |
| 1530 | #define FTQ_RESET 0x00005c00 | |
| 1531 | /* 0x5c04 --> 0x5c10 unused */ | |
| 1532 | #define FTQ_DMA_NORM_READ_CTL 0x00005c10 | |
| 1533 | #define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14 | |
| 1534 | #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18 | |
| 1535 | #define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c | |
| 1536 | #define FTQ_DMA_HIGH_READ_CTL 0x00005c20 | |
| 1537 | #define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24 | |
| 1538 | #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28 | |
| 1539 | #define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c | |
| 1540 | #define FTQ_DMA_COMP_DISC_CTL 0x00005c30 | |
| 1541 | #define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34 | |
| 1542 | #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38 | |
| 1543 | #define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c | |
| 1544 | #define FTQ_SEND_BD_COMP_CTL 0x00005c40 | |
| 1545 | #define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44 | |
| 1546 | #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48 | |
| 1547 | #define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c | |
| 1548 | #define FTQ_SEND_DATA_INIT_CTL 0x00005c50 | |
| 1549 | #define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54 | |
| 1550 | #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58 | |
| 1551 | #define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c | |
| 1552 | #define FTQ_DMA_NORM_WRITE_CTL 0x00005c60 | |
| 1553 | #define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64 | |
| 1554 | #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68 | |
| 1555 | #define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c | |
| 1556 | #define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70 | |
| 1557 | #define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74 | |
| 1558 | #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78 | |
| 1559 | #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c | |
| 1560 | #define FTQ_SWTYPE1_CTL 0x00005c80 | |
| 1561 | #define FTQ_SWTYPE1_FULL_CNT 0x00005c84 | |
| 1562 | #define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88 | |
| 1563 | #define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c | |
| 1564 | #define FTQ_SEND_DATA_COMP_CTL 0x00005c90 | |
| 1565 | #define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94 | |
| 1566 | #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98 | |
| 1567 | #define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c | |
| 1568 | #define FTQ_HOST_COAL_CTL 0x00005ca0 | |
| 1569 | #define FTQ_HOST_COAL_FULL_CNT 0x00005ca4 | |
| 1570 | #define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8 | |
| 1571 | #define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac | |
| 1572 | #define FTQ_MAC_TX_CTL 0x00005cb0 | |
| 1573 | #define FTQ_MAC_TX_FULL_CNT 0x00005cb4 | |
| 1574 | #define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8 | |
| 1575 | #define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc | |
| 1576 | #define FTQ_MB_FREE_CTL 0x00005cc0 | |
| 1577 | #define FTQ_MB_FREE_FULL_CNT 0x00005cc4 | |
| 1578 | #define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8 | |
| 1579 | #define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc | |
| 1580 | #define FTQ_RCVBD_COMP_CTL 0x00005cd0 | |
| 1581 | #define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4 | |
| 1582 | #define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8 | |
| 1583 | #define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc | |
| 1584 | #define FTQ_RCVLST_PLMT_CTL 0x00005ce0 | |
| 1585 | #define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4 | |
| 1586 | #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8 | |
| 1587 | #define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec | |
| 1588 | #define FTQ_RCVDATA_INI_CTL 0x00005cf0 | |
| 1589 | #define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4 | |
| 1590 | #define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8 | |
| 1591 | #define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc | |
| 1592 | #define FTQ_RCVDATA_COMP_CTL 0x00005d00 | |
| 1593 | #define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04 | |
| 1594 | #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08 | |
| 1595 | #define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c | |
| 1596 | #define FTQ_SWTYPE2_CTL 0x00005d10 | |
| 1597 | #define FTQ_SWTYPE2_FULL_CNT 0x00005d14 | |
| 1598 | #define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18 | |
| 1599 | #define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c | |
| 1600 | /* 0x5d20 --> 0x6000 unused */ | |
| 1601 | ||
| 1602 | /* Message signaled interrupt registers */ | |
| 1603 | #define MSGINT_MODE 0x00006000 | |
| 1604 | #define MSGINT_MODE_RESET 0x00000001 | |
| 1605 | #define MSGINT_MODE_ENABLE 0x00000002 | |
| f6eb9b1f | 1606 | #define MSGINT_MODE_ONE_SHOT_DISABLE 0x00000020 |
| baf8a94a | 1607 | #define MSGINT_MODE_MULTIVEC_EN 0x00000080 |
| 1da177e4 LT |
1608 | #define MSGINT_STATUS 0x00006004 |
| 1609 | #define MSGINT_FIFO 0x00006008 | |
| 1610 | /* 0x600c --> 0x6400 unused */ | |
| 1611 | ||
| 1612 | /* DMA completion registers */ | |
| 1613 | #define DMAC_MODE 0x00006400 | |
| 1614 | #define DMAC_MODE_RESET 0x00000001 | |
| 1615 | #define DMAC_MODE_ENABLE 0x00000002 | |
| 1616 | /* 0x6404 --> 0x6800 unused */ | |
| 1617 | ||
| 1618 | /* GRC registers */ | |
| 1619 | #define GRC_MODE 0x00006800 | |
| 1620 | #define GRC_MODE_UPD_ON_COAL 0x00000001 | |
| 1621 | #define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002 | |
| 1622 | #define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004 | |
| 1623 | #define GRC_MODE_BSWAP_DATA 0x00000010 | |
| 1624 | #define GRC_MODE_WSWAP_DATA 0x00000020 | |
| 1625 | #define GRC_MODE_SPLITHDR 0x00000100 | |
| 1626 | #define GRC_MODE_NOFRM_CRACKING 0x00000200 | |
| 1627 | #define GRC_MODE_INCL_CRC 0x00000400 | |
| 1628 | #define GRC_MODE_ALLOW_BAD_FRMS 0x00000800 | |
| 1629 | #define GRC_MODE_NOIRQ_ON_SENDS 0x00002000 | |
| 1630 | #define GRC_MODE_NOIRQ_ON_RCV 0x00004000 | |
| 1631 | #define GRC_MODE_FORCE_PCI32BIT 0x00008000 | |
| 1632 | #define GRC_MODE_HOST_STACKUP 0x00010000 | |
| 1633 | #define GRC_MODE_HOST_SENDBDS 0x00020000 | |
| 1634 | #define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000 | |
| 1635 | #define GRC_MODE_NVRAM_WR_ENABLE 0x00200000 | |
| 614b0590 MC |
1636 | #define GRC_MODE_PCIE_TL_SEL 0x00000000 |
| 1637 | #define GRC_MODE_PCIE_PL_SEL 0x00400000 | |
| 1da177e4 LT |
1638 | #define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000 |
| 1639 | #define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000 | |
| 1640 | #define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000 | |
| 1641 | #define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000 | |
| 1642 | #define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000 | |
| 1643 | #define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000 | |
| 1644 | #define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000 | |
| 614b0590 | 1645 | #define GRC_MODE_PCIE_DL_SEL 0x20000000 |
| 1da177e4 | 1646 | #define GRC_MODE_MCAST_FRM_ENABLE 0x40000000 |
| 614b0590 MC |
1647 | #define GRC_MODE_PCIE_HI_1K_EN 0x80000000 |
| 1648 | #define GRC_MODE_PCIE_PORT_MASK (GRC_MODE_PCIE_TL_SEL | \ | |
| 1649 | GRC_MODE_PCIE_PL_SEL | \ | |
| 1650 | GRC_MODE_PCIE_DL_SEL | \ | |
| 1651 | GRC_MODE_PCIE_HI_1K_EN) | |
| 1da177e4 LT |
1652 | #define GRC_MISC_CFG 0x00006804 |
| 1653 | #define GRC_MISC_CFG_CORECLK_RESET 0x00000001 | |
| 1654 | #define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe | |
| 1655 | #define GRC_MISC_CFG_PRESCALAR_SHIFT 1 | |
| 1656 | #define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000 | |
| 1657 | #define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000 | |
| 1658 | #define GRC_MISC_CFG_BOARD_ID_5701 0x00000000 | |
| 1659 | #define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000 | |
| 1660 | #define GRC_MISC_CFG_BOARD_ID_5703 0x00000000 | |
| 1661 | #define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000 | |
| 1662 | #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000 | |
| 1663 | #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000 | |
| 1664 | #define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000 | |
| 1665 | #define GRC_MISC_CFG_BOARD_ID_5788 0x00010000 | |
| 1666 | #define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000 | |
| 1667 | #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000 | |
| 60189ddf | 1668 | #define GRC_MISC_CFG_EPHY_IDDQ 0x00200000 |
| 1da177e4 LT |
1669 | #define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000 |
| 1670 | #define GRC_LOCAL_CTRL 0x00006808 | |
| 1671 | #define GRC_LCLCTRL_INT_ACTIVE 0x00000001 | |
| 1672 | #define GRC_LCLCTRL_CLEARINT 0x00000002 | |
| 1673 | #define GRC_LCLCTRL_SETINT 0x00000004 | |
| 1674 | #define GRC_LCLCTRL_INT_ON_ATTN 0x00000008 | |
| af36e6b6 | 1675 | #define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */ |
| a4e2b347 MC |
1676 | #define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */ |
| 1677 | #define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */ | |
| 3e7d83bc MC |
1678 | #define GRC_LCLCTRL_GPIO_INPUT3 0x00000020 |
| 1679 | #define GRC_LCLCTRL_GPIO_OE3 0x00000040 | |
| 1680 | #define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080 | |
| 1da177e4 LT |
1681 | #define GRC_LCLCTRL_GPIO_INPUT0 0x00000100 |
| 1682 | #define GRC_LCLCTRL_GPIO_INPUT1 0x00000200 | |
| 1683 | #define GRC_LCLCTRL_GPIO_INPUT2 0x00000400 | |
| 1684 | #define GRC_LCLCTRL_GPIO_OE0 0x00000800 | |
| 1685 | #define GRC_LCLCTRL_GPIO_OE1 0x00001000 | |
| 1686 | #define GRC_LCLCTRL_GPIO_OE2 0x00002000 | |
| 1687 | #define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000 | |
| 1688 | #define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000 | |
| 1689 | #define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000 | |
| 1690 | #define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000 | |
| 1691 | #define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000 | |
| 1692 | #define GRC_LCLCTRL_MEMSZ_256K 0x00000000 | |
| 1693 | #define GRC_LCLCTRL_MEMSZ_512K 0x00040000 | |
| 1694 | #define GRC_LCLCTRL_MEMSZ_1M 0x00080000 | |
| 1695 | #define GRC_LCLCTRL_MEMSZ_2M 0x000c0000 | |
| 1696 | #define GRC_LCLCTRL_MEMSZ_4M 0x00100000 | |
| 1697 | #define GRC_LCLCTRL_MEMSZ_8M 0x00140000 | |
| 1698 | #define GRC_LCLCTRL_MEMSZ_16M 0x00180000 | |
| 1699 | #define GRC_LCLCTRL_BANK_SELECT 0x00200000 | |
| 1700 | #define GRC_LCLCTRL_SSRAM_TYPE 0x00400000 | |
| 1701 | #define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000 | |
| 1702 | #define GRC_TIMER 0x0000680c | |
| 1703 | #define GRC_RX_CPU_EVENT 0x00006810 | |
| 7c5026aa | 1704 | #define GRC_RX_CPU_DRIVER_EVENT 0x00004000 |
| 1da177e4 LT |
1705 | #define GRC_RX_TIMER_REF 0x00006814 |
| 1706 | #define GRC_RX_CPU_SEM 0x00006818 | |
| 1707 | #define GRC_REMOTE_RX_CPU_ATTN 0x0000681c | |
| 1708 | #define GRC_TX_CPU_EVENT 0x00006820 | |
| 1709 | #define GRC_TX_TIMER_REF 0x00006824 | |
| 1710 | #define GRC_TX_CPU_SEM 0x00006828 | |
| 1711 | #define GRC_REMOTE_TX_CPU_ATTN 0x0000682c | |
| 1712 | #define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */ | |
| 1713 | #define GRC_EEPROM_ADDR 0x00006838 | |
| 1714 | #define EEPROM_ADDR_WRITE 0x00000000 | |
| 1715 | #define EEPROM_ADDR_READ 0x80000000 | |
| 1716 | #define EEPROM_ADDR_COMPLETE 0x40000000 | |
| 1717 | #define EEPROM_ADDR_FSM_RESET 0x20000000 | |
| 1718 | #define EEPROM_ADDR_DEVID_MASK 0x1c000000 | |
| 1719 | #define EEPROM_ADDR_DEVID_SHIFT 26 | |
| 1720 | #define EEPROM_ADDR_START 0x02000000 | |
| 1721 | #define EEPROM_ADDR_CLKPERD_SHIFT 16 | |
| 1722 | #define EEPROM_ADDR_ADDR_MASK 0x0000ffff | |
| 1723 | #define EEPROM_ADDR_ADDR_SHIFT 0 | |
| 1724 | #define EEPROM_DEFAULT_CLOCK_PERIOD 0x60 | |
| 1725 | #define EEPROM_CHIP_SIZE (64 * 1024) | |
| 1726 | #define GRC_EEPROM_DATA 0x0000683c | |
| 1727 | #define GRC_EEPROM_CTRL 0x00006840 | |
| 1728 | #define GRC_MDI_CTRL 0x00006844 | |
| 1729 | #define GRC_SEEPROM_DELAY 0x00006848 | |
| b5d3772c MC |
1730 | /* 0x684c --> 0x6890 unused */ |
| 1731 | #define GRC_VCPU_EXT_CTRL 0x00006890 | |
| 1732 | #define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000 | |
| 1733 | #define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 | |
| d9ab5ad1 | 1734 | #define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */ |
| 1da177e4 LT |
1735 | |
| 1736 | /* 0x6c00 --> 0x7000 unused */ | |
| 1737 | ||
| 1738 | /* NVRAM Control registers */ | |
| 1739 | #define NVRAM_CMD 0x00007000 | |
| 1740 | #define NVRAM_CMD_RESET 0x00000001 | |
| 1741 | #define NVRAM_CMD_DONE 0x00000008 | |
| 1742 | #define NVRAM_CMD_GO 0x00000010 | |
| 1743 | #define NVRAM_CMD_WR 0x00000020 | |
| 1744 | #define NVRAM_CMD_RD 0x00000000 | |
| 1745 | #define NVRAM_CMD_ERASE 0x00000040 | |
| 1746 | #define NVRAM_CMD_FIRST 0x00000080 | |
| 1747 | #define NVRAM_CMD_LAST 0x00000100 | |
| 1748 | #define NVRAM_CMD_WREN 0x00010000 | |
| 1749 | #define NVRAM_CMD_WRDI 0x00020000 | |
| 1750 | #define NVRAM_STAT 0x00007004 | |
| 1751 | #define NVRAM_WRDATA 0x00007008 | |
| 1752 | #define NVRAM_ADDR 0x0000700c | |
| 1753 | #define NVRAM_ADDR_MSK 0x00ffffff | |
| 1754 | #define NVRAM_RDDATA 0x00007010 | |
| 1755 | #define NVRAM_CFG1 0x00007014 | |
| 1756 | #define NVRAM_CFG1_FLASHIF_ENAB 0x00000001 | |
| 1757 | #define NVRAM_CFG1_BUFFERED_MODE 0x00000002 | |
| 1758 | #define NVRAM_CFG1_PASS_THRU 0x00000004 | |
| 1759 | #define NVRAM_CFG1_STATUS_BITS 0x00000070 | |
| 1760 | #define NVRAM_CFG1_BIT_BANG 0x00000008 | |
| 1761 | #define NVRAM_CFG1_FLASH_SIZE 0x02000000 | |
| 1762 | #define NVRAM_CFG1_COMPAT_BYPASS 0x80000000 | |
| 1763 | #define NVRAM_CFG1_VENDOR_MASK 0x03000003 | |
| 1764 | #define FLASH_VENDOR_ATMEL_EEPROM 0x02000000 | |
| 1765 | #define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003 | |
| 1766 | #define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003 | |
| 1767 | #define FLASH_VENDOR_ST 0x03000001 | |
| 1768 | #define FLASH_VENDOR_SAIFUN 0x01000003 | |
| 1769 | #define FLASH_VENDOR_SST_SMALL 0x00000001 | |
| 1770 | #define FLASH_VENDOR_SST_LARGE 0x02000001 | |
| 361b4ac2 MC |
1771 | #define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003 |
| 1772 | #define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000 | |
| 1773 | #define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000 | |
| 1774 | #define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003 | |
| 1775 | #define FLASH_5752VENDOR_ST_M45PE10 0x02400000 | |
| 1776 | #define FLASH_5752VENDOR_ST_M45PE20 0x02400002 | |
| 1777 | #define FLASH_5752VENDOR_ST_M45PE40 0x02400001 | |
| 1b27777a MC |
1778 | #define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001 |
| 1779 | #define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002 | |
| 1780 | #define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000 | |
| d3c7b886 | 1781 | #define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003 |
| 70b65a2d | 1782 | #define FLASH_5755VENDOR_ATMEL_FLASH_5 0x02000003 |
| d3c7b886 MC |
1783 | #define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003 |
| 1784 | #define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002 | |
| 1b27777a MC |
1785 | #define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003 |
| 1786 | #define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002 | |
| 1787 | #define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000 | |
| 1788 | #define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000 | |
| 6b91fa02 MC |
1789 | #define FLASH_5761VENDOR_ATMEL_MDB021D 0x00800003 |
| 1790 | #define FLASH_5761VENDOR_ATMEL_MDB041D 0x00800000 | |
| 1791 | #define FLASH_5761VENDOR_ATMEL_MDB081D 0x00800002 | |
| 1792 | #define FLASH_5761VENDOR_ATMEL_MDB161D 0x00800001 | |
| 1793 | #define FLASH_5761VENDOR_ATMEL_ADB021D 0x00000003 | |
| 1794 | #define FLASH_5761VENDOR_ATMEL_ADB041D 0x00000000 | |
| 1795 | #define FLASH_5761VENDOR_ATMEL_ADB081D 0x00000002 | |
| 1796 | #define FLASH_5761VENDOR_ATMEL_ADB161D 0x00000001 | |
| 1797 | #define FLASH_5761VENDOR_ST_M_M45PE20 0x02800001 | |
| 1798 | #define FLASH_5761VENDOR_ST_M_M45PE40 0x02800000 | |
| 1799 | #define FLASH_5761VENDOR_ST_M_M45PE80 0x02800002 | |
| 1800 | #define FLASH_5761VENDOR_ST_M_M45PE16 0x02800003 | |
| 1801 | #define FLASH_5761VENDOR_ST_A_M45PE20 0x02000001 | |
| 1802 | #define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000 | |
| 1803 | #define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002 | |
| 1804 | #define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003 | |
| 321d32a0 MC |
1805 | #define FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000 |
| 1806 | #define FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000 | |
| 1807 | #define FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002 | |
| 1808 | #define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002 | |
| 1809 | #define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001 | |
| 1810 | #define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001 | |
| a1b950d5 MC |
1811 | #define FLASH_5717VENDOR_ATMEL_EEPROM 0x02000001 |
| 1812 | #define FLASH_5717VENDOR_MICRO_EEPROM 0x02000003 | |
| 1813 | #define FLASH_5717VENDOR_ATMEL_MDB011D 0x01000001 | |
| 1814 | #define FLASH_5717VENDOR_ATMEL_MDB021D 0x01000003 | |
| 1815 | #define FLASH_5717VENDOR_ST_M_M25PE10 0x02000000 | |
| 1816 | #define FLASH_5717VENDOR_ST_M_M25PE20 0x02000002 | |
| 1817 | #define FLASH_5717VENDOR_ST_M_M45PE10 0x00000001 | |
| 1818 | #define FLASH_5717VENDOR_ST_M_M45PE20 0x00000003 | |
| 1819 | #define FLASH_5717VENDOR_ATMEL_ADB011B 0x01400000 | |
| 1820 | #define FLASH_5717VENDOR_ATMEL_ADB021B 0x01400002 | |
| 1821 | #define FLASH_5717VENDOR_ATMEL_ADB011D 0x01400001 | |
| 1822 | #define FLASH_5717VENDOR_ATMEL_ADB021D 0x01400003 | |
| 1823 | #define FLASH_5717VENDOR_ST_A_M25PE10 0x02400000 | |
| 1824 | #define FLASH_5717VENDOR_ST_A_M25PE20 0x02400002 | |
| 1825 | #define FLASH_5717VENDOR_ST_A_M45PE10 0x02400001 | |
| 1826 | #define FLASH_5717VENDOR_ST_A_M45PE20 0x02400003 | |
| 1827 | #define FLASH_5717VENDOR_ATMEL_45USPT 0x03400000 | |
| 1828 | #define FLASH_5717VENDOR_ST_25USPT 0x03400002 | |
| 1829 | #define FLASH_5717VENDOR_ST_45USPT 0x03400001 | |
| 361b4ac2 MC |
1830 | #define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000 |
| 1831 | #define FLASH_5752PAGE_SIZE_256 0x00000000 | |
| 1832 | #define FLASH_5752PAGE_SIZE_512 0x10000000 | |
| 1833 | #define FLASH_5752PAGE_SIZE_1K 0x20000000 | |
| 1834 | #define FLASH_5752PAGE_SIZE_2K 0x30000000 | |
| 1835 | #define FLASH_5752PAGE_SIZE_4K 0x40000000 | |
| 1836 | #define FLASH_5752PAGE_SIZE_264 0x50000000 | |
| 321d32a0 | 1837 | #define FLASH_5752PAGE_SIZE_528 0x60000000 |
| 1da177e4 LT |
1838 | #define NVRAM_CFG2 0x00007018 |
| 1839 | #define NVRAM_CFG3 0x0000701c | |
| 1840 | #define NVRAM_SWARB 0x00007020 | |
| 1841 | #define SWARB_REQ_SET0 0x00000001 | |
| 1842 | #define SWARB_REQ_SET1 0x00000002 | |
| 1843 | #define SWARB_REQ_SET2 0x00000004 | |
| 1844 | #define SWARB_REQ_SET3 0x00000008 | |
| 1845 | #define SWARB_REQ_CLR0 0x00000010 | |
| 1846 | #define SWARB_REQ_CLR1 0x00000020 | |
| 1847 | #define SWARB_REQ_CLR2 0x00000040 | |
| 1848 | #define SWARB_REQ_CLR3 0x00000080 | |
| 1849 | #define SWARB_GNT0 0x00000100 | |
| 1850 | #define SWARB_GNT1 0x00000200 | |
| 1851 | #define SWARB_GNT2 0x00000400 | |
| 1852 | #define SWARB_GNT3 0x00000800 | |
| 1853 | #define SWARB_REQ0 0x00001000 | |
| 1854 | #define SWARB_REQ1 0x00002000 | |
| 1855 | #define SWARB_REQ2 0x00004000 | |
| 1856 | #define SWARB_REQ3 0x00008000 | |
| 1857 | #define NVRAM_ACCESS 0x00007024 | |
| 1858 | #define ACCESS_ENABLE 0x00000001 | |
| 1859 | #define ACCESS_WR_ENABLE 0x00000002 | |
| 1860 | #define NVRAM_WRITE1 0x00007028 | |
| 6b91fa02 MC |
1861 | /* 0x702c unused */ |
| 1862 | ||
| 1863 | #define NVRAM_ADDR_LOCKOUT 0x00007030 | |
| b2a5c19c MC |
1864 | /* 0x7034 --> 0x7500 unused */ |
| 1865 | ||
| 1866 | #define OTP_MODE 0x00007500 | |
| 1867 | #define OTP_MODE_OTP_THRU_GRC 0x00000001 | |
| 1868 | #define OTP_CTRL 0x00007504 | |
| 1869 | #define OTP_CTRL_OTP_PROG_ENABLE 0x00200000 | |
| 1870 | #define OTP_CTRL_OTP_CMD_READ 0x00000000 | |
| 1871 | #define OTP_CTRL_OTP_CMD_INIT 0x00000008 | |
| 1872 | #define OTP_CTRL_OTP_CMD_START 0x00000001 | |
| 1873 | #define OTP_STATUS 0x00007508 | |
| 1874 | #define OTP_STATUS_CMD_DONE 0x00000001 | |
| 1875 | #define OTP_ADDRESS 0x0000750c | |
| 1876 | #define OTP_ADDRESS_MAGIC1 0x000000a0 | |
| 1877 | #define OTP_ADDRESS_MAGIC2 0x00000080 | |
| 1878 | /* 0x7510 unused */ | |
| 1879 | ||
| 1880 | #define OTP_READ_DATA 0x00007514 | |
| 1881 | /* 0x7518 --> 0x7c04 unused */ | |
| 1da177e4 | 1882 | |
| b5d3772c MC |
1883 | #define PCIE_TRANSACTION_CFG 0x00007c04 |
| 1884 | #define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000 | |
| 1885 | #define PCIE_TRANS_CFG_LOM 0x00000020 | |
| 521e6b90 | 1886 | /* 0x7c08 --> 0x7d28 unused */ |
| b5d3772c | 1887 | |
| 8ed5d97e MC |
1888 | #define PCIE_PWR_MGMT_THRESH 0x00007d28 |
| 1889 | #define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 | |
| 33466d93 MC |
1890 | #define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00 |
| 1891 | #define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000 | |
| 255ca311 MC |
1892 | /* 0x7d2c --> 0x7d54 unused */ |
| 1893 | ||
| 1894 | #define TG3_PCIE_LNKCTL 0x00007d54 | |
| 1895 | #define TG3_PCIE_LNKCTL_L1_PLL_PD_EN 0x00000008 | |
| 1896 | #define TG3_PCIE_LNKCTL_L1_PLL_PD_DIS 0x00000080 | |
| 1897 | /* 0x7d58 --> 0x7e70 unused */ | |
| 521e6b90 | 1898 | |
| 88075d91 MC |
1899 | #define TG3_PCIE_PHY_TSTCTL 0x00007e2c |
| 1900 | #define TG3_PCIE_PHY_TSTCTL_PCIE10 0x00000040 | |
| 1901 | #define TG3_PCIE_PHY_TSTCTL_PSCRAM 0x00000020 | |
| 1902 | ||
| 521e6b90 MC |
1903 | #define TG3_PCIE_EIDLE_DELAY 0x00007e70 |
| 1904 | #define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f | |
| 1905 | #define TG3_PCIE_EIDLE_DELAY_13_CLKS 0x0000000c | |
| 1906 | /* 0x7e74 --> 0x8000 unused */ | |
| 1da177e4 | 1907 | |
| b2a5c19c | 1908 | |
| 614b0590 MC |
1909 | /* Alternate PCIE definitions */ |
| 1910 | #define TG3_PCIE_TLDLPL_PORT 0x00007c00 | |
| 1911 | #define TG3_PCIE_PL_LO_PHYCTL1 0x00000004 | |
| 1912 | #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000 | |
| cea46462 MC |
1913 | #define TG3_PCIE_PL_LO_PHYCTL5 0x00000014 |
| 1914 | #define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000 | |
| 614b0590 | 1915 | |
| b2a5c19c MC |
1916 | /* OTP bit definitions */ |
| 1917 | #define TG3_OTP_AGCTGT_MASK 0x000000e0 | |
| 1918 | #define TG3_OTP_AGCTGT_SHIFT 1 | |
| 1919 | #define TG3_OTP_HPFFLTR_MASK 0x00000300 | |
| 1920 | #define TG3_OTP_HPFFLTR_SHIFT 1 | |
| 1921 | #define TG3_OTP_HPFOVER_MASK 0x00000400 | |
| 1922 | #define TG3_OTP_HPFOVER_SHIFT 1 | |
| 1923 | #define TG3_OTP_LPFDIS_MASK 0x00000800 | |
| 1924 | #define TG3_OTP_LPFDIS_SHIFT 11 | |
| 1925 | #define TG3_OTP_VDAC_MASK 0xff000000 | |
| 1926 | #define TG3_OTP_VDAC_SHIFT 24 | |
| 1927 | #define TG3_OTP_10BTAMP_MASK 0x0000f000 | |
| 1928 | #define TG3_OTP_10BTAMP_SHIFT 8 | |
| 1929 | #define TG3_OTP_ROFF_MASK 0x00e00000 | |
| 1930 | #define TG3_OTP_ROFF_SHIFT 11 | |
| 1931 | #define TG3_OTP_RCOFF_MASK 0x001c0000 | |
| 1932 | #define TG3_OTP_RCOFF_SHIFT 16 | |
| 1933 | ||
| 1934 | #define TG3_OTP_DEFAULT 0x286c1640 | |
| 1935 | ||
| 141518c9 MC |
1936 | |
| 1937 | /* Hardware Legacy NVRAM layout */ | |
| 1938 | #define TG3_NVM_VPD_OFF 0x100 | |
| 1939 | #define TG3_NVM_VPD_LEN 256 | |
| 1940 | ||
| a6f6cb1c MC |
1941 | /* Hardware Selfboot NVRAM layout */ |
| 1942 | #define TG3_NVM_HWSB_CFG1 0x00000004 | |
| 1943 | #define TG3_NVM_HWSB_CFG1_MAJMSK 0xf8000000 | |
| 1944 | #define TG3_NVM_HWSB_CFG1_MAJSFT 27 | |
| 1945 | #define TG3_NVM_HWSB_CFG1_MINMSK 0x07c00000 | |
| 1946 | #define TG3_NVM_HWSB_CFG1_MINSFT 22 | |
| b2a5c19c | 1947 | |
| 1da177e4 | 1948 | #define TG3_EEPROM_MAGIC 0x669955aa |
| b16250e3 MC |
1949 | #define TG3_EEPROM_MAGIC_FW 0xa5000000 |
| 1950 | #define TG3_EEPROM_MAGIC_FW_MSK 0xff000000 | |
| a5767dec MC |
1951 | #define TG3_EEPROM_SB_FORMAT_MASK 0x00e00000 |
| 1952 | #define TG3_EEPROM_SB_FORMAT_1 0x00200000 | |
| 1953 | #define TG3_EEPROM_SB_REVISION_MASK 0x001f0000 | |
| 1954 | #define TG3_EEPROM_SB_REVISION_0 0x00000000 | |
| 1955 | #define TG3_EEPROM_SB_REVISION_2 0x00020000 | |
| 1956 | #define TG3_EEPROM_SB_REVISION_3 0x00030000 | |
| a4153d40 MC |
1957 | #define TG3_EEPROM_SB_REVISION_4 0x00040000 |
| 1958 | #define TG3_EEPROM_SB_REVISION_5 0x00050000 | |
| bba226ac | 1959 | #define TG3_EEPROM_SB_REVISION_6 0x00060000 |
| b16250e3 MC |
1960 | #define TG3_EEPROM_MAGIC_HW 0xabcd |
| 1961 | #define TG3_EEPROM_MAGIC_HW_MSK 0xffff | |
| 1da177e4 | 1962 | |
| 9c8a620e MC |
1963 | #define TG3_NVM_DIR_START 0x18 |
| 1964 | #define TG3_NVM_DIR_END 0x78 | |
| 1965 | #define TG3_NVM_DIRENT_SIZE 0xc | |
| 1966 | #define TG3_NVM_DIRTYPE_SHIFT 24 | |
| 1967 | #define TG3_NVM_DIRTYPE_ASFINI 1 | |
| ff3a7cb2 MC |
1968 | #define TG3_NVM_PTREV_BCVER 0x94 |
| 1969 | #define TG3_NVM_BCVER_MAJMSK 0x0000ff00 | |
| 1970 | #define TG3_NVM_BCVER_MAJSFT 8 | |
| 1971 | #define TG3_NVM_BCVER_MINMSK 0x000000ff | |
| 9c8a620e | 1972 | |
| dfe00d7d MC |
1973 | #define TG3_EEPROM_SB_F1R0_EDH_OFF 0x10 |
| 1974 | #define TG3_EEPROM_SB_F1R2_EDH_OFF 0x14 | |
| 1975 | #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10 | |
| 1976 | #define TG3_EEPROM_SB_F1R3_EDH_OFF 0x18 | |
| a4153d40 MC |
1977 | #define TG3_EEPROM_SB_F1R4_EDH_OFF 0x1c |
| 1978 | #define TG3_EEPROM_SB_F1R5_EDH_OFF 0x20 | |
| bba226ac | 1979 | #define TG3_EEPROM_SB_F1R6_EDH_OFF 0x4c |
| dfe00d7d MC |
1980 | #define TG3_EEPROM_SB_EDH_MAJ_MASK 0x00000700 |
| 1981 | #define TG3_EEPROM_SB_EDH_MAJ_SHFT 8 | |
| 1982 | #define TG3_EEPROM_SB_EDH_MIN_MASK 0x000000ff | |
| 1983 | #define TG3_EEPROM_SB_EDH_BLD_MASK 0x0000f800 | |
| 1984 | #define TG3_EEPROM_SB_EDH_BLD_SHFT 11 | |
| 1985 | ||
| 1986 | ||
| 1da177e4 LT |
1987 | /* 32K Window into NIC internal memory */ |
| 1988 | #define NIC_SRAM_WIN_BASE 0x00008000 | |
| 1989 | ||
| 1990 | /* Offsets into first 32k of NIC internal memory. */ | |
| 1991 | #define NIC_SRAM_PAGE_ZERO 0x00000000 | |
| 1992 | #define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */ | |
| 1993 | #define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */ | |
| 1994 | #define NIC_SRAM_STATS_BLK 0x00000300 | |
| 1995 | #define NIC_SRAM_STATUS_BLK 0x00000b00 | |
| 1996 | ||
| 1997 | #define NIC_SRAM_FIRMWARE_MBOX 0x00000b50 | |
| 1998 | #define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654 | |
| 1999 | #define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */ | |
| 2000 | ||
| 2001 | #define NIC_SRAM_DATA_SIG 0x00000b54 | |
| 2002 | #define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */ | |
| 2003 | ||
| 2004 | #define NIC_SRAM_DATA_CFG 0x00000b58 | |
| 2005 | #define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c | |
| 2006 | #define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000 | |
| 2007 | #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004 | |
| 2008 | #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008 | |
| 2009 | #define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030 | |
| 2010 | #define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000 | |
| 2011 | #define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010 | |
| 2012 | #define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020 | |
| 2013 | #define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040 | |
| 2014 | #define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080 | |
| 2015 | #define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100 | |
| 2016 | #define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000 | |
| 2017 | #define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000 | |
| 2018 | #define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000 | |
| 0d3031d9 | 2019 | #define NIC_SRAM_DATA_CFG_APE_ENABLE 0x00200000 |
| 1da177e4 LT |
2020 | |
| 2021 | #define NIC_SRAM_DATA_VER 0x00000b5c | |
| 2022 | #define NIC_SRAM_DATA_VER_SHIFT 16 | |
| 2023 | ||
| 2024 | #define NIC_SRAM_DATA_PHY_ID 0x00000b74 | |
| 2025 | #define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000 | |
| 2026 | #define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff | |
| 2027 | ||
| 2028 | #define NIC_SRAM_FW_CMD_MBOX 0x00000b78 | |
| 2029 | #define FWCMD_NICDRV_ALIVE 0x00000001 | |
| 2030 | #define FWCMD_NICDRV_PAUSE_FW 0x00000002 | |
| 2031 | #define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003 | |
| 2032 | #define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004 | |
| 2033 | #define FWCMD_NICDRV_FIX_DMAR 0x00000005 | |
| 2034 | #define FWCMD_NICDRV_FIX_DMAW 0x00000006 | |
| 7c5026aa | 2035 | #define FWCMD_NICDRV_LINK_UPDATE 0x0000000c |
| 28fbef78 | 2036 | #define FWCMD_NICDRV_ALIVE2 0x0000000d |
| 130b8e4d | 2037 | #define FWCMD_NICDRV_ALIVE3 0x0000000e |
| 1da177e4 LT |
2038 | #define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c |
| 2039 | #define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80 | |
| 2040 | #define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00 | |
| 2041 | #define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04 | |
| 2042 | #define DRV_STATE_START 0x00000001 | |
| 2043 | #define DRV_STATE_START_DONE 0x80000001 | |
| 2044 | #define DRV_STATE_UNLOAD 0x00000002 | |
| 2045 | #define DRV_STATE_UNLOAD_DONE 0x80000002 | |
| 2046 | #define DRV_STATE_WOL 0x00000003 | |
| 2047 | #define DRV_STATE_SUSPEND 0x00000004 | |
| 2048 | ||
| 2049 | #define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08 | |
| 2050 | ||
| 2051 | #define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14 | |
| 2052 | #define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18 | |
| 2053 | ||
| 6921d201 MC |
2054 | #define NIC_SRAM_WOL_MBOX 0x00000d30 |
| 2055 | #define WOL_SIGNATURE 0x474c0000 | |
| 2056 | #define WOL_DRV_STATE_SHUTDOWN 0x00000001 | |
| 2057 | #define WOL_DRV_WOL 0x00000002 | |
| 2058 | #define WOL_SET_MAGIC_PKT 0x00000004 | |
| 2059 | ||
| 1da177e4 LT |
2060 | #define NIC_SRAM_DATA_CFG_2 0x00000d38 |
| 2061 | ||
| 6833c043 | 2062 | #define NIC_SRAM_DATA_CFG_2_APD_EN 0x00000400 |
| 1da177e4 LT |
2063 | #define SHASTA_EXT_LED_MODE_MASK 0x00018000 |
| 2064 | #define SHASTA_EXT_LED_LEGACY 0x00000000 | |
| 2065 | #define SHASTA_EXT_LED_SHARED 0x00008000 | |
| 2066 | #define SHASTA_EXT_LED_MAC 0x00010000 | |
| 2067 | #define SHASTA_EXT_LED_COMBO 0x00018000 | |
| 2068 | ||
| 8ed5d97e MC |
2069 | #define NIC_SRAM_DATA_CFG_3 0x00000d3c |
| 2070 | #define NIC_SRAM_ASPM_DEBOUNCE 0x00000002 | |
| 2071 | ||
| a9daf367 MC |
2072 | #define NIC_SRAM_DATA_CFG_4 0x00000d60 |
| 2073 | #define NIC_SRAM_GMII_MODE 0x00000002 | |
| 14417063 | 2074 | #define NIC_SRAM_RGMII_INBAND_DISABLE 0x00000004 |
| a9daf367 MC |
2075 | #define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008 |
| 2076 | #define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010 | |
| 2077 | ||
| 1da177e4 LT |
2078 | #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 |
| 2079 | ||
| 2080 | #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 | |
| 2081 | #define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000 | |
| 2082 | #define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */ | |
| 2083 | #define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */ | |
| 2084 | #define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */ | |
| 2085 | #define NIC_SRAM_MBUF_POOL_BASE 0x00008000 | |
| 2086 | #define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000 | |
| 2087 | #define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000 | |
| 2088 | #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000 | |
| 2089 | #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000 | |
| 2090 | ||
| 52cdf852 | 2091 | |
| 1da177e4 | 2092 | /* Currently this is fixed. */ |
| 3f0e3ad7 | 2093 | #define TG3_PHY_MII_ADDR 0x01 |
| 1da177e4 | 2094 | |
| 52cdf852 | 2095 | |
| 52cdf852 | 2096 | /*** Tigon3 specific PHY MII registers. ***/ |
| 1da177e4 LT |
2097 | #define TG3_BMCR_SPEED1000 0x0040 |
| 2098 | ||
| 2099 | #define MII_TG3_CTRL 0x09 /* 1000-baseT control register */ | |
| 2100 | #define MII_TG3_CTRL_ADV_1000_HALF 0x0100 | |
| 2101 | #define MII_TG3_CTRL_ADV_1000_FULL 0x0200 | |
| 2102 | #define MII_TG3_CTRL_AS_MASTER 0x0800 | |
| 2103 | #define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000 | |
| 2104 | ||
| ddfc87bf MC |
2105 | #define MII_TG3_MMD_CTRL 0x0d /* MMD Access Control register */ |
| 2106 | #define MII_TG3_MMD_CTRL_DATA_NOINC 0x4000 | |
| 2107 | #define MII_TG3_MMD_ADDRESS 0x0e /* MMD Address Data register */ | |
| 2108 | ||
| 1da177e4 LT |
2109 | #define MII_TG3_EXT_CTRL 0x10 /* Extended control register */ |
| 2110 | #define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001 | |
| 2111 | #define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002 | |
| 6921d201 | 2112 | #define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008 |
| 1da177e4 LT |
2113 | #define MII_TG3_EXT_CTRL_TBI 0x8000 |
| 2114 | ||
| 2115 | #define MII_TG3_EXT_STAT 0x11 /* Extended status register */ | |
| 2116 | #define MII_TG3_EXT_STAT_LPASS 0x0100 | |
| 2117 | ||
| f08aa1a8 | 2118 | #define MII_TG3_RXR_COUNTERS 0x14 /* Local/Remote Receiver Counts */ |
| 1da177e4 | 2119 | #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */ |
| f08aa1a8 | 2120 | #define MII_TG3_DSP_CONTROL 0x16 /* DSP control register */ |
| b2a5c19c MC |
2121 | #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */ |
| 2122 | ||
| 2123 | #define MII_TG3_DSP_TAP1 0x0001 | |
| 2124 | #define MII_TG3_DSP_TAP1_AGCTGT_DFLT 0x0007 | |
| 21a00ab2 MC |
2125 | #define MII_TG3_DSP_TAP26 0x001a |
| 2126 | #define MII_TG3_DSP_TAP26_ALNOKO 0x0001 | |
| 2127 | #define MII_TG3_DSP_TAP26_RMRXSTO 0x0002 | |
| 2128 | #define MII_TG3_DSP_TAP26_OPCSINPT 0x0004 | |
| b2a5c19c | 2129 | #define MII_TG3_DSP_AADJ1CH0 0x001f |
| 52b02d04 MC |
2130 | #define MII_TG3_DSP_CH34TP2 0x4022 |
| 2131 | #define MII_TG3_DSP_CH34TP2_HIBW01 0x0010 | |
| b2a5c19c MC |
2132 | #define MII_TG3_DSP_AADJ1CH3 0x601f |
| 2133 | #define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002 | |
| f08aa1a8 | 2134 | #define MII_TG3_DSP_EXP1_INT_STAT 0x0f01 |
| c1f614a1 | 2135 | #define MII_TG3_DSP_EXP8 0x0f08 |
| b2a5c19c MC |
2136 | #define MII_TG3_DSP_EXP8_REJ2MHz 0x0001 |
| 2137 | #define MII_TG3_DSP_EXP8_AEDW 0x0200 | |
| 2138 | #define MII_TG3_DSP_EXP75 0x0f75 | |
| 2139 | #define MII_TG3_DSP_EXP96 0x0f96 | |
| 2140 | #define MII_TG3_DSP_EXP97 0x0f97 | |
| 1da177e4 LT |
2141 | |
| 2142 | #define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */ | |
| 2143 | ||
| 0a459aac MC |
2144 | #define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010 |
| 2145 | #define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020 | |
| 2146 | #define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180 | |
| 2147 | #define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002 | |
| 2148 | ||
| 9ef8ca99 MC |
2149 | #define MII_TG3_AUXCTL_MISC_WREN 0x8000 |
| 2150 | #define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200 | |
| 2151 | #define MII_TG3_AUXCTL_MISC_RDSEL_MISC 0x7000 | |
| b2a5c19c MC |
2152 | #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007 |
| 2153 | ||
| 2154 | #define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800 | |
| 2155 | #define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400 | |
| 2156 | #define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000 | |
| 9ef8ca99 | 2157 | |
| 1da177e4 LT |
2158 | #define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */ |
| 2159 | #define MII_TG3_AUX_STAT_LPASS 0x0004 | |
| 2160 | #define MII_TG3_AUX_STAT_SPDMASK 0x0700 | |
| 2161 | #define MII_TG3_AUX_STAT_10HALF 0x0100 | |
| 2162 | #define MII_TG3_AUX_STAT_10FULL 0x0200 | |
| 2163 | #define MII_TG3_AUX_STAT_100HALF 0x0300 | |
| 2164 | #define MII_TG3_AUX_STAT_100_4 0x0400 | |
| 2165 | #define MII_TG3_AUX_STAT_100FULL 0x0500 | |
| 2166 | #define MII_TG3_AUX_STAT_1000HALF 0x0600 | |
| 2167 | #define MII_TG3_AUX_STAT_1000FULL 0x0700 | |
| 715116a1 MC |
2168 | #define MII_TG3_AUX_STAT_100 0x0008 |
| 2169 | #define MII_TG3_AUX_STAT_FULL 0x0001 | |
| 1da177e4 LT |
2170 | |
| 2171 | #define MII_TG3_ISTAT 0x1a /* IRQ status register */ | |
| 2172 | #define MII_TG3_IMASK 0x1b /* IRQ mask register */ | |
| 2173 | ||
| 2174 | /* ISTAT/IMASK event bits */ | |
| 2175 | #define MII_TG3_INT_LINKCHG 0x0002 | |
| 2176 | #define MII_TG3_INT_SPEEDCHG 0x0004 | |
| 2177 | #define MII_TG3_INT_DUPLEXCHG 0x0008 | |
| 2178 | #define MII_TG3_INT_ANEG_PAGE_RX 0x0400 | |
| 2179 | ||
| b2a5c19c MC |
2180 | #define MII_TG3_MISC_SHDW 0x1c |
| 2181 | #define MII_TG3_MISC_SHDW_WREN 0x8000 | |
| aa10f27d MC |
2182 | |
| 2183 | #define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001 | |
| 2184 | #define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020 | |
| b2a5c19c MC |
2185 | #define MII_TG3_MISC_SHDW_APD_SEL 0x2800 |
| 2186 | ||
| 2187 | #define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001 | |
| 2188 | #define MII_TG3_MISC_SHDW_SCR5_DLLAPD 0x0002 | |
| 2189 | #define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004 | |
| 2190 | #define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008 | |
| 2191 | #define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010 | |
| aa10f27d | 2192 | #define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400 |
| b2a5c19c | 2193 | |
| c1d2a196 MC |
2194 | #define MII_TG3_TEST1 0x1e |
| 2195 | #define MII_TG3_TEST1_TRIM_EN 0x0010 | |
| 569a5df8 | 2196 | #define MII_TG3_TEST1_CRC_EN 0x8000 |
| c1d2a196 | 2197 | |
| 52b02d04 | 2198 | /* Clause 45 expansion registers */ |
| 52b02d04 MC |
2199 | #define TG3_CL45_D7_EEERES_STAT 0x803e |
| 2200 | #define TG3_CL45_D7_EEERES_STAT_LP_100TX 0x0002 | |
| 2201 | #define TG3_CL45_D7_EEERES_STAT_LP_1000T 0x0004 | |
| 2202 | ||
| 535ef6e1 MC |
2203 | |
| 2204 | /* Fast Ethernet Tranceiver definitions */ | |
| 2205 | #define MII_TG3_FET_PTEST 0x17 | |
| 1061b7c5 MC |
2206 | #define MII_TG3_FET_PTEST_FRC_TX_LINK 0x1000 |
| 2207 | #define MII_TG3_FET_PTEST_FRC_TX_LOCK 0x0800 | |
| 2208 | ||
| 535ef6e1 MC |
2209 | #define MII_TG3_FET_TEST 0x1f |
| 2210 | #define MII_TG3_FET_SHADOW_EN 0x0080 | |
| 2211 | ||
| 2212 | #define MII_TG3_FET_SHDW_MISCCTRL 0x10 | |
| 2213 | #define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000 | |
| 2214 | ||
| 0e5f784c MC |
2215 | #define MII_TG3_FET_SHDW_AUXMODE4 0x1a |
| 2216 | #define MII_TG3_FET_SHDW_AUXMODE4_SBPD 0x0008 | |
| 2217 | ||
| 535ef6e1 MC |
2218 | #define MII_TG3_FET_SHDW_AUXSTAT2 0x1b |
| 2219 | #define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020 | |
| 2220 | ||
| 2221 | ||
| 0d3031d9 MC |
2222 | /* APE registers. Accessible through BAR1 */ |
| 2223 | #define TG3_APE_EVENT 0x000c | |
| 2224 | #define APE_EVENT_1 0x00000001 | |
| 2225 | #define TG3_APE_LOCK_REQ 0x002c | |
| 2226 | #define APE_LOCK_REQ_DRIVER 0x00001000 | |
| 2227 | #define TG3_APE_LOCK_GRANT 0x004c | |
| 2228 | #define APE_LOCK_GRANT_DRIVER 0x00001000 | |
| 2229 | #define TG3_APE_SEG_SIG 0x4000 | |
| 2230 | #define APE_SEG_SIG_MAGIC 0x41504521 | |
| 2231 | ||
| 2232 | /* APE shared memory. Accessible through BAR1 */ | |
| 2233 | #define TG3_APE_FW_STATUS 0x400c | |
| 2234 | #define APE_FW_STATUS_READY 0x00000100 | |
| ecc79648 MC |
2235 | #define TG3_APE_FW_FEATURES 0x4010 |
| 2236 | #define TG3_APE_FW_FEATURE_NCSI 0x00000002 | |
| 7fd76445 MC |
2237 | #define TG3_APE_FW_VERSION 0x4018 |
| 2238 | #define APE_FW_VERSION_MAJMSK 0xff000000 | |
| 2239 | #define APE_FW_VERSION_MAJSFT 24 | |
| 2240 | #define APE_FW_VERSION_MINMSK 0x00ff0000 | |
| 2241 | #define APE_FW_VERSION_MINSFT 16 | |
| 2242 | #define APE_FW_VERSION_REVMSK 0x0000ff00 | |
| 2243 | #define APE_FW_VERSION_REVSFT 8 | |
| 2244 | #define APE_FW_VERSION_BLDMSK 0x000000ff | |
| 0d3031d9 MC |
2245 | #define TG3_APE_HOST_SEG_SIG 0x4200 |
| 2246 | #define APE_HOST_SEG_SIG_MAGIC 0x484f5354 | |
| 2247 | #define TG3_APE_HOST_SEG_LEN 0x4204 | |
| dc6d0744 | 2248 | #define APE_HOST_SEG_LEN_MAGIC 0x00000020 |
| 0d3031d9 MC |
2249 | #define TG3_APE_HOST_INIT_COUNT 0x4208 |
| 2250 | #define TG3_APE_HOST_DRIVER_ID 0x420c | |
| 6867c843 MC |
2251 | #define APE_HOST_DRIVER_ID_LINUX 0xf0000000 |
| 2252 | #define APE_HOST_DRIVER_ID_MAGIC(maj, min) \ | |
| 2253 | (APE_HOST_DRIVER_ID_LINUX | (maj & 0xff) << 16 | (min & 0xff) << 8) | |
| 0d3031d9 MC |
2254 | #define TG3_APE_HOST_BEHAVIOR 0x4210 |
| 2255 | #define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001 | |
| 2256 | #define TG3_APE_HOST_HEARTBEAT_INT_MS 0x4214 | |
| 2257 | #define APE_HOST_HEARTBEAT_INT_DISABLE 0 | |
| 2258 | #define APE_HOST_HEARTBEAT_INT_5SEC 5000 | |
| 2259 | #define TG3_APE_HOST_HEARTBEAT_COUNT 0x4218 | |
| dc6d0744 MC |
2260 | #define TG3_APE_HOST_DRVR_STATE 0x421c |
| 2261 | #define TG3_APE_HOST_DRVR_STATE_START 0x00000001 | |
| 2262 | #define TG3_APE_HOST_DRVR_STATE_UNLOAD 0x00000002 | |
| 2263 | #define TG3_APE_HOST_DRVR_STATE_WOL 0x00000003 | |
| 2264 | #define TG3_APE_HOST_WOL_SPEED 0x4224 | |
| 2265 | #define TG3_APE_HOST_WOL_SPEED_AUTO 0x00008000 | |
| 0d3031d9 MC |
2266 | |
| 2267 | #define TG3_APE_EVENT_STATUS 0x4300 | |
| 2268 | ||
| 2269 | #define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010 | |
| 2270 | #define APE_EVENT_STATUS_STATE_CHNGE 0x00000500 | |
| 2271 | #define APE_EVENT_STATUS_STATE_START 0x00010000 | |
| 2272 | #define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000 | |
| 2273 | #define APE_EVENT_STATUS_STATE_WOL 0x00030000 | |
| 2274 | #define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000 | |
| 2275 | #define APE_EVENT_STATUS_EVENT_PENDING 0x80000000 | |
| 2276 | ||
| f92d9dc1 MC |
2277 | #define TG3_APE_PER_LOCK_REQ 0x8400 |
| 2278 | #define APE_LOCK_PER_REQ_DRIVER 0x00001000 | |
| 2279 | #define TG3_APE_PER_LOCK_GRANT 0x8420 | |
| 2280 | #define APE_PER_LOCK_GRANT_DRIVER 0x00001000 | |
| 2281 | ||
| 0d3031d9 | 2282 | /* APE convenience enumerations. */ |
| 77b483f1 | 2283 | #define TG3_APE_LOCK_GRC 1 |
| 0d3031d9 MC |
2284 | #define TG3_APE_LOCK_MEM 4 |
| 2285 | ||
| a5767dec MC |
2286 | #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10 |
| 2287 | ||
| 0d3031d9 | 2288 | |
| 1da177e4 LT |
2289 | /* There are two ways to manage the TX descriptors on the tigon3. |
| 2290 | * Either the descriptors are in host DMA'able memory, or they | |
| 2291 | * exist only in the cards on-chip SRAM. All 16 send bds are under | |
| 2292 | * the same mode, they may not be configured individually. | |
| 2293 | * | |
| 2294 | * This driver always uses host memory TX descriptors. | |
| 2295 | * | |
| 2296 | * To use host memory TX descriptors: | |
| 2297 | * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register. | |
| 2298 | * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear. | |
| 2299 | * 2) Allocate DMA'able memory. | |
| 2300 | * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: | |
| 2301 | * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory | |
| 2302 | * obtained in step 2 | |
| 2303 | * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC. | |
| 2304 | * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number | |
| 2305 | * of TX descriptors. Leave flags field clear. | |
| 2306 | * 4) Access TX descriptors via host memory. The chip | |
| 2307 | * will refetch into local SRAM as needed when producer | |
| 2308 | * index mailboxes are updated. | |
| 2309 | * | |
| 2310 | * To use on-chip TX descriptors: | |
| 2311 | * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register. | |
| 2312 | * Make sure GRC_MODE_HOST_SENDBDS is clear. | |
| 2313 | * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: | |
| 2314 | * a) Set TG3_BDINFO_HOST_ADDR to zero. | |
| 2315 | * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC | |
| 2316 | * c) TG3_BDINFO_MAXLEN_FLAGS is don't care. | |
| 2317 | * 3) Access TX descriptors directly in on-chip SRAM | |
| 2318 | * using normal {read,write}l(). (and not using | |
| 2319 | * pointer dereferencing of ioremap()'d memory like | |
| 2320 | * the broken Broadcom driver does) | |
| 2321 | * | |
| 2322 | * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of | |
| 2323 | * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices. | |
| 2324 | */ | |
| 2325 | struct tg3_tx_buffer_desc { | |
| 2326 | u32 addr_hi; | |
| 2327 | u32 addr_lo; | |
| 2328 | ||
| 2329 | u32 len_flags; | |
| 2330 | #define TXD_FLAG_TCPUDP_CSUM 0x0001 | |
| 2331 | #define TXD_FLAG_IP_CSUM 0x0002 | |
| 2332 | #define TXD_FLAG_END 0x0004 | |
| 2333 | #define TXD_FLAG_IP_FRAG 0x0008 | |
| f6eb9b1f | 2334 | #define TXD_FLAG_JMB_PKT 0x0008 |
| 1da177e4 LT |
2335 | #define TXD_FLAG_IP_FRAG_END 0x0010 |
| 2336 | #define TXD_FLAG_VLAN 0x0040 | |
| 2337 | #define TXD_FLAG_COAL_NOW 0x0080 | |
| 2338 | #define TXD_FLAG_CPU_PRE_DMA 0x0100 | |
| 2339 | #define TXD_FLAG_CPU_POST_DMA 0x0200 | |
| 2340 | #define TXD_FLAG_ADD_SRC_ADDR 0x1000 | |
| 2341 | #define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000 | |
| 2342 | #define TXD_FLAG_NO_CRC 0x8000 | |
| 2343 | #define TXD_LEN_SHIFT 16 | |
| 2344 | ||
| 2345 | u32 vlan_tag; | |
| 2346 | #define TXD_VLAN_TAG_SHIFT 0 | |
| 2347 | #define TXD_MSS_SHIFT 16 | |
| 2348 | }; | |
| 2349 | ||
| 2350 | #define TXD_ADDR 0x00UL /* 64-bit */ | |
| 2351 | #define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */ | |
| 2352 | #define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */ | |
| 2353 | #define TXD_SIZE 0x10UL | |
| 2354 | ||
| 2355 | struct tg3_rx_buffer_desc { | |
| 2356 | u32 addr_hi; | |
| 2357 | u32 addr_lo; | |
| 2358 | ||
| 2359 | u32 idx_len; | |
| 2360 | #define RXD_IDX_MASK 0xffff0000 | |
| 2361 | #define RXD_IDX_SHIFT 16 | |
| 2362 | #define RXD_LEN_MASK 0x0000ffff | |
| 2363 | #define RXD_LEN_SHIFT 0 | |
| 2364 | ||
| 2365 | u32 type_flags; | |
| 2366 | #define RXD_TYPE_SHIFT 16 | |
| 2367 | #define RXD_FLAGS_SHIFT 0 | |
| 2368 | ||
| 2369 | #define RXD_FLAG_END 0x0004 | |
| 2370 | #define RXD_FLAG_MINI 0x0800 | |
| 2371 | #define RXD_FLAG_JUMBO 0x0020 | |
| 2372 | #define RXD_FLAG_VLAN 0x0040 | |
| 2373 | #define RXD_FLAG_ERROR 0x0400 | |
| 2374 | #define RXD_FLAG_IP_CSUM 0x1000 | |
| 2375 | #define RXD_FLAG_TCPUDP_CSUM 0x2000 | |
| 2376 | #define RXD_FLAG_IS_TCP 0x4000 | |
| 2377 | ||
| 2378 | u32 ip_tcp_csum; | |
| 2379 | #define RXD_IPCSUM_MASK 0xffff0000 | |
| 2380 | #define RXD_IPCSUM_SHIFT 16 | |
| 2381 | #define RXD_TCPCSUM_MASK 0x0000ffff | |
| 2382 | #define RXD_TCPCSUM_SHIFT 0 | |
| 2383 | ||
| 2384 | u32 err_vlan; | |
| 2385 | ||
| 2386 | #define RXD_VLAN_MASK 0x0000ffff | |
| 2387 | ||
| 2388 | #define RXD_ERR_BAD_CRC 0x00010000 | |
| 2389 | #define RXD_ERR_COLLISION 0x00020000 | |
| 2390 | #define RXD_ERR_LINK_LOST 0x00040000 | |
| 2391 | #define RXD_ERR_PHY_DECODE 0x00080000 | |
| 2392 | #define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000 | |
| 2393 | #define RXD_ERR_MAC_ABRT 0x00200000 | |
| 2394 | #define RXD_ERR_TOO_SMALL 0x00400000 | |
| 2395 | #define RXD_ERR_NO_RESOURCES 0x00800000 | |
| 2396 | #define RXD_ERR_HUGE_FRAME 0x01000000 | |
| 2397 | #define RXD_ERR_MASK 0xffff0000 | |
| 2398 | ||
| 2399 | u32 reserved; | |
| 2400 | u32 opaque; | |
| 2401 | #define RXD_OPAQUE_INDEX_MASK 0x0000ffff | |
| 2402 | #define RXD_OPAQUE_INDEX_SHIFT 0 | |
| 2403 | #define RXD_OPAQUE_RING_STD 0x00010000 | |
| 2404 | #define RXD_OPAQUE_RING_JUMBO 0x00020000 | |
| 2405 | #define RXD_OPAQUE_RING_MINI 0x00040000 | |
| 2406 | #define RXD_OPAQUE_RING_MASK 0x00070000 | |
| 2407 | }; | |
| 2408 | ||
| 2409 | struct tg3_ext_rx_buffer_desc { | |
| 2410 | struct { | |
| 2411 | u32 addr_hi; | |
| 2412 | u32 addr_lo; | |
| 2413 | } addrlist[3]; | |
| 2414 | u32 len2_len1; | |
| 2415 | u32 resv_len3; | |
| 2416 | struct tg3_rx_buffer_desc std; | |
| 2417 | }; | |
| 2418 | ||
| 2419 | /* We only use this when testing out the DMA engine | |
| 2420 | * at probe time. This is the internal format of buffer | |
| 2421 | * descriptors used by the chip at NIC_SRAM_DMA_DESCS. | |
| 2422 | */ | |
| 2423 | struct tg3_internal_buffer_desc { | |
| 2424 | u32 addr_hi; | |
| 2425 | u32 addr_lo; | |
| 2426 | u32 nic_mbuf; | |
| 2427 | /* XXX FIX THIS */ | |
| 2428 | #ifdef __BIG_ENDIAN | |
| 2429 | u16 cqid_sqid; | |
| 2430 | u16 len; | |
| 2431 | #else | |
| 2432 | u16 len; | |
| 2433 | u16 cqid_sqid; | |
| 2434 | #endif | |
| 2435 | u32 flags; | |
| 2436 | u32 __cookie1; | |
| 2437 | u32 __cookie2; | |
| 2438 | u32 __cookie3; | |
| 2439 | }; | |
| 2440 | ||
| 2441 | #define TG3_HW_STATUS_SIZE 0x50 | |
| 2442 | struct tg3_hw_status { | |
| 2443 | u32 status; | |
| 2444 | #define SD_STATUS_UPDATED 0x00000001 | |
| 2445 | #define SD_STATUS_LINK_CHG 0x00000002 | |
| 2446 | #define SD_STATUS_ERROR 0x00000004 | |
| 2447 | ||
| 2448 | u32 status_tag; | |
| 2449 | ||
| 2450 | #ifdef __BIG_ENDIAN | |
| 2451 | u16 rx_consumer; | |
| 2452 | u16 rx_jumbo_consumer; | |
| 2453 | #else | |
| 2454 | u16 rx_jumbo_consumer; | |
| 2455 | u16 rx_consumer; | |
| 2456 | #endif | |
| 2457 | ||
| 2458 | #ifdef __BIG_ENDIAN | |
| 2459 | u16 reserved; | |
| 2460 | u16 rx_mini_consumer; | |
| 2461 | #else | |
| 2462 | u16 rx_mini_consumer; | |
| 2463 | u16 reserved; | |
| 2464 | #endif | |
| 2465 | struct { | |
| 2466 | #ifdef __BIG_ENDIAN | |
| 2467 | u16 tx_consumer; | |
| 2468 | u16 rx_producer; | |
| 2469 | #else | |
| 2470 | u16 rx_producer; | |
| 2471 | u16 tx_consumer; | |
| 2472 | #endif | |
| 2473 | } idx[16]; | |
| 2474 | }; | |
| 2475 | ||
| 2476 | typedef struct { | |
| 2477 | u32 high, low; | |
| 2478 | } tg3_stat64_t; | |
| 2479 | ||
| 2480 | struct tg3_hw_stats { | |
| 2481 | u8 __reserved0[0x400-0x300]; | |
| 2482 | ||
| 2483 | /* Statistics maintained by Receive MAC. */ | |
| 2484 | tg3_stat64_t rx_octets; | |
| 2485 | u64 __reserved1; | |
| 2486 | tg3_stat64_t rx_fragments; | |
| 2487 | tg3_stat64_t rx_ucast_packets; | |
| 2488 | tg3_stat64_t rx_mcast_packets; | |
| 2489 | tg3_stat64_t rx_bcast_packets; | |
| 2490 | tg3_stat64_t rx_fcs_errors; | |
| 2491 | tg3_stat64_t rx_align_errors; | |
| 2492 | tg3_stat64_t rx_xon_pause_rcvd; | |
| 2493 | tg3_stat64_t rx_xoff_pause_rcvd; | |
| 2494 | tg3_stat64_t rx_mac_ctrl_rcvd; | |
| 2495 | tg3_stat64_t rx_xoff_entered; | |
| 2496 | tg3_stat64_t rx_frame_too_long_errors; | |
| 2497 | tg3_stat64_t rx_jabbers; | |
| 2498 | tg3_stat64_t rx_undersize_packets; | |
| 2499 | tg3_stat64_t rx_in_length_errors; | |
| 2500 | tg3_stat64_t rx_out_length_errors; | |
| 2501 | tg3_stat64_t rx_64_or_less_octet_packets; | |
| 2502 | tg3_stat64_t rx_65_to_127_octet_packets; | |
| 2503 | tg3_stat64_t rx_128_to_255_octet_packets; | |
| 2504 | tg3_stat64_t rx_256_to_511_octet_packets; | |
| 2505 | tg3_stat64_t rx_512_to_1023_octet_packets; | |
| 2506 | tg3_stat64_t rx_1024_to_1522_octet_packets; | |
| 2507 | tg3_stat64_t rx_1523_to_2047_octet_packets; | |
| 2508 | tg3_stat64_t rx_2048_to_4095_octet_packets; | |
| 2509 | tg3_stat64_t rx_4096_to_8191_octet_packets; | |
| 2510 | tg3_stat64_t rx_8192_to_9022_octet_packets; | |
| 2511 | ||
| 2512 | u64 __unused0[37]; | |
| 2513 | ||
| 2514 | /* Statistics maintained by Transmit MAC. */ | |
| 2515 | tg3_stat64_t tx_octets; | |
| 2516 | u64 __reserved2; | |
| 2517 | tg3_stat64_t tx_collisions; | |
| 2518 | tg3_stat64_t tx_xon_sent; | |
| 2519 | tg3_stat64_t tx_xoff_sent; | |
| 2520 | tg3_stat64_t tx_flow_control; | |
| 2521 | tg3_stat64_t tx_mac_errors; | |
| 2522 | tg3_stat64_t tx_single_collisions; | |
| 2523 | tg3_stat64_t tx_mult_collisions; | |
| 2524 | tg3_stat64_t tx_deferred; | |
| 2525 | u64 __reserved3; | |
| 2526 | tg3_stat64_t tx_excessive_collisions; | |
| 2527 | tg3_stat64_t tx_late_collisions; | |
| 2528 | tg3_stat64_t tx_collide_2times; | |
| 2529 | tg3_stat64_t tx_collide_3times; | |
| 2530 | tg3_stat64_t tx_collide_4times; | |
| 2531 | tg3_stat64_t tx_collide_5times; | |
| 2532 | tg3_stat64_t tx_collide_6times; | |
| 2533 | tg3_stat64_t tx_collide_7times; | |
| 2534 | tg3_stat64_t tx_collide_8times; | |
| 2535 | tg3_stat64_t tx_collide_9times; | |
| 2536 | tg3_stat64_t tx_collide_10times; | |
| 2537 | tg3_stat64_t tx_collide_11times; | |
| 2538 | tg3_stat64_t tx_collide_12times; | |
| 2539 | tg3_stat64_t tx_collide_13times; | |
| 2540 | tg3_stat64_t tx_collide_14times; | |
| 2541 | tg3_stat64_t tx_collide_15times; | |
| 2542 | tg3_stat64_t tx_ucast_packets; | |
| 2543 | tg3_stat64_t tx_mcast_packets; | |
| 2544 | tg3_stat64_t tx_bcast_packets; | |
| 2545 | tg3_stat64_t tx_carrier_sense_errors; | |
| 2546 | tg3_stat64_t tx_discards; | |
| 2547 | tg3_stat64_t tx_errors; | |
| 2548 | ||
| 2549 | u64 __unused1[31]; | |
| 2550 | ||
| 2551 | /* Statistics maintained by Receive List Placement. */ | |
| 2552 | tg3_stat64_t COS_rx_packets[16]; | |
| 2553 | tg3_stat64_t COS_rx_filter_dropped; | |
| 2554 | tg3_stat64_t dma_writeq_full; | |
| 2555 | tg3_stat64_t dma_write_prioq_full; | |
| 2556 | tg3_stat64_t rxbds_empty; | |
| 2557 | tg3_stat64_t rx_discards; | |
| 2558 | tg3_stat64_t rx_errors; | |
| 2559 | tg3_stat64_t rx_threshold_hit; | |
| 2560 | ||
| 2561 | u64 __unused2[9]; | |
| 2562 | ||
| 2563 | /* Statistics maintained by Send Data Initiator. */ | |
| 2564 | tg3_stat64_t COS_out_packets[16]; | |
| 2565 | tg3_stat64_t dma_readq_full; | |
| 2566 | tg3_stat64_t dma_read_prioq_full; | |
| 2567 | tg3_stat64_t tx_comp_queue_full; | |
| 2568 | ||
| 2569 | /* Statistics maintained by Host Coalescing. */ | |
| 2570 | tg3_stat64_t ring_set_send_prod_index; | |
| 2571 | tg3_stat64_t ring_status_update; | |
| 2572 | tg3_stat64_t nic_irqs; | |
| 2573 | tg3_stat64_t nic_avoided_irqs; | |
| 2574 | tg3_stat64_t nic_tx_threshold_hit; | |
| 2575 | ||
| 2576 | u8 __reserved4[0xb00-0x9c0]; | |
| 2577 | }; | |
| 2578 | ||
| 2579 | /* 'mapping' is superfluous as the chip does not write into | |
| 2580 | * the tx/rx post rings so we could just fetch it from there. | |
| 2581 | * But the cache behavior is better how we are doing it now. | |
| 2582 | */ | |
| 2583 | struct ring_info { | |
| 2584 | struct sk_buff *skb; | |
| 4e5e4f0d | 2585 | DEFINE_DMA_UNMAP_ADDR(mapping); |
| 1da177e4 LT |
2586 | }; |
| 2587 | ||
| 1da177e4 LT |
2588 | struct tg3_link_config { |
| 2589 | /* Describes what we're trying to get. */ | |
| 2590 | u32 advertising; | |
| 2591 | u16 speed; | |
| 2592 | u8 duplex; | |
| 2593 | u8 autoneg; | |
| 8d018621 | 2594 | u8 flowctrl; |
| 1da177e4 LT |
2595 | |
| 2596 | /* Describes what we actually have. */ | |
| 8d018621 MC |
2597 | u8 active_flowctrl; |
| 2598 | ||
| 1da177e4 LT |
2599 | u8 active_duplex; |
| 2600 | #define SPEED_INVALID 0xffff | |
| 2601 | #define DUPLEX_INVALID 0xff | |
| 2602 | #define AUTONEG_INVALID 0xff | |
| 8d018621 | 2603 | u16 active_speed; |
| 1da177e4 LT |
2604 | |
| 2605 | /* When we go in and out of low power mode we need | |
| 2606 | * to swap with this state. | |
| 2607 | */ | |
| 1da177e4 LT |
2608 | u16 orig_speed; |
| 2609 | u8 orig_duplex; | |
| 2610 | u8 orig_autoneg; | |
| b02fd9e3 | 2611 | u32 orig_advertising; |
| 1da177e4 LT |
2612 | }; |
| 2613 | ||
| 2614 | struct tg3_bufmgr_config { | |
| 2615 | u32 mbuf_read_dma_low_water; | |
| 2616 | u32 mbuf_mac_rx_low_water; | |
| 2617 | u32 mbuf_high_water; | |
| 2618 | ||
| 2619 | u32 mbuf_read_dma_low_water_jumbo; | |
| 2620 | u32 mbuf_mac_rx_low_water_jumbo; | |
| 2621 | u32 mbuf_high_water_jumbo; | |
| 2622 | ||
| 2623 | u32 dma_low_water; | |
| 2624 | u32 dma_high_water; | |
| 2625 | }; | |
| 2626 | ||
| 2627 | struct tg3_ethtool_stats { | |
| 2628 | /* Statistics maintained by Receive MAC. */ | |
| c6cdf436 | 2629 | u64 rx_octets; |
| 1da177e4 LT |
2630 | u64 rx_fragments; |
| 2631 | u64 rx_ucast_packets; | |
| 2632 | u64 rx_mcast_packets; | |
| 2633 | u64 rx_bcast_packets; | |
| 2634 | u64 rx_fcs_errors; | |
| 2635 | u64 rx_align_errors; | |
| 2636 | u64 rx_xon_pause_rcvd; | |
| 2637 | u64 rx_xoff_pause_rcvd; | |
| 2638 | u64 rx_mac_ctrl_rcvd; | |
| 2639 | u64 rx_xoff_entered; | |
| 2640 | u64 rx_frame_too_long_errors; | |
| 2641 | u64 rx_jabbers; | |
| 2642 | u64 rx_undersize_packets; | |
| 2643 | u64 rx_in_length_errors; | |
| 2644 | u64 rx_out_length_errors; | |
| 2645 | u64 rx_64_or_less_octet_packets; | |
| 2646 | u64 rx_65_to_127_octet_packets; | |
| 2647 | u64 rx_128_to_255_octet_packets; | |
| 2648 | u64 rx_256_to_511_octet_packets; | |
| 2649 | u64 rx_512_to_1023_octet_packets; | |
| 2650 | u64 rx_1024_to_1522_octet_packets; | |
| 2651 | u64 rx_1523_to_2047_octet_packets; | |
| 2652 | u64 rx_2048_to_4095_octet_packets; | |
| 2653 | u64 rx_4096_to_8191_octet_packets; | |
| 2654 | u64 rx_8192_to_9022_octet_packets; | |
| 2655 | ||
| 2656 | /* Statistics maintained by Transmit MAC. */ | |
| 2657 | u64 tx_octets; | |
| 2658 | u64 tx_collisions; | |
| 2659 | u64 tx_xon_sent; | |
| 2660 | u64 tx_xoff_sent; | |
| 2661 | u64 tx_flow_control; | |
| 2662 | u64 tx_mac_errors; | |
| 2663 | u64 tx_single_collisions; | |
| 2664 | u64 tx_mult_collisions; | |
| 2665 | u64 tx_deferred; | |
| 2666 | u64 tx_excessive_collisions; | |
| 2667 | u64 tx_late_collisions; | |
| 2668 | u64 tx_collide_2times; | |
| 2669 | u64 tx_collide_3times; | |
| 2670 | u64 tx_collide_4times; | |
| 2671 | u64 tx_collide_5times; | |
| 2672 | u64 tx_collide_6times; | |
| 2673 | u64 tx_collide_7times; | |
| 2674 | u64 tx_collide_8times; | |
| 2675 | u64 tx_collide_9times; | |
| 2676 | u64 tx_collide_10times; | |
| 2677 | u64 tx_collide_11times; | |
| 2678 | u64 tx_collide_12times; | |
| 2679 | u64 tx_collide_13times; | |
| 2680 | u64 tx_collide_14times; | |
| 2681 | u64 tx_collide_15times; | |
| 2682 | u64 tx_ucast_packets; | |
| 2683 | u64 tx_mcast_packets; | |
| 2684 | u64 tx_bcast_packets; | |
| 2685 | u64 tx_carrier_sense_errors; | |
| 2686 | u64 tx_discards; | |
| 2687 | u64 tx_errors; | |
| 2688 | ||
| 2689 | /* Statistics maintained by Receive List Placement. */ | |
| 2690 | u64 dma_writeq_full; | |
| 2691 | u64 dma_write_prioq_full; | |
| 2692 | u64 rxbds_empty; | |
| 2693 | u64 rx_discards; | |
| 2694 | u64 rx_errors; | |
| 2695 | u64 rx_threshold_hit; | |
| 2696 | ||
| 2697 | /* Statistics maintained by Send Data Initiator. */ | |
| 2698 | u64 dma_readq_full; | |
| 2699 | u64 dma_read_prioq_full; | |
| 2700 | u64 tx_comp_queue_full; | |
| 2701 | ||
| 2702 | /* Statistics maintained by Host Coalescing. */ | |
| 2703 | u64 ring_set_send_prod_index; | |
| 2704 | u64 ring_status_update; | |
| 2705 | u64 nic_irqs; | |
| 2706 | u64 nic_avoided_irqs; | |
| 2707 | u64 nic_tx_threshold_hit; | |
| 2708 | }; | |
| 2709 | ||
| 21f581a5 | 2710 | struct tg3_rx_prodring_set { |
| 411da640 | 2711 | u32 rx_std_prod_idx; |
| b196c7e4 | 2712 | u32 rx_std_cons_idx; |
| 411da640 | 2713 | u32 rx_jmb_prod_idx; |
| b196c7e4 | 2714 | u32 rx_jmb_cons_idx; |
| 21f581a5 | 2715 | struct tg3_rx_buffer_desc *rx_std; |
| 79ed5ac7 | 2716 | struct tg3_ext_rx_buffer_desc *rx_jmb; |
| 21f581a5 MC |
2717 | struct ring_info *rx_std_buffers; |
| 2718 | struct ring_info *rx_jmb_buffers; | |
| 2719 | dma_addr_t rx_std_mapping; | |
| 2720 | dma_addr_t rx_jmb_mapping; | |
| 2721 | }; | |
| 2722 | ||
| 6fd45cb8 MC |
2723 | #define TG3_IRQ_MAX_VECS_RSS 5 |
| 2724 | #define TG3_IRQ_MAX_VECS TG3_IRQ_MAX_VECS_RSS | |
| 8ef0442f MC |
2725 | |
| 2726 | struct tg3_napi { | |
| 2727 | struct napi_struct napi ____cacheline_aligned; | |
| 2728 | struct tg3 *tp; | |
| 898a56f8 MC |
2729 | struct tg3_hw_status *hw_status; |
| 2730 | ||
| 2731 | u32 last_tag; | |
| 2732 | u32 last_irq_tag; | |
| 2733 | u32 int_mbox; | |
| fd2ce37f | 2734 | u32 coal_now; |
| f3f3f27e | 2735 | |
| 07ae8fc0 | 2736 | u32 consmbox ____cacheline_aligned; |
| 72334482 | 2737 | u32 rx_rcb_ptr; |
| 8d9d7cfc | 2738 | u16 *rx_rcb_prod_idx; |
| 8fea32b9 | 2739 | struct tg3_rx_prodring_set prodring; |
| 72334482 | 2740 | struct tg3_rx_buffer_desc *rx_rcb; |
| 07ae8fc0 MC |
2741 | |
| 2742 | u32 tx_prod ____cacheline_aligned; | |
| 2743 | u32 tx_cons; | |
| 2744 | u32 tx_pending; | |
| 2745 | u32 prodmbox; | |
| f3f3f27e | 2746 | struct tg3_tx_buffer_desc *tx_ring; |
| f4188d8a | 2747 | struct ring_info *tx_buffers; |
| 898a56f8 MC |
2748 | |
| 2749 | dma_addr_t status_mapping; | |
| 72334482 | 2750 | dma_addr_t rx_rcb_mapping; |
| f3f3f27e | 2751 | dma_addr_t tx_desc_mapping; |
| 4f125f42 MC |
2752 | |
| 2753 | char irq_lbl[IFNAMSIZ]; | |
| 2754 | unsigned int irq_vec; | |
| 8ef0442f MC |
2755 | }; |
| 2756 | ||
| 1da177e4 LT |
2757 | struct tg3 { |
| 2758 | /* begin "general, frequently-used members" cacheline section */ | |
| 2759 | ||
| f47c11ee DM |
2760 | /* If the IRQ handler (which runs lockless) needs to be |
| 2761 | * quiesced, the following bitmask state is used. The | |
| 2762 | * SYNC flag is set by non-IRQ context code to initiate | |
| 2763 | * the quiescence. | |
| 2764 | * | |
| 2765 | * When the IRQ handler notices that SYNC is set, it | |
| 2766 | * disables interrupts and returns. | |
| 2767 | * | |
| 2768 | * When all outstanding IRQ handlers have returned after | |
| 2769 | * the SYNC flag has been set, the setter can be assured | |
| 2770 | * that interrupts will no longer get run. | |
| 2771 | * | |
| 2772 | * In this way all SMP driver locks are never acquired | |
| 2773 | * in hw IRQ context, only sw IRQ context or lower. | |
| 2774 | */ | |
| 2775 | unsigned int irq_sync; | |
| 2776 | ||
| 1da177e4 LT |
2777 | /* SMP locking strategy: |
| 2778 | * | |
| 00b70504 MC |
2779 | * lock: Held during reset, PHY access, timer, and when |
| 2780 | * updating tg3_flags and tg3_flags2. | |
| 1da177e4 | 2781 | * |
| 1b2a7205 MC |
2782 | * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds |
| 2783 | * netif_tx_lock when it needs to call | |
| 2784 | * netif_wake_queue. | |
| 1da177e4 | 2785 | * |
| f47c11ee | 2786 | * Both of these locks are to be held with BH safety. |
| 00b70504 MC |
2787 | * |
| 2788 | * Because the IRQ handler, tg3_poll, and tg3_start_xmit | |
| 2789 | * are running lockless, it is necessary to completely | |
| 2790 | * quiesce the chip with tg3_netif_stop and tg3_full_lock | |
| 2791 | * before reconfiguring the device. | |
| 2792 | * | |
| 2793 | * indirect_lock: Held when accessing registers indirectly | |
| 2794 | * with IRQ disabling. | |
| 1da177e4 LT |
2795 | */ |
| 2796 | spinlock_t lock; | |
| 2797 | spinlock_t indirect_lock; | |
| 2798 | ||
| 20094930 MC |
2799 | u32 (*read32) (struct tg3 *, u32); |
| 2800 | void (*write32) (struct tg3 *, u32, u32); | |
| 09ee929c | 2801 | u32 (*read32_mbox) (struct tg3 *, u32); |
| 20094930 MC |
2802 | void (*write32_mbox) (struct tg3 *, u32, |
| 2803 | u32); | |
| 1da177e4 | 2804 | void __iomem *regs; |
| 0d3031d9 | 2805 | void __iomem *aperegs; |
| 1da177e4 LT |
2806 | struct net_device *dev; |
| 2807 | struct pci_dev *pdev; | |
| 2808 | ||
| f89f38b8 | 2809 | u32 coal_now; |
| 1da177e4 LT |
2810 | u32 msg_enable; |
| 2811 | ||
| 2812 | /* begin "tx thread" cacheline section */ | |
| 20094930 MC |
2813 | void (*write32_tx_mbox) (struct tg3 *, u32, |
| 2814 | u32); | |
| 1da177e4 LT |
2815 | |
| 2816 | /* begin "rx thread" cacheline section */ | |
| 8ef0442f | 2817 | struct tg3_napi napi[TG3_IRQ_MAX_VECS]; |
| 20094930 MC |
2818 | void (*write32_rx_mbox) (struct tg3 *, u32, |
| 2819 | u32); | |
| d2757fc4 | 2820 | u32 rx_copy_thresh; |
| 2c49a44d MC |
2821 | u32 rx_std_ring_mask; |
| 2822 | u32 rx_jmb_ring_mask; | |
| 7cb32cf2 | 2823 | u32 rx_ret_ring_mask; |
| 1da177e4 LT |
2824 | u32 rx_pending; |
| 2825 | u32 rx_jumbo_pending; | |
| 21f581a5 | 2826 | u32 rx_std_max_post; |
| d2757fc4 | 2827 | u32 rx_offset; |
| 21f581a5 | 2828 | u32 rx_pkt_map_sz; |
| 1da177e4 | 2829 | |
| 7e72aad4 | 2830 | |
| 1da177e4 | 2831 | /* begin "everything else" cacheline(s) section */ |
| b0057c51 | 2832 | unsigned long rx_dropped; |
| 511d2224 | 2833 | struct rtnl_link_stats64 net_stats_prev; |
| 1da177e4 LT |
2834 | struct tg3_ethtool_stats estats; |
| 2835 | struct tg3_ethtool_stats estats_prev; | |
| 2836 | ||
| 4ba526ce | 2837 | union { |
| 1da177e4 | 2838 | unsigned long phy_crc_errors; |
| 4ba526ce MC |
2839 | unsigned long last_event_jiffies; |
| 2840 | }; | |
| 1da177e4 | 2841 | |
| 1da177e4 | 2842 | u32 tg3_flags; |
| fac9b83e | 2843 | #define TG3_FLAG_TAGGED_STATUS 0x00000001 |
| 1da177e4 LT |
2844 | #define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002 |
| 2845 | #define TG3_FLAG_RX_CHECKSUMS 0x00000004 | |
| 2846 | #define TG3_FLAG_USE_LINKCHG_REG 0x00000008 | |
| 1da177e4 | 2847 | #define TG3_FLAG_ENABLE_ASF 0x00000020 |
| 8ed5d97e | 2848 | #define TG3_FLAG_ASPM_WORKAROUND 0x00000040 |
| 1da177e4 | 2849 | #define TG3_FLAG_POLL_SERDES 0x00000080 |
| 1da177e4 | 2850 | #define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100 |
| 1da177e4 LT |
2851 | #define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200 |
| 2852 | #define TG3_FLAG_WOL_SPEED_100MB 0x00000400 | |
| 2853 | #define TG3_FLAG_WOL_ENABLE 0x00000800 | |
| 2854 | #define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000 | |
| 2855 | #define TG3_FLAG_NVRAM 0x00002000 | |
| 2856 | #define TG3_FLAG_NVRAM_BUFFERED 0x00004000 | |
| 8f666b07 | 2857 | #define TG3_FLAG_SUPPORT_MSI 0x00008000 |
| 679563f4 MC |
2858 | #define TG3_FLAG_SUPPORT_MSIX 0x00010000 |
| 2859 | #define TG3_FLAG_SUPPORT_MSI_OR_MSIX (TG3_FLAG_SUPPORT_MSI | \ | |
| 2860 | TG3_FLAG_SUPPORT_MSIX) | |
| 1da177e4 LT |
2861 | #define TG3_FLAG_PCIX_MODE 0x00020000 |
| 2862 | #define TG3_FLAG_PCI_HIGH_SPEED 0x00040000 | |
| 2863 | #define TG3_FLAG_PCI_32BIT 0x00080000 | |
| bbadf503 | 2864 | #define TG3_FLAG_SRAM_USE_CONFIG 0x00100000 |
| df3e6548 | 2865 | #define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000 |
| a85feb8c | 2866 | #define TG3_FLAG_WOL_CAP 0x00400000 |
| 0f893dc6 | 2867 | #define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000 |
| 1da177e4 | 2868 | #define TG3_FLAG_PAUSE_AUTONEG 0x02000000 |
| 795d01c5 | 2869 | #define TG3_FLAG_CPMU_PRESENT 0x04000000 |
| 4a29cc2e | 2870 | #define TG3_FLAG_40BIT_DMA_BUG 0x08000000 |
| 1da177e4 | 2871 | #define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000 |
| 8f666b07 | 2872 | #define TG3_FLAG_JUMBO_CAPABLE 0x20000000 |
| d18edcb2 | 2873 | #define TG3_FLAG_CHIP_RESETTING 0x40000000 |
| 1da177e4 LT |
2874 | #define TG3_FLAG_INIT_COMPLETE 0x80000000 |
| 2875 | u32 tg3_flags2; | |
| 2876 | #define TG3_FLG2_RESTART_TIMER 0x00000001 | |
| 7f62ad5d | 2877 | #define TG3_FLG2_TSO_BUG 0x00000002 |
| 1da177e4 LT |
2878 | #define TG3_FLG2_IS_5788 0x00000008 |
| 2879 | #define TG3_FLG2_MAX_RXPEND_64 0x00000010 | |
| 2880 | #define TG3_FLG2_TSO_CAPABLE 0x00000020 | |
| 1da177e4 LT |
2881 | #define TG3_FLG2_PCI_EXPRESS 0x00000200 |
| 2882 | #define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400 | |
| 2883 | #define TG3_FLG2_HW_AUTONEG 0x00000800 | |
| 9d26e213 | 2884 | #define TG3_FLG2_IS_NIC 0x00001000 |
| 1da177e4 | 2885 | #define TG3_FLG2_FLASH 0x00008000 |
| 5a6f3074 | 2886 | #define TG3_FLG2_HW_TSO_1 0x00010000 |
| 1da177e4 | 2887 | #define TG3_FLG2_5705_PLUS 0x00040000 |
| 6708e5cc | 2888 | #define TG3_FLG2_5750_PLUS 0x00080000 |
| e849cdc3 | 2889 | #define TG3_FLG2_HW_TSO_3 0x00100000 |
| 88b06bc2 | 2890 | #define TG3_FLG2_USING_MSI 0x00200000 |
| 679563f4 MC |
2891 | #define TG3_FLG2_USING_MSIX 0x00400000 |
| 2892 | #define TG3_FLG2_USING_MSI_OR_MSIX (TG3_FLG2_USING_MSI | \ | |
| 2893 | TG3_FLG2_USING_MSIX) | |
| 6892914f | 2894 | #define TG3_FLG2_ICH_WORKAROUND 0x02000000 |
| a4e2b347 | 2895 | #define TG3_FLG2_5780_CLASS 0x04000000 |
| 5a6f3074 | 2896 | #define TG3_FLG2_HW_TSO_2 0x08000000 |
| e849cdc3 MC |
2897 | #define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | \ |
| 2898 | TG3_FLG2_HW_TSO_2 | \ | |
| 2899 | TG3_FLG2_HW_TSO_3) | |
| fcfa0a32 | 2900 | #define TG3_FLG2_1SHOT_MSI 0x10000000 |
| f49639e6 | 2901 | #define TG3_FLG2_NO_FWARE_REPORTED 0x40000000 |
| 6b91fa02 MC |
2902 | u32 tg3_flags3; |
| 2903 | #define TG3_FLG3_NO_NVRAM_ADDR_TRANS 0x00000001 | |
| 0d3031d9 | 2904 | #define TG3_FLG3_ENABLE_APE 0x00000002 |
| f66a29b0 | 2905 | #define TG3_FLG3_PROTECTED_NVRAM 0x00000004 |
| 41588ba1 | 2906 | #define TG3_FLG3_5701_DMA_BUG 0x00000008 |
| dd477003 | 2907 | #define TG3_FLG3_USE_PHYLIB 0x00000010 |
| 158d7abd | 2908 | #define TG3_FLG3_MDIOBUS_INITED 0x00000020 |
| de9f5230 | 2909 | #define TG3_FLG3_LRG_PROD_RING_CAP 0x00000080 |
| 14417063 | 2910 | #define TG3_FLG3_RGMII_INBAND_DISABLE 0x00000100 |
| a9daf367 MC |
2911 | #define TG3_FLG3_RGMII_EXT_IBND_RX_EN 0x00000200 |
| 2912 | #define TG3_FLG3_RGMII_EXT_IBND_TX_EN 0x00000400 | |
| 5e7dfd0f | 2913 | #define TG3_FLG3_CLKREQ_BUG 0x00000800 |
| 321d32a0 | 2914 | #define TG3_FLG3_5755_PLUS 0x00002000 |
| df259d8c | 2915 | #define TG3_FLG3_NO_NVRAM 0x00004000 |
| baf8a94a | 2916 | #define TG3_FLG3_ENABLE_RSS 0x00020000 |
| 19cfaecc | 2917 | #define TG3_FLG3_ENABLE_TSS 0x00040000 |
| 0e1406dd MC |
2918 | #define TG3_FLG3_4G_DMA_BNDRY_BUG 0x00080000 |
| 2919 | #define TG3_FLG3_40BIT_DMA_LIMIT_BUG 0x00100000 | |
| 92c6b8d1 | 2920 | #define TG3_FLG3_SHORT_DMA_BUG 0x00200000 |
| b703df6f | 2921 | #define TG3_FLG3_USE_JUMBO_BDFLAG 0x00400000 |
| 614b0590 | 2922 | #define TG3_FLG3_L1PLLPD_EN 0x00800000 |
| 1407deb1 | 2923 | #define TG3_FLG3_57765_PLUS 0x01000000 |
| dc6d0744 | 2924 | #define TG3_FLG3_APE_HAS_NCSI 0x02000000 |
| 0a58d668 | 2925 | #define TG3_FLG3_5717_PLUS 0x04000000 |
| 1da177e4 | 2926 | |
| 1da177e4 LT |
2927 | struct timer_list timer; |
| 2928 | u16 timer_counter; | |
| 2929 | u16 timer_multiplier; | |
| 2930 | u32 timer_offset; | |
| 2931 | u16 asf_counter; | |
| 2932 | u16 asf_multiplier; | |
| 2933 | ||
| 3d3ebe74 MC |
2934 | /* 1 second counter for transient serdes link events */ |
| 2935 | u32 serdes_counter; | |
| 2936 | #define SERDES_AN_TIMEOUT_5704S 2 | |
| 2937 | #define SERDES_PARALLEL_DET_TIMEOUT 1 | |
| 2938 | #define SERDES_AN_TIMEOUT_5714S 1 | |
| 2939 | ||
| 1da177e4 LT |
2940 | struct tg3_link_config link_config; |
| 2941 | struct tg3_bufmgr_config bufmgr_config; | |
| 2942 | ||
| 2943 | /* cache h/w values, often passed straight to h/w */ | |
| 2944 | u32 rx_mode; | |
| 2945 | u32 tx_mode; | |
| 2946 | u32 mac_mode; | |
| 2947 | u32 mi_mode; | |
| 2948 | u32 misc_host_ctrl; | |
| 2949 | u32 grc_mode; | |
| 2950 | u32 grc_local_ctrl; | |
| 2951 | u32 dma_rwctrl; | |
| 2952 | u32 coalesce_mode; | |
| 8ed5d97e | 2953 | u32 pwrmgmt_thresh; |
| 1da177e4 LT |
2954 | |
| 2955 | /* PCI block */ | |
| 795d01c5 | 2956 | u32 pci_chip_rev_id; |
| 69fc4053 | 2957 | u16 pci_cmd; |
| 1da177e4 LT |
2958 | u8 pci_cacheline_sz; |
| 2959 | u8 pci_lat_timer; | |
| 1da177e4 LT |
2960 | |
| 2961 | int pm_cap; | |
| 4cf78e4f | 2962 | int msi_cap; |
| 5e7dfd0f | 2963 | union { |
| 9974a356 | 2964 | int pcix_cap; |
| 5e7dfd0f MC |
2965 | int pcie_cap; |
| 2966 | }; | |
| cf79003d | 2967 | int pcie_readrq; |
| 1da177e4 | 2968 | |
| 298cf9be | 2969 | struct mii_bus *mdio_bus; |
| 158d7abd MC |
2970 | int mdio_irq[PHY_MAX_ADDR]; |
| 2971 | ||
| 882e9793 MC |
2972 | u8 phy_addr; |
| 2973 | ||
| 1da177e4 LT |
2974 | /* PHY info */ |
| 2975 | u32 phy_id; | |
| 79eb6904 MC |
2976 | #define TG3_PHY_ID_MASK 0xfffffff0 |
| 2977 | #define TG3_PHY_ID_BCM5400 0x60008040 | |
| 2978 | #define TG3_PHY_ID_BCM5401 0x60008050 | |
| 2979 | #define TG3_PHY_ID_BCM5411 0x60008070 | |
| 2980 | #define TG3_PHY_ID_BCM5701 0x60008110 | |
| 2981 | #define TG3_PHY_ID_BCM5703 0x60008160 | |
| 2982 | #define TG3_PHY_ID_BCM5704 0x60008190 | |
| 2983 | #define TG3_PHY_ID_BCM5705 0x600081a0 | |
| 2984 | #define TG3_PHY_ID_BCM5750 0x60008180 | |
| 2985 | #define TG3_PHY_ID_BCM5752 0x60008100 | |
| 2986 | #define TG3_PHY_ID_BCM5714 0x60008340 | |
| 2987 | #define TG3_PHY_ID_BCM5780 0x60008350 | |
| 2988 | #define TG3_PHY_ID_BCM5755 0xbc050cc0 | |
| 2989 | #define TG3_PHY_ID_BCM5787 0xbc050ce0 | |
| 2990 | #define TG3_PHY_ID_BCM5756 0xbc050ed0 | |
| 2991 | #define TG3_PHY_ID_BCM5784 0xbc050fa0 | |
| 2992 | #define TG3_PHY_ID_BCM5761 0xbc050fd0 | |
| 2993 | #define TG3_PHY_ID_BCM5718C 0x5c0d8a00 | |
| 2994 | #define TG3_PHY_ID_BCM5718S 0xbc050ff0 | |
| 2995 | #define TG3_PHY_ID_BCM57765 0x5c0d8a40 | |
| 302b500b | 2996 | #define TG3_PHY_ID_BCM5719C 0x5c0d8a20 |
| 79eb6904 MC |
2997 | #define TG3_PHY_ID_BCM5906 0xdc00ac40 |
| 2998 | #define TG3_PHY_ID_BCM8002 0x60010140 | |
| 79eb6904 MC |
2999 | #define TG3_PHY_ID_INVALID 0xffffffff |
| 3000 | ||
| 6a443a0f MC |
3001 | #define PHY_ID_RTL8211C 0x001cc910 |
| 3002 | #define PHY_ID_RTL8201E 0x00008200 | |
| 3003 | ||
| 79eb6904 MC |
3004 | #define TG3_PHY_ID_REV_MASK 0x0000000f |
| 3005 | #define TG3_PHY_REV_BCM5401_B0 0x1 | |
| 3006 | ||
| 79eb6904 MC |
3007 | /* This macro assumes the passed PHY ID is |
| 3008 | * already masked with TG3_PHY_ID_MASK. | |
| 3009 | */ | |
| 3010 | #define TG3_KNOWN_PHY_ID(X) \ | |
| 3011 | ((X) == TG3_PHY_ID_BCM5400 || (X) == TG3_PHY_ID_BCM5401 || \ | |
| 3012 | (X) == TG3_PHY_ID_BCM5411 || (X) == TG3_PHY_ID_BCM5701 || \ | |
| 3013 | (X) == TG3_PHY_ID_BCM5703 || (X) == TG3_PHY_ID_BCM5704 || \ | |
| 3014 | (X) == TG3_PHY_ID_BCM5705 || (X) == TG3_PHY_ID_BCM5750 || \ | |
| 3015 | (X) == TG3_PHY_ID_BCM5752 || (X) == TG3_PHY_ID_BCM5714 || \ | |
| 3016 | (X) == TG3_PHY_ID_BCM5780 || (X) == TG3_PHY_ID_BCM5787 || \ | |
| 3017 | (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \ | |
| 3018 | (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \ | |
| 3019 | (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \ | |
| 302b500b MC |
3020 | (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \ |
| 3021 | (X) == TG3_PHY_ID_BCM8002) | |
| 79eb6904 | 3022 | |
| 80096068 MC |
3023 | u32 phy_flags; |
| 3024 | #define TG3_PHYFLG_IS_LOW_POWER 0x00000001 | |
| f07e9af3 MC |
3025 | #define TG3_PHYFLG_IS_CONNECTED 0x00000002 |
| 3026 | #define TG3_PHYFLG_USE_MI_INTERRUPT 0x00000004 | |
| 3027 | #define TG3_PHYFLG_PHY_SERDES 0x00000010 | |
| 3028 | #define TG3_PHYFLG_MII_SERDES 0x00000020 | |
| 3029 | #define TG3_PHYFLG_ANY_SERDES (TG3_PHYFLG_PHY_SERDES | \ | |
| 3030 | TG3_PHYFLG_MII_SERDES) | |
| 3031 | #define TG3_PHYFLG_IS_FET 0x00000040 | |
| 3032 | #define TG3_PHYFLG_10_100_ONLY 0x00000080 | |
| 3033 | #define TG3_PHYFLG_ENABLE_APD 0x00000100 | |
| 3034 | #define TG3_PHYFLG_CAPACITIVE_COUPLING 0x00000200 | |
| 3035 | #define TG3_PHYFLG_NO_ETH_WIRE_SPEED 0x00000400 | |
| 3036 | #define TG3_PHYFLG_JITTER_BUG 0x00000800 | |
| 3037 | #define TG3_PHYFLG_ADJUST_TRIM 0x00001000 | |
| 3038 | #define TG3_PHYFLG_ADC_BUG 0x00002000 | |
| 3039 | #define TG3_PHYFLG_5704_A0_BUG 0x00004000 | |
| 3040 | #define TG3_PHYFLG_BER_BUG 0x00008000 | |
| 3041 | #define TG3_PHYFLG_SERDES_PREEMPHASIS 0x00010000 | |
| 3042 | #define TG3_PHYFLG_PARALLEL_DETECT 0x00020000 | |
| 52b02d04 | 3043 | #define TG3_PHYFLG_EEE_CAP 0x00040000 |
| 80096068 | 3044 | |
| 1da177e4 | 3045 | u32 led_ctrl; |
| b2a5c19c | 3046 | u32 phy_otp; |
| 52b02d04 | 3047 | u32 setlpicnt; |
| 1da177e4 | 3048 | |
| 141518c9 MC |
3049 | #define TG3_BPN_SIZE 24 |
| 3050 | char board_part_number[TG3_BPN_SIZE]; | |
| 3051 | #define TG3_VER_SIZE ETHTOOL_FWVERS_LEN | |
| 9c8a620e | 3052 | char fw_ver[TG3_VER_SIZE]; |
| 1da177e4 LT |
3053 | u32 nic_sram_data_cfg; |
| 3054 | u32 pci_clock_ctrl; | |
| 3055 | struct pci_dev *pdev_peer; | |
| 3056 | ||
| 1da177e4 LT |
3057 | struct tg3_hw_stats *hw_stats; |
| 3058 | dma_addr_t stats_mapping; | |
| 3059 | struct work_struct reset_task; | |
| 3060 | ||
| ec41c7df | 3061 | int nvram_lock_cnt; |
| 1da177e4 | 3062 | u32 nvram_size; |
| fd1122a2 MC |
3063 | #define TG3_NVRAM_SIZE_64KB 0x00010000 |
| 3064 | #define TG3_NVRAM_SIZE_128KB 0x00020000 | |
| 3065 | #define TG3_NVRAM_SIZE_256KB 0x00040000 | |
| 3066 | #define TG3_NVRAM_SIZE_512KB 0x00080000 | |
| 3067 | #define TG3_NVRAM_SIZE_1MB 0x00100000 | |
| 3068 | #define TG3_NVRAM_SIZE_2MB 0x00200000 | |
| 3069 | ||
| 1da177e4 LT |
3070 | u32 nvram_pagesize; |
| 3071 | u32 nvram_jedecnum; | |
| 3072 | ||
| 3073 | #define JEDEC_ATMEL 0x1f | |
| 3074 | #define JEDEC_ST 0x20 | |
| 3075 | #define JEDEC_SAIFUN 0x4f | |
| 3076 | #define JEDEC_SST 0xbf | |
| 3077 | ||
| fd1122a2 | 3078 | #define ATMEL_AT24C64_CHIP_SIZE TG3_NVRAM_SIZE_64KB |
| 1da177e4 LT |
3079 | #define ATMEL_AT24C64_PAGE_SIZE (32) |
| 3080 | ||
| fd1122a2 | 3081 | #define ATMEL_AT24C512_CHIP_SIZE TG3_NVRAM_SIZE_512KB |
| 1da177e4 LT |
3082 | #define ATMEL_AT24C512_PAGE_SIZE (128) |
| 3083 | ||
| 3084 | #define ATMEL_AT45DB0X1B_PAGE_POS 9 | |
| 3085 | #define ATMEL_AT45DB0X1B_PAGE_SIZE 264 | |
| 3086 | ||
| 3087 | #define ATMEL_AT25F512_PAGE_SIZE 256 | |
| 3088 | ||
| 3089 | #define ST_M45PEX0_PAGE_SIZE 256 | |
| 3090 | ||
| 3091 | #define SAIFUN_SA25F0XX_PAGE_SIZE 256 | |
| 3092 | ||
| 3093 | #define SST_25VF0X0_PAGE_SIZE 4098 | |
| 3094 | ||
| 4f125f42 MC |
3095 | unsigned int irq_max; |
| 3096 | unsigned int irq_cnt; | |
| 3097 | ||
| 15f9850d | 3098 | struct ethtool_coalesce coal; |
| 077f849d JSR |
3099 | |
| 3100 | /* firmware info */ | |
| 9e9fd12d | 3101 | const char *fw_needed; |
| 077f849d JSR |
3102 | const struct firmware *fw; |
| 3103 | u32 fw_len; /* includes BSS */ | |
| 1da177e4 LT |
3104 | }; |
| 3105 | ||
| 3106 | #endif /* !(_T3_H) */ |