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[BLUETOOTH]: Introduce skb->data accessor methods for hci_{acl,event,sco}_hdr
[deliverable/linux.git] / drivers / net / tulip / dmfe.c
CommitLineData
1da177e4
LT		 1/*
2 A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
3 ethernet driver for Linux.
4 Copyright (C) 1997 Sten Wang
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 DAVICOM Web-Site: www.davicom.com.tw
17
18 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
19 Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
20
21 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
22
23 Marcelo Tosatti <marcelo@conectiva.com.br> :
24 Made it compile in 2.3 (device to net_device)
25
26 Alan Cox <alan@redhat.com> :
27 Cleaned up for kernel merge.
28 Removed the back compatibility support
29 Reformatted, fixing spelling etc as I went
30 Removed IRQ 0-15 assumption
31
32 Jeff Garzik <jgarzik@pobox.com> :
33 Updated to use new PCI driver API.
34 Resource usage cleanups.
35 Report driver version to user.
36
37 Tobias Ringstrom <tori@unhappy.mine.nu> :
38 Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
39 Andrew Morton and Frank Davis for the SMP safety fixes.
40
41 Vojtech Pavlik <vojtech@suse.cz> :
42 Cleaned up pointer arithmetics.
43 Fixed a lot of 64bit issues.
44 Cleaned up printk()s a bit.
45 Fixed some obvious big endian problems.
46
47 Tobias Ringstrom <tori@unhappy.mine.nu> :
48 Use time_after for jiffies calculation. Added ethtool
49 support. Updated PCI resource allocation. Do not
50 forget to unmap PCI mapped skbs.
51
52 Alan Cox <alan@redhat.com>
f3b197ac 53 Added new PCI identifiers provided by Clear Zhang at ALi
1da177e4
LT		 54 for their 1563 ethernet device.
55
56 TODO
57
58 Implement pci_driver::suspend() and pci_driver::resume()
59 power management methods.
60
61 Check on 64 bit boxes.
62 Check and fix on big endian boxes.
63
64 Test and make sure PCI latency is now correct for all cases.
65*/
66
67#define DRV_NAME "dmfe"
68#define DRV_VERSION "1.36.4"
69#define DRV_RELDATE "2002-01-17"
70
71#include <linux/module.h>
72#include <linux/kernel.h>
73#include <linux/string.h>
74#include <linux/timer.h>
75#include <linux/ptrace.h>
76#include <linux/errno.h>
77#include <linux/ioport.h>
78#include <linux/slab.h>
79#include <linux/interrupt.h>
80#include <linux/pci.h>
cb199d42 81#include <linux/dma-mapping.h>
1da177e4
LT		 82#include <linux/init.h>
83#include <linux/netdevice.h>
84#include <linux/etherdevice.h>
85#include <linux/ethtool.h>
86#include <linux/skbuff.h>
87#include <linux/delay.h>
88#include <linux/spinlock.h>
89#include <linux/crc32.h>
90#include <linux/bitops.h>
91
92#include <asm/processor.h>
93#include <asm/io.h>
94#include <asm/dma.h>
95#include <asm/uaccess.h>
96#include <asm/irq.h>
97
98
99/* Board/System/Debug information/definition ---------------- */
100#define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
101#define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
102#define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
103#define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
104
105#define DM9102_IO_SIZE 0x80
106#define DM9102A_IO_SIZE 0x100
107#define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
108#define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
109#define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
110#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
111#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
112#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
113#define TX_BUF_ALLOC 0x600
114#define RX_ALLOC_SIZE 0x620
115#define DM910X_RESET 1
116#define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
117#define CR6_DEFAULT 0x00080000 /* HD */
118#define CR7_DEFAULT 0x180c1
119#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
120#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
121#define MAX_PACKET_SIZE 1514
122#define DMFE_MAX_MULTICAST 14
123#define RX_COPY_SIZE 100
124#define MAX_CHECK_PACKET 0x8000
125#define DM9801_NOISE_FLOOR 8
126#define DM9802_NOISE_FLOOR 5
127
128#define DMFE_10MHF 0
129#define DMFE_100MHF 1
130#define DMFE_10MFD 4
131#define DMFE_100MFD 5
132#define DMFE_AUTO 8
133#define DMFE_1M_HPNA 0x10
134
135#define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
136#define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
137#define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
138#define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
139#define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
140#define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
141
142#define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
143#define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
144#define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
145
f67ba792
ML		 146#define DMFE_DBUG(dbug_now, msg, value) \
147 do { \
148 if (dmfe_debug || (dbug_now)) \
149 printk(KERN_ERR DRV_NAME ": %s %lx\n",\
150 (msg), (long) (value)); \
151 } while (0)
1da177e4 152
f67ba792
ML		 153#define SHOW_MEDIA_TYPE(mode) \
154 printk (KERN_INFO DRV_NAME ": Change Speed to %sMhz %s duplex\n" , \
155 (mode & 1) ? "100":"10", (mode & 4) ? "full":"half");
1da177e4
LT		 156
157
158/* CR9 definition: SROM/MII */
159#define CR9_SROM_READ 0x4800
160#define CR9_SRCS 0x1
161#define CR9_SRCLK 0x2
162#define CR9_CRDOUT 0x8
163#define SROM_DATA_0 0x0
164#define SROM_DATA_1 0x4
165#define PHY_DATA_1 0x20000
166#define PHY_DATA_0 0x00000
167#define MDCLKH 0x10000
168
169#define PHY_POWER_DOWN 0x800
170
171#define SROM_V41_CODE 0x14
172
f67ba792
ML		 173#define SROM_CLK_WRITE(data, ioaddr) \
174 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
175 udelay(5); \
176 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
177 udelay(5); \
178 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
179 udelay(5);
180
181#define __CHK_IO_SIZE(pci_id, dev_rev) \
182 (( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? \
183 DM9102A_IO_SIZE: DM9102_IO_SIZE)
1da177e4 184
f67ba792
ML		 185#define CHK_IO_SIZE(pci_dev, dev_rev) \
186 (__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev))
1da177e4
LT		 187
188/* Sten Check */
189#define DEVICE net_device
190
191/* Structure/enum declaration ------------------------------- */
192struct tx_desc {
a31e40f6 193 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
1da177e4
LT		 194 char *tx_buf_ptr; /* Data for us */
195 struct tx_desc *next_tx_desc;
196} __attribute__(( aligned(32) ));
197
198struct rx_desc {
a31e40f6 199 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
1da177e4
LT		 200 struct sk_buff *rx_skb_ptr; /* Data for us */
201 struct rx_desc *next_rx_desc;
202} __attribute__(( aligned(32) ));
203
204struct dmfe_board_info {
205 u32 chip_id; /* Chip vendor/Device ID */
206 u32 chip_revision; /* Chip revision */
ead9bffb 207 struct DEVICE *next_dev; /* next device */
1da177e4
LT		 208 struct pci_dev *pdev; /* PCI device */
209 spinlock_t lock;
210
211 long ioaddr; /* I/O base address */
212 u32 cr0_data;
213 u32 cr5_data;
214 u32 cr6_data;
215 u32 cr7_data;
216 u32 cr15_data;
217
218 /* pointer for memory physical address */
219 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
220 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
221 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
222 dma_addr_t first_tx_desc_dma;
223 dma_addr_t first_rx_desc_dma;
224
225 /* descriptor pointer */
226 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
227 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
228 unsigned char *desc_pool_ptr; /* descriptor pool memory */
229 struct tx_desc *first_tx_desc;
230 struct tx_desc *tx_insert_ptr;
231 struct tx_desc *tx_remove_ptr;
232 struct rx_desc *first_rx_desc;
233 struct rx_desc *rx_insert_ptr;
234 struct rx_desc *rx_ready_ptr; /* packet come pointer */
235 unsigned long tx_packet_cnt; /* transmitted packet count */
236 unsigned long tx_queue_cnt; /* wait to send packet count */
237 unsigned long rx_avail_cnt; /* available rx descriptor count */
238 unsigned long interval_rx_cnt; /* rx packet count a callback time */
239
240 u16 HPNA_command; /* For HPNA register 16 */
241 u16 HPNA_timer; /* For HPNA remote device check */
242 u16 dbug_cnt;
243 u16 NIC_capability; /* NIC media capability */
244 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
245
246 u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
247 u8 chip_type; /* Keep DM9102A chip type */
248 u8 media_mode; /* user specify media mode */
249 u8 op_mode; /* real work media mode */
250 u8 phy_addr;
1da177e4
LT		 251 u8 wait_reset; /* Hardware failed, need to reset */
252 u8 dm910x_chk_mode; /* Operating mode check */
253 u8 first_in_callback; /* Flag to record state */
254 struct timer_list timer;
255
256 /* System defined statistic counter */
257 struct net_device_stats stats;
258
259 /* Driver defined statistic counter */
260 unsigned long tx_fifo_underrun;
261 unsigned long tx_loss_carrier;
262 unsigned long tx_no_carrier;
263 unsigned long tx_late_collision;
264 unsigned long tx_excessive_collision;
265 unsigned long tx_jabber_timeout;
266 unsigned long reset_count;
267 unsigned long reset_cr8;
268 unsigned long reset_fatal;
269 unsigned long reset_TXtimeout;
270
271 /* NIC SROM data */
272 unsigned char srom[128];
273};
274
275enum dmfe_offsets {
276 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
277 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
278 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
279 DCR15 = 0x78
280};
281
282enum dmfe_CR6_bits {
283 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
284 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
285 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
286};
287
288/* Global variable declaration ----------------------------- */
289static int __devinitdata printed_version;
290static char version[] __devinitdata =
291 KERN_INFO DRV_NAME ": Davicom DM9xxx net driver, version "
292 DRV_VERSION " (" DRV_RELDATE ")\n";
293
294static int dmfe_debug;
295static unsigned char dmfe_media_mode = DMFE_AUTO;
296static u32 dmfe_cr6_user_set;
297
298/* For module input parameter */
299static int debug;
300static u32 cr6set;
301static unsigned char mode = 8;
302static u8 chkmode = 1;
303static u8 HPNA_mode; /* Default: Low Power/High Speed */
304static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
305static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
306static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
307static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
308 4: TX pause packet */
309
310
311/* function declaration ------------------------------------- */
312static int dmfe_open(struct DEVICE *);
313static int dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
314static int dmfe_stop(struct DEVICE *);
315static struct net_device_stats * dmfe_get_stats(struct DEVICE *);
316static void dmfe_set_filter_mode(struct DEVICE *);
7282d491 317static const struct ethtool_ops netdev_ethtool_ops;
1da177e4 318static u16 read_srom_word(long ,int);
7d12e780 319static irqreturn_t dmfe_interrupt(int , void *);
1da177e4
LT		 320#ifdef CONFIG_NET_POLL_CONTROLLER
321static void poll_dmfe (struct net_device *dev);
322#endif
323static void dmfe_descriptor_init(struct dmfe_board_info *, unsigned long);
324static void allocate_rx_buffer(struct dmfe_board_info *);
325static void update_cr6(u32, unsigned long);
326static void send_filter_frame(struct DEVICE * ,int);
327static void dm9132_id_table(struct DEVICE * ,int);
328static u16 phy_read(unsigned long, u8, u8, u32);
329static void phy_write(unsigned long, u8, u8, u16, u32);
330static void phy_write_1bit(unsigned long, u32);
331static u16 phy_read_1bit(unsigned long);
332static u8 dmfe_sense_speed(struct dmfe_board_info *);
333static void dmfe_process_mode(struct dmfe_board_info *);
334static void dmfe_timer(unsigned long);
335static inline u32 cal_CRC(unsigned char *, unsigned int, u8);
336static void dmfe_rx_packet(struct DEVICE *, struct dmfe_board_info *);
337static void dmfe_free_tx_pkt(struct DEVICE *, struct dmfe_board_info *);
338static void dmfe_reuse_skb(struct dmfe_board_info *, struct sk_buff *);
339static void dmfe_dynamic_reset(struct DEVICE *);
340static void dmfe_free_rxbuffer(struct dmfe_board_info *);
341static void dmfe_init_dm910x(struct DEVICE *);
342static void dmfe_parse_srom(struct dmfe_board_info *);
343static void dmfe_program_DM9801(struct dmfe_board_info *, int);
344static void dmfe_program_DM9802(struct dmfe_board_info *);
345static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
346static void dmfe_set_phyxcer(struct dmfe_board_info *);
347
f67ba792 348/* DM910X network board routine ---------------------------- */
1da177e4
LT		 349
350/*
351 * Search DM910X board ,allocate space and register it
352 */
353
354static int __devinit dmfe_init_one (struct pci_dev *pdev,
355 const struct pci_device_id *ent)
356{
357 struct dmfe_board_info *db; /* board information structure */
358 struct net_device *dev;
359 u32 dev_rev, pci_pmr;
360 int i, err;
361
362 DMFE_DBUG(0, "dmfe_init_one()", 0);
363
364 if (!printed_version++)
365 printk(version);
366
367 /* Init network device */
368 dev = alloc_etherdev(sizeof(*db));
369 if (dev == NULL)
370 return -ENOMEM;
371 SET_MODULE_OWNER(dev);
372 SET_NETDEV_DEV(dev, &pdev->dev);
373
cb199d42 374 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
f67ba792
ML		 375 printk(KERN_WARNING DRV_NAME
376 ": 32-bit PCI DMA not available.\n");
1da177e4
LT		 377 err = -ENODEV;
378 goto err_out_free;
379 }
380
381 /* Enable Master/IO access, Disable memory access */
382 err = pci_enable_device(pdev);
383 if (err)
384 goto err_out_free;
385
386 if (!pci_resource_start(pdev, 0)) {
387 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
388 err = -ENODEV;
389 goto err_out_disable;
390 }
391
392 /* Read Chip revision */
393 pci_read_config_dword(pdev, PCI_REVISION_ID, &dev_rev);
394
395 if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev, dev_rev)) ) {
396 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
397 err = -ENODEV;
398 goto err_out_disable;
399 }
400
401#if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
402
403 /* Set Latency Timer 80h */
404 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
405 Need a PCI quirk.. */
406
407 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
408#endif
409
410 if (pci_request_regions(pdev, DRV_NAME)) {
411 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
412 err = -ENODEV;
413 goto err_out_disable;
414 }
415
416 /* Init system & device */
417 db = netdev_priv(dev);
418
419 /* Allocate Tx/Rx descriptor memory */
f67ba792
ML		 420 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) *
421 DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
422
423 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC *
424 TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
1da177e4
LT		 425
426 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
427 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
428 db->buf_pool_start = db->buf_pool_ptr;
429 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
430
431 db->chip_id = ent->driver_data;
432 db->ioaddr = pci_resource_start(pdev, 0);
433 db->chip_revision = dev_rev;
434
435 db->pdev = pdev;
436
437 dev->base_addr = db->ioaddr;
438 dev->irq = pdev->irq;
439 pci_set_drvdata(pdev, dev);
440 dev->open = &dmfe_open;
441 dev->hard_start_xmit = &dmfe_start_xmit;
442 dev->stop = &dmfe_stop;
443 dev->get_stats = &dmfe_get_stats;
444 dev->set_multicast_list = &dmfe_set_filter_mode;
445#ifdef CONFIG_NET_POLL_CONTROLLER
446 dev->poll_controller = &poll_dmfe;
447#endif
448 dev->ethtool_ops = &netdev_ethtool_ops;
cfa51b9d 449 netif_carrier_off(dev);
1da177e4
LT		 450 spin_lock_init(&db->lock);
451
452 pci_read_config_dword(pdev, 0x50, &pci_pmr);
453 pci_pmr &= 0x70000;
454 if ( (pci_pmr == 0x10000) && (dev_rev == 0x02000031) )
455 db->chip_type = 1; /* DM9102A E3 */
456 else
457 db->chip_type = 0;
458
459 /* read 64 word srom data */
460 for (i = 0; i < 64; i++)
a31e40f6 461 ((__le16 *) db->srom)[i] =
f67ba792 462 cpu_to_le16(read_srom_word(db->ioaddr, i));
1da177e4
LT		 463
464 /* Set Node address */
465 for (i = 0; i < 6; i++)
466 dev->dev_addr[i] = db->srom[20 + i];
467
468 err = register_netdev (dev);
469 if (err)
470 goto err_out_res;
471
472 printk(KERN_INFO "%s: Davicom DM%04lx at pci%s,",
473 dev->name,
474 ent->driver_data >> 16,
475 pci_name(pdev));
476 for (i = 0; i < 6; i++)
477 printk("%c%02x", i ? ':' : ' ', dev->dev_addr[i]);
478 printk(", irq %d.\n", dev->irq);
479
480 pci_set_master(pdev);
481
482 return 0;
483
484err_out_res:
485 pci_release_regions(pdev);
486err_out_disable:
487 pci_disable_device(pdev);
488err_out_free:
489 pci_set_drvdata(pdev, NULL);
490 free_netdev(dev);
491
492 return err;
493}
494
495
496static void __devexit dmfe_remove_one (struct pci_dev *pdev)
497{
498 struct net_device *dev = pci_get_drvdata(pdev);
499 struct dmfe_board_info *db = netdev_priv(dev);
500
501 DMFE_DBUG(0, "dmfe_remove_one()", 0);
502
503 if (dev) {
4dc68f3d
ML		 504
505 unregister_netdev(dev);
506
1da177e4
LT		 507 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
508 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
509 db->desc_pool_dma_ptr);
510 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
511 db->buf_pool_ptr, db->buf_pool_dma_ptr);
1da177e4
LT		 512 pci_release_regions(pdev);
513 free_netdev(dev); /* free board information */
4dc68f3d 514
1da177e4
LT		 515 pci_set_drvdata(pdev, NULL);
516 }
517
518 DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
519}
520
521
522/*
523 * Open the interface.
524 * The interface is opened whenever "ifconfig" actives it.
525 */
526
527static int dmfe_open(struct DEVICE *dev)
528{
529 int ret;
530 struct dmfe_board_info *db = netdev_priv(dev);
531
532 DMFE_DBUG(0, "dmfe_open", 0);
533
f67ba792
ML		 534 ret = request_irq(dev->irq, &dmfe_interrupt,
535 IRQF_SHARED, dev->name, dev);
1da177e4
LT		 536 if (ret)
537 return ret;
538
539 /* system variable init */
540 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
541 db->tx_packet_cnt = 0;
542 db->tx_queue_cnt = 0;
543 db->rx_avail_cnt = 0;
1da177e4
LT		 544 db->wait_reset = 0;
545
546 db->first_in_callback = 0;
547 db->NIC_capability = 0xf; /* All capability*/
548 db->PHY_reg4 = 0x1e0;
549
550 /* CR6 operation mode decision */
551 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
552 (db->chip_revision >= 0x02000030) ) {
553 db->cr6_data |= DMFE_TXTH_256;
554 db->cr0_data = CR0_DEFAULT;
555 db->dm910x_chk_mode=4; /* Enter the normal mode */
556 } else {
557 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
558 db->cr0_data = 0;
559 db->dm910x_chk_mode = 1; /* Enter the check mode */
560 }
561
562 /* Initilize DM910X board */
563 dmfe_init_dm910x(dev);
564
565 /* Active System Interface */
566 netif_wake_queue(dev);
567
568 /* set and active a timer process */
569 init_timer(&db->timer);
570 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
571 db->timer.data = (unsigned long)dev;
572 db->timer.function = &dmfe_timer;
573 add_timer(&db->timer);
574
575 return 0;
576}
577
578
579/* Initilize DM910X board
580 * Reset DM910X board
581 * Initilize TX/Rx descriptor chain structure
582 * Send the set-up frame
583 * Enable Tx/Rx machine
584 */
585
586static void dmfe_init_dm910x(struct DEVICE *dev)
587{
588 struct dmfe_board_info *db = netdev_priv(dev);
589 unsigned long ioaddr = db->ioaddr;
590
591 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
592
593 /* Reset DM910x MAC controller */
594 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
595 udelay(100);
596 outl(db->cr0_data, ioaddr + DCR0);
597 udelay(5);
598
599 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
600 db->phy_addr = 1;
601
602 /* Parser SROM and media mode */
603 dmfe_parse_srom(db);
604 db->media_mode = dmfe_media_mode;
605
606 /* RESET Phyxcer Chip by GPR port bit 7 */
607 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
608 if (db->chip_id == PCI_DM9009_ID) {
609 outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
610 mdelay(300); /* Delay 300 ms */
611 }
612 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
613
614 /* Process Phyxcer Media Mode */
615 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
616 dmfe_set_phyxcer(db);
617
618 /* Media Mode Process */
619 if ( !(db->media_mode & DMFE_AUTO) )
620 db->op_mode = db->media_mode; /* Force Mode */
621
622 /* Initiliaze Transmit/Receive decriptor and CR3/4 */
623 dmfe_descriptor_init(db, ioaddr);
624
625 /* Init CR6 to program DM910x operation */
626 update_cr6(db->cr6_data, ioaddr);
627
628 /* Send setup frame */
629 if (db->chip_id == PCI_DM9132_ID)
630 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
631 else
632 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
633
634 /* Init CR7, interrupt active bit */
635 db->cr7_data = CR7_DEFAULT;
636 outl(db->cr7_data, ioaddr + DCR7);
637
638 /* Init CR15, Tx jabber and Rx watchdog timer */
639 outl(db->cr15_data, ioaddr + DCR15);
640
641 /* Enable DM910X Tx/Rx function */
642 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
643 update_cr6(db->cr6_data, ioaddr);
644}
645
646
647/*
648 * Hardware start transmission.
649 * Send a packet to media from the upper layer.
650 */
651
652static int dmfe_start_xmit(struct sk_buff *skb, struct DEVICE *dev)
653{
654 struct dmfe_board_info *db = netdev_priv(dev);
655 struct tx_desc *txptr;
656 unsigned long flags;
657
658 DMFE_DBUG(0, "dmfe_start_xmit", 0);
659
660 /* Resource flag check */
661 netif_stop_queue(dev);
662
663 /* Too large packet check */
664 if (skb->len > MAX_PACKET_SIZE) {
665 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
666 dev_kfree_skb(skb);
667 return 0;
668 }
669
670 spin_lock_irqsave(&db->lock, flags);
671
672 /* No Tx resource check, it never happen nromally */
673 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
674 spin_unlock_irqrestore(&db->lock, flags);
f67ba792
ML		 675 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n",
676 db->tx_queue_cnt);
1da177e4
LT		 677 return 1;
678 }
679
680 /* Disable NIC interrupt */
681 outl(0, dev->base_addr + DCR7);
682
683 /* transmit this packet */
684 txptr = db->tx_insert_ptr;
685 memcpy(txptr->tx_buf_ptr, skb->data, skb->len);
686 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
687
688 /* Point to next transmit free descriptor */
689 db->tx_insert_ptr = txptr->next_tx_desc;
690
691 /* Transmit Packet Process */
692 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
693 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
694 db->tx_packet_cnt++; /* Ready to send */
695 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
696 dev->trans_start = jiffies; /* saved time stamp */
697 } else {
698 db->tx_queue_cnt++; /* queue TX packet */
699 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
700 }
701
702 /* Tx resource check */
703 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
704 netif_wake_queue(dev);
705
706 /* Restore CR7 to enable interrupt */
707 spin_unlock_irqrestore(&db->lock, flags);
708 outl(db->cr7_data, dev->base_addr + DCR7);
709
710 /* free this SKB */
711 dev_kfree_skb(skb);
712
713 return 0;
714}
715
716
717/*
718 * Stop the interface.
719 * The interface is stopped when it is brought.
720 */
721
722static int dmfe_stop(struct DEVICE *dev)
723{
724 struct dmfe_board_info *db = netdev_priv(dev);
725 unsigned long ioaddr = dev->base_addr;
726
727 DMFE_DBUG(0, "dmfe_stop", 0);
728
729 /* disable system */
730 netif_stop_queue(dev);
731
732 /* deleted timer */
733 del_timer_sync(&db->timer);
734
735 /* Reset & stop DM910X board */
736 outl(DM910X_RESET, ioaddr + DCR0);
737 udelay(5);
738 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
739
740 /* free interrupt */
741 free_irq(dev->irq, dev);
742
743 /* free allocated rx buffer */
744 dmfe_free_rxbuffer(db);
745
746#if 0
747 /* show statistic counter */
f67ba792
ML		 748 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx"
749 " LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
1da177e4
LT		 750 db->tx_fifo_underrun, db->tx_excessive_collision,
751 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
752 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
753 db->reset_fatal, db->reset_TXtimeout);
754#endif
755
756 return 0;
757}
758
759
760/*
761 * DM9102 insterrupt handler
762 * receive the packet to upper layer, free the transmitted packet
763 */
764
7d12e780 765static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
1da177e4
LT		 766{
767 struct DEVICE *dev = dev_id;
768 struct dmfe_board_info *db = netdev_priv(dev);
769 unsigned long ioaddr = dev->base_addr;
770 unsigned long flags;
771
772 DMFE_DBUG(0, "dmfe_interrupt()", 0);
773
1da177e4
LT		 774 spin_lock_irqsave(&db->lock, flags);
775
776 /* Got DM910X status */
777 db->cr5_data = inl(ioaddr + DCR5);
778 outl(db->cr5_data, ioaddr + DCR5);
779 if ( !(db->cr5_data & 0xc1) ) {
780 spin_unlock_irqrestore(&db->lock, flags);
781 return IRQ_HANDLED;
782 }
783
784 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
785 outl(0, ioaddr + DCR7);
786
787 /* Check system status */
788 if (db->cr5_data & 0x2000) {
789 /* system bus error happen */
790 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
791 db->reset_fatal++;
792 db->wait_reset = 1; /* Need to RESET */
793 spin_unlock_irqrestore(&db->lock, flags);
794 return IRQ_HANDLED;
795 }
796
797 /* Received the coming packet */
798 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
799 dmfe_rx_packet(dev, db);
800
801 /* reallocate rx descriptor buffer */
802 if (db->rx_avail_cnt<RX_DESC_CNT)
803 allocate_rx_buffer(db);
804
805 /* Free the transmitted descriptor */
806 if ( db->cr5_data & 0x01)
807 dmfe_free_tx_pkt(dev, db);
808
809 /* Mode Check */
810 if (db->dm910x_chk_mode & 0x2) {
811 db->dm910x_chk_mode = 0x4;
812 db->cr6_data |= 0x100;
813 update_cr6(db->cr6_data, db->ioaddr);
814 }
815
816 /* Restore CR7 to enable interrupt mask */
817 outl(db->cr7_data, ioaddr + DCR7);
818
819 spin_unlock_irqrestore(&db->lock, flags);
820 return IRQ_HANDLED;
821}
822
823
824#ifdef CONFIG_NET_POLL_CONTROLLER
825/*
826 * Polling 'interrupt' - used by things like netconsole to send skbs
827 * without having to re-enable interrupts. It's not called while
828 * the interrupt routine is executing.
829 */
830
831static void poll_dmfe (struct net_device *dev)
832{
833 /* disable_irq here is not very nice, but with the lockless
834 interrupt handler we have no other choice. */
835 disable_irq(dev->irq);
7d12e780 836 dmfe_interrupt (dev->irq, dev);
1da177e4
LT		 837 enable_irq(dev->irq);
838}
839#endif
840
841/*
842 * Free TX resource after TX complete
843 */
844
845static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
846{
847 struct tx_desc *txptr;
848 unsigned long ioaddr = dev->base_addr;
849 u32 tdes0;
850
851 txptr = db->tx_remove_ptr;
852 while(db->tx_packet_cnt) {
853 tdes0 = le32_to_cpu(txptr->tdes0);
854 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
855 if (tdes0 & 0x80000000)
856 break;
857
858 /* A packet sent completed */
859 db->tx_packet_cnt--;
860 db->stats.tx_packets++;
861
862 /* Transmit statistic counter */
863 if ( tdes0 != 0x7fffffff ) {
864 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
865 db->stats.collisions += (tdes0 >> 3) & 0xf;
866 db->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
867 if (tdes0 & TDES0_ERR_MASK) {
868 db->stats.tx_errors++;
869
870 if (tdes0 & 0x0002) { /* UnderRun */
871 db->tx_fifo_underrun++;
872 if ( !(db->cr6_data & CR6_SFT) ) {
873 db->cr6_data = db->cr6_data | CR6_SFT;
874 update_cr6(db->cr6_data, db->ioaddr);
875 }
876 }
877 if (tdes0 & 0x0100)
878 db->tx_excessive_collision++;
879 if (tdes0 & 0x0200)
880 db->tx_late_collision++;
881 if (tdes0 & 0x0400)
882 db->tx_no_carrier++;
883 if (tdes0 & 0x0800)
884 db->tx_loss_carrier++;
885 if (tdes0 & 0x4000)
886 db->tx_jabber_timeout++;
887 }
888 }
889
890 txptr = txptr->next_tx_desc;
891 }/* End of while */
892
893 /* Update TX remove pointer to next */
894 db->tx_remove_ptr = txptr;
895
896 /* Send the Tx packet in queue */
897 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
898 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
899 db->tx_packet_cnt++; /* Ready to send */
900 db->tx_queue_cnt--;
901 outl(0x1, ioaddr + DCR1); /* Issue Tx polling */
902 dev->trans_start = jiffies; /* saved time stamp */
903 }
904
905 /* Resource available check */
906 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
907 netif_wake_queue(dev); /* Active upper layer, send again */
908}
909
910
911/*
912 * Calculate the CRC valude of the Rx packet
913 * flag = 1 : return the reverse CRC (for the received packet CRC)
914 * 0 : return the normal CRC (for Hash Table index)
915 */
916
917static inline u32 cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
918{
919 u32 crc = crc32(~0, Data, Len);
920 if (flag) crc = ~crc;
921 return crc;
922}
923
924
925/*
926 * Receive the come packet and pass to upper layer
927 */
928
929static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
930{
931 struct rx_desc *rxptr;
4dc68f3d 932 struct sk_buff *skb, *newskb;
1da177e4
LT		 933 int rxlen;
934 u32 rdes0;
935
936 rxptr = db->rx_ready_ptr;
937
938 while(db->rx_avail_cnt) {
939 rdes0 = le32_to_cpu(rxptr->rdes0);
940 if (rdes0 & 0x80000000) /* packet owner check */
941 break;
942
943 db->rx_avail_cnt--;
944 db->interval_rx_cnt++;
945
f67ba792
ML		 946 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2),
947 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
948
1da177e4
LT		 949 if ( (rdes0 & 0x300) != 0x300) {
950 /* A packet without First/Last flag */
951 /* reuse this SKB */
952 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
953 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
954 } else {
955 /* A packet with First/Last flag */
956 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
957
958 /* error summary bit check */
959 if (rdes0 & 0x8000) {
960 /* This is a error packet */
961 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
962 db->stats.rx_errors++;
963 if (rdes0 & 1)
964 db->stats.rx_fifo_errors++;
965 if (rdes0 & 2)
966 db->stats.rx_crc_errors++;
967 if (rdes0 & 0x80)
968 db->stats.rx_length_errors++;
969 }
970
971 if ( !(rdes0 & 0x8000) ||
972 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
973 skb = rxptr->rx_skb_ptr;
974
975 /* Received Packet CRC check need or not */
976 if ( (db->dm910x_chk_mode & 1) &&
689be439
DM		 977 (cal_CRC(skb->data, rxlen, 1) !=
978 (*(u32 *) (skb->data+rxlen) ))) { /* FIXME (?) */
1da177e4
LT		 979 /* Found a error received packet */
980 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
981 db->dm910x_chk_mode = 3;
982 } else {
983 /* Good packet, send to upper layer */
984 /* Shorst packet used new SKB */
4dc68f3d
ML		 985 if ((rxlen < RX_COPY_SIZE) &&
986 ((newskb = dev_alloc_skb(rxlen + 2))
987 != NULL)) {
988
989 skb = newskb;
1da177e4 990 /* size less than COPY_SIZE, allocate a rxlen SKB */
1da177e4 991 skb_reserve(skb, 2); /* 16byte align */
689be439 992 memcpy(skb_put(skb, rxlen), rxptr->rx_skb_ptr->data, rxlen);
1da177e4 993 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
4c13eb66 994 } else
1da177e4 995 skb_put(skb, rxlen);
4c13eb66 996
1da177e4
LT		 997 skb->protocol = eth_type_trans(skb, dev);
998 netif_rx(skb);
999 dev->last_rx = jiffies;
1000 db->stats.rx_packets++;
1001 db->stats.rx_bytes += rxlen;
1002 }
1003 } else {
1004 /* Reuse SKB buffer when the packet is error */
1005 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
1006 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1007 }
1008 }
1009
1010 rxptr = rxptr->next_rx_desc;
1011 }
1012
1013 db->rx_ready_ptr = rxptr;
1014}
1015
1016
1017/*
1018 * Get statistics from driver.
1019 */
1020
1021static struct net_device_stats * dmfe_get_stats(struct DEVICE *dev)
1022{
1023 struct dmfe_board_info *db = netdev_priv(dev);
1024
1025 DMFE_DBUG(0, "dmfe_get_stats", 0);
1026 return &db->stats;
1027}
1028
1029
1030/*
1031 * Set DM910X multicast address
1032 */
1033
1034static void dmfe_set_filter_mode(struct DEVICE * dev)
1035{
1036 struct dmfe_board_info *db = netdev_priv(dev);
1037 unsigned long flags;
1038
1039 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
1040 spin_lock_irqsave(&db->lock, flags);
1041
1042 if (dev->flags & IFF_PROMISC) {
1043 DMFE_DBUG(0, "Enable PROM Mode", 0);
1044 db->cr6_data |= CR6_PM | CR6_PBF;
1045 update_cr6(db->cr6_data, db->ioaddr);
1046 spin_unlock_irqrestore(&db->lock, flags);
1047 return;
1048 }
1049
1050 if (dev->flags & IFF_ALLMULTI || dev->mc_count > DMFE_MAX_MULTICAST) {
1051 DMFE_DBUG(0, "Pass all multicast address", dev->mc_count);
1052 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1053 db->cr6_data |= CR6_PAM;
1054 spin_unlock_irqrestore(&db->lock, flags);
1055 return;
1056 }
1057
1058 DMFE_DBUG(0, "Set multicast address", dev->mc_count);
1059 if (db->chip_id == PCI_DM9132_ID)
1060 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
1061 else
1062 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
1063 spin_unlock_irqrestore(&db->lock, flags);
1064}
1065
1066static void netdev_get_drvinfo(struct net_device *dev,
1067 struct ethtool_drvinfo *info)
1068{
1069 struct dmfe_board_info *np = netdev_priv(dev);
1070
1071 strcpy(info->driver, DRV_NAME);
1072 strcpy(info->version, DRV_VERSION);
1073 if (np->pdev)
1074 strcpy(info->bus_info, pci_name(np->pdev));
1075 else
1076 sprintf(info->bus_info, "EISA 0x%lx %d",
1077 dev->base_addr, dev->irq);
1078}
1079
7282d491 1080static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4 1081 .get_drvinfo = netdev_get_drvinfo,
cfa51b9d 1082 .get_link = ethtool_op_get_link,
1da177e4
LT		 1083};
1084
1085/*
1086 * A periodic timer routine
1087 * Dynamic media sense, allocate Rx buffer...
1088 */
1089
1090static void dmfe_timer(unsigned long data)
1091{
1092 u32 tmp_cr8;
1093 unsigned char tmp_cr12;
1094 struct DEVICE *dev = (struct DEVICE *) data;
1095 struct dmfe_board_info *db = netdev_priv(dev);
1096 unsigned long flags;
1097
cfa51b9d
ML		 1098 int link_ok, link_ok_phy;
1099
1da177e4
LT		 1100 DMFE_DBUG(0, "dmfe_timer()", 0);
1101 spin_lock_irqsave(&db->lock, flags);
1102
1103 /* Media mode process when Link OK before enter this route */
1104 if (db->first_in_callback == 0) {
1105 db->first_in_callback = 1;
1106 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1107 db->cr6_data &= ~0x40000;
1108 update_cr6(db->cr6_data, db->ioaddr);
f67ba792
ML		 1109 phy_write(db->ioaddr,
1110 db->phy_addr, 0, 0x1000, db->chip_id);
1da177e4
LT		 1111 db->cr6_data |= 0x40000;
1112 update_cr6(db->cr6_data, db->ioaddr);
1113 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1114 add_timer(&db->timer);
1115 spin_unlock_irqrestore(&db->lock, flags);
1116 return;
1117 }
1118 }
1119
1120
1121 /* Operating Mode Check */
1122 if ( (db->dm910x_chk_mode & 0x1) &&
1123 (db->stats.rx_packets > MAX_CHECK_PACKET) )
1124 db->dm910x_chk_mode = 0x4;
1125
1126 /* Dynamic reset DM910X : system error or transmit time-out */
1127 tmp_cr8 = inl(db->ioaddr + DCR8);
1128 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1129 db->reset_cr8++;
1130 db->wait_reset = 1;
1131 }
1132 db->interval_rx_cnt = 0;
1133
1134 /* TX polling kick monitor */
1135 if ( db->tx_packet_cnt &&
1136 time_after(jiffies, dev->trans_start + DMFE_TX_KICK) ) {
1137 outl(0x1, dev->base_addr + DCR1); /* Tx polling again */
1138
1139 /* TX Timeout */
1140 if ( time_after(jiffies, dev->trans_start + DMFE_TX_TIMEOUT) ) {
1141 db->reset_TXtimeout++;
1142 db->wait_reset = 1;
1143 printk(KERN_WARNING "%s: Tx timeout - resetting\n",
1144 dev->name);
1145 }
1146 }
1147
1148 if (db->wait_reset) {
1149 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1150 db->reset_count++;
1151 dmfe_dynamic_reset(dev);
1152 db->first_in_callback = 0;
1153 db->timer.expires = DMFE_TIMER_WUT;
1154 add_timer(&db->timer);
1155 spin_unlock_irqrestore(&db->lock, flags);
1156 return;
1157 }
1158
1159 /* Link status check, Dynamic media type change */
1160 if (db->chip_id == PCI_DM9132_ID)
1161 tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */
1162 else
1163 tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
1164
1165 if ( ((db->chip_id == PCI_DM9102_ID) &&
1166 (db->chip_revision == 0x02000030)) ||
1167 ((db->chip_id == PCI_DM9132_ID) &&
1168 (db->chip_revision == 0x02000010)) ) {
1169 /* DM9102A Chip */
1170 if (tmp_cr12 & 2)
cfa51b9d 1171 link_ok = 0;
1da177e4 1172 else
cfa51b9d 1173 link_ok = 1;
1da177e4 1174 }
cfa51b9d
ML		 1175 else
1176 /*0x43 is used instead of 0x3 because bit 6 should represent
1177 link status of external PHY */
1178 link_ok = (tmp_cr12 & 0x43) ? 1 : 0;
1179
1180
1181 /* If chip reports that link is failed it could be because external
1182 PHY link status pin is not conected correctly to chip
1183 To be sure ask PHY too.
1184 */
1185
1186 /* need a dummy read because of PHY's register latch*/
1187 phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
1188 link_ok_phy = (phy_read (db->ioaddr,
1189 db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
1da177e4 1190
cfa51b9d
ML		 1191 if (link_ok_phy != link_ok) {
1192 DMFE_DBUG (0, "PHY and chip report different link status", 0);
1193 link_ok = link_ok | link_ok_phy;
1194 }
1195
1196 if ( !link_ok && netif_carrier_ok(dev)) {
1da177e4
LT		 1197 /* Link Failed */
1198 DMFE_DBUG(0, "Link Failed", tmp_cr12);
cfa51b9d 1199 netif_carrier_off(dev);
1da177e4
LT		 1200
1201 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1202 /* AUTO or force 1M Homerun/Longrun don't need */
1203 if ( !(db->media_mode & 0x38) )
f67ba792
ML		 1204 phy_write(db->ioaddr, db->phy_addr,
1205 0, 0x1000, db->chip_id);
1da177e4
LT		 1206
1207 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1208 if (db->media_mode & DMFE_AUTO) {
1209 /* 10/100M link failed, used 1M Home-Net */
1210 db->cr6_data|=0x00040000; /* bit18=1, MII */
1211 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1212 update_cr6(db->cr6_data, db->ioaddr);
1213 }
cfa51b9d
ML		 1214 } else if (!netif_carrier_ok(dev)) {
1215
1216 DMFE_DBUG(0, "Link link OK", tmp_cr12);
1217
1218 /* Auto Sense Speed */
1219 if ( !(db->media_mode & DMFE_AUTO) || !dmfe_sense_speed(db)) {
1220 netif_carrier_on(dev);
1221 SHOW_MEDIA_TYPE(db->op_mode);
1da177e4
LT		 1222 }
1223
cfa51b9d
ML		 1224 dmfe_process_mode(db);
1225 }
1226
1da177e4
LT		 1227 /* HPNA remote command check */
1228 if (db->HPNA_command & 0xf00) {
1229 db->HPNA_timer--;
1230 if (!db->HPNA_timer)
1231 dmfe_HPNA_remote_cmd_chk(db);
1232 }
1233
1234 /* Timer active again */
1235 db->timer.expires = DMFE_TIMER_WUT;
1236 add_timer(&db->timer);
1237 spin_unlock_irqrestore(&db->lock, flags);
1238}
1239
1240
1241/*
1242 * Dynamic reset the DM910X board
1243 * Stop DM910X board
1244 * Free Tx/Rx allocated memory
1245 * Reset DM910X board
1246 * Re-initilize DM910X board
1247 */
1248
1249static void dmfe_dynamic_reset(struct DEVICE *dev)
1250{
1251 struct dmfe_board_info *db = netdev_priv(dev);
1252
1253 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1254
1255 /* Sopt MAC controller */
1256 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1257 update_cr6(db->cr6_data, dev->base_addr);
1258 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1259 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1260
1261 /* Disable upper layer interface */
1262 netif_stop_queue(dev);
1263
1264 /* Free Rx Allocate buffer */
1265 dmfe_free_rxbuffer(db);
1266
1267 /* system variable init */
1268 db->tx_packet_cnt = 0;
1269 db->tx_queue_cnt = 0;
1270 db->rx_avail_cnt = 0;
cfa51b9d 1271 netif_carrier_off(dev);
1da177e4
LT		 1272 db->wait_reset = 0;
1273
1274 /* Re-initilize DM910X board */
1275 dmfe_init_dm910x(dev);
1276
1277 /* Restart upper layer interface */
1278 netif_wake_queue(dev);
1279}
1280
1281
1282/*
1283 * free all allocated rx buffer
1284 */
1285
1286static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1287{
1288 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
1289
1290 /* free allocated rx buffer */
1291 while (db->rx_avail_cnt) {
1292 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1293 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1294 db->rx_avail_cnt--;
1295 }
1296}
1297
1298
1299/*
1300 * Reuse the SK buffer
1301 */
1302
1303static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1304{
1305 struct rx_desc *rxptr = db->rx_insert_ptr;
1306
1307 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1308 rxptr->rx_skb_ptr = skb;
f67ba792
ML		 1309 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev,
1310 skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1da177e4
LT		 1311 wmb();
1312 rxptr->rdes0 = cpu_to_le32(0x80000000);
1313 db->rx_avail_cnt++;
1314 db->rx_insert_ptr = rxptr->next_rx_desc;
1315 } else
1316 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1317}
1318
1319
1320/*
1321 * Initialize transmit/Receive descriptor
1322 * Using Chain structure, and allocate Tx/Rx buffer
1323 */
1324
1325static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioaddr)
1326{
1327 struct tx_desc *tmp_tx;
1328 struct rx_desc *tmp_rx;
1329 unsigned char *tmp_buf;
1330 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1331 dma_addr_t tmp_buf_dma;
1332 int i;
1333
1334 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1335
1336 /* tx descriptor start pointer */
1337 db->tx_insert_ptr = db->first_tx_desc;
1338 db->tx_remove_ptr = db->first_tx_desc;
1339 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1340
1341 /* rx descriptor start pointer */
f67ba792
ML		 1342 db->first_rx_desc = (void *)db->first_tx_desc +
1343 sizeof(struct tx_desc) * TX_DESC_CNT;
1344
1345 db->first_rx_desc_dma = db->first_tx_desc_dma +
1346 sizeof(struct tx_desc) * TX_DESC_CNT;
1da177e4
LT		 1347 db->rx_insert_ptr = db->first_rx_desc;
1348 db->rx_ready_ptr = db->first_rx_desc;
1349 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1350
1351 /* Init Transmit chain */
1352 tmp_buf = db->buf_pool_start;
1353 tmp_buf_dma = db->buf_pool_dma_start;
1354 tmp_tx_dma = db->first_tx_desc_dma;
1355 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1356 tmp_tx->tx_buf_ptr = tmp_buf;
1357 tmp_tx->tdes0 = cpu_to_le32(0);
1358 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1359 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1360 tmp_tx_dma += sizeof(struct tx_desc);
1361 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1362 tmp_tx->next_tx_desc = tmp_tx + 1;
1363 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1364 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1365 }
1366 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1367 tmp_tx->next_tx_desc = db->first_tx_desc;
1368
1369 /* Init Receive descriptor chain */
1370 tmp_rx_dma=db->first_rx_desc_dma;
1371 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1372 tmp_rx->rdes0 = cpu_to_le32(0);
1373 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1374 tmp_rx_dma += sizeof(struct rx_desc);
1375 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1376 tmp_rx->next_rx_desc = tmp_rx + 1;
1377 }
1378 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1379 tmp_rx->next_rx_desc = db->first_rx_desc;
1380
1381 /* pre-allocate Rx buffer */
1382 allocate_rx_buffer(db);
1383}
1384
1385
1386/*
1387 * Update CR6 value
1388 * Firstly stop DM910X , then written value and start
1389 */
1390
1391static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1392{
1393 u32 cr6_tmp;
1394
1395 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1396 outl(cr6_tmp, ioaddr + DCR6);
1397 udelay(5);
1398 outl(cr6_data, ioaddr + DCR6);
1399 udelay(5);
1400}
1401
1402
1403/*
1404 * Send a setup frame for DM9132
1405 * This setup frame initilize DM910X address filter mode
1406*/
1407
1408static void dm9132_id_table(struct DEVICE *dev, int mc_cnt)
1409{
1410 struct dev_mc_list *mcptr;
1411 u16 * addrptr;
1412 unsigned long ioaddr = dev->base_addr+0xc0; /* ID Table */
1413 u32 hash_val;
1414 u16 i, hash_table[4];
1415
1416 DMFE_DBUG(0, "dm9132_id_table()", 0);
1417
1418 /* Node address */
1419 addrptr = (u16 *) dev->dev_addr;
1420 outw(addrptr[0], ioaddr);
1421 ioaddr += 4;
1422 outw(addrptr[1], ioaddr);
1423 ioaddr += 4;
1424 outw(addrptr[2], ioaddr);
1425 ioaddr += 4;
1426
1427 /* Clear Hash Table */
1428 for (i = 0; i < 4; i++)
1429 hash_table[i] = 0x0;
1430
1431 /* broadcast address */
1432 hash_table[3] = 0x8000;
1433
1434 /* the multicast address in Hash Table : 64 bits */
1435 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1436 hash_val = cal_CRC( (char *) mcptr->dmi_addr, 6, 0) & 0x3f;
1437 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1438 }
1439
1440 /* Write the hash table to MAC MD table */
1441 for (i = 0; i < 4; i++, ioaddr += 4)
1442 outw(hash_table[i], ioaddr);
1443}
1444
1445
1446/*
1447 * Send a setup frame for DM9102/DM9102A
1448 * This setup frame initilize DM910X address filter mode
1449 */
1450
1451static void send_filter_frame(struct DEVICE *dev, int mc_cnt)
1452{
1453 struct dmfe_board_info *db = netdev_priv(dev);
1454 struct dev_mc_list *mcptr;
1455 struct tx_desc *txptr;
1456 u16 * addrptr;
1457 u32 * suptr;
1458 int i;
1459
1460 DMFE_DBUG(0, "send_filter_frame()", 0);
1461
1462 txptr = db->tx_insert_ptr;
1463 suptr = (u32 *) txptr->tx_buf_ptr;
1464
1465 /* Node address */
1466 addrptr = (u16 *) dev->dev_addr;
1467 *suptr++ = addrptr[0];
1468 *suptr++ = addrptr[1];
1469 *suptr++ = addrptr[2];
1470
1471 /* broadcast address */
1472 *suptr++ = 0xffff;
1473 *suptr++ = 0xffff;
1474 *suptr++ = 0xffff;
1475
1476 /* fit the multicast address */
1477 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1478 addrptr = (u16 *) mcptr->dmi_addr;
1479 *suptr++ = addrptr[0];
1480 *suptr++ = addrptr[1];
1481 *suptr++ = addrptr[2];
1482 }
1483
1484 for (; i<14; i++) {
1485 *suptr++ = 0xffff;
1486 *suptr++ = 0xffff;
1487 *suptr++ = 0xffff;
1488 }
1489
1490 /* prepare the setup frame */
1491 db->tx_insert_ptr = txptr->next_tx_desc;
1492 txptr->tdes1 = cpu_to_le32(0x890000c0);
1493
1494 /* Resource Check and Send the setup packet */
1495 if (!db->tx_packet_cnt) {
1496 /* Resource Empty */
1497 db->tx_packet_cnt++;
1498 txptr->tdes0 = cpu_to_le32(0x80000000);
1499 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1500 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1501 update_cr6(db->cr6_data, dev->base_addr);
1502 dev->trans_start = jiffies;
1503 } else
1504 db->tx_queue_cnt++; /* Put in TX queue */
1505}
1506
1507
1508/*
1509 * Allocate rx buffer,
1510 * As possible as allocate maxiumn Rx buffer
1511 */
1512
1513static void allocate_rx_buffer(struct dmfe_board_info *db)
1514{
1515 struct rx_desc *rxptr;
1516 struct sk_buff *skb;
1517
1518 rxptr = db->rx_insert_ptr;
1519
1520 while(db->rx_avail_cnt < RX_DESC_CNT) {
1521 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1522 break;
1523 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
f67ba792
ML		 1524 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data,
1525 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1da177e4
LT		 1526 wmb();
1527 rxptr->rdes0 = cpu_to_le32(0x80000000);
1528 rxptr = rxptr->next_rx_desc;
1529 db->rx_avail_cnt++;
1530 }
1531
1532 db->rx_insert_ptr = rxptr;
1533}
1534
1535
1536/*
1537 * Read one word data from the serial ROM
1538 */
1539
1540static u16 read_srom_word(long ioaddr, int offset)
1541{
1542 int i;
1543 u16 srom_data = 0;
1544 long cr9_ioaddr = ioaddr + DCR9;
1545
1546 outl(CR9_SROM_READ, cr9_ioaddr);
1547 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1548
1549 /* Send the Read Command 110b */
1550 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1551 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1552 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1553
1554 /* Send the offset */
1555 for (i = 5; i >= 0; i--) {
1556 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1557 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1558 }
1559
1560 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1561
1562 for (i = 16; i > 0; i--) {
1563 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1564 udelay(5);
f67ba792
ML		 1565 srom_data = (srom_data << 1) |
1566 ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1da177e4
LT		 1567 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1568 udelay(5);
1569 }
1570
1571 outl(CR9_SROM_READ, cr9_ioaddr);
1572 return srom_data;
1573}
1574
1575
1576/*
1577 * Auto sense the media mode
1578 */
1579
1580static u8 dmfe_sense_speed(struct dmfe_board_info * db)
1581{
1582 u8 ErrFlag = 0;
1583 u16 phy_mode;
1584
1585 /* CR6 bit18=0, select 10/100M */
1586 update_cr6( (db->cr6_data & ~0x40000), db->ioaddr);
1587
1588 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1589 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1590
1591 if ( (phy_mode & 0x24) == 0x24 ) {
1592 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
f67ba792
ML		 1593 phy_mode = phy_read(db->ioaddr,
1594 db->phy_addr, 7, db->chip_id) & 0xf000;
1da177e4 1595 else /* DM9102/DM9102A */
f67ba792
ML		 1596 phy_mode = phy_read(db->ioaddr,
1597 db->phy_addr, 17, db->chip_id) & 0xf000;
1da177e4
LT		 1598 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1599 switch (phy_mode) {
1600 case 0x1000: db->op_mode = DMFE_10MHF; break;
1601 case 0x2000: db->op_mode = DMFE_10MFD; break;
1602 case 0x4000: db->op_mode = DMFE_100MHF; break;
1603 case 0x8000: db->op_mode = DMFE_100MFD; break;
1604 default: db->op_mode = DMFE_10MHF;
1605 ErrFlag = 1;
1606 break;
1607 }
1608 } else {
1609 db->op_mode = DMFE_10MHF;
1610 DMFE_DBUG(0, "Link Failed :", phy_mode);
1611 ErrFlag = 1;
1612 }
1613
1614 return ErrFlag;
1615}
1616
1617
1618/*
1619 * Set 10/100 phyxcer capability
1620 * AUTO mode : phyxcer register4 is NIC capability
1621 * Force mode: phyxcer register4 is the force media
1622 */
1623
1624static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1625{
1626 u16 phy_reg;
1627
1628 /* Select 10/100M phyxcer */
1629 db->cr6_data &= ~0x40000;
1630 update_cr6(db->cr6_data, db->ioaddr);
1631
1632 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1633 if (db->chip_id == PCI_DM9009_ID) {
f67ba792
ML		 1634 phy_reg = phy_read(db->ioaddr,
1635 db->phy_addr, 18, db->chip_id) & ~0x1000;
1636
1637 phy_write(db->ioaddr,
1638 db->phy_addr, 18, phy_reg, db->chip_id);
1da177e4
LT		 1639 }
1640
1641 /* Phyxcer capability setting */
1642 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1643
1644 if (db->media_mode & DMFE_AUTO) {
1645 /* AUTO Mode */
1646 phy_reg |= db->PHY_reg4;
1647 } else {
1648 /* Force Mode */
1649 switch(db->media_mode) {
1650 case DMFE_10MHF: phy_reg |= 0x20; break;
1651 case DMFE_10MFD: phy_reg |= 0x40; break;
1652 case DMFE_100MHF: phy_reg |= 0x80; break;
1653 case DMFE_100MFD: phy_reg |= 0x100; break;
1654 }
1655 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1656 }
1657
1658 /* Write new capability to Phyxcer Reg4 */
1659 if ( !(phy_reg & 0x01e0)) {
1660 phy_reg|=db->PHY_reg4;
1661 db->media_mode|=DMFE_AUTO;
1662 }
1663 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1664
1665 /* Restart Auto-Negotiation */
1666 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1667 phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1668 if ( !db->chip_type )
1669 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1670}
1671
1672
1673/*
1674 * Process op-mode
1675 * AUTO mode : PHY controller in Auto-negotiation Mode
1676 * Force mode: PHY controller in force mode with HUB
1677 * N-way force capability with SWITCH
1678 */
1679
1680static void dmfe_process_mode(struct dmfe_board_info *db)
1681{
1682 u16 phy_reg;
1683
1684 /* Full Duplex Mode Check */
1685 if (db->op_mode & 0x4)
1686 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1687 else
1688 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1689
1690 /* Transciver Selection */
1691 if (db->op_mode & 0x10) /* 1M HomePNA */
1692 db->cr6_data |= 0x40000;/* External MII select */
1693 else
1694 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1695
1696 update_cr6(db->cr6_data, db->ioaddr);
1697
1698 /* 10/100M phyxcer force mode need */
1699 if ( !(db->media_mode & 0x18)) {
1700 /* Forece Mode */
1701 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1702 if ( !(phy_reg & 0x1) ) {
1703 /* parter without N-Way capability */
1704 phy_reg = 0x0;
1705 switch(db->op_mode) {
1706 case DMFE_10MHF: phy_reg = 0x0; break;
1707 case DMFE_10MFD: phy_reg = 0x100; break;
1708 case DMFE_100MHF: phy_reg = 0x2000; break;
1709 case DMFE_100MFD: phy_reg = 0x2100; break;
1710 }
f67ba792
ML		 1711 phy_write(db->ioaddr,
1712 db->phy_addr, 0, phy_reg, db->chip_id);
1da177e4
LT		 1713 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1714 mdelay(20);
f67ba792
ML		 1715 phy_write(db->ioaddr,
1716 db->phy_addr, 0, phy_reg, db->chip_id);
1da177e4
LT		 1717 }
1718 }
1719}
1720
1721
1722/*
1723 * Write a word to Phy register
1724 */
1725
f67ba792
ML		 1726static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
1727 u16 phy_data, u32 chip_id)
1da177e4
LT		 1728{
1729 u16 i;
1730 unsigned long ioaddr;
1731
1732 if (chip_id == PCI_DM9132_ID) {
1733 ioaddr = iobase + 0x80 + offset * 4;
1734 outw(phy_data, ioaddr);
1735 } else {
1736 /* DM9102/DM9102A Chip */
1737 ioaddr = iobase + DCR9;
1738
1739 /* Send 33 synchronization clock to Phy controller */
1740 for (i = 0; i < 35; i++)
1741 phy_write_1bit(ioaddr, PHY_DATA_1);
1742
1743 /* Send start command(01) to Phy */
1744 phy_write_1bit(ioaddr, PHY_DATA_0);
1745 phy_write_1bit(ioaddr, PHY_DATA_1);
1746
1747 /* Send write command(01) to Phy */
1748 phy_write_1bit(ioaddr, PHY_DATA_0);
1749 phy_write_1bit(ioaddr, PHY_DATA_1);
1750
1751 /* Send Phy address */
1752 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1753 phy_write_1bit(ioaddr,
1754 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1755
1756 /* Send register address */
1757 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1758 phy_write_1bit(ioaddr,
1759 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1760
1761 /* written trasnition */
1762 phy_write_1bit(ioaddr, PHY_DATA_1);
1763 phy_write_1bit(ioaddr, PHY_DATA_0);
1764
1765 /* Write a word data to PHY controller */
1766 for ( i = 0x8000; i > 0; i >>= 1)
f67ba792
ML		 1767 phy_write_1bit(ioaddr,
1768 phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1769 }
1770}
1771
1772
1773/*
1774 * Read a word data from phy register
1775 */
1776
1777static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1778{
1779 int i;
1780 u16 phy_data;
1781 unsigned long ioaddr;
1782
1783 if (chip_id == PCI_DM9132_ID) {
1784 /* DM9132 Chip */
1785 ioaddr = iobase + 0x80 + offset * 4;
1786 phy_data = inw(ioaddr);
1787 } else {
1788 /* DM9102/DM9102A Chip */
1789 ioaddr = iobase + DCR9;
1790
1791 /* Send 33 synchronization clock to Phy controller */
1792 for (i = 0; i < 35; i++)
1793 phy_write_1bit(ioaddr, PHY_DATA_1);
1794
1795 /* Send start command(01) to Phy */
1796 phy_write_1bit(ioaddr, PHY_DATA_0);
1797 phy_write_1bit(ioaddr, PHY_DATA_1);
1798
1799 /* Send read command(10) to Phy */
1800 phy_write_1bit(ioaddr, PHY_DATA_1);
1801 phy_write_1bit(ioaddr, PHY_DATA_0);
1802
1803 /* Send Phy address */
1804 for (i = 0x10; i > 0; i = i >> 1)
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ML		 1805 phy_write_1bit(ioaddr,
1806 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1807
1808 /* Send register address */
1809 for (i = 0x10; i > 0; i = i >> 1)
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ML		 1810 phy_write_1bit(ioaddr,
1811 offset & i ? PHY_DATA_1 : PHY_DATA_0);
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LT		 1812
1813 /* Skip transition state */
1814 phy_read_1bit(ioaddr);
1815
1816 /* read 16bit data */
1817 for (phy_data = 0, i = 0; i < 16; i++) {
1818 phy_data <<= 1;
1819 phy_data |= phy_read_1bit(ioaddr);
1820 }
1821 }
1822
1823 return phy_data;
1824}
1825
1826
1827/*
1828 * Write one bit data to Phy Controller
1829 */
1830
1831static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
1832{
1833 outl(phy_data, ioaddr); /* MII Clock Low */
1834 udelay(1);
1835 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1836 udelay(1);
1837 outl(phy_data, ioaddr); /* MII Clock Low */
1838 udelay(1);
1839}
1840
1841
1842/*
1843 * Read one bit phy data from PHY controller
1844 */
1845
1846static u16 phy_read_1bit(unsigned long ioaddr)
1847{
1848 u16 phy_data;
1849
1850 outl(0x50000, ioaddr);
1851 udelay(1);
1852 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1853 outl(0x40000, ioaddr);
1854 udelay(1);
1855
1856 return phy_data;
1857}
1858
1859
1860/*
1861 * Parser SROM and media mode
1862 */
1863
1864static void dmfe_parse_srom(struct dmfe_board_info * db)
1865{
1866 char * srom = db->srom;
1867 int dmfe_mode, tmp_reg;
1868
1869 DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
1870
1871 /* Init CR15 */
1872 db->cr15_data = CR15_DEFAULT;
1873
1874 /* Check SROM Version */
1875 if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
1876 /* SROM V4.01 */
1877 /* Get NIC support media mode */
16b110c3 1878 db->NIC_capability = le16_to_cpup((__le16 *)srom + 34/2);
1da177e4
LT		 1879 db->PHY_reg4 = 0;
1880 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1881 switch( db->NIC_capability & tmp_reg ) {
1882 case 0x1: db->PHY_reg4 |= 0x0020; break;
1883 case 0x2: db->PHY_reg4 |= 0x0040; break;
1884 case 0x4: db->PHY_reg4 |= 0x0080; break;
1885 case 0x8: db->PHY_reg4 |= 0x0100; break;
1886 }
1887 }
1888
1889 /* Media Mode Force or not check */
16b110c3
AM		 1890 dmfe_mode = le32_to_cpup((__le32 *)srom + 34/4) &
1891 le32_to_cpup((__le32 *)srom + 36/4);
1da177e4
LT		 1892 switch(dmfe_mode) {
1893 case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
1894 case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
1895 case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
1896 case 0x100:
1897 case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
1898 }
1899
1900 /* Special Function setting */
1901 /* VLAN function */
1902 if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
1903 db->cr15_data |= 0x40;
1904
1905 /* Flow Control */
1906 if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
1907 db->cr15_data |= 0x400;
1908
1909 /* TX pause packet */
1910 if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
1911 db->cr15_data |= 0x9800;
1912 }
1913
1914 /* Parse HPNA parameter */
1915 db->HPNA_command = 1;
1916
1917 /* Accept remote command or not */
1918 if (HPNA_rx_cmd == 0)
1919 db->HPNA_command |= 0x8000;
1920
1921 /* Issue remote command & operation mode */
1922 if (HPNA_tx_cmd == 1)
1923 switch(HPNA_mode) { /* Issue Remote Command */
1924 case 0: db->HPNA_command |= 0x0904; break;
1925 case 1: db->HPNA_command |= 0x0a00; break;
1926 case 2: db->HPNA_command |= 0x0506; break;
1927 case 3: db->HPNA_command |= 0x0602; break;
1928 }
1929 else
1930 switch(HPNA_mode) { /* Don't Issue */
1931 case 0: db->HPNA_command |= 0x0004; break;
1932 case 1: db->HPNA_command |= 0x0000; break;
1933 case 2: db->HPNA_command |= 0x0006; break;
1934 case 3: db->HPNA_command |= 0x0002; break;
1935 }
1936
1937 /* Check DM9801 or DM9802 present or not */
1938 db->HPNA_present = 0;
1939 update_cr6(db->cr6_data|0x40000, db->ioaddr);
1940 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1941 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
1942 /* DM9801 or DM9802 present */
1943 db->HPNA_timer = 8;
1944 if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
1945 /* DM9801 HomeRun */
1946 db->HPNA_present = 1;
1947 dmfe_program_DM9801(db, tmp_reg);
1948 } else {
1949 /* DM9802 LongRun */
1950 db->HPNA_present = 2;
1951 dmfe_program_DM9802(db);
1952 }
1953 }
1954
1955}
1956
1957
1958/*
1959 * Init HomeRun DM9801
1960 */
1961
1962static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
1963{
1964 uint reg17, reg25;
1965
1966 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
1967 switch(HPNA_rev) {
1968 case 0xb900: /* DM9801 E3 */
1969 db->HPNA_command |= 0x1000;
1970 reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
1971 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
1972 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1973 break;
1974 case 0xb901: /* DM9801 E4 */
1975 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
1976 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
1977 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1978 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
1979 break;
1980 case 0xb902: /* DM9801 E5 */
1981 case 0xb903: /* DM9801 E6 */
1982 default:
1983 db->HPNA_command |= 0x1000;
1984 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
1985 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
1986 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1987 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
1988 break;
1989 }
1990 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
1991 phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
1992 phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
1993}
1994
1995
1996/*
1997 * Init HomeRun DM9802
1998 */
1999
2000static void dmfe_program_DM9802(struct dmfe_board_info * db)
2001{
2002 uint phy_reg;
2003
2004 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
2005 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2006 phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2007 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
2008 phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
2009}
2010
2011
2012/*
2013 * Check remote HPNA power and speed status. If not correct,
2014 * issue command again.
2015*/
2016
2017static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
2018{
2019 uint phy_reg;
2020
2021 /* Got remote device status */
2022 phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
2023 switch(phy_reg) {
2024 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
2025 case 0x20: phy_reg = 0x0900;break; /* LP/HS */
2026 case 0x40: phy_reg = 0x0600;break; /* HP/LS */
2027 case 0x60: phy_reg = 0x0500;break; /* HP/HS */
2028 }
2029
2030 /* Check remote device status match our setting ot not */
2031 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
f67ba792
ML		 2032 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
2033 db->chip_id);
1da177e4
LT		 2034 db->HPNA_timer=8;
2035 } else
2036 db->HPNA_timer=600; /* Match, every 10 minutes, check */
2037}
2038
2039
2040
2041static struct pci_device_id dmfe_pci_tbl[] = {
2042 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
2043 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
2044 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
2045 { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
2046 { 0, }
2047};
2048MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
2049
2050
2051static struct pci_driver dmfe_driver = {
2052 .name = "dmfe",
2053 .id_table = dmfe_pci_tbl,
2054 .probe = dmfe_init_one,
2055 .remove = __devexit_p(dmfe_remove_one),
2056};
2057
2058MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
2059MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
2060MODULE_LICENSE("GPL");
2061MODULE_VERSION(DRV_VERSION);
2062
2063module_param(debug, int, 0);
2064module_param(mode, byte, 0);
2065module_param(cr6set, int, 0);
2066module_param(chkmode, byte, 0);
2067module_param(HPNA_mode, byte, 0);
2068module_param(HPNA_rx_cmd, byte, 0);
2069module_param(HPNA_tx_cmd, byte, 0);
2070module_param(HPNA_NoiseFloor, byte, 0);
2071module_param(SF_mode, byte, 0);
2072MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
f67ba792
ML		 2073MODULE_PARM_DESC(mode, "Davicom DM9xxx: "
2074 "Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2075
2076MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function "
2077 "(bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
1da177e4
LT		 2078
2079/* Description:
2080 * when user used insmod to add module, system invoked init_module()
2081 * to initilize and register.
2082 */
2083
2084static int __init dmfe_init_module(void)
2085{
2086 int rc;
2087
2088 printk(version);
2089 printed_version = 1;
2090
2091 DMFE_DBUG(0, "init_module() ", debug);
2092
2093 if (debug)
2094 dmfe_debug = debug; /* set debug flag */
2095 if (cr6set)
2096 dmfe_cr6_user_set = cr6set;
2097
2098 switch(mode) {
2099 case DMFE_10MHF:
2100 case DMFE_100MHF:
2101 case DMFE_10MFD:
2102 case DMFE_100MFD:
2103 case DMFE_1M_HPNA:
2104 dmfe_media_mode = mode;
2105 break;
2106 default:dmfe_media_mode = DMFE_AUTO;
2107 break;
2108 }
2109
2110 if (HPNA_mode > 4)
2111 HPNA_mode = 0; /* Default: LP/HS */
2112 if (HPNA_rx_cmd > 1)
2113 HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
2114 if (HPNA_tx_cmd > 1)
2115 HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
2116 if (HPNA_NoiseFloor > 15)
2117 HPNA_NoiseFloor = 0;
2118
29917620 2119 rc = pci_register_driver(&dmfe_driver);
1da177e4
LT		 2120 if (rc < 0)
2121 return rc;
2122
2123 return 0;
2124}
2125
2126
2127/*
2128 * Description:
2129 * when user used rmmod to delete module, system invoked clean_module()
2130 * to un-register all registered services.
2131 */
2132
2133static void __exit dmfe_cleanup_module(void)
2134{
2135 DMFE_DBUG(0, "dmfe_clean_module() ", debug);
2136 pci_unregister_driver(&dmfe_driver);
2137}
2138
2139module_init(dmfe_init_module);
2140module_exit(dmfe_cleanup_module);
Linux kernel - Deliverables
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