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[deliverable/linux.git] / drivers / net / tulip / tulip_core.c
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78a65518 1/* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux.
1da177e4 2
1da177e4
LT		 3 Copyright 2000,2001 The Linux Kernel Team
4 Written/copyright 1994-2001 by Donald Becker.
5
6 This software may be used and distributed according to the terms
7 of the GNU General Public License, incorporated herein by reference.
8
9 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
78a65518 10 for more information on this driver.
1da177e4 11
78a65518 12 Please submit bugs to http://bugzilla.kernel.org/ .
1da177e4
LT		 13*/
14
1da177e4
LT		 15
16#define DRV_NAME "tulip"
17#ifdef CONFIG_TULIP_NAPI
6bab99be 18#define DRV_VERSION "1.1.15-NAPI" /* Keep at least for test */
1da177e4 19#else
6bab99be 20#define DRV_VERSION "1.1.15"
1da177e4 21#endif
6bab99be 22#define DRV_RELDATE "Feb 27, 2007"
1da177e4
LT		 23
24
25#include <linux/module.h>
26#include <linux/pci.h>
27#include "tulip.h"
28#include <linux/init.h>
29#include <linux/etherdevice.h>
30#include <linux/delay.h>
31#include <linux/mii.h>
32#include <linux/ethtool.h>
33#include <linux/crc32.h>
34#include <asm/unaligned.h>
35#include <asm/uaccess.h>
36
49345103 37#ifdef CONFIG_SPARC
d297c31f 38#include <asm/prom.h>
1da177e4
LT		 39#endif
40
41static char version[] __devinitdata =
42 "Linux Tulip driver version " DRV_VERSION " (" DRV_RELDATE ")\n";
43
44
45/* A few user-configurable values. */
46
47/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
48static unsigned int max_interrupt_work = 25;
49
50#define MAX_UNITS 8
51/* Used to pass the full-duplex flag, etc. */
52static int full_duplex[MAX_UNITS];
53static int options[MAX_UNITS];
54static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */
55
56/* The possible media types that can be set in options[] are: */
57const char * const medianame[32] = {
58 "10baseT", "10base2", "AUI", "100baseTx",
59 "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx",
60 "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII",
61 "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4",
62 "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19",
63 "","","","", "","","","", "","","","Transceiver reset",
64};
65
66/* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */
67#if defined(__alpha__) || defined(__arm__) || defined(__hppa__) \
49345103 68 || defined(CONFIG_SPARC) || defined(__ia64__) \
1da177e4
LT		 69 || defined(__sh__) || defined(__mips__)
70static int rx_copybreak = 1518;
71#else
72static int rx_copybreak = 100;
73#endif
74
75/*
76 Set the bus performance register.
77 Typical: Set 16 longword cache alignment, no burst limit.
78 Cache alignment bits 15:14 Burst length 13:8
79 0000 No alignment 0x00000000 unlimited 0800 8 longwords
80 4000 8 longwords 0100 1 longword 1000 16 longwords
81 8000 16 longwords 0200 2 longwords 2000 32 longwords
82 C000 32 longwords 0400 4 longwords
83 Warning: many older 486 systems are broken and require setting 0x00A04800
84 8 longword cache alignment, 8 longword burst.
85 ToDo: Non-Intel setting could be better.
86*/
87
88#if defined(__alpha__) || defined(__ia64__)
89static int csr0 = 0x01A00000 | 0xE000;
90#elif defined(__i386__) || defined(__powerpc__) || defined(__x86_64__)
91static int csr0 = 0x01A00000 | 0x8000;
49345103 92#elif defined(CONFIG_SPARC) || defined(__hppa__)
1da177e4
LT		 93/* The UltraSparc PCI controllers will disconnect at every 64-byte
94 * crossing anyways so it makes no sense to tell Tulip to burst
95 * any more than that.
96 */
97static int csr0 = 0x01A00000 | 0x9000;
98#elif defined(__arm__) || defined(__sh__)
99static int csr0 = 0x01A00000 | 0x4800;
100#elif defined(__mips__)
101static int csr0 = 0x00200000 | 0x4000;
102#else
103#warning Processor architecture undefined!
104static int csr0 = 0x00A00000 | 0x4800;
105#endif
106
107/* Operational parameters that usually are not changed. */
108/* Time in jiffies before concluding the transmitter is hung. */
109#define TX_TIMEOUT (4*HZ)
110
111
112MODULE_AUTHOR("The Linux Kernel Team");
113MODULE_DESCRIPTION("Digital 21*4* Tulip ethernet driver");
114MODULE_LICENSE("GPL");
115MODULE_VERSION(DRV_VERSION);
116module_param(tulip_debug, int, 0);
117module_param(max_interrupt_work, int, 0);
118module_param(rx_copybreak, int, 0);
119module_param(csr0, int, 0);
120module_param_array(options, int, NULL, 0);
121module_param_array(full_duplex, int, NULL, 0);
122
123#define PFX DRV_NAME ": "
124
125#ifdef TULIP_DEBUG
126int tulip_debug = TULIP_DEBUG;
127#else
128int tulip_debug = 1;
129#endif
130
0bb3cf72
FR		 131static void tulip_timer(unsigned long data)
132{
133 struct net_device *dev = (struct net_device *)data;
134 struct tulip_private *tp = netdev_priv(dev);
1da177e4 135
0bb3cf72
FR		 136 if (netif_running(dev))
137 schedule_work(&tp->media_work);
138}
1da177e4
LT		 139
140/*
141 * This table use during operation for capabilities and media timer.
142 *
143 * It is indexed via the values in 'enum chips'
144 */
145
146struct tulip_chip_table tulip_tbl[] = {
147 { }, /* placeholder for array, slot unused currently */
148 { }, /* placeholder for array, slot unused currently */
149
150 /* DC21140 */
151 { "Digital DS21140 Tulip", 128, 0x0001ebef,
0bb3cf72
FR		 152 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer,
153 tulip_media_task },
1da177e4
LT		 154
155 /* DC21142, DC21143 */
b892de0b 156 { "Digital DS21142/43 Tulip", 128, 0x0801fbff,
1da177e4 157 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY
0bb3cf72 158 | HAS_INTR_MITIGATION | HAS_PCI_MWI, tulip_timer, t21142_media_task },
1da177e4
LT		 159
160 /* LC82C168 */
161 { "Lite-On 82c168 PNIC", 256, 0x0001fbef,
0bb3cf72 162 HAS_MII | HAS_PNICNWAY, pnic_timer, },
1da177e4
LT		 163
164 /* MX98713 */
165 { "Macronix 98713 PMAC", 128, 0x0001ebef,
0bb3cf72 166 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
1da177e4
LT		 167
168 /* MX98715 */
169 { "Macronix 98715 PMAC", 256, 0x0001ebef,
0bb3cf72 170 HAS_MEDIA_TABLE, mxic_timer, },
1da177e4
LT		 171
172 /* MX98725 */
173 { "Macronix 98725 PMAC", 256, 0x0001ebef,
0bb3cf72 174 HAS_MEDIA_TABLE, mxic_timer, },
1da177e4
LT		 175
176 /* AX88140 */
177 { "ASIX AX88140", 128, 0x0001fbff,
178 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY
0bb3cf72 179 | IS_ASIX, tulip_timer, tulip_media_task },
1da177e4
LT		 180
181 /* PNIC2 */
182 { "Lite-On PNIC-II", 256, 0x0801fbff,
0bb3cf72 183 HAS_MII | HAS_NWAY | HAS_8023X | HAS_PCI_MWI, pnic2_timer, },
1da177e4
LT		 184
185 /* COMET */
186 { "ADMtek Comet", 256, 0x0001abef,
0bb3cf72 187 HAS_MII | MC_HASH_ONLY | COMET_MAC_ADDR, comet_timer, },
1da177e4
LT		 188
189 /* COMPEX9881 */
190 { "Compex 9881 PMAC", 128, 0x0001ebef,
0bb3cf72 191 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
1da177e4
LT		 192
193 /* I21145 */
194 { "Intel DS21145 Tulip", 128, 0x0801fbff,
195 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI
0bb3cf72 196 | HAS_NWAY | HAS_PCI_MWI, tulip_timer, tulip_media_task },
1da177e4
LT		 197
198 /* DM910X */
199 { "Davicom DM9102/DM9102A", 128, 0x0001ebef,
200 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI,
0bb3cf72 201 tulip_timer, tulip_media_task },
1da177e4
LT		 202
203 /* RS7112 */
204 { "Conexant LANfinity", 256, 0x0001ebef,
0bb3cf72 205 HAS_MII | HAS_ACPI, tulip_timer, tulip_media_task },
1da177e4 206
1da177e4
LT		 207};
208
209
210static struct pci_device_id tulip_pci_tbl[] = {
211 { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 },
212 { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 },
213 { 0x11AD, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, LC82C168 },
214 { 0x10d9, 0x0512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98713 },
215 { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
216/* { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98725 },*/
217 { 0x125B, 0x1400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AX88140 },
218 { 0x11AD, 0xc115, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PNIC2 },
219 { 0x1317, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
220 { 0x1317, 0x0985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
221 { 0x1317, 0x1985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
222 { 0x1317, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
223 { 0x13D1, 0xAB02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
224 { 0x13D1, 0xAB03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
225 { 0x13D1, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
226 { 0x104A, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
227 { 0x104A, 0x2774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
228 { 0x1259, 0xa120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
229 { 0x11F6, 0x9881, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMPEX9881 },
230 { 0x8086, 0x0039, PCI_ANY_ID, PCI_ANY_ID, 0, 0, I21145 },
231 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
232 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
233 { 0x1113, 0x1216, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
234 { 0x1113, 0x1217, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
235 { 0x1113, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
236 { 0x1186, 0x1541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
237 { 0x1186, 0x1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
238 { 0x1186, 0x1591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
239 { 0x14f1, 0x1803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CONEXANT },
240 { 0x1626, 0x8410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
241 { 0x1737, 0xAB09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
242 { 0x1737, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
243 { 0x17B3, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
1da177e4 244 { 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */
9b25978e 245 { 0x14ea, 0xab08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Planex FNW-3602-TX */
1a449358 246 { 0x1414, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
1da177e4
LT		 247 { } /* terminate list */
248};
249MODULE_DEVICE_TABLE(pci, tulip_pci_tbl);
250
251
252/* A full-duplex map for media types. */
253const char tulip_media_cap[32] =
254{0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 28,31,0,0, };
255
256static void tulip_tx_timeout(struct net_device *dev);
257static void tulip_init_ring(struct net_device *dev);
258static int tulip_start_xmit(struct sk_buff *skb, struct net_device *dev);
259static int tulip_open(struct net_device *dev);
260static int tulip_close(struct net_device *dev);
261static void tulip_up(struct net_device *dev);
262static void tulip_down(struct net_device *dev);
263static struct net_device_stats *tulip_get_stats(struct net_device *dev);
264static int private_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
265static void set_rx_mode(struct net_device *dev);
266#ifdef CONFIG_NET_POLL_CONTROLLER
267static void poll_tulip(struct net_device *dev);
268#endif
269
270static void tulip_set_power_state (struct tulip_private *tp,
271 int sleep, int snooze)
272{
273 if (tp->flags & HAS_ACPI) {
274 u32 tmp, newtmp;
275 pci_read_config_dword (tp->pdev, CFDD, &tmp);
276 newtmp = tmp & ~(CFDD_Sleep | CFDD_Snooze);
277 if (sleep)
278 newtmp |= CFDD_Sleep;
279 else if (snooze)
280 newtmp |= CFDD_Snooze;
281 if (tmp != newtmp)
282 pci_write_config_dword (tp->pdev, CFDD, newtmp);
283 }
284
285}
286
287
288static void tulip_up(struct net_device *dev)
289{
290 struct tulip_private *tp = netdev_priv(dev);
291 void __iomem *ioaddr = tp->base_addr;
292 int next_tick = 3*HZ;
b4482a4b 293 u32 reg;
1da177e4
LT		 294 int i;
295
bea3348e
SH		 296#ifdef CONFIG_TULIP_NAPI
297 napi_enable(&tp->napi);
298#endif
299
1da177e4
LT		 300 /* Wake the chip from sleep/snooze mode. */
301 tulip_set_power_state (tp, 0, 0);
302
303 /* On some chip revs we must set the MII/SYM port before the reset!? */
304 if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii))
305 iowrite32(0x00040000, ioaddr + CSR6);
306
307 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
308 iowrite32(0x00000001, ioaddr + CSR0);
b4482a4b 309 pci_read_config_dword(tp->pdev, PCI_COMMAND, &reg); /* flush write */
1da177e4
LT		 310 udelay(100);
311
312 /* Deassert reset.
313 Wait the specified 50 PCI cycles after a reset by initializing
314 Tx and Rx queues and the address filter list. */
315 iowrite32(tp->csr0, ioaddr + CSR0);
b4482a4b 316 pci_read_config_dword(tp->pdev, PCI_COMMAND, &reg); /* flush write */
1da177e4
LT		 317 udelay(100);
318
319 if (tulip_debug > 1)
320 printk(KERN_DEBUG "%s: tulip_up(), irq==%d.\n", dev->name, dev->irq);
321
322 iowrite32(tp->rx_ring_dma, ioaddr + CSR3);
323 iowrite32(tp->tx_ring_dma, ioaddr + CSR4);
324 tp->cur_rx = tp->cur_tx = 0;
325 tp->dirty_rx = tp->dirty_tx = 0;
326
327 if (tp->flags & MC_HASH_ONLY) {
6caf52a4
HH		 328 u32 addr_low = get_unaligned_le32(dev->dev_addr);
329 u32 addr_high = get_unaligned_le16(dev->dev_addr + 4);
1da177e4
LT		 330 if (tp->chip_id == AX88140) {
331 iowrite32(0, ioaddr + CSR13);
332 iowrite32(addr_low, ioaddr + CSR14);
333 iowrite32(1, ioaddr + CSR13);
334 iowrite32(addr_high, ioaddr + CSR14);
335 } else if (tp->flags & COMET_MAC_ADDR) {
336 iowrite32(addr_low, ioaddr + 0xA4);
337 iowrite32(addr_high, ioaddr + 0xA8);
338 iowrite32(0, ioaddr + 0xAC);
339 iowrite32(0, ioaddr + 0xB0);
340 }
341 } else {
342 /* This is set_rx_mode(), but without starting the transmitter. */
343 u16 *eaddrs = (u16 *)dev->dev_addr;
344 u16 *setup_frm = &tp->setup_frame[15*6];
345 dma_addr_t mapping;
346
347 /* 21140 bug: you must add the broadcast address. */
348 memset(tp->setup_frame, 0xff, sizeof(tp->setup_frame));
349 /* Fill the final entry of the table with our physical address. */
350 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
351 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
352 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
353
354 mapping = pci_map_single(tp->pdev, tp->setup_frame,
355 sizeof(tp->setup_frame),
356 PCI_DMA_TODEVICE);
357 tp->tx_buffers[tp->cur_tx].skb = NULL;
358 tp->tx_buffers[tp->cur_tx].mapping = mapping;
359
360 /* Put the setup frame on the Tx list. */
361 tp->tx_ring[tp->cur_tx].length = cpu_to_le32(0x08000000 | 192);
362 tp->tx_ring[tp->cur_tx].buffer1 = cpu_to_le32(mapping);
363 tp->tx_ring[tp->cur_tx].status = cpu_to_le32(DescOwned);
364
365 tp->cur_tx++;
366 }
367
368 tp->saved_if_port = dev->if_port;
369 if (dev->if_port == 0)
370 dev->if_port = tp->default_port;
371
372 /* Allow selecting a default media. */
373 i = 0;
374 if (tp->mtable == NULL)
375 goto media_picked;
376 if (dev->if_port) {
377 int looking_for = tulip_media_cap[dev->if_port] & MediaIsMII ? 11 :
378 (dev->if_port == 12 ? 0 : dev->if_port);
379 for (i = 0; i < tp->mtable->leafcount; i++)
380 if (tp->mtable->mleaf[i].media == looking_for) {
381 printk(KERN_INFO "%s: Using user-specified media %s.\n",
382 dev->name, medianame[dev->if_port]);
383 goto media_picked;
384 }
385 }
386 if ((tp->mtable->defaultmedia & 0x0800) == 0) {
387 int looking_for = tp->mtable->defaultmedia & MEDIA_MASK;
388 for (i = 0; i < tp->mtable->leafcount; i++)
389 if (tp->mtable->mleaf[i].media == looking_for) {
390 printk(KERN_INFO "%s: Using EEPROM-set media %s.\n",
391 dev->name, medianame[looking_for]);
392 goto media_picked;
393 }
394 }
395 /* Start sensing first non-full-duplex media. */
396 for (i = tp->mtable->leafcount - 1;
397 (tulip_media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--)
398 ;
399media_picked:
400
401 tp->csr6 = 0;
402 tp->cur_index = i;
403 tp->nwayset = 0;
404
405 if (dev->if_port) {
406 if (tp->chip_id == DC21143 &&
407 (tulip_media_cap[dev->if_port] & MediaIsMII)) {
408 /* We must reset the media CSRs when we force-select MII mode. */
409 iowrite32(0x0000, ioaddr + CSR13);
410 iowrite32(0x0000, ioaddr + CSR14);
411 iowrite32(0x0008, ioaddr + CSR15);
412 }
413 tulip_select_media(dev, 1);
414 } else if (tp->chip_id == DC21142) {
415 if (tp->mii_cnt) {
416 tulip_select_media(dev, 1);
417 if (tulip_debug > 1)
418 printk(KERN_INFO "%s: Using MII transceiver %d, status "
419 "%4.4x.\n",
420 dev->name, tp->phys[0], tulip_mdio_read(dev, tp->phys[0], 1));
421 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
422 tp->csr6 = csr6_mask_hdcap;
423 dev->if_port = 11;
424 iowrite32(0x0000, ioaddr + CSR13);
425 iowrite32(0x0000, ioaddr + CSR14);
426 } else
427 t21142_start_nway(dev);
428 } else if (tp->chip_id == PNIC2) {
429 /* for initial startup advertise 10/100 Full and Half */
430 tp->sym_advertise = 0x01E0;
431 /* enable autonegotiate end interrupt */
432 iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5);
433 iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7);
434 pnic2_start_nway(dev);
435 } else if (tp->chip_id == LC82C168 && ! tp->medialock) {
436 if (tp->mii_cnt) {
437 dev->if_port = 11;
438 tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0);
439 iowrite32(0x0001, ioaddr + CSR15);
440 } else if (ioread32(ioaddr + CSR5) & TPLnkPass)
441 pnic_do_nway(dev);
442 else {
443 /* Start with 10mbps to do autonegotiation. */
444 iowrite32(0x32, ioaddr + CSR12);
445 tp->csr6 = 0x00420000;
446 iowrite32(0x0001B078, ioaddr + 0xB8);
447 iowrite32(0x0201B078, ioaddr + 0xB8);
448 next_tick = 1*HZ;
449 }
450 } else if ((tp->chip_id == MX98713 || tp->chip_id == COMPEX9881)
451 && ! tp->medialock) {
452 dev->if_port = 0;
453 tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0);
454 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
455 } else if (tp->chip_id == MX98715 || tp->chip_id == MX98725) {
456 /* Provided by BOLO, Macronix - 12/10/1998. */
457 dev->if_port = 0;
458 tp->csr6 = 0x01a80200;
459 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
460 iowrite32(0x11000 | ioread16(ioaddr + 0xa0), ioaddr + 0xa0);
461 } else if (tp->chip_id == COMET || tp->chip_id == CONEXANT) {
462 /* Enable automatic Tx underrun recovery. */
463 iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88);
464 dev->if_port = tp->mii_cnt ? 11 : 0;
465 tp->csr6 = 0x00040000;
466 } else if (tp->chip_id == AX88140) {
467 tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100;
468 } else
469 tulip_select_media(dev, 1);
470
471 /* Start the chip's Tx to process setup frame. */
472 tulip_stop_rxtx(tp);
473 barrier();
474 udelay(5);
475 iowrite32(tp->csr6 | TxOn, ioaddr + CSR6);
476
477 /* Enable interrupts by setting the interrupt mask. */
478 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5);
479 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
480 tulip_start_rxtx(tp);
481 iowrite32(0, ioaddr + CSR2); /* Rx poll demand */
482
483 if (tulip_debug > 2) {
484 printk(KERN_DEBUG "%s: Done tulip_up(), CSR0 %8.8x, CSR5 %8.8x CSR6 %8.8x.\n",
485 dev->name, ioread32(ioaddr + CSR0), ioread32(ioaddr + CSR5),
486 ioread32(ioaddr + CSR6));
487 }
488
489 /* Set the timer to switch to check for link beat and perhaps switch
490 to an alternate media type. */
491 tp->timer.expires = RUN_AT(next_tick);
492 add_timer(&tp->timer);
493#ifdef CONFIG_TULIP_NAPI
494 init_timer(&tp->oom_timer);
495 tp->oom_timer.data = (unsigned long)dev;
496 tp->oom_timer.function = oom_timer;
497#endif
498}
499
500static int
501tulip_open(struct net_device *dev)
502{
503 int retval;
504
1fb9df5d 505 if ((retval = request_irq(dev->irq, &tulip_interrupt, IRQF_SHARED, dev->name, dev)))
1da177e4
LT		 506 return retval;
507
508 tulip_init_ring (dev);
509
510 tulip_up (dev);
511
512 netif_start_queue (dev);
513
514 return 0;
515}
516
517
518static void tulip_tx_timeout(struct net_device *dev)
519{
520 struct tulip_private *tp = netdev_priv(dev);
521 void __iomem *ioaddr = tp->base_addr;
522 unsigned long flags;
523
524 spin_lock_irqsave (&tp->lock, flags);
525
526 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
527 /* Do nothing -- the media monitor should handle this. */
528 if (tulip_debug > 1)
529 printk(KERN_WARNING "%s: Transmit timeout using MII device.\n",
530 dev->name);
531 } else if (tp->chip_id == DC21140 || tp->chip_id == DC21142
532 || tp->chip_id == MX98713 || tp->chip_id == COMPEX9881
ea8f400c 533 || tp->chip_id == DM910X) {
1da177e4
LT		 534 printk(KERN_WARNING "%s: 21140 transmit timed out, status %8.8x, "
535 "SIA %8.8x %8.8x %8.8x %8.8x, resetting...\n",
536 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
537 ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14), ioread32(ioaddr + CSR15));
0bb3cf72
FR		 538 tp->timeout_recovery = 1;
539 schedule_work(&tp->media_work);
540 goto out_unlock;
1da177e4
LT		 541 } else if (tp->chip_id == PNIC2) {
542 printk(KERN_WARNING "%s: PNIC2 transmit timed out, status %8.8x, "
543 "CSR6/7 %8.8x / %8.8x CSR12 %8.8x, resetting...\n",
544 dev->name, (int)ioread32(ioaddr + CSR5), (int)ioread32(ioaddr + CSR6),
545 (int)ioread32(ioaddr + CSR7), (int)ioread32(ioaddr + CSR12));
546 } else {
547 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x, CSR12 "
548 "%8.8x, resetting...\n",
549 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12));
550 dev->if_port = 0;
551 }
552
553#if defined(way_too_many_messages)
554 if (tulip_debug > 3) {
555 int i;
556 for (i = 0; i < RX_RING_SIZE; i++) {
557 u8 *buf = (u8 *)(tp->rx_ring[i].buffer1);
558 int j;
559 printk(KERN_DEBUG "%2d: %8.8x %8.8x %8.8x %8.8x "
560 "%2.2x %2.2x %2.2x.\n",
561 i, (unsigned int)tp->rx_ring[i].status,
562 (unsigned int)tp->rx_ring[i].length,
563 (unsigned int)tp->rx_ring[i].buffer1,
564 (unsigned int)tp->rx_ring[i].buffer2,
565 buf[0], buf[1], buf[2]);
566 for (j = 0; buf[j] != 0xee && j < 1600; j++)
567 if (j < 100) printk(" %2.2x", buf[j]);
568 printk(" j=%d.\n", j);
569 }
570 printk(KERN_DEBUG " Rx ring %8.8x: ", (int)tp->rx_ring);
571 for (i = 0; i < RX_RING_SIZE; i++)
572 printk(" %8.8x", (unsigned int)tp->rx_ring[i].status);
573 printk("\n" KERN_DEBUG " Tx ring %8.8x: ", (int)tp->tx_ring);
574 for (i = 0; i < TX_RING_SIZE; i++)
575 printk(" %8.8x", (unsigned int)tp->tx_ring[i].status);
576 printk("\n");
577 }
578#endif
579
0bb3cf72 580 tulip_tx_timeout_complete(tp, ioaddr);
1da177e4 581
0bb3cf72 582out_unlock:
1da177e4
LT		 583 spin_unlock_irqrestore (&tp->lock, flags);
584 dev->trans_start = jiffies;
585 netif_wake_queue (dev);
586}
587
588
589/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
590static void tulip_init_ring(struct net_device *dev)
591{
592 struct tulip_private *tp = netdev_priv(dev);
593 int i;
594
595 tp->susp_rx = 0;
596 tp->ttimer = 0;
597 tp->nir = 0;
598
599 for (i = 0; i < RX_RING_SIZE; i++) {
600 tp->rx_ring[i].status = 0x00000000;
601 tp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ);
602 tp->rx_ring[i].buffer2 = cpu_to_le32(tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * (i + 1));
603 tp->rx_buffers[i].skb = NULL;
604 tp->rx_buffers[i].mapping = 0;
605 }
606 /* Mark the last entry as wrapping the ring. */
607 tp->rx_ring[i-1].length = cpu_to_le32(PKT_BUF_SZ | DESC_RING_WRAP);
608 tp->rx_ring[i-1].buffer2 = cpu_to_le32(tp->rx_ring_dma);
609
610 for (i = 0; i < RX_RING_SIZE; i++) {
611 dma_addr_t mapping;
612
613 /* Note the receive buffer must be longword aligned.
614 dev_alloc_skb() provides 16 byte alignment. But do *not*
615 use skb_reserve() to align the IP header! */
616 struct sk_buff *skb = dev_alloc_skb(PKT_BUF_SZ);
617 tp->rx_buffers[i].skb = skb;
618 if (skb == NULL)
619 break;
689be439 620 mapping = pci_map_single(tp->pdev, skb->data,
1da177e4
LT		 621 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
622 tp->rx_buffers[i].mapping = mapping;
623 skb->dev = dev; /* Mark as being used by this device. */
624 tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */
625 tp->rx_ring[i].buffer1 = cpu_to_le32(mapping);
626 }
627 tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
628
629 /* The Tx buffer descriptor is filled in as needed, but we
630 do need to clear the ownership bit. */
631 for (i = 0; i < TX_RING_SIZE; i++) {
632 tp->tx_buffers[i].skb = NULL;
633 tp->tx_buffers[i].mapping = 0;
634 tp->tx_ring[i].status = 0x00000000;
635 tp->tx_ring[i].buffer2 = cpu_to_le32(tp->tx_ring_dma + sizeof(struct tulip_tx_desc) * (i + 1));
636 }
637 tp->tx_ring[i-1].buffer2 = cpu_to_le32(tp->tx_ring_dma);
638}
639
640static int
641tulip_start_xmit(struct sk_buff *skb, struct net_device *dev)
642{
643 struct tulip_private *tp = netdev_priv(dev);
644 int entry;
645 u32 flag;
646 dma_addr_t mapping;
647
648 spin_lock_irq(&tp->lock);
649
650 /* Calculate the next Tx descriptor entry. */
651 entry = tp->cur_tx % TX_RING_SIZE;
652
653 tp->tx_buffers[entry].skb = skb;
654 mapping = pci_map_single(tp->pdev, skb->data,
655 skb->len, PCI_DMA_TODEVICE);
656 tp->tx_buffers[entry].mapping = mapping;
657 tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
658
659 if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
660 flag = 0x60000000; /* No interrupt */
661 } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) {
662 flag = 0xe0000000; /* Tx-done intr. */
663 } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) {
664 flag = 0x60000000; /* No Tx-done intr. */
665 } else { /* Leave room for set_rx_mode() to fill entries. */
666 flag = 0xe0000000; /* Tx-done intr. */
667 netif_stop_queue(dev);
668 }
669 if (entry == TX_RING_SIZE-1)
670 flag = 0xe0000000 | DESC_RING_WRAP;
671
672 tp->tx_ring[entry].length = cpu_to_le32(skb->len | flag);
673 /* if we were using Transmit Automatic Polling, we would need a
674 * wmb() here. */
675 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
676 wmb();
677
678 tp->cur_tx++;
679
680 /* Trigger an immediate transmit demand. */
681 iowrite32(0, tp->base_addr + CSR1);
682
683 spin_unlock_irq(&tp->lock);
684
685 dev->trans_start = jiffies;
686
687 return 0;
688}
689
690static void tulip_clean_tx_ring(struct tulip_private *tp)
691{
692 unsigned int dirty_tx;
693
694 for (dirty_tx = tp->dirty_tx ; tp->cur_tx - dirty_tx > 0;
695 dirty_tx++) {
696 int entry = dirty_tx % TX_RING_SIZE;
697 int status = le32_to_cpu(tp->tx_ring[entry].status);
698
699 if (status < 0) {
700 tp->stats.tx_errors++; /* It wasn't Txed */
701 tp->tx_ring[entry].status = 0;
702 }
703
704 /* Check for Tx filter setup frames. */
705 if (tp->tx_buffers[entry].skb == NULL) {
706 /* test because dummy frames not mapped */
707 if (tp->tx_buffers[entry].mapping)
708 pci_unmap_single(tp->pdev,
709 tp->tx_buffers[entry].mapping,
710 sizeof(tp->setup_frame),
711 PCI_DMA_TODEVICE);
712 continue;
713 }
714
715 pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping,
716 tp->tx_buffers[entry].skb->len,
717 PCI_DMA_TODEVICE);
718
719 /* Free the original skb. */
720 dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
721 tp->tx_buffers[entry].skb = NULL;
722 tp->tx_buffers[entry].mapping = 0;
723 }
724}
725
726static void tulip_down (struct net_device *dev)
727{
728 struct tulip_private *tp = netdev_priv(dev);
729 void __iomem *ioaddr = tp->base_addr;
730 unsigned long flags;
731
4bb073c0 732 cancel_work_sync(&tp->media_work);
0bb3cf72 733
bea3348e
SH		 734#ifdef CONFIG_TULIP_NAPI
735 napi_disable(&tp->napi);
736#endif
737
1da177e4
LT		 738 del_timer_sync (&tp->timer);
739#ifdef CONFIG_TULIP_NAPI
740 del_timer_sync (&tp->oom_timer);
741#endif
742 spin_lock_irqsave (&tp->lock, flags);
743
744 /* Disable interrupts by clearing the interrupt mask. */
745 iowrite32 (0x00000000, ioaddr + CSR7);
746
747 /* Stop the Tx and Rx processes. */
748 tulip_stop_rxtx(tp);
749
750 /* prepare receive buffers */
751 tulip_refill_rx(dev);
752
753 /* release any unconsumed transmit buffers */
754 tulip_clean_tx_ring(tp);
755
756 if (ioread32 (ioaddr + CSR6) != 0xffffffff)
757 tp->stats.rx_missed_errors += ioread32 (ioaddr + CSR8) & 0xffff;
758
759 spin_unlock_irqrestore (&tp->lock, flags);
760
761 init_timer(&tp->timer);
762 tp->timer.data = (unsigned long)dev;
763 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
764
765 dev->if_port = tp->saved_if_port;
766
767 /* Leave the driver in snooze, not sleep, mode. */
768 tulip_set_power_state (tp, 0, 1);
769}
770
771
772static int tulip_close (struct net_device *dev)
773{
774 struct tulip_private *tp = netdev_priv(dev);
775 void __iomem *ioaddr = tp->base_addr;
776 int i;
777
778 netif_stop_queue (dev);
779
780 tulip_down (dev);
781
782 if (tulip_debug > 1)
783 printk (KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
784 dev->name, ioread32 (ioaddr + CSR5));
785
786 free_irq (dev->irq, dev);
787
788 /* Free all the skbuffs in the Rx queue. */
789 for (i = 0; i < RX_RING_SIZE; i++) {
790 struct sk_buff *skb = tp->rx_buffers[i].skb;
791 dma_addr_t mapping = tp->rx_buffers[i].mapping;
792
793 tp->rx_buffers[i].skb = NULL;
794 tp->rx_buffers[i].mapping = 0;
795
796 tp->rx_ring[i].status = 0; /* Not owned by Tulip chip. */
797 tp->rx_ring[i].length = 0;
76285ee0
AV		 798 /* An invalid address. */
799 tp->rx_ring[i].buffer1 = cpu_to_le32(0xBADF00D0);
1da177e4
LT		 800 if (skb) {
801 pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ,
802 PCI_DMA_FROMDEVICE);
803 dev_kfree_skb (skb);
804 }
805 }
806 for (i = 0; i < TX_RING_SIZE; i++) {
807 struct sk_buff *skb = tp->tx_buffers[i].skb;
808
809 if (skb != NULL) {
810 pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping,
811 skb->len, PCI_DMA_TODEVICE);
812 dev_kfree_skb (skb);
813 }
814 tp->tx_buffers[i].skb = NULL;
815 tp->tx_buffers[i].mapping = 0;
816 }
817
818 return 0;
819}
820
821static struct net_device_stats *tulip_get_stats(struct net_device *dev)
822{
823 struct tulip_private *tp = netdev_priv(dev);
824 void __iomem *ioaddr = tp->base_addr;
825
826 if (netif_running(dev)) {
827 unsigned long flags;
828
829 spin_lock_irqsave (&tp->lock, flags);
830
831 tp->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
832
833 spin_unlock_irqrestore(&tp->lock, flags);
834 }
835
836 return &tp->stats;
837}
838
839
840static void tulip_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
841{
842 struct tulip_private *np = netdev_priv(dev);
843 strcpy(info->driver, DRV_NAME);
844 strcpy(info->version, DRV_VERSION);
845 strcpy(info->bus_info, pci_name(np->pdev));
846}
847
7282d491 848static const struct ethtool_ops ops = {
1da177e4
LT		 849 .get_drvinfo = tulip_get_drvinfo
850};
851
852/* Provide ioctl() calls to examine the MII xcvr state. */
853static int private_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
854{
855 struct tulip_private *tp = netdev_priv(dev);
856 void __iomem *ioaddr = tp->base_addr;
857 struct mii_ioctl_data *data = if_mii(rq);
858 const unsigned int phy_idx = 0;
859 int phy = tp->phys[phy_idx] & 0x1f;
860 unsigned int regnum = data->reg_num;
861
862 switch (cmd) {
863 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
864 if (tp->mii_cnt)
865 data->phy_id = phy;
866 else if (tp->flags & HAS_NWAY)
867 data->phy_id = 32;
868 else if (tp->chip_id == COMET)
869 data->phy_id = 1;
870 else
871 return -ENODEV;
872
873 case SIOCGMIIREG: /* Read MII PHY register. */
874 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
875 int csr12 = ioread32 (ioaddr + CSR12);
876 int csr14 = ioread32 (ioaddr + CSR14);
877 switch (regnum) {
878 case 0:
879 if (((csr14<<5) & 0x1000) ||
880 (dev->if_port == 5 && tp->nwayset))
881 data->val_out = 0x1000;
882 else
883 data->val_out = (tulip_media_cap[dev->if_port]&MediaIs100 ? 0x2000 : 0)
884 | (tulip_media_cap[dev->if_port]&MediaIsFD ? 0x0100 : 0);
885 break;
886 case 1:
887 data->val_out =
888 0x1848 +
889 ((csr12&0x7000) == 0x5000 ? 0x20 : 0) +
890 ((csr12&0x06) == 6 ? 0 : 4);
891 data->val_out |= 0x6048;
892 break;
893 case 4:
894 /* Advertised value, bogus 10baseTx-FD value from CSR6. */
895 data->val_out =
896 ((ioread32(ioaddr + CSR6) >> 3) & 0x0040) +
897 ((csr14 >> 1) & 0x20) + 1;
898 data->val_out |= ((csr14 >> 9) & 0x03C0);
899 break;
900 case 5: data->val_out = tp->lpar; break;
901 default: data->val_out = 0; break;
902 }
903 } else {
904 data->val_out = tulip_mdio_read (dev, data->phy_id & 0x1f, regnum);
905 }
906 return 0;
907
908 case SIOCSMIIREG: /* Write MII PHY register. */
909 if (!capable (CAP_NET_ADMIN))
910 return -EPERM;
911 if (regnum & ~0x1f)
912 return -EINVAL;
913 if (data->phy_id == phy) {
914 u16 value = data->val_in;
915 switch (regnum) {
916 case 0: /* Check for autonegotiation on or reset. */
917 tp->full_duplex_lock = (value & 0x9000) ? 0 : 1;
918 if (tp->full_duplex_lock)
919 tp->full_duplex = (value & 0x0100) ? 1 : 0;
920 break;
921 case 4:
922 tp->advertising[phy_idx] =
923 tp->mii_advertise = data->val_in;
924 break;
925 }
926 }
927 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
928 u16 value = data->val_in;
929 if (regnum == 0) {
930 if ((value & 0x1200) == 0x1200) {
931 if (tp->chip_id == PNIC2) {
932 pnic2_start_nway (dev);
933 } else {
934 t21142_start_nway (dev);
935 }
936 }
937 } else if (regnum == 4)
938 tp->sym_advertise = value;
939 } else {
940 tulip_mdio_write (dev, data->phy_id & 0x1f, regnum, data->val_in);
941 }
942 return 0;
943 default:
944 return -EOPNOTSUPP;
945 }
946
947 return -EOPNOTSUPP;
948}
949
950
951/* Set or clear the multicast filter for this adaptor.
952 Note that we only use exclusion around actually queueing the
953 new frame, not around filling tp->setup_frame. This is non-deterministic
954 when re-entered but still correct. */
955
956#undef set_bit_le
957#define set_bit_le(i,p) do { ((char *)(p))[(i)/8] |= (1<<((i)%8)); } while(0)
958
959static void build_setup_frame_hash(u16 *setup_frm, struct net_device *dev)
960{
961 struct tulip_private *tp = netdev_priv(dev);
962 u16 hash_table[32];
963 struct dev_mc_list *mclist;
964 int i;
965 u16 *eaddrs;
966
967 memset(hash_table, 0, sizeof(hash_table));
968 set_bit_le(255, hash_table); /* Broadcast entry */
969 /* This should work on big-endian machines as well. */
970 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
971 i++, mclist = mclist->next) {
972 int index = ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x1ff;
973
974 set_bit_le(index, hash_table);
975
976 }
977 for (i = 0; i < 32; i++) {
978 *setup_frm++ = hash_table[i];
979 *setup_frm++ = hash_table[i];
980 }
981 setup_frm = &tp->setup_frame[13*6];
982
983 /* Fill the final entry with our physical address. */
984 eaddrs = (u16 *)dev->dev_addr;
985 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
986 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
987 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
988}
989
990static void build_setup_frame_perfect(u16 *setup_frm, struct net_device *dev)
991{
992 struct tulip_private *tp = netdev_priv(dev);
993 struct dev_mc_list *mclist;
994 int i;
995 u16 *eaddrs;
996
997 /* We have <= 14 addresses so we can use the wonderful
998 16 address perfect filtering of the Tulip. */
999 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
1000 i++, mclist = mclist->next) {
1001 eaddrs = (u16 *)mclist->dmi_addr;
1002 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1003 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1004 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1005 }
1006 /* Fill the unused entries with the broadcast address. */
1007 memset(setup_frm, 0xff, (15-i)*12);
1008 setup_frm = &tp->setup_frame[15*6];
1009
1010 /* Fill the final entry with our physical address. */
1011 eaddrs = (u16 *)dev->dev_addr;
1012 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1013 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1014 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1015}
1016
1017
1018static void set_rx_mode(struct net_device *dev)
1019{
1020 struct tulip_private *tp = netdev_priv(dev);
1021 void __iomem *ioaddr = tp->base_addr;
1022 int csr6;
1023
1024 csr6 = ioread32(ioaddr + CSR6) & ~0x00D5;
1025
1026 tp->csr6 &= ~0x00D5;
1027 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1028 tp->csr6 |= AcceptAllMulticast | AcceptAllPhys;
1029 csr6 |= AcceptAllMulticast | AcceptAllPhys;
1da177e4
LT		 1030 } else if ((dev->mc_count > 1000) || (dev->flags & IFF_ALLMULTI)) {
1031 /* Too many to filter well -- accept all multicasts. */
1032 tp->csr6 |= AcceptAllMulticast;
1033 csr6 |= AcceptAllMulticast;
1034 } else if (tp->flags & MC_HASH_ONLY) {
1035 /* Some work-alikes have only a 64-entry hash filter table. */
1036 /* Should verify correctness on big-endian/__powerpc__ */
1037 struct dev_mc_list *mclist;
1038 int i;
1039 if (dev->mc_count > 64) { /* Arbitrary non-effective limit. */
1040 tp->csr6 |= AcceptAllMulticast;
1041 csr6 |= AcceptAllMulticast;
1042 } else {
1043 u32 mc_filter[2] = {0, 0}; /* Multicast hash filter */
1044 int filterbit;
1045 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1046 i++, mclist = mclist->next) {
1047 if (tp->flags & COMET_MAC_ADDR)
1048 filterbit = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1049 else
1050 filterbit = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1051 filterbit &= 0x3f;
1052 mc_filter[filterbit >> 5] |= 1 << (filterbit & 31);
e174961c
JB		 1053 if (tulip_debug > 2)
1054 printk(KERN_INFO "%s: Added filter for %pM"
0795af57 1055 " %8.8x bit %d.\n",
e174961c 1056 dev->name, mclist->dmi_addr,
0795af57 1057 ether_crc(ETH_ALEN, mclist->dmi_addr), filterbit);
1da177e4
LT		 1058 }
1059 if (mc_filter[0] == tp->mc_filter[0] &&
1060 mc_filter[1] == tp->mc_filter[1])
1061 ; /* No change. */
1062 else if (tp->flags & IS_ASIX) {
1063 iowrite32(2, ioaddr + CSR13);
1064 iowrite32(mc_filter[0], ioaddr + CSR14);
1065 iowrite32(3, ioaddr + CSR13);
1066 iowrite32(mc_filter[1], ioaddr + CSR14);
1067 } else if (tp->flags & COMET_MAC_ADDR) {
1068 iowrite32(mc_filter[0], ioaddr + 0xAC);
1069 iowrite32(mc_filter[1], ioaddr + 0xB0);
1070 }
1071 tp->mc_filter[0] = mc_filter[0];
1072 tp->mc_filter[1] = mc_filter[1];
1073 }
1074 } else {
1075 unsigned long flags;
1076 u32 tx_flags = 0x08000000 | 192;
1077
1078 /* Note that only the low-address shortword of setup_frame is valid!
1079 The values are doubled for big-endian architectures. */
1080 if (dev->mc_count > 14) { /* Must use a multicast hash table. */
1081 build_setup_frame_hash(tp->setup_frame, dev);
1082 tx_flags = 0x08400000 | 192;
1083 } else {
1084 build_setup_frame_perfect(tp->setup_frame, dev);
1085 }
1086
1087 spin_lock_irqsave(&tp->lock, flags);
1088
1089 if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) {
1090 /* Same setup recently queued, we need not add it. */
1091 } else {
1092 unsigned int entry;
1093 int dummy = -1;
1094
1095 /* Now add this frame to the Tx list. */
1096
1097 entry = tp->cur_tx++ % TX_RING_SIZE;
1098
1099 if (entry != 0) {
ea8f400c
PC		 1100 /* Avoid a chip errata by prefixing a dummy entry. */
1101 tp->tx_buffers[entry].skb = NULL;
1102 tp->tx_buffers[entry].mapping = 0;
1103 tp->tx_ring[entry].length =
1104 (entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0;
1105 tp->tx_ring[entry].buffer1 = 0;
1106 /* Must set DescOwned later to avoid race with chip */
1107 dummy = entry;
1108 entry = tp->cur_tx++ % TX_RING_SIZE;
1109
1da177e4
LT		 1110 }
1111
1112 tp->tx_buffers[entry].skb = NULL;
1113 tp->tx_buffers[entry].mapping =
1114 pci_map_single(tp->pdev, tp->setup_frame,
1115 sizeof(tp->setup_frame),
1116 PCI_DMA_TODEVICE);
1117 /* Put the setup frame on the Tx list. */
1118 if (entry == TX_RING_SIZE-1)
1119 tx_flags |= DESC_RING_WRAP; /* Wrap ring. */
1120 tp->tx_ring[entry].length = cpu_to_le32(tx_flags);
1121 tp->tx_ring[entry].buffer1 =
1122 cpu_to_le32(tp->tx_buffers[entry].mapping);
1123 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
1124 if (dummy >= 0)
1125 tp->tx_ring[dummy].status = cpu_to_le32(DescOwned);
1126 if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2)
1127 netif_stop_queue(dev);
1128
1129 /* Trigger an immediate transmit demand. */
1130 iowrite32(0, ioaddr + CSR1);
1131 }
1132
1133 spin_unlock_irqrestore(&tp->lock, flags);
1134 }
1135
1136 iowrite32(csr6, ioaddr + CSR6);
1137}
1138
1139#ifdef CONFIG_TULIP_MWI
1140static void __devinit tulip_mwi_config (struct pci_dev *pdev,
1141 struct net_device *dev)
1142{
1143 struct tulip_private *tp = netdev_priv(dev);
1144 u8 cache;
1145 u16 pci_command;
1146 u32 csr0;
1147
1148 if (tulip_debug > 3)
1149 printk(KERN_DEBUG "%s: tulip_mwi_config()\n", pci_name(pdev));
1150
1151 tp->csr0 = csr0 = 0;
1152
10c64620
PH		 1153 /* if we have any cache line size at all, we can do MRM and MWI */
1154 csr0 |= MRM | MWI;
1da177e4 1155
10c64620
PH		 1156 /* Enable MWI in the standard PCI command bit.
1157 * Check for the case where MWI is desired but not available
1da177e4 1158 */
10c64620 1159 pci_try_set_mwi(pdev);
1da177e4
LT		 1160
1161 /* read result from hardware (in case bit refused to enable) */
1162 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1163 if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE)))
1164 csr0 &= ~MWI;
1165
1166 /* if cache line size hardwired to zero, no MWI */
1167 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
1168 if ((csr0 & MWI) && (cache == 0)) {
1169 csr0 &= ~MWI;
1170 pci_clear_mwi(pdev);
1171 }
1172
1173 /* assign per-cacheline-size cache alignment and
1174 * burst length values
1175 */
1176 switch (cache) {
1177 case 8:
1178 csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift);
1179 break;
1180 case 16:
1181 csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift);
1182 break;
1183 case 32:
1184 csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift);
1185 break;
1186 default:
1187 cache = 0;
1188 break;
1189 }
1190
1191 /* if we have a good cache line size, we by now have a good
1192 * csr0, so save it and exit
1193 */
1194 if (cache)
1195 goto out;
1196
1197 /* we don't have a good csr0 or cache line size, disable MWI */
1198 if (csr0 & MWI) {
1199 pci_clear_mwi(pdev);
1200 csr0 &= ~MWI;
1201 }
1202
1203 /* sane defaults for burst length and cache alignment
1204 * originally from de4x5 driver
1205 */
1206 csr0 |= (8 << BurstLenShift) | (1 << CALShift);
1207
1208out:
1209 tp->csr0 = csr0;
1210 if (tulip_debug > 2)
1211 printk(KERN_DEBUG "%s: MWI config cacheline=%d, csr0=%08x\n",
1212 pci_name(pdev), cache, csr0);
1213}
1214#endif
1215
1216/*
1217 * Chips that have the MRM/reserved bit quirk and the burst quirk. That
1218 * is the DM910X and the on chip ULi devices
1219 */
f3b197ac 1220
1da177e4
LT		 1221static int tulip_uli_dm_quirk(struct pci_dev *pdev)
1222{
1223 if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
1224 return 1;
1da177e4
LT		 1225 return 0;
1226}
1227
1228static int __devinit tulip_init_one (struct pci_dev *pdev,
1229 const struct pci_device_id *ent)
1230{
1231 struct tulip_private *tp;
1232 /* See note below on the multiport cards. */
1233 static unsigned char last_phys_addr[6] = {0x00, 'L', 'i', 'n', 'u', 'x'};
1234 static struct pci_device_id early_486_chipsets[] = {
1235 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) },
1236 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) },
1237 { },
1238 };
1239 static int last_irq;
1240 static int multiport_cnt; /* For four-port boards w/one EEPROM */
1da177e4
LT		 1241 int i, irq;
1242 unsigned short sum;
1243 unsigned char *ee_data;
1244 struct net_device *dev;
1245 void __iomem *ioaddr;
1246 static int board_idx = -1;
1247 int chip_idx = ent->driver_data;
1248 const char *chip_name = tulip_tbl[chip_idx].chip_name;
1249 unsigned int eeprom_missing = 0;
1250 unsigned int force_csr0 = 0;
1251
1252#ifndef MODULE
1253 static int did_version; /* Already printed version info. */
1254 if (tulip_debug > 0 && did_version++ == 0)
1255 printk (KERN_INFO "%s", version);
1256#endif
1257
1258 board_idx++;
1259
1260 /*
1261 * Lan media wire a tulip chip to a wan interface. Needs a very
1262 * different driver (lmc driver)
1263 */
1264
1265 if (pdev->subsystem_vendor == PCI_VENDOR_ID_LMC) {
1266 printk (KERN_ERR PFX "skipping LMC card.\n");
1267 return -ENODEV;
1268 }
1269
1270 /*
1271 * Early DM9100's need software CRC and the DMFE driver
1272 */
1273
1274 if (pdev->vendor == 0x1282 && pdev->device == 0x9100)
1275 {
1da177e4 1276 /* Read Chip revision */
8ca7ee6b 1277 if (pdev->revision < 0x30)
1da177e4
LT		 1278 {
1279 printk(KERN_ERR PFX "skipping early DM9100 with Crc bug (use dmfe)\n");
1280 return -ENODEV;
1281 }
1282 }
1283
1284 /*
1285 * Looks for early PCI chipsets where people report hangs
1286 * without the workarounds being on.
1287 */
1288
1289 /* 1. Intel Saturn. Switch to 8 long words burst, 8 long word cache
f3b197ac 1290 aligned. Aries might need this too. The Saturn errata are not
1da177e4
LT		 1291 pretty reading but thankfully it's an old 486 chipset.
1292
1293 2. The dreaded SiS496 486 chipset. Same workaround as Intel
1294 Saturn.
1295 */
1296
1297 if (pci_dev_present(early_486_chipsets)) {
1298 csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift);
1299 force_csr0 = 1;
1300 }
1301
1302 /* bugfix: the ASIX must have a burst limit or horrible things happen. */
1303 if (chip_idx == AX88140) {
1304 if ((csr0 & 0x3f00) == 0)
1305 csr0 |= 0x2000;
1306 }
1307
1308 /* PNIC doesn't have MWI/MRL/MRM... */
1309 if (chip_idx == LC82C168)
1310 csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */
1311
1312 /* DM9102A has troubles with MRM & clear reserved bits 24:22, 20, 16, 7:1 */
1313 if (tulip_uli_dm_quirk(pdev)) {
1314 csr0 &= ~0x01f100ff;
49345103 1315#if defined(CONFIG_SPARC)
1da177e4
LT		 1316 csr0 = (csr0 & ~0xff00) | 0xe000;
1317#endif
1318 }
1319 /*
1320 * And back to business
1321 */
1322
1323 i = pci_enable_device(pdev);
1324 if (i) {
1325 printk (KERN_ERR PFX
1326 "Cannot enable tulip board #%d, aborting\n",
1327 board_idx);
1328 return i;
1329 }
1330
1331 irq = pdev->irq;
1332
1333 /* alloc_etherdev ensures aligned and zeroed private structures */
1334 dev = alloc_etherdev (sizeof (*tp));
1335 if (!dev) {
1336 printk (KERN_ERR PFX "ether device alloc failed, aborting\n");
1337 return -ENOMEM;
1338 }
1339
1da177e4
LT		 1340 SET_NETDEV_DEV(dev, &pdev->dev);
1341 if (pci_resource_len (pdev, 0) < tulip_tbl[chip_idx].io_size) {
7c7459d1 1342 printk (KERN_ERR PFX "%s: I/O region (0x%llx@0x%llx) too small, "
1da177e4 1343 "aborting\n", pci_name(pdev),
7c7459d1
GKH		 1344 (unsigned long long)pci_resource_len (pdev, 0),
1345 (unsigned long long)pci_resource_start (pdev, 0));
1da177e4
LT		 1346 goto err_out_free_netdev;
1347 }
1348
1349 /* grab all resources from both PIO and MMIO regions, as we
1350 * don't want anyone else messing around with our hardware */
1351 if (pci_request_regions (pdev, "tulip"))
1352 goto err_out_free_netdev;
1353
7f2b1248
GG		 1354 ioaddr = pci_iomap(pdev, TULIP_BAR, tulip_tbl[chip_idx].io_size);
1355
1da177e4
LT		 1356 if (!ioaddr)
1357 goto err_out_free_res;
1358
1da177e4
LT		 1359 /*
1360 * initialize private data structure 'tp'
1361 * it is zeroed and aligned in alloc_etherdev
1362 */
1363 tp = netdev_priv(dev);
c4028958 1364 tp->dev = dev;
1da177e4
LT		 1365
1366 tp->rx_ring = pci_alloc_consistent(pdev,
1367 sizeof(struct tulip_rx_desc) * RX_RING_SIZE +
1368 sizeof(struct tulip_tx_desc) * TX_RING_SIZE,
1369 &tp->rx_ring_dma);
1370 if (!tp->rx_ring)
1371 goto err_out_mtable;
1372 tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE);
1373 tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE;
1374
1375 tp->chip_id = chip_idx;
1376 tp->flags = tulip_tbl[chip_idx].flags;
1377 tp->pdev = pdev;
1378 tp->base_addr = ioaddr;
44c10138 1379 tp->revision = pdev->revision;
1da177e4
LT		 1380 tp->csr0 = csr0;
1381 spin_lock_init(&tp->lock);
1382 spin_lock_init(&tp->mii_lock);
1383 init_timer(&tp->timer);
1384 tp->timer.data = (unsigned long)dev;
1385 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
1386
c4028958 1387 INIT_WORK(&tp->media_work, tulip_tbl[tp->chip_id].media_task);
0bb3cf72 1388
1da177e4
LT		 1389 dev->base_addr = (unsigned long)ioaddr;
1390
1391#ifdef CONFIG_TULIP_MWI
1392 if (!force_csr0 && (tp->flags & HAS_PCI_MWI))
1393 tulip_mwi_config (pdev, dev);
1da177e4
LT		 1394#endif
1395
1396 /* Stop the chip's Tx and Rx processes. */
1397 tulip_stop_rxtx(tp);
1398
1399 pci_set_master(pdev);
1400
1401#ifdef CONFIG_GSC
1402 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP) {
1403 switch (pdev->subsystem_device) {
1404 default:
1405 break;
1406 case 0x1061:
1407 case 0x1062:
1408 case 0x1063:
1409 case 0x1098:
1410 case 0x1099:
1411 case 0x10EE:
1412 tp->flags |= HAS_SWAPPED_SEEPROM | NEEDS_FAKE_MEDIA_TABLE;
1413 chip_name = "GSC DS21140 Tulip";
1414 }
1415 }
1416#endif
1417
1418 /* Clear the missed-packet counter. */
1419 ioread32(ioaddr + CSR8);
1420
1421 /* The station address ROM is read byte serially. The register must
1422 be polled, waiting for the value to be read bit serially from the
1423 EEPROM.
1424 */
1425 ee_data = tp->eeprom;
209261c0 1426 memset(ee_data, 0, sizeof(tp->eeprom));
1da177e4
LT		 1427 sum = 0;
1428 if (chip_idx == LC82C168) {
1429 for (i = 0; i < 3; i++) {
1430 int value, boguscnt = 100000;
1431 iowrite32(0x600 | i, ioaddr + 0x98);
1432 do
1433 value = ioread32(ioaddr + CSR9);
1434 while (value < 0 && --boguscnt > 0);
6caf52a4 1435 put_unaligned_le16(value, ((__le16 *)dev->dev_addr) + i);
1da177e4
LT		 1436 sum += value & 0xffff;
1437 }
1438 } else if (chip_idx == COMET) {
1439 /* No need to read the EEPROM. */
6caf52a4
HH		 1440 put_unaligned_le32(ioread32(ioaddr + 0xA4), dev->dev_addr);
1441 put_unaligned_le16(ioread32(ioaddr + 0xA8), dev->dev_addr + 4);
1da177e4
LT		 1442 for (i = 0; i < 6; i ++)
1443 sum += dev->dev_addr[i];
1444 } else {
1445 /* A serial EEPROM interface, we read now and sort it out later. */
1446 int sa_offset = 0;
1447 int ee_addr_size = tulip_read_eeprom(dev, 0xff, 8) & 0x40000 ? 8 : 6;
209261c0 1448 int ee_max_addr = ((1 << ee_addr_size) - 1) * sizeof(u16);
1da177e4 1449
209261c0
GG		 1450 if (ee_max_addr > sizeof(tp->eeprom))
1451 ee_max_addr = sizeof(tp->eeprom);
1452
1453 for (i = 0; i < ee_max_addr ; i += sizeof(u16)) {
1da177e4
LT		 1454 u16 data = tulip_read_eeprom(dev, i/2, ee_addr_size);
1455 ee_data[i] = data & 0xff;
1456 ee_data[i + 1] = data >> 8;
1457 }
1458
1459 /* DEC now has a specification (see Notes) but early board makers
1460 just put the address in the first EEPROM locations. */
1461 /* This does memcmp(ee_data, ee_data+16, 8) */
1462 for (i = 0; i < 8; i ++)
1463 if (ee_data[i] != ee_data[16+i])
1464 sa_offset = 20;
1465 if (chip_idx == CONEXANT) {
1466 /* Check that the tuple type and length is correct. */
1467 if (ee_data[0x198] == 0x04 && ee_data[0x199] == 6)
1468 sa_offset = 0x19A;
1469 } else if (ee_data[0] == 0xff && ee_data[1] == 0xff &&
1470 ee_data[2] == 0) {
1471 sa_offset = 2; /* Grrr, damn Matrox boards. */
1472 multiport_cnt = 4;
1473 }
1da177e4 1474#ifdef CONFIG_MIPS_COBALT
f3b197ac 1475 if ((pdev->bus->number == 0) &&
1da177e4
LT		 1476 ((PCI_SLOT(pdev->devfn) == 7) ||
1477 (PCI_SLOT(pdev->devfn) == 12))) {
1478 /* Cobalt MAC address in first EEPROM locations. */
1479 sa_offset = 0;
12755c16
RB		 1480 /* Ensure our media table fixup get's applied */
1481 memcpy(ee_data + 16, ee_data, 8);
1da177e4
LT		 1482 }
1483#endif
1484#ifdef CONFIG_GSC
1485 /* Check to see if we have a broken srom */
1486 if (ee_data[0] == 0x61 && ee_data[1] == 0x10) {
1487 /* pci_vendor_id and subsystem_id are swapped */
1488 ee_data[0] = ee_data[2];
1489 ee_data[1] = ee_data[3];
1490 ee_data[2] = 0x61;
1491 ee_data[3] = 0x10;
1492
1493 /* HSC-PCI boards need to be byte-swaped and shifted
1494 * up 1 word. This shift needs to happen at the end
1495 * of the MAC first because of the 2 byte overlap.
1496 */
1497 for (i = 4; i >= 0; i -= 2) {
1498 ee_data[17 + i + 3] = ee_data[17 + i];
1499 ee_data[16 + i + 5] = ee_data[16 + i];
1500 }
1501 }
1502#endif
1503
1504 for (i = 0; i < 6; i ++) {
1505 dev->dev_addr[i] = ee_data[i + sa_offset];
1506 sum += ee_data[i + sa_offset];
1507 }
1508 }
1509 /* Lite-On boards have the address byte-swapped. */
1510 if ((dev->dev_addr[0] == 0xA0 || dev->dev_addr[0] == 0xC0 || dev->dev_addr[0] == 0x02)
1511 && dev->dev_addr[1] == 0x00)
1512 for (i = 0; i < 6; i+=2) {
1513 char tmp = dev->dev_addr[i];
1514 dev->dev_addr[i] = dev->dev_addr[i+1];
1515 dev->dev_addr[i+1] = tmp;
1516 }
1517 /* On the Zynx 315 Etherarray and other multiport boards only the
1518 first Tulip has an EEPROM.
1519 On Sparc systems the mac address is held in the OBP property
1520 "local-mac-address".
1521 The addresses of the subsequent ports are derived from the first.
1522 Many PCI BIOSes also incorrectly report the IRQ line, so we correct
1523 that here as well. */
1524 if (sum == 0 || sum == 6*0xff) {
49345103 1525#if defined(CONFIG_SPARC)
d297c31f
DM		 1526 struct device_node *dp = pci_device_to_OF_node(pdev);
1527 const unsigned char *addr;
1528 int len;
1da177e4
LT		 1529#endif
1530 eeprom_missing = 1;
1531 for (i = 0; i < 5; i++)
1532 dev->dev_addr[i] = last_phys_addr[i];
1533 dev->dev_addr[i] = last_phys_addr[i] + 1;
49345103 1534#if defined(CONFIG_SPARC)
d297c31f
DM		 1535 addr = of_get_property(dp, "local-mac-address", &len);
1536 if (addr && len == 6)
1537 memcpy(dev->dev_addr, addr, 6);
1da177e4 1538#endif
b9c4c609 1539#if defined(__i386__) || defined(__x86_64__) /* Patch up x86 BIOS bug. */
1da177e4
LT		 1540 if (last_irq)
1541 irq = last_irq;
1542#endif
1543 }
1544
1545 for (i = 0; i < 6; i++)
1546 last_phys_addr[i] = dev->dev_addr[i];
1547 last_irq = irq;
1548 dev->irq = irq;
1549
1550 /* The lower four bits are the media type. */
1551 if (board_idx >= 0 && board_idx < MAX_UNITS) {
1552 if (options[board_idx] & MEDIA_MASK)
1553 tp->default_port = options[board_idx] & MEDIA_MASK;
1554 if ((options[board_idx] & FullDuplex) || full_duplex[board_idx] > 0)
1555 tp->full_duplex = 1;
1556 if (mtu[board_idx] > 0)
1557 dev->mtu = mtu[board_idx];
1558 }
1559 if (dev->mem_start & MEDIA_MASK)
1560 tp->default_port = dev->mem_start & MEDIA_MASK;
1561 if (tp->default_port) {
1562 printk(KERN_INFO "tulip%d: Transceiver selection forced to %s.\n",
1563 board_idx, medianame[tp->default_port & MEDIA_MASK]);
1564 tp->medialock = 1;
1565 if (tulip_media_cap[tp->default_port] & MediaAlwaysFD)
1566 tp->full_duplex = 1;
1567 }
1568 if (tp->full_duplex)
1569 tp->full_duplex_lock = 1;
1570
1571 if (tulip_media_cap[tp->default_port] & MediaIsMII) {
1572 u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200 };
1573 tp->mii_advertise = media2advert[tp->default_port - 9];
1574 tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */
1575 }
1576
1577 if (tp->flags & HAS_MEDIA_TABLE) {
1578 sprintf(dev->name, "tulip%d", board_idx); /* hack */
1579 tulip_parse_eeprom(dev);
1580 strcpy(dev->name, "eth%d"); /* un-hack */
1581 }
1582
1583 if ((tp->flags & ALWAYS_CHECK_MII) ||
1584 (tp->mtable && tp->mtable->has_mii) ||
1585 ( ! tp->mtable && (tp->flags & HAS_MII))) {
1586 if (tp->mtable && tp->mtable->has_mii) {
1587 for (i = 0; i < tp->mtable->leafcount; i++)
1588 if (tp->mtable->mleaf[i].media == 11) {
1589 tp->cur_index = i;
1590 tp->saved_if_port = dev->if_port;
1591 tulip_select_media(dev, 2);
1592 dev->if_port = tp->saved_if_port;
1593 break;
1594 }
1595 }
1596
1597 /* Find the connected MII xcvrs.
1598 Doing this in open() would allow detecting external xcvrs
1599 later, but takes much time. */
1600 tulip_find_mii (dev, board_idx);
1601 }
1602
1603 /* The Tulip-specific entries in the device structure. */
1604 dev->open = tulip_open;
1605 dev->hard_start_xmit = tulip_start_xmit;
1606 dev->tx_timeout = tulip_tx_timeout;
1607 dev->watchdog_timeo = TX_TIMEOUT;
1608#ifdef CONFIG_TULIP_NAPI
bea3348e 1609 netif_napi_add(dev, &tp->napi, tulip_poll, 16);
1da177e4
LT		 1610#endif
1611 dev->stop = tulip_close;
1612 dev->get_stats = tulip_get_stats;
1613 dev->do_ioctl = private_ioctl;
1614 dev->set_multicast_list = set_rx_mode;
1615#ifdef CONFIG_NET_POLL_CONTROLLER
1616 dev->poll_controller = &poll_tulip;
1617#endif
1618 SET_ETHTOOL_OPS(dev, &ops);
1619
1620 if (register_netdev(dev))
1621 goto err_out_free_ring;
1622
c69f4122
GG		 1623 printk(KERN_INFO "%s: %s rev %d at "
1624#ifdef CONFIG_TULIP_MMIO
1625 "MMIO"
1626#else
1627 "Port"
1628#endif
44c10138 1629 " %#llx,", dev->name, chip_name, pdev->revision,
c69f4122 1630 (unsigned long long) pci_resource_start(pdev, TULIP_BAR));
1da177e4
LT		 1631 pci_set_drvdata(pdev, dev);
1632
1633 if (eeprom_missing)
1634 printk(" EEPROM not present,");
e174961c 1635 printk(" %pM", dev->dev_addr);
1da177e4
LT		 1636 printk(", IRQ %d.\n", irq);
1637
1638 if (tp->chip_id == PNIC2)
1639 tp->link_change = pnic2_lnk_change;
1640 else if (tp->flags & HAS_NWAY)
1641 tp->link_change = t21142_lnk_change;
1642 else if (tp->flags & HAS_PNICNWAY)
1643 tp->link_change = pnic_lnk_change;
1644
1645 /* Reset the xcvr interface and turn on heartbeat. */
1646 switch (chip_idx) {
1647 case DC21140:
1648 case DM910X:
1da177e4
LT		 1649 default:
1650 if (tp->mtable)
1651 iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
1652 break;
1653 case DC21142:
1654 if (tp->mii_cnt || tulip_media_cap[dev->if_port] & MediaIsMII) {
1655 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
1656 iowrite32(0x0000, ioaddr + CSR13);
1657 iowrite32(0x0000, ioaddr + CSR14);
1658 iowrite32(csr6_mask_hdcap, ioaddr + CSR6);
1659 } else
1660 t21142_start_nway(dev);
1661 break;
1662 case PNIC2:
1663 /* just do a reset for sanity sake */
1664 iowrite32(0x0000, ioaddr + CSR13);
1665 iowrite32(0x0000, ioaddr + CSR14);
1666 break;
1667 case LC82C168:
1668 if ( ! tp->mii_cnt) {
1669 tp->nway = 1;
1670 tp->nwayset = 0;
1671 iowrite32(csr6_ttm | csr6_ca, ioaddr + CSR6);
1672 iowrite32(0x30, ioaddr + CSR12);
1673 iowrite32(0x0001F078, ioaddr + CSR6);
1674 iowrite32(0x0201F078, ioaddr + CSR6); /* Turn on autonegotiation. */
1675 }
1676 break;
1677 case MX98713:
1678 case COMPEX9881:
1679 iowrite32(0x00000000, ioaddr + CSR6);
1680 iowrite32(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */
1681 iowrite32(0x00000001, ioaddr + CSR13);
1682 break;
1683 case MX98715:
1684 case MX98725:
1685 iowrite32(0x01a80000, ioaddr + CSR6);
1686 iowrite32(0xFFFFFFFF, ioaddr + CSR14);
1687 iowrite32(0x00001000, ioaddr + CSR12);
1688 break;
1689 case COMET:
1690 /* No initialization necessary. */
1691 break;
1692 }
1693
1694 /* put the chip in snooze mode until opened */
1695 tulip_set_power_state (tp, 0, 1);
1696
1697 return 0;
1698
1699err_out_free_ring:
1700 pci_free_consistent (pdev,
1701 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1702 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1703 tp->rx_ring, tp->rx_ring_dma);
1704
1705err_out_mtable:
b4558ea9 1706 kfree (tp->mtable);
1da177e4
LT		 1707 pci_iounmap(pdev, ioaddr);
1708
1709err_out_free_res:
1710 pci_release_regions (pdev);
1711
1712err_out_free_netdev:
1713 free_netdev (dev);
1714 return -ENODEV;
1715}
1716
1717
1718#ifdef CONFIG_PM
1719
1720static int tulip_suspend (struct pci_dev *pdev, pm_message_t state)
1721{
1722 struct net_device *dev = pci_get_drvdata(pdev);
1723
1fe2cb32
AB		 1724 if (!dev)
1725 return -EINVAL;
1726
56997fa8
GG		 1727 if (!netif_running(dev))
1728 goto save_state;
1729
1730 tulip_down(dev);
1fe2cb32
AB		 1731
1732 netif_device_detach(dev);
1733 free_irq(dev->irq, dev);
1734
56997fa8 1735save_state:
1fe2cb32
AB		 1736 pci_save_state(pdev);
1737 pci_disable_device(pdev);
1738 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1739
1da177e4
LT		 1740 return 0;
1741}
1742
1743
1744static int tulip_resume(struct pci_dev *pdev)
1745{
1746 struct net_device *dev = pci_get_drvdata(pdev);
1fe2cb32 1747 int retval;
1da177e4 1748
1fe2cb32
AB		 1749 if (!dev)
1750 return -EINVAL;
1751
1752 pci_set_power_state(pdev, PCI_D0);
1753 pci_restore_state(pdev);
1754
56997fa8
GG		 1755 if (!netif_running(dev))
1756 return 0;
1757
9f486ae1
VH		 1758 if ((retval = pci_enable_device(pdev))) {
1759 printk (KERN_ERR "tulip: pci_enable_device failed in resume\n");
1760 return retval;
1761 }
1fe2cb32 1762
1fb9df5d 1763 if ((retval = request_irq(dev->irq, &tulip_interrupt, IRQF_SHARED, dev->name, dev))) {
1fe2cb32
AB		 1764 printk (KERN_ERR "tulip: request_irq failed in resume\n");
1765 return retval;
1da177e4 1766 }
1fe2cb32
AB		 1767
1768 netif_device_attach(dev);
1769
1770 if (netif_running(dev))
1771 tulip_up(dev);
1772
1da177e4
LT		 1773 return 0;
1774}
1775
1776#endif /* CONFIG_PM */
1777
1778
1779static void __devexit tulip_remove_one (struct pci_dev *pdev)
1780{
1781 struct net_device *dev = pci_get_drvdata (pdev);
1782 struct tulip_private *tp;
1783
1784 if (!dev)
1785 return;
1786
1787 tp = netdev_priv(dev);
1788 unregister_netdev(dev);
1789 pci_free_consistent (pdev,
1790 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1791 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1792 tp->rx_ring, tp->rx_ring_dma);
b4558ea9 1793 kfree (tp->mtable);
1da177e4
LT		 1794 pci_iounmap(pdev, tp->base_addr);
1795 free_netdev (dev);
1796 pci_release_regions (pdev);
1797 pci_set_drvdata (pdev, NULL);
1798
1799 /* pci_power_off (pdev, -1); */
1800}
1801
1802#ifdef CONFIG_NET_POLL_CONTROLLER
1803/*
1804 * Polling 'interrupt' - used by things like netconsole to send skbs
1805 * without having to re-enable interrupts. It's not called while
1806 * the interrupt routine is executing.
1807 */
1808
1809static void poll_tulip (struct net_device *dev)
1810{
1811 /* disable_irq here is not very nice, but with the lockless
1812 interrupt handler we have no other choice. */
1813 disable_irq(dev->irq);
7d12e780 1814 tulip_interrupt (dev->irq, dev);
1da177e4
LT		 1815 enable_irq(dev->irq);
1816}
1817#endif
1818
1819static struct pci_driver tulip_driver = {
1820 .name = DRV_NAME,
1821 .id_table = tulip_pci_tbl,
1822 .probe = tulip_init_one,
1823 .remove = __devexit_p(tulip_remove_one),
1824#ifdef CONFIG_PM
1825 .suspend = tulip_suspend,
1826 .resume = tulip_resume,
1827#endif /* CONFIG_PM */
1828};
1829
1830
1831static int __init tulip_init (void)
1832{
1833#ifdef MODULE
1834 printk (KERN_INFO "%s", version);
1835#endif
1836
1837 /* copy module parms into globals */
1838 tulip_rx_copybreak = rx_copybreak;
1839 tulip_max_interrupt_work = max_interrupt_work;
1840
1841 /* probe for and init boards */
29917620 1842 return pci_register_driver(&tulip_driver);
1da177e4
LT		 1843}
1844
1845
1846static void __exit tulip_cleanup (void)
1847{
1848 pci_unregister_driver (&tulip_driver);
1849}
1850
1851
1852module_init(tulip_init);
1853module_exit(tulip_cleanup);
Linux kernel - Deliverables
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