Commit | Line | Data |
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1da177e4 LT |
1 | /* winbond-840.c: A Linux PCI network adapter device driver. */ |
2 | /* | |
3 | Written 1998-2001 by Donald Becker. | |
4 | ||
5 | This software may be used and distributed according to the terms of | |
6 | the GNU General Public License (GPL), incorporated herein by reference. | |
7 | Drivers based on or derived from this code fall under the GPL and must | |
8 | retain the authorship, copyright and license notice. This file is not | |
9 | a complete program and may only be used when the entire operating | |
10 | system is licensed under the GPL. | |
11 | ||
12 | The author may be reached as becker@scyld.com, or C/O | |
13 | Scyld Computing Corporation | |
14 | 410 Severn Ave., Suite 210 | |
15 | Annapolis MD 21403 | |
16 | ||
17 | Support and updates available at | |
18 | http://www.scyld.com/network/drivers.html | |
19 | ||
20 | Do not remove the copyright information. | |
21 | Do not change the version information unless an improvement has been made. | |
22 | Merely removing my name, as Compex has done in the past, does not count | |
23 | as an improvement. | |
24 | ||
25 | Changelog: | |
26 | * ported to 2.4 | |
27 | ??? | |
28 | * spin lock update, memory barriers, new style dma mappings | |
29 | limit each tx buffer to < 1024 bytes | |
30 | remove DescIntr from Rx descriptors (that's an Tx flag) | |
31 | remove next pointer from Tx descriptors | |
32 | synchronize tx_q_bytes | |
33 | software reset in tx_timeout | |
34 | Copyright (C) 2000 Manfred Spraul | |
35 | * further cleanups | |
36 | power management. | |
37 | support for big endian descriptors | |
38 | Copyright (C) 2001 Manfred Spraul | |
39 | * ethtool support (jgarzik) | |
40 | * Replace some MII-related magic numbers with constants (jgarzik) | |
f3b197ac | 41 | |
1da177e4 LT |
42 | TODO: |
43 | * enable pci_power_off | |
44 | * Wake-On-LAN | |
45 | */ | |
f3b197ac | 46 | |
1da177e4 | 47 | #define DRV_NAME "winbond-840" |
d5b20697 AG |
48 | #define DRV_VERSION "1.01-e" |
49 | #define DRV_RELDATE "Sep-11-2006" | |
1da177e4 LT |
50 | |
51 | ||
52 | /* Automatically extracted configuration info: | |
53 | probe-func: winbond840_probe | |
54 | config-in: tristate 'Winbond W89c840 Ethernet support' CONFIG_WINBOND_840 | |
55 | ||
56 | c-help-name: Winbond W89c840 PCI Ethernet support | |
57 | c-help-symbol: CONFIG_WINBOND_840 | |
58 | c-help: This driver is for the Winbond W89c840 chip. It also works with | |
59 | c-help: the TX9882 chip on the Compex RL100-ATX board. | |
f3b197ac | 60 | c-help: More specific information and updates are available from |
1da177e4 LT |
61 | c-help: http://www.scyld.com/network/drivers.html |
62 | */ | |
63 | ||
64 | /* The user-configurable values. | |
65 | These may be modified when a driver module is loaded.*/ | |
66 | ||
67 | static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */ | |
68 | static int max_interrupt_work = 20; | |
69 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). | |
70 | The '840 uses a 64 element hash table based on the Ethernet CRC. */ | |
71 | static int multicast_filter_limit = 32; | |
72 | ||
73 | /* Set the copy breakpoint for the copy-only-tiny-frames scheme. | |
74 | Setting to > 1518 effectively disables this feature. */ | |
75 | static int rx_copybreak; | |
76 | ||
77 | /* Used to pass the media type, etc. | |
78 | Both 'options[]' and 'full_duplex[]' should exist for driver | |
79 | interoperability. | |
80 | The media type is usually passed in 'options[]'. | |
81 | */ | |
82 | #define MAX_UNITS 8 /* More are supported, limit only on options */ | |
83 | static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; | |
84 | static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; | |
85 | ||
86 | /* Operational parameters that are set at compile time. */ | |
87 | ||
88 | /* Keep the ring sizes a power of two for compile efficiency. | |
89 | The compiler will convert <unsigned>'%'<2^N> into a bit mask. | |
90 | Making the Tx ring too large decreases the effectiveness of channel | |
91 | bonding and packet priority. | |
92 | There are no ill effects from too-large receive rings. */ | |
1da177e4 LT |
93 | #define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */ |
94 | #define TX_QUEUE_LEN_RESTART 5 | |
1da177e4 LT |
95 | |
96 | #define TX_BUFLIMIT (1024-128) | |
97 | ||
98 | /* The presumed FIFO size for working around the Tx-FIFO-overflow bug. | |
99 | To avoid overflowing we don't queue again until we have room for a | |
100 | full-size packet. | |
101 | */ | |
102 | #define TX_FIFO_SIZE (2048) | |
103 | #define TX_BUG_FIFO_LIMIT (TX_FIFO_SIZE-1514-16) | |
104 | ||
105 | ||
106 | /* Operational parameters that usually are not changed. */ | |
107 | /* Time in jiffies before concluding the transmitter is hung. */ | |
108 | #define TX_TIMEOUT (2*HZ) | |
109 | ||
1da177e4 LT |
110 | /* Include files, designed to support most kernel versions 2.0.0 and later. */ |
111 | #include <linux/module.h> | |
112 | #include <linux/kernel.h> | |
113 | #include <linux/string.h> | |
114 | #include <linux/timer.h> | |
115 | #include <linux/errno.h> | |
116 | #include <linux/ioport.h> | |
117 | #include <linux/slab.h> | |
118 | #include <linux/interrupt.h> | |
119 | #include <linux/pci.h> | |
10a87fcf | 120 | #include <linux/dma-mapping.h> |
1da177e4 LT |
121 | #include <linux/netdevice.h> |
122 | #include <linux/etherdevice.h> | |
123 | #include <linux/skbuff.h> | |
124 | #include <linux/init.h> | |
125 | #include <linux/delay.h> | |
126 | #include <linux/ethtool.h> | |
127 | #include <linux/mii.h> | |
128 | #include <linux/rtnetlink.h> | |
129 | #include <linux/crc32.h> | |
130 | #include <linux/bitops.h> | |
131 | #include <asm/uaccess.h> | |
132 | #include <asm/processor.h> /* Processor type for cache alignment. */ | |
133 | #include <asm/io.h> | |
134 | #include <asm/irq.h> | |
135 | ||
42eab567 GG |
136 | #include "tulip.h" |
137 | ||
48dd59e3 JG |
138 | #undef PKT_BUF_SZ /* tulip.h also defines this */ |
139 | #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ | |
140 | ||
1da177e4 | 141 | /* These identify the driver base version and may not be removed. */ |
c9d26c97 | 142 | static char version[] = |
1da177e4 LT |
143 | KERN_INFO DRV_NAME ".c:v" DRV_VERSION " (2.4 port) " DRV_RELDATE " Donald Becker <becker@scyld.com>\n" |
144 | KERN_INFO " http://www.scyld.com/network/drivers.html\n"; | |
145 | ||
146 | MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); | |
147 | MODULE_DESCRIPTION("Winbond W89c840 Ethernet driver"); | |
148 | MODULE_LICENSE("GPL"); | |
149 | MODULE_VERSION(DRV_VERSION); | |
150 | ||
151 | module_param(max_interrupt_work, int, 0); | |
152 | module_param(debug, int, 0); | |
153 | module_param(rx_copybreak, int, 0); | |
154 | module_param(multicast_filter_limit, int, 0); | |
155 | module_param_array(options, int, NULL, 0); | |
156 | module_param_array(full_duplex, int, NULL, 0); | |
157 | MODULE_PARM_DESC(max_interrupt_work, "winbond-840 maximum events handled per interrupt"); | |
158 | MODULE_PARM_DESC(debug, "winbond-840 debug level (0-6)"); | |
159 | MODULE_PARM_DESC(rx_copybreak, "winbond-840 copy breakpoint for copy-only-tiny-frames"); | |
160 | MODULE_PARM_DESC(multicast_filter_limit, "winbond-840 maximum number of filtered multicast addresses"); | |
161 | MODULE_PARM_DESC(options, "winbond-840: Bits 0-3: media type, bit 17: full duplex"); | |
162 | MODULE_PARM_DESC(full_duplex, "winbond-840 full duplex setting(s) (1)"); | |
163 | ||
164 | /* | |
165 | Theory of Operation | |
166 | ||
167 | I. Board Compatibility | |
168 | ||
169 | This driver is for the Winbond w89c840 chip. | |
170 | ||
171 | II. Board-specific settings | |
172 | ||
173 | None. | |
174 | ||
175 | III. Driver operation | |
176 | ||
177 | This chip is very similar to the Digital 21*4* "Tulip" family. The first | |
178 | twelve registers and the descriptor format are nearly identical. Read a | |
179 | Tulip manual for operational details. | |
180 | ||
181 | A significant difference is that the multicast filter and station address are | |
182 | stored in registers rather than loaded through a pseudo-transmit packet. | |
183 | ||
184 | Unlike the Tulip, transmit buffers are limited to 1KB. To transmit a | |
185 | full-sized packet we must use both data buffers in a descriptor. Thus the | |
186 | driver uses ring mode where descriptors are implicitly sequential in memory, | |
187 | rather than using the second descriptor address as a chain pointer to | |
188 | subsequent descriptors. | |
189 | ||
190 | IV. Notes | |
191 | ||
192 | If you are going to almost clone a Tulip, why not go all the way and avoid | |
193 | the need for a new driver? | |
194 | ||
195 | IVb. References | |
196 | ||
197 | http://www.scyld.com/expert/100mbps.html | |
198 | http://www.scyld.com/expert/NWay.html | |
199 | http://www.winbond.com.tw/ | |
200 | ||
201 | IVc. Errata | |
202 | ||
203 | A horrible bug exists in the transmit FIFO. Apparently the chip doesn't | |
204 | correctly detect a full FIFO, and queuing more than 2048 bytes may result in | |
205 | silent data corruption. | |
206 | ||
207 | Test with 'ping -s 10000' on a fast computer. | |
208 | ||
209 | */ | |
210 | ||
f3b197ac | 211 | |
1da177e4 LT |
212 | |
213 | /* | |
214 | PCI probe table. | |
215 | */ | |
1da177e4 | 216 | enum chip_capability_flags { |
1f1bd5fc JG |
217 | CanHaveMII=1, HasBrokenTx=2, AlwaysFDX=4, FDXOnNoMII=8, |
218 | }; | |
219 | ||
220 | static const struct pci_device_id w840_pci_tbl[] = { | |
1da177e4 LT |
221 | { 0x1050, 0x0840, PCI_ANY_ID, 0x8153, 0, 0, 0 }, |
222 | { 0x1050, 0x0840, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 }, | |
223 | { 0x11f6, 0x2011, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 }, | |
1f1bd5fc | 224 | { } |
1da177e4 LT |
225 | }; |
226 | MODULE_DEVICE_TABLE(pci, w840_pci_tbl); | |
227 | ||
c3d8e682 JG |
228 | enum { |
229 | netdev_res_size = 128, /* size of PCI BAR resource */ | |
230 | }; | |
231 | ||
1da177e4 LT |
232 | struct pci_id_info { |
233 | const char *name; | |
c3d8e682 | 234 | int drv_flags; /* Driver use, intended as capability flags. */ |
1da177e4 | 235 | }; |
c3d8e682 JG |
236 | |
237 | static const struct pci_id_info pci_id_tbl[] __devinitdata = { | |
238 | { /* Sometime a Level-One switch card. */ | |
239 | "Winbond W89c840", CanHaveMII | HasBrokenTx | FDXOnNoMII}, | |
240 | { "Winbond W89c840", CanHaveMII | HasBrokenTx}, | |
241 | { "Compex RL100-ATX", CanHaveMII | HasBrokenTx}, | |
242 | { } /* terminate list. */ | |
1da177e4 LT |
243 | }; |
244 | ||
245 | /* This driver was written to use PCI memory space, however some x86 systems | |
42eab567 GG |
246 | work only with I/O space accesses. See CONFIG_TULIP_MMIO in .config |
247 | */ | |
1da177e4 LT |
248 | |
249 | /* Offsets to the Command and Status Registers, "CSRs". | |
250 | While similar to the Tulip, these registers are longword aligned. | |
251 | Note: It's not useful to define symbolic names for every register bit in | |
252 | the device. The name can only partially document the semantics and make | |
253 | the driver longer and more difficult to read. | |
254 | */ | |
255 | enum w840_offsets { | |
256 | PCIBusCfg=0x00, TxStartDemand=0x04, RxStartDemand=0x08, | |
257 | RxRingPtr=0x0C, TxRingPtr=0x10, | |
258 | IntrStatus=0x14, NetworkConfig=0x18, IntrEnable=0x1C, | |
259 | RxMissed=0x20, EECtrl=0x24, MIICtrl=0x24, BootRom=0x28, GPTimer=0x2C, | |
260 | CurRxDescAddr=0x30, CurRxBufAddr=0x34, /* Debug use */ | |
261 | MulticastFilter0=0x38, MulticastFilter1=0x3C, StationAddr=0x40, | |
262 | CurTxDescAddr=0x4C, CurTxBufAddr=0x50, | |
263 | }; | |
264 | ||
1da177e4 LT |
265 | /* Bits in the NetworkConfig register. */ |
266 | enum rx_mode_bits { | |
42eab567 GG |
267 | AcceptErr=0x80, |
268 | RxAcceptBroadcast=0x20, AcceptMulticast=0x10, | |
269 | RxAcceptAllPhys=0x08, AcceptMyPhys=0x02, | |
1da177e4 LT |
270 | }; |
271 | ||
272 | enum mii_reg_bits { | |
273 | MDIO_ShiftClk=0x10000, MDIO_DataIn=0x80000, MDIO_DataOut=0x20000, | |
274 | MDIO_EnbOutput=0x40000, MDIO_EnbIn = 0x00000, | |
275 | }; | |
276 | ||
277 | /* The Tulip Rx and Tx buffer descriptors. */ | |
278 | struct w840_rx_desc { | |
279 | s32 status; | |
280 | s32 length; | |
281 | u32 buffer1; | |
282 | u32 buffer2; | |
283 | }; | |
284 | ||
285 | struct w840_tx_desc { | |
286 | s32 status; | |
287 | s32 length; | |
288 | u32 buffer1, buffer2; | |
289 | }; | |
290 | ||
1da177e4 LT |
291 | #define MII_CNT 1 /* winbond only supports one MII */ |
292 | struct netdev_private { | |
293 | struct w840_rx_desc *rx_ring; | |
294 | dma_addr_t rx_addr[RX_RING_SIZE]; | |
295 | struct w840_tx_desc *tx_ring; | |
296 | dma_addr_t tx_addr[TX_RING_SIZE]; | |
297 | dma_addr_t ring_dma_addr; | |
298 | /* The addresses of receive-in-place skbuffs. */ | |
299 | struct sk_buff* rx_skbuff[RX_RING_SIZE]; | |
300 | /* The saved address of a sent-in-place packet/buffer, for later free(). */ | |
301 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; | |
302 | struct net_device_stats stats; | |
303 | struct timer_list timer; /* Media monitoring timer. */ | |
304 | /* Frequently used values: keep some adjacent for cache effect. */ | |
305 | spinlock_t lock; | |
306 | int chip_id, drv_flags; | |
307 | struct pci_dev *pci_dev; | |
308 | int csr6; | |
309 | struct w840_rx_desc *rx_head_desc; | |
310 | unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */ | |
311 | unsigned int rx_buf_sz; /* Based on MTU+slack. */ | |
312 | unsigned int cur_tx, dirty_tx; | |
313 | unsigned int tx_q_bytes; | |
314 | unsigned int tx_full; /* The Tx queue is full. */ | |
315 | /* MII transceiver section. */ | |
316 | int mii_cnt; /* MII device addresses. */ | |
317 | unsigned char phys[MII_CNT]; /* MII device addresses, but only the first is used */ | |
318 | u32 mii; | |
319 | struct mii_if_info mii_if; | |
320 | void __iomem *base_addr; | |
321 | }; | |
322 | ||
323 | static int eeprom_read(void __iomem *ioaddr, int location); | |
324 | static int mdio_read(struct net_device *dev, int phy_id, int location); | |
325 | static void mdio_write(struct net_device *dev, int phy_id, int location, int value); | |
326 | static int netdev_open(struct net_device *dev); | |
327 | static int update_link(struct net_device *dev); | |
328 | static void netdev_timer(unsigned long data); | |
329 | static void init_rxtx_rings(struct net_device *dev); | |
330 | static void free_rxtx_rings(struct netdev_private *np); | |
331 | static void init_registers(struct net_device *dev); | |
332 | static void tx_timeout(struct net_device *dev); | |
333 | static int alloc_ringdesc(struct net_device *dev); | |
334 | static void free_ringdesc(struct netdev_private *np); | |
335 | static int start_tx(struct sk_buff *skb, struct net_device *dev); | |
7d12e780 | 336 | static irqreturn_t intr_handler(int irq, void *dev_instance); |
1da177e4 LT |
337 | static void netdev_error(struct net_device *dev, int intr_status); |
338 | static int netdev_rx(struct net_device *dev); | |
339 | static u32 __set_rx_mode(struct net_device *dev); | |
340 | static void set_rx_mode(struct net_device *dev); | |
341 | static struct net_device_stats *get_stats(struct net_device *dev); | |
342 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
7282d491 | 343 | static const struct ethtool_ops netdev_ethtool_ops; |
1da177e4 LT |
344 | static int netdev_close(struct net_device *dev); |
345 | ||
f3b197ac | 346 | |
1da177e4 LT |
347 | |
348 | static int __devinit w840_probe1 (struct pci_dev *pdev, | |
349 | const struct pci_device_id *ent) | |
350 | { | |
351 | struct net_device *dev; | |
352 | struct netdev_private *np; | |
353 | static int find_cnt; | |
354 | int chip_idx = ent->driver_data; | |
355 | int irq; | |
356 | int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0; | |
357 | void __iomem *ioaddr; | |
0795af57 | 358 | DECLARE_MAC_BUF(mac); |
1da177e4 LT |
359 | |
360 | i = pci_enable_device(pdev); | |
361 | if (i) return i; | |
362 | ||
363 | pci_set_master(pdev); | |
364 | ||
365 | irq = pdev->irq; | |
366 | ||
10a87fcf | 367 | if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) { |
1da177e4 LT |
368 | printk(KERN_WARNING "Winbond-840: Device %s disabled due to DMA limitations.\n", |
369 | pci_name(pdev)); | |
370 | return -EIO; | |
371 | } | |
372 | dev = alloc_etherdev(sizeof(*np)); | |
373 | if (!dev) | |
374 | return -ENOMEM; | |
1da177e4 LT |
375 | SET_NETDEV_DEV(dev, &pdev->dev); |
376 | ||
377 | if (pci_request_regions(pdev, DRV_NAME)) | |
378 | goto err_out_netdev; | |
42eab567 GG |
379 | |
380 | ioaddr = pci_iomap(pdev, TULIP_BAR, netdev_res_size); | |
1da177e4 LT |
381 | if (!ioaddr) |
382 | goto err_out_free_res; | |
383 | ||
384 | for (i = 0; i < 3; i++) | |
c559a5bc | 385 | ((__le16 *)dev->dev_addr)[i] = cpu_to_le16(eeprom_read(ioaddr, i)); |
1da177e4 LT |
386 | |
387 | /* Reset the chip to erase previous misconfiguration. | |
388 | No hold time required! */ | |
389 | iowrite32(0x00000001, ioaddr + PCIBusCfg); | |
390 | ||
391 | dev->base_addr = (unsigned long)ioaddr; | |
392 | dev->irq = irq; | |
393 | ||
394 | np = netdev_priv(dev); | |
395 | np->pci_dev = pdev; | |
396 | np->chip_id = chip_idx; | |
397 | np->drv_flags = pci_id_tbl[chip_idx].drv_flags; | |
398 | spin_lock_init(&np->lock); | |
399 | np->mii_if.dev = dev; | |
400 | np->mii_if.mdio_read = mdio_read; | |
401 | np->mii_if.mdio_write = mdio_write; | |
402 | np->base_addr = ioaddr; | |
f3b197ac | 403 | |
1da177e4 LT |
404 | pci_set_drvdata(pdev, dev); |
405 | ||
406 | if (dev->mem_start) | |
407 | option = dev->mem_start; | |
408 | ||
409 | /* The lower four bits are the media type. */ | |
410 | if (option > 0) { | |
411 | if (option & 0x200) | |
412 | np->mii_if.full_duplex = 1; | |
413 | if (option & 15) | |
414 | printk(KERN_INFO "%s: ignoring user supplied media type %d", | |
415 | dev->name, option & 15); | |
416 | } | |
417 | if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0) | |
418 | np->mii_if.full_duplex = 1; | |
419 | ||
420 | if (np->mii_if.full_duplex) | |
421 | np->mii_if.force_media = 1; | |
422 | ||
423 | /* The chip-specific entries in the device structure. */ | |
424 | dev->open = &netdev_open; | |
425 | dev->hard_start_xmit = &start_tx; | |
426 | dev->stop = &netdev_close; | |
427 | dev->get_stats = &get_stats; | |
428 | dev->set_multicast_list = &set_rx_mode; | |
429 | dev->do_ioctl = &netdev_ioctl; | |
430 | dev->ethtool_ops = &netdev_ethtool_ops; | |
431 | dev->tx_timeout = &tx_timeout; | |
432 | dev->watchdog_timeo = TX_TIMEOUT; | |
433 | ||
434 | i = register_netdev(dev); | |
435 | if (i) | |
436 | goto err_out_cleardev; | |
437 | ||
0795af57 JP |
438 | printk(KERN_INFO "%s: %s at %p, %s, IRQ %d.\n", |
439 | dev->name, pci_id_tbl[chip_idx].name, ioaddr, | |
440 | print_mac(mac, dev->dev_addr), irq); | |
1da177e4 LT |
441 | |
442 | if (np->drv_flags & CanHaveMII) { | |
443 | int phy, phy_idx = 0; | |
444 | for (phy = 1; phy < 32 && phy_idx < MII_CNT; phy++) { | |
445 | int mii_status = mdio_read(dev, phy, MII_BMSR); | |
446 | if (mii_status != 0xffff && mii_status != 0x0000) { | |
447 | np->phys[phy_idx++] = phy; | |
448 | np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE); | |
449 | np->mii = (mdio_read(dev, phy, MII_PHYSID1) << 16)+ | |
450 | mdio_read(dev, phy, MII_PHYSID2); | |
451 | printk(KERN_INFO "%s: MII PHY %8.8xh found at address %d, status " | |
452 | "0x%4.4x advertising %4.4x.\n", | |
453 | dev->name, np->mii, phy, mii_status, np->mii_if.advertising); | |
454 | } | |
455 | } | |
456 | np->mii_cnt = phy_idx; | |
457 | np->mii_if.phy_id = np->phys[0]; | |
458 | if (phy_idx == 0) { | |
459 | printk(KERN_WARNING "%s: MII PHY not found -- this device may " | |
460 | "not operate correctly.\n", dev->name); | |
461 | } | |
462 | } | |
463 | ||
464 | find_cnt++; | |
465 | return 0; | |
466 | ||
467 | err_out_cleardev: | |
468 | pci_set_drvdata(pdev, NULL); | |
469 | pci_iounmap(pdev, ioaddr); | |
470 | err_out_free_res: | |
471 | pci_release_regions(pdev); | |
472 | err_out_netdev: | |
473 | free_netdev (dev); | |
474 | return -ENODEV; | |
475 | } | |
476 | ||
f3b197ac | 477 | |
1da177e4 LT |
478 | /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. These are |
479 | often serial bit streams generated by the host processor. | |
480 | The example below is for the common 93c46 EEPROM, 64 16 bit words. */ | |
481 | ||
482 | /* Delay between EEPROM clock transitions. | |
483 | No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need | |
484 | a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that | |
485 | made udelay() unreliable. | |
486 | The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is | |
405bbe9f | 487 | deprecated. |
1da177e4 LT |
488 | */ |
489 | #define eeprom_delay(ee_addr) ioread32(ee_addr) | |
490 | ||
491 | enum EEPROM_Ctrl_Bits { | |
492 | EE_ShiftClk=0x02, EE_Write0=0x801, EE_Write1=0x805, | |
493 | EE_ChipSelect=0x801, EE_DataIn=0x08, | |
494 | }; | |
495 | ||
496 | /* The EEPROM commands include the alway-set leading bit. */ | |
497 | enum EEPROM_Cmds { | |
498 | EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6), | |
499 | }; | |
500 | ||
501 | static int eeprom_read(void __iomem *addr, int location) | |
502 | { | |
503 | int i; | |
504 | int retval = 0; | |
505 | void __iomem *ee_addr = addr + EECtrl; | |
506 | int read_cmd = location | EE_ReadCmd; | |
507 | iowrite32(EE_ChipSelect, ee_addr); | |
508 | ||
509 | /* Shift the read command bits out. */ | |
510 | for (i = 10; i >= 0; i--) { | |
511 | short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0; | |
512 | iowrite32(dataval, ee_addr); | |
513 | eeprom_delay(ee_addr); | |
514 | iowrite32(dataval | EE_ShiftClk, ee_addr); | |
515 | eeprom_delay(ee_addr); | |
516 | } | |
517 | iowrite32(EE_ChipSelect, ee_addr); | |
518 | eeprom_delay(ee_addr); | |
519 | ||
520 | for (i = 16; i > 0; i--) { | |
521 | iowrite32(EE_ChipSelect | EE_ShiftClk, ee_addr); | |
522 | eeprom_delay(ee_addr); | |
523 | retval = (retval << 1) | ((ioread32(ee_addr) & EE_DataIn) ? 1 : 0); | |
524 | iowrite32(EE_ChipSelect, ee_addr); | |
525 | eeprom_delay(ee_addr); | |
526 | } | |
527 | ||
528 | /* Terminate the EEPROM access. */ | |
529 | iowrite32(0, ee_addr); | |
530 | return retval; | |
531 | } | |
532 | ||
533 | /* MII transceiver control section. | |
534 | Read and write the MII registers using software-generated serial | |
535 | MDIO protocol. See the MII specifications or DP83840A data sheet | |
536 | for details. | |
537 | ||
538 | The maximum data clock rate is 2.5 Mhz. The minimum timing is usually | |
539 | met by back-to-back 33Mhz PCI cycles. */ | |
540 | #define mdio_delay(mdio_addr) ioread32(mdio_addr) | |
541 | ||
542 | /* Set iff a MII transceiver on any interface requires mdio preamble. | |
543 | This only set with older transceivers, so the extra | |
544 | code size of a per-interface flag is not worthwhile. */ | |
545 | static char mii_preamble_required = 1; | |
546 | ||
547 | #define MDIO_WRITE0 (MDIO_EnbOutput) | |
548 | #define MDIO_WRITE1 (MDIO_DataOut | MDIO_EnbOutput) | |
549 | ||
550 | /* Generate the preamble required for initial synchronization and | |
551 | a few older transceivers. */ | |
552 | static void mdio_sync(void __iomem *mdio_addr) | |
553 | { | |
554 | int bits = 32; | |
555 | ||
556 | /* Establish sync by sending at least 32 logic ones. */ | |
557 | while (--bits >= 0) { | |
558 | iowrite32(MDIO_WRITE1, mdio_addr); | |
559 | mdio_delay(mdio_addr); | |
560 | iowrite32(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr); | |
561 | mdio_delay(mdio_addr); | |
562 | } | |
563 | } | |
564 | ||
565 | static int mdio_read(struct net_device *dev, int phy_id, int location) | |
566 | { | |
567 | struct netdev_private *np = netdev_priv(dev); | |
568 | void __iomem *mdio_addr = np->base_addr + MIICtrl; | |
569 | int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location; | |
570 | int i, retval = 0; | |
571 | ||
572 | if (mii_preamble_required) | |
573 | mdio_sync(mdio_addr); | |
574 | ||
575 | /* Shift the read command bits out. */ | |
576 | for (i = 15; i >= 0; i--) { | |
577 | int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; | |
578 | ||
579 | iowrite32(dataval, mdio_addr); | |
580 | mdio_delay(mdio_addr); | |
581 | iowrite32(dataval | MDIO_ShiftClk, mdio_addr); | |
582 | mdio_delay(mdio_addr); | |
583 | } | |
584 | /* Read the two transition, 16 data, and wire-idle bits. */ | |
585 | for (i = 20; i > 0; i--) { | |
586 | iowrite32(MDIO_EnbIn, mdio_addr); | |
587 | mdio_delay(mdio_addr); | |
588 | retval = (retval << 1) | ((ioread32(mdio_addr) & MDIO_DataIn) ? 1 : 0); | |
589 | iowrite32(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr); | |
590 | mdio_delay(mdio_addr); | |
591 | } | |
592 | return (retval>>1) & 0xffff; | |
593 | } | |
594 | ||
595 | static void mdio_write(struct net_device *dev, int phy_id, int location, int value) | |
596 | { | |
597 | struct netdev_private *np = netdev_priv(dev); | |
598 | void __iomem *mdio_addr = np->base_addr + MIICtrl; | |
599 | int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value; | |
600 | int i; | |
601 | ||
602 | if (location == 4 && phy_id == np->phys[0]) | |
603 | np->mii_if.advertising = value; | |
604 | ||
605 | if (mii_preamble_required) | |
606 | mdio_sync(mdio_addr); | |
607 | ||
608 | /* Shift the command bits out. */ | |
609 | for (i = 31; i >= 0; i--) { | |
610 | int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; | |
611 | ||
612 | iowrite32(dataval, mdio_addr); | |
613 | mdio_delay(mdio_addr); | |
614 | iowrite32(dataval | MDIO_ShiftClk, mdio_addr); | |
615 | mdio_delay(mdio_addr); | |
616 | } | |
617 | /* Clear out extra bits. */ | |
618 | for (i = 2; i > 0; i--) { | |
619 | iowrite32(MDIO_EnbIn, mdio_addr); | |
620 | mdio_delay(mdio_addr); | |
621 | iowrite32(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr); | |
622 | mdio_delay(mdio_addr); | |
623 | } | |
624 | return; | |
625 | } | |
626 | ||
f3b197ac | 627 | |
1da177e4 LT |
628 | static int netdev_open(struct net_device *dev) |
629 | { | |
630 | struct netdev_private *np = netdev_priv(dev); | |
631 | void __iomem *ioaddr = np->base_addr; | |
632 | int i; | |
633 | ||
634 | iowrite32(0x00000001, ioaddr + PCIBusCfg); /* Reset */ | |
635 | ||
636 | netif_device_detach(dev); | |
1fb9df5d | 637 | i = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev); |
1da177e4 LT |
638 | if (i) |
639 | goto out_err; | |
640 | ||
641 | if (debug > 1) | |
642 | printk(KERN_DEBUG "%s: w89c840_open() irq %d.\n", | |
643 | dev->name, dev->irq); | |
644 | ||
645 | if((i=alloc_ringdesc(dev))) | |
646 | goto out_err; | |
647 | ||
648 | spin_lock_irq(&np->lock); | |
649 | netif_device_attach(dev); | |
650 | init_registers(dev); | |
651 | spin_unlock_irq(&np->lock); | |
652 | ||
653 | netif_start_queue(dev); | |
654 | if (debug > 2) | |
655 | printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name); | |
656 | ||
657 | /* Set the timer to check for link beat. */ | |
658 | init_timer(&np->timer); | |
659 | np->timer.expires = jiffies + 1*HZ; | |
660 | np->timer.data = (unsigned long)dev; | |
661 | np->timer.function = &netdev_timer; /* timer handler */ | |
662 | add_timer(&np->timer); | |
663 | return 0; | |
664 | out_err: | |
665 | netif_device_attach(dev); | |
666 | return i; | |
667 | } | |
668 | ||
669 | #define MII_DAVICOM_DM9101 0x0181b800 | |
670 | ||
671 | static int update_link(struct net_device *dev) | |
672 | { | |
673 | struct netdev_private *np = netdev_priv(dev); | |
674 | int duplex, fasteth, result, mii_reg; | |
675 | ||
676 | /* BSMR */ | |
677 | mii_reg = mdio_read(dev, np->phys[0], MII_BMSR); | |
678 | ||
679 | if (mii_reg == 0xffff) | |
680 | return np->csr6; | |
681 | /* reread: the link status bit is sticky */ | |
682 | mii_reg = mdio_read(dev, np->phys[0], MII_BMSR); | |
683 | if (!(mii_reg & 0x4)) { | |
684 | if (netif_carrier_ok(dev)) { | |
685 | if (debug) | |
686 | printk(KERN_INFO "%s: MII #%d reports no link. Disabling watchdog.\n", | |
687 | dev->name, np->phys[0]); | |
688 | netif_carrier_off(dev); | |
689 | } | |
690 | return np->csr6; | |
691 | } | |
692 | if (!netif_carrier_ok(dev)) { | |
693 | if (debug) | |
694 | printk(KERN_INFO "%s: MII #%d link is back. Enabling watchdog.\n", | |
695 | dev->name, np->phys[0]); | |
696 | netif_carrier_on(dev); | |
697 | } | |
f3b197ac | 698 | |
1da177e4 LT |
699 | if ((np->mii & ~0xf) == MII_DAVICOM_DM9101) { |
700 | /* If the link partner doesn't support autonegotiation | |
701 | * the MII detects it's abilities with the "parallel detection". | |
702 | * Some MIIs update the LPA register to the result of the parallel | |
703 | * detection, some don't. | |
704 | * The Davicom PHY [at least 0181b800] doesn't. | |
705 | * Instead bit 9 and 13 of the BMCR are updated to the result | |
706 | * of the negotiation.. | |
707 | */ | |
708 | mii_reg = mdio_read(dev, np->phys[0], MII_BMCR); | |
709 | duplex = mii_reg & BMCR_FULLDPLX; | |
710 | fasteth = mii_reg & BMCR_SPEED100; | |
711 | } else { | |
712 | int negotiated; | |
713 | mii_reg = mdio_read(dev, np->phys[0], MII_LPA); | |
714 | negotiated = mii_reg & np->mii_if.advertising; | |
715 | ||
716 | duplex = (negotiated & LPA_100FULL) || ((negotiated & 0x02C0) == LPA_10FULL); | |
717 | fasteth = negotiated & 0x380; | |
718 | } | |
719 | duplex |= np->mii_if.force_media; | |
720 | /* remove fastether and fullduplex */ | |
721 | result = np->csr6 & ~0x20000200; | |
722 | if (duplex) | |
723 | result |= 0x200; | |
724 | if (fasteth) | |
725 | result |= 0x20000000; | |
726 | if (result != np->csr6 && debug) | |
727 | printk(KERN_INFO "%s: Setting %dMBit-%s-duplex based on MII#%d\n", | |
f3b197ac | 728 | dev->name, fasteth ? 100 : 10, |
1da177e4 LT |
729 | duplex ? "full" : "half", np->phys[0]); |
730 | return result; | |
731 | } | |
732 | ||
733 | #define RXTX_TIMEOUT 2000 | |
734 | static inline void update_csr6(struct net_device *dev, int new) | |
735 | { | |
736 | struct netdev_private *np = netdev_priv(dev); | |
737 | void __iomem *ioaddr = np->base_addr; | |
738 | int limit = RXTX_TIMEOUT; | |
739 | ||
740 | if (!netif_device_present(dev)) | |
741 | new = 0; | |
742 | if (new==np->csr6) | |
743 | return; | |
744 | /* stop both Tx and Rx processes */ | |
745 | iowrite32(np->csr6 & ~0x2002, ioaddr + NetworkConfig); | |
746 | /* wait until they have really stopped */ | |
747 | for (;;) { | |
748 | int csr5 = ioread32(ioaddr + IntrStatus); | |
749 | int t; | |
750 | ||
751 | t = (csr5 >> 17) & 0x07; | |
752 | if (t==0||t==1) { | |
753 | /* rx stopped */ | |
754 | t = (csr5 >> 20) & 0x07; | |
755 | if (t==0||t==1) | |
756 | break; | |
757 | } | |
758 | ||
759 | limit--; | |
760 | if(!limit) { | |
761 | printk(KERN_INFO "%s: couldn't stop rxtx, IntrStatus %xh.\n", | |
762 | dev->name, csr5); | |
763 | break; | |
764 | } | |
765 | udelay(1); | |
766 | } | |
767 | np->csr6 = new; | |
768 | /* and restart them with the new configuration */ | |
769 | iowrite32(np->csr6, ioaddr + NetworkConfig); | |
770 | if (new & 0x200) | |
771 | np->mii_if.full_duplex = 1; | |
772 | } | |
773 | ||
774 | static void netdev_timer(unsigned long data) | |
775 | { | |
776 | struct net_device *dev = (struct net_device *)data; | |
777 | struct netdev_private *np = netdev_priv(dev); | |
778 | void __iomem *ioaddr = np->base_addr; | |
779 | ||
780 | if (debug > 2) | |
781 | printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x " | |
782 | "config %8.8x.\n", | |
783 | dev->name, ioread32(ioaddr + IntrStatus), | |
784 | ioread32(ioaddr + NetworkConfig)); | |
785 | spin_lock_irq(&np->lock); | |
786 | update_csr6(dev, update_link(dev)); | |
787 | spin_unlock_irq(&np->lock); | |
788 | np->timer.expires = jiffies + 10*HZ; | |
789 | add_timer(&np->timer); | |
790 | } | |
791 | ||
792 | static void init_rxtx_rings(struct net_device *dev) | |
793 | { | |
794 | struct netdev_private *np = netdev_priv(dev); | |
795 | int i; | |
796 | ||
797 | np->rx_head_desc = &np->rx_ring[0]; | |
798 | np->tx_ring = (struct w840_tx_desc*)&np->rx_ring[RX_RING_SIZE]; | |
799 | ||
800 | /* Initial all Rx descriptors. */ | |
801 | for (i = 0; i < RX_RING_SIZE; i++) { | |
802 | np->rx_ring[i].length = np->rx_buf_sz; | |
803 | np->rx_ring[i].status = 0; | |
804 | np->rx_skbuff[i] = NULL; | |
805 | } | |
806 | /* Mark the last entry as wrapping the ring. */ | |
807 | np->rx_ring[i-1].length |= DescEndRing; | |
808 | ||
809 | /* Fill in the Rx buffers. Handle allocation failure gracefully. */ | |
810 | for (i = 0; i < RX_RING_SIZE; i++) { | |
811 | struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz); | |
812 | np->rx_skbuff[i] = skb; | |
813 | if (skb == NULL) | |
814 | break; | |
689be439 | 815 | np->rx_addr[i] = pci_map_single(np->pci_dev,skb->data, |
bb02aacc | 816 | np->rx_buf_sz,PCI_DMA_FROMDEVICE); |
1da177e4 LT |
817 | |
818 | np->rx_ring[i].buffer1 = np->rx_addr[i]; | |
42eab567 | 819 | np->rx_ring[i].status = DescOwned; |
1da177e4 LT |
820 | } |
821 | ||
822 | np->cur_rx = 0; | |
823 | np->dirty_rx = (unsigned int)(i - RX_RING_SIZE); | |
824 | ||
825 | /* Initialize the Tx descriptors */ | |
826 | for (i = 0; i < TX_RING_SIZE; i++) { | |
827 | np->tx_skbuff[i] = NULL; | |
828 | np->tx_ring[i].status = 0; | |
829 | } | |
830 | np->tx_full = 0; | |
831 | np->tx_q_bytes = np->dirty_tx = np->cur_tx = 0; | |
832 | ||
833 | iowrite32(np->ring_dma_addr, np->base_addr + RxRingPtr); | |
834 | iowrite32(np->ring_dma_addr+sizeof(struct w840_rx_desc)*RX_RING_SIZE, | |
835 | np->base_addr + TxRingPtr); | |
836 | ||
837 | } | |
838 | ||
839 | static void free_rxtx_rings(struct netdev_private* np) | |
840 | { | |
841 | int i; | |
842 | /* Free all the skbuffs in the Rx queue. */ | |
843 | for (i = 0; i < RX_RING_SIZE; i++) { | |
844 | np->rx_ring[i].status = 0; | |
845 | if (np->rx_skbuff[i]) { | |
846 | pci_unmap_single(np->pci_dev, | |
847 | np->rx_addr[i], | |
848 | np->rx_skbuff[i]->len, | |
849 | PCI_DMA_FROMDEVICE); | |
850 | dev_kfree_skb(np->rx_skbuff[i]); | |
851 | } | |
852 | np->rx_skbuff[i] = NULL; | |
853 | } | |
854 | for (i = 0; i < TX_RING_SIZE; i++) { | |
855 | if (np->tx_skbuff[i]) { | |
856 | pci_unmap_single(np->pci_dev, | |
857 | np->tx_addr[i], | |
858 | np->tx_skbuff[i]->len, | |
859 | PCI_DMA_TODEVICE); | |
860 | dev_kfree_skb(np->tx_skbuff[i]); | |
861 | } | |
862 | np->tx_skbuff[i] = NULL; | |
863 | } | |
864 | } | |
865 | ||
866 | static void init_registers(struct net_device *dev) | |
867 | { | |
868 | struct netdev_private *np = netdev_priv(dev); | |
869 | void __iomem *ioaddr = np->base_addr; | |
870 | int i; | |
871 | ||
872 | for (i = 0; i < 6; i++) | |
873 | iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i); | |
874 | ||
875 | /* Initialize other registers. */ | |
876 | #ifdef __BIG_ENDIAN | |
877 | i = (1<<20); /* Big-endian descriptors */ | |
878 | #else | |
879 | i = 0; | |
880 | #endif | |
881 | i |= (0x04<<2); /* skip length 4 u32 */ | |
882 | i |= 0x02; /* give Rx priority */ | |
883 | ||
884 | /* Configure the PCI bus bursts and FIFO thresholds. | |
885 | 486: Set 8 longword cache alignment, 8 longword burst. | |
886 | 586: Set 16 longword cache alignment, no burst limit. | |
887 | Cache alignment bits 15:14 Burst length 13:8 | |
888 | 0000 <not allowed> 0000 align to cache 0800 8 longwords | |
889 | 4000 8 longwords 0100 1 longword 1000 16 longwords | |
890 | 8000 16 longwords 0200 2 longwords 2000 32 longwords | |
891 | C000 32 longwords 0400 4 longwords */ | |
892 | ||
893 | #if defined (__i386__) && !defined(MODULE) | |
894 | /* When not a module we can work around broken '486 PCI boards. */ | |
895 | if (boot_cpu_data.x86 <= 4) { | |
896 | i |= 0x4800; | |
897 | printk(KERN_INFO "%s: This is a 386/486 PCI system, setting cache " | |
898 | "alignment to 8 longwords.\n", dev->name); | |
899 | } else { | |
900 | i |= 0xE000; | |
901 | } | |
902 | #elif defined(__powerpc__) || defined(__i386__) || defined(__alpha__) || defined(__ia64__) || defined(__x86_64__) | |
903 | i |= 0xE000; | |
49345103 | 904 | #elif defined(CONFIG_SPARC) || defined (CONFIG_PARISC) |
1da177e4 LT |
905 | i |= 0x4800; |
906 | #else | |
907 | #warning Processor architecture undefined | |
908 | i |= 0x4800; | |
909 | #endif | |
910 | iowrite32(i, ioaddr + PCIBusCfg); | |
911 | ||
912 | np->csr6 = 0; | |
f3b197ac | 913 | /* 128 byte Tx threshold; |
1da177e4 LT |
914 | Transmit on; Receive on; */ |
915 | update_csr6(dev, 0x00022002 | update_link(dev) | __set_rx_mode(dev)); | |
916 | ||
917 | /* Clear and Enable interrupts by setting the interrupt mask. */ | |
918 | iowrite32(0x1A0F5, ioaddr + IntrStatus); | |
919 | iowrite32(0x1A0F5, ioaddr + IntrEnable); | |
920 | ||
921 | iowrite32(0, ioaddr + RxStartDemand); | |
922 | } | |
923 | ||
924 | static void tx_timeout(struct net_device *dev) | |
925 | { | |
926 | struct netdev_private *np = netdev_priv(dev); | |
927 | void __iomem *ioaddr = np->base_addr; | |
928 | ||
929 | printk(KERN_WARNING "%s: Transmit timed out, status %8.8x," | |
930 | " resetting...\n", dev->name, ioread32(ioaddr + IntrStatus)); | |
931 | ||
932 | { | |
933 | int i; | |
934 | printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring); | |
935 | for (i = 0; i < RX_RING_SIZE; i++) | |
936 | printk(" %8.8x", (unsigned int)np->rx_ring[i].status); | |
937 | printk("\n"KERN_DEBUG" Tx ring %p: ", np->tx_ring); | |
938 | for (i = 0; i < TX_RING_SIZE; i++) | |
939 | printk(" %8.8x", np->tx_ring[i].status); | |
940 | printk("\n"); | |
941 | } | |
942 | printk(KERN_DEBUG "Tx cur %d Tx dirty %d Tx Full %d, q bytes %d.\n", | |
943 | np->cur_tx, np->dirty_tx, np->tx_full, np->tx_q_bytes); | |
944 | printk(KERN_DEBUG "Tx Descriptor addr %xh.\n",ioread32(ioaddr+0x4C)); | |
945 | ||
946 | disable_irq(dev->irq); | |
947 | spin_lock_irq(&np->lock); | |
948 | /* | |
949 | * Under high load dirty_tx and the internal tx descriptor pointer | |
950 | * come out of sync, thus perform a software reset and reinitialize | |
951 | * everything. | |
952 | */ | |
953 | ||
954 | iowrite32(1, np->base_addr+PCIBusCfg); | |
955 | udelay(1); | |
956 | ||
957 | free_rxtx_rings(np); | |
958 | init_rxtx_rings(dev); | |
959 | init_registers(dev); | |
960 | spin_unlock_irq(&np->lock); | |
961 | enable_irq(dev->irq); | |
962 | ||
963 | netif_wake_queue(dev); | |
964 | dev->trans_start = jiffies; | |
965 | np->stats.tx_errors++; | |
966 | return; | |
967 | } | |
968 | ||
969 | /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ | |
970 | static int alloc_ringdesc(struct net_device *dev) | |
971 | { | |
972 | struct netdev_private *np = netdev_priv(dev); | |
973 | ||
974 | np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32); | |
975 | ||
976 | np->rx_ring = pci_alloc_consistent(np->pci_dev, | |
977 | sizeof(struct w840_rx_desc)*RX_RING_SIZE + | |
978 | sizeof(struct w840_tx_desc)*TX_RING_SIZE, | |
979 | &np->ring_dma_addr); | |
980 | if(!np->rx_ring) | |
981 | return -ENOMEM; | |
982 | init_rxtx_rings(dev); | |
983 | return 0; | |
984 | } | |
985 | ||
986 | static void free_ringdesc(struct netdev_private *np) | |
987 | { | |
988 | pci_free_consistent(np->pci_dev, | |
989 | sizeof(struct w840_rx_desc)*RX_RING_SIZE + | |
990 | sizeof(struct w840_tx_desc)*TX_RING_SIZE, | |
991 | np->rx_ring, np->ring_dma_addr); | |
992 | ||
993 | } | |
994 | ||
995 | static int start_tx(struct sk_buff *skb, struct net_device *dev) | |
996 | { | |
997 | struct netdev_private *np = netdev_priv(dev); | |
998 | unsigned entry; | |
999 | ||
1000 | /* Caution: the write order is important here, set the field | |
1001 | with the "ownership" bits last. */ | |
1002 | ||
1003 | /* Calculate the next Tx descriptor entry. */ | |
1004 | entry = np->cur_tx % TX_RING_SIZE; | |
1005 | ||
1006 | np->tx_addr[entry] = pci_map_single(np->pci_dev, | |
1007 | skb->data,skb->len, PCI_DMA_TODEVICE); | |
1008 | np->tx_skbuff[entry] = skb; | |
1009 | ||
1010 | np->tx_ring[entry].buffer1 = np->tx_addr[entry]; | |
1011 | if (skb->len < TX_BUFLIMIT) { | |
1012 | np->tx_ring[entry].length = DescWholePkt | skb->len; | |
1013 | } else { | |
1014 | int len = skb->len - TX_BUFLIMIT; | |
1015 | ||
1016 | np->tx_ring[entry].buffer2 = np->tx_addr[entry]+TX_BUFLIMIT; | |
1017 | np->tx_ring[entry].length = DescWholePkt | (len << 11) | TX_BUFLIMIT; | |
1018 | } | |
1019 | if(entry == TX_RING_SIZE-1) | |
1020 | np->tx_ring[entry].length |= DescEndRing; | |
1021 | ||
1022 | /* Now acquire the irq spinlock. | |
59c51591 | 1023 | * The difficult race is the ordering between |
42eab567 | 1024 | * increasing np->cur_tx and setting DescOwned: |
1da177e4 LT |
1025 | * - if np->cur_tx is increased first the interrupt |
1026 | * handler could consider the packet as transmitted | |
42eab567 GG |
1027 | * since DescOwned is cleared. |
1028 | * - If DescOwned is set first the NIC could report the | |
1da177e4 LT |
1029 | * packet as sent, but the interrupt handler would ignore it |
1030 | * since the np->cur_tx was not yet increased. | |
1031 | */ | |
1032 | spin_lock_irq(&np->lock); | |
1033 | np->cur_tx++; | |
1034 | ||
1035 | wmb(); /* flush length, buffer1, buffer2 */ | |
42eab567 | 1036 | np->tx_ring[entry].status = DescOwned; |
1da177e4 LT |
1037 | wmb(); /* flush status and kick the hardware */ |
1038 | iowrite32(0, np->base_addr + TxStartDemand); | |
1039 | np->tx_q_bytes += skb->len; | |
1040 | /* Work around horrible bug in the chip by marking the queue as full | |
1041 | when we do not have FIFO room for a maximum sized packet. */ | |
1042 | if (np->cur_tx - np->dirty_tx > TX_QUEUE_LEN || | |
1043 | ((np->drv_flags & HasBrokenTx) && np->tx_q_bytes > TX_BUG_FIFO_LIMIT)) { | |
1044 | netif_stop_queue(dev); | |
1045 | wmb(); | |
1046 | np->tx_full = 1; | |
1047 | } | |
1048 | spin_unlock_irq(&np->lock); | |
1049 | ||
1050 | dev->trans_start = jiffies; | |
1051 | ||
1052 | if (debug > 4) { | |
1053 | printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n", | |
1054 | dev->name, np->cur_tx, entry); | |
1055 | } | |
1056 | return 0; | |
1057 | } | |
1058 | ||
1059 | static void netdev_tx_done(struct net_device *dev) | |
1060 | { | |
1061 | struct netdev_private *np = netdev_priv(dev); | |
1062 | for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) { | |
1063 | int entry = np->dirty_tx % TX_RING_SIZE; | |
1064 | int tx_status = np->tx_ring[entry].status; | |
1065 | ||
1066 | if (tx_status < 0) | |
1067 | break; | |
1068 | if (tx_status & 0x8000) { /* There was an error, log it. */ | |
1069 | #ifndef final_version | |
1070 | if (debug > 1) | |
1071 | printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n", | |
1072 | dev->name, tx_status); | |
1073 | #endif | |
1074 | np->stats.tx_errors++; | |
1075 | if (tx_status & 0x0104) np->stats.tx_aborted_errors++; | |
1076 | if (tx_status & 0x0C80) np->stats.tx_carrier_errors++; | |
1077 | if (tx_status & 0x0200) np->stats.tx_window_errors++; | |
1078 | if (tx_status & 0x0002) np->stats.tx_fifo_errors++; | |
1079 | if ((tx_status & 0x0080) && np->mii_if.full_duplex == 0) | |
1080 | np->stats.tx_heartbeat_errors++; | |
1081 | } else { | |
1082 | #ifndef final_version | |
1083 | if (debug > 3) | |
1084 | printk(KERN_DEBUG "%s: Transmit slot %d ok, Tx status %8.8x.\n", | |
1085 | dev->name, entry, tx_status); | |
1086 | #endif | |
1087 | np->stats.tx_bytes += np->tx_skbuff[entry]->len; | |
1088 | np->stats.collisions += (tx_status >> 3) & 15; | |
1089 | np->stats.tx_packets++; | |
1090 | } | |
1091 | /* Free the original skb. */ | |
1092 | pci_unmap_single(np->pci_dev,np->tx_addr[entry], | |
1093 | np->tx_skbuff[entry]->len, | |
1094 | PCI_DMA_TODEVICE); | |
1095 | np->tx_q_bytes -= np->tx_skbuff[entry]->len; | |
1096 | dev_kfree_skb_irq(np->tx_skbuff[entry]); | |
1097 | np->tx_skbuff[entry] = NULL; | |
1098 | } | |
1099 | if (np->tx_full && | |
1100 | np->cur_tx - np->dirty_tx < TX_QUEUE_LEN_RESTART && | |
1101 | np->tx_q_bytes < TX_BUG_FIFO_LIMIT) { | |
1102 | /* The ring is no longer full, clear tbusy. */ | |
1103 | np->tx_full = 0; | |
1104 | wmb(); | |
1105 | netif_wake_queue(dev); | |
1106 | } | |
1107 | } | |
1108 | ||
1109 | /* The interrupt handler does all of the Rx thread work and cleans up | |
1110 | after the Tx thread. */ | |
7d12e780 | 1111 | static irqreturn_t intr_handler(int irq, void *dev_instance) |
1da177e4 LT |
1112 | { |
1113 | struct net_device *dev = (struct net_device *)dev_instance; | |
1114 | struct netdev_private *np = netdev_priv(dev); | |
1115 | void __iomem *ioaddr = np->base_addr; | |
1116 | int work_limit = max_interrupt_work; | |
1117 | int handled = 0; | |
1118 | ||
1119 | if (!netif_device_present(dev)) | |
1120 | return IRQ_NONE; | |
1121 | do { | |
1122 | u32 intr_status = ioread32(ioaddr + IntrStatus); | |
1123 | ||
1124 | /* Acknowledge all of the current interrupt sources ASAP. */ | |
1125 | iowrite32(intr_status & 0x001ffff, ioaddr + IntrStatus); | |
1126 | ||
1127 | if (debug > 4) | |
1128 | printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n", | |
1129 | dev->name, intr_status); | |
1130 | ||
1131 | if ((intr_status & (NormalIntr|AbnormalIntr)) == 0) | |
1132 | break; | |
1133 | ||
1134 | handled = 1; | |
1135 | ||
42eab567 | 1136 | if (intr_status & (RxIntr | RxNoBuf)) |
1da177e4 LT |
1137 | netdev_rx(dev); |
1138 | if (intr_status & RxNoBuf) | |
1139 | iowrite32(0, ioaddr + RxStartDemand); | |
1140 | ||
42eab567 | 1141 | if (intr_status & (TxNoBuf | TxIntr) && |
1da177e4 LT |
1142 | np->cur_tx != np->dirty_tx) { |
1143 | spin_lock(&np->lock); | |
1144 | netdev_tx_done(dev); | |
1145 | spin_unlock(&np->lock); | |
1146 | } | |
1147 | ||
1148 | /* Abnormal error summary/uncommon events handlers. */ | |
1ddb9861 | 1149 | if (intr_status & (AbnormalIntr | TxFIFOUnderflow | SystemError | |
42eab567 | 1150 | TimerInt | TxDied)) |
1da177e4 LT |
1151 | netdev_error(dev, intr_status); |
1152 | ||
1153 | if (--work_limit < 0) { | |
1154 | printk(KERN_WARNING "%s: Too much work at interrupt, " | |
1155 | "status=0x%4.4x.\n", dev->name, intr_status); | |
1156 | /* Set the timer to re-enable the other interrupts after | |
1157 | 10*82usec ticks. */ | |
1158 | spin_lock(&np->lock); | |
1159 | if (netif_device_present(dev)) { | |
1160 | iowrite32(AbnormalIntr | TimerInt, ioaddr + IntrEnable); | |
1161 | iowrite32(10, ioaddr + GPTimer); | |
1162 | } | |
1163 | spin_unlock(&np->lock); | |
1164 | break; | |
1165 | } | |
1166 | } while (1); | |
1167 | ||
1168 | if (debug > 3) | |
1169 | printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n", | |
1170 | dev->name, ioread32(ioaddr + IntrStatus)); | |
1171 | return IRQ_RETVAL(handled); | |
1172 | } | |
1173 | ||
1174 | /* This routine is logically part of the interrupt handler, but separated | |
1175 | for clarity and better register allocation. */ | |
1176 | static int netdev_rx(struct net_device *dev) | |
1177 | { | |
1178 | struct netdev_private *np = netdev_priv(dev); | |
1179 | int entry = np->cur_rx % RX_RING_SIZE; | |
1180 | int work_limit = np->dirty_rx + RX_RING_SIZE - np->cur_rx; | |
1181 | ||
1182 | if (debug > 4) { | |
1183 | printk(KERN_DEBUG " In netdev_rx(), entry %d status %4.4x.\n", | |
1184 | entry, np->rx_ring[entry].status); | |
1185 | } | |
1186 | ||
1187 | /* If EOP is set on the next entry, it's a new packet. Send it up. */ | |
1188 | while (--work_limit >= 0) { | |
1189 | struct w840_rx_desc *desc = np->rx_head_desc; | |
1190 | s32 status = desc->status; | |
1191 | ||
1192 | if (debug > 4) | |
1193 | printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n", | |
1194 | status); | |
1195 | if (status < 0) | |
1196 | break; | |
1197 | if ((status & 0x38008300) != 0x0300) { | |
1198 | if ((status & 0x38000300) != 0x0300) { | |
1199 | /* Ingore earlier buffers. */ | |
1200 | if ((status & 0xffff) != 0x7fff) { | |
1201 | printk(KERN_WARNING "%s: Oversized Ethernet frame spanned " | |
1202 | "multiple buffers, entry %#x status %4.4x!\n", | |
1203 | dev->name, np->cur_rx, status); | |
1204 | np->stats.rx_length_errors++; | |
1205 | } | |
1206 | } else if (status & 0x8000) { | |
1207 | /* There was a fatal error. */ | |
1208 | if (debug > 2) | |
1209 | printk(KERN_DEBUG "%s: Receive error, Rx status %8.8x.\n", | |
1210 | dev->name, status); | |
1211 | np->stats.rx_errors++; /* end of a packet.*/ | |
1212 | if (status & 0x0890) np->stats.rx_length_errors++; | |
1213 | if (status & 0x004C) np->stats.rx_frame_errors++; | |
1214 | if (status & 0x0002) np->stats.rx_crc_errors++; | |
1215 | } | |
1216 | } else { | |
1217 | struct sk_buff *skb; | |
1218 | /* Omit the four octet CRC from the length. */ | |
1219 | int pkt_len = ((status >> 16) & 0x7ff) - 4; | |
1220 | ||
1221 | #ifndef final_version | |
1222 | if (debug > 4) | |
1223 | printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d" | |
1224 | " status %x.\n", pkt_len, status); | |
1225 | #endif | |
1226 | /* Check if the packet is long enough to accept without copying | |
1227 | to a minimally-sized skbuff. */ | |
1228 | if (pkt_len < rx_copybreak | |
1229 | && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) { | |
1da177e4 LT |
1230 | skb_reserve(skb, 2); /* 16 byte align the IP header */ |
1231 | pci_dma_sync_single_for_cpu(np->pci_dev,np->rx_addr[entry], | |
1232 | np->rx_skbuff[entry]->len, | |
1233 | PCI_DMA_FROMDEVICE); | |
8c7b7faa | 1234 | skb_copy_to_linear_data(skb, np->rx_skbuff[entry]->data, pkt_len); |
1da177e4 LT |
1235 | skb_put(skb, pkt_len); |
1236 | pci_dma_sync_single_for_device(np->pci_dev,np->rx_addr[entry], | |
1237 | np->rx_skbuff[entry]->len, | |
1238 | PCI_DMA_FROMDEVICE); | |
1239 | } else { | |
1240 | pci_unmap_single(np->pci_dev,np->rx_addr[entry], | |
1241 | np->rx_skbuff[entry]->len, | |
1242 | PCI_DMA_FROMDEVICE); | |
1243 | skb_put(skb = np->rx_skbuff[entry], pkt_len); | |
1244 | np->rx_skbuff[entry] = NULL; | |
1245 | } | |
1246 | #ifndef final_version /* Remove after testing. */ | |
1247 | /* You will want this info for the initial debug. */ | |
0795af57 JP |
1248 | if (debug > 5) { |
1249 | DECLARE_MAC_BUF(mac); | |
1250 | DECLARE_MAC_BUF(mac2); | |
1251 | ||
1252 | printk(KERN_DEBUG " Rx data %s %s" | |
1253 | " %2.2x%2.2x %d.%d.%d.%d.\n", | |
1254 | print_mac(mac, &skb->data[0]), print_mac(mac2, &skb->data[6]), | |
1255 | skb->data[12], skb->data[13], | |
1256 | skb->data[14], skb->data[15], skb->data[16], skb->data[17]); | |
1257 | } | |
1da177e4 LT |
1258 | #endif |
1259 | skb->protocol = eth_type_trans(skb, dev); | |
1260 | netif_rx(skb); | |
1261 | dev->last_rx = jiffies; | |
1262 | np->stats.rx_packets++; | |
1263 | np->stats.rx_bytes += pkt_len; | |
1264 | } | |
1265 | entry = (++np->cur_rx) % RX_RING_SIZE; | |
1266 | np->rx_head_desc = &np->rx_ring[entry]; | |
1267 | } | |
1268 | ||
1269 | /* Refill the Rx ring buffers. */ | |
1270 | for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) { | |
1271 | struct sk_buff *skb; | |
1272 | entry = np->dirty_rx % RX_RING_SIZE; | |
1273 | if (np->rx_skbuff[entry] == NULL) { | |
1274 | skb = dev_alloc_skb(np->rx_buf_sz); | |
1275 | np->rx_skbuff[entry] = skb; | |
1276 | if (skb == NULL) | |
1277 | break; /* Better luck next round. */ | |
1da177e4 | 1278 | np->rx_addr[entry] = pci_map_single(np->pci_dev, |
689be439 | 1279 | skb->data, |
bb02aacc | 1280 | np->rx_buf_sz, PCI_DMA_FROMDEVICE); |
1da177e4 LT |
1281 | np->rx_ring[entry].buffer1 = np->rx_addr[entry]; |
1282 | } | |
1283 | wmb(); | |
42eab567 | 1284 | np->rx_ring[entry].status = DescOwned; |
1da177e4 LT |
1285 | } |
1286 | ||
1287 | return 0; | |
1288 | } | |
1289 | ||
1290 | static void netdev_error(struct net_device *dev, int intr_status) | |
1291 | { | |
1292 | struct netdev_private *np = netdev_priv(dev); | |
1293 | void __iomem *ioaddr = np->base_addr; | |
1294 | ||
1295 | if (debug > 2) | |
1296 | printk(KERN_DEBUG "%s: Abnormal event, %8.8x.\n", | |
1297 | dev->name, intr_status); | |
1298 | if (intr_status == 0xffffffff) | |
1299 | return; | |
1300 | spin_lock(&np->lock); | |
1301 | if (intr_status & TxFIFOUnderflow) { | |
1302 | int new; | |
1303 | /* Bump up the Tx threshold */ | |
1304 | #if 0 | |
1305 | /* This causes lots of dropped packets, | |
1306 | * and under high load even tx_timeouts | |
1307 | */ | |
1308 | new = np->csr6 + 0x4000; | |
1309 | #else | |
1310 | new = (np->csr6 >> 14)&0x7f; | |
1311 | if (new < 64) | |
1312 | new *= 2; | |
1313 | else | |
1314 | new = 127; /* load full packet before starting */ | |
1315 | new = (np->csr6 & ~(0x7F << 14)) | (new<<14); | |
1316 | #endif | |
1317 | printk(KERN_DEBUG "%s: Tx underflow, new csr6 %8.8x.\n", | |
1318 | dev->name, new); | |
1319 | update_csr6(dev, new); | |
1320 | } | |
42eab567 | 1321 | if (intr_status & RxDied) { /* Missed a Rx frame. */ |
1da177e4 LT |
1322 | np->stats.rx_errors++; |
1323 | } | |
1324 | if (intr_status & TimerInt) { | |
1325 | /* Re-enable other interrupts. */ | |
1326 | if (netif_device_present(dev)) | |
1327 | iowrite32(0x1A0F5, ioaddr + IntrEnable); | |
1328 | } | |
1329 | np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff; | |
1330 | iowrite32(0, ioaddr + RxStartDemand); | |
1331 | spin_unlock(&np->lock); | |
1332 | } | |
1333 | ||
1334 | static struct net_device_stats *get_stats(struct net_device *dev) | |
1335 | { | |
1336 | struct netdev_private *np = netdev_priv(dev); | |
1337 | void __iomem *ioaddr = np->base_addr; | |
1338 | ||
1339 | /* The chip only need report frame silently dropped. */ | |
1340 | spin_lock_irq(&np->lock); | |
1341 | if (netif_running(dev) && netif_device_present(dev)) | |
1342 | np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff; | |
1343 | spin_unlock_irq(&np->lock); | |
1344 | ||
1345 | return &np->stats; | |
1346 | } | |
1347 | ||
1348 | ||
1349 | static u32 __set_rx_mode(struct net_device *dev) | |
1350 | { | |
1351 | struct netdev_private *np = netdev_priv(dev); | |
1352 | void __iomem *ioaddr = np->base_addr; | |
1353 | u32 mc_filter[2]; /* Multicast hash filter */ | |
1354 | u32 rx_mode; | |
1355 | ||
1356 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ | |
1da177e4 | 1357 | memset(mc_filter, 0xff, sizeof(mc_filter)); |
42eab567 | 1358 | rx_mode = RxAcceptBroadcast | AcceptMulticast | RxAcceptAllPhys |
1da177e4 LT |
1359 | | AcceptMyPhys; |
1360 | } else if ((dev->mc_count > multicast_filter_limit) | |
1361 | || (dev->flags & IFF_ALLMULTI)) { | |
1362 | /* Too many to match, or accept all multicasts. */ | |
1363 | memset(mc_filter, 0xff, sizeof(mc_filter)); | |
42eab567 | 1364 | rx_mode = RxAcceptBroadcast | AcceptMulticast | AcceptMyPhys; |
1da177e4 LT |
1365 | } else { |
1366 | struct dev_mc_list *mclist; | |
1367 | int i; | |
1368 | memset(mc_filter, 0, sizeof(mc_filter)); | |
1369 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | |
1370 | i++, mclist = mclist->next) { | |
1371 | int filterbit = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26) ^ 0x3F; | |
1372 | filterbit &= 0x3f; | |
1373 | mc_filter[filterbit >> 5] |= 1 << (filterbit & 31); | |
1374 | } | |
42eab567 | 1375 | rx_mode = RxAcceptBroadcast | AcceptMulticast | AcceptMyPhys; |
1da177e4 LT |
1376 | } |
1377 | iowrite32(mc_filter[0], ioaddr + MulticastFilter0); | |
1378 | iowrite32(mc_filter[1], ioaddr + MulticastFilter1); | |
1379 | return rx_mode; | |
1380 | } | |
1381 | ||
1382 | static void set_rx_mode(struct net_device *dev) | |
1383 | { | |
1384 | struct netdev_private *np = netdev_priv(dev); | |
1385 | u32 rx_mode = __set_rx_mode(dev); | |
1386 | spin_lock_irq(&np->lock); | |
1387 | update_csr6(dev, (np->csr6 & ~0x00F8) | rx_mode); | |
1388 | spin_unlock_irq(&np->lock); | |
1389 | } | |
1390 | ||
1391 | static void netdev_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info) | |
1392 | { | |
1393 | struct netdev_private *np = netdev_priv(dev); | |
1394 | ||
1395 | strcpy (info->driver, DRV_NAME); | |
1396 | strcpy (info->version, DRV_VERSION); | |
1397 | strcpy (info->bus_info, pci_name(np->pci_dev)); | |
1398 | } | |
1399 | ||
1400 | static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1401 | { | |
1402 | struct netdev_private *np = netdev_priv(dev); | |
1403 | int rc; | |
1404 | ||
1405 | spin_lock_irq(&np->lock); | |
1406 | rc = mii_ethtool_gset(&np->mii_if, cmd); | |
1407 | spin_unlock_irq(&np->lock); | |
1408 | ||
1409 | return rc; | |
1410 | } | |
1411 | ||
1412 | static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1413 | { | |
1414 | struct netdev_private *np = netdev_priv(dev); | |
1415 | int rc; | |
1416 | ||
1417 | spin_lock_irq(&np->lock); | |
1418 | rc = mii_ethtool_sset(&np->mii_if, cmd); | |
1419 | spin_unlock_irq(&np->lock); | |
1420 | ||
1421 | return rc; | |
1422 | } | |
1423 | ||
1424 | static int netdev_nway_reset(struct net_device *dev) | |
1425 | { | |
1426 | struct netdev_private *np = netdev_priv(dev); | |
1427 | return mii_nway_restart(&np->mii_if); | |
1428 | } | |
1429 | ||
1430 | static u32 netdev_get_link(struct net_device *dev) | |
1431 | { | |
1432 | struct netdev_private *np = netdev_priv(dev); | |
1433 | return mii_link_ok(&np->mii_if); | |
1434 | } | |
1435 | ||
1436 | static u32 netdev_get_msglevel(struct net_device *dev) | |
1437 | { | |
1438 | return debug; | |
1439 | } | |
1440 | ||
1441 | static void netdev_set_msglevel(struct net_device *dev, u32 value) | |
1442 | { | |
1443 | debug = value; | |
1444 | } | |
1445 | ||
7282d491 | 1446 | static const struct ethtool_ops netdev_ethtool_ops = { |
1da177e4 LT |
1447 | .get_drvinfo = netdev_get_drvinfo, |
1448 | .get_settings = netdev_get_settings, | |
1449 | .set_settings = netdev_set_settings, | |
1450 | .nway_reset = netdev_nway_reset, | |
1451 | .get_link = netdev_get_link, | |
1452 | .get_msglevel = netdev_get_msglevel, | |
1453 | .set_msglevel = netdev_set_msglevel, | |
1da177e4 LT |
1454 | }; |
1455 | ||
1456 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1457 | { | |
1458 | struct mii_ioctl_data *data = if_mii(rq); | |
1459 | struct netdev_private *np = netdev_priv(dev); | |
1460 | ||
1461 | switch(cmd) { | |
1462 | case SIOCGMIIPHY: /* Get address of MII PHY in use. */ | |
1463 | data->phy_id = ((struct netdev_private *)netdev_priv(dev))->phys[0] & 0x1f; | |
1464 | /* Fall Through */ | |
1465 | ||
1466 | case SIOCGMIIREG: /* Read MII PHY register. */ | |
1467 | spin_lock_irq(&np->lock); | |
1468 | data->val_out = mdio_read(dev, data->phy_id & 0x1f, data->reg_num & 0x1f); | |
1469 | spin_unlock_irq(&np->lock); | |
1470 | return 0; | |
1471 | ||
1472 | case SIOCSMIIREG: /* Write MII PHY register. */ | |
1473 | if (!capable(CAP_NET_ADMIN)) | |
1474 | return -EPERM; | |
1475 | spin_lock_irq(&np->lock); | |
1476 | mdio_write(dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in); | |
1477 | spin_unlock_irq(&np->lock); | |
1478 | return 0; | |
1479 | default: | |
1480 | return -EOPNOTSUPP; | |
1481 | } | |
1482 | } | |
1483 | ||
1484 | static int netdev_close(struct net_device *dev) | |
1485 | { | |
1486 | struct netdev_private *np = netdev_priv(dev); | |
1487 | void __iomem *ioaddr = np->base_addr; | |
1488 | ||
1489 | netif_stop_queue(dev); | |
1490 | ||
1491 | if (debug > 1) { | |
1492 | printk(KERN_DEBUG "%s: Shutting down ethercard, status was %8.8x " | |
1493 | "Config %8.8x.\n", dev->name, ioread32(ioaddr + IntrStatus), | |
1494 | ioread32(ioaddr + NetworkConfig)); | |
1495 | printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n", | |
1496 | dev->name, np->cur_tx, np->dirty_tx, np->cur_rx, np->dirty_rx); | |
1497 | } | |
1498 | ||
1499 | /* Stop the chip's Tx and Rx processes. */ | |
1500 | spin_lock_irq(&np->lock); | |
1501 | netif_device_detach(dev); | |
1502 | update_csr6(dev, 0); | |
1503 | iowrite32(0x0000, ioaddr + IntrEnable); | |
1504 | spin_unlock_irq(&np->lock); | |
1505 | ||
1506 | free_irq(dev->irq, dev); | |
1507 | wmb(); | |
1508 | netif_device_attach(dev); | |
1509 | ||
1510 | if (ioread32(ioaddr + NetworkConfig) != 0xffffffff) | |
1511 | np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff; | |
1512 | ||
1513 | #ifdef __i386__ | |
1514 | if (debug > 2) { | |
1515 | int i; | |
1516 | ||
1517 | printk(KERN_DEBUG" Tx ring at %8.8x:\n", | |
1518 | (int)np->tx_ring); | |
1519 | for (i = 0; i < TX_RING_SIZE; i++) | |
1520 | printk(KERN_DEBUG " #%d desc. %4.4x %4.4x %8.8x.\n", | |
1521 | i, np->tx_ring[i].length, | |
1522 | np->tx_ring[i].status, np->tx_ring[i].buffer1); | |
1523 | printk("\n"KERN_DEBUG " Rx ring %8.8x:\n", | |
1524 | (int)np->rx_ring); | |
1525 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1526 | printk(KERN_DEBUG " #%d desc. %4.4x %4.4x %8.8x\n", | |
1527 | i, np->rx_ring[i].length, | |
1528 | np->rx_ring[i].status, np->rx_ring[i].buffer1); | |
1529 | } | |
1530 | } | |
1531 | #endif /* __i386__ debugging only */ | |
1532 | ||
1533 | del_timer_sync(&np->timer); | |
1534 | ||
1535 | free_rxtx_rings(np); | |
1536 | free_ringdesc(np); | |
1537 | ||
1538 | return 0; | |
1539 | } | |
1540 | ||
1541 | static void __devexit w840_remove1 (struct pci_dev *pdev) | |
1542 | { | |
1543 | struct net_device *dev = pci_get_drvdata(pdev); | |
f3b197ac | 1544 | |
1da177e4 LT |
1545 | if (dev) { |
1546 | struct netdev_private *np = netdev_priv(dev); | |
1547 | unregister_netdev(dev); | |
1548 | pci_release_regions(pdev); | |
1549 | pci_iounmap(pdev, np->base_addr); | |
1550 | free_netdev(dev); | |
1551 | } | |
1552 | ||
1553 | pci_set_drvdata(pdev, NULL); | |
1554 | } | |
1555 | ||
1556 | #ifdef CONFIG_PM | |
1557 | ||
1558 | /* | |
1559 | * suspend/resume synchronization: | |
1560 | * - open, close, do_ioctl: | |
1561 | * rtnl_lock, & netif_device_detach after the rtnl_unlock. | |
1562 | * - get_stats: | |
1563 | * spin_lock_irq(np->lock), doesn't touch hw if not present | |
1564 | * - hard_start_xmit: | |
932ff279 | 1565 | * synchronize_irq + netif_tx_disable; |
1da177e4 | 1566 | * - tx_timeout: |
932ff279 | 1567 | * netif_device_detach + netif_tx_disable; |
1da177e4 | 1568 | * - set_multicast_list |
932ff279 | 1569 | * netif_device_detach + netif_tx_disable; |
1da177e4 LT |
1570 | * - interrupt handler |
1571 | * doesn't touch hw if not present, synchronize_irq waits for | |
1572 | * running instances of the interrupt handler. | |
1573 | * | |
1574 | * Disabling hw requires clearing csr6 & IntrEnable. | |
1575 | * update_csr6 & all function that write IntrEnable check netif_device_present | |
1576 | * before settings any bits. | |
1577 | * | |
1578 | * Detach must occur under spin_unlock_irq(), interrupts from a detached | |
1579 | * device would cause an irq storm. | |
1580 | */ | |
05adc3b7 | 1581 | static int w840_suspend (struct pci_dev *pdev, pm_message_t state) |
1da177e4 LT |
1582 | { |
1583 | struct net_device *dev = pci_get_drvdata (pdev); | |
1584 | struct netdev_private *np = netdev_priv(dev); | |
1585 | void __iomem *ioaddr = np->base_addr; | |
1586 | ||
1587 | rtnl_lock(); | |
1588 | if (netif_running (dev)) { | |
1589 | del_timer_sync(&np->timer); | |
1590 | ||
1591 | spin_lock_irq(&np->lock); | |
1592 | netif_device_detach(dev); | |
1593 | update_csr6(dev, 0); | |
1594 | iowrite32(0, ioaddr + IntrEnable); | |
1da177e4 LT |
1595 | spin_unlock_irq(&np->lock); |
1596 | ||
1da177e4 | 1597 | synchronize_irq(dev->irq); |
932ff279 | 1598 | netif_tx_disable(dev); |
6aa20a22 | 1599 | |
1da177e4 LT |
1600 | np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff; |
1601 | ||
1602 | /* no more hardware accesses behind this line. */ | |
1603 | ||
cca4aa83 | 1604 | BUG_ON(np->csr6); |
1da177e4 LT |
1605 | if (ioread32(ioaddr + IntrEnable)) BUG(); |
1606 | ||
1607 | /* pci_power_off(pdev, -1); */ | |
1608 | ||
1609 | free_rxtx_rings(np); | |
1610 | } else { | |
1611 | netif_device_detach(dev); | |
1612 | } | |
1613 | rtnl_unlock(); | |
1614 | return 0; | |
1615 | } | |
1616 | ||
1617 | static int w840_resume (struct pci_dev *pdev) | |
1618 | { | |
1619 | struct net_device *dev = pci_get_drvdata (pdev); | |
1620 | struct netdev_private *np = netdev_priv(dev); | |
9f486ae1 | 1621 | int retval = 0; |
1da177e4 LT |
1622 | |
1623 | rtnl_lock(); | |
1624 | if (netif_device_present(dev)) | |
1625 | goto out; /* device not suspended */ | |
1626 | if (netif_running(dev)) { | |
9f486ae1 VH |
1627 | if ((retval = pci_enable_device(pdev))) { |
1628 | printk (KERN_ERR | |
1629 | "%s: pci_enable_device failed in resume\n", | |
1630 | dev->name); | |
1631 | goto out; | |
1632 | } | |
1da177e4 LT |
1633 | spin_lock_irq(&np->lock); |
1634 | iowrite32(1, np->base_addr+PCIBusCfg); | |
1635 | ioread32(np->base_addr+PCIBusCfg); | |
1636 | udelay(1); | |
1637 | netif_device_attach(dev); | |
1638 | init_rxtx_rings(dev); | |
1639 | init_registers(dev); | |
1640 | spin_unlock_irq(&np->lock); | |
1641 | ||
1642 | netif_wake_queue(dev); | |
1643 | ||
1644 | mod_timer(&np->timer, jiffies + 1*HZ); | |
1645 | } else { | |
1646 | netif_device_attach(dev); | |
1647 | } | |
1648 | out: | |
1649 | rtnl_unlock(); | |
9f486ae1 | 1650 | return retval; |
1da177e4 LT |
1651 | } |
1652 | #endif | |
1653 | ||
1654 | static struct pci_driver w840_driver = { | |
1655 | .name = DRV_NAME, | |
1656 | .id_table = w840_pci_tbl, | |
1657 | .probe = w840_probe1, | |
1658 | .remove = __devexit_p(w840_remove1), | |
1659 | #ifdef CONFIG_PM | |
1660 | .suspend = w840_suspend, | |
1661 | .resume = w840_resume, | |
1662 | #endif | |
1663 | }; | |
1664 | ||
1665 | static int __init w840_init(void) | |
1666 | { | |
1667 | printk(version); | |
29917620 | 1668 | return pci_register_driver(&w840_driver); |
1da177e4 LT |
1669 | } |
1670 | ||
1671 | static void __exit w840_exit(void) | |
1672 | { | |
1673 | pci_unregister_driver(&w840_driver); | |
1674 | } | |
1675 | ||
1676 | module_init(w840_init); | |
1677 | module_exit(w840_exit); |