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ucc_geth: Fix TX watchdog timeout handling
[deliverable/linux.git] / drivers / net / ucc_geth.c
CommitLineData
ce973b14 1/*
4e19b5c1 2 * Copyright (C) 2006-2007 Freescale Semicondutor, Inc. All rights reserved.
ce973b14
LY		 3 *
4 * Author: Shlomi Gridish <gridish@freescale.com>
18a8e864 5 * Li Yang <leoli@freescale.com>
ce973b14
LY		 6 *
7 * Description:
8 * QE UCC Gigabit Ethernet Driver
9 *
ce973b14
LY		 10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/slab.h>
19#include <linux/stddef.h>
20#include <linux/interrupt.h>
21#include <linux/netdevice.h>
22#include <linux/etherdevice.h>
23#include <linux/skbuff.h>
24#include <linux/spinlock.h>
25#include <linux/mm.h>
ce973b14
LY		 26#include <linux/dma-mapping.h>
27#include <linux/fsl_devices.h>
ce973b14 28#include <linux/mii.h>
728de4c9 29#include <linux/phy.h>
df19b6b0 30#include <linux/workqueue.h>
55b6c8e9 31#include <linux/of_platform.h>
ce973b14
LY		 32
33#include <asm/uaccess.h>
34#include <asm/irq.h>
35#include <asm/io.h>
36#include <asm/immap_qe.h>
37#include <asm/qe.h>
38#include <asm/ucc.h>
39#include <asm/ucc_fast.h>
40
41#include "ucc_geth.h"
728de4c9 42#include "ucc_geth_mii.h"
ce973b14
LY		 43
44#undef DEBUG
45
ce973b14
LY		 46#define ugeth_printk(level, format, arg...) \
47 printk(level format "\n", ## arg)
48
49#define ugeth_dbg(format, arg...) \
50 ugeth_printk(KERN_DEBUG , format , ## arg)
51#define ugeth_err(format, arg...) \
52 ugeth_printk(KERN_ERR , format , ## arg)
53#define ugeth_info(format, arg...) \
54 ugeth_printk(KERN_INFO , format , ## arg)
55#define ugeth_warn(format, arg...) \
56 ugeth_printk(KERN_WARNING , format , ## arg)
57
58#ifdef UGETH_VERBOSE_DEBUG
59#define ugeth_vdbg ugeth_dbg
60#else
61#define ugeth_vdbg(fmt, args...) do { } while (0)
62#endif /* UGETH_VERBOSE_DEBUG */
890de95e 63#define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
ce973b14 64
88a15f2e 65
ce973b14
LY		 66static DEFINE_SPINLOCK(ugeth_lock);
67
890de95e
LY		 68static struct {
69 u32 msg_enable;
70} debug = { -1 };
71
72module_param_named(debug, debug.msg_enable, int, 0);
73MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
74
18a8e864 75static struct ucc_geth_info ugeth_primary_info = {
ce973b14
LY		 76 .uf_info = {
77 .bd_mem_part = MEM_PART_SYSTEM,
78 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
79 .max_rx_buf_length = 1536,
728de4c9 80 /* adjusted at startup if max-speed 1000 */
ce973b14
LY		 81 .urfs = UCC_GETH_URFS_INIT,
82 .urfet = UCC_GETH_URFET_INIT,
83 .urfset = UCC_GETH_URFSET_INIT,
84 .utfs = UCC_GETH_UTFS_INIT,
85 .utfet = UCC_GETH_UTFET_INIT,
86 .utftt = UCC_GETH_UTFTT_INIT,
ce973b14
LY		 87 .ufpt = 256,
88 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
89 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
90 .tenc = UCC_FAST_TX_ENCODING_NRZ,
91 .renc = UCC_FAST_RX_ENCODING_NRZ,
92 .tcrc = UCC_FAST_16_BIT_CRC,
93 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
94 },
95 .numQueuesTx = 1,
96 .numQueuesRx = 1,
97 .extendedFilteringChainPointer = ((uint32_t) NULL),
98 .typeorlen = 3072 /*1536 */ ,
99 .nonBackToBackIfgPart1 = 0x40,
100 .nonBackToBackIfgPart2 = 0x60,
101 .miminumInterFrameGapEnforcement = 0x50,
102 .backToBackInterFrameGap = 0x60,
103 .mblinterval = 128,
104 .nortsrbytetime = 5,
105 .fracsiz = 1,
106 .strictpriorityq = 0xff,
107 .altBebTruncation = 0xa,
108 .excessDefer = 1,
109 .maxRetransmission = 0xf,
110 .collisionWindow = 0x37,
111 .receiveFlowControl = 1,
ac421852 112 .transmitFlowControl = 1,
ce973b14
LY		 113 .maxGroupAddrInHash = 4,
114 .maxIndAddrInHash = 4,
115 .prel = 7,
116 .maxFrameLength = 1518,
117 .minFrameLength = 64,
118 .maxD1Length = 1520,
119 .maxD2Length = 1520,
120 .vlantype = 0x8100,
121 .ecamptr = ((uint32_t) NULL),
122 .eventRegMask = UCCE_OTHER,
123 .pausePeriod = 0xf000,
124 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
125 .bdRingLenTx = {
126 TX_BD_RING_LEN,
127 TX_BD_RING_LEN,
128 TX_BD_RING_LEN,
129 TX_BD_RING_LEN,
130 TX_BD_RING_LEN,
131 TX_BD_RING_LEN,
132 TX_BD_RING_LEN,
133 TX_BD_RING_LEN},
134
135 .bdRingLenRx = {
136 RX_BD_RING_LEN,
137 RX_BD_RING_LEN,
138 RX_BD_RING_LEN,
139 RX_BD_RING_LEN,
140 RX_BD_RING_LEN,
141 RX_BD_RING_LEN,
142 RX_BD_RING_LEN,
143 RX_BD_RING_LEN},
144
145 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
146 .largestexternallookupkeysize =
147 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
ac421852
LY		 148 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
149 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
150 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
ce973b14
LY		 151 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
152 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
153 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
154 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
155 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
ffea31ed
JT		 156 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
157 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
ce973b14
LY		 158 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
159 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
160};
161
18a8e864 162static struct ucc_geth_info ugeth_info[8];
ce973b14
LY		 163
164#ifdef DEBUG
165static void mem_disp(u8 *addr, int size)
166{
167 u8 *i;
168 int size16Aling = (size >> 4) << 4;
169 int size4Aling = (size >> 2) << 2;
170 int notAlign = 0;
171 if (size % 16)
172 notAlign = 1;
173
174 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
175 printk("0x%08x: %08x %08x %08x %08x\r\n",
176 (u32) i,
177 *((u32 *) (i)),
178 *((u32 *) (i + 4)),
179 *((u32 *) (i + 8)), *((u32 *) (i + 12)));
180 if (notAlign == 1)
181 printk("0x%08x: ", (u32) i);
182 for (; (u32) i < (u32) addr + size4Aling; i += 4)
183 printk("%08x ", *((u32 *) (i)));
184 for (; (u32) i < (u32) addr + size; i++)
185 printk("%02x", *((u8 *) (i)));
186 if (notAlign == 1)
187 printk("\r\n");
188}
189#endif /* DEBUG */
190
191#ifdef CONFIG_UGETH_FILTERING
192static void enqueue(struct list_head *node, struct list_head *lh)
193{
194 unsigned long flags;
195
1083cfe1 196 spin_lock_irqsave(&ugeth_lock, flags);
ce973b14 197 list_add_tail(node, lh);
1083cfe1 198 spin_unlock_irqrestore(&ugeth_lock, flags);
ce973b14
LY		 199}
200#endif /* CONFIG_UGETH_FILTERING */
201
202static struct list_head *dequeue(struct list_head *lh)
203{
204 unsigned long flags;
205
1083cfe1 206 spin_lock_irqsave(&ugeth_lock, flags);
ce973b14
LY		 207 if (!list_empty(lh)) {
208 struct list_head *node = lh->next;
209 list_del(node);
1083cfe1 210 spin_unlock_irqrestore(&ugeth_lock, flags);
ce973b14
LY		 211 return node;
212 } else {
1083cfe1 213 spin_unlock_irqrestore(&ugeth_lock, flags);
ce973b14
LY		 214 return NULL;
215 }
216}
217
6fee40e9
AF		 218static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
219 u8 __iomem *bd)
ce973b14
LY		 220{
221 struct sk_buff *skb = NULL;
222
223 skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
224 UCC_GETH_RX_DATA_BUF_ALIGNMENT);
225
226 if (skb == NULL)
227 return NULL;
228
229 /* We need the data buffer to be aligned properly. We will reserve
230 * as many bytes as needed to align the data properly
231 */
232 skb_reserve(skb,
233 UCC_GETH_RX_DATA_BUF_ALIGNMENT -
234 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
235 1)));
236
237 skb->dev = ugeth->dev;
238
6fee40e9 239 out_be32(&((struct qe_bd __iomem *)bd)->buf,
7f80202b 240 dma_map_single(&ugeth->dev->dev,
ce973b14
LY		 241 skb->data,
242 ugeth->ug_info->uf_info.max_rx_buf_length +
243 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
244 DMA_FROM_DEVICE));
245
6fee40e9
AF		 246 out_be32((u32 __iomem *)bd,
247 (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
ce973b14
LY		 248
249 return skb;
250}
251
18a8e864 252static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
ce973b14 253{
6fee40e9 254 u8 __iomem *bd;
ce973b14
LY		 255 u32 bd_status;
256 struct sk_buff *skb;
257 int i;
258
259 bd = ugeth->p_rx_bd_ring[rxQ];
260 i = 0;
261
262 do {
6fee40e9 263 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 264 skb = get_new_skb(ugeth, bd);
265
266 if (!skb) /* If can not allocate data buffer,
267 abort. Cleanup will be elsewhere */
268 return -ENOMEM;
269
270 ugeth->rx_skbuff[rxQ][i] = skb;
271
272 /* advance the BD pointer */
18a8e864 273 bd += sizeof(struct qe_bd);
ce973b14
LY		 274 i++;
275 } while (!(bd_status & R_W));
276
277 return 0;
278}
279
18a8e864 280static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 281 u32 *p_start,
ce973b14
LY		 282 u8 num_entries,
283 u32 thread_size,
284 u32 thread_alignment,
18a8e864 285 enum qe_risc_allocation risc,
ce973b14
LY		 286 int skip_page_for_first_entry)
287{
288 u32 init_enet_offset;
289 u8 i;
290 int snum;
291
292 for (i = 0; i < num_entries; i++) {
293 if ((snum = qe_get_snum()) < 0) {
890de95e
LY		 294 if (netif_msg_ifup(ugeth))
295 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
ce973b14
LY		 296 return snum;
297 }
298 if ((i == 0) && skip_page_for_first_entry)
299 /* First entry of Rx does not have page */
300 init_enet_offset = 0;
301 else {
302 init_enet_offset =
303 qe_muram_alloc(thread_size, thread_alignment);
4c35630c 304 if (IS_ERR_VALUE(init_enet_offset)) {
890de95e
LY		 305 if (netif_msg_ifup(ugeth))
306 ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory.");
ce973b14
LY		 307 qe_put_snum((u8) snum);
308 return -ENOMEM;
309 }
310 }
311 *(p_start++) =
312 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
313 | risc;
314 }
315
316 return 0;
317}
318
18a8e864 319static int return_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 320 u32 *p_start,
ce973b14 321 u8 num_entries,
18a8e864 322 enum qe_risc_allocation risc,
ce973b14
LY		 323 int skip_page_for_first_entry)
324{
325 u32 init_enet_offset;
326 u8 i;
327 int snum;
328
329 for (i = 0; i < num_entries; i++) {
6fee40e9
AF		 330 u32 val = *p_start;
331
ce973b14
LY		 332 /* Check that this entry was actually valid --
333 needed in case failed in allocations */
6fee40e9 334 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
ce973b14 335 snum =
6fee40e9 336 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
ce973b14
LY		 337 ENET_INIT_PARAM_SNUM_SHIFT;
338 qe_put_snum((u8) snum);
339 if (!((i == 0) && skip_page_for_first_entry)) {
340 /* First entry of Rx does not have page */
341 init_enet_offset =
6fee40e9 342 (val & ENET_INIT_PARAM_PTR_MASK);
ce973b14
LY		 343 qe_muram_free(init_enet_offset);
344 }
6fee40e9 345 *p_start++ = 0;
ce973b14
LY		 346 }
347 }
348
349 return 0;
350}
351
352#ifdef DEBUG
18a8e864 353static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 354 u32 __iomem *p_start,
ce973b14
LY		 355 u8 num_entries,
356 u32 thread_size,
18a8e864 357 enum qe_risc_allocation risc,
ce973b14
LY		 358 int skip_page_for_first_entry)
359{
360 u32 init_enet_offset;
361 u8 i;
362 int snum;
363
364 for (i = 0; i < num_entries; i++) {
6fee40e9
AF		 365 u32 val = in_be32(p_start);
366
ce973b14
LY		 367 /* Check that this entry was actually valid --
368 needed in case failed in allocations */
6fee40e9 369 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
ce973b14 370 snum =
6fee40e9 371 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
ce973b14
LY		 372 ENET_INIT_PARAM_SNUM_SHIFT;
373 qe_put_snum((u8) snum);
374 if (!((i == 0) && skip_page_for_first_entry)) {
375 /* First entry of Rx does not have page */
376 init_enet_offset =
377 (in_be32(p_start) &
378 ENET_INIT_PARAM_PTR_MASK);
379 ugeth_info("Init enet entry %d:", i);
380 ugeth_info("Base address: 0x%08x",
381 (u32)
382 qe_muram_addr(init_enet_offset));
383 mem_disp(qe_muram_addr(init_enet_offset),
384 thread_size);
385 }
386 p_start++;
387 }
388 }
389
390 return 0;
391}
392#endif
393
394#ifdef CONFIG_UGETH_FILTERING
18a8e864 395static struct enet_addr_container *get_enet_addr_container(void)
ce973b14 396{
18a8e864 397 struct enet_addr_container *enet_addr_cont;
ce973b14
LY		 398
399 /* allocate memory */
18a8e864 400 enet_addr_cont = kmalloc(sizeof(struct enet_addr_container), GFP_KERNEL);
ce973b14 401 if (!enet_addr_cont) {
18a8e864 402 ugeth_err("%s: No memory for enet_addr_container object.",
b39d66a8 403 __func__);
ce973b14
LY		 404 return NULL;
405 }
406
407 return enet_addr_cont;
408}
409#endif /* CONFIG_UGETH_FILTERING */
410
18a8e864 411static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
ce973b14
LY		 412{
413 kfree(enet_addr_cont);
414}
415
df19b6b0 416static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
18a8e864
LY		 417{
418 out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
419 out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
420 out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
421}
422
ce973b14 423#ifdef CONFIG_UGETH_FILTERING
18a8e864
LY		 424static int hw_add_addr_in_paddr(struct ucc_geth_private *ugeth,
425 u8 *p_enet_addr, u8 paddr_num)
ce973b14 426{
18a8e864 427 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
ce973b14
LY		 428
429 if (!(paddr_num < NUM_OF_PADDRS)) {
b39d66a8 430 ugeth_warn("%s: Illegal paddr_num.", __func__);
ce973b14
LY		 431 return -EINVAL;
432 }
433
434 p_82xx_addr_filt =
18a8e864 435 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
ce973b14
LY		 436 addressfiltering;
437
438 /* Ethernet frames are defined in Little Endian mode, */
439 /* therefore to insert the address we reverse the bytes. */
18a8e864 440 set_mac_addr(&p_82xx_addr_filt->paddr[paddr_num].h, p_enet_addr);
ce973b14
LY		 441 return 0;
442}
443#endif /* CONFIG_UGETH_FILTERING */
444
18a8e864 445static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
ce973b14 446{
6fee40e9 447 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
ce973b14
LY		 448
449 if (!(paddr_num < NUM_OF_PADDRS)) {
b39d66a8 450 ugeth_warn("%s: Illagel paddr_num.", __func__);
ce973b14
LY		 451 return -EINVAL;
452 }
453
454 p_82xx_addr_filt =
6fee40e9 455 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
ce973b14
LY		 456 addressfiltering;
457
458 /* Writing address ff.ff.ff.ff.ff.ff disables address
459 recognition for this register */
460 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
461 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
462 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
463
464 return 0;
465}
466
18a8e864
LY		 467static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
468 u8 *p_enet_addr)
ce973b14 469{
6fee40e9 470 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
ce973b14
LY		 471 u32 cecr_subblock;
472
473 p_82xx_addr_filt =
6fee40e9 474 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
ce973b14
LY		 475 addressfiltering;
476
477 cecr_subblock =
478 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
479
480 /* Ethernet frames are defined in Little Endian mode,
481 therefor to insert */
482 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
18a8e864
LY		 483
484 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
ce973b14
LY		 485
486 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
18a8e864 487 QE_CR_PROTOCOL_ETHERNET, 0);
ce973b14
LY		 488}
489
490#ifdef CONFIG_UGETH_MAGIC_PACKET
18a8e864 491static void magic_packet_detection_enable(struct ucc_geth_private *ugeth)
ce973b14 492{
18a8e864 493 struct ucc_fast_private *uccf;
6fee40e9 494 struct ucc_geth __iomem *ug_regs;
ce973b14
LY		 495 u32 maccfg2, uccm;
496
497 uccf = ugeth->uccf;
498 ug_regs = ugeth->ug_regs;
499
500 /* Enable interrupts for magic packet detection */
501 uccm = in_be32(uccf->p_uccm);
502 uccm |= UCCE_MPD;
503 out_be32(uccf->p_uccm, uccm);
504
505 /* Enable magic packet detection */
506 maccfg2 = in_be32(&ug_regs->maccfg2);
507 maccfg2 |= MACCFG2_MPE;
508 out_be32(&ug_regs->maccfg2, maccfg2);
509}
510
18a8e864 511static void magic_packet_detection_disable(struct ucc_geth_private *ugeth)
ce973b14 512{
18a8e864 513 struct ucc_fast_private *uccf;
6fee40e9 514 struct ucc_geth __iomem *ug_regs;
ce973b14
LY		 515 u32 maccfg2, uccm;
516
517 uccf = ugeth->uccf;
518 ug_regs = ugeth->ug_regs;
519
520 /* Disable interrupts for magic packet detection */
521 uccm = in_be32(uccf->p_uccm);
522 uccm &= ~UCCE_MPD;
523 out_be32(uccf->p_uccm, uccm);
524
525 /* Disable magic packet detection */
526 maccfg2 = in_be32(&ug_regs->maccfg2);
527 maccfg2 &= ~MACCFG2_MPE;
528 out_be32(&ug_regs->maccfg2, maccfg2);
529}
530#endif /* MAGIC_PACKET */
531
18a8e864 532static inline int compare_addr(u8 **addr1, u8 **addr2)
ce973b14
LY		 533{
534 return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
535}
536
537#ifdef DEBUG
18a8e864
LY		 538static void get_statistics(struct ucc_geth_private *ugeth,
539 struct ucc_geth_tx_firmware_statistics *
ce973b14 540 tx_firmware_statistics,
18a8e864 541 struct ucc_geth_rx_firmware_statistics *
ce973b14 542 rx_firmware_statistics,
18a8e864 543 struct ucc_geth_hardware_statistics *hardware_statistics)
ce973b14 544{
6fee40e9
AF		 545 struct ucc_fast __iomem *uf_regs;
546 struct ucc_geth __iomem *ug_regs;
18a8e864
LY		 547 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
548 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
ce973b14
LY		 549
550 ug_regs = ugeth->ug_regs;
6fee40e9 551 uf_regs = (struct ucc_fast __iomem *) ug_regs;
ce973b14
LY		 552 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
553 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
554
555 /* Tx firmware only if user handed pointer and driver actually
556 gathers Tx firmware statistics */
557 if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
558 tx_firmware_statistics->sicoltx =
559 in_be32(&p_tx_fw_statistics_pram->sicoltx);
560 tx_firmware_statistics->mulcoltx =
561 in_be32(&p_tx_fw_statistics_pram->mulcoltx);
562 tx_firmware_statistics->latecoltxfr =
563 in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
564 tx_firmware_statistics->frabortduecol =
565 in_be32(&p_tx_fw_statistics_pram->frabortduecol);
566 tx_firmware_statistics->frlostinmactxer =
567 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
568 tx_firmware_statistics->carriersenseertx =
569 in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
570 tx_firmware_statistics->frtxok =
571 in_be32(&p_tx_fw_statistics_pram->frtxok);
572 tx_firmware_statistics->txfrexcessivedefer =
573 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
574 tx_firmware_statistics->txpkts256 =
575 in_be32(&p_tx_fw_statistics_pram->txpkts256);
576 tx_firmware_statistics->txpkts512 =
577 in_be32(&p_tx_fw_statistics_pram->txpkts512);
578 tx_firmware_statistics->txpkts1024 =
579 in_be32(&p_tx_fw_statistics_pram->txpkts1024);
580 tx_firmware_statistics->txpktsjumbo =
581 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
582 }
583
584 /* Rx firmware only if user handed pointer and driver actually
585 * gathers Rx firmware statistics */
586 if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
587 int i;
588 rx_firmware_statistics->frrxfcser =
589 in_be32(&p_rx_fw_statistics_pram->frrxfcser);
590 rx_firmware_statistics->fraligner =
591 in_be32(&p_rx_fw_statistics_pram->fraligner);
592 rx_firmware_statistics->inrangelenrxer =
593 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
594 rx_firmware_statistics->outrangelenrxer =
595 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
596 rx_firmware_statistics->frtoolong =
597 in_be32(&p_rx_fw_statistics_pram->frtoolong);
598 rx_firmware_statistics->runt =
599 in_be32(&p_rx_fw_statistics_pram->runt);
600 rx_firmware_statistics->verylongevent =
601 in_be32(&p_rx_fw_statistics_pram->verylongevent);
602 rx_firmware_statistics->symbolerror =
603 in_be32(&p_rx_fw_statistics_pram->symbolerror);
604 rx_firmware_statistics->dropbsy =
605 in_be32(&p_rx_fw_statistics_pram->dropbsy);
606 for (i = 0; i < 0x8; i++)
607 rx_firmware_statistics->res0[i] =
608 p_rx_fw_statistics_pram->res0[i];
609 rx_firmware_statistics->mismatchdrop =
610 in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
611 rx_firmware_statistics->underpkts =
612 in_be32(&p_rx_fw_statistics_pram->underpkts);
613 rx_firmware_statistics->pkts256 =
614 in_be32(&p_rx_fw_statistics_pram->pkts256);
615 rx_firmware_statistics->pkts512 =
616 in_be32(&p_rx_fw_statistics_pram->pkts512);
617 rx_firmware_statistics->pkts1024 =
618 in_be32(&p_rx_fw_statistics_pram->pkts1024);
619 rx_firmware_statistics->pktsjumbo =
620 in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
621 rx_firmware_statistics->frlossinmacer =
622 in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
623 rx_firmware_statistics->pausefr =
624 in_be32(&p_rx_fw_statistics_pram->pausefr);
625 for (i = 0; i < 0x4; i++)
626 rx_firmware_statistics->res1[i] =
627 p_rx_fw_statistics_pram->res1[i];
628 rx_firmware_statistics->removevlan =
629 in_be32(&p_rx_fw_statistics_pram->removevlan);
630 rx_firmware_statistics->replacevlan =
631 in_be32(&p_rx_fw_statistics_pram->replacevlan);
632 rx_firmware_statistics->insertvlan =
633 in_be32(&p_rx_fw_statistics_pram->insertvlan);
634 }
635
636 /* Hardware only if user handed pointer and driver actually
637 gathers hardware statistics */
638 if (hardware_statistics && (in_be32(&uf_regs->upsmr) & UPSMR_HSE)) {
639 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
640 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
641 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
642 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
643 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
644 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
645 hardware_statistics->txok = in_be32(&ug_regs->txok);
646 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
647 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
648 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
649 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
650 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
651 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
652 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
653 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
654 }
655}
656
18a8e864 657static void dump_bds(struct ucc_geth_private *ugeth)
ce973b14
LY		 658{
659 int i;
660 int length;
661
662 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
663 if (ugeth->p_tx_bd_ring[i]) {
664 length =
665 (ugeth->ug_info->bdRingLenTx[i] *
18a8e864 666 sizeof(struct qe_bd));
ce973b14
LY		 667 ugeth_info("TX BDs[%d]", i);
668 mem_disp(ugeth->p_tx_bd_ring[i], length);
669 }
670 }
671 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
672 if (ugeth->p_rx_bd_ring[i]) {
673 length =
674 (ugeth->ug_info->bdRingLenRx[i] *
18a8e864 675 sizeof(struct qe_bd));
ce973b14
LY		 676 ugeth_info("RX BDs[%d]", i);
677 mem_disp(ugeth->p_rx_bd_ring[i], length);
678 }
679 }
680}
681
18a8e864 682static void dump_regs(struct ucc_geth_private *ugeth)
ce973b14
LY		 683{
684 int i;
685
686 ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num);
687 ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
688
689 ugeth_info("maccfg1 : addr - 0x%08x, val - 0x%08x",
690 (u32) & ugeth->ug_regs->maccfg1,
691 in_be32(&ugeth->ug_regs->maccfg1));
692 ugeth_info("maccfg2 : addr - 0x%08x, val - 0x%08x",
693 (u32) & ugeth->ug_regs->maccfg2,
694 in_be32(&ugeth->ug_regs->maccfg2));
695 ugeth_info("ipgifg : addr - 0x%08x, val - 0x%08x",
696 (u32) & ugeth->ug_regs->ipgifg,
697 in_be32(&ugeth->ug_regs->ipgifg));
698 ugeth_info("hafdup : addr - 0x%08x, val - 0x%08x",
699 (u32) & ugeth->ug_regs->hafdup,
700 in_be32(&ugeth->ug_regs->hafdup));
ce973b14
LY		 701 ugeth_info("ifctl : addr - 0x%08x, val - 0x%08x",
702 (u32) & ugeth->ug_regs->ifctl,
703 in_be32(&ugeth->ug_regs->ifctl));
704 ugeth_info("ifstat : addr - 0x%08x, val - 0x%08x",
705 (u32) & ugeth->ug_regs->ifstat,
706 in_be32(&ugeth->ug_regs->ifstat));
707 ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
708 (u32) & ugeth->ug_regs->macstnaddr1,
709 in_be32(&ugeth->ug_regs->macstnaddr1));
710 ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
711 (u32) & ugeth->ug_regs->macstnaddr2,
712 in_be32(&ugeth->ug_regs->macstnaddr2));
713 ugeth_info("uempr : addr - 0x%08x, val - 0x%08x",
714 (u32) & ugeth->ug_regs->uempr,
715 in_be32(&ugeth->ug_regs->uempr));
716 ugeth_info("utbipar : addr - 0x%08x, val - 0x%08x",
717 (u32) & ugeth->ug_regs->utbipar,
718 in_be32(&ugeth->ug_regs->utbipar));
719 ugeth_info("uescr : addr - 0x%08x, val - 0x%04x",
720 (u32) & ugeth->ug_regs->uescr,
721 in_be16(&ugeth->ug_regs->uescr));
722 ugeth_info("tx64 : addr - 0x%08x, val - 0x%08x",
723 (u32) & ugeth->ug_regs->tx64,
724 in_be32(&ugeth->ug_regs->tx64));
725 ugeth_info("tx127 : addr - 0x%08x, val - 0x%08x",
726 (u32) & ugeth->ug_regs->tx127,
727 in_be32(&ugeth->ug_regs->tx127));
728 ugeth_info("tx255 : addr - 0x%08x, val - 0x%08x",
729 (u32) & ugeth->ug_regs->tx255,
730 in_be32(&ugeth->ug_regs->tx255));
731 ugeth_info("rx64 : addr - 0x%08x, val - 0x%08x",
732 (u32) & ugeth->ug_regs->rx64,
733 in_be32(&ugeth->ug_regs->rx64));
734 ugeth_info("rx127 : addr - 0x%08x, val - 0x%08x",
735 (u32) & ugeth->ug_regs->rx127,
736 in_be32(&ugeth->ug_regs->rx127));
737 ugeth_info("rx255 : addr - 0x%08x, val - 0x%08x",
738 (u32) & ugeth->ug_regs->rx255,
739 in_be32(&ugeth->ug_regs->rx255));
740 ugeth_info("txok : addr - 0x%08x, val - 0x%08x",
741 (u32) & ugeth->ug_regs->txok,
742 in_be32(&ugeth->ug_regs->txok));
743 ugeth_info("txcf : addr - 0x%08x, val - 0x%04x",
744 (u32) & ugeth->ug_regs->txcf,
745 in_be16(&ugeth->ug_regs->txcf));
746 ugeth_info("tmca : addr - 0x%08x, val - 0x%08x",
747 (u32) & ugeth->ug_regs->tmca,
748 in_be32(&ugeth->ug_regs->tmca));
749 ugeth_info("tbca : addr - 0x%08x, val - 0x%08x",
750 (u32) & ugeth->ug_regs->tbca,
751 in_be32(&ugeth->ug_regs->tbca));
752 ugeth_info("rxfok : addr - 0x%08x, val - 0x%08x",
753 (u32) & ugeth->ug_regs->rxfok,
754 in_be32(&ugeth->ug_regs->rxfok));
755 ugeth_info("rxbok : addr - 0x%08x, val - 0x%08x",
756 (u32) & ugeth->ug_regs->rxbok,
757 in_be32(&ugeth->ug_regs->rxbok));
758 ugeth_info("rbyt : addr - 0x%08x, val - 0x%08x",
759 (u32) & ugeth->ug_regs->rbyt,
760 in_be32(&ugeth->ug_regs->rbyt));
761 ugeth_info("rmca : addr - 0x%08x, val - 0x%08x",
762 (u32) & ugeth->ug_regs->rmca,
763 in_be32(&ugeth->ug_regs->rmca));
764 ugeth_info("rbca : addr - 0x%08x, val - 0x%08x",
765 (u32) & ugeth->ug_regs->rbca,
766 in_be32(&ugeth->ug_regs->rbca));
767 ugeth_info("scar : addr - 0x%08x, val - 0x%08x",
768 (u32) & ugeth->ug_regs->scar,
769 in_be32(&ugeth->ug_regs->scar));
770 ugeth_info("scam : addr - 0x%08x, val - 0x%08x",
771 (u32) & ugeth->ug_regs->scam,
772 in_be32(&ugeth->ug_regs->scam));
773
774 if (ugeth->p_thread_data_tx) {
775 int numThreadsTxNumerical;
776 switch (ugeth->ug_info->numThreadsTx) {
777 case UCC_GETH_NUM_OF_THREADS_1:
778 numThreadsTxNumerical = 1;
779 break;
780 case UCC_GETH_NUM_OF_THREADS_2:
781 numThreadsTxNumerical = 2;
782 break;
783 case UCC_GETH_NUM_OF_THREADS_4:
784 numThreadsTxNumerical = 4;
785 break;
786 case UCC_GETH_NUM_OF_THREADS_6:
787 numThreadsTxNumerical = 6;
788 break;
789 case UCC_GETH_NUM_OF_THREADS_8:
790 numThreadsTxNumerical = 8;
791 break;
792 default:
793 numThreadsTxNumerical = 0;
794 break;
795 }
796
797 ugeth_info("Thread data TXs:");
798 ugeth_info("Base address: 0x%08x",
799 (u32) ugeth->p_thread_data_tx);
800 for (i = 0; i < numThreadsTxNumerical; i++) {
801 ugeth_info("Thread data TX[%d]:", i);
802 ugeth_info("Base address: 0x%08x",
803 (u32) & ugeth->p_thread_data_tx[i]);
804 mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
18a8e864 805 sizeof(struct ucc_geth_thread_data_tx));
ce973b14
LY		 806 }
807 }
808 if (ugeth->p_thread_data_rx) {
809 int numThreadsRxNumerical;
810 switch (ugeth->ug_info->numThreadsRx) {
811 case UCC_GETH_NUM_OF_THREADS_1:
812 numThreadsRxNumerical = 1;
813 break;
814 case UCC_GETH_NUM_OF_THREADS_2:
815 numThreadsRxNumerical = 2;
816 break;
817 case UCC_GETH_NUM_OF_THREADS_4:
818 numThreadsRxNumerical = 4;
819 break;
820 case UCC_GETH_NUM_OF_THREADS_6:
821 numThreadsRxNumerical = 6;
822 break;
823 case UCC_GETH_NUM_OF_THREADS_8:
824 numThreadsRxNumerical = 8;
825 break;
826 default:
827 numThreadsRxNumerical = 0;
828 break;
829 }
830
831 ugeth_info("Thread data RX:");
832 ugeth_info("Base address: 0x%08x",
833 (u32) ugeth->p_thread_data_rx);
834 for (i = 0; i < numThreadsRxNumerical; i++) {
835 ugeth_info("Thread data RX[%d]:", i);
836 ugeth_info("Base address: 0x%08x",
837 (u32) & ugeth->p_thread_data_rx[i]);
838 mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
18a8e864 839 sizeof(struct ucc_geth_thread_data_rx));
ce973b14
LY		 840 }
841 }
842 if (ugeth->p_exf_glbl_param) {
843 ugeth_info("EXF global param:");
844 ugeth_info("Base address: 0x%08x",
845 (u32) ugeth->p_exf_glbl_param);
846 mem_disp((u8 *) ugeth->p_exf_glbl_param,
847 sizeof(*ugeth->p_exf_glbl_param));
848 }
849 if (ugeth->p_tx_glbl_pram) {
850 ugeth_info("TX global param:");
851 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
852 ugeth_info("temoder : addr - 0x%08x, val - 0x%04x",
853 (u32) & ugeth->p_tx_glbl_pram->temoder,
854 in_be16(&ugeth->p_tx_glbl_pram->temoder));
855 ugeth_info("sqptr : addr - 0x%08x, val - 0x%08x",
856 (u32) & ugeth->p_tx_glbl_pram->sqptr,
857 in_be32(&ugeth->p_tx_glbl_pram->sqptr));
858 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
859 (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
860 in_be32(&ugeth->p_tx_glbl_pram->
861 schedulerbasepointer));
862 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
863 (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
864 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
865 ugeth_info("tstate : addr - 0x%08x, val - 0x%08x",
866 (u32) & ugeth->p_tx_glbl_pram->tstate,
867 in_be32(&ugeth->p_tx_glbl_pram->tstate));
868 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
869 (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
870 ugeth->p_tx_glbl_pram->iphoffset[0]);
871 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
872 (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
873 ugeth->p_tx_glbl_pram->iphoffset[1]);
874 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
875 (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
876 ugeth->p_tx_glbl_pram->iphoffset[2]);
877 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
878 (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
879 ugeth->p_tx_glbl_pram->iphoffset[3]);
880 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
881 (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
882 ugeth->p_tx_glbl_pram->iphoffset[4]);
883 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
884 (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
885 ugeth->p_tx_glbl_pram->iphoffset[5]);
886 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
887 (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
888 ugeth->p_tx_glbl_pram->iphoffset[6]);
889 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
890 (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
891 ugeth->p_tx_glbl_pram->iphoffset[7]);
892 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
893 (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
894 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
895 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
896 (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
897 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
898 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
899 (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
900 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
901 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
902 (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
903 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
904 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
905 (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
906 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
907 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
908 (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
909 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
910 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
911 (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
912 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
913 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
914 (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
915 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
916 ugeth_info("tqptr : addr - 0x%08x, val - 0x%08x",
917 (u32) & ugeth->p_tx_glbl_pram->tqptr,
918 in_be32(&ugeth->p_tx_glbl_pram->tqptr));
919 }
920 if (ugeth->p_rx_glbl_pram) {
921 ugeth_info("RX global param:");
922 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
923 ugeth_info("remoder : addr - 0x%08x, val - 0x%08x",
924 (u32) & ugeth->p_rx_glbl_pram->remoder,
925 in_be32(&ugeth->p_rx_glbl_pram->remoder));
926 ugeth_info("rqptr : addr - 0x%08x, val - 0x%08x",
927 (u32) & ugeth->p_rx_glbl_pram->rqptr,
928 in_be32(&ugeth->p_rx_glbl_pram->rqptr));
929 ugeth_info("typeorlen : addr - 0x%08x, val - 0x%04x",
930 (u32) & ugeth->p_rx_glbl_pram->typeorlen,
931 in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
932 ugeth_info("rxgstpack : addr - 0x%08x, val - 0x%02x",
933 (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
934 ugeth->p_rx_glbl_pram->rxgstpack);
935 ugeth_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x",
936 (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
937 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
938 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
939 (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
940 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
941 ugeth_info("rstate : addr - 0x%08x, val - 0x%02x",
942 (u32) & ugeth->p_rx_glbl_pram->rstate,
943 ugeth->p_rx_glbl_pram->rstate);
944 ugeth_info("mrblr : addr - 0x%08x, val - 0x%04x",
945 (u32) & ugeth->p_rx_glbl_pram->mrblr,
946 in_be16(&ugeth->p_rx_glbl_pram->mrblr));
947 ugeth_info("rbdqptr : addr - 0x%08x, val - 0x%08x",
948 (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
949 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
950 ugeth_info("mflr : addr - 0x%08x, val - 0x%04x",
951 (u32) & ugeth->p_rx_glbl_pram->mflr,
952 in_be16(&ugeth->p_rx_glbl_pram->mflr));
953 ugeth_info("minflr : addr - 0x%08x, val - 0x%04x",
954 (u32) & ugeth->p_rx_glbl_pram->minflr,
955 in_be16(&ugeth->p_rx_glbl_pram->minflr));
956 ugeth_info("maxd1 : addr - 0x%08x, val - 0x%04x",
957 (u32) & ugeth->p_rx_glbl_pram->maxd1,
958 in_be16(&ugeth->p_rx_glbl_pram->maxd1));
959 ugeth_info("maxd2 : addr - 0x%08x, val - 0x%04x",
960 (u32) & ugeth->p_rx_glbl_pram->maxd2,
961 in_be16(&ugeth->p_rx_glbl_pram->maxd2));
962 ugeth_info("ecamptr : addr - 0x%08x, val - 0x%08x",
963 (u32) & ugeth->p_rx_glbl_pram->ecamptr,
964 in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
965 ugeth_info("l2qt : addr - 0x%08x, val - 0x%08x",
966 (u32) & ugeth->p_rx_glbl_pram->l2qt,
967 in_be32(&ugeth->p_rx_glbl_pram->l2qt));
968 ugeth_info("l3qt[0] : addr - 0x%08x, val - 0x%08x",
969 (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
970 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
971 ugeth_info("l3qt[1] : addr - 0x%08x, val - 0x%08x",
972 (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
973 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
974 ugeth_info("l3qt[2] : addr - 0x%08x, val - 0x%08x",
975 (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
976 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
977 ugeth_info("l3qt[3] : addr - 0x%08x, val - 0x%08x",
978 (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
979 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
980 ugeth_info("l3qt[4] : addr - 0x%08x, val - 0x%08x",
981 (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
982 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
983 ugeth_info("l3qt[5] : addr - 0x%08x, val - 0x%08x",
984 (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
985 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
986 ugeth_info("l3qt[6] : addr - 0x%08x, val - 0x%08x",
987 (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
988 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
989 ugeth_info("l3qt[7] : addr - 0x%08x, val - 0x%08x",
990 (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
991 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
992 ugeth_info("vlantype : addr - 0x%08x, val - 0x%04x",
993 (u32) & ugeth->p_rx_glbl_pram->vlantype,
994 in_be16(&ugeth->p_rx_glbl_pram->vlantype));
995 ugeth_info("vlantci : addr - 0x%08x, val - 0x%04x",
996 (u32) & ugeth->p_rx_glbl_pram->vlantci,
997 in_be16(&ugeth->p_rx_glbl_pram->vlantci));
998 for (i = 0; i < 64; i++)
999 ugeth_info
1000 ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
1001 i,
1002 (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
1003 ugeth->p_rx_glbl_pram->addressfiltering[i]);
1004 ugeth_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x",
1005 (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
1006 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
1007 }
1008 if (ugeth->p_send_q_mem_reg) {
1009 ugeth_info("Send Q memory registers:");
1010 ugeth_info("Base address: 0x%08x",
1011 (u32) ugeth->p_send_q_mem_reg);
1012 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1013 ugeth_info("SQQD[%d]:", i);
1014 ugeth_info("Base address: 0x%08x",
1015 (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
1016 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
18a8e864 1017 sizeof(struct ucc_geth_send_queue_qd));
ce973b14
LY		 1018 }
1019 }
1020 if (ugeth->p_scheduler) {
1021 ugeth_info("Scheduler:");
1022 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
1023 mem_disp((u8 *) ugeth->p_scheduler,
1024 sizeof(*ugeth->p_scheduler));
1025 }
1026 if (ugeth->p_tx_fw_statistics_pram) {
1027 ugeth_info("TX FW statistics pram:");
1028 ugeth_info("Base address: 0x%08x",
1029 (u32) ugeth->p_tx_fw_statistics_pram);
1030 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
1031 sizeof(*ugeth->p_tx_fw_statistics_pram));
1032 }
1033 if (ugeth->p_rx_fw_statistics_pram) {
1034 ugeth_info("RX FW statistics pram:");
1035 ugeth_info("Base address: 0x%08x",
1036 (u32) ugeth->p_rx_fw_statistics_pram);
1037 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
1038 sizeof(*ugeth->p_rx_fw_statistics_pram));
1039 }
1040 if (ugeth->p_rx_irq_coalescing_tbl) {
1041 ugeth_info("RX IRQ coalescing tables:");
1042 ugeth_info("Base address: 0x%08x",
1043 (u32) ugeth->p_rx_irq_coalescing_tbl);
1044 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1045 ugeth_info("RX IRQ coalescing table entry[%d]:", i);
1046 ugeth_info("Base address: 0x%08x",
1047 (u32) & ugeth->p_rx_irq_coalescing_tbl->
1048 coalescingentry[i]);
1049 ugeth_info
1050 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
1051 (u32) & ugeth->p_rx_irq_coalescing_tbl->
1052 coalescingentry[i].interruptcoalescingmaxvalue,
1053 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1054 coalescingentry[i].
1055 interruptcoalescingmaxvalue));
1056 ugeth_info
1057 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
1058 (u32) & ugeth->p_rx_irq_coalescing_tbl->
1059 coalescingentry[i].interruptcoalescingcounter,
1060 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1061 coalescingentry[i].
1062 interruptcoalescingcounter));
1063 }
1064 }
1065 if (ugeth->p_rx_bd_qs_tbl) {
1066 ugeth_info("RX BD QS tables:");
1067 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
1068 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1069 ugeth_info("RX BD QS table[%d]:", i);
1070 ugeth_info("Base address: 0x%08x",
1071 (u32) & ugeth->p_rx_bd_qs_tbl[i]);
1072 ugeth_info
1073 ("bdbaseptr : addr - 0x%08x, val - 0x%08x",
1074 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
1075 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
1076 ugeth_info
1077 ("bdptr : addr - 0x%08x, val - 0x%08x",
1078 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
1079 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
1080 ugeth_info
1081 ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
1082 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
1083 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
1084 externalbdbaseptr));
1085 ugeth_info
1086 ("externalbdptr : addr - 0x%08x, val - 0x%08x",
1087 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
1088 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
1089 ugeth_info("ucode RX Prefetched BDs:");
1090 ugeth_info("Base address: 0x%08x",
1091 (u32)
1092 qe_muram_addr(in_be32
1093 (&ugeth->p_rx_bd_qs_tbl[i].
1094 bdbaseptr)));
1095 mem_disp((u8 *)
1096 qe_muram_addr(in_be32
1097 (&ugeth->p_rx_bd_qs_tbl[i].
1098 bdbaseptr)),
18a8e864 1099 sizeof(struct ucc_geth_rx_prefetched_bds));
ce973b14
LY		 1100 }
1101 }
1102 if (ugeth->p_init_enet_param_shadow) {
1103 int size;
1104 ugeth_info("Init enet param shadow:");
1105 ugeth_info("Base address: 0x%08x",
1106 (u32) ugeth->p_init_enet_param_shadow);
1107 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1108 sizeof(*ugeth->p_init_enet_param_shadow));
1109
18a8e864 1110 size = sizeof(struct ucc_geth_thread_rx_pram);
ce973b14
LY		 1111 if (ugeth->ug_info->rxExtendedFiltering) {
1112 size +=
1113 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1114 if (ugeth->ug_info->largestexternallookupkeysize ==
1115 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1116 size +=
1117 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1118 if (ugeth->ug_info->largestexternallookupkeysize ==
1119 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1120 size +=
1121 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1122 }
1123
1124 dump_init_enet_entries(ugeth,
1125 &(ugeth->p_init_enet_param_shadow->
1126 txthread[0]),
1127 ENET_INIT_PARAM_MAX_ENTRIES_TX,
18a8e864 1128 sizeof(struct ucc_geth_thread_tx_pram),
ce973b14
LY		 1129 ugeth->ug_info->riscTx, 0);
1130 dump_init_enet_entries(ugeth,
1131 &(ugeth->p_init_enet_param_shadow->
1132 rxthread[0]),
1133 ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1134 ugeth->ug_info->riscRx, 1);
1135 }
1136}
1137#endif /* DEBUG */
1138
6fee40e9
AF		 1139static void init_default_reg_vals(u32 __iomem *upsmr_register,
1140 u32 __iomem *maccfg1_register,
1141 u32 __iomem *maccfg2_register)
ce973b14
LY		 1142{
1143 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1144 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1145 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1146}
1147
1148static int init_half_duplex_params(int alt_beb,
1149 int back_pressure_no_backoff,
1150 int no_backoff,
1151 int excess_defer,
1152 u8 alt_beb_truncation,
1153 u8 max_retransmissions,
1154 u8 collision_window,
6fee40e9 1155 u32 __iomem *hafdup_register)
ce973b14
LY		 1156{
1157 u32 value = 0;
1158
1159 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1160 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1161 (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1162 return -EINVAL;
1163
1164 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1165
1166 if (alt_beb)
1167 value |= HALFDUP_ALT_BEB;
1168 if (back_pressure_no_backoff)
1169 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1170 if (no_backoff)
1171 value |= HALFDUP_NO_BACKOFF;
1172 if (excess_defer)
1173 value |= HALFDUP_EXCESSIVE_DEFER;
1174
1175 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1176
1177 value |= collision_window;
1178
1179 out_be32(hafdup_register, value);
1180 return 0;
1181}
1182
1183static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1184 u8 non_btb_ipg,
1185 u8 min_ifg,
1186 u8 btb_ipg,
6fee40e9 1187 u32 __iomem *ipgifg_register)
ce973b14
LY		 1188{
1189 u32 value = 0;
1190
1191 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1192 IPG part 2 */
1193 if (non_btb_cs_ipg > non_btb_ipg)
1194 return -EINVAL;
1195
1196 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1197 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1198 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1199 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1200 return -EINVAL;
1201
1202 value |=
1203 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1204 IPGIFG_NBTB_CS_IPG_MASK);
1205 value |=
1206 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1207 IPGIFG_NBTB_IPG_MASK);
1208 value |=
1209 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1210 IPGIFG_MIN_IFG_MASK);
1211 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1212
1213 out_be32(ipgifg_register, value);
1214 return 0;
1215}
1216
ac421852 1217int init_flow_control_params(u32 automatic_flow_control_mode,
ce973b14
LY		 1218 int rx_flow_control_enable,
1219 int tx_flow_control_enable,
1220 u16 pause_period,
1221 u16 extension_field,
6fee40e9
AF		 1222 u32 __iomem *upsmr_register,
1223 u32 __iomem *uempr_register,
1224 u32 __iomem *maccfg1_register)
ce973b14
LY		 1225{
1226 u32 value = 0;
1227
1228 /* Set UEMPR register */
1229 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1230 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1231 out_be32(uempr_register, value);
1232
1233 /* Set UPSMR register */
1234 value = in_be32(upsmr_register);
1235 value |= automatic_flow_control_mode;
1236 out_be32(upsmr_register, value);
1237
1238 value = in_be32(maccfg1_register);
1239 if (rx_flow_control_enable)
1240 value |= MACCFG1_FLOW_RX;
1241 if (tx_flow_control_enable)
1242 value |= MACCFG1_FLOW_TX;
1243 out_be32(maccfg1_register, value);
1244
1245 return 0;
1246}
1247
1248static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1249 int auto_zero_hardware_statistics,
6fee40e9
AF		 1250 u32 __iomem *upsmr_register,
1251 u16 __iomem *uescr_register)
ce973b14
LY		 1252{
1253 u32 upsmr_value = 0;
1254 u16 uescr_value = 0;
1255 /* Enable hardware statistics gathering if requested */
1256 if (enable_hardware_statistics) {
1257 upsmr_value = in_be32(upsmr_register);
1258 upsmr_value |= UPSMR_HSE;
1259 out_be32(upsmr_register, upsmr_value);
1260 }
1261
1262 /* Clear hardware statistics counters */
1263 uescr_value = in_be16(uescr_register);
1264 uescr_value |= UESCR_CLRCNT;
1265 /* Automatically zero hardware statistics counters on read,
1266 if requested */
1267 if (auto_zero_hardware_statistics)
1268 uescr_value |= UESCR_AUTOZ;
1269 out_be16(uescr_register, uescr_value);
1270
1271 return 0;
1272}
1273
1274static int init_firmware_statistics_gathering_mode(int
1275 enable_tx_firmware_statistics,
1276 int enable_rx_firmware_statistics,
6fee40e9 1277 u32 __iomem *tx_rmon_base_ptr,
ce973b14 1278 u32 tx_firmware_statistics_structure_address,
6fee40e9 1279 u32 __iomem *rx_rmon_base_ptr,
ce973b14 1280 u32 rx_firmware_statistics_structure_address,
6fee40e9
AF		 1281 u16 __iomem *temoder_register,
1282 u32 __iomem *remoder_register)
ce973b14
LY		 1283{
1284 /* Note: this function does not check if */
1285 /* the parameters it receives are NULL */
1286 u16 temoder_value;
1287 u32 remoder_value;
1288
1289 if (enable_tx_firmware_statistics) {
1290 out_be32(tx_rmon_base_ptr,
1291 tx_firmware_statistics_structure_address);
1292 temoder_value = in_be16(temoder_register);
1293 temoder_value |= TEMODER_TX_RMON_STATISTICS_ENABLE;
1294 out_be16(temoder_register, temoder_value);
1295 }
1296
1297 if (enable_rx_firmware_statistics) {
1298 out_be32(rx_rmon_base_ptr,
1299 rx_firmware_statistics_structure_address);
1300 remoder_value = in_be32(remoder_register);
1301 remoder_value |= REMODER_RX_RMON_STATISTICS_ENABLE;
1302 out_be32(remoder_register, remoder_value);
1303 }
1304
1305 return 0;
1306}
1307
1308static int init_mac_station_addr_regs(u8 address_byte_0,
1309 u8 address_byte_1,
1310 u8 address_byte_2,
1311 u8 address_byte_3,
1312 u8 address_byte_4,
1313 u8 address_byte_5,
6fee40e9
AF		 1314 u32 __iomem *macstnaddr1_register,
1315 u32 __iomem *macstnaddr2_register)
ce973b14
LY		 1316{
1317 u32 value = 0;
1318
1319 /* Example: for a station address of 0x12345678ABCD, */
1320 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1321
1322 /* MACSTNADDR1 Register: */
1323
1324 /* 0 7 8 15 */
1325 /* station address byte 5 station address byte 4 */
1326 /* 16 23 24 31 */
1327 /* station address byte 3 station address byte 2 */
1328 value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1329 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1330 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1331 value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1332
1333 out_be32(macstnaddr1_register, value);
1334
1335 /* MACSTNADDR2 Register: */
1336
1337 /* 0 7 8 15 */
1338 /* station address byte 1 station address byte 0 */
1339 /* 16 23 24 31 */
1340 /* reserved reserved */
1341 value = 0;
1342 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1343 value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1344
1345 out_be32(macstnaddr2_register, value);
1346
1347 return 0;
1348}
1349
ce973b14 1350static int init_check_frame_length_mode(int length_check,
6fee40e9 1351 u32 __iomem *maccfg2_register)
ce973b14
LY		 1352{
1353 u32 value = 0;
1354
1355 value = in_be32(maccfg2_register);
1356
1357 if (length_check)
1358 value |= MACCFG2_LC;
1359 else
1360 value &= ~MACCFG2_LC;
1361
1362 out_be32(maccfg2_register, value);
1363 return 0;
1364}
1365
1366static int init_preamble_length(u8 preamble_length,
6fee40e9 1367 u32 __iomem *maccfg2_register)
ce973b14
LY		 1368{
1369 u32 value = 0;
1370
1371 if ((preamble_length < 3) || (preamble_length > 7))
1372 return -EINVAL;
1373
1374 value = in_be32(maccfg2_register);
1375 value &= ~MACCFG2_PREL_MASK;
1376 value |= (preamble_length << MACCFG2_PREL_SHIFT);
1377 out_be32(maccfg2_register, value);
1378 return 0;
1379}
1380
ce973b14
LY		 1381static int init_rx_parameters(int reject_broadcast,
1382 int receive_short_frames,
6fee40e9 1383 int promiscuous, u32 __iomem *upsmr_register)
ce973b14
LY		 1384{
1385 u32 value = 0;
1386
1387 value = in_be32(upsmr_register);
1388
1389 if (reject_broadcast)
1390 value |= UPSMR_BRO;
1391 else
1392 value &= ~UPSMR_BRO;
1393
1394 if (receive_short_frames)
1395 value |= UPSMR_RSH;
1396 else
1397 value &= ~UPSMR_RSH;
1398
1399 if (promiscuous)
1400 value |= UPSMR_PRO;
1401 else
1402 value &= ~UPSMR_PRO;
1403
1404 out_be32(upsmr_register, value);
1405
1406 return 0;
1407}
1408
1409static int init_max_rx_buff_len(u16 max_rx_buf_len,
6fee40e9 1410 u16 __iomem *mrblr_register)
ce973b14
LY		 1411{
1412 /* max_rx_buf_len value must be a multiple of 128 */
1413 if ((max_rx_buf_len == 0)
1414 || (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1415 return -EINVAL;
1416
1417 out_be16(mrblr_register, max_rx_buf_len);
1418 return 0;
1419}
1420
1421static int init_min_frame_len(u16 min_frame_length,
6fee40e9
AF		 1422 u16 __iomem *minflr_register,
1423 u16 __iomem *mrblr_register)
ce973b14
LY		 1424{
1425 u16 mrblr_value = 0;
1426
1427 mrblr_value = in_be16(mrblr_register);
1428 if (min_frame_length >= (mrblr_value - 4))
1429 return -EINVAL;
1430
1431 out_be16(minflr_register, min_frame_length);
1432 return 0;
1433}
1434
18a8e864 1435static int adjust_enet_interface(struct ucc_geth_private *ugeth)
ce973b14 1436{
18a8e864 1437 struct ucc_geth_info *ug_info;
6fee40e9
AF		 1438 struct ucc_geth __iomem *ug_regs;
1439 struct ucc_fast __iomem *uf_regs;
728de4c9
KP		 1440 int ret_val;
1441 u32 upsmr, maccfg2, tbiBaseAddress;
ce973b14
LY		 1442 u16 value;
1443
b39d66a8 1444 ugeth_vdbg("%s: IN", __func__);
ce973b14
LY		 1445
1446 ug_info = ugeth->ug_info;
1447 ug_regs = ugeth->ug_regs;
1448 uf_regs = ugeth->uccf->uf_regs;
1449
ce973b14
LY		 1450 /* Set MACCFG2 */
1451 maccfg2 = in_be32(&ug_regs->maccfg2);
1452 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
728de4c9
KP		 1453 if ((ugeth->max_speed == SPEED_10) ||
1454 (ugeth->max_speed == SPEED_100))
ce973b14 1455 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
728de4c9 1456 else if (ugeth->max_speed == SPEED_1000)
ce973b14
LY		 1457 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1458 maccfg2 |= ug_info->padAndCrc;
1459 out_be32(&ug_regs->maccfg2, maccfg2);
1460
1461 /* Set UPSMR */
1462 upsmr = in_be32(&uf_regs->upsmr);
1463 upsmr &= ~(UPSMR_RPM | UPSMR_R10M | UPSMR_TBIM | UPSMR_RMM);
728de4c9
KP		 1464 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1465 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1466 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
bd0ceaab
KP		 1467 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1468 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
728de4c9 1469 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
ce973b14 1470 upsmr |= UPSMR_RPM;
728de4c9
KP		 1471 switch (ugeth->max_speed) {
1472 case SPEED_10:
1473 upsmr |= UPSMR_R10M;
1474 /* FALLTHROUGH */
1475 case SPEED_100:
1476 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1477 upsmr |= UPSMR_RMM;
1478 }
1479 }
1480 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1481 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
ce973b14 1482 upsmr |= UPSMR_TBIM;
728de4c9 1483 }
ce973b14
LY		 1484 out_be32(&uf_regs->upsmr, upsmr);
1485
ce973b14
LY		 1486 /* Disable autonegotiation in tbi mode, because by default it
1487 comes up in autonegotiation mode. */
1488 /* Note that this depends on proper setting in utbipar register. */
728de4c9
KP		 1489 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1490 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
ce973b14
LY		 1491 tbiBaseAddress = in_be32(&ug_regs->utbipar);
1492 tbiBaseAddress &= UTBIPAR_PHY_ADDRESS_MASK;
1493 tbiBaseAddress >>= UTBIPAR_PHY_ADDRESS_SHIFT;
728de4c9
KP		 1494 value = ugeth->phydev->bus->read(ugeth->phydev->bus,
1495 (u8) tbiBaseAddress, ENET_TBI_MII_CR);
ce973b14 1496 value &= ~0x1000; /* Turn off autonegotiation */
728de4c9
KP		 1497 ugeth->phydev->bus->write(ugeth->phydev->bus,
1498 (u8) tbiBaseAddress, ENET_TBI_MII_CR, value);
ce973b14
LY		 1499 }
1500
1501 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1502
1503 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1504 if (ret_val != 0) {
890de95e
LY		 1505 if (netif_msg_probe(ugeth))
1506 ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.",
b39d66a8 1507 __func__);
ce973b14
LY		 1508 return ret_val;
1509 }
1510
1511 return 0;
1512}
1513
1514/* Called every time the controller might need to be made
1515 * aware of new link state. The PHY code conveys this
1516 * information through variables in the ugeth structure, and this
1517 * function converts those variables into the appropriate
1518 * register values, and can bring down the device if needed.
1519 */
728de4c9 1520
ce973b14
LY		 1521static void adjust_link(struct net_device *dev)
1522{
18a8e864 1523 struct ucc_geth_private *ugeth = netdev_priv(dev);
6fee40e9
AF		 1524 struct ucc_geth __iomem *ug_regs;
1525 struct ucc_fast __iomem *uf_regs;
728de4c9
KP		 1526 struct phy_device *phydev = ugeth->phydev;
1527 unsigned long flags;
1528 int new_state = 0;
ce973b14
LY		 1529
1530 ug_regs = ugeth->ug_regs;
728de4c9 1531 uf_regs = ugeth->uccf->uf_regs;
ce973b14 1532
728de4c9
KP		 1533 spin_lock_irqsave(&ugeth->lock, flags);
1534
1535 if (phydev->link) {
1536 u32 tempval = in_be32(&ug_regs->maccfg2);
1537 u32 upsmr = in_be32(&uf_regs->upsmr);
ce973b14
LY		 1538 /* Now we make sure that we can be in full duplex mode.
1539 * If not, we operate in half-duplex mode. */
728de4c9
KP		 1540 if (phydev->duplex != ugeth->oldduplex) {
1541 new_state = 1;
1542 if (!(phydev->duplex))
ce973b14 1543 tempval &= ~(MACCFG2_FDX);
728de4c9 1544 else
ce973b14 1545 tempval |= MACCFG2_FDX;
728de4c9 1546 ugeth->oldduplex = phydev->duplex;
ce973b14
LY		 1547 }
1548
728de4c9
KP		 1549 if (phydev->speed != ugeth->oldspeed) {
1550 new_state = 1;
1551 switch (phydev->speed) {
1552 case SPEED_1000:
1553 tempval = ((tempval &
1554 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1555 MACCFG2_INTERFACE_MODE_BYTE);
a1862a53 1556 break;
728de4c9
KP		 1557 case SPEED_100:
1558 case SPEED_10:
1559 tempval = ((tempval &
1560 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1561 MACCFG2_INTERFACE_MODE_NIBBLE);
1562 /* if reduced mode, re-set UPSMR.R10M */
1563 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1564 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1565 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
bd0ceaab
KP		 1566 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1567 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
728de4c9
KP		 1568 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1569 if (phydev->speed == SPEED_10)
1570 upsmr |= UPSMR_R10M;
1571 else
1572 upsmr &= ~(UPSMR_R10M);
1573 }
ce973b14
LY		 1574 break;
1575 default:
728de4c9
KP		 1576 if (netif_msg_link(ugeth))
1577 ugeth_warn(
1578 "%s: Ack! Speed (%d) is not 10/100/1000!",
1579 dev->name, phydev->speed);
ce973b14
LY		 1580 break;
1581 }
728de4c9 1582 ugeth->oldspeed = phydev->speed;
ce973b14
LY		 1583 }
1584
728de4c9
KP		 1585 out_be32(&ug_regs->maccfg2, tempval);
1586 out_be32(&uf_regs->upsmr, upsmr);
1587
ce973b14 1588 if (!ugeth->oldlink) {
728de4c9 1589 new_state = 1;
ce973b14 1590 ugeth->oldlink = 1;
ce973b14 1591 }
728de4c9
KP		 1592 } else if (ugeth->oldlink) {
1593 new_state = 1;
ce973b14
LY		 1594 ugeth->oldlink = 0;
1595 ugeth->oldspeed = 0;
1596 ugeth->oldduplex = -1;
ce973b14 1597 }
728de4c9
KP		 1598
1599 if (new_state && netif_msg_link(ugeth))
1600 phy_print_status(phydev);
1601
1602 spin_unlock_irqrestore(&ugeth->lock, flags);
ce973b14
LY		 1603}
1604
1605/* Configure the PHY for dev.
1606 * returns 0 if success. -1 if failure
1607 */
1608static int init_phy(struct net_device *dev)
1609{
728de4c9
KP		 1610 struct ucc_geth_private *priv = netdev_priv(dev);
1611 struct phy_device *phydev;
1612 char phy_id[BUS_ID_SIZE];
ce973b14 1613
728de4c9
KP		 1614 priv->oldlink = 0;
1615 priv->oldspeed = 0;
1616 priv->oldduplex = -1;
ce973b14 1617
fb28ad35
KS		 1618 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, priv->ug_info->mdio_bus,
1619 priv->ug_info->phy_address);
ce973b14 1620
728de4c9 1621 phydev = phy_connect(dev, phy_id, &adjust_link, 0, priv->phy_interface);
ce973b14 1622
728de4c9
KP		 1623 if (IS_ERR(phydev)) {
1624 printk("%s: Could not attach to PHY\n", dev->name);
1625 return PTR_ERR(phydev);
ce973b14
LY		 1626 }
1627
728de4c9 1628 phydev->supported &= (ADVERTISED_10baseT_Half |
ce973b14
LY		 1629 ADVERTISED_10baseT_Full |
1630 ADVERTISED_100baseT_Half |
728de4c9 1631 ADVERTISED_100baseT_Full);
ce973b14 1632
728de4c9
KP		 1633 if (priv->max_speed == SPEED_1000)
1634 phydev->supported |= ADVERTISED_1000baseT_Full;
ce973b14 1635
728de4c9 1636 phydev->advertising = phydev->supported;
68dc44af 1637
728de4c9 1638 priv->phydev = phydev;
ce973b14
LY		 1639
1640 return 0;
ce973b14
LY		 1641}
1642
728de4c9 1643
ce973b14 1644
18a8e864 1645static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
ce973b14 1646{
18a8e864 1647 struct ucc_fast_private *uccf;
ce973b14
LY		 1648 u32 cecr_subblock;
1649 u32 temp;
b3431c64 1650 int i = 10;
ce973b14
LY		 1651
1652 uccf = ugeth->uccf;
1653
1654 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1655 temp = in_be32(uccf->p_uccm);
1656 temp &= ~UCCE_GRA;
1657 out_be32(uccf->p_uccm, temp);
1658 out_be32(uccf->p_ucce, UCCE_GRA); /* clear by writing 1 */
1659
1660 /* Issue host command */
1661 cecr_subblock =
1662 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1663 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
18a8e864 1664 QE_CR_PROTOCOL_ETHERNET, 0);
ce973b14
LY		 1665
1666 /* Wait for command to complete */
1667 do {
b3431c64 1668 msleep(10);
ce973b14 1669 temp = in_be32(uccf->p_ucce);
b3431c64 1670 } while (!(temp & UCCE_GRA) && --i);
ce973b14
LY		 1671
1672 uccf->stopped_tx = 1;
1673
1674 return 0;
1675}
1676
18a8e864 1677static int ugeth_graceful_stop_rx(struct ucc_geth_private * ugeth)
ce973b14 1678{
18a8e864 1679 struct ucc_fast_private *uccf;
ce973b14
LY		 1680 u32 cecr_subblock;
1681 u8 temp;
b3431c64 1682 int i = 10;
ce973b14
LY		 1683
1684 uccf = ugeth->uccf;
1685
1686 /* Clear acknowledge bit */
6fee40e9 1687 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
ce973b14 1688 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
6fee40e9 1689 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
ce973b14
LY		 1690
1691 /* Keep issuing command and checking acknowledge bit until
1692 it is asserted, according to spec */
1693 do {
1694 /* Issue host command */
1695 cecr_subblock =
1696 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1697 ucc_num);
1698 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
18a8e864 1699 QE_CR_PROTOCOL_ETHERNET, 0);
b3431c64 1700 msleep(10);
6fee40e9 1701 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
b3431c64 1702 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
ce973b14
LY		 1703
1704 uccf->stopped_rx = 1;
1705
1706 return 0;
1707}
1708
18a8e864 1709static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
ce973b14 1710{
18a8e864 1711 struct ucc_fast_private *uccf;
ce973b14
LY		 1712 u32 cecr_subblock;
1713
1714 uccf = ugeth->uccf;
1715
1716 cecr_subblock =
1717 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
18a8e864 1718 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
ce973b14
LY		 1719 uccf->stopped_tx = 0;
1720
1721 return 0;
1722}
1723
18a8e864 1724static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
ce973b14 1725{
18a8e864 1726 struct ucc_fast_private *uccf;
ce973b14
LY		 1727 u32 cecr_subblock;
1728
1729 uccf = ugeth->uccf;
1730
1731 cecr_subblock =
1732 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
18a8e864 1733 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
ce973b14
LY		 1734 0);
1735 uccf->stopped_rx = 0;
1736
1737 return 0;
1738}
1739
18a8e864 1740static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
ce973b14 1741{
18a8e864 1742 struct ucc_fast_private *uccf;
ce973b14
LY		 1743 int enabled_tx, enabled_rx;
1744
1745 uccf = ugeth->uccf;
1746
1747 /* check if the UCC number is in range. */
1748 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
890de95e 1749 if (netif_msg_probe(ugeth))
b39d66a8 1750 ugeth_err("%s: ucc_num out of range.", __func__);
ce973b14
LY		 1751 return -EINVAL;
1752 }
1753
1754 enabled_tx = uccf->enabled_tx;
1755 enabled_rx = uccf->enabled_rx;
1756
1757 /* Get Tx and Rx going again, in case this channel was actively
1758 disabled. */
1759 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1760 ugeth_restart_tx(ugeth);
1761 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1762 ugeth_restart_rx(ugeth);
1763
1764 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */
1765
1766 return 0;
1767
1768}
1769
18a8e864 1770static int ugeth_disable(struct ucc_geth_private * ugeth, enum comm_dir mode)
ce973b14 1771{
18a8e864 1772 struct ucc_fast_private *uccf;
ce973b14
LY		 1773
1774 uccf = ugeth->uccf;
1775
1776 /* check if the UCC number is in range. */
1777 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
890de95e 1778 if (netif_msg_probe(ugeth))
b39d66a8 1779 ugeth_err("%s: ucc_num out of range.", __func__);
ce973b14
LY		 1780 return -EINVAL;
1781 }
1782
1783 /* Stop any transmissions */
1784 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1785 ugeth_graceful_stop_tx(ugeth);
1786
1787 /* Stop any receptions */
1788 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1789 ugeth_graceful_stop_rx(ugeth);
1790
1791 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1792
1793 return 0;
1794}
1795
18a8e864 1796static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
ce973b14
LY		 1797{
1798#ifdef DEBUG
1799 ucc_fast_dump_regs(ugeth->uccf);
1800 dump_regs(ugeth);
1801 dump_bds(ugeth);
1802#endif
1803}
1804
1805#ifdef CONFIG_UGETH_FILTERING
18a8e864 1806static int ugeth_ext_filtering_serialize_tad(struct ucc_geth_tad_params *
ce973b14 1807 p_UccGethTadParams,
18a8e864 1808 struct qe_fltr_tad *qe_fltr_tad)
ce973b14
LY		 1809{
1810 u16 temp;
1811
1812 /* Zero serialized TAD */
1813 memset(qe_fltr_tad, 0, QE_FLTR_TAD_SIZE);
1814
1815 qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_V; /* Must have this */
1816 if (p_UccGethTadParams->rx_non_dynamic_extended_features_mode ||
1817 (p_UccGethTadParams->vtag_op != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
1818 || (p_UccGethTadParams->vnontag_op !=
1819 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP)
1820 )
1821 qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_EF;
1822 if (p_UccGethTadParams->reject_frame)
1823 qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_REJ;
1824 temp =
1825 (u16) (((u16) p_UccGethTadParams->
1826 vtag_op) << UCC_GETH_TAD_VTAG_OP_SHIFT);
1827 qe_fltr_tad->serialized[0] |= (u8) (temp >> 8); /* upper bits */
1828
1829 qe_fltr_tad->serialized[1] |= (u8) (temp & 0x00ff); /* lower bits */
1830 if (p_UccGethTadParams->vnontag_op ==
1831 UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT)
1832 qe_fltr_tad->serialized[1] |= UCC_GETH_TAD_V_NON_VTAG_OP;
1833 qe_fltr_tad->serialized[1] |=
1834 p_UccGethTadParams->rqos << UCC_GETH_TAD_RQOS_SHIFT;
1835
1836 qe_fltr_tad->serialized[2] |=
1837 p_UccGethTadParams->vpri << UCC_GETH_TAD_V_PRIORITY_SHIFT;
1838 /* upper bits */
1839 qe_fltr_tad->serialized[2] |= (u8) (p_UccGethTadParams->vid >> 8);
1840 /* lower bits */
1841 qe_fltr_tad->serialized[3] |= (u8) (p_UccGethTadParams->vid & 0x00ff);
1842
1843 return 0;
1844}
1845
18a8e864
LY		 1846static struct enet_addr_container_t
1847 *ugeth_82xx_filtering_get_match_addr_in_hash(struct ucc_geth_private *ugeth,
1848 struct enet_addr *p_enet_addr)
ce973b14 1849{
18a8e864 1850 struct enet_addr_container *enet_addr_cont;
ce973b14
LY		 1851 struct list_head *p_lh;
1852 u16 i, num;
1853 int32_t j;
1854 u8 *p_counter;
1855
1856 if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
1857 p_lh = &ugeth->group_hash_q;
1858 p_counter = &(ugeth->numGroupAddrInHash);
1859 } else {
1860 p_lh = &ugeth->ind_hash_q;
1861 p_counter = &(ugeth->numIndAddrInHash);
1862 }
1863
1864 if (!p_lh)
1865 return NULL;
1866
1867 num = *p_counter;
1868
1869 for (i = 0; i < num; i++) {
1870 enet_addr_cont =
18a8e864 1871 (struct enet_addr_container *)
ce973b14
LY		 1872 ENET_ADDR_CONT_ENTRY(dequeue(p_lh));
1873 for (j = ENET_NUM_OCTETS_PER_ADDRESS - 1; j >= 0; j--) {
1874 if ((*p_enet_addr)[j] != (enet_addr_cont->address)[j])
1875 break;
1876 if (j == 0)
1877 return enet_addr_cont; /* Found */
1878 }
1879 enqueue(p_lh, &enet_addr_cont->node); /* Put it back */
1880 }
1881 return NULL;
1882}
1883
18a8e864
LY		 1884static int ugeth_82xx_filtering_add_addr_in_hash(struct ucc_geth_private *ugeth,
1885 struct enet_addr *p_enet_addr)
ce973b14 1886{
18a8e864
LY		 1887 enum ucc_geth_enet_address_recognition_location location;
1888 struct enet_addr_container *enet_addr_cont;
ce973b14
LY		 1889 struct list_head *p_lh;
1890 u8 i;
1891 u32 limit;
1892 u8 *p_counter;
1893
1894 if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
1895 p_lh = &ugeth->group_hash_q;
1896 limit = ugeth->ug_info->maxGroupAddrInHash;
1897 location =
1898 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH;
1899 p_counter = &(ugeth->numGroupAddrInHash);
1900 } else {
1901 p_lh = &ugeth->ind_hash_q;
1902 limit = ugeth->ug_info->maxIndAddrInHash;
1903 location =
1904 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH;
1905 p_counter = &(ugeth->numIndAddrInHash);
1906 }
1907
1908 if ((enet_addr_cont =
1909 ugeth_82xx_filtering_get_match_addr_in_hash(ugeth, p_enet_addr))) {
1910 list_add(p_lh, &enet_addr_cont->node); /* Put it back */
1911 return 0;
1912 }
1913 if ((!p_lh) || (!(*p_counter < limit)))
1914 return -EBUSY;
1915 if (!(enet_addr_cont = get_enet_addr_container()))
1916 return -ENOMEM;
1917 for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++)
1918 (enet_addr_cont->address)[i] = (*p_enet_addr)[i];
1919 enet_addr_cont->location = location;
1920 enqueue(p_lh, &enet_addr_cont->node); /* Put it back */
1921 ++(*p_counter);
1922
18a8e864 1923 hw_add_addr_in_hash(ugeth, enet_addr_cont->address);
ce973b14
LY		 1924 return 0;
1925}
1926
18a8e864
LY		 1927static int ugeth_82xx_filtering_clear_addr_in_hash(struct ucc_geth_private *ugeth,
1928 struct enet_addr *p_enet_addr)
ce973b14 1929{
18a8e864
LY		 1930 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
1931 struct enet_addr_container *enet_addr_cont;
1932 struct ucc_fast_private *uccf;
1933 enum comm_dir comm_dir;
ce973b14
LY		 1934 u16 i, num;
1935 struct list_head *p_lh;
1936 u32 *addr_h, *addr_l;
1937 u8 *p_counter;
1938
1939 uccf = ugeth->uccf;
1940
1941 p_82xx_addr_filt =
18a8e864 1942 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
ce973b14
LY		 1943 addressfiltering;
1944
1945 if (!
1946 (enet_addr_cont =
1947 ugeth_82xx_filtering_get_match_addr_in_hash(ugeth, p_enet_addr)))
1948 return -ENOENT;
1949
1950 /* It's been found and removed from the CQ. */
1951 /* Now destroy its container */
1952 put_enet_addr_container(enet_addr_cont);
1953
1954 if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
1955 addr_h = &(p_82xx_addr_filt->gaddr_h);
1956 addr_l = &(p_82xx_addr_filt->gaddr_l);
1957 p_lh = &ugeth->group_hash_q;
1958 p_counter = &(ugeth->numGroupAddrInHash);
1959 } else {
1960 addr_h = &(p_82xx_addr_filt->iaddr_h);
1961 addr_l = &(p_82xx_addr_filt->iaddr_l);
1962 p_lh = &ugeth->ind_hash_q;
1963 p_counter = &(ugeth->numIndAddrInHash);
1964 }
1965
1966 comm_dir = 0;
1967 if (uccf->enabled_tx)
1968 comm_dir |= COMM_DIR_TX;
1969 if (uccf->enabled_rx)
1970 comm_dir |= COMM_DIR_RX;
1971 if (comm_dir)
1972 ugeth_disable(ugeth, comm_dir);
1973
1974 /* Clear the hash table. */
1975 out_be32(addr_h, 0x00000000);
1976 out_be32(addr_l, 0x00000000);
1977
1978 /* Add all remaining CQ elements back into hash */
1979 num = --(*p_counter);
1980 for (i = 0; i < num; i++) {
1981 enet_addr_cont =
18a8e864 1982 (struct enet_addr_container *)
ce973b14 1983 ENET_ADDR_CONT_ENTRY(dequeue(p_lh));
18a8e864 1984 hw_add_addr_in_hash(ugeth, enet_addr_cont->address);
ce973b14
LY		 1985 enqueue(p_lh, &enet_addr_cont->node); /* Put it back */
1986 }
1987
1988 if (comm_dir)
1989 ugeth_enable(ugeth, comm_dir);
1990
1991 return 0;
1992}
1993#endif /* CONFIG_UGETH_FILTERING */
1994
18a8e864 1995static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
ce973b14 1996 ugeth,
18a8e864 1997 enum enet_addr_type
ce973b14
LY		 1998 enet_addr_type)
1999{
6fee40e9 2000 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
18a8e864
LY		 2001 struct ucc_fast_private *uccf;
2002 enum comm_dir comm_dir;
ce973b14
LY		 2003 struct list_head *p_lh;
2004 u16 i, num;
6fee40e9
AF		 2005 u32 __iomem *addr_h;
2006 u32 __iomem *addr_l;
ce973b14
LY		 2007 u8 *p_counter;
2008
2009 uccf = ugeth->uccf;
2010
2011 p_82xx_addr_filt =
6fee40e9
AF		 2012 (struct ucc_geth_82xx_address_filtering_pram __iomem *)
2013 ugeth->p_rx_glbl_pram->addressfiltering;
ce973b14
LY		 2014
2015 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
2016 addr_h = &(p_82xx_addr_filt->gaddr_h);
2017 addr_l = &(p_82xx_addr_filt->gaddr_l);
2018 p_lh = &ugeth->group_hash_q;
2019 p_counter = &(ugeth->numGroupAddrInHash);
2020 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
2021 addr_h = &(p_82xx_addr_filt->iaddr_h);
2022 addr_l = &(p_82xx_addr_filt->iaddr_l);
2023 p_lh = &ugeth->ind_hash_q;
2024 p_counter = &(ugeth->numIndAddrInHash);
2025 } else
2026 return -EINVAL;
2027
2028 comm_dir = 0;
2029 if (uccf->enabled_tx)
2030 comm_dir |= COMM_DIR_TX;
2031 if (uccf->enabled_rx)
2032 comm_dir |= COMM_DIR_RX;
2033 if (comm_dir)
2034 ugeth_disable(ugeth, comm_dir);
2035
2036 /* Clear the hash table. */
2037 out_be32(addr_h, 0x00000000);
2038 out_be32(addr_l, 0x00000000);
2039
2040 if (!p_lh)
2041 return 0;
2042
2043 num = *p_counter;
2044
2045 /* Delete all remaining CQ elements */
2046 for (i = 0; i < num; i++)
2047 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
2048
2049 *p_counter = 0;
2050
2051 if (comm_dir)
2052 ugeth_enable(ugeth, comm_dir);
2053
2054 return 0;
2055}
2056
2057#ifdef CONFIG_UGETH_FILTERING
18a8e864
LY		 2058static int ugeth_82xx_filtering_add_addr_in_paddr(struct ucc_geth_private *ugeth,
2059 struct enet_addr *p_enet_addr,
ce973b14
LY		 2060 u8 paddr_num)
2061{
2062 int i;
2063
2064 if ((*p_enet_addr)[0] & ENET_GROUP_ADDR)
2065 ugeth_warn
2066 ("%s: multicast address added to paddr will have no "
2067 "effect - is this what you wanted?",
b39d66a8 2068 __func__);
ce973b14
LY		 2069
2070 ugeth->indAddrRegUsed[paddr_num] = 1; /* mark this paddr as used */
2071 /* store address in our database */
2072 for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++)
2073 ugeth->paddr[paddr_num][i] = (*p_enet_addr)[i];
2074 /* put in hardware */
2075 return hw_add_addr_in_paddr(ugeth, p_enet_addr, paddr_num);
2076}
2077#endif /* CONFIG_UGETH_FILTERING */
2078
18a8e864 2079static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
ce973b14
LY		 2080 u8 paddr_num)
2081{
2082 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
2083 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
2084}
2085
18a8e864 2086static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
ce973b14
LY		 2087{
2088 u16 i, j;
6fee40e9 2089 u8 __iomem *bd;
ce973b14
LY		 2090
2091 if (!ugeth)
2092 return;
2093
80a9fad8 2094 if (ugeth->uccf) {
ce973b14 2095 ucc_fast_free(ugeth->uccf);
80a9fad8
AV		 2096 ugeth->uccf = NULL;
2097 }
ce973b14
LY		 2098
2099 if (ugeth->p_thread_data_tx) {
2100 qe_muram_free(ugeth->thread_dat_tx_offset);
2101 ugeth->p_thread_data_tx = NULL;
2102 }
2103 if (ugeth->p_thread_data_rx) {
2104 qe_muram_free(ugeth->thread_dat_rx_offset);
2105 ugeth->p_thread_data_rx = NULL;
2106 }
2107 if (ugeth->p_exf_glbl_param) {
2108 qe_muram_free(ugeth->exf_glbl_param_offset);
2109 ugeth->p_exf_glbl_param = NULL;
2110 }
2111 if (ugeth->p_rx_glbl_pram) {
2112 qe_muram_free(ugeth->rx_glbl_pram_offset);
2113 ugeth->p_rx_glbl_pram = NULL;
2114 }
2115 if (ugeth->p_tx_glbl_pram) {
2116 qe_muram_free(ugeth->tx_glbl_pram_offset);
2117 ugeth->p_tx_glbl_pram = NULL;
2118 }
2119 if (ugeth->p_send_q_mem_reg) {
2120 qe_muram_free(ugeth->send_q_mem_reg_offset);
2121 ugeth->p_send_q_mem_reg = NULL;
2122 }
2123 if (ugeth->p_scheduler) {
2124 qe_muram_free(ugeth->scheduler_offset);
2125 ugeth->p_scheduler = NULL;
2126 }
2127 if (ugeth->p_tx_fw_statistics_pram) {
2128 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
2129 ugeth->p_tx_fw_statistics_pram = NULL;
2130 }
2131 if (ugeth->p_rx_fw_statistics_pram) {
2132 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
2133 ugeth->p_rx_fw_statistics_pram = NULL;
2134 }
2135 if (ugeth->p_rx_irq_coalescing_tbl) {
2136 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
2137 ugeth->p_rx_irq_coalescing_tbl = NULL;
2138 }
2139 if (ugeth->p_rx_bd_qs_tbl) {
2140 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
2141 ugeth->p_rx_bd_qs_tbl = NULL;
2142 }
2143 if (ugeth->p_init_enet_param_shadow) {
2144 return_init_enet_entries(ugeth,
2145 &(ugeth->p_init_enet_param_shadow->
2146 rxthread[0]),
2147 ENET_INIT_PARAM_MAX_ENTRIES_RX,
2148 ugeth->ug_info->riscRx, 1);
2149 return_init_enet_entries(ugeth,
2150 &(ugeth->p_init_enet_param_shadow->
2151 txthread[0]),
2152 ENET_INIT_PARAM_MAX_ENTRIES_TX,
2153 ugeth->ug_info->riscTx, 0);
2154 kfree(ugeth->p_init_enet_param_shadow);
2155 ugeth->p_init_enet_param_shadow = NULL;
2156 }
2157 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
2158 bd = ugeth->p_tx_bd_ring[i];
3a8205ea
NIP		 2159 if (!bd)
2160 continue;
ce973b14
LY		 2161 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
2162 if (ugeth->tx_skbuff[i][j]) {
7f80202b 2163 dma_unmap_single(&ugeth->dev->dev,
6fee40e9
AF		 2164 in_be32(&((struct qe_bd __iomem *)bd)->buf),
2165 (in_be32((u32 __iomem *)bd) &
ce973b14
LY		 2166 BD_LENGTH_MASK),
2167 DMA_TO_DEVICE);
2168 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
2169 ugeth->tx_skbuff[i][j] = NULL;
2170 }
2171 }
2172
2173 kfree(ugeth->tx_skbuff[i]);
2174
2175 if (ugeth->p_tx_bd_ring[i]) {
2176 if (ugeth->ug_info->uf_info.bd_mem_part ==
2177 MEM_PART_SYSTEM)
2178 kfree((void *)ugeth->tx_bd_ring_offset[i]);
2179 else if (ugeth->ug_info->uf_info.bd_mem_part ==
2180 MEM_PART_MURAM)
2181 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
2182 ugeth->p_tx_bd_ring[i] = NULL;
2183 }
2184 }
2185 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
2186 if (ugeth->p_rx_bd_ring[i]) {
2187 /* Return existing data buffers in ring */
2188 bd = ugeth->p_rx_bd_ring[i];
2189 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
2190 if (ugeth->rx_skbuff[i][j]) {
7f80202b 2191 dma_unmap_single(&ugeth->dev->dev,
6fee40e9 2192 in_be32(&((struct qe_bd __iomem *)bd)->buf),
18a8e864
LY		 2193 ugeth->ug_info->
2194 uf_info.max_rx_buf_length +
2195 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
2196 DMA_FROM_DEVICE);
2197 dev_kfree_skb_any(
2198 ugeth->rx_skbuff[i][j]);
ce973b14
LY		 2199 ugeth->rx_skbuff[i][j] = NULL;
2200 }
18a8e864 2201 bd += sizeof(struct qe_bd);
ce973b14
LY		 2202 }
2203
2204 kfree(ugeth->rx_skbuff[i]);
2205
2206 if (ugeth->ug_info->uf_info.bd_mem_part ==
2207 MEM_PART_SYSTEM)
2208 kfree((void *)ugeth->rx_bd_ring_offset[i]);
2209 else if (ugeth->ug_info->uf_info.bd_mem_part ==
2210 MEM_PART_MURAM)
2211 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
2212 ugeth->p_rx_bd_ring[i] = NULL;
2213 }
2214 }
2215 while (!list_empty(&ugeth->group_hash_q))
2216 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2217 (dequeue(&ugeth->group_hash_q)));
2218 while (!list_empty(&ugeth->ind_hash_q))
2219 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2220 (dequeue(&ugeth->ind_hash_q)));
2221
2222}
2223
2224static void ucc_geth_set_multi(struct net_device *dev)
2225{
18a8e864 2226 struct ucc_geth_private *ugeth;
ce973b14 2227 struct dev_mc_list *dmi;
6fee40e9
AF		 2228 struct ucc_fast __iomem *uf_regs;
2229 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
9030b3dd 2230 int i;
ce973b14
LY		 2231
2232 ugeth = netdev_priv(dev);
2233
2234 uf_regs = ugeth->uccf->uf_regs;
2235
2236 if (dev->flags & IFF_PROMISC) {
2237
6fee40e9 2238 out_be32(&uf_regs->upsmr, in_be32(&uf_regs->upsmr) | UPSMR_PRO);
ce973b14
LY		 2239
2240 } else {
2241
6fee40e9 2242 out_be32(&uf_regs->upsmr, in_be32(&uf_regs->upsmr)&~UPSMR_PRO);
ce973b14
LY		 2243
2244 p_82xx_addr_filt =
6fee40e9 2245 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
ce973b14
LY		 2246 p_rx_glbl_pram->addressfiltering;
2247
2248 if (dev->flags & IFF_ALLMULTI) {
2249 /* Catch all multicast addresses, so set the
2250 * filter to all 1's.
2251 */
2252 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2253 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2254 } else {
2255 /* Clear filter and add the addresses in the list.
2256 */
2257 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2258 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2259
2260 dmi = dev->mc_list;
2261
2262 for (i = 0; i < dev->mc_count; i++, dmi = dmi->next) {
2263
2264 /* Only support group multicast for now.
2265 */
2266 if (!(dmi->dmi_addr[0] & 1))
2267 continue;
2268
ce973b14
LY		 2269 /* Ask CPM to run CRC and set bit in
2270 * filter mask.
2271 */
9030b3dd 2272 hw_add_addr_in_hash(ugeth, dmi->dmi_addr);
ce973b14
LY		 2273 }
2274 }
2275 }
2276}
2277
18a8e864 2278static void ucc_geth_stop(struct ucc_geth_private *ugeth)
ce973b14 2279{
6fee40e9 2280 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
728de4c9 2281 struct phy_device *phydev = ugeth->phydev;
ce973b14
LY		 2282 u32 tempval;
2283
b39d66a8 2284 ugeth_vdbg("%s: IN", __func__);
ce973b14
LY		 2285
2286 /* Disable the controller */
2287 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2288
2289 /* Tell the kernel the link is down */
728de4c9 2290 phy_stop(phydev);
ce973b14
LY		 2291
2292 /* Mask all interrupts */
c6f5047b 2293 out_be32(ugeth->uccf->p_uccm, 0x00000000);
ce973b14
LY		 2294
2295 /* Clear all interrupts */
2296 out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2297
2298 /* Disable Rx and Tx */
2299 tempval = in_be32(&ug_regs->maccfg1);
2300 tempval &= ~(MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2301 out_be32(&ug_regs->maccfg1, tempval);
2302
ce973b14
LY		 2303 free_irq(ugeth->ug_info->uf_info.irq, ugeth->dev);
2304
ce973b14
LY		 2305 ucc_geth_memclean(ugeth);
2306}
2307
728de4c9 2308static int ucc_struct_init(struct ucc_geth_private *ugeth)
ce973b14 2309{
18a8e864
LY		 2310 struct ucc_geth_info *ug_info;
2311 struct ucc_fast_info *uf_info;
728de4c9 2312 int i;
ce973b14
LY		 2313
2314 ug_info = ugeth->ug_info;
2315 uf_info = &ug_info->uf_info;
2316
2317 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2318 (uf_info->bd_mem_part == MEM_PART_MURAM))) {
890de95e
LY		 2319 if (netif_msg_probe(ugeth))
2320 ugeth_err("%s: Bad memory partition value.",
b39d66a8 2321 __func__);
ce973b14
LY		 2322 return -EINVAL;
2323 }
2324
2325 /* Rx BD lengths */
2326 for (i = 0; i < ug_info->numQueuesRx; i++) {
2327 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2328 (ug_info->bdRingLenRx[i] %
2329 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
890de95e
LY		 2330 if (netif_msg_probe(ugeth))
2331 ugeth_err
2332 ("%s: Rx BD ring length must be multiple of 4, no smaller than 8.",
b39d66a8 2333 __func__);
ce973b14
LY		 2334 return -EINVAL;
2335 }
2336 }
2337
2338 /* Tx BD lengths */
2339 for (i = 0; i < ug_info->numQueuesTx; i++) {
2340 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
890de95e
LY		 2341 if (netif_msg_probe(ugeth))
2342 ugeth_err
2343 ("%s: Tx BD ring length must be no smaller than 2.",
b39d66a8 2344 __func__);
ce973b14
LY		 2345 return -EINVAL;
2346 }
2347 }
2348
2349 /* mrblr */
2350 if ((uf_info->max_rx_buf_length == 0) ||
2351 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
890de95e
LY		 2352 if (netif_msg_probe(ugeth))
2353 ugeth_err
2354 ("%s: max_rx_buf_length must be non-zero multiple of 128.",
b39d66a8 2355 __func__);
ce973b14
LY		 2356 return -EINVAL;
2357 }
2358
2359 /* num Tx queues */
2360 if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
890de95e 2361 if (netif_msg_probe(ugeth))
b39d66a8 2362 ugeth_err("%s: number of tx queues too large.", __func__);
ce973b14
LY		 2363 return -EINVAL;
2364 }
2365
2366 /* num Rx queues */
2367 if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
890de95e 2368 if (netif_msg_probe(ugeth))
b39d66a8 2369 ugeth_err("%s: number of rx queues too large.", __func__);
ce973b14
LY		 2370 return -EINVAL;
2371 }
2372
2373 /* l2qt */
2374 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2375 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
890de95e
LY		 2376 if (netif_msg_probe(ugeth))
2377 ugeth_err
2378 ("%s: VLAN priority table entry must not be"
2379 " larger than number of Rx queues.",
b39d66a8 2380 __func__);
ce973b14
LY		 2381 return -EINVAL;
2382 }
2383 }
2384
2385 /* l3qt */
2386 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2387 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
890de95e
LY		 2388 if (netif_msg_probe(ugeth))
2389 ugeth_err
2390 ("%s: IP priority table entry must not be"
2391 " larger than number of Rx queues.",
b39d66a8 2392 __func__);
ce973b14
LY		 2393 return -EINVAL;
2394 }
2395 }
2396
2397 if (ug_info->cam && !ug_info->ecamptr) {
890de95e
LY		 2398 if (netif_msg_probe(ugeth))
2399 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
b39d66a8 2400 __func__);
ce973b14
LY		 2401 return -EINVAL;
2402 }
2403
2404 if ((ug_info->numStationAddresses !=
2405 UCC_GETH_NUM_OF_STATION_ADDRESSES_1)
2406 && ug_info->rxExtendedFiltering) {
890de95e
LY		 2407 if (netif_msg_probe(ugeth))
2408 ugeth_err("%s: Number of station addresses greater than 1 "
2409 "not allowed in extended parsing mode.",
b39d66a8 2410 __func__);
ce973b14
LY		 2411 return -EINVAL;
2412 }
2413
2414 /* Generate uccm_mask for receive */
2415 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2416 for (i = 0; i < ug_info->numQueuesRx; i++)
2417 uf_info->uccm_mask |= (UCCE_RXBF_SINGLE_MASK << i);
2418
2419 for (i = 0; i < ug_info->numQueuesTx; i++)
2420 uf_info->uccm_mask |= (UCCE_TXBF_SINGLE_MASK << i);
2421 /* Initialize the general fast UCC block. */
728de4c9 2422 if (ucc_fast_init(uf_info, &ugeth->uccf)) {
890de95e 2423 if (netif_msg_probe(ugeth))
b39d66a8 2424 ugeth_err("%s: Failed to init uccf.", __func__);
ce973b14
LY		 2425 ucc_geth_memclean(ugeth);
2426 return -ENOMEM;
2427 }
728de4c9 2428
6fee40e9 2429 ugeth->ug_regs = (struct ucc_geth __iomem *) ioremap(uf_info->regs, sizeof(struct ucc_geth));
728de4c9
KP		 2430
2431 return 0;
2432}
2433
2434static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2435{
6fee40e9
AF		 2436 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2437 struct ucc_geth_init_pram __iomem *p_init_enet_pram;
728de4c9
KP		 2438 struct ucc_fast_private *uccf;
2439 struct ucc_geth_info *ug_info;
2440 struct ucc_fast_info *uf_info;
6fee40e9
AF		 2441 struct ucc_fast __iomem *uf_regs;
2442 struct ucc_geth __iomem *ug_regs;
728de4c9
KP		 2443 int ret_val = -EINVAL;
2444 u32 remoder = UCC_GETH_REMODER_INIT;
2445 u32 init_enet_pram_offset, cecr_subblock, command, maccfg1;
2446 u32 ifstat, i, j, size, l2qt, l3qt, length;
2447 u16 temoder = UCC_GETH_TEMODER_INIT;
2448 u16 test;
2449 u8 function_code = 0;
6fee40e9
AF		 2450 u8 __iomem *bd;
2451 u8 __iomem *endOfRing;
728de4c9
KP		 2452 u8 numThreadsRxNumerical, numThreadsTxNumerical;
2453
b39d66a8 2454 ugeth_vdbg("%s: IN", __func__);
728de4c9
KP		 2455 uccf = ugeth->uccf;
2456 ug_info = ugeth->ug_info;
2457 uf_info = &ug_info->uf_info;
2458 uf_regs = uccf->uf_regs;
2459 ug_regs = ugeth->ug_regs;
ce973b14
LY		 2460
2461 switch (ug_info->numThreadsRx) {
2462 case UCC_GETH_NUM_OF_THREADS_1:
2463 numThreadsRxNumerical = 1;
2464 break;
2465 case UCC_GETH_NUM_OF_THREADS_2:
2466 numThreadsRxNumerical = 2;
2467 break;
2468 case UCC_GETH_NUM_OF_THREADS_4:
2469 numThreadsRxNumerical = 4;
2470 break;
2471 case UCC_GETH_NUM_OF_THREADS_6:
2472 numThreadsRxNumerical = 6;
2473 break;
2474 case UCC_GETH_NUM_OF_THREADS_8:
2475 numThreadsRxNumerical = 8;
2476 break;
2477 default:
890de95e
LY		 2478 if (netif_msg_ifup(ugeth))
2479 ugeth_err("%s: Bad number of Rx threads value.",
b39d66a8 2480 __func__);
ce973b14
LY		 2481 ucc_geth_memclean(ugeth);
2482 return -EINVAL;
2483 break;
2484 }
2485
2486 switch (ug_info->numThreadsTx) {
2487 case UCC_GETH_NUM_OF_THREADS_1:
2488 numThreadsTxNumerical = 1;
2489 break;
2490 case UCC_GETH_NUM_OF_THREADS_2:
2491 numThreadsTxNumerical = 2;
2492 break;
2493 case UCC_GETH_NUM_OF_THREADS_4:
2494 numThreadsTxNumerical = 4;
2495 break;
2496 case UCC_GETH_NUM_OF_THREADS_6:
2497 numThreadsTxNumerical = 6;
2498 break;
2499 case UCC_GETH_NUM_OF_THREADS_8:
2500 numThreadsTxNumerical = 8;
2501 break;
2502 default:
890de95e
LY		 2503 if (netif_msg_ifup(ugeth))
2504 ugeth_err("%s: Bad number of Tx threads value.",
b39d66a8 2505 __func__);
ce973b14
LY		 2506 ucc_geth_memclean(ugeth);
2507 return -EINVAL;
2508 break;
2509 }
2510
2511 /* Calculate rx_extended_features */
2512 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2513 ug_info->ipAddressAlignment ||
2514 (ug_info->numStationAddresses !=
2515 UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2516
2517 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2518 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
2519 || (ug_info->vlanOperationNonTagged !=
2520 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2521
ce973b14
LY		 2522 init_default_reg_vals(&uf_regs->upsmr,
2523 &ug_regs->maccfg1, &ug_regs->maccfg2);
2524
2525 /* Set UPSMR */
2526 /* For more details see the hardware spec. */
2527 init_rx_parameters(ug_info->bro,
2528 ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2529
2530 /* We're going to ignore other registers for now, */
2531 /* except as needed to get up and running */
2532
2533 /* Set MACCFG1 */
2534 /* For more details see the hardware spec. */
2535 init_flow_control_params(ug_info->aufc,
2536 ug_info->receiveFlowControl,
ac421852 2537 ug_info->transmitFlowControl,
ce973b14
LY		 2538 ug_info->pausePeriod,
2539 ug_info->extensionField,
2540 &uf_regs->upsmr,
2541 &ug_regs->uempr, &ug_regs->maccfg1);
2542
2543 maccfg1 = in_be32(&ug_regs->maccfg1);
2544 maccfg1 |= MACCFG1_ENABLE_RX;
2545 maccfg1 |= MACCFG1_ENABLE_TX;
2546 out_be32(&ug_regs->maccfg1, maccfg1);
2547
2548 /* Set IPGIFG */
2549 /* For more details see the hardware spec. */
2550 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2551 ug_info->nonBackToBackIfgPart2,
2552 ug_info->
2553 miminumInterFrameGapEnforcement,
2554 ug_info->backToBackInterFrameGap,
2555 &ug_regs->ipgifg);
2556 if (ret_val != 0) {
890de95e
LY		 2557 if (netif_msg_ifup(ugeth))
2558 ugeth_err("%s: IPGIFG initialization parameter too large.",
b39d66a8 2559 __func__);
ce973b14
LY		 2560 ucc_geth_memclean(ugeth);
2561 return ret_val;
2562 }
2563
2564 /* Set HAFDUP */
2565 /* For more details see the hardware spec. */
2566 ret_val = init_half_duplex_params(ug_info->altBeb,
2567 ug_info->backPressureNoBackoff,
2568 ug_info->noBackoff,
2569 ug_info->excessDefer,
2570 ug_info->altBebTruncation,
2571 ug_info->maxRetransmission,
2572 ug_info->collisionWindow,
2573 &ug_regs->hafdup);
2574 if (ret_val != 0) {
890de95e
LY		 2575 if (netif_msg_ifup(ugeth))
2576 ugeth_err("%s: Half Duplex initialization parameter too large.",
b39d66a8 2577 __func__);
ce973b14
LY		 2578 ucc_geth_memclean(ugeth);
2579 return ret_val;
2580 }
2581
2582 /* Set IFSTAT */
2583 /* For more details see the hardware spec. */
2584 /* Read only - resets upon read */
2585 ifstat = in_be32(&ug_regs->ifstat);
2586
2587 /* Clear UEMPR */
2588 /* For more details see the hardware spec. */
2589 out_be32(&ug_regs->uempr, 0);
2590
2591 /* Set UESCR */
2592 /* For more details see the hardware spec. */
2593 init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2594 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2595 0, &uf_regs->upsmr, &ug_regs->uescr);
2596
2597 /* Allocate Tx bds */
2598 for (j = 0; j < ug_info->numQueuesTx; j++) {
2599 /* Allocate in multiple of
2600 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2601 according to spec */
18a8e864 2602 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
ce973b14
LY		 2603 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2604 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
18a8e864 2605 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
ce973b14
LY		 2606 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2607 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2608 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2609 u32 align = 4;
2610 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2611 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2612 ugeth->tx_bd_ring_offset[j] =
6fee40e9 2613 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
04b588d7 2614
ce973b14
LY		 2615 if (ugeth->tx_bd_ring_offset[j] != 0)
2616 ugeth->p_tx_bd_ring[j] =
6fee40e9 2617 (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
ce973b14
LY		 2618 align) & ~(align - 1));
2619 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2620 ugeth->tx_bd_ring_offset[j] =
2621 qe_muram_alloc(length,
2622 UCC_GETH_TX_BD_RING_ALIGNMENT);
4c35630c 2623 if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
ce973b14 2624 ugeth->p_tx_bd_ring[j] =
6fee40e9 2625 (u8 __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2626 tx_bd_ring_offset[j]);
2627 }
2628 if (!ugeth->p_tx_bd_ring[j]) {
890de95e
LY		 2629 if (netif_msg_ifup(ugeth))
2630 ugeth_err
2631 ("%s: Can not allocate memory for Tx bd rings.",
b39d66a8 2632 __func__);
ce973b14
LY		 2633 ucc_geth_memclean(ugeth);
2634 return -ENOMEM;
2635 }
2636 /* Zero unused end of bd ring, according to spec */
6fee40e9
AF		 2637 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2638 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
18a8e864 2639 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
ce973b14
LY		 2640 }
2641
2642 /* Allocate Rx bds */
2643 for (j = 0; j < ug_info->numQueuesRx; j++) {
18a8e864 2644 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
ce973b14
LY		 2645 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2646 u32 align = 4;
2647 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2648 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2649 ugeth->rx_bd_ring_offset[j] =
6fee40e9 2650 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
ce973b14
LY		 2651 if (ugeth->rx_bd_ring_offset[j] != 0)
2652 ugeth->p_rx_bd_ring[j] =
6fee40e9 2653 (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
ce973b14
LY		 2654 align) & ~(align - 1));
2655 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2656 ugeth->rx_bd_ring_offset[j] =
2657 qe_muram_alloc(length,
2658 UCC_GETH_RX_BD_RING_ALIGNMENT);
4c35630c 2659 if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
ce973b14 2660 ugeth->p_rx_bd_ring[j] =
6fee40e9 2661 (u8 __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2662 rx_bd_ring_offset[j]);
2663 }
2664 if (!ugeth->p_rx_bd_ring[j]) {
890de95e
LY		 2665 if (netif_msg_ifup(ugeth))
2666 ugeth_err
2667 ("%s: Can not allocate memory for Rx bd rings.",
b39d66a8 2668 __func__);
ce973b14
LY		 2669 ucc_geth_memclean(ugeth);
2670 return -ENOMEM;
2671 }
2672 }
2673
2674 /* Init Tx bds */
2675 for (j = 0; j < ug_info->numQueuesTx; j++) {
2676 /* Setup the skbuff rings */
04b588d7
AD		 2677 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2678 ugeth->ug_info->bdRingLenTx[j],
2679 GFP_KERNEL);
ce973b14
LY		 2680
2681 if (ugeth->tx_skbuff[j] == NULL) {
890de95e
LY		 2682 if (netif_msg_ifup(ugeth))
2683 ugeth_err("%s: Could not allocate tx_skbuff",
b39d66a8 2684 __func__);
ce973b14
LY		 2685 ucc_geth_memclean(ugeth);
2686 return -ENOMEM;
2687 }
2688
2689 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2690 ugeth->tx_skbuff[j][i] = NULL;
2691
2692 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2693 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2694 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
18a8e864 2695 /* clear bd buffer */
6fee40e9 2696 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
18a8e864 2697 /* set bd status and length */
6fee40e9 2698 out_be32((u32 __iomem *)bd, 0);
18a8e864 2699 bd += sizeof(struct qe_bd);
ce973b14 2700 }
18a8e864
LY		 2701 bd -= sizeof(struct qe_bd);
2702 /* set bd status and length */
6fee40e9 2703 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */
ce973b14
LY		 2704 }
2705
2706 /* Init Rx bds */
2707 for (j = 0; j < ug_info->numQueuesRx; j++) {
2708 /* Setup the skbuff rings */
04b588d7
AD		 2709 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2710 ugeth->ug_info->bdRingLenRx[j],
2711 GFP_KERNEL);
ce973b14
LY		 2712
2713 if (ugeth->rx_skbuff[j] == NULL) {
890de95e
LY		 2714 if (netif_msg_ifup(ugeth))
2715 ugeth_err("%s: Could not allocate rx_skbuff",
b39d66a8 2716 __func__);
ce973b14
LY		 2717 ucc_geth_memclean(ugeth);
2718 return -ENOMEM;
2719 }
2720
2721 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2722 ugeth->rx_skbuff[j][i] = NULL;
2723
2724 ugeth->skb_currx[j] = 0;
2725 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2726 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
18a8e864 2727 /* set bd status and length */
6fee40e9 2728 out_be32((u32 __iomem *)bd, R_I);
18a8e864 2729 /* clear bd buffer */
6fee40e9 2730 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
18a8e864 2731 bd += sizeof(struct qe_bd);
ce973b14 2732 }
18a8e864
LY		 2733 bd -= sizeof(struct qe_bd);
2734 /* set bd status and length */
6fee40e9 2735 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */
ce973b14
LY		 2736 }
2737
2738 /*
2739 * Global PRAM
2740 */
2741 /* Tx global PRAM */
2742 /* Allocate global tx parameter RAM page */
2743 ugeth->tx_glbl_pram_offset =
18a8e864 2744 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
ce973b14 2745 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
4c35630c 2746 if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
890de95e
LY		 2747 if (netif_msg_ifup(ugeth))
2748 ugeth_err
2749 ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
b39d66a8 2750 __func__);
ce973b14
LY		 2751 ucc_geth_memclean(ugeth);
2752 return -ENOMEM;
2753 }
2754 ugeth->p_tx_glbl_pram =
6fee40e9 2755 (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2756 tx_glbl_pram_offset);
2757 /* Zero out p_tx_glbl_pram */
6fee40e9 2758 memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
ce973b14
LY		 2759
2760 /* Fill global PRAM */
2761
2762 /* TQPTR */
2763 /* Size varies with number of Tx threads */
2764 ugeth->thread_dat_tx_offset =
2765 qe_muram_alloc(numThreadsTxNumerical *
18a8e864 2766 sizeof(struct ucc_geth_thread_data_tx) +
ce973b14
LY		 2767 32 * (numThreadsTxNumerical == 1),
2768 UCC_GETH_THREAD_DATA_ALIGNMENT);
4c35630c 2769 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
890de95e
LY		 2770 if (netif_msg_ifup(ugeth))
2771 ugeth_err
2772 ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
b39d66a8 2773 __func__);
ce973b14
LY		 2774 ucc_geth_memclean(ugeth);
2775 return -ENOMEM;
2776 }
2777
2778 ugeth->p_thread_data_tx =
6fee40e9 2779 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2780 thread_dat_tx_offset);
2781 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2782
2783 /* vtagtable */
2784 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2785 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2786 ug_info->vtagtable[i]);
2787
2788 /* iphoffset */
2789 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
6fee40e9
AF		 2790 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2791 ug_info->iphoffset[i]);
ce973b14
LY		 2792
2793 /* SQPTR */
2794 /* Size varies with number of Tx queues */
2795 ugeth->send_q_mem_reg_offset =
2796 qe_muram_alloc(ug_info->numQueuesTx *
18a8e864 2797 sizeof(struct ucc_geth_send_queue_qd),
ce973b14 2798 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
4c35630c 2799 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
890de95e
LY		 2800 if (netif_msg_ifup(ugeth))
2801 ugeth_err
2802 ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
b39d66a8 2803 __func__);
ce973b14
LY		 2804 ucc_geth_memclean(ugeth);
2805 return -ENOMEM;
2806 }
2807
2808 ugeth->p_send_q_mem_reg =
6fee40e9 2809 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2810 send_q_mem_reg_offset);
2811 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2812
2813 /* Setup the table */
2814 /* Assume BD rings are already established */
2815 for (i = 0; i < ug_info->numQueuesTx; i++) {
2816 endOfRing =
2817 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
18a8e864 2818 1) * sizeof(struct qe_bd);
ce973b14
LY		 2819 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2820 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2821 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2822 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2823 last_bd_completed_address,
2824 (u32) virt_to_phys(endOfRing));
2825 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2826 MEM_PART_MURAM) {
2827 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2828 (u32) immrbar_virt_to_phys(ugeth->
2829 p_tx_bd_ring[i]));
2830 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2831 last_bd_completed_address,
2832 (u32) immrbar_virt_to_phys(endOfRing));
2833 }
2834 }
2835
2836 /* schedulerbasepointer */
2837
2838 if (ug_info->numQueuesTx > 1) {
2839 /* scheduler exists only if more than 1 tx queue */
2840 ugeth->scheduler_offset =
18a8e864 2841 qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
ce973b14 2842 UCC_GETH_SCHEDULER_ALIGNMENT);
4c35630c 2843 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
890de95e
LY		 2844 if (netif_msg_ifup(ugeth))
2845 ugeth_err
2846 ("%s: Can not allocate DPRAM memory for p_scheduler.",
b39d66a8 2847 __func__);
ce973b14
LY		 2848 ucc_geth_memclean(ugeth);
2849 return -ENOMEM;
2850 }
2851
2852 ugeth->p_scheduler =
6fee40e9 2853 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2854 scheduler_offset);
2855 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2856 ugeth->scheduler_offset);
2857 /* Zero out p_scheduler */
6fee40e9 2858 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
ce973b14
LY		 2859
2860 /* Set values in scheduler */
2861 out_be32(&ugeth->p_scheduler->mblinterval,
2862 ug_info->mblinterval);
2863 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2864 ug_info->nortsrbytetime);
6fee40e9
AF		 2865 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2866 out_8(&ugeth->p_scheduler->strictpriorityq,
2867 ug_info->strictpriorityq);
2868 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2869 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
ce973b14 2870 for (i = 0; i < NUM_TX_QUEUES; i++)
6fee40e9
AF		 2871 out_8(&ugeth->p_scheduler->weightfactor[i],
2872 ug_info->weightfactor[i]);
ce973b14
LY		 2873
2874 /* Set pointers to cpucount registers in scheduler */
2875 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2876 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2877 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2878 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2879 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2880 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2881 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2882 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2883 }
2884
2885 /* schedulerbasepointer */
2886 /* TxRMON_PTR (statistics) */
2887 if (ug_info->
2888 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2889 ugeth->tx_fw_statistics_pram_offset =
2890 qe_muram_alloc(sizeof
18a8e864 2891 (struct ucc_geth_tx_firmware_statistics_pram),
ce973b14 2892 UCC_GETH_TX_STATISTICS_ALIGNMENT);
4c35630c 2893 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
890de95e
LY		 2894 if (netif_msg_ifup(ugeth))
2895 ugeth_err
2896 ("%s: Can not allocate DPRAM memory for"
2897 " p_tx_fw_statistics_pram.",
b39d66a8 2898 __func__);
ce973b14
LY		 2899 ucc_geth_memclean(ugeth);
2900 return -ENOMEM;
2901 }
2902 ugeth->p_tx_fw_statistics_pram =
6fee40e9 2903 (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
ce973b14
LY		 2904 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2905 /* Zero out p_tx_fw_statistics_pram */
6fee40e9 2906 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram,
18a8e864 2907 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
ce973b14
LY		 2908 }
2909
2910 /* temoder */
2911 /* Already has speed set */
2912
2913 if (ug_info->numQueuesTx > 1)
2914 temoder |= TEMODER_SCHEDULER_ENABLE;
2915 if (ug_info->ipCheckSumGenerate)
2916 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2917 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2918 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2919
2920 test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2921
2922 /* Function code register value to be used later */
6b0b594b 2923 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
ce973b14
LY		 2924 /* Required for QE */
2925
2926 /* function code register */
2927 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2928
2929 /* Rx global PRAM */
2930 /* Allocate global rx parameter RAM page */
2931 ugeth->rx_glbl_pram_offset =
18a8e864 2932 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
ce973b14 2933 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
4c35630c 2934 if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
890de95e
LY		 2935 if (netif_msg_ifup(ugeth))
2936 ugeth_err
2937 ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
b39d66a8 2938 __func__);
ce973b14
LY		 2939 ucc_geth_memclean(ugeth);
2940 return -ENOMEM;
2941 }
2942 ugeth->p_rx_glbl_pram =
6fee40e9 2943 (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2944 rx_glbl_pram_offset);
2945 /* Zero out p_rx_glbl_pram */
6fee40e9 2946 memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
ce973b14
LY		 2947
2948 /* Fill global PRAM */
2949
2950 /* RQPTR */
2951 /* Size varies with number of Rx threads */
2952 ugeth->thread_dat_rx_offset =
2953 qe_muram_alloc(numThreadsRxNumerical *
18a8e864 2954 sizeof(struct ucc_geth_thread_data_rx),
ce973b14 2955 UCC_GETH_THREAD_DATA_ALIGNMENT);
4c35630c 2956 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
890de95e
LY		 2957 if (netif_msg_ifup(ugeth))
2958 ugeth_err
2959 ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
b39d66a8 2960 __func__);
ce973b14
LY		 2961 ucc_geth_memclean(ugeth);
2962 return -ENOMEM;
2963 }
2964
2965 ugeth->p_thread_data_rx =
6fee40e9 2966 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2967 thread_dat_rx_offset);
2968 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2969
2970 /* typeorlen */
2971 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2972
2973 /* rxrmonbaseptr (statistics) */
2974 if (ug_info->
2975 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2976 ugeth->rx_fw_statistics_pram_offset =
2977 qe_muram_alloc(sizeof
18a8e864 2978 (struct ucc_geth_rx_firmware_statistics_pram),
ce973b14 2979 UCC_GETH_RX_STATISTICS_ALIGNMENT);
4c35630c 2980 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
890de95e
LY		 2981 if (netif_msg_ifup(ugeth))
2982 ugeth_err
2983 ("%s: Can not allocate DPRAM memory for"
b39d66a8 2984 " p_rx_fw_statistics_pram.", __func__);
ce973b14
LY		 2985 ucc_geth_memclean(ugeth);
2986 return -ENOMEM;
2987 }
2988 ugeth->p_rx_fw_statistics_pram =
6fee40e9 2989 (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
ce973b14
LY		 2990 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2991 /* Zero out p_rx_fw_statistics_pram */
6fee40e9 2992 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0,
18a8e864 2993 sizeof(struct ucc_geth_rx_firmware_statistics_pram));
ce973b14
LY		 2994 }
2995
2996 /* intCoalescingPtr */
2997
2998 /* Size varies with number of Rx queues */
2999 ugeth->rx_irq_coalescing_tbl_offset =
3000 qe_muram_alloc(ug_info->numQueuesRx *
7563907e
MB		 3001 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
3002 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
4c35630c 3003 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
890de95e
LY		 3004 if (netif_msg_ifup(ugeth))
3005 ugeth_err
3006 ("%s: Can not allocate DPRAM memory for"
b39d66a8 3007 " p_rx_irq_coalescing_tbl.", __func__);
ce973b14
LY		 3008 ucc_geth_memclean(ugeth);
3009 return -ENOMEM;
3010 }
3011
3012 ugeth->p_rx_irq_coalescing_tbl =
6fee40e9 3013 (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
ce973b14
LY		 3014 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
3015 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
3016 ugeth->rx_irq_coalescing_tbl_offset);
3017
3018 /* Fill interrupt coalescing table */
3019 for (i = 0; i < ug_info->numQueuesRx; i++) {
3020 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
3021 interruptcoalescingmaxvalue,
3022 ug_info->interruptcoalescingmaxvalue[i]);
3023 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
3024 interruptcoalescingcounter,
3025 ug_info->interruptcoalescingmaxvalue[i]);
3026 }
3027
3028 /* MRBLR */
3029 init_max_rx_buff_len(uf_info->max_rx_buf_length,
3030 &ugeth->p_rx_glbl_pram->mrblr);
3031 /* MFLR */
3032 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
3033 /* MINFLR */
3034 init_min_frame_len(ug_info->minFrameLength,
3035 &ugeth->p_rx_glbl_pram->minflr,
3036 &ugeth->p_rx_glbl_pram->mrblr);
3037 /* MAXD1 */
3038 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
3039 /* MAXD2 */
3040 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
3041
3042 /* l2qt */
3043 l2qt = 0;
3044 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
3045 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
3046 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
3047
3048 /* l3qt */
3049 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
3050 l3qt = 0;
3051 for (i = 0; i < 8; i++)
3052 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
18a8e864 3053 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
ce973b14
LY		 3054 }
3055
3056 /* vlantype */
3057 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
3058
3059 /* vlantci */
3060 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
3061
3062 /* ecamptr */
3063 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
3064
3065 /* RBDQPTR */
3066 /* Size varies with number of Rx queues */
3067 ugeth->rx_bd_qs_tbl_offset =
3068 qe_muram_alloc(ug_info->numQueuesRx *
18a8e864
LY		 3069 (sizeof(struct ucc_geth_rx_bd_queues_entry) +
3070 sizeof(struct ucc_geth_rx_prefetched_bds)),
ce973b14 3071 UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
4c35630c 3072 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
890de95e
LY		 3073 if (netif_msg_ifup(ugeth))
3074 ugeth_err
3075 ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
b39d66a8 3076 __func__);
ce973b14
LY		 3077 ucc_geth_memclean(ugeth);
3078 return -ENOMEM;
3079 }
3080
3081 ugeth->p_rx_bd_qs_tbl =
6fee40e9 3082 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 3083 rx_bd_qs_tbl_offset);
3084 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
3085 /* Zero out p_rx_bd_qs_tbl */
6fee40e9 3086 memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl,
ce973b14 3087 0,
18a8e864
LY		 3088 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
3089 sizeof(struct ucc_geth_rx_prefetched_bds)));
ce973b14
LY		 3090
3091 /* Setup the table */
3092 /* Assume BD rings are already established */
3093 for (i = 0; i < ug_info->numQueuesRx; i++) {
3094 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
3095 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
3096 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
3097 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
3098 MEM_PART_MURAM) {
3099 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
3100 (u32) immrbar_virt_to_phys(ugeth->
3101 p_rx_bd_ring[i]));
3102 }
3103 /* rest of fields handled by QE */
3104 }
3105
3106 /* remoder */
3107 /* Already has speed set */
3108
3109 if (ugeth->rx_extended_features)
3110 remoder |= REMODER_RX_EXTENDED_FEATURES;
3111 if (ug_info->rxExtendedFiltering)
3112 remoder |= REMODER_RX_EXTENDED_FILTERING;
3113 if (ug_info->dynamicMaxFrameLength)
3114 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
3115 if (ug_info->dynamicMinFrameLength)
3116 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
3117 remoder |=
3118 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
3119 remoder |=
3120 ug_info->
3121 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
3122 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
3123 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
3124 if (ug_info->ipCheckSumCheck)
3125 remoder |= REMODER_IP_CHECKSUM_CHECK;
3126 if (ug_info->ipAddressAlignment)
3127 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
3128 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
3129
3130 /* Note that this function must be called */
3131 /* ONLY AFTER p_tx_fw_statistics_pram */
3132 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
3133 init_firmware_statistics_gathering_mode((ug_info->
3134 statisticsMode &
3135 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
3136 (ug_info->statisticsMode &
3137 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
3138 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
3139 ugeth->tx_fw_statistics_pram_offset,
3140 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
3141 ugeth->rx_fw_statistics_pram_offset,
3142 &ugeth->p_tx_glbl_pram->temoder,
3143 &ugeth->p_rx_glbl_pram->remoder);
3144
3145 /* function code register */
6fee40e9 3146 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
ce973b14
LY		 3147
3148 /* initialize extended filtering */
3149 if (ug_info->rxExtendedFiltering) {
3150 if (!ug_info->extendedFilteringChainPointer) {
890de95e
LY		 3151 if (netif_msg_ifup(ugeth))
3152 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
b39d66a8 3153 __func__);
ce973b14
LY		 3154 ucc_geth_memclean(ugeth);
3155 return -EINVAL;
3156 }
3157
3158 /* Allocate memory for extended filtering Mode Global
3159 Parameters */
3160 ugeth->exf_glbl_param_offset =
18a8e864 3161 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
ce973b14 3162 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
4c35630c 3163 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
890de95e
LY		 3164 if (netif_msg_ifup(ugeth))
3165 ugeth_err
3166 ("%s: Can not allocate DPRAM memory for"
b39d66a8 3167 " p_exf_glbl_param.", __func__);
ce973b14
LY		 3168 ucc_geth_memclean(ugeth);
3169 return -ENOMEM;
3170 }
3171
3172 ugeth->p_exf_glbl_param =
6fee40e9 3173 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 3174 exf_glbl_param_offset);
3175 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
3176 ugeth->exf_glbl_param_offset);
3177 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
3178 (u32) ug_info->extendedFilteringChainPointer);
3179
3180 } else { /* initialize 82xx style address filtering */
3181
3182 /* Init individual address recognition registers to disabled */
3183
3184 for (j = 0; j < NUM_OF_PADDRS; j++)
3185 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
3186
ce973b14 3187 p_82xx_addr_filt =
6fee40e9 3188 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
ce973b14
LY		 3189 p_rx_glbl_pram->addressfiltering;
3190
3191 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
3192 ENET_ADDR_TYPE_GROUP);
3193 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
3194 ENET_ADDR_TYPE_INDIVIDUAL);
3195 }
3196
3197 /*
3198 * Initialize UCC at QE level
3199 */
3200
3201 command = QE_INIT_TX_RX;
3202
3203 /* Allocate shadow InitEnet command parameter structure.
3204 * This is needed because after the InitEnet command is executed,
3205 * the structure in DPRAM is released, because DPRAM is a premium
3206 * resource.
3207 * This shadow structure keeps a copy of what was done so that the
3208 * allocated resources can be released when the channel is freed.
3209 */
3210 if (!(ugeth->p_init_enet_param_shadow =
04b588d7 3211 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
890de95e
LY		 3212 if (netif_msg_ifup(ugeth))
3213 ugeth_err
3214 ("%s: Can not allocate memory for"
b39d66a8 3215 " p_UccInitEnetParamShadows.", __func__);
ce973b14
LY		 3216 ucc_geth_memclean(ugeth);
3217 return -ENOMEM;
3218 }
3219 /* Zero out *p_init_enet_param_shadow */
3220 memset((char *)ugeth->p_init_enet_param_shadow,
18a8e864 3221 0, sizeof(struct ucc_geth_init_pram));
ce973b14
LY		 3222
3223 /* Fill shadow InitEnet command parameter structure */
3224
3225 ugeth->p_init_enet_param_shadow->resinit1 =
3226 ENET_INIT_PARAM_MAGIC_RES_INIT1;
3227 ugeth->p_init_enet_param_shadow->resinit2 =
3228 ENET_INIT_PARAM_MAGIC_RES_INIT2;
3229 ugeth->p_init_enet_param_shadow->resinit3 =
3230 ENET_INIT_PARAM_MAGIC_RES_INIT3;
3231 ugeth->p_init_enet_param_shadow->resinit4 =
3232 ENET_INIT_PARAM_MAGIC_RES_INIT4;
3233 ugeth->p_init_enet_param_shadow->resinit5 =
3234 ENET_INIT_PARAM_MAGIC_RES_INIT5;
3235 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3236 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
3237 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3238 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
3239
3240 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3241 ugeth->rx_glbl_pram_offset | ug_info->riscRx;
3242 if ((ug_info->largestexternallookupkeysize !=
3243 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE)
3244 && (ug_info->largestexternallookupkeysize !=
3245 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3246 && (ug_info->largestexternallookupkeysize !=
3247 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
890de95e
LY		 3248 if (netif_msg_ifup(ugeth))
3249 ugeth_err("%s: Invalid largest External Lookup Key Size.",
b39d66a8 3250 __func__);
ce973b14
LY		 3251 ucc_geth_memclean(ugeth);
3252 return -EINVAL;
3253 }
3254 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
3255 ug_info->largestexternallookupkeysize;
18a8e864 3256 size = sizeof(struct ucc_geth_thread_rx_pram);
ce973b14
LY		 3257 if (ug_info->rxExtendedFiltering) {
3258 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
3259 if (ug_info->largestexternallookupkeysize ==
3260 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3261 size +=
3262 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
3263 if (ug_info->largestexternallookupkeysize ==
3264 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
3265 size +=
3266 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
3267 }
3268
3269 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
3270 p_init_enet_param_shadow->rxthread[0]),
3271 (u8) (numThreadsRxNumerical + 1)
3272 /* Rx needs one extra for terminator */
3273 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
3274 ug_info->riscRx, 1)) != 0) {
890de95e
LY		 3275 if (netif_msg_ifup(ugeth))
3276 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
b39d66a8 3277 __func__);
ce973b14
LY		 3278 ucc_geth_memclean(ugeth);
3279 return ret_val;
3280 }
3281
3282 ugeth->p_init_enet_param_shadow->txglobal =
3283 ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3284 if ((ret_val =
3285 fill_init_enet_entries(ugeth,
3286 &(ugeth->p_init_enet_param_shadow->
3287 txthread[0]), numThreadsTxNumerical,
18a8e864 3288 sizeof(struct ucc_geth_thread_tx_pram),
ce973b14
LY		 3289 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3290 ug_info->riscTx, 0)) != 0) {
890de95e
LY		 3291 if (netif_msg_ifup(ugeth))
3292 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
b39d66a8 3293 __func__);
ce973b14
LY		 3294 ucc_geth_memclean(ugeth);
3295 return ret_val;
3296 }
3297
3298 /* Load Rx bds with buffers */
3299 for (i = 0; i < ug_info->numQueuesRx; i++) {
3300 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
890de95e
LY		 3301 if (netif_msg_ifup(ugeth))
3302 ugeth_err("%s: Can not fill Rx bds with buffers.",
b39d66a8 3303 __func__);
ce973b14
LY		 3304 ucc_geth_memclean(ugeth);
3305 return ret_val;
3306 }
3307 }
3308
3309 /* Allocate InitEnet command parameter structure */
18a8e864 3310 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
4c35630c 3311 if (IS_ERR_VALUE(init_enet_pram_offset)) {
890de95e
LY		 3312 if (netif_msg_ifup(ugeth))
3313 ugeth_err
3314 ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
b39d66a8 3315 __func__);
ce973b14
LY		 3316 ucc_geth_memclean(ugeth);
3317 return -ENOMEM;
3318 }
3319 p_init_enet_pram =
6fee40e9 3320 (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset);
ce973b14
LY		 3321
3322 /* Copy shadow InitEnet command parameter structure into PRAM */
6fee40e9
AF		 3323 out_8(&p_init_enet_pram->resinit1,
3324 ugeth->p_init_enet_param_shadow->resinit1);
3325 out_8(&p_init_enet_pram->resinit2,
3326 ugeth->p_init_enet_param_shadow->resinit2);
3327 out_8(&p_init_enet_pram->resinit3,
3328 ugeth->p_init_enet_param_shadow->resinit3);
3329 out_8(&p_init_enet_pram->resinit4,
3330 ugeth->p_init_enet_param_shadow->resinit4);
ce973b14
LY		 3331 out_be16(&p_init_enet_pram->resinit5,
3332 ugeth->p_init_enet_param_shadow->resinit5);
6fee40e9
AF		 3333 out_8(&p_init_enet_pram->largestexternallookupkeysize,
3334 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
ce973b14
LY		 3335 out_be32(&p_init_enet_pram->rgftgfrxglobal,
3336 ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3337 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3338 out_be32(&p_init_enet_pram->rxthread[i],
3339 ugeth->p_init_enet_param_shadow->rxthread[i]);
3340 out_be32(&p_init_enet_pram->txglobal,
3341 ugeth->p_init_enet_param_shadow->txglobal);
3342 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3343 out_be32(&p_init_enet_pram->txthread[i],
3344 ugeth->p_init_enet_param_shadow->txthread[i]);
3345
3346 /* Issue QE command */
3347 cecr_subblock =
3348 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
18a8e864 3349 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
ce973b14
LY		 3350 init_enet_pram_offset);
3351
3352 /* Free InitEnet command parameter */
3353 qe_muram_free(init_enet_pram_offset);
3354
3355 return 0;
3356}
3357
1762a29a
AV		 3358static int ucc_geth_close(struct net_device *dev);
3359static int ucc_geth_open(struct net_device *dev);
3360
3361/* Reopen device. This will reset the MAC and PHY. */
3362static void ucc_geth_timeout_work(struct work_struct *work)
ce973b14 3363{
1762a29a
AV		 3364 struct ucc_geth_private *ugeth;
3365 struct net_device *dev;
3366
3367 ugeth = container_of(work, struct ucc_geth_private, timeout_work);
3368 dev = ugeth->dev;
ce973b14 3369
b39d66a8 3370 ugeth_vdbg("%s: IN", __func__);
ce973b14 3371
09f75cd7 3372 dev->stats.tx_errors++;
ce973b14
LY		 3373
3374 ugeth_dump_regs(ugeth);
3375
3376 if (dev->flags & IFF_UP) {
1762a29a
AV		 3377 /*
3378 * Must reset MAC *and* PHY. This is done by reopening
3379 * the device.
3380 */
3381 ucc_geth_close(dev);
3382 ucc_geth_open(dev);
ce973b14
LY		 3383 }
3384
263ba320 3385 netif_tx_schedule_all(dev);
ce973b14
LY		 3386}
3387
1762a29a
AV		 3388/*
3389 * ucc_geth_timeout gets called when a packet has not been
3390 * transmitted after a set amount of time.
3391 */
3392static void ucc_geth_timeout(struct net_device *dev)
3393{
3394 struct ucc_geth_private *ugeth = netdev_priv(dev);
3395
3396 netif_carrier_off(dev);
3397 schedule_work(&ugeth->timeout_work);
3398}
3399
ce973b14
LY		 3400/* This is called by the kernel when a frame is ready for transmission. */
3401/* It is pointed to by the dev->hard_start_xmit function pointer */
3402static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3403{
18a8e864 3404 struct ucc_geth_private *ugeth = netdev_priv(dev);
d5b9049d
MR		 3405#ifdef CONFIG_UGETH_TX_ON_DEMAND
3406 struct ucc_fast_private *uccf;
3407#endif
6fee40e9 3408 u8 __iomem *bd; /* BD pointer */
ce973b14
LY		 3409 u32 bd_status;
3410 u8 txQ = 0;
3411
b39d66a8 3412 ugeth_vdbg("%s: IN", __func__);
ce973b14
LY		 3413
3414 spin_lock_irq(&ugeth->lock);
3415
09f75cd7 3416 dev->stats.tx_bytes += skb->len;
ce973b14
LY		 3417
3418 /* Start from the next BD that should be filled */
3419 bd = ugeth->txBd[txQ];
6fee40e9 3420 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3421 /* Save the skb pointer so we can free it later */
3422 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3423
3424 /* Update the current skb pointer (wrapping if this was the last) */
3425 ugeth->skb_curtx[txQ] =
3426 (ugeth->skb_curtx[txQ] +
3427 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3428
3429 /* set up the buffer descriptor */
6fee40e9 3430 out_be32(&((struct qe_bd __iomem *)bd)->buf,
7f80202b
AF		 3431 dma_map_single(&ugeth->dev->dev, skb->data,
3432 skb->len, DMA_TO_DEVICE));
ce973b14 3433
18a8e864 3434 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
ce973b14
LY		 3435
3436 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3437
18a8e864 3438 /* set bd status and length */
6fee40e9 3439 out_be32((u32 __iomem *)bd, bd_status);
ce973b14
LY		 3440
3441 dev->trans_start = jiffies;
3442
3443 /* Move to next BD in the ring */
3444 if (!(bd_status & T_W))
a394f013 3445 bd += sizeof(struct qe_bd);
ce973b14 3446 else
a394f013 3447 bd = ugeth->p_tx_bd_ring[txQ];
ce973b14
LY		 3448
3449 /* If the next BD still needs to be cleaned up, then the bds
3450 are full. We need to tell the kernel to stop sending us stuff. */
3451 if (bd == ugeth->confBd[txQ]) {
3452 if (!netif_queue_stopped(dev))
3453 netif_stop_queue(dev);
3454 }
3455
a394f013
LY		 3456 ugeth->txBd[txQ] = bd;
3457
ce973b14
LY		 3458 if (ugeth->p_scheduler) {
3459 ugeth->cpucount[txQ]++;
3460 /* Indicate to QE that there are more Tx bds ready for
3461 transmission */
3462 /* This is done by writing a running counter of the bd
3463 count to the scheduler PRAM. */
3464 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3465 }
3466
d5b9049d
MR		 3467#ifdef CONFIG_UGETH_TX_ON_DEMAND
3468 uccf = ugeth->uccf;
3469 out_be16(uccf->p_utodr, UCC_FAST_TOD);
3470#endif
ce973b14
LY		 3471 spin_unlock_irq(&ugeth->lock);
3472
6f6881b8 3473 return 0;
ce973b14
LY		 3474}
3475
18a8e864 3476static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
ce973b14
LY		 3477{
3478 struct sk_buff *skb;
6fee40e9 3479 u8 __iomem *bd;
ce973b14
LY		 3480 u16 length, howmany = 0;
3481 u32 bd_status;
3482 u8 *bdBuffer;
4b8fdefa 3483 struct net_device *dev;
ce973b14 3484
b39d66a8 3485 ugeth_vdbg("%s: IN", __func__);
ce973b14 3486
88a15f2e
EM		 3487 dev = ugeth->dev;
3488
ce973b14
LY		 3489 /* collect received buffers */
3490 bd = ugeth->rxBd[rxQ];
3491
6fee40e9 3492 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3493
3494 /* while there are received buffers and BD is full (~R_E) */
3495 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
6fee40e9 3496 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf);
ce973b14
LY		 3497 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3498 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3499
3500 /* determine whether buffer is first, last, first and last
3501 (single buffer frame) or middle (not first and not last) */
3502 if (!skb ||
3503 (!(bd_status & (R_F | R_L))) ||
3504 (bd_status & R_ERRORS_FATAL)) {
890de95e
LY		 3505 if (netif_msg_rx_err(ugeth))
3506 ugeth_err("%s, %d: ERROR!!! skb - 0x%08x",
b39d66a8 3507 __func__, __LINE__, (u32) skb);
ce973b14
LY		 3508 if (skb)
3509 dev_kfree_skb_any(skb);
3510
3511 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
09f75cd7 3512 dev->stats.rx_dropped++;
ce973b14 3513 } else {
09f75cd7 3514 dev->stats.rx_packets++;
ce973b14
LY		 3515 howmany++;
3516
3517 /* Prep the skb for the packet */
3518 skb_put(skb, length);
3519
3520 /* Tell the skb what kind of packet this is */
3521 skb->protocol = eth_type_trans(skb, ugeth->dev);
3522
09f75cd7 3523 dev->stats.rx_bytes += length;
ce973b14 3524 /* Send the packet up the stack */
ce973b14 3525 netif_receive_skb(skb);
ce973b14
LY		 3526 }
3527
ce973b14
LY		 3528 skb = get_new_skb(ugeth, bd);
3529 if (!skb) {
890de95e 3530 if (netif_msg_rx_err(ugeth))
b39d66a8 3531 ugeth_warn("%s: No Rx Data Buffer", __func__);
09f75cd7 3532 dev->stats.rx_dropped++;
ce973b14
LY		 3533 break;
3534 }
3535
3536 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3537
3538 /* update to point at the next skb */
3539 ugeth->skb_currx[rxQ] =
3540 (ugeth->skb_currx[rxQ] +
3541 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3542
3543 if (bd_status & R_W)
3544 bd = ugeth->p_rx_bd_ring[rxQ];
3545 else
18a8e864 3546 bd += sizeof(struct qe_bd);
ce973b14 3547
6fee40e9 3548 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3549 }
3550
3551 ugeth->rxBd[rxQ] = bd;
ce973b14
LY		 3552 return howmany;
3553}
3554
3555static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3556{
3557 /* Start from the next BD that should be filled */
18a8e864 3558 struct ucc_geth_private *ugeth = netdev_priv(dev);
6fee40e9 3559 u8 __iomem *bd; /* BD pointer */
ce973b14
LY		 3560 u32 bd_status;
3561
3562 bd = ugeth->confBd[txQ];
6fee40e9 3563 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3564
3565 /* Normal processing. */
3566 while ((bd_status & T_R) == 0) {
3567 /* BD contains already transmitted buffer. */
3568 /* Handle the transmitted buffer and release */
3569 /* the BD to be used with the current frame */
3570
a394f013 3571 if ((bd == ugeth->txBd[txQ]) && (netif_queue_stopped(dev) == 0))
ce973b14
LY		 3572 break;
3573
09f75cd7 3574 dev->stats.tx_packets++;
ce973b14
LY		 3575
3576 /* Free the sk buffer associated with this TxBD */
3577 dev_kfree_skb_irq(ugeth->
3578 tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]);
3579 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3580 ugeth->skb_dirtytx[txQ] =
3581 (ugeth->skb_dirtytx[txQ] +
3582 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3583
3584 /* We freed a buffer, so now we can restart transmission */
3585 if (netif_queue_stopped(dev))
3586 netif_wake_queue(dev);
3587
3588 /* Advance the confirmation BD pointer */
3589 if (!(bd_status & T_W))
a394f013 3590 bd += sizeof(struct qe_bd);
ce973b14 3591 else
a394f013 3592 bd = ugeth->p_tx_bd_ring[txQ];
6fee40e9 3593 bd_status = in_be32((u32 __iomem *)bd);
ce973b14 3594 }
a394f013 3595 ugeth->confBd[txQ] = bd;
ce973b14
LY		 3596 return 0;
3597}
3598
bea3348e 3599static int ucc_geth_poll(struct napi_struct *napi, int budget)
ce973b14 3600{
bea3348e
SH		 3601 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
3602 struct net_device *dev = ugeth->dev;
702ff12c 3603 struct ucc_geth_info *ug_info;
bea3348e 3604 int howmany, i;
ce973b14 3605
702ff12c
MR		 3606 ug_info = ugeth->ug_info;
3607
702ff12c 3608 howmany = 0;
bea3348e
SH		 3609 for (i = 0; i < ug_info->numQueuesRx; i++)
3610 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
702ff12c 3611
bea3348e
SH		 3612 if (howmany < budget) {
3613 struct ucc_fast_private *uccf;
3614 u32 uccm;
ce973b14 3615
bea3348e 3616 netif_rx_complete(dev, napi);
702ff12c
MR		 3617 uccf = ugeth->uccf;
3618 uccm = in_be32(uccf->p_uccm);
3619 uccm |= UCCE_RX_EVENTS;
3620 out_be32(uccf->p_uccm, uccm);
3621 }
ce973b14 3622
bea3348e 3623 return howmany;
ce973b14 3624}
ce973b14 3625
7d12e780 3626static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
ce973b14 3627{
06efcad0 3628 struct net_device *dev = info;
18a8e864
LY		 3629 struct ucc_geth_private *ugeth = netdev_priv(dev);
3630 struct ucc_fast_private *uccf;
3631 struct ucc_geth_info *ug_info;
702ff12c
MR		 3632 register u32 ucce;
3633 register u32 uccm;
702ff12c
MR		 3634 register u32 tx_mask;
3635 u8 i;
ce973b14 3636
b39d66a8 3637 ugeth_vdbg("%s: IN", __func__);
ce973b14 3638
ce973b14
LY		 3639 uccf = ugeth->uccf;
3640 ug_info = ugeth->ug_info;
3641
702ff12c
MR		 3642 /* read and clear events */
3643 ucce = (u32) in_be32(uccf->p_ucce);
3644 uccm = (u32) in_be32(uccf->p_uccm);
3645 ucce &= uccm;
3646 out_be32(uccf->p_ucce, ucce);
ce973b14 3647
702ff12c
MR		 3648 /* check for receive events that require processing */
3649 if (ucce & UCCE_RX_EVENTS) {
bea3348e
SH		 3650 if (netif_rx_schedule_prep(dev, &ugeth->napi)) {
3651 uccm &= ~UCCE_RX_EVENTS;
702ff12c 3652 out_be32(uccf->p_uccm, uccm);
bea3348e 3653 __netif_rx_schedule(dev, &ugeth->napi);
702ff12c 3654 }
702ff12c 3655 }
ce973b14 3656
702ff12c
MR		 3657 /* Tx event processing */
3658 if (ucce & UCCE_TX_EVENTS) {
3659 spin_lock(&ugeth->lock);
3660 tx_mask = UCCE_TXBF_SINGLE_MASK;
ce973b14
LY		 3661 for (i = 0; i < ug_info->numQueuesTx; i++) {
3662 if (ucce & tx_mask)
3663 ucc_geth_tx(dev, i);
3664 ucce &= ~tx_mask;
3665 tx_mask <<= 1;
3666 }
702ff12c
MR		 3667 spin_unlock(&ugeth->lock);
3668 }
ce973b14 3669
702ff12c
MR		 3670 /* Errors and other events */
3671 if (ucce & UCCE_OTHER) {
ce973b14 3672 if (ucce & UCCE_BSY) {
09f75cd7 3673 dev->stats.rx_errors++;
ce973b14 3674 }
702ff12c 3675 if (ucce & UCCE_TXE) {
09f75cd7 3676 dev->stats.tx_errors++;
ce973b14
LY		 3677 }
3678 }
ce973b14
LY		 3679
3680 return IRQ_HANDLED;
3681}
3682
26d29ea7
AV		 3683#ifdef CONFIG_NET_POLL_CONTROLLER
3684/*
3685 * Polling 'interrupt' - used by things like netconsole to send skbs
3686 * without having to re-enable interrupts. It's not called while
3687 * the interrupt routine is executing.
3688 */
3689static void ucc_netpoll(struct net_device *dev)
3690{
3691 struct ucc_geth_private *ugeth = netdev_priv(dev);
3692 int irq = ugeth->ug_info->uf_info.irq;
3693
3694 disable_irq(irq);
3695 ucc_geth_irq_handler(irq, dev);
3696 enable_irq(irq);
3697}
3698#endif /* CONFIG_NET_POLL_CONTROLLER */
3699
ce973b14
LY		 3700/* Called when something needs to use the ethernet device */
3701/* Returns 0 for success. */
3702static int ucc_geth_open(struct net_device *dev)
3703{
18a8e864 3704 struct ucc_geth_private *ugeth = netdev_priv(dev);
ce973b14
LY		 3705 int err;
3706
b39d66a8 3707 ugeth_vdbg("%s: IN", __func__);
ce973b14
LY		 3708
3709 /* Test station address */
3710 if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
890de95e
LY		 3711 if (netif_msg_ifup(ugeth))
3712 ugeth_err("%s: Multicast address used for station address"
b39d66a8 3713 " - is this what you wanted?", __func__);
ce973b14
LY		 3714 return -EINVAL;
3715 }
3716
728de4c9
KP		 3717 err = ucc_struct_init(ugeth);
3718 if (err) {
890de95e
LY		 3719 if (netif_msg_ifup(ugeth))
3720 ugeth_err("%s: Cannot configure internal struct, aborting.", dev->name);
728de4c9
KP		 3721 return err;
3722 }
3723
bea3348e 3724 napi_enable(&ugeth->napi);
1a342d22 3725
ce973b14
LY		 3726 err = ucc_geth_startup(ugeth);
3727 if (err) {
890de95e
LY		 3728 if (netif_msg_ifup(ugeth))
3729 ugeth_err("%s: Cannot configure net device, aborting.",
3730 dev->name);
bea3348e 3731 goto out_err;
ce973b14
LY		 3732 }
3733
3734 err = adjust_enet_interface(ugeth);
3735 if (err) {
890de95e
LY		 3736 if (netif_msg_ifup(ugeth))
3737 ugeth_err("%s: Cannot configure net device, aborting.",
3738 dev->name);
bea3348e 3739 goto out_err;
ce973b14
LY		 3740 }
3741
3742 /* Set MACSTNADDR1, MACSTNADDR2 */
3743 /* For more details see the hardware spec. */
3744 init_mac_station_addr_regs(dev->dev_addr[0],
3745 dev->dev_addr[1],
3746 dev->dev_addr[2],
3747 dev->dev_addr[3],
3748 dev->dev_addr[4],
3749 dev->dev_addr[5],
3750 &ugeth->ug_regs->macstnaddr1,
3751 &ugeth->ug_regs->macstnaddr2);
3752
3753 err = init_phy(dev);
3754 if (err) {
890de95e
LY		 3755 if (netif_msg_ifup(ugeth))
3756 ugeth_err("%s: Cannot initialize PHY, aborting.", dev->name);
bea3348e 3757 goto out_err;
ce973b14 3758 }
728de4c9
KP		 3759
3760 phy_start(ugeth->phydev);
3761
ce973b14
LY		 3762 err =
3763 request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler, 0,
3764 "UCC Geth", dev);
3765 if (err) {
890de95e
LY		 3766 if (netif_msg_ifup(ugeth))
3767 ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3768 dev->name);
ce973b14 3769 ucc_geth_stop(ugeth);
bea3348e 3770 goto out_err;
ce973b14 3771 }
ce973b14 3772
ce973b14
LY		 3773 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3774 if (err) {
890de95e
LY		 3775 if (netif_msg_ifup(ugeth))
3776 ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
ce973b14 3777 ucc_geth_stop(ugeth);
bea3348e 3778 goto out_err;
ce973b14
LY		 3779 }
3780
3781 netif_start_queue(dev);
3782
3783 return err;
bea3348e
SH		 3784
3785out_err:
bea3348e 3786 napi_disable(&ugeth->napi);
1a342d22 3787
bea3348e 3788 return err;
ce973b14
LY		 3789}
3790
3791/* Stops the kernel queue, and halts the controller */
3792static int ucc_geth_close(struct net_device *dev)
3793{
18a8e864 3794 struct ucc_geth_private *ugeth = netdev_priv(dev);
ce973b14 3795
b39d66a8 3796 ugeth_vdbg("%s: IN", __func__);
ce973b14 3797
bea3348e 3798 napi_disable(&ugeth->napi);
bea3348e 3799
ce973b14
LY		 3800 ucc_geth_stop(ugeth);
3801
728de4c9
KP		 3802 phy_disconnect(ugeth->phydev);
3803 ugeth->phydev = NULL;
ce973b14
LY		 3804
3805 netif_stop_queue(dev);
3806
3807 return 0;
3808}
3809
4e19b5c1 3810static phy_interface_t to_phy_interface(const char *phy_connection_type)
728de4c9 3811{
4e19b5c1 3812 if (strcasecmp(phy_connection_type, "mii") == 0)
728de4c9 3813 return PHY_INTERFACE_MODE_MII;
4e19b5c1 3814 if (strcasecmp(phy_connection_type, "gmii") == 0)
728de4c9 3815 return PHY_INTERFACE_MODE_GMII;
4e19b5c1 3816 if (strcasecmp(phy_connection_type, "tbi") == 0)
728de4c9 3817 return PHY_INTERFACE_MODE_TBI;
4e19b5c1 3818 if (strcasecmp(phy_connection_type, "rmii") == 0)
728de4c9 3819 return PHY_INTERFACE_MODE_RMII;
4e19b5c1 3820 if (strcasecmp(phy_connection_type, "rgmii") == 0)
728de4c9 3821 return PHY_INTERFACE_MODE_RGMII;
4e19b5c1 3822 if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
728de4c9 3823 return PHY_INTERFACE_MODE_RGMII_ID;
bd0ceaab
KP		 3824 if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3825 return PHY_INTERFACE_MODE_RGMII_TXID;
3826 if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3827 return PHY_INTERFACE_MODE_RGMII_RXID;
4e19b5c1 3828 if (strcasecmp(phy_connection_type, "rtbi") == 0)
728de4c9
KP		 3829 return PHY_INTERFACE_MODE_RTBI;
3830
3831 return PHY_INTERFACE_MODE_MII;
3832}
3833
18a8e864 3834static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *match)
ce973b14 3835{
18a8e864
LY		 3836 struct device *device = &ofdev->dev;
3837 struct device_node *np = ofdev->node;
728de4c9 3838 struct device_node *mdio;
ce973b14
LY		 3839 struct net_device *dev = NULL;
3840 struct ucc_geth_private *ugeth = NULL;
3841 struct ucc_geth_info *ug_info;
18a8e864
LY		 3842 struct resource res;
3843 struct device_node *phy;
728de4c9 3844 int err, ucc_num, max_speed = 0;
18a8e864 3845 const phandle *ph;
3d137fdd 3846 const u32 *fixed_link;
18a8e864 3847 const unsigned int *prop;
9fb1e350 3848 const char *sprop;
9b4c7a4e 3849 const void *mac_addr;
728de4c9
KP		 3850 phy_interface_t phy_interface;
3851 static const int enet_to_speed[] = {
3852 SPEED_10, SPEED_10, SPEED_10,
3853 SPEED_100, SPEED_100, SPEED_100,
3854 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3855 };
3856 static const phy_interface_t enet_to_phy_interface[] = {
3857 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3858 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3859 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3860 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3861 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
3862 };
ce973b14 3863
b39d66a8 3864 ugeth_vdbg("%s: IN", __func__);
ce973b14 3865
56626f33
AV		 3866 prop = of_get_property(np, "cell-index", NULL);
3867 if (!prop) {
3868 prop = of_get_property(np, "device-id", NULL);
3869 if (!prop)
3870 return -ENODEV;
3871 }
3872
18a8e864
LY		 3873 ucc_num = *prop - 1;
3874 if ((ucc_num < 0) || (ucc_num > 7))
3875 return -ENODEV;
3876
3877 ug_info = &ugeth_info[ucc_num];
890de95e
LY		 3878 if (ug_info == NULL) {
3879 if (netif_msg_probe(&debug))
3880 ugeth_err("%s: [%d] Missing additional data!",
b39d66a8 3881 __func__, ucc_num);
890de95e
LY		 3882 return -ENODEV;
3883 }
3884
18a8e864 3885 ug_info->uf_info.ucc_num = ucc_num;
728de4c9 3886
9fb1e350
TT		 3887 sprop = of_get_property(np, "rx-clock-name", NULL);
3888 if (sprop) {
3889 ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3890 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3891 (ug_info->uf_info.rx_clock > QE_CLK24)) {
3892 printk(KERN_ERR
3893 "ucc_geth: invalid rx-clock-name property\n");
3894 return -EINVAL;
3895 }
3896 } else {
3897 prop = of_get_property(np, "rx-clock", NULL);
3898 if (!prop) {
3899 /* If both rx-clock-name and rx-clock are missing,
3900 we want to tell people to use rx-clock-name. */
3901 printk(KERN_ERR
3902 "ucc_geth: missing rx-clock-name property\n");
3903 return -EINVAL;
3904 }
3905 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3906 printk(KERN_ERR
3907 "ucc_geth: invalid rx-clock propperty\n");
3908 return -EINVAL;
3909 }
3910 ug_info->uf_info.rx_clock = *prop;
3911 }
3912
3913 sprop = of_get_property(np, "tx-clock-name", NULL);
3914 if (sprop) {
3915 ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3916 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3917 (ug_info->uf_info.tx_clock > QE_CLK24)) {
3918 printk(KERN_ERR
3919 "ucc_geth: invalid tx-clock-name property\n");
3920 return -EINVAL;
3921 }
3922 } else {
e410553f 3923 prop = of_get_property(np, "tx-clock", NULL);
9fb1e350
TT		 3924 if (!prop) {
3925 printk(KERN_ERR
3926 "ucc_geth: mising tx-clock-name property\n");
3927 return -EINVAL;
3928 }
3929 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3930 printk(KERN_ERR
3931 "ucc_geth: invalid tx-clock property\n");
3932 return -EINVAL;
3933 }
3934 ug_info->uf_info.tx_clock = *prop;
3935 }
3936
18a8e864
LY		 3937 err = of_address_to_resource(np, 0, &res);
3938 if (err)
3939 return -EINVAL;
3940
3941 ug_info->uf_info.regs = res.start;
3942 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3d137fdd
JT		 3943 fixed_link = of_get_property(np, "fixed-link", NULL);
3944 if (fixed_link) {
f38d1008 3945 snprintf(ug_info->mdio_bus, MII_BUS_ID_SIZE, "0");
3d137fdd
JT		 3946 ug_info->phy_address = fixed_link[0];
3947 phy = NULL;
3948 } else {
3949 ph = of_get_property(np, "phy-handle", NULL);
3950 phy = of_find_node_by_phandle(*ph);
18a8e864 3951
3d137fdd
JT		 3952 if (phy == NULL)
3953 return -ENODEV;
ce973b14 3954
3d137fdd
JT		 3955 /* set the PHY address */
3956 prop = of_get_property(phy, "reg", NULL);
3957 if (prop == NULL)
3958 return -1;
3959 ug_info->phy_address = *prop;
3960
3961 /* Set the bus id */
3962 mdio = of_get_parent(phy);
3963
3964 if (mdio == NULL)
3965 return -1;
18a8e864 3966
3d137fdd
JT		 3967 err = of_address_to_resource(mdio, 0, &res);
3968 of_node_put(mdio);
3969
3970 if (err)
3971 return -1;
3972
9d9326d3 3973 snprintf(ug_info->mdio_bus, MII_BUS_ID_SIZE, "%x", res.start);
3d137fdd 3974 }
728de4c9
KP		 3975
3976 /* get the phy interface type, or default to MII */
4e19b5c1 3977 prop = of_get_property(np, "phy-connection-type", NULL);
728de4c9
KP		 3978 if (!prop) {
3979 /* handle interface property present in old trees */
40cd3a45 3980 prop = of_get_property(phy, "interface", NULL);
4e19b5c1 3981 if (prop != NULL) {
728de4c9 3982 phy_interface = enet_to_phy_interface[*prop];
4e19b5c1
KP		 3983 max_speed = enet_to_speed[*prop];
3984 } else
728de4c9
KP		 3985 phy_interface = PHY_INTERFACE_MODE_MII;
3986 } else {
3987 phy_interface = to_phy_interface((const char *)prop);
3988 }
3989
4e19b5c1
KP		 3990 /* get speed, or derive from PHY interface */
3991 if (max_speed == 0)
728de4c9
KP		 3992 switch (phy_interface) {
3993 case PHY_INTERFACE_MODE_GMII:
3994 case PHY_INTERFACE_MODE_RGMII:
3995 case PHY_INTERFACE_MODE_RGMII_ID:
bd0ceaab
KP		 3996 case PHY_INTERFACE_MODE_RGMII_RXID:
3997 case PHY_INTERFACE_MODE_RGMII_TXID:
728de4c9
KP		 3998 case PHY_INTERFACE_MODE_TBI:
3999 case PHY_INTERFACE_MODE_RTBI:
4000 max_speed = SPEED_1000;
4001 break;
4002 default:
4003 max_speed = SPEED_100;
4004 break;
4005 }
728de4c9
KP		 4006
4007 if (max_speed == SPEED_1000) {
4e19b5c1 4008 /* configure muram FIFOs for gigabit operation */
728de4c9
KP		 4009 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
4010 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
4011 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
4012 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
4013 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
4014 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
ffea31ed
JT		 4015 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
4016 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
728de4c9
KP		 4017 }
4018
890de95e
LY		 4019 if (netif_msg_probe(&debug))
4020 printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
4021 ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
4022 ug_info->uf_info.irq);
ce973b14 4023
ce973b14
LY		 4024 /* Create an ethernet device instance */
4025 dev = alloc_etherdev(sizeof(*ugeth));
4026
4027 if (dev == NULL)
4028 return -ENOMEM;
4029
4030 ugeth = netdev_priv(dev);
4031 spin_lock_init(&ugeth->lock);
4032
80a9fad8
AV		 4033 /* Create CQs for hash tables */
4034 INIT_LIST_HEAD(&ugeth->group_hash_q);
4035 INIT_LIST_HEAD(&ugeth->ind_hash_q);
4036
ce973b14
LY		 4037 dev_set_drvdata(device, dev);
4038
4039 /* Set the dev->base_addr to the gfar reg region */
4040 dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
4041
ce973b14
LY		 4042 SET_NETDEV_DEV(dev, device);
4043
4044 /* Fill in the dev structure */
ac421852 4045 uec_set_ethtool_ops(dev);
ce973b14
LY		 4046 dev->open = ucc_geth_open;
4047 dev->hard_start_xmit = ucc_geth_start_xmit;
4048 dev->tx_timeout = ucc_geth_timeout;
4049 dev->watchdog_timeo = TX_TIMEOUT;
1762a29a 4050 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
bea3348e 4051 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, UCC_GETH_DEV_WEIGHT);
26d29ea7
AV		 4052#ifdef CONFIG_NET_POLL_CONTROLLER
4053 dev->poll_controller = ucc_netpoll;
4054#endif
ce973b14 4055 dev->stop = ucc_geth_close;
ce973b14
LY		 4056// dev->change_mtu = ucc_geth_change_mtu;
4057 dev->mtu = 1500;
4058 dev->set_multicast_list = ucc_geth_set_multi;
ce973b14 4059
890de95e 4060 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
728de4c9
KP		 4061 ugeth->phy_interface = phy_interface;
4062 ugeth->max_speed = max_speed;
4063
ce973b14
LY		 4064 err = register_netdev(dev);
4065 if (err) {
890de95e
LY		 4066 if (netif_msg_probe(ugeth))
4067 ugeth_err("%s: Cannot register net device, aborting.",
4068 dev->name);
ce973b14
LY		 4069 free_netdev(dev);
4070 return err;
4071 }
4072
e9eb70c9 4073 mac_addr = of_get_mac_address(np);
9b4c7a4e
LY		 4074 if (mac_addr)
4075 memcpy(dev->dev_addr, mac_addr, 6);
ce973b14 4076
728de4c9
KP		 4077 ugeth->ug_info = ug_info;
4078 ugeth->dev = dev;
4079
ce973b14
LY		 4080 return 0;
4081}
4082
18a8e864 4083static int ucc_geth_remove(struct of_device* ofdev)
ce973b14 4084{
18a8e864 4085 struct device *device = &ofdev->dev;
ce973b14
LY		 4086 struct net_device *dev = dev_get_drvdata(device);
4087 struct ucc_geth_private *ugeth = netdev_priv(dev);
4088
80a9fad8 4089 unregister_netdev(dev);
ce973b14 4090 free_netdev(dev);
80a9fad8
AV		 4091 ucc_geth_memclean(ugeth);
4092 dev_set_drvdata(device, NULL);
ce973b14
LY		 4093
4094 return 0;
4095}
4096
18a8e864
LY		 4097static struct of_device_id ucc_geth_match[] = {
4098 {
4099 .type = "network",
4100 .compatible = "ucc_geth",
4101 },
4102 {},
4103};
4104
4105MODULE_DEVICE_TABLE(of, ucc_geth_match);
4106
4107static struct of_platform_driver ucc_geth_driver = {
4108 .name = DRV_NAME,
4109 .match_table = ucc_geth_match,
4110 .probe = ucc_geth_probe,
4111 .remove = ucc_geth_remove,
ce973b14
LY		 4112};
4113
4114static int __init ucc_geth_init(void)
4115{
728de4c9
KP		 4116 int i, ret;
4117
4118 ret = uec_mdio_init();
4119
4120 if (ret)
4121 return ret;
18a8e864 4122
890de95e
LY		 4123 if (netif_msg_drv(&debug))
4124 printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
ce973b14
LY		 4125 for (i = 0; i < 8; i++)
4126 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
4127 sizeof(ugeth_primary_info));
4128
728de4c9
KP		 4129 ret = of_register_platform_driver(&ucc_geth_driver);
4130
4131 if (ret)
4132 uec_mdio_exit();
4133
4134 return ret;
ce973b14
LY		 4135}
4136
4137static void __exit ucc_geth_exit(void)
4138{
a4f0c2ca 4139 of_unregister_platform_driver(&ucc_geth_driver);
728de4c9 4140 uec_mdio_exit();
ce973b14
LY		 4141}
4142
4143module_init(ucc_geth_init);
4144module_exit(ucc_geth_exit);
4145
4146MODULE_AUTHOR("Freescale Semiconductor, Inc");
4147MODULE_DESCRIPTION(DRV_DESC);
c2bcf00b 4148MODULE_VERSION(DRV_VERSION);
ce973b14 4149MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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