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2e55cc72 DB |
1 | /* |
2 | * ASIX AX8817X based USB 2.0 Ethernet Devices | |
933a27d3 | 3 | * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com> |
2e55cc72 | 4 | * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net> |
933a27d3 | 5 | * Copyright (C) 2006 James Painter <jamie.painter@iname.com> |
2e55cc72 DB |
6 | * Copyright (c) 2002-2003 TiVo Inc. |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | // #define DEBUG // error path messages, extra info | |
24 | // #define VERBOSE // more; success messages | |
25 | ||
2e55cc72 DB |
26 | #include <linux/module.h> |
27 | #include <linux/kmod.h> | |
2e55cc72 DB |
28 | #include <linux/init.h> |
29 | #include <linux/netdevice.h> | |
30 | #include <linux/etherdevice.h> | |
31 | #include <linux/ethtool.h> | |
32 | #include <linux/workqueue.h> | |
33 | #include <linux/mii.h> | |
34 | #include <linux/usb.h> | |
35 | #include <linux/crc32.h> | |
3692e94f | 36 | #include <linux/usb/usbnet.h> |
2e55cc72 | 37 | |
933a27d3 DH |
38 | #define DRIVER_VERSION "14-Jun-2006" |
39 | static const char driver_name [] = "asix"; | |
40 | ||
2e55cc72 DB |
41 | /* ASIX AX8817X based USB 2.0 Ethernet Devices */ |
42 | ||
43 | #define AX_CMD_SET_SW_MII 0x06 | |
44 | #define AX_CMD_READ_MII_REG 0x07 | |
45 | #define AX_CMD_WRITE_MII_REG 0x08 | |
46 | #define AX_CMD_SET_HW_MII 0x0a | |
47 | #define AX_CMD_READ_EEPROM 0x0b | |
48 | #define AX_CMD_WRITE_EEPROM 0x0c | |
49 | #define AX_CMD_WRITE_ENABLE 0x0d | |
50 | #define AX_CMD_WRITE_DISABLE 0x0e | |
933a27d3 | 51 | #define AX_CMD_READ_RX_CTL 0x0f |
2e55cc72 DB |
52 | #define AX_CMD_WRITE_RX_CTL 0x10 |
53 | #define AX_CMD_READ_IPG012 0x11 | |
54 | #define AX_CMD_WRITE_IPG0 0x12 | |
55 | #define AX_CMD_WRITE_IPG1 0x13 | |
933a27d3 | 56 | #define AX_CMD_READ_NODE_ID 0x13 |
2e55cc72 DB |
57 | #define AX_CMD_WRITE_IPG2 0x14 |
58 | #define AX_CMD_WRITE_MULTI_FILTER 0x16 | |
933a27d3 | 59 | #define AX88172_CMD_READ_NODE_ID 0x17 |
2e55cc72 DB |
60 | #define AX_CMD_READ_PHY_ID 0x19 |
61 | #define AX_CMD_READ_MEDIUM_STATUS 0x1a | |
62 | #define AX_CMD_WRITE_MEDIUM_MODE 0x1b | |
63 | #define AX_CMD_READ_MONITOR_MODE 0x1c | |
64 | #define AX_CMD_WRITE_MONITOR_MODE 0x1d | |
933a27d3 | 65 | #define AX_CMD_READ_GPIOS 0x1e |
2e55cc72 DB |
66 | #define AX_CMD_WRITE_GPIOS 0x1f |
67 | #define AX_CMD_SW_RESET 0x20 | |
68 | #define AX_CMD_SW_PHY_STATUS 0x21 | |
69 | #define AX_CMD_SW_PHY_SELECT 0x22 | |
2e55cc72 DB |
70 | |
71 | #define AX_MONITOR_MODE 0x01 | |
72 | #define AX_MONITOR_LINK 0x02 | |
73 | #define AX_MONITOR_MAGIC 0x04 | |
74 | #define AX_MONITOR_HSFS 0x10 | |
75 | ||
76 | /* AX88172 Medium Status Register values */ | |
933a27d3 DH |
77 | #define AX88172_MEDIUM_FD 0x02 |
78 | #define AX88172_MEDIUM_TX 0x04 | |
79 | #define AX88172_MEDIUM_FC 0x10 | |
80 | #define AX88172_MEDIUM_DEFAULT \ | |
81 | ( AX88172_MEDIUM_FD | AX88172_MEDIUM_TX | AX88172_MEDIUM_FC ) | |
2e55cc72 DB |
82 | |
83 | #define AX_MCAST_FILTER_SIZE 8 | |
84 | #define AX_MAX_MCAST 64 | |
85 | ||
2e55cc72 DB |
86 | #define AX_SWRESET_CLEAR 0x00 |
87 | #define AX_SWRESET_RR 0x01 | |
88 | #define AX_SWRESET_RT 0x02 | |
89 | #define AX_SWRESET_PRTE 0x04 | |
90 | #define AX_SWRESET_PRL 0x08 | |
91 | #define AX_SWRESET_BZ 0x10 | |
92 | #define AX_SWRESET_IPRL 0x20 | |
93 | #define AX_SWRESET_IPPD 0x40 | |
94 | ||
95 | #define AX88772_IPG0_DEFAULT 0x15 | |
96 | #define AX88772_IPG1_DEFAULT 0x0c | |
97 | #define AX88772_IPG2_DEFAULT 0x12 | |
98 | ||
933a27d3 DH |
99 | /* AX88772 & AX88178 Medium Mode Register */ |
100 | #define AX_MEDIUM_PF 0x0080 | |
101 | #define AX_MEDIUM_JFE 0x0040 | |
102 | #define AX_MEDIUM_TFC 0x0020 | |
103 | #define AX_MEDIUM_RFC 0x0010 | |
104 | #define AX_MEDIUM_ENCK 0x0008 | |
105 | #define AX_MEDIUM_AC 0x0004 | |
106 | #define AX_MEDIUM_FD 0x0002 | |
107 | #define AX_MEDIUM_GM 0x0001 | |
108 | #define AX_MEDIUM_SM 0x1000 | |
109 | #define AX_MEDIUM_SBP 0x0800 | |
110 | #define AX_MEDIUM_PS 0x0200 | |
111 | #define AX_MEDIUM_RE 0x0100 | |
112 | ||
113 | #define AX88178_MEDIUM_DEFAULT \ | |
114 | (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \ | |
115 | AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \ | |
116 | AX_MEDIUM_RE ) | |
2e55cc72 | 117 | |
933a27d3 DH |
118 | #define AX88772_MEDIUM_DEFAULT \ |
119 | (AX_MEDIUM_FD | AX_MEDIUM_RFC | \ | |
120 | AX_MEDIUM_TFC | AX_MEDIUM_PS | \ | |
121 | AX_MEDIUM_AC | AX_MEDIUM_RE ) | |
122 | ||
123 | /* AX88772 & AX88178 RX_CTL values */ | |
124 | #define AX_RX_CTL_SO 0x0080 | |
125 | #define AX_RX_CTL_AP 0x0020 | |
126 | #define AX_RX_CTL_AM 0x0010 | |
127 | #define AX_RX_CTL_AB 0x0008 | |
128 | #define AX_RX_CTL_SEP 0x0004 | |
129 | #define AX_RX_CTL_AMALL 0x0002 | |
130 | #define AX_RX_CTL_PRO 0x0001 | |
131 | #define AX_RX_CTL_MFB_2048 0x0000 | |
132 | #define AX_RX_CTL_MFB_4096 0x0100 | |
133 | #define AX_RX_CTL_MFB_8192 0x0200 | |
134 | #define AX_RX_CTL_MFB_16384 0x0300 | |
135 | ||
136 | #define AX_DEFAULT_RX_CTL \ | |
137 | (AX_RX_CTL_SO | AX_RX_CTL_AB ) | |
138 | ||
139 | /* GPIO 0 .. 2 toggles */ | |
140 | #define AX_GPIO_GPO0EN 0x01 /* GPIO0 Output enable */ | |
141 | #define AX_GPIO_GPO_0 0x02 /* GPIO0 Output value */ | |
142 | #define AX_GPIO_GPO1EN 0x04 /* GPIO1 Output enable */ | |
143 | #define AX_GPIO_GPO_1 0x08 /* GPIO1 Output value */ | |
144 | #define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */ | |
145 | #define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */ | |
146 | #define AX_GPIO_RESERVED 0x40 /* Reserved */ | |
147 | #define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */ | |
148 | ||
149 | #define AX_EEPROM_MAGIC 0xdeadbeef | |
150 | #define AX88172_EEPROM_LEN 0x40 | |
151 | #define AX88772_EEPROM_LEN 0xff | |
152 | ||
153 | #define PHY_MODE_MARVELL 0x0000 | |
154 | #define MII_MARVELL_LED_CTRL 0x0018 | |
155 | #define MII_MARVELL_STATUS 0x001b | |
156 | #define MII_MARVELL_CTRL 0x0014 | |
157 | ||
158 | #define MARVELL_LED_MANUAL 0x0019 | |
159 | ||
160 | #define MARVELL_STATUS_HWCFG 0x0004 | |
161 | ||
162 | #define MARVELL_CTRL_TXDELAY 0x0002 | |
163 | #define MARVELL_CTRL_RXDELAY 0x0080 | |
2e55cc72 DB |
164 | |
165 | /* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */ | |
48b1be6a | 166 | struct asix_data { |
2e55cc72 | 167 | u8 multi_filter[AX_MCAST_FILTER_SIZE]; |
933a27d3 DH |
168 | u8 phymode; |
169 | u8 ledmode; | |
170 | u8 eeprom_len; | |
2e55cc72 DB |
171 | }; |
172 | ||
173 | struct ax88172_int_data { | |
51bf2976 | 174 | __le16 res1; |
2e55cc72 | 175 | u8 link; |
51bf2976 | 176 | __le16 res2; |
2e55cc72 | 177 | u8 status; |
51bf2976 | 178 | __le16 res3; |
2e55cc72 DB |
179 | } __attribute__ ((packed)); |
180 | ||
48b1be6a | 181 | static int asix_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, |
2e55cc72 DB |
182 | u16 size, void *data) |
183 | { | |
51bf2976 AV |
184 | void *buf; |
185 | int err = -ENOMEM; | |
186 | ||
60b86755 JP |
187 | netdev_dbg(dev->net, "asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", |
188 | cmd, value, index, size); | |
51bf2976 AV |
189 | |
190 | buf = kmalloc(size, GFP_KERNEL); | |
191 | if (!buf) | |
192 | goto out; | |
193 | ||
194 | err = usb_control_msg( | |
2e55cc72 DB |
195 | dev->udev, |
196 | usb_rcvctrlpipe(dev->udev, 0), | |
197 | cmd, | |
198 | USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, | |
199 | value, | |
200 | index, | |
51bf2976 | 201 | buf, |
2e55cc72 DB |
202 | size, |
203 | USB_CTRL_GET_TIMEOUT); | |
94d43363 | 204 | if (err == size) |
51bf2976 | 205 | memcpy(data, buf, size); |
94d43363 RD |
206 | else if (err >= 0) |
207 | err = -EINVAL; | |
51bf2976 AV |
208 | kfree(buf); |
209 | ||
210 | out: | |
211 | return err; | |
2e55cc72 DB |
212 | } |
213 | ||
48b1be6a | 214 | static int asix_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, |
2e55cc72 DB |
215 | u16 size, void *data) |
216 | { | |
51bf2976 AV |
217 | void *buf = NULL; |
218 | int err = -ENOMEM; | |
219 | ||
60b86755 JP |
220 | netdev_dbg(dev->net, "asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", |
221 | cmd, value, index, size); | |
51bf2976 AV |
222 | |
223 | if (data) { | |
224 | buf = kmalloc(size, GFP_KERNEL); | |
225 | if (!buf) | |
226 | goto out; | |
227 | memcpy(buf, data, size); | |
228 | } | |
229 | ||
230 | err = usb_control_msg( | |
2e55cc72 DB |
231 | dev->udev, |
232 | usb_sndctrlpipe(dev->udev, 0), | |
233 | cmd, | |
234 | USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, | |
235 | value, | |
236 | index, | |
51bf2976 | 237 | buf, |
2e55cc72 DB |
238 | size, |
239 | USB_CTRL_SET_TIMEOUT); | |
51bf2976 AV |
240 | kfree(buf); |
241 | ||
242 | out: | |
243 | return err; | |
2e55cc72 DB |
244 | } |
245 | ||
7d12e780 | 246 | static void asix_async_cmd_callback(struct urb *urb) |
2e55cc72 DB |
247 | { |
248 | struct usb_ctrlrequest *req = (struct usb_ctrlrequest *)urb->context; | |
c94cb314 | 249 | int status = urb->status; |
2e55cc72 | 250 | |
c94cb314 | 251 | if (status < 0) |
48b1be6a | 252 | printk(KERN_DEBUG "asix_async_cmd_callback() failed with %d", |
c94cb314 | 253 | status); |
2e55cc72 DB |
254 | |
255 | kfree(req); | |
256 | usb_free_urb(urb); | |
257 | } | |
258 | ||
933a27d3 DH |
259 | static void |
260 | asix_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value, u16 index, | |
261 | u16 size, void *data) | |
262 | { | |
263 | struct usb_ctrlrequest *req; | |
264 | int status; | |
265 | struct urb *urb; | |
266 | ||
60b86755 JP |
267 | netdev_dbg(dev->net, "asix_write_cmd_async() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", |
268 | cmd, value, index, size); | |
933a27d3 | 269 | if ((urb = usb_alloc_urb(0, GFP_ATOMIC)) == NULL) { |
60b86755 | 270 | netdev_err(dev->net, "Error allocating URB in write_cmd_async!\n"); |
933a27d3 DH |
271 | return; |
272 | } | |
273 | ||
274 | if ((req = kmalloc(sizeof(struct usb_ctrlrequest), GFP_ATOMIC)) == NULL) { | |
60b86755 | 275 | netdev_err(dev->net, "Failed to allocate memory for control request\n"); |
933a27d3 DH |
276 | usb_free_urb(urb); |
277 | return; | |
278 | } | |
279 | ||
280 | req->bRequestType = USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE; | |
281 | req->bRequest = cmd; | |
9aa742ef ON |
282 | req->wValue = cpu_to_le16(value); |
283 | req->wIndex = cpu_to_le16(index); | |
284 | req->wLength = cpu_to_le16(size); | |
933a27d3 DH |
285 | |
286 | usb_fill_control_urb(urb, dev->udev, | |
287 | usb_sndctrlpipe(dev->udev, 0), | |
288 | (void *)req, data, size, | |
289 | asix_async_cmd_callback, req); | |
290 | ||
291 | if((status = usb_submit_urb(urb, GFP_ATOMIC)) < 0) { | |
60b86755 JP |
292 | netdev_err(dev->net, "Error submitting the control message: status=%d\n", |
293 | status); | |
933a27d3 DH |
294 | kfree(req); |
295 | usb_free_urb(urb); | |
296 | } | |
297 | } | |
298 | ||
299 | static int asix_rx_fixup(struct usbnet *dev, struct sk_buff *skb) | |
300 | { | |
301 | u8 *head; | |
302 | u32 header; | |
303 | char *packet; | |
304 | struct sk_buff *ax_skb; | |
305 | u16 size; | |
306 | ||
307 | head = (u8 *) skb->data; | |
308 | memcpy(&header, head, sizeof(header)); | |
309 | le32_to_cpus(&header); | |
310 | packet = head + sizeof(header); | |
311 | ||
312 | skb_pull(skb, 4); | |
313 | ||
314 | while (skb->len > 0) { | |
315 | if ((short)(header & 0x0000ffff) != | |
316 | ~((short)((header & 0xffff0000) >> 16))) { | |
60b86755 | 317 | netdev_err(dev->net, "asix_rx_fixup() Bad Header Length\n"); |
933a27d3 DH |
318 | } |
319 | /* get the packet length */ | |
320 | size = (u16) (header & 0x0000ffff); | |
321 | ||
322 | if ((skb->len) - ((size + 1) & 0xfffe) == 0) | |
323 | return 2; | |
324 | if (size > ETH_FRAME_LEN) { | |
60b86755 JP |
325 | netdev_err(dev->net, "asix_rx_fixup() Bad RX Length %d\n", |
326 | size); | |
933a27d3 DH |
327 | return 0; |
328 | } | |
329 | ax_skb = skb_clone(skb, GFP_ATOMIC); | |
330 | if (ax_skb) { | |
331 | ax_skb->len = size; | |
332 | ax_skb->data = packet; | |
27a884dc | 333 | skb_set_tail_pointer(ax_skb, size); |
933a27d3 DH |
334 | usbnet_skb_return(dev, ax_skb); |
335 | } else { | |
336 | return 0; | |
337 | } | |
338 | ||
339 | skb_pull(skb, (size + 1) & 0xfffe); | |
340 | ||
341 | if (skb->len == 0) | |
342 | break; | |
343 | ||
344 | head = (u8 *) skb->data; | |
345 | memcpy(&header, head, sizeof(header)); | |
346 | le32_to_cpus(&header); | |
347 | packet = head + sizeof(header); | |
348 | skb_pull(skb, 4); | |
349 | } | |
350 | ||
351 | if (skb->len < 0) { | |
60b86755 JP |
352 | netdev_err(dev->net, "asix_rx_fixup() Bad SKB Length %d\n", |
353 | skb->len); | |
933a27d3 DH |
354 | return 0; |
355 | } | |
356 | return 1; | |
357 | } | |
358 | ||
359 | static struct sk_buff *asix_tx_fixup(struct usbnet *dev, struct sk_buff *skb, | |
360 | gfp_t flags) | |
361 | { | |
362 | int padlen; | |
363 | int headroom = skb_headroom(skb); | |
364 | int tailroom = skb_tailroom(skb); | |
365 | u32 packet_len; | |
366 | u32 padbytes = 0xffff0000; | |
367 | ||
368 | padlen = ((skb->len + 4) % 512) ? 0 : 4; | |
369 | ||
8e95a202 JP |
370 | if ((!skb_cloned(skb)) && |
371 | ((headroom + tailroom) >= (4 + padlen))) { | |
933a27d3 DH |
372 | if ((headroom < 4) || (tailroom < padlen)) { |
373 | skb->data = memmove(skb->head + 4, skb->data, skb->len); | |
27a884dc | 374 | skb_set_tail_pointer(skb, skb->len); |
933a27d3 DH |
375 | } |
376 | } else { | |
377 | struct sk_buff *skb2; | |
378 | skb2 = skb_copy_expand(skb, 4, padlen, flags); | |
379 | dev_kfree_skb_any(skb); | |
380 | skb = skb2; | |
381 | if (!skb) | |
382 | return NULL; | |
383 | } | |
384 | ||
385 | skb_push(skb, 4); | |
386 | packet_len = (((skb->len - 4) ^ 0x0000ffff) << 16) + (skb->len - 4); | |
57e4f041 | 387 | cpu_to_le32s(&packet_len); |
27d7ff46 | 388 | skb_copy_to_linear_data(skb, &packet_len, sizeof(packet_len)); |
933a27d3 DH |
389 | |
390 | if ((skb->len % 512) == 0) { | |
57e4f041 | 391 | cpu_to_le32s(&padbytes); |
27a884dc | 392 | memcpy(skb_tail_pointer(skb), &padbytes, sizeof(padbytes)); |
933a27d3 DH |
393 | skb_put(skb, sizeof(padbytes)); |
394 | } | |
395 | return skb; | |
396 | } | |
397 | ||
398 | static void asix_status(struct usbnet *dev, struct urb *urb) | |
399 | { | |
400 | struct ax88172_int_data *event; | |
401 | int link; | |
402 | ||
403 | if (urb->actual_length < 8) | |
404 | return; | |
405 | ||
406 | event = urb->transfer_buffer; | |
407 | link = event->link & 0x01; | |
408 | if (netif_carrier_ok(dev->net) != link) { | |
409 | if (link) { | |
410 | netif_carrier_on(dev->net); | |
411 | usbnet_defer_kevent (dev, EVENT_LINK_RESET ); | |
412 | } else | |
413 | netif_carrier_off(dev->net); | |
60b86755 | 414 | netdev_dbg(dev->net, "Link Status is: %d\n", link); |
933a27d3 DH |
415 | } |
416 | } | |
417 | ||
48b1be6a DH |
418 | static inline int asix_set_sw_mii(struct usbnet *dev) |
419 | { | |
420 | int ret; | |
421 | ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL); | |
422 | if (ret < 0) | |
60b86755 | 423 | netdev_err(dev->net, "Failed to enable software MII access\n"); |
48b1be6a DH |
424 | return ret; |
425 | } | |
426 | ||
427 | static inline int asix_set_hw_mii(struct usbnet *dev) | |
428 | { | |
429 | int ret; | |
430 | ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL); | |
431 | if (ret < 0) | |
60b86755 | 432 | netdev_err(dev->net, "Failed to enable hardware MII access\n"); |
48b1be6a DH |
433 | return ret; |
434 | } | |
435 | ||
933a27d3 | 436 | static inline int asix_get_phy_addr(struct usbnet *dev) |
48b1be6a | 437 | { |
51bf2976 AV |
438 | u8 buf[2]; |
439 | int ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, 0, 0, 2, buf); | |
48b1be6a | 440 | |
60b86755 | 441 | netdev_dbg(dev->net, "asix_get_phy_addr()\n"); |
933a27d3 | 442 | |
51bf2976 | 443 | if (ret < 0) { |
60b86755 | 444 | netdev_err(dev->net, "Error reading PHYID register: %02x\n", ret); |
51bf2976 | 445 | goto out; |
48b1be6a | 446 | } |
60b86755 JP |
447 | netdev_dbg(dev->net, "asix_get_phy_addr() returning 0x%04x\n", |
448 | *((__le16 *)buf)); | |
51bf2976 AV |
449 | ret = buf[1]; |
450 | ||
451 | out: | |
48b1be6a DH |
452 | return ret; |
453 | } | |
454 | ||
455 | static int asix_sw_reset(struct usbnet *dev, u8 flags) | |
456 | { | |
457 | int ret; | |
458 | ||
459 | ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL); | |
460 | if (ret < 0) | |
60b86755 | 461 | netdev_err(dev->net, "Failed to send software reset: %02x\n", ret); |
933a27d3 DH |
462 | |
463 | return ret; | |
464 | } | |
48b1be6a | 465 | |
933a27d3 DH |
466 | static u16 asix_read_rx_ctl(struct usbnet *dev) |
467 | { | |
51bf2976 AV |
468 | __le16 v; |
469 | int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, &v); | |
933a27d3 | 470 | |
51bf2976 | 471 | if (ret < 0) { |
60b86755 | 472 | netdev_err(dev->net, "Error reading RX_CTL register: %02x\n", ret); |
51bf2976 | 473 | goto out; |
933a27d3 | 474 | } |
51bf2976 AV |
475 | ret = le16_to_cpu(v); |
476 | out: | |
48b1be6a DH |
477 | return ret; |
478 | } | |
479 | ||
480 | static int asix_write_rx_ctl(struct usbnet *dev, u16 mode) | |
481 | { | |
482 | int ret; | |
483 | ||
60b86755 | 484 | netdev_dbg(dev->net, "asix_write_rx_ctl() - mode = 0x%04x\n", mode); |
48b1be6a DH |
485 | ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL); |
486 | if (ret < 0) | |
60b86755 JP |
487 | netdev_err(dev->net, "Failed to write RX_CTL mode to 0x%04x: %02x\n", |
488 | mode, ret); | |
48b1be6a DH |
489 | |
490 | return ret; | |
491 | } | |
492 | ||
933a27d3 | 493 | static u16 asix_read_medium_status(struct usbnet *dev) |
2e55cc72 | 494 | { |
51bf2976 AV |
495 | __le16 v; |
496 | int ret = asix_read_cmd(dev, AX_CMD_READ_MEDIUM_STATUS, 0, 0, 2, &v); | |
2e55cc72 | 497 | |
51bf2976 | 498 | if (ret < 0) { |
60b86755 JP |
499 | netdev_err(dev->net, "Error reading Medium Status register: %02x\n", |
500 | ret); | |
51bf2976 | 501 | goto out; |
2e55cc72 | 502 | } |
51bf2976 AV |
503 | ret = le16_to_cpu(v); |
504 | out: | |
933a27d3 | 505 | return ret; |
2e55cc72 DB |
506 | } |
507 | ||
933a27d3 | 508 | static int asix_write_medium_mode(struct usbnet *dev, u16 mode) |
2e55cc72 | 509 | { |
933a27d3 | 510 | int ret; |
2e55cc72 | 511 | |
60b86755 | 512 | netdev_dbg(dev->net, "asix_write_medium_mode() - mode = 0x%04x\n", mode); |
933a27d3 DH |
513 | ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode, 0, 0, NULL); |
514 | if (ret < 0) | |
60b86755 JP |
515 | netdev_err(dev->net, "Failed to write Medium Mode mode to 0x%04x: %02x\n", |
516 | mode, ret); | |
2e55cc72 | 517 | |
933a27d3 DH |
518 | return ret; |
519 | } | |
2e55cc72 | 520 | |
933a27d3 DH |
521 | static int asix_write_gpio(struct usbnet *dev, u16 value, int sleep) |
522 | { | |
523 | int ret; | |
2e55cc72 | 524 | |
60b86755 | 525 | netdev_dbg(dev->net, "asix_write_gpio() - value = 0x%04x\n", value); |
933a27d3 DH |
526 | ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, value, 0, 0, NULL); |
527 | if (ret < 0) | |
60b86755 JP |
528 | netdev_err(dev->net, "Failed to write GPIO value 0x%04x: %02x\n", |
529 | value, ret); | |
2e55cc72 | 530 | |
933a27d3 DH |
531 | if (sleep) |
532 | msleep(sleep); | |
533 | ||
534 | return ret; | |
2e55cc72 DB |
535 | } |
536 | ||
933a27d3 DH |
537 | /* |
538 | * AX88772 & AX88178 have a 16-bit RX_CTL value | |
539 | */ | |
48b1be6a | 540 | static void asix_set_multicast(struct net_device *net) |
2e55cc72 DB |
541 | { |
542 | struct usbnet *dev = netdev_priv(net); | |
48b1be6a | 543 | struct asix_data *data = (struct asix_data *)&dev->data; |
933a27d3 | 544 | u16 rx_ctl = AX_DEFAULT_RX_CTL; |
2e55cc72 DB |
545 | |
546 | if (net->flags & IFF_PROMISC) { | |
933a27d3 | 547 | rx_ctl |= AX_RX_CTL_PRO; |
8e95a202 | 548 | } else if (net->flags & IFF_ALLMULTI || |
4cd24eaf | 549 | netdev_mc_count(net) > AX_MAX_MCAST) { |
933a27d3 | 550 | rx_ctl |= AX_RX_CTL_AMALL; |
4cd24eaf | 551 | } else if (netdev_mc_empty(net)) { |
2e55cc72 DB |
552 | /* just broadcast and directed */ |
553 | } else { | |
554 | /* We use the 20 byte dev->data | |
555 | * for our 8 byte filter buffer | |
556 | * to avoid allocating memory that | |
557 | * is tricky to free later */ | |
558 | struct dev_mc_list *mc_list = net->mc_list; | |
559 | u32 crc_bits; | |
560 | int i; | |
561 | ||
562 | memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE); | |
563 | ||
564 | /* Build the multicast hash filter. */ | |
4cd24eaf | 565 | for (i = 0; i < netdev_mc_count(net); i++) { |
2e55cc72 DB |
566 | crc_bits = |
567 | ether_crc(ETH_ALEN, | |
568 | mc_list->dmi_addr) >> 26; | |
569 | data->multi_filter[crc_bits >> 3] |= | |
570 | 1 << (crc_bits & 7); | |
571 | mc_list = mc_list->next; | |
572 | } | |
573 | ||
48b1be6a | 574 | asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0, |
2e55cc72 DB |
575 | AX_MCAST_FILTER_SIZE, data->multi_filter); |
576 | ||
933a27d3 | 577 | rx_ctl |= AX_RX_CTL_AM; |
2e55cc72 DB |
578 | } |
579 | ||
48b1be6a | 580 | asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL); |
2e55cc72 DB |
581 | } |
582 | ||
48b1be6a | 583 | static int asix_mdio_read(struct net_device *netdev, int phy_id, int loc) |
2e55cc72 DB |
584 | { |
585 | struct usbnet *dev = netdev_priv(netdev); | |
51bf2976 | 586 | __le16 res; |
2e55cc72 | 587 | |
a9fc6338 | 588 | mutex_lock(&dev->phy_mutex); |
48b1be6a DH |
589 | asix_set_sw_mii(dev); |
590 | asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, | |
51bf2976 | 591 | (__u16)loc, 2, &res); |
48b1be6a | 592 | asix_set_hw_mii(dev); |
a9fc6338 | 593 | mutex_unlock(&dev->phy_mutex); |
2e55cc72 | 594 | |
60b86755 JP |
595 | netdev_dbg(dev->net, "asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n", |
596 | phy_id, loc, le16_to_cpu(res)); | |
2e55cc72 | 597 | |
51bf2976 | 598 | return le16_to_cpu(res); |
2e55cc72 DB |
599 | } |
600 | ||
601 | static void | |
48b1be6a | 602 | asix_mdio_write(struct net_device *netdev, int phy_id, int loc, int val) |
2e55cc72 DB |
603 | { |
604 | struct usbnet *dev = netdev_priv(netdev); | |
51bf2976 | 605 | __le16 res = cpu_to_le16(val); |
2e55cc72 | 606 | |
60b86755 JP |
607 | netdev_dbg(dev->net, "asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n", |
608 | phy_id, loc, val); | |
a9fc6338 | 609 | mutex_lock(&dev->phy_mutex); |
48b1be6a | 610 | asix_set_sw_mii(dev); |
51bf2976 | 611 | asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, &res); |
48b1be6a | 612 | asix_set_hw_mii(dev); |
a9fc6338 | 613 | mutex_unlock(&dev->phy_mutex); |
2e55cc72 DB |
614 | } |
615 | ||
933a27d3 DH |
616 | /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */ |
617 | static u32 asix_get_phyid(struct usbnet *dev) | |
2e55cc72 | 618 | { |
933a27d3 DH |
619 | int phy_reg; |
620 | u32 phy_id; | |
2e55cc72 | 621 | |
933a27d3 DH |
622 | phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1); |
623 | if (phy_reg < 0) | |
624 | return 0; | |
2e55cc72 | 625 | |
933a27d3 | 626 | phy_id = (phy_reg & 0xffff) << 16; |
2e55cc72 | 627 | |
933a27d3 DH |
628 | phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2); |
629 | if (phy_reg < 0) | |
630 | return 0; | |
631 | ||
632 | phy_id |= (phy_reg & 0xffff); | |
633 | ||
634 | return phy_id; | |
2e55cc72 DB |
635 | } |
636 | ||
637 | static void | |
48b1be6a | 638 | asix_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) |
2e55cc72 DB |
639 | { |
640 | struct usbnet *dev = netdev_priv(net); | |
641 | u8 opt; | |
642 | ||
48b1be6a | 643 | if (asix_read_cmd(dev, AX_CMD_READ_MONITOR_MODE, 0, 0, 1, &opt) < 0) { |
2e55cc72 DB |
644 | wolinfo->supported = 0; |
645 | wolinfo->wolopts = 0; | |
646 | return; | |
647 | } | |
648 | wolinfo->supported = WAKE_PHY | WAKE_MAGIC; | |
649 | wolinfo->wolopts = 0; | |
650 | if (opt & AX_MONITOR_MODE) { | |
651 | if (opt & AX_MONITOR_LINK) | |
652 | wolinfo->wolopts |= WAKE_PHY; | |
653 | if (opt & AX_MONITOR_MAGIC) | |
654 | wolinfo->wolopts |= WAKE_MAGIC; | |
655 | } | |
656 | } | |
657 | ||
658 | static int | |
48b1be6a | 659 | asix_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) |
2e55cc72 DB |
660 | { |
661 | struct usbnet *dev = netdev_priv(net); | |
662 | u8 opt = 0; | |
2e55cc72 DB |
663 | |
664 | if (wolinfo->wolopts & WAKE_PHY) | |
665 | opt |= AX_MONITOR_LINK; | |
666 | if (wolinfo->wolopts & WAKE_MAGIC) | |
667 | opt |= AX_MONITOR_MAGIC; | |
668 | if (opt != 0) | |
669 | opt |= AX_MONITOR_MODE; | |
670 | ||
48b1be6a | 671 | if (asix_write_cmd(dev, AX_CMD_WRITE_MONITOR_MODE, |
51bf2976 | 672 | opt, 0, 0, NULL) < 0) |
2e55cc72 DB |
673 | return -EINVAL; |
674 | ||
675 | return 0; | |
676 | } | |
677 | ||
48b1be6a | 678 | static int asix_get_eeprom_len(struct net_device *net) |
2e55cc72 | 679 | { |
933a27d3 DH |
680 | struct usbnet *dev = netdev_priv(net); |
681 | struct asix_data *data = (struct asix_data *)&dev->data; | |
682 | ||
683 | return data->eeprom_len; | |
2e55cc72 DB |
684 | } |
685 | ||
48b1be6a | 686 | static int asix_get_eeprom(struct net_device *net, |
2e55cc72 DB |
687 | struct ethtool_eeprom *eeprom, u8 *data) |
688 | { | |
689 | struct usbnet *dev = netdev_priv(net); | |
51bf2976 | 690 | __le16 *ebuf = (__le16 *)data; |
2e55cc72 DB |
691 | int i; |
692 | ||
693 | /* Crude hack to ensure that we don't overwrite memory | |
694 | * if an odd length is supplied | |
695 | */ | |
696 | if (eeprom->len % 2) | |
697 | return -EINVAL; | |
698 | ||
699 | eeprom->magic = AX_EEPROM_MAGIC; | |
700 | ||
701 | /* ax8817x returns 2 bytes from eeprom on read */ | |
702 | for (i=0; i < eeprom->len / 2; i++) { | |
48b1be6a | 703 | if (asix_read_cmd(dev, AX_CMD_READ_EEPROM, |
2e55cc72 DB |
704 | eeprom->offset + i, 0, 2, &ebuf[i]) < 0) |
705 | return -EINVAL; | |
706 | } | |
707 | return 0; | |
708 | } | |
709 | ||
48b1be6a | 710 | static void asix_get_drvinfo (struct net_device *net, |
2e55cc72 DB |
711 | struct ethtool_drvinfo *info) |
712 | { | |
933a27d3 DH |
713 | struct usbnet *dev = netdev_priv(net); |
714 | struct asix_data *data = (struct asix_data *)&dev->data; | |
715 | ||
2e55cc72 DB |
716 | /* Inherit standard device info */ |
717 | usbnet_get_drvinfo(net, info); | |
933a27d3 DH |
718 | strncpy (info->driver, driver_name, sizeof info->driver); |
719 | strncpy (info->version, DRIVER_VERSION, sizeof info->version); | |
720 | info->eedump_len = data->eeprom_len; | |
2e55cc72 DB |
721 | } |
722 | ||
933a27d3 DH |
723 | static u32 asix_get_link(struct net_device *net) |
724 | { | |
725 | struct usbnet *dev = netdev_priv(net); | |
726 | ||
727 | return mii_link_ok(&dev->mii); | |
728 | } | |
729 | ||
730 | static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd) | |
731 | { | |
732 | struct usbnet *dev = netdev_priv(net); | |
733 | ||
734 | return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); | |
735 | } | |
736 | ||
737 | /* We need to override some ethtool_ops so we require our | |
738 | own structure so we don't interfere with other usbnet | |
739 | devices that may be connected at the same time. */ | |
0fc0b732 | 740 | static const struct ethtool_ops ax88172_ethtool_ops = { |
933a27d3 DH |
741 | .get_drvinfo = asix_get_drvinfo, |
742 | .get_link = asix_get_link, | |
933a27d3 | 743 | .get_msglevel = usbnet_get_msglevel, |
2e55cc72 | 744 | .set_msglevel = usbnet_set_msglevel, |
48b1be6a DH |
745 | .get_wol = asix_get_wol, |
746 | .set_wol = asix_set_wol, | |
747 | .get_eeprom_len = asix_get_eeprom_len, | |
748 | .get_eeprom = asix_get_eeprom, | |
c41286fd AB |
749 | .get_settings = usbnet_get_settings, |
750 | .set_settings = usbnet_set_settings, | |
751 | .nway_reset = usbnet_nway_reset, | |
2e55cc72 DB |
752 | }; |
753 | ||
933a27d3 | 754 | static void ax88172_set_multicast(struct net_device *net) |
2e55cc72 DB |
755 | { |
756 | struct usbnet *dev = netdev_priv(net); | |
933a27d3 DH |
757 | struct asix_data *data = (struct asix_data *)&dev->data; |
758 | u8 rx_ctl = 0x8c; | |
2e55cc72 | 759 | |
933a27d3 DH |
760 | if (net->flags & IFF_PROMISC) { |
761 | rx_ctl |= 0x01; | |
8e95a202 | 762 | } else if (net->flags & IFF_ALLMULTI || |
4cd24eaf | 763 | netdev_mc_count(net) > AX_MAX_MCAST) { |
933a27d3 | 764 | rx_ctl |= 0x02; |
4cd24eaf | 765 | } else if (netdev_mc_empty(net)) { |
933a27d3 DH |
766 | /* just broadcast and directed */ |
767 | } else { | |
768 | /* We use the 20 byte dev->data | |
769 | * for our 8 byte filter buffer | |
770 | * to avoid allocating memory that | |
771 | * is tricky to free later */ | |
772 | struct dev_mc_list *mc_list = net->mc_list; | |
773 | u32 crc_bits; | |
774 | int i; | |
775 | ||
776 | memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE); | |
777 | ||
778 | /* Build the multicast hash filter. */ | |
4cd24eaf | 779 | for (i = 0; i < netdev_mc_count(net); i++) { |
933a27d3 DH |
780 | crc_bits = |
781 | ether_crc(ETH_ALEN, | |
782 | mc_list->dmi_addr) >> 26; | |
783 | data->multi_filter[crc_bits >> 3] |= | |
784 | 1 << (crc_bits & 7); | |
785 | mc_list = mc_list->next; | |
786 | } | |
787 | ||
788 | asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0, | |
789 | AX_MCAST_FILTER_SIZE, data->multi_filter); | |
790 | ||
791 | rx_ctl |= 0x10; | |
792 | } | |
793 | ||
794 | asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL); | |
795 | } | |
796 | ||
797 | static int ax88172_link_reset(struct usbnet *dev) | |
798 | { | |
799 | u8 mode; | |
800 | struct ethtool_cmd ecmd; | |
801 | ||
802 | mii_check_media(&dev->mii, 1, 1); | |
803 | mii_ethtool_gset(&dev->mii, &ecmd); | |
804 | mode = AX88172_MEDIUM_DEFAULT; | |
805 | ||
806 | if (ecmd.duplex != DUPLEX_FULL) | |
807 | mode |= ~AX88172_MEDIUM_FD; | |
808 | ||
60b86755 JP |
809 | netdev_dbg(dev->net, "ax88172_link_reset() speed: %d duplex: %d setting mode to 0x%04x\n", |
810 | ecmd.speed, ecmd.duplex, mode); | |
933a27d3 DH |
811 | |
812 | asix_write_medium_mode(dev, mode); | |
813 | ||
814 | return 0; | |
2e55cc72 DB |
815 | } |
816 | ||
1703338c SH |
817 | static const struct net_device_ops ax88172_netdev_ops = { |
818 | .ndo_open = usbnet_open, | |
819 | .ndo_stop = usbnet_stop, | |
820 | .ndo_start_xmit = usbnet_start_xmit, | |
821 | .ndo_tx_timeout = usbnet_tx_timeout, | |
822 | .ndo_change_mtu = usbnet_change_mtu, | |
823 | .ndo_set_mac_address = eth_mac_addr, | |
824 | .ndo_validate_addr = eth_validate_addr, | |
825 | .ndo_do_ioctl = asix_ioctl, | |
826 | .ndo_set_multicast_list = ax88172_set_multicast, | |
827 | }; | |
828 | ||
48b1be6a | 829 | static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf) |
2e55cc72 DB |
830 | { |
831 | int ret = 0; | |
51bf2976 | 832 | u8 buf[ETH_ALEN]; |
2e55cc72 DB |
833 | int i; |
834 | unsigned long gpio_bits = dev->driver_info->data; | |
933a27d3 DH |
835 | struct asix_data *data = (struct asix_data *)&dev->data; |
836 | ||
837 | data->eeprom_len = AX88172_EEPROM_LEN; | |
2e55cc72 DB |
838 | |
839 | usbnet_get_endpoints(dev,intf); | |
840 | ||
2e55cc72 DB |
841 | /* Toggle the GPIOs in a manufacturer/model specific way */ |
842 | for (i = 2; i >= 0; i--) { | |
48b1be6a | 843 | if ((ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, |
2e55cc72 | 844 | (gpio_bits >> (i * 8)) & 0xff, 0, 0, |
51bf2976 AV |
845 | NULL)) < 0) |
846 | goto out; | |
2e55cc72 DB |
847 | msleep(5); |
848 | } | |
849 | ||
933a27d3 | 850 | if ((ret = asix_write_rx_ctl(dev, 0x80)) < 0) |
51bf2976 | 851 | goto out; |
2e55cc72 DB |
852 | |
853 | /* Get the MAC address */ | |
933a27d3 | 854 | if ((ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, |
51bf2976 | 855 | 0, 0, ETH_ALEN, buf)) < 0) { |
2e55cc72 | 856 | dbg("read AX_CMD_READ_NODE_ID failed: %d", ret); |
51bf2976 | 857 | goto out; |
2e55cc72 DB |
858 | } |
859 | memcpy(dev->net->dev_addr, buf, ETH_ALEN); | |
860 | ||
2e55cc72 DB |
861 | /* Initialize MII structure */ |
862 | dev->mii.dev = dev->net; | |
48b1be6a DH |
863 | dev->mii.mdio_read = asix_mdio_read; |
864 | dev->mii.mdio_write = asix_mdio_write; | |
2e55cc72 DB |
865 | dev->mii.phy_id_mask = 0x3f; |
866 | dev->mii.reg_num_mask = 0x1f; | |
933a27d3 | 867 | dev->mii.phy_id = asix_get_phy_addr(dev); |
2e55cc72 | 868 | |
1703338c | 869 | dev->net->netdev_ops = &ax88172_netdev_ops; |
48b1be6a | 870 | dev->net->ethtool_ops = &ax88172_ethtool_ops; |
2e55cc72 | 871 | |
933a27d3 DH |
872 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET); |
873 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, | |
2e55cc72 DB |
874 | ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); |
875 | mii_nway_restart(&dev->mii); | |
876 | ||
877 | return 0; | |
51bf2976 AV |
878 | |
879 | out: | |
2e55cc72 DB |
880 | return ret; |
881 | } | |
882 | ||
0fc0b732 | 883 | static const struct ethtool_ops ax88772_ethtool_ops = { |
48b1be6a | 884 | .get_drvinfo = asix_get_drvinfo, |
933a27d3 | 885 | .get_link = asix_get_link, |
2e55cc72 DB |
886 | .get_msglevel = usbnet_get_msglevel, |
887 | .set_msglevel = usbnet_set_msglevel, | |
48b1be6a DH |
888 | .get_wol = asix_get_wol, |
889 | .set_wol = asix_set_wol, | |
890 | .get_eeprom_len = asix_get_eeprom_len, | |
891 | .get_eeprom = asix_get_eeprom, | |
c41286fd AB |
892 | .get_settings = usbnet_get_settings, |
893 | .set_settings = usbnet_set_settings, | |
894 | .nway_reset = usbnet_nway_reset, | |
2e55cc72 DB |
895 | }; |
896 | ||
933a27d3 DH |
897 | static int ax88772_link_reset(struct usbnet *dev) |
898 | { | |
899 | u16 mode; | |
900 | struct ethtool_cmd ecmd; | |
901 | ||
902 | mii_check_media(&dev->mii, 1, 1); | |
903 | mii_ethtool_gset(&dev->mii, &ecmd); | |
904 | mode = AX88772_MEDIUM_DEFAULT; | |
905 | ||
906 | if (ecmd.speed != SPEED_100) | |
907 | mode &= ~AX_MEDIUM_PS; | |
908 | ||
909 | if (ecmd.duplex != DUPLEX_FULL) | |
910 | mode &= ~AX_MEDIUM_FD; | |
911 | ||
60b86755 JP |
912 | netdev_dbg(dev->net, "ax88772_link_reset() speed: %d duplex: %d setting mode to 0x%04x\n", |
913 | ecmd.speed, ecmd.duplex, mode); | |
933a27d3 DH |
914 | |
915 | asix_write_medium_mode(dev, mode); | |
916 | ||
917 | return 0; | |
918 | } | |
919 | ||
1703338c SH |
920 | static const struct net_device_ops ax88772_netdev_ops = { |
921 | .ndo_open = usbnet_open, | |
922 | .ndo_stop = usbnet_stop, | |
923 | .ndo_start_xmit = usbnet_start_xmit, | |
924 | .ndo_tx_timeout = usbnet_tx_timeout, | |
925 | .ndo_change_mtu = usbnet_change_mtu, | |
926 | .ndo_set_mac_address = eth_mac_addr, | |
927 | .ndo_validate_addr = eth_validate_addr, | |
928 | .ndo_do_ioctl = asix_ioctl, | |
929 | .ndo_set_multicast_list = asix_set_multicast, | |
930 | }; | |
931 | ||
2e55cc72 DB |
932 | static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf) |
933 | { | |
d0ffff8f | 934 | int ret, embd_phy; |
933a27d3 DH |
935 | u16 rx_ctl; |
936 | struct asix_data *data = (struct asix_data *)&dev->data; | |
51bf2976 | 937 | u8 buf[ETH_ALEN]; |
933a27d3 DH |
938 | u32 phyid; |
939 | ||
940 | data->eeprom_len = AX88772_EEPROM_LEN; | |
2e55cc72 DB |
941 | |
942 | usbnet_get_endpoints(dev,intf); | |
943 | ||
933a27d3 DH |
944 | if ((ret = asix_write_gpio(dev, |
945 | AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5)) < 0) | |
51bf2976 | 946 | goto out; |
2e55cc72 | 947 | |
d0ffff8f AS |
948 | /* 0x10 is the phy id of the embedded 10/100 ethernet phy */ |
949 | embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0); | |
48b1be6a | 950 | if ((ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, |
51bf2976 | 951 | embd_phy, 0, 0, NULL)) < 0) { |
2e55cc72 | 952 | dbg("Select PHY #1 failed: %d", ret); |
51bf2976 | 953 | goto out; |
2e55cc72 DB |
954 | } |
955 | ||
d0ffff8f | 956 | if ((ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL)) < 0) |
51bf2976 | 957 | goto out; |
2e55cc72 DB |
958 | |
959 | msleep(150); | |
48b1be6a | 960 | if ((ret = asix_sw_reset(dev, AX_SWRESET_CLEAR)) < 0) |
51bf2976 | 961 | goto out; |
2e55cc72 DB |
962 | |
963 | msleep(150); | |
d0ffff8f AS |
964 | if (embd_phy) { |
965 | if ((ret = asix_sw_reset(dev, AX_SWRESET_IPRL)) < 0) | |
51bf2976 | 966 | goto out; |
d0ffff8f AS |
967 | } |
968 | else { | |
969 | if ((ret = asix_sw_reset(dev, AX_SWRESET_PRTE)) < 0) | |
51bf2976 | 970 | goto out; |
d0ffff8f | 971 | } |
2e55cc72 DB |
972 | |
973 | msleep(150); | |
933a27d3 DH |
974 | rx_ctl = asix_read_rx_ctl(dev); |
975 | dbg("RX_CTL is 0x%04x after software reset", rx_ctl); | |
976 | if ((ret = asix_write_rx_ctl(dev, 0x0000)) < 0) | |
51bf2976 | 977 | goto out; |
2e55cc72 | 978 | |
933a27d3 DH |
979 | rx_ctl = asix_read_rx_ctl(dev); |
980 | dbg("RX_CTL is 0x%04x setting to 0x0000", rx_ctl); | |
981 | ||
2e55cc72 | 982 | /* Get the MAC address */ |
933a27d3 | 983 | if ((ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, |
2e55cc72 DB |
984 | 0, 0, ETH_ALEN, buf)) < 0) { |
985 | dbg("Failed to read MAC address: %d", ret); | |
51bf2976 | 986 | goto out; |
2e55cc72 DB |
987 | } |
988 | memcpy(dev->net->dev_addr, buf, ETH_ALEN); | |
989 | ||
2e55cc72 DB |
990 | /* Initialize MII structure */ |
991 | dev->mii.dev = dev->net; | |
48b1be6a DH |
992 | dev->mii.mdio_read = asix_mdio_read; |
993 | dev->mii.mdio_write = asix_mdio_write; | |
933a27d3 DH |
994 | dev->mii.phy_id_mask = 0x1f; |
995 | dev->mii.reg_num_mask = 0x1f; | |
933a27d3 DH |
996 | dev->mii.phy_id = asix_get_phy_addr(dev); |
997 | ||
998 | phyid = asix_get_phyid(dev); | |
999 | dbg("PHYID=0x%08x", phyid); | |
2e55cc72 | 1000 | |
48b1be6a | 1001 | if ((ret = asix_sw_reset(dev, AX_SWRESET_PRL)) < 0) |
51bf2976 | 1002 | goto out; |
2e55cc72 | 1003 | |
2e55cc72 | 1004 | msleep(150); |
48b1be6a DH |
1005 | |
1006 | if ((ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL)) < 0) | |
51bf2976 | 1007 | goto out; |
2e55cc72 | 1008 | |
48b1be6a | 1009 | msleep(150); |
2e55cc72 | 1010 | |
1703338c | 1011 | dev->net->netdev_ops = &ax88772_netdev_ops; |
2e55cc72 DB |
1012 | dev->net->ethtool_ops = &ax88772_ethtool_ops; |
1013 | ||
933a27d3 DH |
1014 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET); |
1015 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, | |
2e55cc72 DB |
1016 | ADVERTISE_ALL | ADVERTISE_CSMA); |
1017 | mii_nway_restart(&dev->mii); | |
1018 | ||
933a27d3 | 1019 | if ((ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT)) < 0) |
51bf2976 | 1020 | goto out; |
2e55cc72 | 1021 | |
48b1be6a | 1022 | if ((ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0, |
2e55cc72 | 1023 | AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, |
51bf2976 | 1024 | AX88772_IPG2_DEFAULT, 0, NULL)) < 0) { |
2e55cc72 | 1025 | dbg("Write IPG,IPG1,IPG2 failed: %d", ret); |
51bf2976 | 1026 | goto out; |
2e55cc72 | 1027 | } |
2e55cc72 DB |
1028 | |
1029 | /* Set RX_CTL to default values with 2k buffer, and enable cactus */ | |
933a27d3 | 1030 | if ((ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL)) < 0) |
51bf2976 | 1031 | goto out; |
2e55cc72 | 1032 | |
933a27d3 DH |
1033 | rx_ctl = asix_read_rx_ctl(dev); |
1034 | dbg("RX_CTL is 0x%04x after all initializations", rx_ctl); | |
1035 | ||
1036 | rx_ctl = asix_read_medium_status(dev); | |
1037 | dbg("Medium Status is 0x%04x after all initializations", rx_ctl); | |
1038 | ||
2e55cc72 DB |
1039 | /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ |
1040 | if (dev->driver_info->flags & FLAG_FRAMING_AX) { | |
1041 | /* hard_mtu is still the default - the device does not support | |
1042 | jumbo eth frames */ | |
1043 | dev->rx_urb_size = 2048; | |
1044 | } | |
2e55cc72 DB |
1045 | return 0; |
1046 | ||
51bf2976 | 1047 | out: |
2e55cc72 DB |
1048 | return ret; |
1049 | } | |
1050 | ||
933a27d3 DH |
1051 | static struct ethtool_ops ax88178_ethtool_ops = { |
1052 | .get_drvinfo = asix_get_drvinfo, | |
1053 | .get_link = asix_get_link, | |
933a27d3 DH |
1054 | .get_msglevel = usbnet_get_msglevel, |
1055 | .set_msglevel = usbnet_set_msglevel, | |
1056 | .get_wol = asix_get_wol, | |
1057 | .set_wol = asix_set_wol, | |
1058 | .get_eeprom_len = asix_get_eeprom_len, | |
1059 | .get_eeprom = asix_get_eeprom, | |
c41286fd AB |
1060 | .get_settings = usbnet_get_settings, |
1061 | .set_settings = usbnet_set_settings, | |
1062 | .nway_reset = usbnet_nway_reset, | |
933a27d3 DH |
1063 | }; |
1064 | ||
1065 | static int marvell_phy_init(struct usbnet *dev) | |
2e55cc72 | 1066 | { |
933a27d3 DH |
1067 | struct asix_data *data = (struct asix_data *)&dev->data; |
1068 | u16 reg; | |
2e55cc72 | 1069 | |
60b86755 | 1070 | netdev_dbg(dev->net, "marvell_phy_init()\n"); |
2e55cc72 | 1071 | |
933a27d3 | 1072 | reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS); |
60b86755 | 1073 | netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg); |
2e55cc72 | 1074 | |
933a27d3 DH |
1075 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL, |
1076 | MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY); | |
2e55cc72 | 1077 | |
933a27d3 DH |
1078 | if (data->ledmode) { |
1079 | reg = asix_mdio_read(dev->net, dev->mii.phy_id, | |
1080 | MII_MARVELL_LED_CTRL); | |
60b86755 | 1081 | netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg); |
2e55cc72 | 1082 | |
933a27d3 DH |
1083 | reg &= 0xf8ff; |
1084 | reg |= (1 + 0x0100); | |
1085 | asix_mdio_write(dev->net, dev->mii.phy_id, | |
1086 | MII_MARVELL_LED_CTRL, reg); | |
2e55cc72 | 1087 | |
933a27d3 DH |
1088 | reg = asix_mdio_read(dev->net, dev->mii.phy_id, |
1089 | MII_MARVELL_LED_CTRL); | |
60b86755 | 1090 | netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg); |
933a27d3 DH |
1091 | reg &= 0xfc0f; |
1092 | } | |
2e55cc72 | 1093 | |
933a27d3 DH |
1094 | return 0; |
1095 | } | |
1096 | ||
1097 | static int marvell_led_status(struct usbnet *dev, u16 speed) | |
1098 | { | |
1099 | u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL); | |
1100 | ||
60b86755 | 1101 | netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg); |
933a27d3 DH |
1102 | |
1103 | /* Clear out the center LED bits - 0x03F0 */ | |
1104 | reg &= 0xfc0f; | |
1105 | ||
1106 | switch (speed) { | |
1107 | case SPEED_1000: | |
1108 | reg |= 0x03e0; | |
1109 | break; | |
1110 | case SPEED_100: | |
1111 | reg |= 0x03b0; | |
1112 | break; | |
1113 | default: | |
1114 | reg |= 0x02f0; | |
2e55cc72 DB |
1115 | } |
1116 | ||
60b86755 | 1117 | netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg); |
933a27d3 DH |
1118 | asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg); |
1119 | ||
1120 | return 0; | |
1121 | } | |
1122 | ||
1123 | static int ax88178_link_reset(struct usbnet *dev) | |
1124 | { | |
1125 | u16 mode; | |
1126 | struct ethtool_cmd ecmd; | |
1127 | struct asix_data *data = (struct asix_data *)&dev->data; | |
1128 | ||
60b86755 | 1129 | netdev_dbg(dev->net, "ax88178_link_reset()\n"); |
933a27d3 DH |
1130 | |
1131 | mii_check_media(&dev->mii, 1, 1); | |
1132 | mii_ethtool_gset(&dev->mii, &ecmd); | |
1133 | mode = AX88178_MEDIUM_DEFAULT; | |
1134 | ||
1135 | if (ecmd.speed == SPEED_1000) | |
a7f75c0c | 1136 | mode |= AX_MEDIUM_GM; |
933a27d3 DH |
1137 | else if (ecmd.speed == SPEED_100) |
1138 | mode |= AX_MEDIUM_PS; | |
1139 | else | |
1140 | mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM); | |
1141 | ||
a7f75c0c PK |
1142 | mode |= AX_MEDIUM_ENCK; |
1143 | ||
933a27d3 DH |
1144 | if (ecmd.duplex == DUPLEX_FULL) |
1145 | mode |= AX_MEDIUM_FD; | |
1146 | else | |
1147 | mode &= ~AX_MEDIUM_FD; | |
1148 | ||
60b86755 JP |
1149 | netdev_dbg(dev->net, "ax88178_link_reset() speed: %d duplex: %d setting mode to 0x%04x\n", |
1150 | ecmd.speed, ecmd.duplex, mode); | |
933a27d3 DH |
1151 | |
1152 | asix_write_medium_mode(dev, mode); | |
1153 | ||
1154 | if (data->phymode == PHY_MODE_MARVELL && data->ledmode) | |
1155 | marvell_led_status(dev, ecmd.speed); | |
1156 | ||
1157 | return 0; | |
1158 | } | |
1159 | ||
1160 | static void ax88178_set_mfb(struct usbnet *dev) | |
1161 | { | |
1162 | u16 mfb = AX_RX_CTL_MFB_16384; | |
1163 | u16 rxctl; | |
1164 | u16 medium; | |
1165 | int old_rx_urb_size = dev->rx_urb_size; | |
1166 | ||
1167 | if (dev->hard_mtu < 2048) { | |
1168 | dev->rx_urb_size = 2048; | |
1169 | mfb = AX_RX_CTL_MFB_2048; | |
1170 | } else if (dev->hard_mtu < 4096) { | |
1171 | dev->rx_urb_size = 4096; | |
1172 | mfb = AX_RX_CTL_MFB_4096; | |
1173 | } else if (dev->hard_mtu < 8192) { | |
1174 | dev->rx_urb_size = 8192; | |
1175 | mfb = AX_RX_CTL_MFB_8192; | |
1176 | } else if (dev->hard_mtu < 16384) { | |
1177 | dev->rx_urb_size = 16384; | |
1178 | mfb = AX_RX_CTL_MFB_16384; | |
2e55cc72 | 1179 | } |
933a27d3 DH |
1180 | |
1181 | rxctl = asix_read_rx_ctl(dev); | |
1182 | asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb); | |
1183 | ||
1184 | medium = asix_read_medium_status(dev); | |
1185 | if (dev->net->mtu > 1500) | |
1186 | medium |= AX_MEDIUM_JFE; | |
1187 | else | |
1188 | medium &= ~AX_MEDIUM_JFE; | |
1189 | asix_write_medium_mode(dev, medium); | |
1190 | ||
1191 | if (dev->rx_urb_size > old_rx_urb_size) | |
1192 | usbnet_unlink_rx_urbs(dev); | |
2e55cc72 DB |
1193 | } |
1194 | ||
933a27d3 | 1195 | static int ax88178_change_mtu(struct net_device *net, int new_mtu) |
2e55cc72 | 1196 | { |
933a27d3 DH |
1197 | struct usbnet *dev = netdev_priv(net); |
1198 | int ll_mtu = new_mtu + net->hard_header_len + 4; | |
2e55cc72 | 1199 | |
60b86755 | 1200 | netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu); |
2e55cc72 | 1201 | |
933a27d3 DH |
1202 | if (new_mtu <= 0 || ll_mtu > 16384) |
1203 | return -EINVAL; | |
1204 | ||
1205 | if ((ll_mtu % dev->maxpacket) == 0) | |
1206 | return -EDOM; | |
1207 | ||
1208 | net->mtu = new_mtu; | |
1209 | dev->hard_mtu = net->mtu + net->hard_header_len; | |
1210 | ax88178_set_mfb(dev); | |
1211 | ||
1212 | return 0; | |
1213 | } | |
1214 | ||
1703338c SH |
1215 | static const struct net_device_ops ax88178_netdev_ops = { |
1216 | .ndo_open = usbnet_open, | |
1217 | .ndo_stop = usbnet_stop, | |
1218 | .ndo_start_xmit = usbnet_start_xmit, | |
1219 | .ndo_tx_timeout = usbnet_tx_timeout, | |
1220 | .ndo_set_mac_address = eth_mac_addr, | |
1221 | .ndo_validate_addr = eth_validate_addr, | |
1222 | .ndo_set_multicast_list = asix_set_multicast, | |
1223 | .ndo_do_ioctl = asix_ioctl, | |
1224 | .ndo_change_mtu = ax88178_change_mtu, | |
1225 | }; | |
1226 | ||
933a27d3 DH |
1227 | static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf) |
1228 | { | |
1229 | struct asix_data *data = (struct asix_data *)&dev->data; | |
1230 | int ret; | |
51bf2976 AV |
1231 | u8 buf[ETH_ALEN]; |
1232 | __le16 eeprom; | |
1233 | u8 status; | |
933a27d3 DH |
1234 | int gpio0 = 0; |
1235 | u32 phyid; | |
1236 | ||
1237 | usbnet_get_endpoints(dev,intf); | |
1238 | ||
51bf2976 AV |
1239 | asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status); |
1240 | dbg("GPIO Status: 0x%04x", status); | |
933a27d3 DH |
1241 | |
1242 | asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL); | |
1243 | asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom); | |
1244 | asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL); | |
1245 | ||
1246 | dbg("EEPROM index 0x17 is 0x%04x", eeprom); | |
1247 | ||
51bf2976 | 1248 | if (eeprom == cpu_to_le16(0xffff)) { |
933a27d3 DH |
1249 | data->phymode = PHY_MODE_MARVELL; |
1250 | data->ledmode = 0; | |
1251 | gpio0 = 1; | |
2e55cc72 | 1252 | } else { |
51bf2976 AV |
1253 | data->phymode = le16_to_cpu(eeprom) & 7; |
1254 | data->ledmode = le16_to_cpu(eeprom) >> 8; | |
1255 | gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1; | |
2e55cc72 | 1256 | } |
933a27d3 | 1257 | dbg("GPIO0: %d, PhyMode: %d", gpio0, data->phymode); |
2e55cc72 | 1258 | |
933a27d3 | 1259 | asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | AX_GPIO_GPO1EN, 40); |
51bf2976 | 1260 | if ((le16_to_cpu(eeprom) >> 8) != 1) { |
933a27d3 DH |
1261 | asix_write_gpio(dev, 0x003c, 30); |
1262 | asix_write_gpio(dev, 0x001c, 300); | |
1263 | asix_write_gpio(dev, 0x003c, 30); | |
1264 | } else { | |
1265 | dbg("gpio phymode == 1 path"); | |
1266 | asix_write_gpio(dev, AX_GPIO_GPO1EN, 30); | |
1267 | asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30); | |
1268 | } | |
2e55cc72 | 1269 | |
933a27d3 DH |
1270 | asix_sw_reset(dev, 0); |
1271 | msleep(150); | |
1272 | ||
1273 | asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD); | |
1274 | msleep(150); | |
1275 | ||
1276 | asix_write_rx_ctl(dev, 0); | |
1277 | ||
1278 | /* Get the MAC address */ | |
933a27d3 DH |
1279 | if ((ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, |
1280 | 0, 0, ETH_ALEN, buf)) < 0) { | |
1281 | dbg("Failed to read MAC address: %d", ret); | |
51bf2976 | 1282 | goto out; |
2e55cc72 | 1283 | } |
933a27d3 | 1284 | memcpy(dev->net->dev_addr, buf, ETH_ALEN); |
2e55cc72 | 1285 | |
933a27d3 DH |
1286 | /* Initialize MII structure */ |
1287 | dev->mii.dev = dev->net; | |
1288 | dev->mii.mdio_read = asix_mdio_read; | |
1289 | dev->mii.mdio_write = asix_mdio_write; | |
1290 | dev->mii.phy_id_mask = 0x1f; | |
1291 | dev->mii.reg_num_mask = 0xff; | |
1292 | dev->mii.supports_gmii = 1; | |
933a27d3 | 1293 | dev->mii.phy_id = asix_get_phy_addr(dev); |
1703338c SH |
1294 | |
1295 | dev->net->netdev_ops = &ax88178_netdev_ops; | |
933a27d3 | 1296 | dev->net->ethtool_ops = &ax88178_ethtool_ops; |
2e55cc72 | 1297 | |
933a27d3 DH |
1298 | phyid = asix_get_phyid(dev); |
1299 | dbg("PHYID=0x%08x", phyid); | |
2e55cc72 | 1300 | |
933a27d3 DH |
1301 | if (data->phymode == PHY_MODE_MARVELL) { |
1302 | marvell_phy_init(dev); | |
1303 | msleep(60); | |
1304 | } | |
1305 | ||
1306 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, | |
1307 | BMCR_RESET | BMCR_ANENABLE); | |
1308 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, | |
1309 | ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
1310 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000, | |
1311 | ADVERTISE_1000FULL); | |
1312 | ||
1313 | mii_nway_restart(&dev->mii); | |
1314 | ||
1315 | if ((ret = asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT)) < 0) | |
51bf2976 | 1316 | goto out; |
933a27d3 DH |
1317 | |
1318 | if ((ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL)) < 0) | |
51bf2976 | 1319 | goto out; |
933a27d3 DH |
1320 | |
1321 | /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ | |
1322 | if (dev->driver_info->flags & FLAG_FRAMING_AX) { | |
1323 | /* hard_mtu is still the default - the device does not support | |
1324 | jumbo eth frames */ | |
1325 | dev->rx_urb_size = 2048; | |
1326 | } | |
2e55cc72 | 1327 | return 0; |
933a27d3 | 1328 | |
51bf2976 | 1329 | out: |
933a27d3 | 1330 | return ret; |
2e55cc72 DB |
1331 | } |
1332 | ||
1333 | static const struct driver_info ax8817x_info = { | |
1334 | .description = "ASIX AX8817x USB 2.0 Ethernet", | |
48b1be6a DH |
1335 | .bind = ax88172_bind, |
1336 | .status = asix_status, | |
2e55cc72 DB |
1337 | .link_reset = ax88172_link_reset, |
1338 | .reset = ax88172_link_reset, | |
37e8273c | 1339 | .flags = FLAG_ETHER | FLAG_LINK_INTR, |
2e55cc72 DB |
1340 | .data = 0x00130103, |
1341 | }; | |
1342 | ||
1343 | static const struct driver_info dlink_dub_e100_info = { | |
1344 | .description = "DLink DUB-E100 USB Ethernet", | |
48b1be6a DH |
1345 | .bind = ax88172_bind, |
1346 | .status = asix_status, | |
2e55cc72 DB |
1347 | .link_reset = ax88172_link_reset, |
1348 | .reset = ax88172_link_reset, | |
37e8273c | 1349 | .flags = FLAG_ETHER | FLAG_LINK_INTR, |
2e55cc72 DB |
1350 | .data = 0x009f9d9f, |
1351 | }; | |
1352 | ||
1353 | static const struct driver_info netgear_fa120_info = { | |
1354 | .description = "Netgear FA-120 USB Ethernet", | |
48b1be6a DH |
1355 | .bind = ax88172_bind, |
1356 | .status = asix_status, | |
2e55cc72 DB |
1357 | .link_reset = ax88172_link_reset, |
1358 | .reset = ax88172_link_reset, | |
37e8273c | 1359 | .flags = FLAG_ETHER | FLAG_LINK_INTR, |
2e55cc72 DB |
1360 | .data = 0x00130103, |
1361 | }; | |
1362 | ||
1363 | static const struct driver_info hawking_uf200_info = { | |
1364 | .description = "Hawking UF200 USB Ethernet", | |
48b1be6a DH |
1365 | .bind = ax88172_bind, |
1366 | .status = asix_status, | |
2e55cc72 DB |
1367 | .link_reset = ax88172_link_reset, |
1368 | .reset = ax88172_link_reset, | |
37e8273c | 1369 | .flags = FLAG_ETHER | FLAG_LINK_INTR, |
2e55cc72 DB |
1370 | .data = 0x001f1d1f, |
1371 | }; | |
1372 | ||
1373 | static const struct driver_info ax88772_info = { | |
1374 | .description = "ASIX AX88772 USB 2.0 Ethernet", | |
1375 | .bind = ax88772_bind, | |
48b1be6a | 1376 | .status = asix_status, |
2e55cc72 DB |
1377 | .link_reset = ax88772_link_reset, |
1378 | .reset = ax88772_link_reset, | |
37e8273c | 1379 | .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR, |
933a27d3 DH |
1380 | .rx_fixup = asix_rx_fixup, |
1381 | .tx_fixup = asix_tx_fixup, | |
1382 | }; | |
1383 | ||
1384 | static const struct driver_info ax88178_info = { | |
1385 | .description = "ASIX AX88178 USB 2.0 Ethernet", | |
1386 | .bind = ax88178_bind, | |
1387 | .status = asix_status, | |
1388 | .link_reset = ax88178_link_reset, | |
1389 | .reset = ax88178_link_reset, | |
37e8273c | 1390 | .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR, |
933a27d3 DH |
1391 | .rx_fixup = asix_rx_fixup, |
1392 | .tx_fixup = asix_tx_fixup, | |
2e55cc72 DB |
1393 | }; |
1394 | ||
1395 | static const struct usb_device_id products [] = { | |
1396 | { | |
1397 | // Linksys USB200M | |
1398 | USB_DEVICE (0x077b, 0x2226), | |
1399 | .driver_info = (unsigned long) &ax8817x_info, | |
1400 | }, { | |
1401 | // Netgear FA120 | |
1402 | USB_DEVICE (0x0846, 0x1040), | |
1403 | .driver_info = (unsigned long) &netgear_fa120_info, | |
1404 | }, { | |
1405 | // DLink DUB-E100 | |
1406 | USB_DEVICE (0x2001, 0x1a00), | |
1407 | .driver_info = (unsigned long) &dlink_dub_e100_info, | |
1408 | }, { | |
1409 | // Intellinet, ST Lab USB Ethernet | |
1410 | USB_DEVICE (0x0b95, 0x1720), | |
1411 | .driver_info = (unsigned long) &ax8817x_info, | |
1412 | }, { | |
1413 | // Hawking UF200, TrendNet TU2-ET100 | |
1414 | USB_DEVICE (0x07b8, 0x420a), | |
1415 | .driver_info = (unsigned long) &hawking_uf200_info, | |
1416 | }, { | |
39c4b38c DH |
1417 | // Billionton Systems, USB2AR |
1418 | USB_DEVICE (0x08dd, 0x90ff), | |
1419 | .driver_info = (unsigned long) &ax8817x_info, | |
2e55cc72 DB |
1420 | }, { |
1421 | // ATEN UC210T | |
1422 | USB_DEVICE (0x0557, 0x2009), | |
1423 | .driver_info = (unsigned long) &ax8817x_info, | |
1424 | }, { | |
1425 | // Buffalo LUA-U2-KTX | |
1426 | USB_DEVICE (0x0411, 0x003d), | |
1427 | .driver_info = (unsigned long) &ax8817x_info, | |
ac7b77f1 MD |
1428 | }, { |
1429 | // Buffalo LUA-U2-GT 10/100/1000 | |
1430 | USB_DEVICE (0x0411, 0x006e), | |
1431 | .driver_info = (unsigned long) &ax88178_info, | |
2e55cc72 DB |
1432 | }, { |
1433 | // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter" | |
1434 | USB_DEVICE (0x6189, 0x182d), | |
1435 | .driver_info = (unsigned long) &ax8817x_info, | |
1436 | }, { | |
1437 | // corega FEther USB2-TX | |
1438 | USB_DEVICE (0x07aa, 0x0017), | |
1439 | .driver_info = (unsigned long) &ax8817x_info, | |
1440 | }, { | |
1441 | // Surecom EP-1427X-2 | |
1442 | USB_DEVICE (0x1189, 0x0893), | |
1443 | .driver_info = (unsigned long) &ax8817x_info, | |
1444 | }, { | |
1445 | // goodway corp usb gwusb2e | |
1446 | USB_DEVICE (0x1631, 0x6200), | |
1447 | .driver_info = (unsigned long) &ax8817x_info, | |
39c4b38c DH |
1448 | }, { |
1449 | // JVC MP-PRX1 Port Replicator | |
1450 | USB_DEVICE (0x04f1, 0x3008), | |
1451 | .driver_info = (unsigned long) &ax8817x_info, | |
2e55cc72 DB |
1452 | }, { |
1453 | // ASIX AX88772 10/100 | |
39c4b38c DH |
1454 | USB_DEVICE (0x0b95, 0x7720), |
1455 | .driver_info = (unsigned long) &ax88772_info, | |
7327413c EW |
1456 | }, { |
1457 | // ASIX AX88178 10/100/1000 | |
1458 | USB_DEVICE (0x0b95, 0x1780), | |
933a27d3 | 1459 | .driver_info = (unsigned long) &ax88178_info, |
5e0f76c6 DH |
1460 | }, { |
1461 | // Linksys USB200M Rev 2 | |
1462 | USB_DEVICE (0x13b1, 0x0018), | |
1463 | .driver_info = (unsigned long) &ax88772_info, | |
5732ce84 DH |
1464 | }, { |
1465 | // 0Q0 cable ethernet | |
1466 | USB_DEVICE (0x1557, 0x7720), | |
1467 | .driver_info = (unsigned long) &ax88772_info, | |
933a27d3 DH |
1468 | }, { |
1469 | // DLink DUB-E100 H/W Ver B1 | |
1470 | USB_DEVICE (0x07d1, 0x3c05), | |
1471 | .driver_info = (unsigned long) &ax88772_info, | |
b923e7fc DH |
1472 | }, { |
1473 | // DLink DUB-E100 H/W Ver B1 Alternate | |
1474 | USB_DEVICE (0x2001, 0x3c05), | |
1475 | .driver_info = (unsigned long) &ax88772_info, | |
933a27d3 DH |
1476 | }, { |
1477 | // Linksys USB1000 | |
1478 | USB_DEVICE (0x1737, 0x0039), | |
1479 | .driver_info = (unsigned long) &ax88178_info, | |
b29cf31d YH |
1480 | }, { |
1481 | // IO-DATA ETG-US2 | |
1482 | USB_DEVICE (0x04bb, 0x0930), | |
1483 | .driver_info = (unsigned long) &ax88178_info, | |
2ed22bc2 DH |
1484 | }, { |
1485 | // Belkin F5D5055 | |
1486 | USB_DEVICE(0x050d, 0x5055), | |
1487 | .driver_info = (unsigned long) &ax88178_info, | |
3d60efb5 AN |
1488 | }, { |
1489 | // Apple USB Ethernet Adapter | |
1490 | USB_DEVICE(0x05ac, 0x1402), | |
1491 | .driver_info = (unsigned long) &ax88772_info, | |
ccf95402 JC |
1492 | }, { |
1493 | // Cables-to-Go USB Ethernet Adapter | |
1494 | USB_DEVICE(0x0b95, 0x772a), | |
1495 | .driver_info = (unsigned long) &ax88772_info, | |
fef7cc08 GKH |
1496 | }, { |
1497 | // ABOCOM for pci | |
1498 | USB_DEVICE(0x14ea, 0xab11), | |
1499 | .driver_info = (unsigned long) &ax88178_info, | |
1500 | }, { | |
1501 | // ASIX 88772a | |
1502 | USB_DEVICE(0x0db0, 0xa877), | |
1503 | .driver_info = (unsigned long) &ax88772_info, | |
2e55cc72 DB |
1504 | }, |
1505 | { }, // END | |
1506 | }; | |
1507 | MODULE_DEVICE_TABLE(usb, products); | |
1508 | ||
1509 | static struct usb_driver asix_driver = { | |
2e55cc72 DB |
1510 | .name = "asix", |
1511 | .id_table = products, | |
1512 | .probe = usbnet_probe, | |
1513 | .suspend = usbnet_suspend, | |
1514 | .resume = usbnet_resume, | |
1515 | .disconnect = usbnet_disconnect, | |
a11a6544 | 1516 | .supports_autosuspend = 1, |
2e55cc72 DB |
1517 | }; |
1518 | ||
1519 | static int __init asix_init(void) | |
1520 | { | |
1521 | return usb_register(&asix_driver); | |
1522 | } | |
1523 | module_init(asix_init); | |
1524 | ||
1525 | static void __exit asix_exit(void) | |
1526 | { | |
1527 | usb_deregister(&asix_driver); | |
1528 | } | |
1529 | module_exit(asix_exit); | |
1530 | ||
1531 | MODULE_AUTHOR("David Hollis"); | |
1532 | MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices"); | |
1533 | MODULE_LICENSE("GPL"); | |
1534 |