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iwlwifi: don't include iwl-dev.h from iwl-devtrace.h
[deliverable/linux.git] / drivers / net / usb / asix.c
CommitLineData
2e55cc72
DB		 1/*
2 * ASIX AX8817X based USB 2.0 Ethernet Devices
933a27d3 3 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
2e55cc72 4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
933a27d3 5 * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
2e55cc72
DB		 6 * Copyright (c) 2002-2003 TiVo Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23// #define DEBUG // error path messages, extra info
24// #define VERBOSE // more; success messages
25
2e55cc72
DB		 26#include <linux/module.h>
27#include <linux/kmod.h>
2e55cc72
DB		 28#include <linux/init.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/workqueue.h>
33#include <linux/mii.h>
34#include <linux/usb.h>
35#include <linux/crc32.h>
3692e94f 36#include <linux/usb/usbnet.h>
2e55cc72 37
933a27d3
DH		 38#define DRIVER_VERSION "14-Jun-2006"
39static const char driver_name [] = "asix";
40
2e55cc72
DB		 41/* ASIX AX8817X based USB 2.0 Ethernet Devices */
42
43#define AX_CMD_SET_SW_MII 0x06
44#define AX_CMD_READ_MII_REG 0x07
45#define AX_CMD_WRITE_MII_REG 0x08
46#define AX_CMD_SET_HW_MII 0x0a
47#define AX_CMD_READ_EEPROM 0x0b
48#define AX_CMD_WRITE_EEPROM 0x0c
49#define AX_CMD_WRITE_ENABLE 0x0d
50#define AX_CMD_WRITE_DISABLE 0x0e
933a27d3 51#define AX_CMD_READ_RX_CTL 0x0f
2e55cc72
DB		 52#define AX_CMD_WRITE_RX_CTL 0x10
53#define AX_CMD_READ_IPG012 0x11
54#define AX_CMD_WRITE_IPG0 0x12
55#define AX_CMD_WRITE_IPG1 0x13
933a27d3 56#define AX_CMD_READ_NODE_ID 0x13
7f29a3ba 57#define AX_CMD_WRITE_NODE_ID 0x14
2e55cc72
DB		 58#define AX_CMD_WRITE_IPG2 0x14
59#define AX_CMD_WRITE_MULTI_FILTER 0x16
933a27d3 60#define AX88172_CMD_READ_NODE_ID 0x17
2e55cc72
DB		 61#define AX_CMD_READ_PHY_ID 0x19
62#define AX_CMD_READ_MEDIUM_STATUS 0x1a
63#define AX_CMD_WRITE_MEDIUM_MODE 0x1b
64#define AX_CMD_READ_MONITOR_MODE 0x1c
65#define AX_CMD_WRITE_MONITOR_MODE 0x1d
933a27d3 66#define AX_CMD_READ_GPIOS 0x1e
2e55cc72
DB		 67#define AX_CMD_WRITE_GPIOS 0x1f
68#define AX_CMD_SW_RESET 0x20
69#define AX_CMD_SW_PHY_STATUS 0x21
70#define AX_CMD_SW_PHY_SELECT 0x22
2e55cc72
DB		 71
72#define AX_MONITOR_MODE 0x01
73#define AX_MONITOR_LINK 0x02
74#define AX_MONITOR_MAGIC 0x04
75#define AX_MONITOR_HSFS 0x10
76
77/* AX88172 Medium Status Register values */
933a27d3
DH		 78#define AX88172_MEDIUM_FD 0x02
79#define AX88172_MEDIUM_TX 0x04
80#define AX88172_MEDIUM_FC 0x10
81#define AX88172_MEDIUM_DEFAULT \
82 ( AX88172_MEDIUM_FD | AX88172_MEDIUM_TX | AX88172_MEDIUM_FC )
2e55cc72
DB		 83
84#define AX_MCAST_FILTER_SIZE 8
85#define AX_MAX_MCAST 64
86
2e55cc72
DB		 87#define AX_SWRESET_CLEAR 0x00
88#define AX_SWRESET_RR 0x01
89#define AX_SWRESET_RT 0x02
90#define AX_SWRESET_PRTE 0x04
91#define AX_SWRESET_PRL 0x08
92#define AX_SWRESET_BZ 0x10
93#define AX_SWRESET_IPRL 0x20
94#define AX_SWRESET_IPPD 0x40
95
96#define AX88772_IPG0_DEFAULT 0x15
97#define AX88772_IPG1_DEFAULT 0x0c
98#define AX88772_IPG2_DEFAULT 0x12
99
933a27d3
DH		 100/* AX88772 & AX88178 Medium Mode Register */
101#define AX_MEDIUM_PF 0x0080
102#define AX_MEDIUM_JFE 0x0040
103#define AX_MEDIUM_TFC 0x0020
104#define AX_MEDIUM_RFC 0x0010
105#define AX_MEDIUM_ENCK 0x0008
106#define AX_MEDIUM_AC 0x0004
107#define AX_MEDIUM_FD 0x0002
108#define AX_MEDIUM_GM 0x0001
109#define AX_MEDIUM_SM 0x1000
110#define AX_MEDIUM_SBP 0x0800
111#define AX_MEDIUM_PS 0x0200
112#define AX_MEDIUM_RE 0x0100
113
114#define AX88178_MEDIUM_DEFAULT \
115 (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \
116 AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \
117 AX_MEDIUM_RE )
2e55cc72 118
933a27d3
DH		 119#define AX88772_MEDIUM_DEFAULT \
120 (AX_MEDIUM_FD | AX_MEDIUM_RFC | \
121 AX_MEDIUM_TFC | AX_MEDIUM_PS | \
122 AX_MEDIUM_AC | AX_MEDIUM_RE )
123
124/* AX88772 & AX88178 RX_CTL values */
125#define AX_RX_CTL_SO 0x0080
126#define AX_RX_CTL_AP 0x0020
127#define AX_RX_CTL_AM 0x0010
128#define AX_RX_CTL_AB 0x0008
129#define AX_RX_CTL_SEP 0x0004
130#define AX_RX_CTL_AMALL 0x0002
131#define AX_RX_CTL_PRO 0x0001
132#define AX_RX_CTL_MFB_2048 0x0000
133#define AX_RX_CTL_MFB_4096 0x0100
134#define AX_RX_CTL_MFB_8192 0x0200
135#define AX_RX_CTL_MFB_16384 0x0300
136
137#define AX_DEFAULT_RX_CTL \
138 (AX_RX_CTL_SO | AX_RX_CTL_AB )
139
140/* GPIO 0 .. 2 toggles */
141#define AX_GPIO_GPO0EN 0x01 /* GPIO0 Output enable */
142#define AX_GPIO_GPO_0 0x02 /* GPIO0 Output value */
143#define AX_GPIO_GPO1EN 0x04 /* GPIO1 Output enable */
144#define AX_GPIO_GPO_1 0x08 /* GPIO1 Output value */
145#define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */
146#define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */
147#define AX_GPIO_RESERVED 0x40 /* Reserved */
148#define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */
149
150#define AX_EEPROM_MAGIC 0xdeadbeef
151#define AX88172_EEPROM_LEN 0x40
152#define AX88772_EEPROM_LEN 0xff
153
154#define PHY_MODE_MARVELL 0x0000
155#define MII_MARVELL_LED_CTRL 0x0018
156#define MII_MARVELL_STATUS 0x001b
157#define MII_MARVELL_CTRL 0x0014
158
159#define MARVELL_LED_MANUAL 0x0019
160
161#define MARVELL_STATUS_HWCFG 0x0004
162
163#define MARVELL_CTRL_TXDELAY 0x0002
164#define MARVELL_CTRL_RXDELAY 0x0080
2e55cc72
DB		 165
166/* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */
48b1be6a 167struct asix_data {
2e55cc72 168 u8 multi_filter[AX_MCAST_FILTER_SIZE];
7f29a3ba 169 u8 mac_addr[ETH_ALEN];
933a27d3
DH		 170 u8 phymode;
171 u8 ledmode;
172 u8 eeprom_len;
2e55cc72
DB		 173};
174
175struct ax88172_int_data {
51bf2976 176 __le16 res1;
2e55cc72 177 u8 link;
51bf2976 178 __le16 res2;
2e55cc72 179 u8 status;
51bf2976 180 __le16 res3;
2e55cc72
DB		 181} __attribute__ ((packed));
182
48b1be6a 183static int asix_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
2e55cc72
DB		 184 u16 size, void *data)
185{
51bf2976
AV		 186 void *buf;
187 int err = -ENOMEM;
188
60b86755
JP		 189 netdev_dbg(dev->net, "asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
190 cmd, value, index, size);
51bf2976
AV		 191
192 buf = kmalloc(size, GFP_KERNEL);
193 if (!buf)
194 goto out;
195
196 err = usb_control_msg(
2e55cc72
DB		 197 dev->udev,
198 usb_rcvctrlpipe(dev->udev, 0),
199 cmd,
200 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
201 value,
202 index,
51bf2976 203 buf,
2e55cc72
DB		 204 size,
205 USB_CTRL_GET_TIMEOUT);
94d43363 206 if (err == size)
51bf2976 207 memcpy(data, buf, size);
94d43363
RD		 208 else if (err >= 0)
209 err = -EINVAL;
51bf2976
AV		 210 kfree(buf);
211
212out:
213 return err;
2e55cc72
DB		 214}
215
48b1be6a 216static int asix_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
2e55cc72
DB		 217 u16 size, void *data)
218{
51bf2976
AV		 219 void *buf = NULL;
220 int err = -ENOMEM;
221
60b86755
JP		 222 netdev_dbg(dev->net, "asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
223 cmd, value, index, size);
51bf2976
AV		 224
225 if (data) {
226 buf = kmalloc(size, GFP_KERNEL);
227 if (!buf)
228 goto out;
229 memcpy(buf, data, size);
230 }
231
232 err = usb_control_msg(
2e55cc72
DB		 233 dev->udev,
234 usb_sndctrlpipe(dev->udev, 0),
235 cmd,
236 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
237 value,
238 index,
51bf2976 239 buf,
2e55cc72
DB		 240 size,
241 USB_CTRL_SET_TIMEOUT);
51bf2976
AV		 242 kfree(buf);
243
244out:
245 return err;
2e55cc72
DB		 246}
247
7d12e780 248static void asix_async_cmd_callback(struct urb *urb)
2e55cc72
DB		 249{
250 struct usb_ctrlrequest *req = (struct usb_ctrlrequest *)urb->context;
c94cb314 251 int status = urb->status;
2e55cc72 252
c94cb314 253 if (status < 0)
48b1be6a 254 printk(KERN_DEBUG "asix_async_cmd_callback() failed with %d",
c94cb314 255 status);
2e55cc72
DB		 256
257 kfree(req);
258 usb_free_urb(urb);
259}
260
933a27d3
DH		 261static void
262asix_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value, u16 index,
263 u16 size, void *data)
264{
265 struct usb_ctrlrequest *req;
266 int status;
267 struct urb *urb;
268
60b86755
JP		 269 netdev_dbg(dev->net, "asix_write_cmd_async() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
270 cmd, value, index, size);
933a27d3 271 if ((urb = usb_alloc_urb(0, GFP_ATOMIC)) == NULL) {
60b86755 272 netdev_err(dev->net, "Error allocating URB in write_cmd_async!\n");
933a27d3
DH		 273 return;
274 }
275
276 if ((req = kmalloc(sizeof(struct usb_ctrlrequest), GFP_ATOMIC)) == NULL) {
60b86755 277 netdev_err(dev->net, "Failed to allocate memory for control request\n");
933a27d3
DH		 278 usb_free_urb(urb);
279 return;
280 }
281
282 req->bRequestType = USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE;
283 req->bRequest = cmd;
9aa742ef
ON		 284 req->wValue = cpu_to_le16(value);
285 req->wIndex = cpu_to_le16(index);
286 req->wLength = cpu_to_le16(size);
933a27d3
DH		 287
288 usb_fill_control_urb(urb, dev->udev,
289 usb_sndctrlpipe(dev->udev, 0),
290 (void *)req, data, size,
291 asix_async_cmd_callback, req);
292
293 if((status = usb_submit_urb(urb, GFP_ATOMIC)) < 0) {
60b86755
JP		 294 netdev_err(dev->net, "Error submitting the control message: status=%d\n",
295 status);
933a27d3
DH		 296 kfree(req);
297 usb_free_urb(urb);
298 }
299}
300
301static int asix_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
302{
303 u8 *head;
304 u32 header;
305 char *packet;
306 struct sk_buff *ax_skb;
307 u16 size;
308
309 head = (u8 *) skb->data;
310 memcpy(&header, head, sizeof(header));
311 le32_to_cpus(&header);
312 packet = head + sizeof(header);
313
314 skb_pull(skb, 4);
315
316 while (skb->len > 0) {
317 if ((short)(header & 0x0000ffff) !=
318 ~((short)((header & 0xffff0000) >> 16))) {
60b86755 319 netdev_err(dev->net, "asix_rx_fixup() Bad Header Length\n");
933a27d3
DH		 320 }
321 /* get the packet length */
322 size = (u16) (header & 0x0000ffff);
323
324 if ((skb->len) - ((size + 1) & 0xfffe) == 0)
325 return 2;
326 if (size > ETH_FRAME_LEN) {
60b86755
JP		 327 netdev_err(dev->net, "asix_rx_fixup() Bad RX Length %d\n",
328 size);
933a27d3
DH		 329 return 0;
330 }
331 ax_skb = skb_clone(skb, GFP_ATOMIC);
332 if (ax_skb) {
333 ax_skb->len = size;
334 ax_skb->data = packet;
27a884dc 335 skb_set_tail_pointer(ax_skb, size);
933a27d3
DH		 336 usbnet_skb_return(dev, ax_skb);
337 } else {
338 return 0;
339 }
340
341 skb_pull(skb, (size + 1) & 0xfffe);
342
343 if (skb->len == 0)
344 break;
345
346 head = (u8 *) skb->data;
347 memcpy(&header, head, sizeof(header));
348 le32_to_cpus(&header);
349 packet = head + sizeof(header);
350 skb_pull(skb, 4);
351 }
352
353 if (skb->len < 0) {
60b86755
JP		 354 netdev_err(dev->net, "asix_rx_fixup() Bad SKB Length %d\n",
355 skb->len);
933a27d3
DH		 356 return 0;
357 }
358 return 1;
359}
360
361static struct sk_buff *asix_tx_fixup(struct usbnet *dev, struct sk_buff *skb,
362 gfp_t flags)
363{
364 int padlen;
365 int headroom = skb_headroom(skb);
366 int tailroom = skb_tailroom(skb);
367 u32 packet_len;
368 u32 padbytes = 0xffff0000;
369
370 padlen = ((skb->len + 4) % 512) ? 0 : 4;
371
8e95a202
JP		 372 if ((!skb_cloned(skb)) &&
373 ((headroom + tailroom) >= (4 + padlen))) {
933a27d3
DH		 374 if ((headroom < 4) || (tailroom < padlen)) {
375 skb->data = memmove(skb->head + 4, skb->data, skb->len);
27a884dc 376 skb_set_tail_pointer(skb, skb->len);
933a27d3
DH		 377 }
378 } else {
379 struct sk_buff *skb2;
380 skb2 = skb_copy_expand(skb, 4, padlen, flags);
381 dev_kfree_skb_any(skb);
382 skb = skb2;
383 if (!skb)
384 return NULL;
385 }
386
387 skb_push(skb, 4);
388 packet_len = (((skb->len - 4) ^ 0x0000ffff) << 16) + (skb->len - 4);
57e4f041 389 cpu_to_le32s(&packet_len);
27d7ff46 390 skb_copy_to_linear_data(skb, &packet_len, sizeof(packet_len));
933a27d3
DH		 391
392 if ((skb->len % 512) == 0) {
57e4f041 393 cpu_to_le32s(&padbytes);
27a884dc 394 memcpy(skb_tail_pointer(skb), &padbytes, sizeof(padbytes));
933a27d3
DH		 395 skb_put(skb, sizeof(padbytes));
396 }
397 return skb;
398}
399
400static void asix_status(struct usbnet *dev, struct urb *urb)
401{
402 struct ax88172_int_data *event;
403 int link;
404
405 if (urb->actual_length < 8)
406 return;
407
408 event = urb->transfer_buffer;
409 link = event->link & 0x01;
410 if (netif_carrier_ok(dev->net) != link) {
411 if (link) {
412 netif_carrier_on(dev->net);
413 usbnet_defer_kevent (dev, EVENT_LINK_RESET );
414 } else
415 netif_carrier_off(dev->net);
60b86755 416 netdev_dbg(dev->net, "Link Status is: %d\n", link);
933a27d3
DH		 417 }
418}
419
48b1be6a
DH		 420static inline int asix_set_sw_mii(struct usbnet *dev)
421{
422 int ret;
423 ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL);
424 if (ret < 0)
60b86755 425 netdev_err(dev->net, "Failed to enable software MII access\n");
48b1be6a
DH		 426 return ret;
427}
428
429static inline int asix_set_hw_mii(struct usbnet *dev)
430{
431 int ret;
432 ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL);
433 if (ret < 0)
60b86755 434 netdev_err(dev->net, "Failed to enable hardware MII access\n");
48b1be6a
DH		 435 return ret;
436}
437
933a27d3 438static inline int asix_get_phy_addr(struct usbnet *dev)
48b1be6a 439{
51bf2976
AV		 440 u8 buf[2];
441 int ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, 0, 0, 2, buf);
48b1be6a 442
60b86755 443 netdev_dbg(dev->net, "asix_get_phy_addr()\n");
933a27d3 444
51bf2976 445 if (ret < 0) {
60b86755 446 netdev_err(dev->net, "Error reading PHYID register: %02x\n", ret);
51bf2976 447 goto out;
48b1be6a 448 }
60b86755
JP		 449 netdev_dbg(dev->net, "asix_get_phy_addr() returning 0x%04x\n",
450 *((__le16 *)buf));
51bf2976
AV		 451 ret = buf[1];
452
453out:
48b1be6a
DH		 454 return ret;
455}
456
457static int asix_sw_reset(struct usbnet *dev, u8 flags)
458{
459 int ret;
460
461 ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL);
462 if (ret < 0)
60b86755 463 netdev_err(dev->net, "Failed to send software reset: %02x\n", ret);
933a27d3
DH		 464
465 return ret;
466}
48b1be6a 467
933a27d3
DH		 468static u16 asix_read_rx_ctl(struct usbnet *dev)
469{
51bf2976
AV		 470 __le16 v;
471 int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, &v);
933a27d3 472
51bf2976 473 if (ret < 0) {
60b86755 474 netdev_err(dev->net, "Error reading RX_CTL register: %02x\n", ret);
51bf2976 475 goto out;
933a27d3 476 }
51bf2976
AV		 477 ret = le16_to_cpu(v);
478out:
48b1be6a
DH		 479 return ret;
480}
481
482static int asix_write_rx_ctl(struct usbnet *dev, u16 mode)
483{
484 int ret;
485
60b86755 486 netdev_dbg(dev->net, "asix_write_rx_ctl() - mode = 0x%04x\n", mode);
48b1be6a
DH		 487 ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL);
488 if (ret < 0)
60b86755
JP		 489 netdev_err(dev->net, "Failed to write RX_CTL mode to 0x%04x: %02x\n",
490 mode, ret);
48b1be6a
DH		 491
492 return ret;
493}
494
933a27d3 495static u16 asix_read_medium_status(struct usbnet *dev)
2e55cc72 496{
51bf2976
AV		 497 __le16 v;
498 int ret = asix_read_cmd(dev, AX_CMD_READ_MEDIUM_STATUS, 0, 0, 2, &v);
2e55cc72 499
51bf2976 500 if (ret < 0) {
60b86755
JP		 501 netdev_err(dev->net, "Error reading Medium Status register: %02x\n",
502 ret);
51bf2976 503 goto out;
2e55cc72 504 }
51bf2976
AV		 505 ret = le16_to_cpu(v);
506out:
933a27d3 507 return ret;
2e55cc72
DB		 508}
509
933a27d3 510static int asix_write_medium_mode(struct usbnet *dev, u16 mode)
2e55cc72 511{
933a27d3 512 int ret;
2e55cc72 513
60b86755 514 netdev_dbg(dev->net, "asix_write_medium_mode() - mode = 0x%04x\n", mode);
933a27d3
DH		 515 ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode, 0, 0, NULL);
516 if (ret < 0)
60b86755
JP		 517 netdev_err(dev->net, "Failed to write Medium Mode mode to 0x%04x: %02x\n",
518 mode, ret);
2e55cc72 519
933a27d3
DH		 520 return ret;
521}
2e55cc72 522
933a27d3
DH		 523static int asix_write_gpio(struct usbnet *dev, u16 value, int sleep)
524{
525 int ret;
2e55cc72 526
60b86755 527 netdev_dbg(dev->net, "asix_write_gpio() - value = 0x%04x\n", value);
933a27d3
DH		 528 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, value, 0, 0, NULL);
529 if (ret < 0)
60b86755
JP		 530 netdev_err(dev->net, "Failed to write GPIO value 0x%04x: %02x\n",
531 value, ret);
2e55cc72 532
933a27d3
DH		 533 if (sleep)
534 msleep(sleep);
535
536 return ret;
2e55cc72
DB		 537}
538
933a27d3
DH		 539/*
540 * AX88772 & AX88178 have a 16-bit RX_CTL value
541 */
48b1be6a 542static void asix_set_multicast(struct net_device *net)
2e55cc72
DB		 543{
544 struct usbnet *dev = netdev_priv(net);
48b1be6a 545 struct asix_data *data = (struct asix_data *)&dev->data;
933a27d3 546 u16 rx_ctl = AX_DEFAULT_RX_CTL;
2e55cc72
DB		 547
548 if (net->flags & IFF_PROMISC) {
933a27d3 549 rx_ctl |= AX_RX_CTL_PRO;
8e95a202 550 } else if (net->flags & IFF_ALLMULTI ||
4cd24eaf 551 netdev_mc_count(net) > AX_MAX_MCAST) {
933a27d3 552 rx_ctl |= AX_RX_CTL_AMALL;
4cd24eaf 553 } else if (netdev_mc_empty(net)) {
2e55cc72
DB		 554 /* just broadcast and directed */
555 } else {
556 /* We use the 20 byte dev->data
557 * for our 8 byte filter buffer
558 * to avoid allocating memory that
559 * is tricky to free later */
a92635dc 560 struct dev_mc_list *mc_list;
2e55cc72 561 u32 crc_bits;
2e55cc72
DB		 562
563 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
564
565 /* Build the multicast hash filter. */
a92635dc 566 netdev_for_each_mc_addr(mc_list, net) {
2e55cc72
DB		 567 crc_bits =
568 ether_crc(ETH_ALEN,
569 mc_list->dmi_addr) >> 26;
570 data->multi_filter[crc_bits >> 3] |=
571 1 << (crc_bits & 7);
2e55cc72
DB		 572 }
573
48b1be6a 574 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
2e55cc72
DB		 575 AX_MCAST_FILTER_SIZE, data->multi_filter);
576
933a27d3 577 rx_ctl |= AX_RX_CTL_AM;
2e55cc72
DB		 578 }
579
48b1be6a 580 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
2e55cc72
DB		 581}
582
48b1be6a 583static int asix_mdio_read(struct net_device *netdev, int phy_id, int loc)
2e55cc72
DB		 584{
585 struct usbnet *dev = netdev_priv(netdev);
51bf2976 586 __le16 res;
2e55cc72 587
a9fc6338 588 mutex_lock(&dev->phy_mutex);
48b1be6a
DH		 589 asix_set_sw_mii(dev);
590 asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id,
51bf2976 591 (__u16)loc, 2, &res);
48b1be6a 592 asix_set_hw_mii(dev);
a9fc6338 593 mutex_unlock(&dev->phy_mutex);
2e55cc72 594
60b86755
JP		 595 netdev_dbg(dev->net, "asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n",
596 phy_id, loc, le16_to_cpu(res));
2e55cc72 597
51bf2976 598 return le16_to_cpu(res);
2e55cc72
DB		 599}
600
601static void
48b1be6a 602asix_mdio_write(struct net_device *netdev, int phy_id, int loc, int val)
2e55cc72
DB		 603{
604 struct usbnet *dev = netdev_priv(netdev);
51bf2976 605 __le16 res = cpu_to_le16(val);
2e55cc72 606
60b86755
JP		 607 netdev_dbg(dev->net, "asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n",
608 phy_id, loc, val);
a9fc6338 609 mutex_lock(&dev->phy_mutex);
48b1be6a 610 asix_set_sw_mii(dev);
51bf2976 611 asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, &res);
48b1be6a 612 asix_set_hw_mii(dev);
a9fc6338 613 mutex_unlock(&dev->phy_mutex);
2e55cc72
DB		 614}
615
933a27d3
DH		 616/* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
617static u32 asix_get_phyid(struct usbnet *dev)
2e55cc72 618{
933a27d3
DH		 619 int phy_reg;
620 u32 phy_id;
2e55cc72 621
933a27d3
DH		 622 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
623 if (phy_reg < 0)
624 return 0;
2e55cc72 625
933a27d3 626 phy_id = (phy_reg & 0xffff) << 16;
2e55cc72 627
933a27d3
DH		 628 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
629 if (phy_reg < 0)
630 return 0;
631
632 phy_id |= (phy_reg & 0xffff);
633
634 return phy_id;
2e55cc72
DB		 635}
636
637static void
48b1be6a 638asix_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo)
2e55cc72
DB		 639{
640 struct usbnet *dev = netdev_priv(net);
641 u8 opt;
642
48b1be6a 643 if (asix_read_cmd(dev, AX_CMD_READ_MONITOR_MODE, 0, 0, 1, &opt) < 0) {
2e55cc72
DB		 644 wolinfo->supported = 0;
645 wolinfo->wolopts = 0;
646 return;
647 }
648 wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
649 wolinfo->wolopts = 0;
650 if (opt & AX_MONITOR_MODE) {
651 if (opt & AX_MONITOR_LINK)
652 wolinfo->wolopts |= WAKE_PHY;
653 if (opt & AX_MONITOR_MAGIC)
654 wolinfo->wolopts |= WAKE_MAGIC;
655 }
656}
657
658static int
48b1be6a 659asix_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo)
2e55cc72
DB		 660{
661 struct usbnet *dev = netdev_priv(net);
662 u8 opt = 0;
2e55cc72
DB		 663
664 if (wolinfo->wolopts & WAKE_PHY)
665 opt |= AX_MONITOR_LINK;
666 if (wolinfo->wolopts & WAKE_MAGIC)
667 opt |= AX_MONITOR_MAGIC;
668 if (opt != 0)
669 opt |= AX_MONITOR_MODE;
670
48b1be6a 671 if (asix_write_cmd(dev, AX_CMD_WRITE_MONITOR_MODE,
51bf2976 672 opt, 0, 0, NULL) < 0)
2e55cc72
DB		 673 return -EINVAL;
674
675 return 0;
676}
677
48b1be6a 678static int asix_get_eeprom_len(struct net_device *net)
2e55cc72 679{
933a27d3
DH		 680 struct usbnet *dev = netdev_priv(net);
681 struct asix_data *data = (struct asix_data *)&dev->data;
682
683 return data->eeprom_len;
2e55cc72
DB		 684}
685
48b1be6a 686static int asix_get_eeprom(struct net_device *net,
2e55cc72
DB		 687 struct ethtool_eeprom *eeprom, u8 *data)
688{
689 struct usbnet *dev = netdev_priv(net);
51bf2976 690 __le16 *ebuf = (__le16 *)data;
2e55cc72
DB		 691 int i;
692
693 /* Crude hack to ensure that we don't overwrite memory
694 * if an odd length is supplied
695 */
696 if (eeprom->len % 2)
697 return -EINVAL;
698
699 eeprom->magic = AX_EEPROM_MAGIC;
700
701 /* ax8817x returns 2 bytes from eeprom on read */
702 for (i=0; i < eeprom->len / 2; i++) {
48b1be6a 703 if (asix_read_cmd(dev, AX_CMD_READ_EEPROM,
2e55cc72
DB		 704 eeprom->offset + i, 0, 2, &ebuf[i]) < 0)
705 return -EINVAL;
706 }
707 return 0;
708}
709
48b1be6a 710static void asix_get_drvinfo (struct net_device *net,
2e55cc72
DB		 711 struct ethtool_drvinfo *info)
712{
933a27d3
DH		 713 struct usbnet *dev = netdev_priv(net);
714 struct asix_data *data = (struct asix_data *)&dev->data;
715
2e55cc72
DB		 716 /* Inherit standard device info */
717 usbnet_get_drvinfo(net, info);
933a27d3
DH		 718 strncpy (info->driver, driver_name, sizeof info->driver);
719 strncpy (info->version, DRIVER_VERSION, sizeof info->version);
720 info->eedump_len = data->eeprom_len;
2e55cc72
DB		 721}
722
933a27d3
DH		 723static u32 asix_get_link(struct net_device *net)
724{
725 struct usbnet *dev = netdev_priv(net);
726
727 return mii_link_ok(&dev->mii);
728}
729
730static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
731{
732 struct usbnet *dev = netdev_priv(net);
733
734 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
735}
736
7f29a3ba
JK		 737static int asix_set_mac_address(struct net_device *net, void *p)
738{
739 struct usbnet *dev = netdev_priv(net);
740 struct asix_data *data = (struct asix_data *)&dev->data;
741 struct sockaddr *addr = p;
742
743 if (netif_running(net))
744 return -EBUSY;
745 if (!is_valid_ether_addr(addr->sa_data))
746 return -EADDRNOTAVAIL;
747
748 memcpy(net->dev_addr, addr->sa_data, ETH_ALEN);
749
750 /* We use the 20 byte dev->data
751 * for our 6 byte mac buffer
752 * to avoid allocating memory that
753 * is tricky to free later */
754 memcpy(data->mac_addr, addr->sa_data, ETH_ALEN);
755 asix_write_cmd_async(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
756 data->mac_addr);
757
758 return 0;
759}
760
933a27d3
DH		 761/* We need to override some ethtool_ops so we require our
762 own structure so we don't interfere with other usbnet
763 devices that may be connected at the same time. */
0fc0b732 764static const struct ethtool_ops ax88172_ethtool_ops = {
933a27d3
DH		 765 .get_drvinfo = asix_get_drvinfo,
766 .get_link = asix_get_link,
933a27d3 767 .get_msglevel = usbnet_get_msglevel,
2e55cc72 768 .set_msglevel = usbnet_set_msglevel,
48b1be6a
DH		 769 .get_wol = asix_get_wol,
770 .set_wol = asix_set_wol,
771 .get_eeprom_len = asix_get_eeprom_len,
772 .get_eeprom = asix_get_eeprom,
c41286fd
AB		 773 .get_settings = usbnet_get_settings,
774 .set_settings = usbnet_set_settings,
775 .nway_reset = usbnet_nway_reset,
2e55cc72
DB		 776};
777
933a27d3 778static void ax88172_set_multicast(struct net_device *net)
2e55cc72
DB		 779{
780 struct usbnet *dev = netdev_priv(net);
933a27d3
DH		 781 struct asix_data *data = (struct asix_data *)&dev->data;
782 u8 rx_ctl = 0x8c;
2e55cc72 783
933a27d3
DH		 784 if (net->flags & IFF_PROMISC) {
785 rx_ctl |= 0x01;
8e95a202 786 } else if (net->flags & IFF_ALLMULTI ||
4cd24eaf 787 netdev_mc_count(net) > AX_MAX_MCAST) {
933a27d3 788 rx_ctl |= 0x02;
4cd24eaf 789 } else if (netdev_mc_empty(net)) {
933a27d3
DH		 790 /* just broadcast and directed */
791 } else {
792 /* We use the 20 byte dev->data
793 * for our 8 byte filter buffer
794 * to avoid allocating memory that
795 * is tricky to free later */
a92635dc 796 struct dev_mc_list *mc_list;
933a27d3 797 u32 crc_bits;
933a27d3
DH		 798
799 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
800
801 /* Build the multicast hash filter. */
a92635dc 802 netdev_for_each_mc_addr(mc_list, net) {
933a27d3
DH		 803 crc_bits =
804 ether_crc(ETH_ALEN,
805 mc_list->dmi_addr) >> 26;
806 data->multi_filter[crc_bits >> 3] |=
807 1 << (crc_bits & 7);
933a27d3
DH		 808 }
809
810 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
811 AX_MCAST_FILTER_SIZE, data->multi_filter);
812
813 rx_ctl |= 0x10;
814 }
815
816 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
817}
818
819static int ax88172_link_reset(struct usbnet *dev)
820{
821 u8 mode;
822 struct ethtool_cmd ecmd;
823
824 mii_check_media(&dev->mii, 1, 1);
825 mii_ethtool_gset(&dev->mii, &ecmd);
826 mode = AX88172_MEDIUM_DEFAULT;
827
828 if (ecmd.duplex != DUPLEX_FULL)
829 mode |= ~AX88172_MEDIUM_FD;
830
60b86755
JP		 831 netdev_dbg(dev->net, "ax88172_link_reset() speed: %d duplex: %d setting mode to 0x%04x\n",
832 ecmd.speed, ecmd.duplex, mode);
933a27d3
DH		 833
834 asix_write_medium_mode(dev, mode);
835
836 return 0;
2e55cc72
DB		 837}
838
1703338c
SH		 839static const struct net_device_ops ax88172_netdev_ops = {
840 .ndo_open = usbnet_open,
841 .ndo_stop = usbnet_stop,
842 .ndo_start_xmit = usbnet_start_xmit,
843 .ndo_tx_timeout = usbnet_tx_timeout,
844 .ndo_change_mtu = usbnet_change_mtu,
845 .ndo_set_mac_address = eth_mac_addr,
846 .ndo_validate_addr = eth_validate_addr,
847 .ndo_do_ioctl = asix_ioctl,
848 .ndo_set_multicast_list = ax88172_set_multicast,
849};
850
48b1be6a 851static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
2e55cc72
DB		 852{
853 int ret = 0;
51bf2976 854 u8 buf[ETH_ALEN];
2e55cc72
DB		 855 int i;
856 unsigned long gpio_bits = dev->driver_info->data;
933a27d3
DH		 857 struct asix_data *data = (struct asix_data *)&dev->data;
858
859 data->eeprom_len = AX88172_EEPROM_LEN;
2e55cc72
DB		 860
861 usbnet_get_endpoints(dev,intf);
862
2e55cc72
DB		 863 /* Toggle the GPIOs in a manufacturer/model specific way */
864 for (i = 2; i >= 0; i--) {
48b1be6a 865 if ((ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
2e55cc72 866 (gpio_bits >> (i * 8)) & 0xff, 0, 0,
51bf2976
AV		 867 NULL)) < 0)
868 goto out;
2e55cc72
DB		 869 msleep(5);
870 }
871
933a27d3 872 if ((ret = asix_write_rx_ctl(dev, 0x80)) < 0)
51bf2976 873 goto out;
2e55cc72
DB		 874
875 /* Get the MAC address */
933a27d3 876 if ((ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID,
51bf2976 877 0, 0, ETH_ALEN, buf)) < 0) {
2e55cc72 878 dbg("read AX_CMD_READ_NODE_ID failed: %d", ret);
51bf2976 879 goto out;
2e55cc72
DB		 880 }
881 memcpy(dev->net->dev_addr, buf, ETH_ALEN);
882
2e55cc72
DB		 883 /* Initialize MII structure */
884 dev->mii.dev = dev->net;
48b1be6a
DH		 885 dev->mii.mdio_read = asix_mdio_read;
886 dev->mii.mdio_write = asix_mdio_write;
2e55cc72
DB		 887 dev->mii.phy_id_mask = 0x3f;
888 dev->mii.reg_num_mask = 0x1f;
933a27d3 889 dev->mii.phy_id = asix_get_phy_addr(dev);
2e55cc72 890
1703338c 891 dev->net->netdev_ops = &ax88172_netdev_ops;
48b1be6a 892 dev->net->ethtool_ops = &ax88172_ethtool_ops;
2e55cc72 893
933a27d3
DH		 894 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
895 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
2e55cc72
DB		 896 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
897 mii_nway_restart(&dev->mii);
898
899 return 0;
51bf2976
AV		 900
901out:
2e55cc72
DB		 902 return ret;
903}
904
0fc0b732 905static const struct ethtool_ops ax88772_ethtool_ops = {
48b1be6a 906 .get_drvinfo = asix_get_drvinfo,
933a27d3 907 .get_link = asix_get_link,
2e55cc72
DB		 908 .get_msglevel = usbnet_get_msglevel,
909 .set_msglevel = usbnet_set_msglevel,
48b1be6a
DH		 910 .get_wol = asix_get_wol,
911 .set_wol = asix_set_wol,
912 .get_eeprom_len = asix_get_eeprom_len,
913 .get_eeprom = asix_get_eeprom,
c41286fd
AB		 914 .get_settings = usbnet_get_settings,
915 .set_settings = usbnet_set_settings,
916 .nway_reset = usbnet_nway_reset,
2e55cc72
DB		 917};
918
933a27d3
DH		 919static int ax88772_link_reset(struct usbnet *dev)
920{
921 u16 mode;
922 struct ethtool_cmd ecmd;
923
924 mii_check_media(&dev->mii, 1, 1);
925 mii_ethtool_gset(&dev->mii, &ecmd);
926 mode = AX88772_MEDIUM_DEFAULT;
927
928 if (ecmd.speed != SPEED_100)
929 mode &= ~AX_MEDIUM_PS;
930
931 if (ecmd.duplex != DUPLEX_FULL)
932 mode &= ~AX_MEDIUM_FD;
933
60b86755
JP		 934 netdev_dbg(dev->net, "ax88772_link_reset() speed: %d duplex: %d setting mode to 0x%04x\n",
935 ecmd.speed, ecmd.duplex, mode);
933a27d3
DH		 936
937 asix_write_medium_mode(dev, mode);
938
939 return 0;
940}
941
1703338c
SH		 942static const struct net_device_ops ax88772_netdev_ops = {
943 .ndo_open = usbnet_open,
944 .ndo_stop = usbnet_stop,
945 .ndo_start_xmit = usbnet_start_xmit,
946 .ndo_tx_timeout = usbnet_tx_timeout,
947 .ndo_change_mtu = usbnet_change_mtu,
7f29a3ba 948 .ndo_set_mac_address = asix_set_mac_address,
1703338c
SH		 949 .ndo_validate_addr = eth_validate_addr,
950 .ndo_do_ioctl = asix_ioctl,
951 .ndo_set_multicast_list = asix_set_multicast,
952};
953
2e55cc72
DB		 954static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
955{
d0ffff8f 956 int ret, embd_phy;
933a27d3
DH		 957 u16 rx_ctl;
958 struct asix_data *data = (struct asix_data *)&dev->data;
51bf2976 959 u8 buf[ETH_ALEN];
933a27d3
DH		 960 u32 phyid;
961
962 data->eeprom_len = AX88772_EEPROM_LEN;
2e55cc72
DB		 963
964 usbnet_get_endpoints(dev,intf);
965
933a27d3
DH		 966 if ((ret = asix_write_gpio(dev,
967 AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5)) < 0)
51bf2976 968 goto out;
2e55cc72 969
d0ffff8f
AS		 970 /* 0x10 is the phy id of the embedded 10/100 ethernet phy */
971 embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0);
48b1be6a 972 if ((ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT,
51bf2976 973 embd_phy, 0, 0, NULL)) < 0) {
2e55cc72 974 dbg("Select PHY #1 failed: %d", ret);
51bf2976 975 goto out;
2e55cc72
DB		 976 }
977
d0ffff8f 978 if ((ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL)) < 0)
51bf2976 979 goto out;
2e55cc72
DB		 980
981 msleep(150);
48b1be6a 982 if ((ret = asix_sw_reset(dev, AX_SWRESET_CLEAR)) < 0)
51bf2976 983 goto out;
2e55cc72
DB		 984
985 msleep(150);
d0ffff8f
AS		 986 if (embd_phy) {
987 if ((ret = asix_sw_reset(dev, AX_SWRESET_IPRL)) < 0)
51bf2976 988 goto out;
d0ffff8f
AS		 989 }
990 else {
991 if ((ret = asix_sw_reset(dev, AX_SWRESET_PRTE)) < 0)
51bf2976 992 goto out;
d0ffff8f 993 }
2e55cc72
DB		 994
995 msleep(150);
933a27d3
DH		 996 rx_ctl = asix_read_rx_ctl(dev);
997 dbg("RX_CTL is 0x%04x after software reset", rx_ctl);
998 if ((ret = asix_write_rx_ctl(dev, 0x0000)) < 0)
51bf2976 999 goto out;
2e55cc72 1000
933a27d3
DH		 1001 rx_ctl = asix_read_rx_ctl(dev);
1002 dbg("RX_CTL is 0x%04x setting to 0x0000", rx_ctl);
1003
2e55cc72 1004 /* Get the MAC address */
933a27d3 1005 if ((ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
2e55cc72
DB		 1006 0, 0, ETH_ALEN, buf)) < 0) {
1007 dbg("Failed to read MAC address: %d", ret);
51bf2976 1008 goto out;
2e55cc72
DB		 1009 }
1010 memcpy(dev->net->dev_addr, buf, ETH_ALEN);
1011
2e55cc72
DB		 1012 /* Initialize MII structure */
1013 dev->mii.dev = dev->net;
48b1be6a
DH		 1014 dev->mii.mdio_read = asix_mdio_read;
1015 dev->mii.mdio_write = asix_mdio_write;
933a27d3
DH		 1016 dev->mii.phy_id_mask = 0x1f;
1017 dev->mii.reg_num_mask = 0x1f;
933a27d3
DH		 1018 dev->mii.phy_id = asix_get_phy_addr(dev);
1019
1020 phyid = asix_get_phyid(dev);
1021 dbg("PHYID=0x%08x", phyid);
2e55cc72 1022
48b1be6a 1023 if ((ret = asix_sw_reset(dev, AX_SWRESET_PRL)) < 0)
51bf2976 1024 goto out;
2e55cc72 1025
2e55cc72 1026 msleep(150);
48b1be6a
DH		 1027
1028 if ((ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL)) < 0)
51bf2976 1029 goto out;
2e55cc72 1030
48b1be6a 1031 msleep(150);
2e55cc72 1032
1703338c 1033 dev->net->netdev_ops = &ax88772_netdev_ops;
2e55cc72
DB		 1034 dev->net->ethtool_ops = &ax88772_ethtool_ops;
1035
933a27d3
DH		 1036 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
1037 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
2e55cc72
DB		 1038 ADVERTISE_ALL | ADVERTISE_CSMA);
1039 mii_nway_restart(&dev->mii);
1040
933a27d3 1041 if ((ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT)) < 0)
51bf2976 1042 goto out;
2e55cc72 1043
48b1be6a 1044 if ((ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
2e55cc72 1045 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
51bf2976 1046 AX88772_IPG2_DEFAULT, 0, NULL)) < 0) {
2e55cc72 1047 dbg("Write IPG,IPG1,IPG2 failed: %d", ret);
51bf2976 1048 goto out;
2e55cc72 1049 }
2e55cc72
DB		 1050
1051 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
933a27d3 1052 if ((ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL)) < 0)
51bf2976 1053 goto out;
2e55cc72 1054
933a27d3
DH		 1055 rx_ctl = asix_read_rx_ctl(dev);
1056 dbg("RX_CTL is 0x%04x after all initializations", rx_ctl);
1057
1058 rx_ctl = asix_read_medium_status(dev);
1059 dbg("Medium Status is 0x%04x after all initializations", rx_ctl);
1060
2e55cc72
DB		 1061 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
1062 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
1063 /* hard_mtu is still the default - the device does not support
1064 jumbo eth frames */
1065 dev->rx_urb_size = 2048;
1066 }
2e55cc72
DB		 1067 return 0;
1068
51bf2976 1069out:
2e55cc72
DB		 1070 return ret;
1071}
1072
933a27d3
DH		 1073static struct ethtool_ops ax88178_ethtool_ops = {
1074 .get_drvinfo = asix_get_drvinfo,
1075 .get_link = asix_get_link,
933a27d3
DH		 1076 .get_msglevel = usbnet_get_msglevel,
1077 .set_msglevel = usbnet_set_msglevel,
1078 .get_wol = asix_get_wol,
1079 .set_wol = asix_set_wol,
1080 .get_eeprom_len = asix_get_eeprom_len,
1081 .get_eeprom = asix_get_eeprom,
c41286fd
AB		 1082 .get_settings = usbnet_get_settings,
1083 .set_settings = usbnet_set_settings,
1084 .nway_reset = usbnet_nway_reset,
933a27d3
DH		 1085};
1086
1087static int marvell_phy_init(struct usbnet *dev)
2e55cc72 1088{
933a27d3
DH		 1089 struct asix_data *data = (struct asix_data *)&dev->data;
1090 u16 reg;
2e55cc72 1091
60b86755 1092 netdev_dbg(dev->net, "marvell_phy_init()\n");
2e55cc72 1093
933a27d3 1094 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
60b86755 1095 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg);
2e55cc72 1096
933a27d3
DH		 1097 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
1098 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
2e55cc72 1099
933a27d3
DH		 1100 if (data->ledmode) {
1101 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
1102 MII_MARVELL_LED_CTRL);
60b86755 1103 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg);
2e55cc72 1104
933a27d3
DH		 1105 reg &= 0xf8ff;
1106 reg |= (1 + 0x0100);
1107 asix_mdio_write(dev->net, dev->mii.phy_id,
1108 MII_MARVELL_LED_CTRL, reg);
2e55cc72 1109
933a27d3
DH		 1110 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
1111 MII_MARVELL_LED_CTRL);
60b86755 1112 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg);
933a27d3
DH		 1113 reg &= 0xfc0f;
1114 }
2e55cc72 1115
933a27d3
DH		 1116 return 0;
1117}
1118
1119static int marvell_led_status(struct usbnet *dev, u16 speed)
1120{
1121 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
1122
60b86755 1123 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg);
933a27d3
DH		 1124
1125 /* Clear out the center LED bits - 0x03F0 */
1126 reg &= 0xfc0f;
1127
1128 switch (speed) {
1129 case SPEED_1000:
1130 reg |= 0x03e0;
1131 break;
1132 case SPEED_100:
1133 reg |= 0x03b0;
1134 break;
1135 default:
1136 reg |= 0x02f0;
2e55cc72
DB		 1137 }
1138
60b86755 1139 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg);
933a27d3
DH		 1140 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
1141
1142 return 0;
1143}
1144
1145static int ax88178_link_reset(struct usbnet *dev)
1146{
1147 u16 mode;
1148 struct ethtool_cmd ecmd;
1149 struct asix_data *data = (struct asix_data *)&dev->data;
1150
60b86755 1151 netdev_dbg(dev->net, "ax88178_link_reset()\n");
933a27d3
DH		 1152
1153 mii_check_media(&dev->mii, 1, 1);
1154 mii_ethtool_gset(&dev->mii, &ecmd);
1155 mode = AX88178_MEDIUM_DEFAULT;
1156
1157 if (ecmd.speed == SPEED_1000)
a7f75c0c 1158 mode |= AX_MEDIUM_GM;
933a27d3
DH		 1159 else if (ecmd.speed == SPEED_100)
1160 mode |= AX_MEDIUM_PS;
1161 else
1162 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
1163
a7f75c0c
PK		 1164 mode |= AX_MEDIUM_ENCK;
1165
933a27d3
DH		 1166 if (ecmd.duplex == DUPLEX_FULL)
1167 mode |= AX_MEDIUM_FD;
1168 else
1169 mode &= ~AX_MEDIUM_FD;
1170
60b86755
JP		 1171 netdev_dbg(dev->net, "ax88178_link_reset() speed: %d duplex: %d setting mode to 0x%04x\n",
1172 ecmd.speed, ecmd.duplex, mode);
933a27d3
DH		 1173
1174 asix_write_medium_mode(dev, mode);
1175
1176 if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
1177 marvell_led_status(dev, ecmd.speed);
1178
1179 return 0;
1180}
1181
1182static void ax88178_set_mfb(struct usbnet *dev)
1183{
1184 u16 mfb = AX_RX_CTL_MFB_16384;
1185 u16 rxctl;
1186 u16 medium;
1187 int old_rx_urb_size = dev->rx_urb_size;
1188
1189 if (dev->hard_mtu < 2048) {
1190 dev->rx_urb_size = 2048;
1191 mfb = AX_RX_CTL_MFB_2048;
1192 } else if (dev->hard_mtu < 4096) {
1193 dev->rx_urb_size = 4096;
1194 mfb = AX_RX_CTL_MFB_4096;
1195 } else if (dev->hard_mtu < 8192) {
1196 dev->rx_urb_size = 8192;
1197 mfb = AX_RX_CTL_MFB_8192;
1198 } else if (dev->hard_mtu < 16384) {
1199 dev->rx_urb_size = 16384;
1200 mfb = AX_RX_CTL_MFB_16384;
2e55cc72 1201 }
933a27d3
DH		 1202
1203 rxctl = asix_read_rx_ctl(dev);
1204 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb);
1205
1206 medium = asix_read_medium_status(dev);
1207 if (dev->net->mtu > 1500)
1208 medium |= AX_MEDIUM_JFE;
1209 else
1210 medium &= ~AX_MEDIUM_JFE;
1211 asix_write_medium_mode(dev, medium);
1212
1213 if (dev->rx_urb_size > old_rx_urb_size)
1214 usbnet_unlink_rx_urbs(dev);
2e55cc72
DB		 1215}
1216
933a27d3 1217static int ax88178_change_mtu(struct net_device *net, int new_mtu)
2e55cc72 1218{
933a27d3
DH		 1219 struct usbnet *dev = netdev_priv(net);
1220 int ll_mtu = new_mtu + net->hard_header_len + 4;
2e55cc72 1221
60b86755 1222 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu);
2e55cc72 1223
933a27d3
DH		 1224 if (new_mtu <= 0 || ll_mtu > 16384)
1225 return -EINVAL;
1226
1227 if ((ll_mtu % dev->maxpacket) == 0)
1228 return -EDOM;
1229
1230 net->mtu = new_mtu;
1231 dev->hard_mtu = net->mtu + net->hard_header_len;
1232 ax88178_set_mfb(dev);
1233
1234 return 0;
1235}
1236
1703338c
SH		 1237static const struct net_device_ops ax88178_netdev_ops = {
1238 .ndo_open = usbnet_open,
1239 .ndo_stop = usbnet_stop,
1240 .ndo_start_xmit = usbnet_start_xmit,
1241 .ndo_tx_timeout = usbnet_tx_timeout,
7f29a3ba 1242 .ndo_set_mac_address = asix_set_mac_address,
1703338c
SH		 1243 .ndo_validate_addr = eth_validate_addr,
1244 .ndo_set_multicast_list = asix_set_multicast,
1245 .ndo_do_ioctl = asix_ioctl,
1246 .ndo_change_mtu = ax88178_change_mtu,
1247};
1248
933a27d3
DH		 1249static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
1250{
1251 struct asix_data *data = (struct asix_data *)&dev->data;
1252 int ret;
51bf2976
AV		 1253 u8 buf[ETH_ALEN];
1254 __le16 eeprom;
1255 u8 status;
933a27d3
DH		 1256 int gpio0 = 0;
1257 u32 phyid;
1258
1259 usbnet_get_endpoints(dev,intf);
1260
51bf2976
AV		 1261 asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status);
1262 dbg("GPIO Status: 0x%04x", status);
933a27d3
DH		 1263
1264 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL);
1265 asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom);
1266 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL);
1267
1268 dbg("EEPROM index 0x17 is 0x%04x", eeprom);
1269
51bf2976 1270 if (eeprom == cpu_to_le16(0xffff)) {
933a27d3
DH		 1271 data->phymode = PHY_MODE_MARVELL;
1272 data->ledmode = 0;
1273 gpio0 = 1;
2e55cc72 1274 } else {
51bf2976
AV		 1275 data->phymode = le16_to_cpu(eeprom) & 7;
1276 data->ledmode = le16_to_cpu(eeprom) >> 8;
1277 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1;
2e55cc72 1278 }
933a27d3 1279 dbg("GPIO0: %d, PhyMode: %d", gpio0, data->phymode);
2e55cc72 1280
933a27d3 1281 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | AX_GPIO_GPO1EN, 40);
51bf2976 1282 if ((le16_to_cpu(eeprom) >> 8) != 1) {
933a27d3
DH		 1283 asix_write_gpio(dev, 0x003c, 30);
1284 asix_write_gpio(dev, 0x001c, 300);
1285 asix_write_gpio(dev, 0x003c, 30);
1286 } else {
1287 dbg("gpio phymode == 1 path");
1288 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30);
1289 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30);
1290 }
2e55cc72 1291
933a27d3
DH		 1292 asix_sw_reset(dev, 0);
1293 msleep(150);
1294
1295 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD);
1296 msleep(150);
1297
1298 asix_write_rx_ctl(dev, 0);
1299
1300 /* Get the MAC address */
933a27d3
DH		 1301 if ((ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
1302 0, 0, ETH_ALEN, buf)) < 0) {
1303 dbg("Failed to read MAC address: %d", ret);
51bf2976 1304 goto out;
2e55cc72 1305 }
933a27d3 1306 memcpy(dev->net->dev_addr, buf, ETH_ALEN);
2e55cc72 1307
933a27d3
DH		 1308 /* Initialize MII structure */
1309 dev->mii.dev = dev->net;
1310 dev->mii.mdio_read = asix_mdio_read;
1311 dev->mii.mdio_write = asix_mdio_write;
1312 dev->mii.phy_id_mask = 0x1f;
1313 dev->mii.reg_num_mask = 0xff;
1314 dev->mii.supports_gmii = 1;
933a27d3 1315 dev->mii.phy_id = asix_get_phy_addr(dev);
1703338c
SH		 1316
1317 dev->net->netdev_ops = &ax88178_netdev_ops;
933a27d3 1318 dev->net->ethtool_ops = &ax88178_ethtool_ops;
2e55cc72 1319
933a27d3
DH		 1320 phyid = asix_get_phyid(dev);
1321 dbg("PHYID=0x%08x", phyid);
2e55cc72 1322
933a27d3
DH		 1323 if (data->phymode == PHY_MODE_MARVELL) {
1324 marvell_phy_init(dev);
1325 msleep(60);
1326 }
1327
1328 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR,
1329 BMCR_RESET | BMCR_ANENABLE);
1330 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
1331 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1332 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
1333 ADVERTISE_1000FULL);
1334
1335 mii_nway_restart(&dev->mii);
1336
1337 if ((ret = asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT)) < 0)
51bf2976 1338 goto out;
933a27d3
DH		 1339
1340 if ((ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL)) < 0)
51bf2976 1341 goto out;
933a27d3
DH		 1342
1343 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
1344 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
1345 /* hard_mtu is still the default - the device does not support
1346 jumbo eth frames */
1347 dev->rx_urb_size = 2048;
1348 }
2e55cc72 1349 return 0;
933a27d3 1350
51bf2976 1351out:
933a27d3 1352 return ret;
2e55cc72
DB		 1353}
1354
1355static const struct driver_info ax8817x_info = {
1356 .description = "ASIX AX8817x USB 2.0 Ethernet",
48b1be6a
DH		 1357 .bind = ax88172_bind,
1358 .status = asix_status,
2e55cc72
DB		 1359 .link_reset = ax88172_link_reset,
1360 .reset = ax88172_link_reset,
37e8273c 1361 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 1362 .data = 0x00130103,
1363};
1364
1365static const struct driver_info dlink_dub_e100_info = {
1366 .description = "DLink DUB-E100 USB Ethernet",
48b1be6a
DH		 1367 .bind = ax88172_bind,
1368 .status = asix_status,
2e55cc72
DB		 1369 .link_reset = ax88172_link_reset,
1370 .reset = ax88172_link_reset,
37e8273c 1371 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 1372 .data = 0x009f9d9f,
1373};
1374
1375static const struct driver_info netgear_fa120_info = {
1376 .description = "Netgear FA-120 USB Ethernet",
48b1be6a
DH		 1377 .bind = ax88172_bind,
1378 .status = asix_status,
2e55cc72
DB		 1379 .link_reset = ax88172_link_reset,
1380 .reset = ax88172_link_reset,
37e8273c 1381 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 1382 .data = 0x00130103,
1383};
1384
1385static const struct driver_info hawking_uf200_info = {
1386 .description = "Hawking UF200 USB Ethernet",
48b1be6a
DH		 1387 .bind = ax88172_bind,
1388 .status = asix_status,
2e55cc72
DB		 1389 .link_reset = ax88172_link_reset,
1390 .reset = ax88172_link_reset,
37e8273c 1391 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 1392 .data = 0x001f1d1f,
1393};
1394
1395static const struct driver_info ax88772_info = {
1396 .description = "ASIX AX88772 USB 2.0 Ethernet",
1397 .bind = ax88772_bind,
48b1be6a 1398 .status = asix_status,
2e55cc72
DB		 1399 .link_reset = ax88772_link_reset,
1400 .reset = ax88772_link_reset,
37e8273c 1401 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR,
933a27d3
DH		 1402 .rx_fixup = asix_rx_fixup,
1403 .tx_fixup = asix_tx_fixup,
1404};
1405
1406static const struct driver_info ax88178_info = {
1407 .description = "ASIX AX88178 USB 2.0 Ethernet",
1408 .bind = ax88178_bind,
1409 .status = asix_status,
1410 .link_reset = ax88178_link_reset,
1411 .reset = ax88178_link_reset,
37e8273c 1412 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR,
933a27d3
DH		 1413 .rx_fixup = asix_rx_fixup,
1414 .tx_fixup = asix_tx_fixup,
2e55cc72
DB		 1415};
1416
1417static const struct usb_device_id products [] = {
1418{
1419 // Linksys USB200M
1420 USB_DEVICE (0x077b, 0x2226),
1421 .driver_info = (unsigned long) &ax8817x_info,
1422}, {
1423 // Netgear FA120
1424 USB_DEVICE (0x0846, 0x1040),
1425 .driver_info = (unsigned long) &netgear_fa120_info,
1426}, {
1427 // DLink DUB-E100
1428 USB_DEVICE (0x2001, 0x1a00),
1429 .driver_info = (unsigned long) &dlink_dub_e100_info,
1430}, {
1431 // Intellinet, ST Lab USB Ethernet
1432 USB_DEVICE (0x0b95, 0x1720),
1433 .driver_info = (unsigned long) &ax8817x_info,
1434}, {
1435 // Hawking UF200, TrendNet TU2-ET100
1436 USB_DEVICE (0x07b8, 0x420a),
1437 .driver_info = (unsigned long) &hawking_uf200_info,
1438}, {
39c4b38c
DH		 1439 // Billionton Systems, USB2AR
1440 USB_DEVICE (0x08dd, 0x90ff),
1441 .driver_info = (unsigned long) &ax8817x_info,
2e55cc72
DB		 1442}, {
1443 // ATEN UC210T
1444 USB_DEVICE (0x0557, 0x2009),
1445 .driver_info = (unsigned long) &ax8817x_info,
1446}, {
1447 // Buffalo LUA-U2-KTX
1448 USB_DEVICE (0x0411, 0x003d),
1449 .driver_info = (unsigned long) &ax8817x_info,
ac7b77f1
MD		 1450}, {
1451 // Buffalo LUA-U2-GT 10/100/1000
1452 USB_DEVICE (0x0411, 0x006e),
1453 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB		 1454}, {
1455 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
1456 USB_DEVICE (0x6189, 0x182d),
1457 .driver_info = (unsigned long) &ax8817x_info,
1458}, {
1459 // corega FEther USB2-TX
1460 USB_DEVICE (0x07aa, 0x0017),
1461 .driver_info = (unsigned long) &ax8817x_info,
1462}, {
1463 // Surecom EP-1427X-2
1464 USB_DEVICE (0x1189, 0x0893),
1465 .driver_info = (unsigned long) &ax8817x_info,
1466}, {
1467 // goodway corp usb gwusb2e
1468 USB_DEVICE (0x1631, 0x6200),
1469 .driver_info = (unsigned long) &ax8817x_info,
39c4b38c
DH		 1470}, {
1471 // JVC MP-PRX1 Port Replicator
1472 USB_DEVICE (0x04f1, 0x3008),
1473 .driver_info = (unsigned long) &ax8817x_info,
2e55cc72
DB		 1474}, {
1475 // ASIX AX88772 10/100
39c4b38c
DH		 1476 USB_DEVICE (0x0b95, 0x7720),
1477 .driver_info = (unsigned long) &ax88772_info,
7327413c
EW		 1478}, {
1479 // ASIX AX88178 10/100/1000
1480 USB_DEVICE (0x0b95, 0x1780),
933a27d3 1481 .driver_info = (unsigned long) &ax88178_info,
5e0f76c6
DH		 1482}, {
1483 // Linksys USB200M Rev 2
1484 USB_DEVICE (0x13b1, 0x0018),
1485 .driver_info = (unsigned long) &ax88772_info,
5732ce84
DH		 1486}, {
1487 // 0Q0 cable ethernet
1488 USB_DEVICE (0x1557, 0x7720),
1489 .driver_info = (unsigned long) &ax88772_info,
933a27d3
DH		 1490}, {
1491 // DLink DUB-E100 H/W Ver B1
1492 USB_DEVICE (0x07d1, 0x3c05),
1493 .driver_info = (unsigned long) &ax88772_info,
b923e7fc
DH		 1494}, {
1495 // DLink DUB-E100 H/W Ver B1 Alternate
1496 USB_DEVICE (0x2001, 0x3c05),
1497 .driver_info = (unsigned long) &ax88772_info,
933a27d3
DH		 1498}, {
1499 // Linksys USB1000
1500 USB_DEVICE (0x1737, 0x0039),
1501 .driver_info = (unsigned long) &ax88178_info,
b29cf31d
YH		 1502}, {
1503 // IO-DATA ETG-US2
1504 USB_DEVICE (0x04bb, 0x0930),
1505 .driver_info = (unsigned long) &ax88178_info,
2ed22bc2
DH		 1506}, {
1507 // Belkin F5D5055
1508 USB_DEVICE(0x050d, 0x5055),
1509 .driver_info = (unsigned long) &ax88178_info,
3d60efb5
AN		 1510}, {
1511 // Apple USB Ethernet Adapter
1512 USB_DEVICE(0x05ac, 0x1402),
1513 .driver_info = (unsigned long) &ax88772_info,
ccf95402
JC		 1514}, {
1515 // Cables-to-Go USB Ethernet Adapter
1516 USB_DEVICE(0x0b95, 0x772a),
1517 .driver_info = (unsigned long) &ax88772_info,
fef7cc08
GKH		 1518}, {
1519 // ABOCOM for pci
1520 USB_DEVICE(0x14ea, 0xab11),
1521 .driver_info = (unsigned long) &ax88178_info,
1522}, {
1523 // ASIX 88772a
1524 USB_DEVICE(0x0db0, 0xa877),
1525 .driver_info = (unsigned long) &ax88772_info,
2e55cc72
DB		 1526},
1527 { }, // END
1528};
1529MODULE_DEVICE_TABLE(usb, products);
1530
1531static struct usb_driver asix_driver = {
2e55cc72
DB		 1532 .name = "asix",
1533 .id_table = products,
1534 .probe = usbnet_probe,
1535 .suspend = usbnet_suspend,
1536 .resume = usbnet_resume,
1537 .disconnect = usbnet_disconnect,
a11a6544 1538 .supports_autosuspend = 1,
2e55cc72
DB		 1539};
1540
1541static int __init asix_init(void)
1542{
1543 return usb_register(&asix_driver);
1544}
1545module_init(asix_init);
1546
1547static void __exit asix_exit(void)
1548{
1549 usb_deregister(&asix_driver);
1550}
1551module_exit(asix_exit);
1552
1553MODULE_AUTHOR("David Hollis");
1554MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
1555MODULE_LICENSE("GPL");
1556
Linux kernel - Deliverables
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