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regulator: tps65023: Use [set|get]_voltage_sel_regmap instead of open coded
[deliverable/linux.git] / drivers / net / usb / asix_devices.c
CommitLineData
2e55cc72
DB		 1/*
2 * ASIX AX8817X based USB 2.0 Ethernet Devices
933a27d3 3 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
2e55cc72 4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
933a27d3 5 * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
2e55cc72
DB		 6 * Copyright (c) 2002-2003 TiVo Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
607740bc 23#include "asix.h"
933a27d3
DH		 24
25#define PHY_MODE_MARVELL 0x0000
26#define MII_MARVELL_LED_CTRL 0x0018
27#define MII_MARVELL_STATUS 0x001b
28#define MII_MARVELL_CTRL 0x0014
29
30#define MARVELL_LED_MANUAL 0x0019
31
32#define MARVELL_STATUS_HWCFG 0x0004
33
34#define MARVELL_CTRL_TXDELAY 0x0002
35#define MARVELL_CTRL_RXDELAY 0x0080
2e55cc72 36
3486140e 37#define PHY_MODE_RTL8211CL 0x000C
610d885d 38
2e55cc72 39struct ax88172_int_data {
51bf2976 40 __le16 res1;
2e55cc72 41 u8 link;
51bf2976 42 __le16 res2;
2e55cc72 43 u8 status;
51bf2976 44 __le16 res3;
ba2d3587 45} __packed;
2e55cc72 46
933a27d3
DH		 47static void asix_status(struct usbnet *dev, struct urb *urb)
48{
49 struct ax88172_int_data *event;
50 int link;
51
52 if (urb->actual_length < 8)
53 return;
54
55 event = urb->transfer_buffer;
56 link = event->link & 0x01;
57 if (netif_carrier_ok(dev->net) != link) {
58 if (link) {
59 netif_carrier_on(dev->net);
60 usbnet_defer_kevent (dev, EVENT_LINK_RESET );
61 } else
62 netif_carrier_off(dev->net);
60b86755 63 netdev_dbg(dev->net, "Link Status is: %d\n", link);
933a27d3
DH		 64 }
65}
66
452b5ecd
JCPV		 67static void asix_set_netdev_dev_addr(struct usbnet *dev, u8 *addr)
68{
69 if (is_valid_ether_addr(addr)) {
70 memcpy(dev->net->dev_addr, addr, ETH_ALEN);
71 } else {
72 netdev_info(dev->net, "invalid hw address, using random\n");
73 eth_hw_addr_random(dev->net);
74 }
75}
76
933a27d3
DH		 77/* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
78static u32 asix_get_phyid(struct usbnet *dev)
2e55cc72 79{
933a27d3
DH		 80 int phy_reg;
81 u32 phy_id;
a77929a2 82 int i;
2e55cc72 83
a77929a2
GG		 84 /* Poll for the rare case the FW or phy isn't ready yet. */
85 for (i = 0; i < 100; i++) {
86 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
87 if (phy_reg != 0 && phy_reg != 0xFFFF)
88 break;
89 mdelay(1);
90 }
91
92 if (phy_reg <= 0 || phy_reg == 0xFFFF)
933a27d3 93 return 0;
2e55cc72 94
933a27d3 95 phy_id = (phy_reg & 0xffff) << 16;
2e55cc72 96
933a27d3
DH		 97 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
98 if (phy_reg < 0)
99 return 0;
100
101 phy_id |= (phy_reg & 0xffff);
102
103 return phy_id;
2e55cc72
DB		 104}
105
933a27d3
DH		 106static u32 asix_get_link(struct net_device *net)
107{
108 struct usbnet *dev = netdev_priv(net);
109
110 return mii_link_ok(&dev->mii);
111}
112
113static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
114{
115 struct usbnet *dev = netdev_priv(net);
116
117 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
118}
119
120/* We need to override some ethtool_ops so we require our
121 own structure so we don't interfere with other usbnet
122 devices that may be connected at the same time. */
0fc0b732 123static const struct ethtool_ops ax88172_ethtool_ops = {
933a27d3
DH		 124 .get_drvinfo = asix_get_drvinfo,
125 .get_link = asix_get_link,
933a27d3 126 .get_msglevel = usbnet_get_msglevel,
2e55cc72 127 .set_msglevel = usbnet_set_msglevel,
48b1be6a
DH		 128 .get_wol = asix_get_wol,
129 .set_wol = asix_set_wol,
130 .get_eeprom_len = asix_get_eeprom_len,
131 .get_eeprom = asix_get_eeprom,
cb7b24cd 132 .set_eeprom = asix_set_eeprom,
c41286fd
AB		 133 .get_settings = usbnet_get_settings,
134 .set_settings = usbnet_set_settings,
135 .nway_reset = usbnet_nway_reset,
2e55cc72
DB		 136};
137
933a27d3 138static void ax88172_set_multicast(struct net_device *net)
2e55cc72
DB		 139{
140 struct usbnet *dev = netdev_priv(net);
933a27d3
DH		 141 struct asix_data *data = (struct asix_data *)&dev->data;
142 u8 rx_ctl = 0x8c;
2e55cc72 143
933a27d3
DH		 144 if (net->flags & IFF_PROMISC) {
145 rx_ctl |= 0x01;
8e95a202 146 } else if (net->flags & IFF_ALLMULTI ||
4cd24eaf 147 netdev_mc_count(net) > AX_MAX_MCAST) {
933a27d3 148 rx_ctl |= 0x02;
4cd24eaf 149 } else if (netdev_mc_empty(net)) {
933a27d3
DH		 150 /* just broadcast and directed */
151 } else {
152 /* We use the 20 byte dev->data
153 * for our 8 byte filter buffer
154 * to avoid allocating memory that
155 * is tricky to free later */
22bedad3 156 struct netdev_hw_addr *ha;
933a27d3 157 u32 crc_bits;
933a27d3
DH		 158
159 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
160
161 /* Build the multicast hash filter. */
22bedad3
JP		 162 netdev_for_each_mc_addr(ha, net) {
163 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
933a27d3
DH		 164 data->multi_filter[crc_bits >> 3] |=
165 1 << (crc_bits & 7);
933a27d3
DH		 166 }
167
168 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
169 AX_MCAST_FILTER_SIZE, data->multi_filter);
170
171 rx_ctl |= 0x10;
172 }
173
174 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
175}
176
177static int ax88172_link_reset(struct usbnet *dev)
178{
179 u8 mode;
8ae6daca 180 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3
DH		 181
182 mii_check_media(&dev->mii, 1, 1);
183 mii_ethtool_gset(&dev->mii, &ecmd);
184 mode = AX88172_MEDIUM_DEFAULT;
185
186 if (ecmd.duplex != DUPLEX_FULL)
187 mode |= ~AX88172_MEDIUM_FD;
188
8ae6daca
DD		 189 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
190 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
933a27d3
DH		 191
192 asix_write_medium_mode(dev, mode);
193
194 return 0;
2e55cc72
DB		 195}
196
1703338c
SH		 197static const struct net_device_ops ax88172_netdev_ops = {
198 .ndo_open = usbnet_open,
199 .ndo_stop = usbnet_stop,
200 .ndo_start_xmit = usbnet_start_xmit,
201 .ndo_tx_timeout = usbnet_tx_timeout,
202 .ndo_change_mtu = usbnet_change_mtu,
203 .ndo_set_mac_address = eth_mac_addr,
204 .ndo_validate_addr = eth_validate_addr,
205 .ndo_do_ioctl = asix_ioctl,
afc4b13d 206 .ndo_set_rx_mode = ax88172_set_multicast,
1703338c
SH		 207};
208
48b1be6a 209static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
2e55cc72
DB		 210{
211 int ret = 0;
51bf2976 212 u8 buf[ETH_ALEN];
2e55cc72
DB		 213 int i;
214 unsigned long gpio_bits = dev->driver_info->data;
215
216 usbnet_get_endpoints(dev,intf);
217
2e55cc72
DB		 218 /* Toggle the GPIOs in a manufacturer/model specific way */
219 for (i = 2; i >= 0; i--) {
83e1b918
GG		 220 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
221 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL);
222 if (ret < 0)
51bf2976 223 goto out;
2e55cc72
DB		 224 msleep(5);
225 }
226
83e1b918
GG		 227 ret = asix_write_rx_ctl(dev, 0x80);
228 if (ret < 0)
51bf2976 229 goto out;
2e55cc72
DB		 230
231 /* Get the MAC address */
83e1b918
GG		 232 ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
233 if (ret < 0) {
49ae25b0
GKH		 234 netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n",
235 ret);
51bf2976 236 goto out;
2e55cc72 237 }
452b5ecd
JCPV		 238
239 asix_set_netdev_dev_addr(dev, buf);
2e55cc72 240
2e55cc72
DB		 241 /* Initialize MII structure */
242 dev->mii.dev = dev->net;
48b1be6a
DH		 243 dev->mii.mdio_read = asix_mdio_read;
244 dev->mii.mdio_write = asix_mdio_write;
2e55cc72
DB		 245 dev->mii.phy_id_mask = 0x3f;
246 dev->mii.reg_num_mask = 0x1f;
933a27d3 247 dev->mii.phy_id = asix_get_phy_addr(dev);
2e55cc72 248
1703338c 249 dev->net->netdev_ops = &ax88172_netdev_ops;
48b1be6a 250 dev->net->ethtool_ops = &ax88172_ethtool_ops;
95162d65
ED		 251 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
252 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
2e55cc72 253
933a27d3
DH		 254 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
255 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
2e55cc72
DB		 256 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
257 mii_nway_restart(&dev->mii);
258
259 return 0;
51bf2976
AV		 260
261out:
2e55cc72
DB		 262 return ret;
263}
264
0fc0b732 265static const struct ethtool_ops ax88772_ethtool_ops = {
48b1be6a 266 .get_drvinfo = asix_get_drvinfo,
933a27d3 267 .get_link = asix_get_link,
2e55cc72
DB		 268 .get_msglevel = usbnet_get_msglevel,
269 .set_msglevel = usbnet_set_msglevel,
48b1be6a
DH		 270 .get_wol = asix_get_wol,
271 .set_wol = asix_set_wol,
272 .get_eeprom_len = asix_get_eeprom_len,
273 .get_eeprom = asix_get_eeprom,
cb7b24cd 274 .set_eeprom = asix_set_eeprom,
c41286fd
AB		 275 .get_settings = usbnet_get_settings,
276 .set_settings = usbnet_set_settings,
277 .nway_reset = usbnet_nway_reset,
2e55cc72
DB		 278};
279
933a27d3
DH		 280static int ax88772_link_reset(struct usbnet *dev)
281{
282 u16 mode;
8ae6daca 283 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3
DH		 284
285 mii_check_media(&dev->mii, 1, 1);
286 mii_ethtool_gset(&dev->mii, &ecmd);
287 mode = AX88772_MEDIUM_DEFAULT;
288
8ae6daca 289 if (ethtool_cmd_speed(&ecmd) != SPEED_100)
933a27d3
DH		 290 mode &= ~AX_MEDIUM_PS;
291
292 if (ecmd.duplex != DUPLEX_FULL)
293 mode &= ~AX_MEDIUM_FD;
294
8ae6daca
DD		 295 netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
296 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
933a27d3
DH		 297
298 asix_write_medium_mode(dev, mode);
299
300 return 0;
301}
302
4ad1438f 303static int ax88772_reset(struct usbnet *dev)
2e55cc72 304{
8ef66bdc 305 struct asix_data *data = (struct asix_data *)&dev->data;
d0ffff8f 306 int ret, embd_phy;
933a27d3 307 u16 rx_ctl;
2e55cc72 308
83e1b918
GG		 309 ret = asix_write_gpio(dev,
310 AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5);
311 if (ret < 0)
51bf2976 312 goto out;
2e55cc72 313
d0ffff8f 314 embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0);
4ad1438f 315
83e1b918
GG		 316 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL);
317 if (ret < 0) {
49ae25b0 318 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
51bf2976 319 goto out;
2e55cc72
DB		 320 }
321
83e1b918
GG		 322 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL);
323 if (ret < 0)
51bf2976 324 goto out;
2e55cc72
DB		 325
326 msleep(150);
83e1b918
GG		 327
328 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR);
329 if (ret < 0)
51bf2976 330 goto out;
2e55cc72
DB		 331
332 msleep(150);
4ad1438f 333
d0ffff8f 334 if (embd_phy) {
83e1b918
GG		 335 ret = asix_sw_reset(dev, AX_SWRESET_IPRL);
336 if (ret < 0)
51bf2976 337 goto out;
83e1b918
GG		 338 } else {
339 ret = asix_sw_reset(dev, AX_SWRESET_PRTE);
340 if (ret < 0)
51bf2976 341 goto out;
d0ffff8f 342 }
2e55cc72
DB		 343
344 msleep(150);
933a27d3 345 rx_ctl = asix_read_rx_ctl(dev);
49ae25b0 346 netdev_dbg(dev->net, "RX_CTL is 0x%04x after software reset\n", rx_ctl);
83e1b918
GG		 347 ret = asix_write_rx_ctl(dev, 0x0000);
348 if (ret < 0)
51bf2976 349 goto out;
2e55cc72 350
933a27d3 351 rx_ctl = asix_read_rx_ctl(dev);
49ae25b0 352 netdev_dbg(dev->net, "RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl);
933a27d3 353
83e1b918
GG		 354 ret = asix_sw_reset(dev, AX_SWRESET_PRL);
355 if (ret < 0)
51bf2976 356 goto out;
2e55cc72 357
2e55cc72 358 msleep(150);
48b1be6a 359
83e1b918
GG		 360 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL);
361 if (ret < 0)
51bf2976 362 goto out;
2e55cc72 363
48b1be6a 364 msleep(150);
2e55cc72 365
933a27d3
DH		 366 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
367 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
2e55cc72
DB		 368 ADVERTISE_ALL | ADVERTISE_CSMA);
369 mii_nway_restart(&dev->mii);
370
83e1b918
GG		 371 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT);
372 if (ret < 0)
51bf2976 373 goto out;
2e55cc72 374
83e1b918 375 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
2e55cc72 376 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
83e1b918
GG		 377 AX88772_IPG2_DEFAULT, 0, NULL);
378 if (ret < 0) {
49ae25b0 379 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
51bf2976 380 goto out;
2e55cc72 381 }
2e55cc72 382
8ef66bdc
JK		 383 /* Rewrite MAC address */
384 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
385 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
386 data->mac_addr);
387 if (ret < 0)
388 goto out;
389
2e55cc72 390 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
83e1b918
GG		 391 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL);
392 if (ret < 0)
51bf2976 393 goto out;
2e55cc72 394
933a27d3 395 rx_ctl = asix_read_rx_ctl(dev);
49ae25b0
GKH		 396 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
397 rx_ctl);
933a27d3
DH		 398
399 rx_ctl = asix_read_medium_status(dev);
49ae25b0
GKH		 400 netdev_dbg(dev->net,
401 "Medium Status is 0x%04x after all initializations\n",
402 rx_ctl);
933a27d3 403
4ad1438f
GG		 404 return 0;
405
406out:
407 return ret;
408
409}
410
411static const struct net_device_ops ax88772_netdev_ops = {
412 .ndo_open = usbnet_open,
413 .ndo_stop = usbnet_stop,
414 .ndo_start_xmit = usbnet_start_xmit,
415 .ndo_tx_timeout = usbnet_tx_timeout,
416 .ndo_change_mtu = usbnet_change_mtu,
417 .ndo_set_mac_address = asix_set_mac_address,
418 .ndo_validate_addr = eth_validate_addr,
419 .ndo_do_ioctl = asix_ioctl,
420 .ndo_set_rx_mode = asix_set_multicast,
421};
422
423static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
424{
5620df65 425 int ret, embd_phy, i;
4ad1438f
GG		 426 u8 buf[ETH_ALEN];
427 u32 phyid;
428
4ad1438f
GG		 429 usbnet_get_endpoints(dev,intf);
430
431 /* Get the MAC address */
5620df65
LS		 432 if (dev->driver_info->data & FLAG_EEPROM_MAC) {
433 for (i = 0; i < (ETH_ALEN >> 1); i++) {
434 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x04 + i,
435 0, 2, buf + i * 2);
436 if (ret < 0)
437 break;
438 }
439 } else {
440 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
441 0, 0, ETH_ALEN, buf);
442 }
443
83e1b918 444 if (ret < 0) {
49ae25b0 445 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
83e1b918 446 return ret;
4ad1438f 447 }
452b5ecd
JCPV		 448
449 asix_set_netdev_dev_addr(dev, buf);
4ad1438f
GG		 450
451 /* Initialize MII structure */
452 dev->mii.dev = dev->net;
453 dev->mii.mdio_read = asix_mdio_read;
454 dev->mii.mdio_write = asix_mdio_write;
455 dev->mii.phy_id_mask = 0x1f;
456 dev->mii.reg_num_mask = 0x1f;
457 dev->mii.phy_id = asix_get_phy_addr(dev);
458
4ad1438f
GG		 459 dev->net->netdev_ops = &ax88772_netdev_ops;
460 dev->net->ethtool_ops = &ax88772_ethtool_ops;
95162d65
ED		 461 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
462 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
4ad1438f 463
d3665188
GG		 464 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
465
466 /* Reset the PHY to normal operation mode */
467 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL);
468 if (ret < 0) {
49ae25b0 469 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
d3665188
GG		 470 return ret;
471 }
472
473 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL);
83e1b918
GG		 474 if (ret < 0)
475 return ret;
4ad1438f 476
d3665188
GG		 477 msleep(150);
478
479 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR);
480 if (ret < 0)
481 return ret;
482
483 msleep(150);
484
485 ret = asix_sw_reset(dev, embd_phy ? AX_SWRESET_IPRL : AX_SWRESET_PRTE);
486
487 /* Read PHYID register *AFTER* the PHY was reset properly */
488 phyid = asix_get_phyid(dev);
49ae25b0 489 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
d3665188 490
2e55cc72
DB		 491 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
492 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
493 /* hard_mtu is still the default - the device does not support
494 jumbo eth frames */
495 dev->rx_urb_size = 2048;
496 }
83e1b918 497
8b5b6f54
LS		 498 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
499 if (!dev->driver_priv)
500 return -ENOMEM;
501
2e55cc72 502 return 0;
2e55cc72
DB		 503}
504
ad327910 505static void ax88772_unbind(struct usbnet *dev, struct usb_interface *intf)
8b5b6f54
LS		 506{
507 if (dev->driver_priv)
508 kfree(dev->driver_priv);
509}
510
bc689c97 511static const struct ethtool_ops ax88178_ethtool_ops = {
933a27d3
DH		 512 .get_drvinfo = asix_get_drvinfo,
513 .get_link = asix_get_link,
933a27d3
DH		 514 .get_msglevel = usbnet_get_msglevel,
515 .set_msglevel = usbnet_set_msglevel,
516 .get_wol = asix_get_wol,
517 .set_wol = asix_set_wol,
518 .get_eeprom_len = asix_get_eeprom_len,
519 .get_eeprom = asix_get_eeprom,
cb7b24cd 520 .set_eeprom = asix_set_eeprom,
c41286fd
AB		 521 .get_settings = usbnet_get_settings,
522 .set_settings = usbnet_set_settings,
523 .nway_reset = usbnet_nway_reset,
933a27d3
DH		 524};
525
526static int marvell_phy_init(struct usbnet *dev)
2e55cc72 527{
933a27d3
DH		 528 struct asix_data *data = (struct asix_data *)&dev->data;
529 u16 reg;
2e55cc72 530
60b86755 531 netdev_dbg(dev->net, "marvell_phy_init()\n");
2e55cc72 532
933a27d3 533 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
60b86755 534 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg);
2e55cc72 535
933a27d3
DH		 536 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
537 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
2e55cc72 538
933a27d3
DH		 539 if (data->ledmode) {
540 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
541 MII_MARVELL_LED_CTRL);
60b86755 542 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg);
2e55cc72 543
933a27d3
DH		 544 reg &= 0xf8ff;
545 reg |= (1 + 0x0100);
546 asix_mdio_write(dev->net, dev->mii.phy_id,
547 MII_MARVELL_LED_CTRL, reg);
2e55cc72 548
933a27d3
DH		 549 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
550 MII_MARVELL_LED_CTRL);
60b86755 551 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg);
933a27d3
DH		 552 reg &= 0xfc0f;
553 }
2e55cc72 554
933a27d3
DH		 555 return 0;
556}
557
610d885d
GG		 558static int rtl8211cl_phy_init(struct usbnet *dev)
559{
560 struct asix_data *data = (struct asix_data *)&dev->data;
561
562 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n");
563
564 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);
565 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);
566 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,
567 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);
568 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
569
570 if (data->ledmode == 12) {
571 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);
572 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);
573 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
574 }
575
576 return 0;
577}
578
933a27d3
DH		 579static int marvell_led_status(struct usbnet *dev, u16 speed)
580{
581 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
582
60b86755 583 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg);
933a27d3
DH		 584
585 /* Clear out the center LED bits - 0x03F0 */
586 reg &= 0xfc0f;
587
588 switch (speed) {
589 case SPEED_1000:
590 reg |= 0x03e0;
591 break;
592 case SPEED_100:
593 reg |= 0x03b0;
594 break;
595 default:
596 reg |= 0x02f0;
2e55cc72
DB		 597 }
598
60b86755 599 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg);
933a27d3
DH		 600 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
601
602 return 0;
603}
604
610d885d
GG		 605static int ax88178_reset(struct usbnet *dev)
606{
607 struct asix_data *data = (struct asix_data *)&dev->data;
608 int ret;
609 __le16 eeprom;
610 u8 status;
611 int gpio0 = 0;
b2d3ad29 612 u32 phyid;
610d885d
GG		 613
614 asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status);
49ae25b0 615 netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status);
610d885d
GG		 616
617 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL);
618 asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom);
619 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL);
620
49ae25b0 621 netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom);
610d885d
GG		 622
623 if (eeprom == cpu_to_le16(0xffff)) {
624 data->phymode = PHY_MODE_MARVELL;
625 data->ledmode = 0;
626 gpio0 = 1;
627 } else {
b2d3ad29 628 data->phymode = le16_to_cpu(eeprom) & 0x7F;
610d885d
GG		 629 data->ledmode = le16_to_cpu(eeprom) >> 8;
630 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1;
631 }
49ae25b0 632 netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode);
610d885d 633
b2d3ad29 634 /* Power up external GigaPHY through AX88178 GPIO pin */
610d885d
GG		 635 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | AX_GPIO_GPO1EN, 40);
636 if ((le16_to_cpu(eeprom) >> 8) != 1) {
637 asix_write_gpio(dev, 0x003c, 30);
638 asix_write_gpio(dev, 0x001c, 300);
639 asix_write_gpio(dev, 0x003c, 30);
640 } else {
49ae25b0 641 netdev_dbg(dev->net, "gpio phymode == 1 path\n");
610d885d
GG		 642 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30);
643 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30);
644 }
645
b2d3ad29
GG		 646 /* Read PHYID register *AFTER* powering up PHY */
647 phyid = asix_get_phyid(dev);
49ae25b0 648 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
b2d3ad29
GG		 649
650 /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */
651 asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL);
652
610d885d
GG		 653 asix_sw_reset(dev, 0);
654 msleep(150);
655
656 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD);
657 msleep(150);
658
659 asix_write_rx_ctl(dev, 0);
660
661 if (data->phymode == PHY_MODE_MARVELL) {
662 marvell_phy_init(dev);
663 msleep(60);
664 } else if (data->phymode == PHY_MODE_RTL8211CL)
665 rtl8211cl_phy_init(dev);
666
667 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR,
668 BMCR_RESET | BMCR_ANENABLE);
669 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
670 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
671 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
672 ADVERTISE_1000FULL);
673
674 mii_nway_restart(&dev->mii);
675
83e1b918
GG		 676 ret = asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT);
677 if (ret < 0)
678 return ret;
610d885d 679
71bc5d94
JK		 680 /* Rewrite MAC address */
681 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
682 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
683 data->mac_addr);
684 if (ret < 0)
685 return ret;
686
83e1b918
GG		 687 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL);
688 if (ret < 0)
689 return ret;
610d885d
GG		 690
691 return 0;
610d885d
GG		 692}
693
933a27d3
DH		 694static int ax88178_link_reset(struct usbnet *dev)
695{
696 u16 mode;
8ae6daca 697 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3 698 struct asix_data *data = (struct asix_data *)&dev->data;
8ae6daca 699 u32 speed;
933a27d3 700
60b86755 701 netdev_dbg(dev->net, "ax88178_link_reset()\n");
933a27d3
DH		 702
703 mii_check_media(&dev->mii, 1, 1);
704 mii_ethtool_gset(&dev->mii, &ecmd);
705 mode = AX88178_MEDIUM_DEFAULT;
8ae6daca 706 speed = ethtool_cmd_speed(&ecmd);
933a27d3 707
8ae6daca 708 if (speed == SPEED_1000)
a7f75c0c 709 mode |= AX_MEDIUM_GM;
8ae6daca 710 else if (speed == SPEED_100)
933a27d3
DH		 711 mode |= AX_MEDIUM_PS;
712 else
713 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
714
a7f75c0c
PK		 715 mode |= AX_MEDIUM_ENCK;
716
933a27d3
DH		 717 if (ecmd.duplex == DUPLEX_FULL)
718 mode |= AX_MEDIUM_FD;
719 else
720 mode &= ~AX_MEDIUM_FD;
721
8ae6daca
DD		 722 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
723 speed, ecmd.duplex, mode);
933a27d3
DH		 724
725 asix_write_medium_mode(dev, mode);
726
727 if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
8ae6daca 728 marvell_led_status(dev, speed);
933a27d3
DH		 729
730 return 0;
731}
732
733static void ax88178_set_mfb(struct usbnet *dev)
734{
735 u16 mfb = AX_RX_CTL_MFB_16384;
736 u16 rxctl;
737 u16 medium;
738 int old_rx_urb_size = dev->rx_urb_size;
739
740 if (dev->hard_mtu < 2048) {
741 dev->rx_urb_size = 2048;
742 mfb = AX_RX_CTL_MFB_2048;
743 } else if (dev->hard_mtu < 4096) {
744 dev->rx_urb_size = 4096;
745 mfb = AX_RX_CTL_MFB_4096;
746 } else if (dev->hard_mtu < 8192) {
747 dev->rx_urb_size = 8192;
748 mfb = AX_RX_CTL_MFB_8192;
749 } else if (dev->hard_mtu < 16384) {
750 dev->rx_urb_size = 16384;
751 mfb = AX_RX_CTL_MFB_16384;
2e55cc72 752 }
933a27d3
DH		 753
754 rxctl = asix_read_rx_ctl(dev);
755 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb);
756
757 medium = asix_read_medium_status(dev);
758 if (dev->net->mtu > 1500)
759 medium |= AX_MEDIUM_JFE;
760 else
761 medium &= ~AX_MEDIUM_JFE;
762 asix_write_medium_mode(dev, medium);
763
764 if (dev->rx_urb_size > old_rx_urb_size)
765 usbnet_unlink_rx_urbs(dev);
2e55cc72
DB		 766}
767
933a27d3 768static int ax88178_change_mtu(struct net_device *net, int new_mtu)
2e55cc72 769{
933a27d3
DH		 770 struct usbnet *dev = netdev_priv(net);
771 int ll_mtu = new_mtu + net->hard_header_len + 4;
2e55cc72 772
60b86755 773 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu);
2e55cc72 774
933a27d3
DH		 775 if (new_mtu <= 0 || ll_mtu > 16384)
776 return -EINVAL;
777
778 if ((ll_mtu % dev->maxpacket) == 0)
779 return -EDOM;
780
781 net->mtu = new_mtu;
782 dev->hard_mtu = net->mtu + net->hard_header_len;
783 ax88178_set_mfb(dev);
784
785 return 0;
786}
787
1703338c
SH		 788static const struct net_device_ops ax88178_netdev_ops = {
789 .ndo_open = usbnet_open,
790 .ndo_stop = usbnet_stop,
791 .ndo_start_xmit = usbnet_start_xmit,
792 .ndo_tx_timeout = usbnet_tx_timeout,
7f29a3ba 793 .ndo_set_mac_address = asix_set_mac_address,
1703338c 794 .ndo_validate_addr = eth_validate_addr,
afc4b13d 795 .ndo_set_rx_mode = asix_set_multicast,
1703338c
SH		 796 .ndo_do_ioctl = asix_ioctl,
797 .ndo_change_mtu = ax88178_change_mtu,
798};
799
933a27d3
DH		 800static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
801{
933a27d3 802 int ret;
51bf2976 803 u8 buf[ETH_ALEN];
933a27d3
DH		 804
805 usbnet_get_endpoints(dev,intf);
806
933a27d3 807 /* Get the MAC address */
83e1b918
GG		 808 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
809 if (ret < 0) {
49ae25b0 810 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
83e1b918 811 return ret;
2e55cc72 812 }
452b5ecd
JCPV		 813
814 asix_set_netdev_dev_addr(dev, buf);
2e55cc72 815
933a27d3
DH		 816 /* Initialize MII structure */
817 dev->mii.dev = dev->net;
818 dev->mii.mdio_read = asix_mdio_read;
819 dev->mii.mdio_write = asix_mdio_write;
820 dev->mii.phy_id_mask = 0x1f;
821 dev->mii.reg_num_mask = 0xff;
822 dev->mii.supports_gmii = 1;
933a27d3 823 dev->mii.phy_id = asix_get_phy_addr(dev);
1703338c
SH		 824
825 dev->net->netdev_ops = &ax88178_netdev_ops;
933a27d3 826 dev->net->ethtool_ops = &ax88178_ethtool_ops;
2e55cc72 827
b2d3ad29
GG		 828 /* Blink LEDS so users know driver saw dongle */
829 asix_sw_reset(dev, 0);
830 msleep(150);
2e55cc72 831
b2d3ad29
GG		 832 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD);
833 msleep(150);
933a27d3
DH		 834
835 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
836 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
837 /* hard_mtu is still the default - the device does not support
838 jumbo eth frames */
839 dev->rx_urb_size = 2048;
840 }
933a27d3 841
8b5b6f54
LS		 842 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
843 if (!dev->driver_priv)
844 return -ENOMEM;
845
83e1b918 846 return 0;
2e55cc72
DB		 847}
848
849static const struct driver_info ax8817x_info = {
850 .description = "ASIX AX8817x USB 2.0 Ethernet",
48b1be6a
DH		 851 .bind = ax88172_bind,
852 .status = asix_status,
2e55cc72
DB		 853 .link_reset = ax88172_link_reset,
854 .reset = ax88172_link_reset,
37e8273c 855 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 856 .data = 0x00130103,
857};
858
859static const struct driver_info dlink_dub_e100_info = {
860 .description = "DLink DUB-E100 USB Ethernet",
48b1be6a
DH		 861 .bind = ax88172_bind,
862 .status = asix_status,
2e55cc72
DB		 863 .link_reset = ax88172_link_reset,
864 .reset = ax88172_link_reset,
37e8273c 865 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 866 .data = 0x009f9d9f,
867};
868
869static const struct driver_info netgear_fa120_info = {
870 .description = "Netgear FA-120 USB Ethernet",
48b1be6a
DH		 871 .bind = ax88172_bind,
872 .status = asix_status,
2e55cc72
DB		 873 .link_reset = ax88172_link_reset,
874 .reset = ax88172_link_reset,
37e8273c 875 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 876 .data = 0x00130103,
877};
878
879static const struct driver_info hawking_uf200_info = {
880 .description = "Hawking UF200 USB Ethernet",
48b1be6a
DH		 881 .bind = ax88172_bind,
882 .status = asix_status,
2e55cc72
DB		 883 .link_reset = ax88172_link_reset,
884 .reset = ax88172_link_reset,
37e8273c 885 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 886 .data = 0x001f1d1f,
887};
888
889static const struct driver_info ax88772_info = {
890 .description = "ASIX AX88772 USB 2.0 Ethernet",
891 .bind = ax88772_bind,
8b5b6f54 892 .unbind = ax88772_unbind,
48b1be6a 893 .status = asix_status,
2e55cc72 894 .link_reset = ax88772_link_reset,
4ad1438f 895 .reset = ax88772_reset,
a9e0aca4 896 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET,
8b5b6f54 897 .rx_fixup = asix_rx_fixup_common,
933a27d3
DH		 898 .tx_fixup = asix_tx_fixup,
899};
900
5620df65
LS		 901static const struct driver_info ax88772b_info = {
902 .description = "ASIX AX88772B USB 2.0 Ethernet",
903 .bind = ax88772_bind,
8b5b6f54 904 .unbind = ax88772_unbind,
5620df65
LS		 905 .status = asix_status,
906 .link_reset = ax88772_link_reset,
907 .reset = ax88772_reset,
908 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
909 FLAG_MULTI_PACKET,
8b5b6f54 910 .rx_fixup = asix_rx_fixup_common,
5620df65
LS		 911 .tx_fixup = asix_tx_fixup,
912 .data = FLAG_EEPROM_MAC,
913};
914
933a27d3
DH		 915static const struct driver_info ax88178_info = {
916 .description = "ASIX AX88178 USB 2.0 Ethernet",
917 .bind = ax88178_bind,
8b5b6f54 918 .unbind = ax88772_unbind,
933a27d3
DH		 919 .status = asix_status,
920 .link_reset = ax88178_link_reset,
610d885d 921 .reset = ax88178_reset,
37e8273c 922 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR,
8b5b6f54 923 .rx_fixup = asix_rx_fixup_common,
933a27d3 924 .tx_fixup = asix_tx_fixup,
2e55cc72
DB		 925};
926
45af3fb4
GT		 927/*
928 * USBLINK 20F9 "USB 2.0 LAN" USB ethernet adapter, typically found in
929 * no-name packaging.
930 * USB device strings are:
931 * 1: Manufacturer: USBLINK
932 * 2: Product: HG20F9 USB2.0
933 * 3: Serial: 000003
934 * Appears to be compatible with Asix 88772B.
935 */
936static const struct driver_info hg20f9_info = {
937 .description = "HG20F9 USB 2.0 Ethernet",
938 .bind = ax88772_bind,
939 .unbind = ax88772_unbind,
940 .status = asix_status,
941 .link_reset = ax88772_link_reset,
942 .reset = ax88772_reset,
943 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
944 FLAG_MULTI_PACKET,
945 .rx_fixup = asix_rx_fixup_common,
946 .tx_fixup = asix_tx_fixup,
947 .data = FLAG_EEPROM_MAC,
948};
949
16626b0c
CR		 950extern const struct driver_info ax88172a_info;
951
2e55cc72
DB		 952static const struct usb_device_id products [] = {
953{
954 // Linksys USB200M
955 USB_DEVICE (0x077b, 0x2226),
956 .driver_info = (unsigned long) &ax8817x_info,
957}, {
958 // Netgear FA120
959 USB_DEVICE (0x0846, 0x1040),
960 .driver_info = (unsigned long) &netgear_fa120_info,
961}, {
962 // DLink DUB-E100
963 USB_DEVICE (0x2001, 0x1a00),
964 .driver_info = (unsigned long) &dlink_dub_e100_info,
965}, {
966 // Intellinet, ST Lab USB Ethernet
967 USB_DEVICE (0x0b95, 0x1720),
968 .driver_info = (unsigned long) &ax8817x_info,
969}, {
970 // Hawking UF200, TrendNet TU2-ET100
971 USB_DEVICE (0x07b8, 0x420a),
972 .driver_info = (unsigned long) &hawking_uf200_info,
973}, {
39c4b38c
DH		 974 // Billionton Systems, USB2AR
975 USB_DEVICE (0x08dd, 0x90ff),
976 .driver_info = (unsigned long) &ax8817x_info,
2e55cc72
DB		 977}, {
978 // ATEN UC210T
979 USB_DEVICE (0x0557, 0x2009),
980 .driver_info = (unsigned long) &ax8817x_info,
981}, {
982 // Buffalo LUA-U2-KTX
983 USB_DEVICE (0x0411, 0x003d),
984 .driver_info = (unsigned long) &ax8817x_info,
ac7b77f1
MD		 985}, {
986 // Buffalo LUA-U2-GT 10/100/1000
987 USB_DEVICE (0x0411, 0x006e),
988 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB		 989}, {
990 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
991 USB_DEVICE (0x6189, 0x182d),
992 .driver_info = (unsigned long) &ax8817x_info,
4e503919
JN		 993}, {
994 // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter"
995 USB_DEVICE (0x0df6, 0x0056),
996 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB		 997}, {
998 // corega FEther USB2-TX
999 USB_DEVICE (0x07aa, 0x0017),
1000 .driver_info = (unsigned long) &ax8817x_info,
1001}, {
1002 // Surecom EP-1427X-2
1003 USB_DEVICE (0x1189, 0x0893),
1004 .driver_info = (unsigned long) &ax8817x_info,
1005}, {
1006 // goodway corp usb gwusb2e
1007 USB_DEVICE (0x1631, 0x6200),
1008 .driver_info = (unsigned long) &ax8817x_info,
39c4b38c
DH		 1009}, {
1010 // JVC MP-PRX1 Port Replicator
1011 USB_DEVICE (0x04f1, 0x3008),
1012 .driver_info = (unsigned long) &ax8817x_info,
66dc81ec
QP		 1013}, {
1014 // Lenovo U2L100P 10/100
1015 USB_DEVICE (0x17ef, 0x7203),
1016 .driver_info = (unsigned long) &ax88772_info,
30885909
MV		 1017}, {
1018 // ASIX AX88772B 10/100
1019 USB_DEVICE (0x0b95, 0x772b),
5620df65 1020 .driver_info = (unsigned long) &ax88772b_info,
2e55cc72
DB		 1021}, {
1022 // ASIX AX88772 10/100
39c4b38c
DH		 1023 USB_DEVICE (0x0b95, 0x7720),
1024 .driver_info = (unsigned long) &ax88772_info,
7327413c
EW		 1025}, {
1026 // ASIX AX88178 10/100/1000
1027 USB_DEVICE (0x0b95, 0x1780),
933a27d3 1028 .driver_info = (unsigned long) &ax88178_info,
f4680d3d
AE		 1029}, {
1030 // Logitec LAN-GTJ/U2A
1031 USB_DEVICE (0x0789, 0x0160),
1032 .driver_info = (unsigned long) &ax88178_info,
5e0f76c6
DH		 1033}, {
1034 // Linksys USB200M Rev 2
1035 USB_DEVICE (0x13b1, 0x0018),
1036 .driver_info = (unsigned long) &ax88772_info,
5732ce84
DH		 1037}, {
1038 // 0Q0 cable ethernet
1039 USB_DEVICE (0x1557, 0x7720),
1040 .driver_info = (unsigned long) &ax88772_info,
933a27d3
DH		 1041}, {
1042 // DLink DUB-E100 H/W Ver B1
1043 USB_DEVICE (0x07d1, 0x3c05),
1044 .driver_info = (unsigned long) &ax88772_info,
b923e7fc
DH		 1045}, {
1046 // DLink DUB-E100 H/W Ver B1 Alternate
1047 USB_DEVICE (0x2001, 0x3c05),
1048 .driver_info = (unsigned long) &ax88772_info,
ed3770a9
S		 1049}, {
1050 // DLink DUB-E100 H/W Ver C1
1051 USB_DEVICE (0x2001, 0x1a02),
1052 .driver_info = (unsigned long) &ax88772_info,
933a27d3
DH		 1053}, {
1054 // Linksys USB1000
1055 USB_DEVICE (0x1737, 0x0039),
1056 .driver_info = (unsigned long) &ax88178_info,
b29cf31d
YH		 1057}, {
1058 // IO-DATA ETG-US2
1059 USB_DEVICE (0x04bb, 0x0930),
1060 .driver_info = (unsigned long) &ax88178_info,
2ed22bc2
DH		 1061}, {
1062 // Belkin F5D5055
1063 USB_DEVICE(0x050d, 0x5055),
1064 .driver_info = (unsigned long) &ax88178_info,
3d60efb5
AN		 1065}, {
1066 // Apple USB Ethernet Adapter
1067 USB_DEVICE(0x05ac, 0x1402),
1068 .driver_info = (unsigned long) &ax88772_info,
ccf95402
JC		 1069}, {
1070 // Cables-to-Go USB Ethernet Adapter
1071 USB_DEVICE(0x0b95, 0x772a),
1072 .driver_info = (unsigned long) &ax88772_info,
fef7cc08
GKH		 1073}, {
1074 // ABOCOM for pci
1075 USB_DEVICE(0x14ea, 0xab11),
1076 .driver_info = (unsigned long) &ax88178_info,
1077}, {
1078 // ASIX 88772a
1079 USB_DEVICE(0x0db0, 0xa877),
1080 .driver_info = (unsigned long) &ax88772_info,
e8303a3b
AJ		 1081}, {
1082 // Asus USB Ethernet Adapter
1083 USB_DEVICE (0x0b95, 0x7e2b),
1084 .driver_info = (unsigned long) &ax88772_info,
16626b0c
CR		 1085}, {
1086 /* ASIX 88172a demo board */
1087 USB_DEVICE(0x0b95, 0x172a),
1088 .driver_info = (unsigned long) &ax88172a_info,
45af3fb4
GT		 1089}, {
1090 /*
1091 * USBLINK HG20F9 "USB 2.0 LAN"
1092 * Appears to have gazumped Linksys's manufacturer ID but
1093 * doesn't (yet) conflict with any known Linksys product.
1094 */
1095 USB_DEVICE(0x066b, 0x20f9),
1096 .driver_info = (unsigned long) &hg20f9_info,
2e55cc72
DB		 1097},
1098 { }, // END
1099};
1100MODULE_DEVICE_TABLE(usb, products);
1101
1102static struct usb_driver asix_driver = {
83e1b918 1103 .name = DRIVER_NAME,
2e55cc72
DB		 1104 .id_table = products,
1105 .probe = usbnet_probe,
1106 .suspend = usbnet_suspend,
1107 .resume = usbnet_resume,
1108 .disconnect = usbnet_disconnect,
a11a6544 1109 .supports_autosuspend = 1,
e1f12eb6 1110 .disable_hub_initiated_lpm = 1,
2e55cc72
DB		 1111};
1112
d632eb1b 1113module_usb_driver(asix_driver);
2e55cc72
DB		 1114
1115MODULE_AUTHOR("David Hollis");
4ad1438f 1116MODULE_VERSION(DRIVER_VERSION);
2e55cc72
DB		 1117MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
1118MODULE_LICENSE("GPL");
1119
Linux kernel - Deliverables
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