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tcp: Document use of undefined variable.
[deliverable/linux.git] / drivers / net / usb / asix_devices.c
CommitLineData
2e55cc72
DB		 1/*
2 * ASIX AX8817X based USB 2.0 Ethernet Devices
933a27d3 3 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
2e55cc72 4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
933a27d3 5 * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
2e55cc72
DB		 6 * Copyright (c) 2002-2003 TiVo Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
607740bc 23#include "asix.h"
933a27d3
DH		 24
25#define PHY_MODE_MARVELL 0x0000
26#define MII_MARVELL_LED_CTRL 0x0018
27#define MII_MARVELL_STATUS 0x001b
28#define MII_MARVELL_CTRL 0x0014
29
30#define MARVELL_LED_MANUAL 0x0019
31
32#define MARVELL_STATUS_HWCFG 0x0004
33
34#define MARVELL_CTRL_TXDELAY 0x0002
35#define MARVELL_CTRL_RXDELAY 0x0080
2e55cc72 36
3486140e 37#define PHY_MODE_RTL8211CL 0x000C
610d885d 38
2e55cc72 39struct ax88172_int_data {
51bf2976 40 __le16 res1;
2e55cc72 41 u8 link;
51bf2976 42 __le16 res2;
2e55cc72 43 u8 status;
51bf2976 44 __le16 res3;
ba2d3587 45} __packed;
2e55cc72 46
933a27d3
DH		 47static void asix_status(struct usbnet *dev, struct urb *urb)
48{
49 struct ax88172_int_data *event;
50 int link;
51
52 if (urb->actual_length < 8)
53 return;
54
55 event = urb->transfer_buffer;
56 link = event->link & 0x01;
57 if (netif_carrier_ok(dev->net) != link) {
58 if (link) {
59 netif_carrier_on(dev->net);
60 usbnet_defer_kevent (dev, EVENT_LINK_RESET );
61 } else
62 netif_carrier_off(dev->net);
60b86755 63 netdev_dbg(dev->net, "Link Status is: %d\n", link);
933a27d3
DH		 64 }
65}
66
933a27d3
DH		 67/* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
68static u32 asix_get_phyid(struct usbnet *dev)
2e55cc72 69{
933a27d3
DH		 70 int phy_reg;
71 u32 phy_id;
a77929a2 72 int i;
2e55cc72 73
a77929a2
GG		 74 /* Poll for the rare case the FW or phy isn't ready yet. */
75 for (i = 0; i < 100; i++) {
76 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
77 if (phy_reg != 0 && phy_reg != 0xFFFF)
78 break;
79 mdelay(1);
80 }
81
82 if (phy_reg <= 0 || phy_reg == 0xFFFF)
933a27d3 83 return 0;
2e55cc72 84
933a27d3 85 phy_id = (phy_reg & 0xffff) << 16;
2e55cc72 86
933a27d3
DH		 87 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
88 if (phy_reg < 0)
89 return 0;
90
91 phy_id |= (phy_reg & 0xffff);
92
93 return phy_id;
2e55cc72
DB		 94}
95
933a27d3
DH		 96static u32 asix_get_link(struct net_device *net)
97{
98 struct usbnet *dev = netdev_priv(net);
99
100 return mii_link_ok(&dev->mii);
101}
102
103static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
104{
105 struct usbnet *dev = netdev_priv(net);
106
107 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
108}
109
110/* We need to override some ethtool_ops so we require our
111 own structure so we don't interfere with other usbnet
112 devices that may be connected at the same time. */
0fc0b732 113static const struct ethtool_ops ax88172_ethtool_ops = {
933a27d3
DH		 114 .get_drvinfo = asix_get_drvinfo,
115 .get_link = asix_get_link,
933a27d3 116 .get_msglevel = usbnet_get_msglevel,
2e55cc72 117 .set_msglevel = usbnet_set_msglevel,
48b1be6a
DH		 118 .get_wol = asix_get_wol,
119 .set_wol = asix_set_wol,
120 .get_eeprom_len = asix_get_eeprom_len,
121 .get_eeprom = asix_get_eeprom,
cb7b24cd 122 .set_eeprom = asix_set_eeprom,
c41286fd
AB		 123 .get_settings = usbnet_get_settings,
124 .set_settings = usbnet_set_settings,
125 .nway_reset = usbnet_nway_reset,
2e55cc72
DB		 126};
127
933a27d3 128static void ax88172_set_multicast(struct net_device *net)
2e55cc72
DB		 129{
130 struct usbnet *dev = netdev_priv(net);
933a27d3
DH		 131 struct asix_data *data = (struct asix_data *)&dev->data;
132 u8 rx_ctl = 0x8c;
2e55cc72 133
933a27d3
DH		 134 if (net->flags & IFF_PROMISC) {
135 rx_ctl |= 0x01;
8e95a202 136 } else if (net->flags & IFF_ALLMULTI ||
4cd24eaf 137 netdev_mc_count(net) > AX_MAX_MCAST) {
933a27d3 138 rx_ctl |= 0x02;
4cd24eaf 139 } else if (netdev_mc_empty(net)) {
933a27d3
DH		 140 /* just broadcast and directed */
141 } else {
142 /* We use the 20 byte dev->data
143 * for our 8 byte filter buffer
144 * to avoid allocating memory that
145 * is tricky to free later */
22bedad3 146 struct netdev_hw_addr *ha;
933a27d3 147 u32 crc_bits;
933a27d3
DH		 148
149 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
150
151 /* Build the multicast hash filter. */
22bedad3
JP		 152 netdev_for_each_mc_addr(ha, net) {
153 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
933a27d3
DH		 154 data->multi_filter[crc_bits >> 3] |=
155 1 << (crc_bits & 7);
933a27d3
DH		 156 }
157
158 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
159 AX_MCAST_FILTER_SIZE, data->multi_filter);
160
161 rx_ctl |= 0x10;
162 }
163
164 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
165}
166
167static int ax88172_link_reset(struct usbnet *dev)
168{
169 u8 mode;
8ae6daca 170 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3
DH		 171
172 mii_check_media(&dev->mii, 1, 1);
173 mii_ethtool_gset(&dev->mii, &ecmd);
174 mode = AX88172_MEDIUM_DEFAULT;
175
176 if (ecmd.duplex != DUPLEX_FULL)
177 mode |= ~AX88172_MEDIUM_FD;
178
8ae6daca
DD		 179 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
180 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
933a27d3
DH		 181
182 asix_write_medium_mode(dev, mode);
183
184 return 0;
2e55cc72
DB		 185}
186
1703338c
SH		 187static const struct net_device_ops ax88172_netdev_ops = {
188 .ndo_open = usbnet_open,
189 .ndo_stop = usbnet_stop,
190 .ndo_start_xmit = usbnet_start_xmit,
191 .ndo_tx_timeout = usbnet_tx_timeout,
192 .ndo_change_mtu = usbnet_change_mtu,
193 .ndo_set_mac_address = eth_mac_addr,
194 .ndo_validate_addr = eth_validate_addr,
195 .ndo_do_ioctl = asix_ioctl,
afc4b13d 196 .ndo_set_rx_mode = ax88172_set_multicast,
1703338c
SH		 197};
198
48b1be6a 199static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
2e55cc72
DB		 200{
201 int ret = 0;
51bf2976 202 u8 buf[ETH_ALEN];
2e55cc72
DB		 203 int i;
204 unsigned long gpio_bits = dev->driver_info->data;
205
206 usbnet_get_endpoints(dev,intf);
207
2e55cc72
DB		 208 /* Toggle the GPIOs in a manufacturer/model specific way */
209 for (i = 2; i >= 0; i--) {
83e1b918
GG		 210 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
211 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL);
212 if (ret < 0)
51bf2976 213 goto out;
2e55cc72
DB		 214 msleep(5);
215 }
216
83e1b918
GG		 217 ret = asix_write_rx_ctl(dev, 0x80);
218 if (ret < 0)
51bf2976 219 goto out;
2e55cc72
DB		 220
221 /* Get the MAC address */
83e1b918
GG		 222 ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
223 if (ret < 0) {
2e55cc72 224 dbg("read AX_CMD_READ_NODE_ID failed: %d", ret);
51bf2976 225 goto out;
2e55cc72
DB		 226 }
227 memcpy(dev->net->dev_addr, buf, ETH_ALEN);
228
2e55cc72
DB		 229 /* Initialize MII structure */
230 dev->mii.dev = dev->net;
48b1be6a
DH		 231 dev->mii.mdio_read = asix_mdio_read;
232 dev->mii.mdio_write = asix_mdio_write;
2e55cc72
DB		 233 dev->mii.phy_id_mask = 0x3f;
234 dev->mii.reg_num_mask = 0x1f;
933a27d3 235 dev->mii.phy_id = asix_get_phy_addr(dev);
2e55cc72 236
1703338c 237 dev->net->netdev_ops = &ax88172_netdev_ops;
48b1be6a 238 dev->net->ethtool_ops = &ax88172_ethtool_ops;
95162d65
ED		 239 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
240 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
2e55cc72 241
933a27d3
DH		 242 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
243 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
2e55cc72
DB		 244 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
245 mii_nway_restart(&dev->mii);
246
247 return 0;
51bf2976
AV		 248
249out:
2e55cc72
DB		 250 return ret;
251}
252
0fc0b732 253static const struct ethtool_ops ax88772_ethtool_ops = {
48b1be6a 254 .get_drvinfo = asix_get_drvinfo,
933a27d3 255 .get_link = asix_get_link,
2e55cc72
DB		 256 .get_msglevel = usbnet_get_msglevel,
257 .set_msglevel = usbnet_set_msglevel,
48b1be6a
DH		 258 .get_wol = asix_get_wol,
259 .set_wol = asix_set_wol,
260 .get_eeprom_len = asix_get_eeprom_len,
261 .get_eeprom = asix_get_eeprom,
cb7b24cd 262 .set_eeprom = asix_set_eeprom,
c41286fd
AB		 263 .get_settings = usbnet_get_settings,
264 .set_settings = usbnet_set_settings,
265 .nway_reset = usbnet_nway_reset,
2e55cc72
DB		 266};
267
933a27d3
DH		 268static int ax88772_link_reset(struct usbnet *dev)
269{
270 u16 mode;
8ae6daca 271 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3
DH		 272
273 mii_check_media(&dev->mii, 1, 1);
274 mii_ethtool_gset(&dev->mii, &ecmd);
275 mode = AX88772_MEDIUM_DEFAULT;
276
8ae6daca 277 if (ethtool_cmd_speed(&ecmd) != SPEED_100)
933a27d3
DH		 278 mode &= ~AX_MEDIUM_PS;
279
280 if (ecmd.duplex != DUPLEX_FULL)
281 mode &= ~AX_MEDIUM_FD;
282
8ae6daca
DD		 283 netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
284 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
933a27d3
DH		 285
286 asix_write_medium_mode(dev, mode);
287
288 return 0;
289}
290
4ad1438f 291static int ax88772_reset(struct usbnet *dev)
2e55cc72 292{
8ef66bdc 293 struct asix_data *data = (struct asix_data *)&dev->data;
d0ffff8f 294 int ret, embd_phy;
933a27d3 295 u16 rx_ctl;
2e55cc72 296
83e1b918
GG		 297 ret = asix_write_gpio(dev,
298 AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5);
299 if (ret < 0)
51bf2976 300 goto out;
2e55cc72 301
d0ffff8f 302 embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0);
4ad1438f 303
83e1b918
GG		 304 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL);
305 if (ret < 0) {
2e55cc72 306 dbg("Select PHY #1 failed: %d", ret);
51bf2976 307 goto out;
2e55cc72
DB		 308 }
309
83e1b918
GG		 310 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL);
311 if (ret < 0)
51bf2976 312 goto out;
2e55cc72
DB		 313
314 msleep(150);
83e1b918
GG		 315
316 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR);
317 if (ret < 0)
51bf2976 318 goto out;
2e55cc72
DB		 319
320 msleep(150);
4ad1438f 321
d0ffff8f 322 if (embd_phy) {
83e1b918
GG		 323 ret = asix_sw_reset(dev, AX_SWRESET_IPRL);
324 if (ret < 0)
51bf2976 325 goto out;
83e1b918
GG		 326 } else {
327 ret = asix_sw_reset(dev, AX_SWRESET_PRTE);
328 if (ret < 0)
51bf2976 329 goto out;
d0ffff8f 330 }
2e55cc72
DB		 331
332 msleep(150);
933a27d3
DH		 333 rx_ctl = asix_read_rx_ctl(dev);
334 dbg("RX_CTL is 0x%04x after software reset", rx_ctl);
83e1b918
GG		 335 ret = asix_write_rx_ctl(dev, 0x0000);
336 if (ret < 0)
51bf2976 337 goto out;
2e55cc72 338
933a27d3
DH		 339 rx_ctl = asix_read_rx_ctl(dev);
340 dbg("RX_CTL is 0x%04x setting to 0x0000", rx_ctl);
341
83e1b918
GG		 342 ret = asix_sw_reset(dev, AX_SWRESET_PRL);
343 if (ret < 0)
51bf2976 344 goto out;
2e55cc72 345
2e55cc72 346 msleep(150);
48b1be6a 347
83e1b918
GG		 348 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL);
349 if (ret < 0)
51bf2976 350 goto out;
2e55cc72 351
48b1be6a 352 msleep(150);
2e55cc72 353
933a27d3
DH		 354 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
355 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
2e55cc72
DB		 356 ADVERTISE_ALL | ADVERTISE_CSMA);
357 mii_nway_restart(&dev->mii);
358
83e1b918
GG		 359 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT);
360 if (ret < 0)
51bf2976 361 goto out;
2e55cc72 362
83e1b918 363 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
2e55cc72 364 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
83e1b918
GG		 365 AX88772_IPG2_DEFAULT, 0, NULL);
366 if (ret < 0) {
2e55cc72 367 dbg("Write IPG,IPG1,IPG2 failed: %d", ret);
51bf2976 368 goto out;
2e55cc72 369 }
2e55cc72 370
8ef66bdc
JK		 371 /* Rewrite MAC address */
372 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
373 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
374 data->mac_addr);
375 if (ret < 0)
376 goto out;
377
2e55cc72 378 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
83e1b918
GG		 379 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL);
380 if (ret < 0)
51bf2976 381 goto out;
2e55cc72 382
933a27d3
DH		 383 rx_ctl = asix_read_rx_ctl(dev);
384 dbg("RX_CTL is 0x%04x after all initializations", rx_ctl);
385
386 rx_ctl = asix_read_medium_status(dev);
387 dbg("Medium Status is 0x%04x after all initializations", rx_ctl);
388
4ad1438f
GG		 389 return 0;
390
391out:
392 return ret;
393
394}
395
396static const struct net_device_ops ax88772_netdev_ops = {
397 .ndo_open = usbnet_open,
398 .ndo_stop = usbnet_stop,
399 .ndo_start_xmit = usbnet_start_xmit,
400 .ndo_tx_timeout = usbnet_tx_timeout,
401 .ndo_change_mtu = usbnet_change_mtu,
402 .ndo_set_mac_address = asix_set_mac_address,
403 .ndo_validate_addr = eth_validate_addr,
404 .ndo_do_ioctl = asix_ioctl,
405 .ndo_set_rx_mode = asix_set_multicast,
406};
407
408static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
409{
d3665188 410 int ret, embd_phy;
4ad1438f
GG		 411 u8 buf[ETH_ALEN];
412 u32 phyid;
413
4ad1438f
GG		 414 usbnet_get_endpoints(dev,intf);
415
416 /* Get the MAC address */
83e1b918
GG		 417 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
418 if (ret < 0) {
4ad1438f 419 dbg("Failed to read MAC address: %d", ret);
83e1b918 420 return ret;
4ad1438f
GG		 421 }
422 memcpy(dev->net->dev_addr, buf, ETH_ALEN);
423
424 /* Initialize MII structure */
425 dev->mii.dev = dev->net;
426 dev->mii.mdio_read = asix_mdio_read;
427 dev->mii.mdio_write = asix_mdio_write;
428 dev->mii.phy_id_mask = 0x1f;
429 dev->mii.reg_num_mask = 0x1f;
430 dev->mii.phy_id = asix_get_phy_addr(dev);
431
4ad1438f
GG		 432 dev->net->netdev_ops = &ax88772_netdev_ops;
433 dev->net->ethtool_ops = &ax88772_ethtool_ops;
95162d65
ED		 434 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
435 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
4ad1438f 436
d3665188
GG		 437 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
438
439 /* Reset the PHY to normal operation mode */
440 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL);
441 if (ret < 0) {
442 dbg("Select PHY #1 failed: %d", ret);
443 return ret;
444 }
445
446 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL);
83e1b918
GG		 447 if (ret < 0)
448 return ret;
4ad1438f 449
d3665188
GG		 450 msleep(150);
451
452 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR);
453 if (ret < 0)
454 return ret;
455
456 msleep(150);
457
458 ret = asix_sw_reset(dev, embd_phy ? AX_SWRESET_IPRL : AX_SWRESET_PRTE);
459
460 /* Read PHYID register *AFTER* the PHY was reset properly */
461 phyid = asix_get_phyid(dev);
462 dbg("PHYID=0x%08x", phyid);
463
2e55cc72
DB		 464 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
465 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
466 /* hard_mtu is still the default - the device does not support
467 jumbo eth frames */
468 dev->rx_urb_size = 2048;
469 }
83e1b918 470
2e55cc72 471 return 0;
2e55cc72
DB		 472}
473
bc689c97 474static const struct ethtool_ops ax88178_ethtool_ops = {
933a27d3
DH		 475 .get_drvinfo = asix_get_drvinfo,
476 .get_link = asix_get_link,
933a27d3
DH		 477 .get_msglevel = usbnet_get_msglevel,
478 .set_msglevel = usbnet_set_msglevel,
479 .get_wol = asix_get_wol,
480 .set_wol = asix_set_wol,
481 .get_eeprom_len = asix_get_eeprom_len,
482 .get_eeprom = asix_get_eeprom,
cb7b24cd 483 .set_eeprom = asix_set_eeprom,
c41286fd
AB		 484 .get_settings = usbnet_get_settings,
485 .set_settings = usbnet_set_settings,
486 .nway_reset = usbnet_nway_reset,
933a27d3
DH		 487};
488
489static int marvell_phy_init(struct usbnet *dev)
2e55cc72 490{
933a27d3
DH		 491 struct asix_data *data = (struct asix_data *)&dev->data;
492 u16 reg;
2e55cc72 493
60b86755 494 netdev_dbg(dev->net, "marvell_phy_init()\n");
2e55cc72 495
933a27d3 496 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
60b86755 497 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg);
2e55cc72 498
933a27d3
DH		 499 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
500 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
2e55cc72 501
933a27d3
DH		 502 if (data->ledmode) {
503 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
504 MII_MARVELL_LED_CTRL);
60b86755 505 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg);
2e55cc72 506
933a27d3
DH		 507 reg &= 0xf8ff;
508 reg |= (1 + 0x0100);
509 asix_mdio_write(dev->net, dev->mii.phy_id,
510 MII_MARVELL_LED_CTRL, reg);
2e55cc72 511
933a27d3
DH		 512 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
513 MII_MARVELL_LED_CTRL);
60b86755 514 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg);
933a27d3
DH		 515 reg &= 0xfc0f;
516 }
2e55cc72 517
933a27d3
DH		 518 return 0;
519}
520
610d885d
GG		 521static int rtl8211cl_phy_init(struct usbnet *dev)
522{
523 struct asix_data *data = (struct asix_data *)&dev->data;
524
525 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n");
526
527 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);
528 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);
529 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,
530 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);
531 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
532
533 if (data->ledmode == 12) {
534 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);
535 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);
536 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
537 }
538
539 return 0;
540}
541
933a27d3
DH		 542static int marvell_led_status(struct usbnet *dev, u16 speed)
543{
544 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
545
60b86755 546 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg);
933a27d3
DH		 547
548 /* Clear out the center LED bits - 0x03F0 */
549 reg &= 0xfc0f;
550
551 switch (speed) {
552 case SPEED_1000:
553 reg |= 0x03e0;
554 break;
555 case SPEED_100:
556 reg |= 0x03b0;
557 break;
558 default:
559 reg |= 0x02f0;
2e55cc72
DB		 560 }
561
60b86755 562 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg);
933a27d3
DH		 563 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
564
565 return 0;
566}
567
610d885d
GG		 568static int ax88178_reset(struct usbnet *dev)
569{
570 struct asix_data *data = (struct asix_data *)&dev->data;
571 int ret;
572 __le16 eeprom;
573 u8 status;
574 int gpio0 = 0;
b2d3ad29 575 u32 phyid;
610d885d
GG		 576
577 asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status);
578 dbg("GPIO Status: 0x%04x", status);
579
580 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL);
581 asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom);
582 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL);
583
584 dbg("EEPROM index 0x17 is 0x%04x", eeprom);
585
586 if (eeprom == cpu_to_le16(0xffff)) {
587 data->phymode = PHY_MODE_MARVELL;
588 data->ledmode = 0;
589 gpio0 = 1;
590 } else {
b2d3ad29 591 data->phymode = le16_to_cpu(eeprom) & 0x7F;
610d885d
GG		 592 data->ledmode = le16_to_cpu(eeprom) >> 8;
593 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1;
594 }
595 dbg("GPIO0: %d, PhyMode: %d", gpio0, data->phymode);
596
b2d3ad29 597 /* Power up external GigaPHY through AX88178 GPIO pin */
610d885d
GG		 598 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | AX_GPIO_GPO1EN, 40);
599 if ((le16_to_cpu(eeprom) >> 8) != 1) {
600 asix_write_gpio(dev, 0x003c, 30);
601 asix_write_gpio(dev, 0x001c, 300);
602 asix_write_gpio(dev, 0x003c, 30);
603 } else {
604 dbg("gpio phymode == 1 path");
605 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30);
606 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30);
607 }
608
b2d3ad29
GG		 609 /* Read PHYID register *AFTER* powering up PHY */
610 phyid = asix_get_phyid(dev);
611 dbg("PHYID=0x%08x", phyid);
612
613 /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */
614 asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL);
615
610d885d
GG		 616 asix_sw_reset(dev, 0);
617 msleep(150);
618
619 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD);
620 msleep(150);
621
622 asix_write_rx_ctl(dev, 0);
623
624 if (data->phymode == PHY_MODE_MARVELL) {
625 marvell_phy_init(dev);
626 msleep(60);
627 } else if (data->phymode == PHY_MODE_RTL8211CL)
628 rtl8211cl_phy_init(dev);
629
630 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR,
631 BMCR_RESET | BMCR_ANENABLE);
632 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
633 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
634 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
635 ADVERTISE_1000FULL);
636
637 mii_nway_restart(&dev->mii);
638
83e1b918
GG		 639 ret = asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT);
640 if (ret < 0)
641 return ret;
610d885d 642
71bc5d94
JK		 643 /* Rewrite MAC address */
644 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
645 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
646 data->mac_addr);
647 if (ret < 0)
648 return ret;
649
83e1b918
GG		 650 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL);
651 if (ret < 0)
652 return ret;
610d885d
GG		 653
654 return 0;
610d885d
GG		 655}
656
933a27d3
DH		 657static int ax88178_link_reset(struct usbnet *dev)
658{
659 u16 mode;
8ae6daca 660 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3 661 struct asix_data *data = (struct asix_data *)&dev->data;
8ae6daca 662 u32 speed;
933a27d3 663
60b86755 664 netdev_dbg(dev->net, "ax88178_link_reset()\n");
933a27d3
DH		 665
666 mii_check_media(&dev->mii, 1, 1);
667 mii_ethtool_gset(&dev->mii, &ecmd);
668 mode = AX88178_MEDIUM_DEFAULT;
8ae6daca 669 speed = ethtool_cmd_speed(&ecmd);
933a27d3 670
8ae6daca 671 if (speed == SPEED_1000)
a7f75c0c 672 mode |= AX_MEDIUM_GM;
8ae6daca 673 else if (speed == SPEED_100)
933a27d3
DH		 674 mode |= AX_MEDIUM_PS;
675 else
676 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
677
a7f75c0c
PK		 678 mode |= AX_MEDIUM_ENCK;
679
933a27d3
DH		 680 if (ecmd.duplex == DUPLEX_FULL)
681 mode |= AX_MEDIUM_FD;
682 else
683 mode &= ~AX_MEDIUM_FD;
684
8ae6daca
DD		 685 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
686 speed, ecmd.duplex, mode);
933a27d3
DH		 687
688 asix_write_medium_mode(dev, mode);
689
690 if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
8ae6daca 691 marvell_led_status(dev, speed);
933a27d3
DH		 692
693 return 0;
694}
695
696static void ax88178_set_mfb(struct usbnet *dev)
697{
698 u16 mfb = AX_RX_CTL_MFB_16384;
699 u16 rxctl;
700 u16 medium;
701 int old_rx_urb_size = dev->rx_urb_size;
702
703 if (dev->hard_mtu < 2048) {
704 dev->rx_urb_size = 2048;
705 mfb = AX_RX_CTL_MFB_2048;
706 } else if (dev->hard_mtu < 4096) {
707 dev->rx_urb_size = 4096;
708 mfb = AX_RX_CTL_MFB_4096;
709 } else if (dev->hard_mtu < 8192) {
710 dev->rx_urb_size = 8192;
711 mfb = AX_RX_CTL_MFB_8192;
712 } else if (dev->hard_mtu < 16384) {
713 dev->rx_urb_size = 16384;
714 mfb = AX_RX_CTL_MFB_16384;
2e55cc72 715 }
933a27d3
DH		 716
717 rxctl = asix_read_rx_ctl(dev);
718 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb);
719
720 medium = asix_read_medium_status(dev);
721 if (dev->net->mtu > 1500)
722 medium |= AX_MEDIUM_JFE;
723 else
724 medium &= ~AX_MEDIUM_JFE;
725 asix_write_medium_mode(dev, medium);
726
727 if (dev->rx_urb_size > old_rx_urb_size)
728 usbnet_unlink_rx_urbs(dev);
2e55cc72
DB		 729}
730
933a27d3 731static int ax88178_change_mtu(struct net_device *net, int new_mtu)
2e55cc72 732{
933a27d3
DH		 733 struct usbnet *dev = netdev_priv(net);
734 int ll_mtu = new_mtu + net->hard_header_len + 4;
2e55cc72 735
60b86755 736 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu);
2e55cc72 737
933a27d3
DH		 738 if (new_mtu <= 0 || ll_mtu > 16384)
739 return -EINVAL;
740
741 if ((ll_mtu % dev->maxpacket) == 0)
742 return -EDOM;
743
744 net->mtu = new_mtu;
745 dev->hard_mtu = net->mtu + net->hard_header_len;
746 ax88178_set_mfb(dev);
747
748 return 0;
749}
750
1703338c
SH		 751static const struct net_device_ops ax88178_netdev_ops = {
752 .ndo_open = usbnet_open,
753 .ndo_stop = usbnet_stop,
754 .ndo_start_xmit = usbnet_start_xmit,
755 .ndo_tx_timeout = usbnet_tx_timeout,
7f29a3ba 756 .ndo_set_mac_address = asix_set_mac_address,
1703338c 757 .ndo_validate_addr = eth_validate_addr,
afc4b13d 758 .ndo_set_rx_mode = asix_set_multicast,
1703338c
SH		 759 .ndo_do_ioctl = asix_ioctl,
760 .ndo_change_mtu = ax88178_change_mtu,
761};
762
933a27d3
DH		 763static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
764{
933a27d3 765 int ret;
51bf2976 766 u8 buf[ETH_ALEN];
933a27d3
DH		 767
768 usbnet_get_endpoints(dev,intf);
769
933a27d3 770 /* Get the MAC address */
83e1b918
GG		 771 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
772 if (ret < 0) {
933a27d3 773 dbg("Failed to read MAC address: %d", ret);
83e1b918 774 return ret;
2e55cc72 775 }
933a27d3 776 memcpy(dev->net->dev_addr, buf, ETH_ALEN);
2e55cc72 777
933a27d3
DH		 778 /* Initialize MII structure */
779 dev->mii.dev = dev->net;
780 dev->mii.mdio_read = asix_mdio_read;
781 dev->mii.mdio_write = asix_mdio_write;
782 dev->mii.phy_id_mask = 0x1f;
783 dev->mii.reg_num_mask = 0xff;
784 dev->mii.supports_gmii = 1;
933a27d3 785 dev->mii.phy_id = asix_get_phy_addr(dev);
1703338c
SH		 786
787 dev->net->netdev_ops = &ax88178_netdev_ops;
933a27d3 788 dev->net->ethtool_ops = &ax88178_ethtool_ops;
2e55cc72 789
b2d3ad29
GG		 790 /* Blink LEDS so users know driver saw dongle */
791 asix_sw_reset(dev, 0);
792 msleep(150);
2e55cc72 793
b2d3ad29
GG		 794 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD);
795 msleep(150);
933a27d3
DH		 796
797 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
798 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
799 /* hard_mtu is still the default - the device does not support
800 jumbo eth frames */
801 dev->rx_urb_size = 2048;
802 }
933a27d3 803
83e1b918 804 return 0;
2e55cc72
DB		 805}
806
807static const struct driver_info ax8817x_info = {
808 .description = "ASIX AX8817x USB 2.0 Ethernet",
48b1be6a
DH		 809 .bind = ax88172_bind,
810 .status = asix_status,
2e55cc72
DB		 811 .link_reset = ax88172_link_reset,
812 .reset = ax88172_link_reset,
37e8273c 813 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 814 .data = 0x00130103,
815};
816
817static const struct driver_info dlink_dub_e100_info = {
818 .description = "DLink DUB-E100 USB Ethernet",
48b1be6a
DH		 819 .bind = ax88172_bind,
820 .status = asix_status,
2e55cc72
DB		 821 .link_reset = ax88172_link_reset,
822 .reset = ax88172_link_reset,
37e8273c 823 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 824 .data = 0x009f9d9f,
825};
826
827static const struct driver_info netgear_fa120_info = {
828 .description = "Netgear FA-120 USB Ethernet",
48b1be6a
DH		 829 .bind = ax88172_bind,
830 .status = asix_status,
2e55cc72
DB		 831 .link_reset = ax88172_link_reset,
832 .reset = ax88172_link_reset,
37e8273c 833 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 834 .data = 0x00130103,
835};
836
837static const struct driver_info hawking_uf200_info = {
838 .description = "Hawking UF200 USB Ethernet",
48b1be6a
DH		 839 .bind = ax88172_bind,
840 .status = asix_status,
2e55cc72
DB		 841 .link_reset = ax88172_link_reset,
842 .reset = ax88172_link_reset,
37e8273c 843 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 844 .data = 0x001f1d1f,
845};
846
847static const struct driver_info ax88772_info = {
848 .description = "ASIX AX88772 USB 2.0 Ethernet",
849 .bind = ax88772_bind,
48b1be6a 850 .status = asix_status,
2e55cc72 851 .link_reset = ax88772_link_reset,
4ad1438f 852 .reset = ax88772_reset,
a9e0aca4 853 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET,
933a27d3
DH		 854 .rx_fixup = asix_rx_fixup,
855 .tx_fixup = asix_tx_fixup,
856};
857
858static const struct driver_info ax88178_info = {
859 .description = "ASIX AX88178 USB 2.0 Ethernet",
860 .bind = ax88178_bind,
861 .status = asix_status,
862 .link_reset = ax88178_link_reset,
610d885d 863 .reset = ax88178_reset,
37e8273c 864 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR,
933a27d3
DH		 865 .rx_fixup = asix_rx_fixup,
866 .tx_fixup = asix_tx_fixup,
2e55cc72
DB		 867};
868
16626b0c
CR		 869extern const struct driver_info ax88172a_info;
870
2e55cc72
DB		 871static const struct usb_device_id products [] = {
872{
873 // Linksys USB200M
874 USB_DEVICE (0x077b, 0x2226),
875 .driver_info = (unsigned long) &ax8817x_info,
876}, {
877 // Netgear FA120
878 USB_DEVICE (0x0846, 0x1040),
879 .driver_info = (unsigned long) &netgear_fa120_info,
880}, {
881 // DLink DUB-E100
882 USB_DEVICE (0x2001, 0x1a00),
883 .driver_info = (unsigned long) &dlink_dub_e100_info,
884}, {
885 // Intellinet, ST Lab USB Ethernet
886 USB_DEVICE (0x0b95, 0x1720),
887 .driver_info = (unsigned long) &ax8817x_info,
888}, {
889 // Hawking UF200, TrendNet TU2-ET100
890 USB_DEVICE (0x07b8, 0x420a),
891 .driver_info = (unsigned long) &hawking_uf200_info,
892}, {
39c4b38c
DH		 893 // Billionton Systems, USB2AR
894 USB_DEVICE (0x08dd, 0x90ff),
895 .driver_info = (unsigned long) &ax8817x_info,
2e55cc72
DB		 896}, {
897 // ATEN UC210T
898 USB_DEVICE (0x0557, 0x2009),
899 .driver_info = (unsigned long) &ax8817x_info,
900}, {
901 // Buffalo LUA-U2-KTX
902 USB_DEVICE (0x0411, 0x003d),
903 .driver_info = (unsigned long) &ax8817x_info,
ac7b77f1
MD		 904}, {
905 // Buffalo LUA-U2-GT 10/100/1000
906 USB_DEVICE (0x0411, 0x006e),
907 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB		 908}, {
909 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
910 USB_DEVICE (0x6189, 0x182d),
911 .driver_info = (unsigned long) &ax8817x_info,
4e503919
JN		 912}, {
913 // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter"
914 USB_DEVICE (0x0df6, 0x0056),
915 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB		 916}, {
917 // corega FEther USB2-TX
918 USB_DEVICE (0x07aa, 0x0017),
919 .driver_info = (unsigned long) &ax8817x_info,
920}, {
921 // Surecom EP-1427X-2
922 USB_DEVICE (0x1189, 0x0893),
923 .driver_info = (unsigned long) &ax8817x_info,
924}, {
925 // goodway corp usb gwusb2e
926 USB_DEVICE (0x1631, 0x6200),
927 .driver_info = (unsigned long) &ax8817x_info,
39c4b38c
DH		 928}, {
929 // JVC MP-PRX1 Port Replicator
930 USB_DEVICE (0x04f1, 0x3008),
931 .driver_info = (unsigned long) &ax8817x_info,
30885909
MV		 932}, {
933 // ASIX AX88772B 10/100
934 USB_DEVICE (0x0b95, 0x772b),
935 .driver_info = (unsigned long) &ax88772_info,
2e55cc72
DB		 936}, {
937 // ASIX AX88772 10/100
39c4b38c
DH		 938 USB_DEVICE (0x0b95, 0x7720),
939 .driver_info = (unsigned long) &ax88772_info,
7327413c
EW		 940}, {
941 // ASIX AX88178 10/100/1000
942 USB_DEVICE (0x0b95, 0x1780),
933a27d3 943 .driver_info = (unsigned long) &ax88178_info,
f4680d3d
AE		 944}, {
945 // Logitec LAN-GTJ/U2A
946 USB_DEVICE (0x0789, 0x0160),
947 .driver_info = (unsigned long) &ax88178_info,
5e0f76c6
DH		 948}, {
949 // Linksys USB200M Rev 2
950 USB_DEVICE (0x13b1, 0x0018),
951 .driver_info = (unsigned long) &ax88772_info,
5732ce84
DH		 952}, {
953 // 0Q0 cable ethernet
954 USB_DEVICE (0x1557, 0x7720),
955 .driver_info = (unsigned long) &ax88772_info,
933a27d3
DH		 956}, {
957 // DLink DUB-E100 H/W Ver B1
958 USB_DEVICE (0x07d1, 0x3c05),
959 .driver_info = (unsigned long) &ax88772_info,
b923e7fc
DH		 960}, {
961 // DLink DUB-E100 H/W Ver B1 Alternate
962 USB_DEVICE (0x2001, 0x3c05),
963 .driver_info = (unsigned long) &ax88772_info,
933a27d3
DH		 964}, {
965 // Linksys USB1000
966 USB_DEVICE (0x1737, 0x0039),
967 .driver_info = (unsigned long) &ax88178_info,
b29cf31d
YH		 968}, {
969 // IO-DATA ETG-US2
970 USB_DEVICE (0x04bb, 0x0930),
971 .driver_info = (unsigned long) &ax88178_info,
2ed22bc2
DH		 972}, {
973 // Belkin F5D5055
974 USB_DEVICE(0x050d, 0x5055),
975 .driver_info = (unsigned long) &ax88178_info,
3d60efb5
AN		 976}, {
977 // Apple USB Ethernet Adapter
978 USB_DEVICE(0x05ac, 0x1402),
979 .driver_info = (unsigned long) &ax88772_info,
ccf95402
JC		 980}, {
981 // Cables-to-Go USB Ethernet Adapter
982 USB_DEVICE(0x0b95, 0x772a),
983 .driver_info = (unsigned long) &ax88772_info,
fef7cc08
GKH		 984}, {
985 // ABOCOM for pci
986 USB_DEVICE(0x14ea, 0xab11),
987 .driver_info = (unsigned long) &ax88178_info,
988}, {
989 // ASIX 88772a
990 USB_DEVICE(0x0db0, 0xa877),
991 .driver_info = (unsigned long) &ax88772_info,
e8303a3b
AJ		 992}, {
993 // Asus USB Ethernet Adapter
994 USB_DEVICE (0x0b95, 0x7e2b),
995 .driver_info = (unsigned long) &ax88772_info,
16626b0c
CR		 996}, {
997 /* ASIX 88172a demo board */
998 USB_DEVICE(0x0b95, 0x172a),
999 .driver_info = (unsigned long) &ax88172a_info,
2e55cc72
DB		 1000},
1001 { }, // END
1002};
1003MODULE_DEVICE_TABLE(usb, products);
1004
1005static struct usb_driver asix_driver = {
83e1b918 1006 .name = DRIVER_NAME,
2e55cc72
DB		 1007 .id_table = products,
1008 .probe = usbnet_probe,
1009 .suspend = usbnet_suspend,
1010 .resume = usbnet_resume,
1011 .disconnect = usbnet_disconnect,
a11a6544 1012 .supports_autosuspend = 1,
e1f12eb6 1013 .disable_hub_initiated_lpm = 1,
2e55cc72
DB		 1014};
1015
d632eb1b 1016module_usb_driver(asix_driver);
2e55cc72
DB		 1017
1018MODULE_AUTHOR("David Hollis");
4ad1438f 1019MODULE_VERSION(DRIVER_VERSION);
2e55cc72
DB		 1020MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
1021MODULE_LICENSE("GPL");
1022
Linux kernel - Deliverables
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