Commit | Line | Data |
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2e55cc72 DB |
1 | /* |
2 | * ASIX AX8817X based USB 2.0 Ethernet Devices | |
933a27d3 | 3 | * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com> |
2e55cc72 | 4 | * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net> |
933a27d3 | 5 | * Copyright (C) 2006 James Painter <jamie.painter@iname.com> |
2e55cc72 DB |
6 | * Copyright (c) 2002-2003 TiVo Inc. |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
607740bc | 23 | #include "asix.h" |
933a27d3 DH |
24 | |
25 | #define PHY_MODE_MARVELL 0x0000 | |
26 | #define MII_MARVELL_LED_CTRL 0x0018 | |
27 | #define MII_MARVELL_STATUS 0x001b | |
28 | #define MII_MARVELL_CTRL 0x0014 | |
29 | ||
30 | #define MARVELL_LED_MANUAL 0x0019 | |
31 | ||
32 | #define MARVELL_STATUS_HWCFG 0x0004 | |
33 | ||
34 | #define MARVELL_CTRL_TXDELAY 0x0002 | |
35 | #define MARVELL_CTRL_RXDELAY 0x0080 | |
2e55cc72 | 36 | |
3486140e | 37 | #define PHY_MODE_RTL8211CL 0x000C |
610d885d | 38 | |
2e55cc72 | 39 | struct ax88172_int_data { |
51bf2976 | 40 | __le16 res1; |
2e55cc72 | 41 | u8 link; |
51bf2976 | 42 | __le16 res2; |
2e55cc72 | 43 | u8 status; |
51bf2976 | 44 | __le16 res3; |
ba2d3587 | 45 | } __packed; |
2e55cc72 | 46 | |
933a27d3 DH |
47 | static void asix_status(struct usbnet *dev, struct urb *urb) |
48 | { | |
49 | struct ax88172_int_data *event; | |
50 | int link; | |
51 | ||
52 | if (urb->actual_length < 8) | |
53 | return; | |
54 | ||
55 | event = urb->transfer_buffer; | |
56 | link = event->link & 0x01; | |
57 | if (netif_carrier_ok(dev->net) != link) { | |
58 | if (link) { | |
59 | netif_carrier_on(dev->net); | |
60 | usbnet_defer_kevent (dev, EVENT_LINK_RESET ); | |
61 | } else | |
62 | netif_carrier_off(dev->net); | |
60b86755 | 63 | netdev_dbg(dev->net, "Link Status is: %d\n", link); |
933a27d3 DH |
64 | } |
65 | } | |
66 | ||
933a27d3 DH |
67 | /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */ |
68 | static u32 asix_get_phyid(struct usbnet *dev) | |
2e55cc72 | 69 | { |
933a27d3 DH |
70 | int phy_reg; |
71 | u32 phy_id; | |
a77929a2 | 72 | int i; |
2e55cc72 | 73 | |
a77929a2 GG |
74 | /* Poll for the rare case the FW or phy isn't ready yet. */ |
75 | for (i = 0; i < 100; i++) { | |
76 | phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1); | |
77 | if (phy_reg != 0 && phy_reg != 0xFFFF) | |
78 | break; | |
79 | mdelay(1); | |
80 | } | |
81 | ||
82 | if (phy_reg <= 0 || phy_reg == 0xFFFF) | |
933a27d3 | 83 | return 0; |
2e55cc72 | 84 | |
933a27d3 | 85 | phy_id = (phy_reg & 0xffff) << 16; |
2e55cc72 | 86 | |
933a27d3 DH |
87 | phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2); |
88 | if (phy_reg < 0) | |
89 | return 0; | |
90 | ||
91 | phy_id |= (phy_reg & 0xffff); | |
92 | ||
93 | return phy_id; | |
2e55cc72 DB |
94 | } |
95 | ||
933a27d3 DH |
96 | static u32 asix_get_link(struct net_device *net) |
97 | { | |
98 | struct usbnet *dev = netdev_priv(net); | |
99 | ||
100 | return mii_link_ok(&dev->mii); | |
101 | } | |
102 | ||
103 | static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd) | |
104 | { | |
105 | struct usbnet *dev = netdev_priv(net); | |
106 | ||
107 | return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); | |
108 | } | |
109 | ||
110 | /* We need to override some ethtool_ops so we require our | |
111 | own structure so we don't interfere with other usbnet | |
112 | devices that may be connected at the same time. */ | |
0fc0b732 | 113 | static const struct ethtool_ops ax88172_ethtool_ops = { |
933a27d3 DH |
114 | .get_drvinfo = asix_get_drvinfo, |
115 | .get_link = asix_get_link, | |
933a27d3 | 116 | .get_msglevel = usbnet_get_msglevel, |
2e55cc72 | 117 | .set_msglevel = usbnet_set_msglevel, |
48b1be6a DH |
118 | .get_wol = asix_get_wol, |
119 | .set_wol = asix_set_wol, | |
120 | .get_eeprom_len = asix_get_eeprom_len, | |
121 | .get_eeprom = asix_get_eeprom, | |
cb7b24cd | 122 | .set_eeprom = asix_set_eeprom, |
c41286fd AB |
123 | .get_settings = usbnet_get_settings, |
124 | .set_settings = usbnet_set_settings, | |
125 | .nway_reset = usbnet_nway_reset, | |
2e55cc72 DB |
126 | }; |
127 | ||
933a27d3 | 128 | static void ax88172_set_multicast(struct net_device *net) |
2e55cc72 DB |
129 | { |
130 | struct usbnet *dev = netdev_priv(net); | |
933a27d3 DH |
131 | struct asix_data *data = (struct asix_data *)&dev->data; |
132 | u8 rx_ctl = 0x8c; | |
2e55cc72 | 133 | |
933a27d3 DH |
134 | if (net->flags & IFF_PROMISC) { |
135 | rx_ctl |= 0x01; | |
8e95a202 | 136 | } else if (net->flags & IFF_ALLMULTI || |
4cd24eaf | 137 | netdev_mc_count(net) > AX_MAX_MCAST) { |
933a27d3 | 138 | rx_ctl |= 0x02; |
4cd24eaf | 139 | } else if (netdev_mc_empty(net)) { |
933a27d3 DH |
140 | /* just broadcast and directed */ |
141 | } else { | |
142 | /* We use the 20 byte dev->data | |
143 | * for our 8 byte filter buffer | |
144 | * to avoid allocating memory that | |
145 | * is tricky to free later */ | |
22bedad3 | 146 | struct netdev_hw_addr *ha; |
933a27d3 | 147 | u32 crc_bits; |
933a27d3 DH |
148 | |
149 | memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE); | |
150 | ||
151 | /* Build the multicast hash filter. */ | |
22bedad3 JP |
152 | netdev_for_each_mc_addr(ha, net) { |
153 | crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
933a27d3 DH |
154 | data->multi_filter[crc_bits >> 3] |= |
155 | 1 << (crc_bits & 7); | |
933a27d3 DH |
156 | } |
157 | ||
158 | asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0, | |
159 | AX_MCAST_FILTER_SIZE, data->multi_filter); | |
160 | ||
161 | rx_ctl |= 0x10; | |
162 | } | |
163 | ||
164 | asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL); | |
165 | } | |
166 | ||
167 | static int ax88172_link_reset(struct usbnet *dev) | |
168 | { | |
169 | u8 mode; | |
8ae6daca | 170 | struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; |
933a27d3 DH |
171 | |
172 | mii_check_media(&dev->mii, 1, 1); | |
173 | mii_ethtool_gset(&dev->mii, &ecmd); | |
174 | mode = AX88172_MEDIUM_DEFAULT; | |
175 | ||
176 | if (ecmd.duplex != DUPLEX_FULL) | |
177 | mode |= ~AX88172_MEDIUM_FD; | |
178 | ||
8ae6daca DD |
179 | netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", |
180 | ethtool_cmd_speed(&ecmd), ecmd.duplex, mode); | |
933a27d3 DH |
181 | |
182 | asix_write_medium_mode(dev, mode); | |
183 | ||
184 | return 0; | |
2e55cc72 DB |
185 | } |
186 | ||
1703338c SH |
187 | static const struct net_device_ops ax88172_netdev_ops = { |
188 | .ndo_open = usbnet_open, | |
189 | .ndo_stop = usbnet_stop, | |
190 | .ndo_start_xmit = usbnet_start_xmit, | |
191 | .ndo_tx_timeout = usbnet_tx_timeout, | |
192 | .ndo_change_mtu = usbnet_change_mtu, | |
193 | .ndo_set_mac_address = eth_mac_addr, | |
194 | .ndo_validate_addr = eth_validate_addr, | |
195 | .ndo_do_ioctl = asix_ioctl, | |
afc4b13d | 196 | .ndo_set_rx_mode = ax88172_set_multicast, |
1703338c SH |
197 | }; |
198 | ||
48b1be6a | 199 | static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf) |
2e55cc72 DB |
200 | { |
201 | int ret = 0; | |
51bf2976 | 202 | u8 buf[ETH_ALEN]; |
2e55cc72 DB |
203 | int i; |
204 | unsigned long gpio_bits = dev->driver_info->data; | |
205 | ||
206 | usbnet_get_endpoints(dev,intf); | |
207 | ||
2e55cc72 DB |
208 | /* Toggle the GPIOs in a manufacturer/model specific way */ |
209 | for (i = 2; i >= 0; i--) { | |
83e1b918 GG |
210 | ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, |
211 | (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL); | |
212 | if (ret < 0) | |
51bf2976 | 213 | goto out; |
2e55cc72 DB |
214 | msleep(5); |
215 | } | |
216 | ||
83e1b918 GG |
217 | ret = asix_write_rx_ctl(dev, 0x80); |
218 | if (ret < 0) | |
51bf2976 | 219 | goto out; |
2e55cc72 DB |
220 | |
221 | /* Get the MAC address */ | |
83e1b918 GG |
222 | ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf); |
223 | if (ret < 0) { | |
49ae25b0 GKH |
224 | netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n", |
225 | ret); | |
51bf2976 | 226 | goto out; |
2e55cc72 DB |
227 | } |
228 | memcpy(dev->net->dev_addr, buf, ETH_ALEN); | |
229 | ||
2e55cc72 DB |
230 | /* Initialize MII structure */ |
231 | dev->mii.dev = dev->net; | |
48b1be6a DH |
232 | dev->mii.mdio_read = asix_mdio_read; |
233 | dev->mii.mdio_write = asix_mdio_write; | |
2e55cc72 DB |
234 | dev->mii.phy_id_mask = 0x3f; |
235 | dev->mii.reg_num_mask = 0x1f; | |
933a27d3 | 236 | dev->mii.phy_id = asix_get_phy_addr(dev); |
2e55cc72 | 237 | |
1703338c | 238 | dev->net->netdev_ops = &ax88172_netdev_ops; |
48b1be6a | 239 | dev->net->ethtool_ops = &ax88172_ethtool_ops; |
95162d65 ED |
240 | dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */ |
241 | dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */ | |
2e55cc72 | 242 | |
933a27d3 DH |
243 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET); |
244 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, | |
2e55cc72 DB |
245 | ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); |
246 | mii_nway_restart(&dev->mii); | |
247 | ||
248 | return 0; | |
51bf2976 AV |
249 | |
250 | out: | |
2e55cc72 DB |
251 | return ret; |
252 | } | |
253 | ||
0fc0b732 | 254 | static const struct ethtool_ops ax88772_ethtool_ops = { |
48b1be6a | 255 | .get_drvinfo = asix_get_drvinfo, |
933a27d3 | 256 | .get_link = asix_get_link, |
2e55cc72 DB |
257 | .get_msglevel = usbnet_get_msglevel, |
258 | .set_msglevel = usbnet_set_msglevel, | |
48b1be6a DH |
259 | .get_wol = asix_get_wol, |
260 | .set_wol = asix_set_wol, | |
261 | .get_eeprom_len = asix_get_eeprom_len, | |
262 | .get_eeprom = asix_get_eeprom, | |
cb7b24cd | 263 | .set_eeprom = asix_set_eeprom, |
c41286fd AB |
264 | .get_settings = usbnet_get_settings, |
265 | .set_settings = usbnet_set_settings, | |
266 | .nway_reset = usbnet_nway_reset, | |
2e55cc72 DB |
267 | }; |
268 | ||
933a27d3 DH |
269 | static int ax88772_link_reset(struct usbnet *dev) |
270 | { | |
271 | u16 mode; | |
8ae6daca | 272 | struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; |
933a27d3 DH |
273 | |
274 | mii_check_media(&dev->mii, 1, 1); | |
275 | mii_ethtool_gset(&dev->mii, &ecmd); | |
276 | mode = AX88772_MEDIUM_DEFAULT; | |
277 | ||
8ae6daca | 278 | if (ethtool_cmd_speed(&ecmd) != SPEED_100) |
933a27d3 DH |
279 | mode &= ~AX_MEDIUM_PS; |
280 | ||
281 | if (ecmd.duplex != DUPLEX_FULL) | |
282 | mode &= ~AX_MEDIUM_FD; | |
283 | ||
8ae6daca DD |
284 | netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", |
285 | ethtool_cmd_speed(&ecmd), ecmd.duplex, mode); | |
933a27d3 DH |
286 | |
287 | asix_write_medium_mode(dev, mode); | |
288 | ||
289 | return 0; | |
290 | } | |
291 | ||
4ad1438f | 292 | static int ax88772_reset(struct usbnet *dev) |
2e55cc72 | 293 | { |
8ef66bdc | 294 | struct asix_data *data = (struct asix_data *)&dev->data; |
d0ffff8f | 295 | int ret, embd_phy; |
933a27d3 | 296 | u16 rx_ctl; |
2e55cc72 | 297 | |
83e1b918 GG |
298 | ret = asix_write_gpio(dev, |
299 | AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5); | |
300 | if (ret < 0) | |
51bf2976 | 301 | goto out; |
2e55cc72 | 302 | |
d0ffff8f | 303 | embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0); |
4ad1438f | 304 | |
83e1b918 GG |
305 | ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL); |
306 | if (ret < 0) { | |
49ae25b0 | 307 | netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret); |
51bf2976 | 308 | goto out; |
2e55cc72 DB |
309 | } |
310 | ||
83e1b918 GG |
311 | ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL); |
312 | if (ret < 0) | |
51bf2976 | 313 | goto out; |
2e55cc72 DB |
314 | |
315 | msleep(150); | |
83e1b918 GG |
316 | |
317 | ret = asix_sw_reset(dev, AX_SWRESET_CLEAR); | |
318 | if (ret < 0) | |
51bf2976 | 319 | goto out; |
2e55cc72 DB |
320 | |
321 | msleep(150); | |
4ad1438f | 322 | |
d0ffff8f | 323 | if (embd_phy) { |
83e1b918 GG |
324 | ret = asix_sw_reset(dev, AX_SWRESET_IPRL); |
325 | if (ret < 0) | |
51bf2976 | 326 | goto out; |
83e1b918 GG |
327 | } else { |
328 | ret = asix_sw_reset(dev, AX_SWRESET_PRTE); | |
329 | if (ret < 0) | |
51bf2976 | 330 | goto out; |
d0ffff8f | 331 | } |
2e55cc72 DB |
332 | |
333 | msleep(150); | |
933a27d3 | 334 | rx_ctl = asix_read_rx_ctl(dev); |
49ae25b0 | 335 | netdev_dbg(dev->net, "RX_CTL is 0x%04x after software reset\n", rx_ctl); |
83e1b918 GG |
336 | ret = asix_write_rx_ctl(dev, 0x0000); |
337 | if (ret < 0) | |
51bf2976 | 338 | goto out; |
2e55cc72 | 339 | |
933a27d3 | 340 | rx_ctl = asix_read_rx_ctl(dev); |
49ae25b0 | 341 | netdev_dbg(dev->net, "RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl); |
933a27d3 | 342 | |
83e1b918 GG |
343 | ret = asix_sw_reset(dev, AX_SWRESET_PRL); |
344 | if (ret < 0) | |
51bf2976 | 345 | goto out; |
2e55cc72 | 346 | |
2e55cc72 | 347 | msleep(150); |
48b1be6a | 348 | |
83e1b918 GG |
349 | ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL); |
350 | if (ret < 0) | |
51bf2976 | 351 | goto out; |
2e55cc72 | 352 | |
48b1be6a | 353 | msleep(150); |
2e55cc72 | 354 | |
933a27d3 DH |
355 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET); |
356 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, | |
2e55cc72 DB |
357 | ADVERTISE_ALL | ADVERTISE_CSMA); |
358 | mii_nway_restart(&dev->mii); | |
359 | ||
83e1b918 GG |
360 | ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT); |
361 | if (ret < 0) | |
51bf2976 | 362 | goto out; |
2e55cc72 | 363 | |
83e1b918 | 364 | ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0, |
2e55cc72 | 365 | AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, |
83e1b918 GG |
366 | AX88772_IPG2_DEFAULT, 0, NULL); |
367 | if (ret < 0) { | |
49ae25b0 | 368 | netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret); |
51bf2976 | 369 | goto out; |
2e55cc72 | 370 | } |
2e55cc72 | 371 | |
8ef66bdc JK |
372 | /* Rewrite MAC address */ |
373 | memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN); | |
374 | ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, | |
375 | data->mac_addr); | |
376 | if (ret < 0) | |
377 | goto out; | |
378 | ||
2e55cc72 | 379 | /* Set RX_CTL to default values with 2k buffer, and enable cactus */ |
83e1b918 GG |
380 | ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL); |
381 | if (ret < 0) | |
51bf2976 | 382 | goto out; |
2e55cc72 | 383 | |
933a27d3 | 384 | rx_ctl = asix_read_rx_ctl(dev); |
49ae25b0 GKH |
385 | netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n", |
386 | rx_ctl); | |
933a27d3 DH |
387 | |
388 | rx_ctl = asix_read_medium_status(dev); | |
49ae25b0 GKH |
389 | netdev_dbg(dev->net, |
390 | "Medium Status is 0x%04x after all initializations\n", | |
391 | rx_ctl); | |
933a27d3 | 392 | |
4ad1438f GG |
393 | return 0; |
394 | ||
395 | out: | |
396 | return ret; | |
397 | ||
398 | } | |
399 | ||
400 | static const struct net_device_ops ax88772_netdev_ops = { | |
401 | .ndo_open = usbnet_open, | |
402 | .ndo_stop = usbnet_stop, | |
403 | .ndo_start_xmit = usbnet_start_xmit, | |
404 | .ndo_tx_timeout = usbnet_tx_timeout, | |
405 | .ndo_change_mtu = usbnet_change_mtu, | |
406 | .ndo_set_mac_address = asix_set_mac_address, | |
407 | .ndo_validate_addr = eth_validate_addr, | |
408 | .ndo_do_ioctl = asix_ioctl, | |
409 | .ndo_set_rx_mode = asix_set_multicast, | |
410 | }; | |
411 | ||
412 | static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf) | |
413 | { | |
d3665188 | 414 | int ret, embd_phy; |
4ad1438f GG |
415 | u8 buf[ETH_ALEN]; |
416 | u32 phyid; | |
417 | ||
4ad1438f GG |
418 | usbnet_get_endpoints(dev,intf); |
419 | ||
420 | /* Get the MAC address */ | |
83e1b918 GG |
421 | ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf); |
422 | if (ret < 0) { | |
49ae25b0 | 423 | netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret); |
83e1b918 | 424 | return ret; |
4ad1438f GG |
425 | } |
426 | memcpy(dev->net->dev_addr, buf, ETH_ALEN); | |
427 | ||
428 | /* Initialize MII structure */ | |
429 | dev->mii.dev = dev->net; | |
430 | dev->mii.mdio_read = asix_mdio_read; | |
431 | dev->mii.mdio_write = asix_mdio_write; | |
432 | dev->mii.phy_id_mask = 0x1f; | |
433 | dev->mii.reg_num_mask = 0x1f; | |
434 | dev->mii.phy_id = asix_get_phy_addr(dev); | |
435 | ||
4ad1438f GG |
436 | dev->net->netdev_ops = &ax88772_netdev_ops; |
437 | dev->net->ethtool_ops = &ax88772_ethtool_ops; | |
95162d65 ED |
438 | dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */ |
439 | dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */ | |
4ad1438f | 440 | |
d3665188 GG |
441 | embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0); |
442 | ||
443 | /* Reset the PHY to normal operation mode */ | |
444 | ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL); | |
445 | if (ret < 0) { | |
49ae25b0 | 446 | netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret); |
d3665188 GG |
447 | return ret; |
448 | } | |
449 | ||
450 | ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL); | |
83e1b918 GG |
451 | if (ret < 0) |
452 | return ret; | |
4ad1438f | 453 | |
d3665188 GG |
454 | msleep(150); |
455 | ||
456 | ret = asix_sw_reset(dev, AX_SWRESET_CLEAR); | |
457 | if (ret < 0) | |
458 | return ret; | |
459 | ||
460 | msleep(150); | |
461 | ||
462 | ret = asix_sw_reset(dev, embd_phy ? AX_SWRESET_IPRL : AX_SWRESET_PRTE); | |
463 | ||
464 | /* Read PHYID register *AFTER* the PHY was reset properly */ | |
465 | phyid = asix_get_phyid(dev); | |
49ae25b0 | 466 | netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid); |
d3665188 | 467 | |
2e55cc72 DB |
468 | /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ |
469 | if (dev->driver_info->flags & FLAG_FRAMING_AX) { | |
470 | /* hard_mtu is still the default - the device does not support | |
471 | jumbo eth frames */ | |
472 | dev->rx_urb_size = 2048; | |
473 | } | |
83e1b918 | 474 | |
2e55cc72 | 475 | return 0; |
2e55cc72 DB |
476 | } |
477 | ||
bc689c97 | 478 | static const struct ethtool_ops ax88178_ethtool_ops = { |
933a27d3 DH |
479 | .get_drvinfo = asix_get_drvinfo, |
480 | .get_link = asix_get_link, | |
933a27d3 DH |
481 | .get_msglevel = usbnet_get_msglevel, |
482 | .set_msglevel = usbnet_set_msglevel, | |
483 | .get_wol = asix_get_wol, | |
484 | .set_wol = asix_set_wol, | |
485 | .get_eeprom_len = asix_get_eeprom_len, | |
486 | .get_eeprom = asix_get_eeprom, | |
cb7b24cd | 487 | .set_eeprom = asix_set_eeprom, |
c41286fd AB |
488 | .get_settings = usbnet_get_settings, |
489 | .set_settings = usbnet_set_settings, | |
490 | .nway_reset = usbnet_nway_reset, | |
933a27d3 DH |
491 | }; |
492 | ||
493 | static int marvell_phy_init(struct usbnet *dev) | |
2e55cc72 | 494 | { |
933a27d3 DH |
495 | struct asix_data *data = (struct asix_data *)&dev->data; |
496 | u16 reg; | |
2e55cc72 | 497 | |
60b86755 | 498 | netdev_dbg(dev->net, "marvell_phy_init()\n"); |
2e55cc72 | 499 | |
933a27d3 | 500 | reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS); |
60b86755 | 501 | netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg); |
2e55cc72 | 502 | |
933a27d3 DH |
503 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL, |
504 | MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY); | |
2e55cc72 | 505 | |
933a27d3 DH |
506 | if (data->ledmode) { |
507 | reg = asix_mdio_read(dev->net, dev->mii.phy_id, | |
508 | MII_MARVELL_LED_CTRL); | |
60b86755 | 509 | netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg); |
2e55cc72 | 510 | |
933a27d3 DH |
511 | reg &= 0xf8ff; |
512 | reg |= (1 + 0x0100); | |
513 | asix_mdio_write(dev->net, dev->mii.phy_id, | |
514 | MII_MARVELL_LED_CTRL, reg); | |
2e55cc72 | 515 | |
933a27d3 DH |
516 | reg = asix_mdio_read(dev->net, dev->mii.phy_id, |
517 | MII_MARVELL_LED_CTRL); | |
60b86755 | 518 | netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg); |
933a27d3 DH |
519 | reg &= 0xfc0f; |
520 | } | |
2e55cc72 | 521 | |
933a27d3 DH |
522 | return 0; |
523 | } | |
524 | ||
610d885d GG |
525 | static int rtl8211cl_phy_init(struct usbnet *dev) |
526 | { | |
527 | struct asix_data *data = (struct asix_data *)&dev->data; | |
528 | ||
529 | netdev_dbg(dev->net, "rtl8211cl_phy_init()\n"); | |
530 | ||
531 | asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005); | |
532 | asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0); | |
533 | asix_mdio_write (dev->net, dev->mii.phy_id, 0x01, | |
534 | asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080); | |
535 | asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); | |
536 | ||
537 | if (data->ledmode == 12) { | |
538 | asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002); | |
539 | asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb); | |
540 | asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); | |
541 | } | |
542 | ||
543 | return 0; | |
544 | } | |
545 | ||
933a27d3 DH |
546 | static int marvell_led_status(struct usbnet *dev, u16 speed) |
547 | { | |
548 | u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL); | |
549 | ||
60b86755 | 550 | netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg); |
933a27d3 DH |
551 | |
552 | /* Clear out the center LED bits - 0x03F0 */ | |
553 | reg &= 0xfc0f; | |
554 | ||
555 | switch (speed) { | |
556 | case SPEED_1000: | |
557 | reg |= 0x03e0; | |
558 | break; | |
559 | case SPEED_100: | |
560 | reg |= 0x03b0; | |
561 | break; | |
562 | default: | |
563 | reg |= 0x02f0; | |
2e55cc72 DB |
564 | } |
565 | ||
60b86755 | 566 | netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg); |
933a27d3 DH |
567 | asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg); |
568 | ||
569 | return 0; | |
570 | } | |
571 | ||
610d885d GG |
572 | static int ax88178_reset(struct usbnet *dev) |
573 | { | |
574 | struct asix_data *data = (struct asix_data *)&dev->data; | |
575 | int ret; | |
576 | __le16 eeprom; | |
577 | u8 status; | |
578 | int gpio0 = 0; | |
b2d3ad29 | 579 | u32 phyid; |
610d885d GG |
580 | |
581 | asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status); | |
49ae25b0 | 582 | netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status); |
610d885d GG |
583 | |
584 | asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL); | |
585 | asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom); | |
586 | asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL); | |
587 | ||
49ae25b0 | 588 | netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom); |
610d885d GG |
589 | |
590 | if (eeprom == cpu_to_le16(0xffff)) { | |
591 | data->phymode = PHY_MODE_MARVELL; | |
592 | data->ledmode = 0; | |
593 | gpio0 = 1; | |
594 | } else { | |
b2d3ad29 | 595 | data->phymode = le16_to_cpu(eeprom) & 0x7F; |
610d885d GG |
596 | data->ledmode = le16_to_cpu(eeprom) >> 8; |
597 | gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1; | |
598 | } | |
49ae25b0 | 599 | netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode); |
610d885d | 600 | |
b2d3ad29 | 601 | /* Power up external GigaPHY through AX88178 GPIO pin */ |
610d885d GG |
602 | asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | AX_GPIO_GPO1EN, 40); |
603 | if ((le16_to_cpu(eeprom) >> 8) != 1) { | |
604 | asix_write_gpio(dev, 0x003c, 30); | |
605 | asix_write_gpio(dev, 0x001c, 300); | |
606 | asix_write_gpio(dev, 0x003c, 30); | |
607 | } else { | |
49ae25b0 | 608 | netdev_dbg(dev->net, "gpio phymode == 1 path\n"); |
610d885d GG |
609 | asix_write_gpio(dev, AX_GPIO_GPO1EN, 30); |
610 | asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30); | |
611 | } | |
612 | ||
b2d3ad29 GG |
613 | /* Read PHYID register *AFTER* powering up PHY */ |
614 | phyid = asix_get_phyid(dev); | |
49ae25b0 | 615 | netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid); |
b2d3ad29 GG |
616 | |
617 | /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */ | |
618 | asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL); | |
619 | ||
610d885d GG |
620 | asix_sw_reset(dev, 0); |
621 | msleep(150); | |
622 | ||
623 | asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD); | |
624 | msleep(150); | |
625 | ||
626 | asix_write_rx_ctl(dev, 0); | |
627 | ||
628 | if (data->phymode == PHY_MODE_MARVELL) { | |
629 | marvell_phy_init(dev); | |
630 | msleep(60); | |
631 | } else if (data->phymode == PHY_MODE_RTL8211CL) | |
632 | rtl8211cl_phy_init(dev); | |
633 | ||
634 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, | |
635 | BMCR_RESET | BMCR_ANENABLE); | |
636 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, | |
637 | ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
638 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000, | |
639 | ADVERTISE_1000FULL); | |
640 | ||
641 | mii_nway_restart(&dev->mii); | |
642 | ||
83e1b918 GG |
643 | ret = asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT); |
644 | if (ret < 0) | |
645 | return ret; | |
610d885d | 646 | |
71bc5d94 JK |
647 | /* Rewrite MAC address */ |
648 | memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN); | |
649 | ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, | |
650 | data->mac_addr); | |
651 | if (ret < 0) | |
652 | return ret; | |
653 | ||
83e1b918 GG |
654 | ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL); |
655 | if (ret < 0) | |
656 | return ret; | |
610d885d GG |
657 | |
658 | return 0; | |
610d885d GG |
659 | } |
660 | ||
933a27d3 DH |
661 | static int ax88178_link_reset(struct usbnet *dev) |
662 | { | |
663 | u16 mode; | |
8ae6daca | 664 | struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; |
933a27d3 | 665 | struct asix_data *data = (struct asix_data *)&dev->data; |
8ae6daca | 666 | u32 speed; |
933a27d3 | 667 | |
60b86755 | 668 | netdev_dbg(dev->net, "ax88178_link_reset()\n"); |
933a27d3 DH |
669 | |
670 | mii_check_media(&dev->mii, 1, 1); | |
671 | mii_ethtool_gset(&dev->mii, &ecmd); | |
672 | mode = AX88178_MEDIUM_DEFAULT; | |
8ae6daca | 673 | speed = ethtool_cmd_speed(&ecmd); |
933a27d3 | 674 | |
8ae6daca | 675 | if (speed == SPEED_1000) |
a7f75c0c | 676 | mode |= AX_MEDIUM_GM; |
8ae6daca | 677 | else if (speed == SPEED_100) |
933a27d3 DH |
678 | mode |= AX_MEDIUM_PS; |
679 | else | |
680 | mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM); | |
681 | ||
a7f75c0c PK |
682 | mode |= AX_MEDIUM_ENCK; |
683 | ||
933a27d3 DH |
684 | if (ecmd.duplex == DUPLEX_FULL) |
685 | mode |= AX_MEDIUM_FD; | |
686 | else | |
687 | mode &= ~AX_MEDIUM_FD; | |
688 | ||
8ae6daca DD |
689 | netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", |
690 | speed, ecmd.duplex, mode); | |
933a27d3 DH |
691 | |
692 | asix_write_medium_mode(dev, mode); | |
693 | ||
694 | if (data->phymode == PHY_MODE_MARVELL && data->ledmode) | |
8ae6daca | 695 | marvell_led_status(dev, speed); |
933a27d3 DH |
696 | |
697 | return 0; | |
698 | } | |
699 | ||
700 | static void ax88178_set_mfb(struct usbnet *dev) | |
701 | { | |
702 | u16 mfb = AX_RX_CTL_MFB_16384; | |
703 | u16 rxctl; | |
704 | u16 medium; | |
705 | int old_rx_urb_size = dev->rx_urb_size; | |
706 | ||
707 | if (dev->hard_mtu < 2048) { | |
708 | dev->rx_urb_size = 2048; | |
709 | mfb = AX_RX_CTL_MFB_2048; | |
710 | } else if (dev->hard_mtu < 4096) { | |
711 | dev->rx_urb_size = 4096; | |
712 | mfb = AX_RX_CTL_MFB_4096; | |
713 | } else if (dev->hard_mtu < 8192) { | |
714 | dev->rx_urb_size = 8192; | |
715 | mfb = AX_RX_CTL_MFB_8192; | |
716 | } else if (dev->hard_mtu < 16384) { | |
717 | dev->rx_urb_size = 16384; | |
718 | mfb = AX_RX_CTL_MFB_16384; | |
2e55cc72 | 719 | } |
933a27d3 DH |
720 | |
721 | rxctl = asix_read_rx_ctl(dev); | |
722 | asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb); | |
723 | ||
724 | medium = asix_read_medium_status(dev); | |
725 | if (dev->net->mtu > 1500) | |
726 | medium |= AX_MEDIUM_JFE; | |
727 | else | |
728 | medium &= ~AX_MEDIUM_JFE; | |
729 | asix_write_medium_mode(dev, medium); | |
730 | ||
731 | if (dev->rx_urb_size > old_rx_urb_size) | |
732 | usbnet_unlink_rx_urbs(dev); | |
2e55cc72 DB |
733 | } |
734 | ||
933a27d3 | 735 | static int ax88178_change_mtu(struct net_device *net, int new_mtu) |
2e55cc72 | 736 | { |
933a27d3 DH |
737 | struct usbnet *dev = netdev_priv(net); |
738 | int ll_mtu = new_mtu + net->hard_header_len + 4; | |
2e55cc72 | 739 | |
60b86755 | 740 | netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu); |
2e55cc72 | 741 | |
933a27d3 DH |
742 | if (new_mtu <= 0 || ll_mtu > 16384) |
743 | return -EINVAL; | |
744 | ||
745 | if ((ll_mtu % dev->maxpacket) == 0) | |
746 | return -EDOM; | |
747 | ||
748 | net->mtu = new_mtu; | |
749 | dev->hard_mtu = net->mtu + net->hard_header_len; | |
750 | ax88178_set_mfb(dev); | |
751 | ||
752 | return 0; | |
753 | } | |
754 | ||
1703338c SH |
755 | static const struct net_device_ops ax88178_netdev_ops = { |
756 | .ndo_open = usbnet_open, | |
757 | .ndo_stop = usbnet_stop, | |
758 | .ndo_start_xmit = usbnet_start_xmit, | |
759 | .ndo_tx_timeout = usbnet_tx_timeout, | |
7f29a3ba | 760 | .ndo_set_mac_address = asix_set_mac_address, |
1703338c | 761 | .ndo_validate_addr = eth_validate_addr, |
afc4b13d | 762 | .ndo_set_rx_mode = asix_set_multicast, |
1703338c SH |
763 | .ndo_do_ioctl = asix_ioctl, |
764 | .ndo_change_mtu = ax88178_change_mtu, | |
765 | }; | |
766 | ||
933a27d3 DH |
767 | static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf) |
768 | { | |
933a27d3 | 769 | int ret; |
51bf2976 | 770 | u8 buf[ETH_ALEN]; |
933a27d3 DH |
771 | |
772 | usbnet_get_endpoints(dev,intf); | |
773 | ||
933a27d3 | 774 | /* Get the MAC address */ |
83e1b918 GG |
775 | ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf); |
776 | if (ret < 0) { | |
49ae25b0 | 777 | netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret); |
83e1b918 | 778 | return ret; |
2e55cc72 | 779 | } |
933a27d3 | 780 | memcpy(dev->net->dev_addr, buf, ETH_ALEN); |
2e55cc72 | 781 | |
933a27d3 DH |
782 | /* Initialize MII structure */ |
783 | dev->mii.dev = dev->net; | |
784 | dev->mii.mdio_read = asix_mdio_read; | |
785 | dev->mii.mdio_write = asix_mdio_write; | |
786 | dev->mii.phy_id_mask = 0x1f; | |
787 | dev->mii.reg_num_mask = 0xff; | |
788 | dev->mii.supports_gmii = 1; | |
933a27d3 | 789 | dev->mii.phy_id = asix_get_phy_addr(dev); |
1703338c SH |
790 | |
791 | dev->net->netdev_ops = &ax88178_netdev_ops; | |
933a27d3 | 792 | dev->net->ethtool_ops = &ax88178_ethtool_ops; |
2e55cc72 | 793 | |
b2d3ad29 GG |
794 | /* Blink LEDS so users know driver saw dongle */ |
795 | asix_sw_reset(dev, 0); | |
796 | msleep(150); | |
2e55cc72 | 797 | |
b2d3ad29 GG |
798 | asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD); |
799 | msleep(150); | |
933a27d3 DH |
800 | |
801 | /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ | |
802 | if (dev->driver_info->flags & FLAG_FRAMING_AX) { | |
803 | /* hard_mtu is still the default - the device does not support | |
804 | jumbo eth frames */ | |
805 | dev->rx_urb_size = 2048; | |
806 | } | |
933a27d3 | 807 | |
83e1b918 | 808 | return 0; |
2e55cc72 DB |
809 | } |
810 | ||
811 | static const struct driver_info ax8817x_info = { | |
812 | .description = "ASIX AX8817x USB 2.0 Ethernet", | |
48b1be6a DH |
813 | .bind = ax88172_bind, |
814 | .status = asix_status, | |
2e55cc72 DB |
815 | .link_reset = ax88172_link_reset, |
816 | .reset = ax88172_link_reset, | |
37e8273c | 817 | .flags = FLAG_ETHER | FLAG_LINK_INTR, |
2e55cc72 DB |
818 | .data = 0x00130103, |
819 | }; | |
820 | ||
821 | static const struct driver_info dlink_dub_e100_info = { | |
822 | .description = "DLink DUB-E100 USB Ethernet", | |
48b1be6a DH |
823 | .bind = ax88172_bind, |
824 | .status = asix_status, | |
2e55cc72 DB |
825 | .link_reset = ax88172_link_reset, |
826 | .reset = ax88172_link_reset, | |
37e8273c | 827 | .flags = FLAG_ETHER | FLAG_LINK_INTR, |
2e55cc72 DB |
828 | .data = 0x009f9d9f, |
829 | }; | |
830 | ||
831 | static const struct driver_info netgear_fa120_info = { | |
832 | .description = "Netgear FA-120 USB Ethernet", | |
48b1be6a DH |
833 | .bind = ax88172_bind, |
834 | .status = asix_status, | |
2e55cc72 DB |
835 | .link_reset = ax88172_link_reset, |
836 | .reset = ax88172_link_reset, | |
37e8273c | 837 | .flags = FLAG_ETHER | FLAG_LINK_INTR, |
2e55cc72 DB |
838 | .data = 0x00130103, |
839 | }; | |
840 | ||
841 | static const struct driver_info hawking_uf200_info = { | |
842 | .description = "Hawking UF200 USB Ethernet", | |
48b1be6a DH |
843 | .bind = ax88172_bind, |
844 | .status = asix_status, | |
2e55cc72 DB |
845 | .link_reset = ax88172_link_reset, |
846 | .reset = ax88172_link_reset, | |
37e8273c | 847 | .flags = FLAG_ETHER | FLAG_LINK_INTR, |
2e55cc72 DB |
848 | .data = 0x001f1d1f, |
849 | }; | |
850 | ||
851 | static const struct driver_info ax88772_info = { | |
852 | .description = "ASIX AX88772 USB 2.0 Ethernet", | |
853 | .bind = ax88772_bind, | |
48b1be6a | 854 | .status = asix_status, |
2e55cc72 | 855 | .link_reset = ax88772_link_reset, |
4ad1438f | 856 | .reset = ax88772_reset, |
a9e0aca4 | 857 | .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET, |
933a27d3 DH |
858 | .rx_fixup = asix_rx_fixup, |
859 | .tx_fixup = asix_tx_fixup, | |
860 | }; | |
861 | ||
862 | static const struct driver_info ax88178_info = { | |
863 | .description = "ASIX AX88178 USB 2.0 Ethernet", | |
864 | .bind = ax88178_bind, | |
865 | .status = asix_status, | |
866 | .link_reset = ax88178_link_reset, | |
610d885d | 867 | .reset = ax88178_reset, |
37e8273c | 868 | .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR, |
933a27d3 DH |
869 | .rx_fixup = asix_rx_fixup, |
870 | .tx_fixup = asix_tx_fixup, | |
2e55cc72 DB |
871 | }; |
872 | ||
16626b0c CR |
873 | extern const struct driver_info ax88172a_info; |
874 | ||
2e55cc72 DB |
875 | static const struct usb_device_id products [] = { |
876 | { | |
877 | // Linksys USB200M | |
878 | USB_DEVICE (0x077b, 0x2226), | |
879 | .driver_info = (unsigned long) &ax8817x_info, | |
880 | }, { | |
881 | // Netgear FA120 | |
882 | USB_DEVICE (0x0846, 0x1040), | |
883 | .driver_info = (unsigned long) &netgear_fa120_info, | |
884 | }, { | |
885 | // DLink DUB-E100 | |
886 | USB_DEVICE (0x2001, 0x1a00), | |
887 | .driver_info = (unsigned long) &dlink_dub_e100_info, | |
888 | }, { | |
889 | // Intellinet, ST Lab USB Ethernet | |
890 | USB_DEVICE (0x0b95, 0x1720), | |
891 | .driver_info = (unsigned long) &ax8817x_info, | |
892 | }, { | |
893 | // Hawking UF200, TrendNet TU2-ET100 | |
894 | USB_DEVICE (0x07b8, 0x420a), | |
895 | .driver_info = (unsigned long) &hawking_uf200_info, | |
896 | }, { | |
39c4b38c DH |
897 | // Billionton Systems, USB2AR |
898 | USB_DEVICE (0x08dd, 0x90ff), | |
899 | .driver_info = (unsigned long) &ax8817x_info, | |
2e55cc72 DB |
900 | }, { |
901 | // ATEN UC210T | |
902 | USB_DEVICE (0x0557, 0x2009), | |
903 | .driver_info = (unsigned long) &ax8817x_info, | |
904 | }, { | |
905 | // Buffalo LUA-U2-KTX | |
906 | USB_DEVICE (0x0411, 0x003d), | |
907 | .driver_info = (unsigned long) &ax8817x_info, | |
ac7b77f1 MD |
908 | }, { |
909 | // Buffalo LUA-U2-GT 10/100/1000 | |
910 | USB_DEVICE (0x0411, 0x006e), | |
911 | .driver_info = (unsigned long) &ax88178_info, | |
2e55cc72 DB |
912 | }, { |
913 | // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter" | |
914 | USB_DEVICE (0x6189, 0x182d), | |
915 | .driver_info = (unsigned long) &ax8817x_info, | |
4e503919 JN |
916 | }, { |
917 | // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter" | |
918 | USB_DEVICE (0x0df6, 0x0056), | |
919 | .driver_info = (unsigned long) &ax88178_info, | |
2e55cc72 DB |
920 | }, { |
921 | // corega FEther USB2-TX | |
922 | USB_DEVICE (0x07aa, 0x0017), | |
923 | .driver_info = (unsigned long) &ax8817x_info, | |
924 | }, { | |
925 | // Surecom EP-1427X-2 | |
926 | USB_DEVICE (0x1189, 0x0893), | |
927 | .driver_info = (unsigned long) &ax8817x_info, | |
928 | }, { | |
929 | // goodway corp usb gwusb2e | |
930 | USB_DEVICE (0x1631, 0x6200), | |
931 | .driver_info = (unsigned long) &ax8817x_info, | |
39c4b38c DH |
932 | }, { |
933 | // JVC MP-PRX1 Port Replicator | |
934 | USB_DEVICE (0x04f1, 0x3008), | |
935 | .driver_info = (unsigned long) &ax8817x_info, | |
30885909 MV |
936 | }, { |
937 | // ASIX AX88772B 10/100 | |
938 | USB_DEVICE (0x0b95, 0x772b), | |
939 | .driver_info = (unsigned long) &ax88772_info, | |
2e55cc72 DB |
940 | }, { |
941 | // ASIX AX88772 10/100 | |
39c4b38c DH |
942 | USB_DEVICE (0x0b95, 0x7720), |
943 | .driver_info = (unsigned long) &ax88772_info, | |
7327413c EW |
944 | }, { |
945 | // ASIX AX88178 10/100/1000 | |
946 | USB_DEVICE (0x0b95, 0x1780), | |
933a27d3 | 947 | .driver_info = (unsigned long) &ax88178_info, |
f4680d3d AE |
948 | }, { |
949 | // Logitec LAN-GTJ/U2A | |
950 | USB_DEVICE (0x0789, 0x0160), | |
951 | .driver_info = (unsigned long) &ax88178_info, | |
5e0f76c6 DH |
952 | }, { |
953 | // Linksys USB200M Rev 2 | |
954 | USB_DEVICE (0x13b1, 0x0018), | |
955 | .driver_info = (unsigned long) &ax88772_info, | |
5732ce84 DH |
956 | }, { |
957 | // 0Q0 cable ethernet | |
958 | USB_DEVICE (0x1557, 0x7720), | |
959 | .driver_info = (unsigned long) &ax88772_info, | |
933a27d3 DH |
960 | }, { |
961 | // DLink DUB-E100 H/W Ver B1 | |
962 | USB_DEVICE (0x07d1, 0x3c05), | |
963 | .driver_info = (unsigned long) &ax88772_info, | |
b923e7fc DH |
964 | }, { |
965 | // DLink DUB-E100 H/W Ver B1 Alternate | |
966 | USB_DEVICE (0x2001, 0x3c05), | |
967 | .driver_info = (unsigned long) &ax88772_info, | |
ed3770a9 S |
968 | }, { |
969 | // DLink DUB-E100 H/W Ver C1 | |
970 | USB_DEVICE (0x2001, 0x1a02), | |
971 | .driver_info = (unsigned long) &ax88772_info, | |
933a27d3 DH |
972 | }, { |
973 | // Linksys USB1000 | |
974 | USB_DEVICE (0x1737, 0x0039), | |
975 | .driver_info = (unsigned long) &ax88178_info, | |
b29cf31d YH |
976 | }, { |
977 | // IO-DATA ETG-US2 | |
978 | USB_DEVICE (0x04bb, 0x0930), | |
979 | .driver_info = (unsigned long) &ax88178_info, | |
2ed22bc2 DH |
980 | }, { |
981 | // Belkin F5D5055 | |
982 | USB_DEVICE(0x050d, 0x5055), | |
983 | .driver_info = (unsigned long) &ax88178_info, | |
3d60efb5 AN |
984 | }, { |
985 | // Apple USB Ethernet Adapter | |
986 | USB_DEVICE(0x05ac, 0x1402), | |
987 | .driver_info = (unsigned long) &ax88772_info, | |
ccf95402 JC |
988 | }, { |
989 | // Cables-to-Go USB Ethernet Adapter | |
990 | USB_DEVICE(0x0b95, 0x772a), | |
991 | .driver_info = (unsigned long) &ax88772_info, | |
fef7cc08 GKH |
992 | }, { |
993 | // ABOCOM for pci | |
994 | USB_DEVICE(0x14ea, 0xab11), | |
995 | .driver_info = (unsigned long) &ax88178_info, | |
996 | }, { | |
997 | // ASIX 88772a | |
998 | USB_DEVICE(0x0db0, 0xa877), | |
999 | .driver_info = (unsigned long) &ax88772_info, | |
e8303a3b AJ |
1000 | }, { |
1001 | // Asus USB Ethernet Adapter | |
1002 | USB_DEVICE (0x0b95, 0x7e2b), | |
1003 | .driver_info = (unsigned long) &ax88772_info, | |
16626b0c CR |
1004 | }, { |
1005 | /* ASIX 88172a demo board */ | |
1006 | USB_DEVICE(0x0b95, 0x172a), | |
1007 | .driver_info = (unsigned long) &ax88172a_info, | |
2e55cc72 DB |
1008 | }, |
1009 | { }, // END | |
1010 | }; | |
1011 | MODULE_DEVICE_TABLE(usb, products); | |
1012 | ||
1013 | static struct usb_driver asix_driver = { | |
83e1b918 | 1014 | .name = DRIVER_NAME, |
2e55cc72 DB |
1015 | .id_table = products, |
1016 | .probe = usbnet_probe, | |
1017 | .suspend = usbnet_suspend, | |
1018 | .resume = usbnet_resume, | |
1019 | .disconnect = usbnet_disconnect, | |
a11a6544 | 1020 | .supports_autosuspend = 1, |
e1f12eb6 | 1021 | .disable_hub_initiated_lpm = 1, |
2e55cc72 DB |
1022 | }; |
1023 | ||
d632eb1b | 1024 | module_usb_driver(asix_driver); |
2e55cc72 DB |
1025 | |
1026 | MODULE_AUTHOR("David Hollis"); | |
4ad1438f | 1027 | MODULE_VERSION(DRIVER_VERSION); |
2e55cc72 DB |
1028 | MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices"); |
1029 | MODULE_LICENSE("GPL"); | |
1030 |