asix: Rework reading from EEPROM
[deliverable/linux.git] / drivers / net / usb / asix_devices.c
CommitLineData
2e55cc72
DB
1/*
2 * ASIX AX8817X based USB 2.0 Ethernet Devices
933a27d3 3 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
2e55cc72 4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
933a27d3 5 * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
2e55cc72
DB
6 * Copyright (c) 2002-2003 TiVo Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
607740bc 23#include "asix.h"
933a27d3
DH
24
25#define PHY_MODE_MARVELL 0x0000
26#define MII_MARVELL_LED_CTRL 0x0018
27#define MII_MARVELL_STATUS 0x001b
28#define MII_MARVELL_CTRL 0x0014
29
30#define MARVELL_LED_MANUAL 0x0019
31
32#define MARVELL_STATUS_HWCFG 0x0004
33
34#define MARVELL_CTRL_TXDELAY 0x0002
35#define MARVELL_CTRL_RXDELAY 0x0080
2e55cc72 36
3486140e 37#define PHY_MODE_RTL8211CL 0x000C
610d885d 38
2e55cc72 39struct ax88172_int_data {
51bf2976 40 __le16 res1;
2e55cc72 41 u8 link;
51bf2976 42 __le16 res2;
2e55cc72 43 u8 status;
51bf2976 44 __le16 res3;
ba2d3587 45} __packed;
2e55cc72 46
933a27d3
DH
47static void asix_status(struct usbnet *dev, struct urb *urb)
48{
49 struct ax88172_int_data *event;
50 int link;
51
52 if (urb->actual_length < 8)
53 return;
54
55 event = urb->transfer_buffer;
56 link = event->link & 0x01;
57 if (netif_carrier_ok(dev->net) != link) {
58 if (link) {
59 netif_carrier_on(dev->net);
60 usbnet_defer_kevent (dev, EVENT_LINK_RESET );
61 } else
62 netif_carrier_off(dev->net);
60b86755 63 netdev_dbg(dev->net, "Link Status is: %d\n", link);
933a27d3
DH
64 }
65}
66
933a27d3
DH
67/* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
68static u32 asix_get_phyid(struct usbnet *dev)
2e55cc72 69{
933a27d3
DH
70 int phy_reg;
71 u32 phy_id;
a77929a2 72 int i;
2e55cc72 73
a77929a2
GG
74 /* Poll for the rare case the FW or phy isn't ready yet. */
75 for (i = 0; i < 100; i++) {
76 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
77 if (phy_reg != 0 && phy_reg != 0xFFFF)
78 break;
79 mdelay(1);
80 }
81
82 if (phy_reg <= 0 || phy_reg == 0xFFFF)
933a27d3 83 return 0;
2e55cc72 84
933a27d3 85 phy_id = (phy_reg & 0xffff) << 16;
2e55cc72 86
933a27d3
DH
87 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
88 if (phy_reg < 0)
89 return 0;
90
91 phy_id |= (phy_reg & 0xffff);
92
93 return phy_id;
2e55cc72
DB
94}
95
933a27d3
DH
96static u32 asix_get_link(struct net_device *net)
97{
98 struct usbnet *dev = netdev_priv(net);
99
100 return mii_link_ok(&dev->mii);
101}
102
103static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
104{
105 struct usbnet *dev = netdev_priv(net);
106
107 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
108}
109
110/* We need to override some ethtool_ops so we require our
111 own structure so we don't interfere with other usbnet
112 devices that may be connected at the same time. */
0fc0b732 113static const struct ethtool_ops ax88172_ethtool_ops = {
933a27d3
DH
114 .get_drvinfo = asix_get_drvinfo,
115 .get_link = asix_get_link,
933a27d3 116 .get_msglevel = usbnet_get_msglevel,
2e55cc72 117 .set_msglevel = usbnet_set_msglevel,
48b1be6a
DH
118 .get_wol = asix_get_wol,
119 .set_wol = asix_set_wol,
120 .get_eeprom_len = asix_get_eeprom_len,
121 .get_eeprom = asix_get_eeprom,
c41286fd
AB
122 .get_settings = usbnet_get_settings,
123 .set_settings = usbnet_set_settings,
124 .nway_reset = usbnet_nway_reset,
2e55cc72
DB
125};
126
933a27d3 127static void ax88172_set_multicast(struct net_device *net)
2e55cc72
DB
128{
129 struct usbnet *dev = netdev_priv(net);
933a27d3
DH
130 struct asix_data *data = (struct asix_data *)&dev->data;
131 u8 rx_ctl = 0x8c;
2e55cc72 132
933a27d3
DH
133 if (net->flags & IFF_PROMISC) {
134 rx_ctl |= 0x01;
8e95a202 135 } else if (net->flags & IFF_ALLMULTI ||
4cd24eaf 136 netdev_mc_count(net) > AX_MAX_MCAST) {
933a27d3 137 rx_ctl |= 0x02;
4cd24eaf 138 } else if (netdev_mc_empty(net)) {
933a27d3
DH
139 /* just broadcast and directed */
140 } else {
141 /* We use the 20 byte dev->data
142 * for our 8 byte filter buffer
143 * to avoid allocating memory that
144 * is tricky to free later */
22bedad3 145 struct netdev_hw_addr *ha;
933a27d3 146 u32 crc_bits;
933a27d3
DH
147
148 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
149
150 /* Build the multicast hash filter. */
22bedad3
JP
151 netdev_for_each_mc_addr(ha, net) {
152 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
933a27d3
DH
153 data->multi_filter[crc_bits >> 3] |=
154 1 << (crc_bits & 7);
933a27d3
DH
155 }
156
157 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
158 AX_MCAST_FILTER_SIZE, data->multi_filter);
159
160 rx_ctl |= 0x10;
161 }
162
163 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
164}
165
166static int ax88172_link_reset(struct usbnet *dev)
167{
168 u8 mode;
8ae6daca 169 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3
DH
170
171 mii_check_media(&dev->mii, 1, 1);
172 mii_ethtool_gset(&dev->mii, &ecmd);
173 mode = AX88172_MEDIUM_DEFAULT;
174
175 if (ecmd.duplex != DUPLEX_FULL)
176 mode |= ~AX88172_MEDIUM_FD;
177
8ae6daca
DD
178 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
179 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
933a27d3
DH
180
181 asix_write_medium_mode(dev, mode);
182
183 return 0;
2e55cc72
DB
184}
185
1703338c
SH
186static const struct net_device_ops ax88172_netdev_ops = {
187 .ndo_open = usbnet_open,
188 .ndo_stop = usbnet_stop,
189 .ndo_start_xmit = usbnet_start_xmit,
190 .ndo_tx_timeout = usbnet_tx_timeout,
191 .ndo_change_mtu = usbnet_change_mtu,
192 .ndo_set_mac_address = eth_mac_addr,
193 .ndo_validate_addr = eth_validate_addr,
194 .ndo_do_ioctl = asix_ioctl,
afc4b13d 195 .ndo_set_rx_mode = ax88172_set_multicast,
1703338c
SH
196};
197
48b1be6a 198static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
2e55cc72
DB
199{
200 int ret = 0;
51bf2976 201 u8 buf[ETH_ALEN];
2e55cc72
DB
202 int i;
203 unsigned long gpio_bits = dev->driver_info->data;
204
205 usbnet_get_endpoints(dev,intf);
206
2e55cc72
DB
207 /* Toggle the GPIOs in a manufacturer/model specific way */
208 for (i = 2; i >= 0; i--) {
83e1b918
GG
209 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
210 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL);
211 if (ret < 0)
51bf2976 212 goto out;
2e55cc72
DB
213 msleep(5);
214 }
215
83e1b918
GG
216 ret = asix_write_rx_ctl(dev, 0x80);
217 if (ret < 0)
51bf2976 218 goto out;
2e55cc72
DB
219
220 /* Get the MAC address */
83e1b918
GG
221 ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
222 if (ret < 0) {
2e55cc72 223 dbg("read AX_CMD_READ_NODE_ID failed: %d", ret);
51bf2976 224 goto out;
2e55cc72
DB
225 }
226 memcpy(dev->net->dev_addr, buf, ETH_ALEN);
227
2e55cc72
DB
228 /* Initialize MII structure */
229 dev->mii.dev = dev->net;
48b1be6a
DH
230 dev->mii.mdio_read = asix_mdio_read;
231 dev->mii.mdio_write = asix_mdio_write;
2e55cc72
DB
232 dev->mii.phy_id_mask = 0x3f;
233 dev->mii.reg_num_mask = 0x1f;
933a27d3 234 dev->mii.phy_id = asix_get_phy_addr(dev);
2e55cc72 235
1703338c 236 dev->net->netdev_ops = &ax88172_netdev_ops;
48b1be6a 237 dev->net->ethtool_ops = &ax88172_ethtool_ops;
95162d65
ED
238 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
239 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
2e55cc72 240
933a27d3
DH
241 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
242 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
2e55cc72
DB
243 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
244 mii_nway_restart(&dev->mii);
245
246 return 0;
51bf2976
AV
247
248out:
2e55cc72
DB
249 return ret;
250}
251
0fc0b732 252static const struct ethtool_ops ax88772_ethtool_ops = {
48b1be6a 253 .get_drvinfo = asix_get_drvinfo,
933a27d3 254 .get_link = asix_get_link,
2e55cc72
DB
255 .get_msglevel = usbnet_get_msglevel,
256 .set_msglevel = usbnet_set_msglevel,
48b1be6a
DH
257 .get_wol = asix_get_wol,
258 .set_wol = asix_set_wol,
259 .get_eeprom_len = asix_get_eeprom_len,
260 .get_eeprom = asix_get_eeprom,
c41286fd
AB
261 .get_settings = usbnet_get_settings,
262 .set_settings = usbnet_set_settings,
263 .nway_reset = usbnet_nway_reset,
2e55cc72
DB
264};
265
933a27d3
DH
266static int ax88772_link_reset(struct usbnet *dev)
267{
268 u16 mode;
8ae6daca 269 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3
DH
270
271 mii_check_media(&dev->mii, 1, 1);
272 mii_ethtool_gset(&dev->mii, &ecmd);
273 mode = AX88772_MEDIUM_DEFAULT;
274
8ae6daca 275 if (ethtool_cmd_speed(&ecmd) != SPEED_100)
933a27d3
DH
276 mode &= ~AX_MEDIUM_PS;
277
278 if (ecmd.duplex != DUPLEX_FULL)
279 mode &= ~AX_MEDIUM_FD;
280
8ae6daca
DD
281 netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
282 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
933a27d3
DH
283
284 asix_write_medium_mode(dev, mode);
285
286 return 0;
287}
288
4ad1438f 289static int ax88772_reset(struct usbnet *dev)
2e55cc72 290{
8ef66bdc 291 struct asix_data *data = (struct asix_data *)&dev->data;
d0ffff8f 292 int ret, embd_phy;
933a27d3 293 u16 rx_ctl;
2e55cc72 294
83e1b918
GG
295 ret = asix_write_gpio(dev,
296 AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5);
297 if (ret < 0)
51bf2976 298 goto out;
2e55cc72 299
d0ffff8f 300 embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0);
4ad1438f 301
83e1b918
GG
302 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL);
303 if (ret < 0) {
2e55cc72 304 dbg("Select PHY #1 failed: %d", ret);
51bf2976 305 goto out;
2e55cc72
DB
306 }
307
83e1b918
GG
308 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL);
309 if (ret < 0)
51bf2976 310 goto out;
2e55cc72
DB
311
312 msleep(150);
83e1b918
GG
313
314 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR);
315 if (ret < 0)
51bf2976 316 goto out;
2e55cc72
DB
317
318 msleep(150);
4ad1438f 319
d0ffff8f 320 if (embd_phy) {
83e1b918
GG
321 ret = asix_sw_reset(dev, AX_SWRESET_IPRL);
322 if (ret < 0)
51bf2976 323 goto out;
83e1b918
GG
324 } else {
325 ret = asix_sw_reset(dev, AX_SWRESET_PRTE);
326 if (ret < 0)
51bf2976 327 goto out;
d0ffff8f 328 }
2e55cc72
DB
329
330 msleep(150);
933a27d3
DH
331 rx_ctl = asix_read_rx_ctl(dev);
332 dbg("RX_CTL is 0x%04x after software reset", rx_ctl);
83e1b918
GG
333 ret = asix_write_rx_ctl(dev, 0x0000);
334 if (ret < 0)
51bf2976 335 goto out;
2e55cc72 336
933a27d3
DH
337 rx_ctl = asix_read_rx_ctl(dev);
338 dbg("RX_CTL is 0x%04x setting to 0x0000", rx_ctl);
339
83e1b918
GG
340 ret = asix_sw_reset(dev, AX_SWRESET_PRL);
341 if (ret < 0)
51bf2976 342 goto out;
2e55cc72 343
2e55cc72 344 msleep(150);
48b1be6a 345
83e1b918
GG
346 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL);
347 if (ret < 0)
51bf2976 348 goto out;
2e55cc72 349
48b1be6a 350 msleep(150);
2e55cc72 351
933a27d3
DH
352 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
353 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
2e55cc72
DB
354 ADVERTISE_ALL | ADVERTISE_CSMA);
355 mii_nway_restart(&dev->mii);
356
83e1b918
GG
357 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT);
358 if (ret < 0)
51bf2976 359 goto out;
2e55cc72 360
83e1b918 361 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
2e55cc72 362 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
83e1b918
GG
363 AX88772_IPG2_DEFAULT, 0, NULL);
364 if (ret < 0) {
2e55cc72 365 dbg("Write IPG,IPG1,IPG2 failed: %d", ret);
51bf2976 366 goto out;
2e55cc72 367 }
2e55cc72 368
8ef66bdc
JK
369 /* Rewrite MAC address */
370 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
371 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
372 data->mac_addr);
373 if (ret < 0)
374 goto out;
375
2e55cc72 376 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
83e1b918
GG
377 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL);
378 if (ret < 0)
51bf2976 379 goto out;
2e55cc72 380
933a27d3
DH
381 rx_ctl = asix_read_rx_ctl(dev);
382 dbg("RX_CTL is 0x%04x after all initializations", rx_ctl);
383
384 rx_ctl = asix_read_medium_status(dev);
385 dbg("Medium Status is 0x%04x after all initializations", rx_ctl);
386
4ad1438f
GG
387 return 0;
388
389out:
390 return ret;
391
392}
393
394static const struct net_device_ops ax88772_netdev_ops = {
395 .ndo_open = usbnet_open,
396 .ndo_stop = usbnet_stop,
397 .ndo_start_xmit = usbnet_start_xmit,
398 .ndo_tx_timeout = usbnet_tx_timeout,
399 .ndo_change_mtu = usbnet_change_mtu,
400 .ndo_set_mac_address = asix_set_mac_address,
401 .ndo_validate_addr = eth_validate_addr,
402 .ndo_do_ioctl = asix_ioctl,
403 .ndo_set_rx_mode = asix_set_multicast,
404};
405
406static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
407{
d3665188 408 int ret, embd_phy;
4ad1438f
GG
409 u8 buf[ETH_ALEN];
410 u32 phyid;
411
4ad1438f
GG
412 usbnet_get_endpoints(dev,intf);
413
414 /* Get the MAC address */
83e1b918
GG
415 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
416 if (ret < 0) {
4ad1438f 417 dbg("Failed to read MAC address: %d", ret);
83e1b918 418 return ret;
4ad1438f
GG
419 }
420 memcpy(dev->net->dev_addr, buf, ETH_ALEN);
421
422 /* Initialize MII structure */
423 dev->mii.dev = dev->net;
424 dev->mii.mdio_read = asix_mdio_read;
425 dev->mii.mdio_write = asix_mdio_write;
426 dev->mii.phy_id_mask = 0x1f;
427 dev->mii.reg_num_mask = 0x1f;
428 dev->mii.phy_id = asix_get_phy_addr(dev);
429
4ad1438f
GG
430 dev->net->netdev_ops = &ax88772_netdev_ops;
431 dev->net->ethtool_ops = &ax88772_ethtool_ops;
95162d65
ED
432 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
433 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
4ad1438f 434
d3665188
GG
435 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
436
437 /* Reset the PHY to normal operation mode */
438 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL);
439 if (ret < 0) {
440 dbg("Select PHY #1 failed: %d", ret);
441 return ret;
442 }
443
444 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL);
83e1b918
GG
445 if (ret < 0)
446 return ret;
4ad1438f 447
d3665188
GG
448 msleep(150);
449
450 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR);
451 if (ret < 0)
452 return ret;
453
454 msleep(150);
455
456 ret = asix_sw_reset(dev, embd_phy ? AX_SWRESET_IPRL : AX_SWRESET_PRTE);
457
458 /* Read PHYID register *AFTER* the PHY was reset properly */
459 phyid = asix_get_phyid(dev);
460 dbg("PHYID=0x%08x", phyid);
461
2e55cc72
DB
462 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
463 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
464 /* hard_mtu is still the default - the device does not support
465 jumbo eth frames */
466 dev->rx_urb_size = 2048;
467 }
83e1b918 468
2e55cc72 469 return 0;
2e55cc72
DB
470}
471
bc689c97 472static const struct ethtool_ops ax88178_ethtool_ops = {
933a27d3
DH
473 .get_drvinfo = asix_get_drvinfo,
474 .get_link = asix_get_link,
933a27d3
DH
475 .get_msglevel = usbnet_get_msglevel,
476 .set_msglevel = usbnet_set_msglevel,
477 .get_wol = asix_get_wol,
478 .set_wol = asix_set_wol,
479 .get_eeprom_len = asix_get_eeprom_len,
480 .get_eeprom = asix_get_eeprom,
c41286fd
AB
481 .get_settings = usbnet_get_settings,
482 .set_settings = usbnet_set_settings,
483 .nway_reset = usbnet_nway_reset,
933a27d3
DH
484};
485
486static int marvell_phy_init(struct usbnet *dev)
2e55cc72 487{
933a27d3
DH
488 struct asix_data *data = (struct asix_data *)&dev->data;
489 u16 reg;
2e55cc72 490
60b86755 491 netdev_dbg(dev->net, "marvell_phy_init()\n");
2e55cc72 492
933a27d3 493 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
60b86755 494 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg);
2e55cc72 495
933a27d3
DH
496 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
497 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
2e55cc72 498
933a27d3
DH
499 if (data->ledmode) {
500 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
501 MII_MARVELL_LED_CTRL);
60b86755 502 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg);
2e55cc72 503
933a27d3
DH
504 reg &= 0xf8ff;
505 reg |= (1 + 0x0100);
506 asix_mdio_write(dev->net, dev->mii.phy_id,
507 MII_MARVELL_LED_CTRL, reg);
2e55cc72 508
933a27d3
DH
509 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
510 MII_MARVELL_LED_CTRL);
60b86755 511 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg);
933a27d3
DH
512 reg &= 0xfc0f;
513 }
2e55cc72 514
933a27d3
DH
515 return 0;
516}
517
610d885d
GG
518static int rtl8211cl_phy_init(struct usbnet *dev)
519{
520 struct asix_data *data = (struct asix_data *)&dev->data;
521
522 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n");
523
524 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);
525 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);
526 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,
527 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);
528 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
529
530 if (data->ledmode == 12) {
531 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);
532 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);
533 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
534 }
535
536 return 0;
537}
538
933a27d3
DH
539static int marvell_led_status(struct usbnet *dev, u16 speed)
540{
541 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
542
60b86755 543 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg);
933a27d3
DH
544
545 /* Clear out the center LED bits - 0x03F0 */
546 reg &= 0xfc0f;
547
548 switch (speed) {
549 case SPEED_1000:
550 reg |= 0x03e0;
551 break;
552 case SPEED_100:
553 reg |= 0x03b0;
554 break;
555 default:
556 reg |= 0x02f0;
2e55cc72
DB
557 }
558
60b86755 559 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg);
933a27d3
DH
560 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
561
562 return 0;
563}
564
610d885d
GG
565static int ax88178_reset(struct usbnet *dev)
566{
567 struct asix_data *data = (struct asix_data *)&dev->data;
568 int ret;
569 __le16 eeprom;
570 u8 status;
571 int gpio0 = 0;
b2d3ad29 572 u32 phyid;
610d885d
GG
573
574 asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status);
575 dbg("GPIO Status: 0x%04x", status);
576
577 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL);
578 asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom);
579 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL);
580
581 dbg("EEPROM index 0x17 is 0x%04x", eeprom);
582
583 if (eeprom == cpu_to_le16(0xffff)) {
584 data->phymode = PHY_MODE_MARVELL;
585 data->ledmode = 0;
586 gpio0 = 1;
587 } else {
b2d3ad29 588 data->phymode = le16_to_cpu(eeprom) & 0x7F;
610d885d
GG
589 data->ledmode = le16_to_cpu(eeprom) >> 8;
590 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1;
591 }
592 dbg("GPIO0: %d, PhyMode: %d", gpio0, data->phymode);
593
b2d3ad29 594 /* Power up external GigaPHY through AX88178 GPIO pin */
610d885d
GG
595 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | AX_GPIO_GPO1EN, 40);
596 if ((le16_to_cpu(eeprom) >> 8) != 1) {
597 asix_write_gpio(dev, 0x003c, 30);
598 asix_write_gpio(dev, 0x001c, 300);
599 asix_write_gpio(dev, 0x003c, 30);
600 } else {
601 dbg("gpio phymode == 1 path");
602 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30);
603 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30);
604 }
605
b2d3ad29
GG
606 /* Read PHYID register *AFTER* powering up PHY */
607 phyid = asix_get_phyid(dev);
608 dbg("PHYID=0x%08x", phyid);
609
610 /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */
611 asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL);
612
610d885d
GG
613 asix_sw_reset(dev, 0);
614 msleep(150);
615
616 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD);
617 msleep(150);
618
619 asix_write_rx_ctl(dev, 0);
620
621 if (data->phymode == PHY_MODE_MARVELL) {
622 marvell_phy_init(dev);
623 msleep(60);
624 } else if (data->phymode == PHY_MODE_RTL8211CL)
625 rtl8211cl_phy_init(dev);
626
627 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR,
628 BMCR_RESET | BMCR_ANENABLE);
629 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
630 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
631 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
632 ADVERTISE_1000FULL);
633
634 mii_nway_restart(&dev->mii);
635
83e1b918
GG
636 ret = asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT);
637 if (ret < 0)
638 return ret;
610d885d 639
71bc5d94
JK
640 /* Rewrite MAC address */
641 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
642 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
643 data->mac_addr);
644 if (ret < 0)
645 return ret;
646
83e1b918
GG
647 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL);
648 if (ret < 0)
649 return ret;
610d885d
GG
650
651 return 0;
610d885d
GG
652}
653
933a27d3
DH
654static int ax88178_link_reset(struct usbnet *dev)
655{
656 u16 mode;
8ae6daca 657 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3 658 struct asix_data *data = (struct asix_data *)&dev->data;
8ae6daca 659 u32 speed;
933a27d3 660
60b86755 661 netdev_dbg(dev->net, "ax88178_link_reset()\n");
933a27d3
DH
662
663 mii_check_media(&dev->mii, 1, 1);
664 mii_ethtool_gset(&dev->mii, &ecmd);
665 mode = AX88178_MEDIUM_DEFAULT;
8ae6daca 666 speed = ethtool_cmd_speed(&ecmd);
933a27d3 667
8ae6daca 668 if (speed == SPEED_1000)
a7f75c0c 669 mode |= AX_MEDIUM_GM;
8ae6daca 670 else if (speed == SPEED_100)
933a27d3
DH
671 mode |= AX_MEDIUM_PS;
672 else
673 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
674
a7f75c0c
PK
675 mode |= AX_MEDIUM_ENCK;
676
933a27d3
DH
677 if (ecmd.duplex == DUPLEX_FULL)
678 mode |= AX_MEDIUM_FD;
679 else
680 mode &= ~AX_MEDIUM_FD;
681
8ae6daca
DD
682 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
683 speed, ecmd.duplex, mode);
933a27d3
DH
684
685 asix_write_medium_mode(dev, mode);
686
687 if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
8ae6daca 688 marvell_led_status(dev, speed);
933a27d3
DH
689
690 return 0;
691}
692
693static void ax88178_set_mfb(struct usbnet *dev)
694{
695 u16 mfb = AX_RX_CTL_MFB_16384;
696 u16 rxctl;
697 u16 medium;
698 int old_rx_urb_size = dev->rx_urb_size;
699
700 if (dev->hard_mtu < 2048) {
701 dev->rx_urb_size = 2048;
702 mfb = AX_RX_CTL_MFB_2048;
703 } else if (dev->hard_mtu < 4096) {
704 dev->rx_urb_size = 4096;
705 mfb = AX_RX_CTL_MFB_4096;
706 } else if (dev->hard_mtu < 8192) {
707 dev->rx_urb_size = 8192;
708 mfb = AX_RX_CTL_MFB_8192;
709 } else if (dev->hard_mtu < 16384) {
710 dev->rx_urb_size = 16384;
711 mfb = AX_RX_CTL_MFB_16384;
2e55cc72 712 }
933a27d3
DH
713
714 rxctl = asix_read_rx_ctl(dev);
715 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb);
716
717 medium = asix_read_medium_status(dev);
718 if (dev->net->mtu > 1500)
719 medium |= AX_MEDIUM_JFE;
720 else
721 medium &= ~AX_MEDIUM_JFE;
722 asix_write_medium_mode(dev, medium);
723
724 if (dev->rx_urb_size > old_rx_urb_size)
725 usbnet_unlink_rx_urbs(dev);
2e55cc72
DB
726}
727
933a27d3 728static int ax88178_change_mtu(struct net_device *net, int new_mtu)
2e55cc72 729{
933a27d3
DH
730 struct usbnet *dev = netdev_priv(net);
731 int ll_mtu = new_mtu + net->hard_header_len + 4;
2e55cc72 732
60b86755 733 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu);
2e55cc72 734
933a27d3
DH
735 if (new_mtu <= 0 || ll_mtu > 16384)
736 return -EINVAL;
737
738 if ((ll_mtu % dev->maxpacket) == 0)
739 return -EDOM;
740
741 net->mtu = new_mtu;
742 dev->hard_mtu = net->mtu + net->hard_header_len;
743 ax88178_set_mfb(dev);
744
745 return 0;
746}
747
1703338c
SH
748static const struct net_device_ops ax88178_netdev_ops = {
749 .ndo_open = usbnet_open,
750 .ndo_stop = usbnet_stop,
751 .ndo_start_xmit = usbnet_start_xmit,
752 .ndo_tx_timeout = usbnet_tx_timeout,
7f29a3ba 753 .ndo_set_mac_address = asix_set_mac_address,
1703338c 754 .ndo_validate_addr = eth_validate_addr,
afc4b13d 755 .ndo_set_rx_mode = asix_set_multicast,
1703338c
SH
756 .ndo_do_ioctl = asix_ioctl,
757 .ndo_change_mtu = ax88178_change_mtu,
758};
759
933a27d3
DH
760static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
761{
933a27d3 762 int ret;
51bf2976 763 u8 buf[ETH_ALEN];
933a27d3
DH
764
765 usbnet_get_endpoints(dev,intf);
766
933a27d3 767 /* Get the MAC address */
83e1b918
GG
768 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
769 if (ret < 0) {
933a27d3 770 dbg("Failed to read MAC address: %d", ret);
83e1b918 771 return ret;
2e55cc72 772 }
933a27d3 773 memcpy(dev->net->dev_addr, buf, ETH_ALEN);
2e55cc72 774
933a27d3
DH
775 /* Initialize MII structure */
776 dev->mii.dev = dev->net;
777 dev->mii.mdio_read = asix_mdio_read;
778 dev->mii.mdio_write = asix_mdio_write;
779 dev->mii.phy_id_mask = 0x1f;
780 dev->mii.reg_num_mask = 0xff;
781 dev->mii.supports_gmii = 1;
933a27d3 782 dev->mii.phy_id = asix_get_phy_addr(dev);
1703338c
SH
783
784 dev->net->netdev_ops = &ax88178_netdev_ops;
933a27d3 785 dev->net->ethtool_ops = &ax88178_ethtool_ops;
2e55cc72 786
b2d3ad29
GG
787 /* Blink LEDS so users know driver saw dongle */
788 asix_sw_reset(dev, 0);
789 msleep(150);
2e55cc72 790
b2d3ad29
GG
791 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD);
792 msleep(150);
933a27d3
DH
793
794 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
795 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
796 /* hard_mtu is still the default - the device does not support
797 jumbo eth frames */
798 dev->rx_urb_size = 2048;
799 }
933a27d3 800
83e1b918 801 return 0;
2e55cc72
DB
802}
803
804static const struct driver_info ax8817x_info = {
805 .description = "ASIX AX8817x USB 2.0 Ethernet",
48b1be6a
DH
806 .bind = ax88172_bind,
807 .status = asix_status,
2e55cc72
DB
808 .link_reset = ax88172_link_reset,
809 .reset = ax88172_link_reset,
37e8273c 810 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB
811 .data = 0x00130103,
812};
813
814static const struct driver_info dlink_dub_e100_info = {
815 .description = "DLink DUB-E100 USB Ethernet",
48b1be6a
DH
816 .bind = ax88172_bind,
817 .status = asix_status,
2e55cc72
DB
818 .link_reset = ax88172_link_reset,
819 .reset = ax88172_link_reset,
37e8273c 820 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB
821 .data = 0x009f9d9f,
822};
823
824static const struct driver_info netgear_fa120_info = {
825 .description = "Netgear FA-120 USB Ethernet",
48b1be6a
DH
826 .bind = ax88172_bind,
827 .status = asix_status,
2e55cc72
DB
828 .link_reset = ax88172_link_reset,
829 .reset = ax88172_link_reset,
37e8273c 830 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB
831 .data = 0x00130103,
832};
833
834static const struct driver_info hawking_uf200_info = {
835 .description = "Hawking UF200 USB Ethernet",
48b1be6a
DH
836 .bind = ax88172_bind,
837 .status = asix_status,
2e55cc72
DB
838 .link_reset = ax88172_link_reset,
839 .reset = ax88172_link_reset,
37e8273c 840 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB
841 .data = 0x001f1d1f,
842};
843
844static const struct driver_info ax88772_info = {
845 .description = "ASIX AX88772 USB 2.0 Ethernet",
846 .bind = ax88772_bind,
48b1be6a 847 .status = asix_status,
2e55cc72 848 .link_reset = ax88772_link_reset,
4ad1438f 849 .reset = ax88772_reset,
a9e0aca4 850 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET,
933a27d3
DH
851 .rx_fixup = asix_rx_fixup,
852 .tx_fixup = asix_tx_fixup,
853};
854
855static const struct driver_info ax88178_info = {
856 .description = "ASIX AX88178 USB 2.0 Ethernet",
857 .bind = ax88178_bind,
858 .status = asix_status,
859 .link_reset = ax88178_link_reset,
610d885d 860 .reset = ax88178_reset,
37e8273c 861 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR,
933a27d3
DH
862 .rx_fixup = asix_rx_fixup,
863 .tx_fixup = asix_tx_fixup,
2e55cc72
DB
864};
865
16626b0c
CR
866extern const struct driver_info ax88172a_info;
867
2e55cc72
DB
868static const struct usb_device_id products [] = {
869{
870 // Linksys USB200M
871 USB_DEVICE (0x077b, 0x2226),
872 .driver_info = (unsigned long) &ax8817x_info,
873}, {
874 // Netgear FA120
875 USB_DEVICE (0x0846, 0x1040),
876 .driver_info = (unsigned long) &netgear_fa120_info,
877}, {
878 // DLink DUB-E100
879 USB_DEVICE (0x2001, 0x1a00),
880 .driver_info = (unsigned long) &dlink_dub_e100_info,
881}, {
882 // Intellinet, ST Lab USB Ethernet
883 USB_DEVICE (0x0b95, 0x1720),
884 .driver_info = (unsigned long) &ax8817x_info,
885}, {
886 // Hawking UF200, TrendNet TU2-ET100
887 USB_DEVICE (0x07b8, 0x420a),
888 .driver_info = (unsigned long) &hawking_uf200_info,
889}, {
39c4b38c
DH
890 // Billionton Systems, USB2AR
891 USB_DEVICE (0x08dd, 0x90ff),
892 .driver_info = (unsigned long) &ax8817x_info,
2e55cc72
DB
893}, {
894 // ATEN UC210T
895 USB_DEVICE (0x0557, 0x2009),
896 .driver_info = (unsigned long) &ax8817x_info,
897}, {
898 // Buffalo LUA-U2-KTX
899 USB_DEVICE (0x0411, 0x003d),
900 .driver_info = (unsigned long) &ax8817x_info,
ac7b77f1
MD
901}, {
902 // Buffalo LUA-U2-GT 10/100/1000
903 USB_DEVICE (0x0411, 0x006e),
904 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB
905}, {
906 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
907 USB_DEVICE (0x6189, 0x182d),
908 .driver_info = (unsigned long) &ax8817x_info,
4e503919
JN
909}, {
910 // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter"
911 USB_DEVICE (0x0df6, 0x0056),
912 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB
913}, {
914 // corega FEther USB2-TX
915 USB_DEVICE (0x07aa, 0x0017),
916 .driver_info = (unsigned long) &ax8817x_info,
917}, {
918 // Surecom EP-1427X-2
919 USB_DEVICE (0x1189, 0x0893),
920 .driver_info = (unsigned long) &ax8817x_info,
921}, {
922 // goodway corp usb gwusb2e
923 USB_DEVICE (0x1631, 0x6200),
924 .driver_info = (unsigned long) &ax8817x_info,
39c4b38c
DH
925}, {
926 // JVC MP-PRX1 Port Replicator
927 USB_DEVICE (0x04f1, 0x3008),
928 .driver_info = (unsigned long) &ax8817x_info,
30885909
MV
929}, {
930 // ASIX AX88772B 10/100
931 USB_DEVICE (0x0b95, 0x772b),
932 .driver_info = (unsigned long) &ax88772_info,
2e55cc72
DB
933}, {
934 // ASIX AX88772 10/100
39c4b38c
DH
935 USB_DEVICE (0x0b95, 0x7720),
936 .driver_info = (unsigned long) &ax88772_info,
7327413c
EW
937}, {
938 // ASIX AX88178 10/100/1000
939 USB_DEVICE (0x0b95, 0x1780),
933a27d3 940 .driver_info = (unsigned long) &ax88178_info,
f4680d3d
AE
941}, {
942 // Logitec LAN-GTJ/U2A
943 USB_DEVICE (0x0789, 0x0160),
944 .driver_info = (unsigned long) &ax88178_info,
5e0f76c6
DH
945}, {
946 // Linksys USB200M Rev 2
947 USB_DEVICE (0x13b1, 0x0018),
948 .driver_info = (unsigned long) &ax88772_info,
5732ce84
DH
949}, {
950 // 0Q0 cable ethernet
951 USB_DEVICE (0x1557, 0x7720),
952 .driver_info = (unsigned long) &ax88772_info,
933a27d3
DH
953}, {
954 // DLink DUB-E100 H/W Ver B1
955 USB_DEVICE (0x07d1, 0x3c05),
956 .driver_info = (unsigned long) &ax88772_info,
b923e7fc
DH
957}, {
958 // DLink DUB-E100 H/W Ver B1 Alternate
959 USB_DEVICE (0x2001, 0x3c05),
960 .driver_info = (unsigned long) &ax88772_info,
933a27d3
DH
961}, {
962 // Linksys USB1000
963 USB_DEVICE (0x1737, 0x0039),
964 .driver_info = (unsigned long) &ax88178_info,
b29cf31d
YH
965}, {
966 // IO-DATA ETG-US2
967 USB_DEVICE (0x04bb, 0x0930),
968 .driver_info = (unsigned long) &ax88178_info,
2ed22bc2
DH
969}, {
970 // Belkin F5D5055
971 USB_DEVICE(0x050d, 0x5055),
972 .driver_info = (unsigned long) &ax88178_info,
3d60efb5
AN
973}, {
974 // Apple USB Ethernet Adapter
975 USB_DEVICE(0x05ac, 0x1402),
976 .driver_info = (unsigned long) &ax88772_info,
ccf95402
JC
977}, {
978 // Cables-to-Go USB Ethernet Adapter
979 USB_DEVICE(0x0b95, 0x772a),
980 .driver_info = (unsigned long) &ax88772_info,
fef7cc08
GKH
981}, {
982 // ABOCOM for pci
983 USB_DEVICE(0x14ea, 0xab11),
984 .driver_info = (unsigned long) &ax88178_info,
985}, {
986 // ASIX 88772a
987 USB_DEVICE(0x0db0, 0xa877),
988 .driver_info = (unsigned long) &ax88772_info,
e8303a3b
AJ
989}, {
990 // Asus USB Ethernet Adapter
991 USB_DEVICE (0x0b95, 0x7e2b),
992 .driver_info = (unsigned long) &ax88772_info,
16626b0c
CR
993}, {
994 /* ASIX 88172a demo board */
995 USB_DEVICE(0x0b95, 0x172a),
996 .driver_info = (unsigned long) &ax88172a_info,
2e55cc72
DB
997},
998 { }, // END
999};
1000MODULE_DEVICE_TABLE(usb, products);
1001
1002static struct usb_driver asix_driver = {
83e1b918 1003 .name = DRIVER_NAME,
2e55cc72
DB
1004 .id_table = products,
1005 .probe = usbnet_probe,
1006 .suspend = usbnet_suspend,
1007 .resume = usbnet_resume,
1008 .disconnect = usbnet_disconnect,
a11a6544 1009 .supports_autosuspend = 1,
e1f12eb6 1010 .disable_hub_initiated_lpm = 1,
2e55cc72
DB
1011};
1012
d632eb1b 1013module_usb_driver(asix_driver);
2e55cc72
DB
1014
1015MODULE_AUTHOR("David Hollis");
4ad1438f 1016MODULE_VERSION(DRIVER_VERSION);
2e55cc72
DB
1017MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
1018MODULE_LICENSE("GPL");
1019
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