ac718b69 |
1 | /* |
2 | * Copyright (c) 2013 Realtek Semiconductor Corp. All rights reserved. |
3 | * |
4 | * This program is free software; you can redistribute it and/or |
5 | * modify it under the terms of the GNU General Public License |
6 | * version 2 as published by the Free Software Foundation. |
7 | * |
8 | */ |
9 | |
10 | #include <linux/init.h> |
11 | #include <linux/signal.h> |
12 | #include <linux/slab.h> |
13 | #include <linux/module.h> |
ac718b69 |
14 | #include <linux/netdevice.h> |
15 | #include <linux/etherdevice.h> |
16 | #include <linux/mii.h> |
17 | #include <linux/ethtool.h> |
18 | #include <linux/usb.h> |
19 | #include <linux/crc32.h> |
20 | #include <linux/if_vlan.h> |
21 | #include <linux/uaccess.h> |
22 | |
23 | /* Version Information */ |
24 | #define DRIVER_VERSION "v1.0.0 (2013/05/03)" |
25 | #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" |
26 | #define DRIVER_DESC "Realtek RTL8152 Based USB 2.0 Ethernet Adapters" |
27 | #define MODULENAME "r8152" |
28 | |
29 | #define R8152_PHY_ID 32 |
30 | |
31 | #define PLA_IDR 0xc000 |
32 | #define PLA_RCR 0xc010 |
33 | #define PLA_RMS 0xc016 |
34 | #define PLA_RXFIFO_CTRL0 0xc0a0 |
35 | #define PLA_RXFIFO_CTRL1 0xc0a4 |
36 | #define PLA_RXFIFO_CTRL2 0xc0a8 |
37 | #define PLA_FMC 0xc0b4 |
38 | #define PLA_CFG_WOL 0xc0b6 |
39 | #define PLA_MAR 0xcd00 |
40 | #define PAL_BDC_CR 0xd1a0 |
41 | #define PLA_LEDSEL 0xdd90 |
42 | #define PLA_LED_FEATURE 0xdd92 |
43 | #define PLA_PHYAR 0xde00 |
44 | #define PLA_GPHY_INTR_IMR 0xe022 |
45 | #define PLA_EEE_CR 0xe040 |
46 | #define PLA_EEEP_CR 0xe080 |
47 | #define PLA_MAC_PWR_CTRL 0xe0c0 |
48 | #define PLA_TCR0 0xe610 |
49 | #define PLA_TCR1 0xe612 |
50 | #define PLA_TXFIFO_CTRL 0xe618 |
51 | #define PLA_RSTTELLY 0xe800 |
52 | #define PLA_CR 0xe813 |
53 | #define PLA_CRWECR 0xe81c |
54 | #define PLA_CONFIG5 0xe822 |
55 | #define PLA_PHY_PWR 0xe84c |
56 | #define PLA_OOB_CTRL 0xe84f |
57 | #define PLA_CPCR 0xe854 |
58 | #define PLA_MISC_0 0xe858 |
59 | #define PLA_MISC_1 0xe85a |
60 | #define PLA_OCP_GPHY_BASE 0xe86c |
61 | #define PLA_TELLYCNT 0xe890 |
62 | #define PLA_SFF_STS_7 0xe8de |
63 | #define PLA_PHYSTATUS 0xe908 |
64 | #define PLA_BP_BA 0xfc26 |
65 | #define PLA_BP_0 0xfc28 |
66 | #define PLA_BP_1 0xfc2a |
67 | #define PLA_BP_2 0xfc2c |
68 | #define PLA_BP_3 0xfc2e |
69 | #define PLA_BP_4 0xfc30 |
70 | #define PLA_BP_5 0xfc32 |
71 | #define PLA_BP_6 0xfc34 |
72 | #define PLA_BP_7 0xfc36 |
73 | |
74 | #define USB_DEV_STAT 0xb808 |
75 | #define USB_USB_CTRL 0xd406 |
76 | #define USB_PHY_CTRL 0xd408 |
77 | #define USB_TX_AGG 0xd40a |
78 | #define USB_RX_BUF_TH 0xd40c |
79 | #define USB_USB_TIMER 0xd428 |
80 | #define USB_PM_CTRL_STATUS 0xd432 |
81 | #define USB_TX_DMA 0xd434 |
82 | #define USB_UPS_CTRL 0xd800 |
83 | #define USB_BP_BA 0xfc26 |
84 | #define USB_BP_0 0xfc28 |
85 | #define USB_BP_1 0xfc2a |
86 | #define USB_BP_2 0xfc2c |
87 | #define USB_BP_3 0xfc2e |
88 | #define USB_BP_4 0xfc30 |
89 | #define USB_BP_5 0xfc32 |
90 | #define USB_BP_6 0xfc34 |
91 | #define USB_BP_7 0xfc36 |
92 | |
93 | /* OCP Registers */ |
94 | #define OCP_ALDPS_CONFIG 0x2010 |
95 | #define OCP_EEE_CONFIG1 0x2080 |
96 | #define OCP_EEE_CONFIG2 0x2092 |
97 | #define OCP_EEE_CONFIG3 0x2094 |
98 | #define OCP_EEE_AR 0xa41a |
99 | #define OCP_EEE_DATA 0xa41c |
100 | |
101 | /* PLA_RCR */ |
102 | #define RCR_AAP 0x00000001 |
103 | #define RCR_APM 0x00000002 |
104 | #define RCR_AM 0x00000004 |
105 | #define RCR_AB 0x00000008 |
106 | #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) |
107 | |
108 | /* PLA_RXFIFO_CTRL0 */ |
109 | #define RXFIFO_THR1_NORMAL 0x00080002 |
110 | #define RXFIFO_THR1_OOB 0x01800003 |
111 | |
112 | /* PLA_RXFIFO_CTRL1 */ |
113 | #define RXFIFO_THR2_FULL 0x00000060 |
114 | #define RXFIFO_THR2_HIGH 0x00000038 |
115 | #define RXFIFO_THR2_OOB 0x0000004a |
116 | |
117 | /* PLA_RXFIFO_CTRL2 */ |
118 | #define RXFIFO_THR3_FULL 0x00000078 |
119 | #define RXFIFO_THR3_HIGH 0x00000048 |
120 | #define RXFIFO_THR3_OOB 0x0000005a |
121 | |
122 | /* PLA_TXFIFO_CTRL */ |
123 | #define TXFIFO_THR_NORMAL 0x00400008 |
124 | |
125 | /* PLA_FMC */ |
126 | #define FMC_FCR_MCU_EN 0x0001 |
127 | |
128 | /* PLA_EEEP_CR */ |
129 | #define EEEP_CR_EEEP_TX 0x0002 |
130 | |
131 | /* PLA_TCR0 */ |
132 | #define TCR0_TX_EMPTY 0x0800 |
133 | #define TCR0_AUTO_FIFO 0x0080 |
134 | |
135 | /* PLA_TCR1 */ |
136 | #define VERSION_MASK 0x7cf0 |
137 | |
138 | /* PLA_CR */ |
139 | #define CR_RST 0x10 |
140 | #define CR_RE 0x08 |
141 | #define CR_TE 0x04 |
142 | |
143 | /* PLA_CRWECR */ |
144 | #define CRWECR_NORAML 0x00 |
145 | #define CRWECR_CONFIG 0xc0 |
146 | |
147 | /* PLA_OOB_CTRL */ |
148 | #define NOW_IS_OOB 0x80 |
149 | #define TXFIFO_EMPTY 0x20 |
150 | #define RXFIFO_EMPTY 0x10 |
151 | #define LINK_LIST_READY 0x02 |
152 | #define DIS_MCU_CLROOB 0x01 |
153 | #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) |
154 | |
155 | /* PLA_MISC_1 */ |
156 | #define RXDY_GATED_EN 0x0008 |
157 | |
158 | /* PLA_SFF_STS_7 */ |
159 | #define RE_INIT_LL 0x8000 |
160 | #define MCU_BORW_EN 0x4000 |
161 | |
162 | /* PLA_CPCR */ |
163 | #define CPCR_RX_VLAN 0x0040 |
164 | |
165 | /* PLA_CFG_WOL */ |
166 | #define MAGIC_EN 0x0001 |
167 | |
168 | /* PAL_BDC_CR */ |
169 | #define ALDPS_PROXY_MODE 0x0001 |
170 | |
171 | /* PLA_CONFIG5 */ |
172 | #define LAN_WAKE_EN 0x0002 |
173 | |
174 | /* PLA_LED_FEATURE */ |
175 | #define LED_MODE_MASK 0x0700 |
176 | |
177 | /* PLA_PHY_PWR */ |
178 | #define TX_10M_IDLE_EN 0x0080 |
179 | #define PFM_PWM_SWITCH 0x0040 |
180 | |
181 | /* PLA_MAC_PWR_CTRL */ |
182 | #define D3_CLK_GATED_EN 0x00004000 |
183 | #define MCU_CLK_RATIO 0x07010f07 |
184 | #define MCU_CLK_RATIO_MASK 0x0f0f0f0f |
185 | |
186 | /* PLA_GPHY_INTR_IMR */ |
187 | #define GPHY_STS_MSK 0x0001 |
188 | #define SPEED_DOWN_MSK 0x0002 |
189 | #define SPDWN_RXDV_MSK 0x0004 |
190 | #define SPDWN_LINKCHG_MSK 0x0008 |
191 | |
192 | /* PLA_PHYAR */ |
193 | #define PHYAR_FLAG 0x80000000 |
194 | |
195 | /* PLA_EEE_CR */ |
196 | #define EEE_RX_EN 0x0001 |
197 | #define EEE_TX_EN 0x0002 |
198 | |
199 | /* USB_DEV_STAT */ |
200 | #define STAT_SPEED_MASK 0x0006 |
201 | #define STAT_SPEED_HIGH 0x0000 |
202 | #define STAT_SPEED_FULL 0x0001 |
203 | |
204 | /* USB_TX_AGG */ |
205 | #define TX_AGG_MAX_THRESHOLD 0x03 |
206 | |
207 | /* USB_RX_BUF_TH */ |
208 | #define RX_BUF_THR 0x7a120180 |
209 | |
210 | /* USB_TX_DMA */ |
211 | #define TEST_MODE_DISABLE 0x00000001 |
212 | #define TX_SIZE_ADJUST1 0x00000100 |
213 | |
214 | /* USB_UPS_CTRL */ |
215 | #define POWER_CUT 0x0100 |
216 | |
217 | /* USB_PM_CTRL_STATUS */ |
218 | #define RWSUME_INDICATE 0x0001 |
219 | |
220 | /* USB_USB_CTRL */ |
221 | #define RX_AGG_DISABLE 0x0010 |
222 | |
223 | /* OCP_ALDPS_CONFIG */ |
224 | #define ENPWRSAVE 0x8000 |
225 | #define ENPDNPS 0x0200 |
226 | #define LINKENA 0x0100 |
227 | #define DIS_SDSAVE 0x0010 |
228 | |
229 | /* OCP_EEE_CONFIG1 */ |
230 | #define RG_TXLPI_MSK_HFDUP 0x8000 |
231 | #define RG_MATCLR_EN 0x4000 |
232 | #define EEE_10_CAP 0x2000 |
233 | #define EEE_NWAY_EN 0x1000 |
234 | #define TX_QUIET_EN 0x0200 |
235 | #define RX_QUIET_EN 0x0100 |
236 | #define SDRISETIME 0x0010 /* bit 4 ~ 6 */ |
237 | #define RG_RXLPI_MSK_HFDUP 0x0008 |
238 | #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ |
239 | |
240 | /* OCP_EEE_CONFIG2 */ |
241 | #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ |
242 | #define RG_DACQUIET_EN 0x0400 |
243 | #define RG_LDVQUIET_EN 0x0200 |
244 | #define RG_CKRSEL 0x0020 |
245 | #define RG_EEEPRG_EN 0x0010 |
246 | |
247 | /* OCP_EEE_CONFIG3 */ |
248 | #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */ |
249 | #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ |
250 | #define MSK_PH 0x0006 /* bit 0 ~ 3 */ |
251 | |
252 | /* OCP_EEE_AR */ |
253 | /* bit[15:14] function */ |
254 | #define FUN_ADDR 0x0000 |
255 | #define FUN_DATA 0x4000 |
256 | /* bit[4:0] device addr */ |
257 | #define DEVICE_ADDR 0x0007 |
258 | |
259 | /* OCP_EEE_DATA */ |
260 | #define EEE_ADDR 0x003C |
261 | #define EEE_DATA 0x0002 |
262 | |
263 | enum rtl_register_content { |
264 | _100bps = 0x08, |
265 | _10bps = 0x04, |
266 | LINK_STATUS = 0x02, |
267 | FULL_DUP = 0x01, |
268 | }; |
269 | |
270 | #define RTL8152_REQT_READ 0xc0 |
271 | #define RTL8152_REQT_WRITE 0x40 |
272 | #define RTL8152_REQ_GET_REGS 0x05 |
273 | #define RTL8152_REQ_SET_REGS 0x05 |
274 | |
275 | #define BYTE_EN_DWORD 0xff |
276 | #define BYTE_EN_WORD 0x33 |
277 | #define BYTE_EN_BYTE 0x11 |
278 | #define BYTE_EN_SIX_BYTES 0x3f |
279 | #define BYTE_EN_START_MASK 0x0f |
280 | #define BYTE_EN_END_MASK 0xf0 |
281 | |
282 | #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) |
283 | #define RTL8152_TX_TIMEOUT (HZ) |
284 | |
285 | /* rtl8152 flags */ |
286 | enum rtl8152_flags { |
287 | RTL8152_UNPLUG = 0, |
288 | RX_URB_FAIL, |
289 | RTL8152_SET_RX_MODE, |
290 | WORK_ENABLE |
291 | }; |
292 | |
293 | /* Define these values to match your device */ |
294 | #define VENDOR_ID_REALTEK 0x0bda |
295 | #define PRODUCT_ID_RTL8152 0x8152 |
296 | |
297 | #define MCU_TYPE_PLA 0x0100 |
298 | #define MCU_TYPE_USB 0x0000 |
299 | |
300 | struct rx_desc { |
301 | u32 opts1; |
302 | #define RX_LEN_MASK 0x7fff |
303 | u32 opts2; |
304 | u32 opts3; |
305 | u32 opts4; |
306 | u32 opts5; |
307 | u32 opts6; |
308 | }; |
309 | |
310 | struct tx_desc { |
311 | u32 opts1; |
312 | #define TX_FS (1 << 31) /* First segment of a packet */ |
313 | #define TX_LS (1 << 30) /* Final segment of a packet */ |
314 | #define TX_LEN_MASK 0xffff |
315 | u32 opts2; |
316 | }; |
317 | |
318 | struct r8152 { |
319 | unsigned long flags; |
320 | struct usb_device *udev; |
321 | struct tasklet_struct tl; |
322 | struct net_device *netdev; |
323 | struct urb *rx_urb, *tx_urb; |
324 | struct sk_buff *tx_skb, *rx_skb; |
325 | struct delayed_work schedule; |
326 | struct mii_if_info mii; |
327 | u32 msg_enable; |
328 | u16 ocp_base; |
329 | u8 version; |
330 | u8 speed; |
331 | }; |
332 | |
333 | enum rtl_version { |
334 | RTL_VER_UNKNOWN = 0, |
335 | RTL_VER_01, |
336 | RTL_VER_02 |
337 | }; |
338 | |
339 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
340 | * The RTL chips use a 64 element hash table based on the Ethernet CRC. |
341 | */ |
342 | static const int multicast_filter_limit = 32; |
343 | |
344 | static |
345 | int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) |
346 | { |
347 | return usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), |
348 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, |
349 | value, index, data, size, 500); |
350 | } |
351 | |
352 | static |
353 | int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) |
354 | { |
355 | return usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), |
356 | RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, |
357 | value, index, data, size, 500); |
358 | } |
359 | |
360 | static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, |
361 | void *data, u16 type) |
362 | { |
363 | u16 limit = 64; |
364 | int ret = 0; |
365 | |
366 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
367 | return -ENODEV; |
368 | |
369 | /* both size and indix must be 4 bytes align */ |
370 | if ((size & 3) || !size || (index & 3) || !data) |
371 | return -EPERM; |
372 | |
373 | if ((u32)index + (u32)size > 0xffff) |
374 | return -EPERM; |
375 | |
376 | while (size) { |
377 | if (size > limit) { |
378 | ret = get_registers(tp, index, type, limit, data); |
379 | if (ret < 0) |
380 | break; |
381 | |
382 | index += limit; |
383 | data += limit; |
384 | size -= limit; |
385 | } else { |
386 | ret = get_registers(tp, index, type, size, data); |
387 | if (ret < 0) |
388 | break; |
389 | |
390 | index += size; |
391 | data += size; |
392 | size = 0; |
393 | break; |
394 | } |
395 | } |
396 | |
397 | return ret; |
398 | } |
399 | |
400 | static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, |
401 | u16 size, void *data, u16 type) |
402 | { |
403 | int ret; |
404 | u16 byteen_start, byteen_end, byen; |
405 | u16 limit = 512; |
406 | |
407 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
408 | return -ENODEV; |
409 | |
410 | /* both size and indix must be 4 bytes align */ |
411 | if ((size & 3) || !size || (index & 3) || !data) |
412 | return -EPERM; |
413 | |
414 | if ((u32)index + (u32)size > 0xffff) |
415 | return -EPERM; |
416 | |
417 | byteen_start = byteen & BYTE_EN_START_MASK; |
418 | byteen_end = byteen & BYTE_EN_END_MASK; |
419 | |
420 | byen = byteen_start | (byteen_start << 4); |
421 | ret = set_registers(tp, index, type | byen, 4, data); |
422 | if (ret < 0) |
423 | goto error1; |
424 | |
425 | index += 4; |
426 | data += 4; |
427 | size -= 4; |
428 | |
429 | if (size) { |
430 | size -= 4; |
431 | |
432 | while (size) { |
433 | if (size > limit) { |
434 | ret = set_registers(tp, index, |
435 | type | BYTE_EN_DWORD, |
436 | limit, data); |
437 | if (ret < 0) |
438 | goto error1; |
439 | |
440 | index += limit; |
441 | data += limit; |
442 | size -= limit; |
443 | } else { |
444 | ret = set_registers(tp, index, |
445 | type | BYTE_EN_DWORD, |
446 | size, data); |
447 | if (ret < 0) |
448 | goto error1; |
449 | |
450 | index += size; |
451 | data += size; |
452 | size = 0; |
453 | break; |
454 | } |
455 | } |
456 | |
457 | byen = byteen_end | (byteen_end >> 4); |
458 | ret = set_registers(tp, index, type | byen, 4, data); |
459 | if (ret < 0) |
460 | goto error1; |
461 | } |
462 | |
463 | error1: |
464 | return ret; |
465 | } |
466 | |
467 | static inline |
468 | int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) |
469 | { |
470 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); |
471 | } |
472 | |
473 | static inline |
474 | int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) |
475 | { |
476 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); |
477 | } |
478 | |
479 | static inline |
480 | int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) |
481 | { |
482 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); |
483 | } |
484 | |
485 | static inline |
486 | int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) |
487 | { |
488 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); |
489 | } |
490 | |
491 | static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) |
492 | { |
493 | u32 data; |
494 | |
495 | if (type == MCU_TYPE_PLA) |
496 | pla_ocp_read(tp, index, sizeof(data), &data); |
497 | else |
498 | usb_ocp_read(tp, index, sizeof(data), &data); |
499 | |
500 | return __le32_to_cpu(data); |
501 | } |
502 | |
503 | static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) |
504 | { |
505 | if (type == MCU_TYPE_PLA) |
506 | pla_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(data), &data); |
507 | else |
508 | usb_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(data), &data); |
509 | } |
510 | |
511 | static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) |
512 | { |
513 | u32 data; |
514 | u8 shift = index & 2; |
515 | |
516 | index &= ~3; |
517 | |
518 | if (type == MCU_TYPE_PLA) |
519 | pla_ocp_read(tp, index, sizeof(data), &data); |
520 | else |
521 | usb_ocp_read(tp, index, sizeof(data), &data); |
522 | |
523 | data = __le32_to_cpu(data); |
524 | data >>= (shift * 8); |
525 | data &= 0xffff; |
526 | |
527 | return (u16)data; |
528 | } |
529 | |
530 | static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) |
531 | { |
532 | u32 tmp, mask = 0xffff; |
533 | u16 byen = BYTE_EN_WORD; |
534 | u8 shift = index & 2; |
535 | |
536 | data &= mask; |
537 | |
538 | if (index & 2) { |
539 | byen <<= shift; |
540 | mask <<= (shift * 8); |
541 | data <<= (shift * 8); |
542 | index &= ~3; |
543 | } |
544 | |
545 | if (type == MCU_TYPE_PLA) |
546 | pla_ocp_read(tp, index, sizeof(tmp), &tmp); |
547 | else |
548 | usb_ocp_read(tp, index, sizeof(tmp), &tmp); |
549 | |
550 | tmp = __le32_to_cpu(tmp) & ~mask; |
551 | tmp |= data; |
552 | tmp = __cpu_to_le32(tmp); |
553 | |
554 | if (type == MCU_TYPE_PLA) |
555 | pla_ocp_write(tp, index, byen, sizeof(tmp), &tmp); |
556 | else |
557 | usb_ocp_write(tp, index, byen, sizeof(tmp), &tmp); |
558 | } |
559 | |
560 | static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) |
561 | { |
562 | u32 data; |
563 | u8 shift = index & 3; |
564 | |
565 | index &= ~3; |
566 | |
567 | if (type == MCU_TYPE_PLA) |
568 | pla_ocp_read(tp, index, sizeof(data), &data); |
569 | else |
570 | usb_ocp_read(tp, index, sizeof(data), &data); |
571 | |
572 | data = __le32_to_cpu(data); |
573 | data >>= (shift * 8); |
574 | data &= 0xff; |
575 | |
576 | return (u8)data; |
577 | } |
578 | |
579 | static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) |
580 | { |
581 | u32 tmp, mask = 0xff; |
582 | u16 byen = BYTE_EN_BYTE; |
583 | u8 shift = index & 3; |
584 | |
585 | data &= mask; |
586 | |
587 | if (index & 3) { |
588 | byen <<= shift; |
589 | mask <<= (shift * 8); |
590 | data <<= (shift * 8); |
591 | index &= ~3; |
592 | } |
593 | |
594 | if (type == MCU_TYPE_PLA) |
595 | pla_ocp_read(tp, index, sizeof(tmp), &tmp); |
596 | else |
597 | usb_ocp_read(tp, index, sizeof(tmp), &tmp); |
598 | |
599 | tmp = __le32_to_cpu(tmp) & ~mask; |
600 | tmp |= data; |
601 | tmp = __cpu_to_le32(tmp); |
602 | |
603 | if (type == MCU_TYPE_PLA) |
604 | pla_ocp_write(tp, index, byen, sizeof(tmp), &tmp); |
605 | else |
606 | usb_ocp_write(tp, index, byen, sizeof(tmp), &tmp); |
607 | } |
608 | |
609 | static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) |
610 | { |
611 | u32 ocp_data; |
612 | int i; |
613 | |
614 | ocp_data = PHYAR_FLAG | ((reg_addr & 0x1f) << 16) | |
615 | (value & 0xffff); |
616 | |
617 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data); |
618 | |
619 | for (i = 20; i > 0; i--) { |
620 | udelay(25); |
621 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR); |
622 | if (!(ocp_data & PHYAR_FLAG)) |
623 | break; |
624 | } |
625 | udelay(20); |
626 | } |
627 | |
628 | static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) |
629 | { |
630 | u32 ocp_data; |
631 | int i; |
632 | |
633 | ocp_data = (reg_addr & 0x1f) << 16; |
634 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data); |
635 | |
636 | for (i = 20; i > 0; i--) { |
637 | udelay(25); |
638 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR); |
639 | if (ocp_data & PHYAR_FLAG) |
640 | break; |
641 | } |
642 | udelay(20); |
643 | |
644 | if (!(ocp_data & PHYAR_FLAG)) |
645 | return -EAGAIN; |
646 | |
647 | return (u16)(ocp_data & 0xffff); |
648 | } |
649 | |
650 | static int read_mii_word(struct net_device *netdev, int phy_id, int reg) |
651 | { |
652 | struct r8152 *tp = netdev_priv(netdev); |
653 | |
654 | if (phy_id != R8152_PHY_ID) |
655 | return -EINVAL; |
656 | |
657 | return r8152_mdio_read(tp, reg); |
658 | } |
659 | |
660 | static |
661 | void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) |
662 | { |
663 | struct r8152 *tp = netdev_priv(netdev); |
664 | |
665 | if (phy_id != R8152_PHY_ID) |
666 | return; |
667 | |
668 | r8152_mdio_write(tp, reg, val); |
669 | } |
670 | |
671 | static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) |
672 | { |
673 | u16 ocp_base, ocp_index; |
674 | |
675 | ocp_base = addr & 0xf000; |
676 | if (ocp_base != tp->ocp_base) { |
677 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); |
678 | tp->ocp_base = ocp_base; |
679 | } |
680 | |
681 | ocp_index = (addr & 0x0fff) | 0xb000; |
682 | ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); |
683 | } |
684 | |
685 | static inline void set_ethernet_addr(struct r8152 *tp) |
686 | { |
687 | struct net_device *dev = tp->netdev; |
688 | u8 *node_id; |
689 | |
690 | node_id = kmalloc(sizeof(u8) * 8, GFP_KERNEL); |
691 | if (!node_id) { |
692 | netif_err(tp, probe, dev, "out of memory"); |
693 | return; |
694 | } |
695 | |
696 | if (pla_ocp_read(tp, PLA_IDR, sizeof(u8) * 8, node_id) < 0) |
697 | netif_notice(tp, probe, dev, "inet addr fail\n"); |
698 | else { |
699 | memcpy(dev->dev_addr, node_id, dev->addr_len); |
700 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
701 | } |
702 | kfree(node_id); |
703 | } |
704 | |
705 | static int rtl8152_set_mac_address(struct net_device *netdev, void *p) |
706 | { |
707 | struct r8152 *tp = netdev_priv(netdev); |
708 | struct sockaddr *addr = p; |
709 | |
710 | if (!is_valid_ether_addr(addr->sa_data)) |
711 | return -EADDRNOTAVAIL; |
712 | |
713 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); |
714 | |
715 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); |
716 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); |
717 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); |
718 | |
719 | return 0; |
720 | } |
721 | |
722 | static int alloc_all_urbs(struct r8152 *tp) |
723 | { |
724 | tp->rx_urb = usb_alloc_urb(0, GFP_KERNEL); |
725 | if (!tp->rx_urb) |
726 | return 0; |
727 | tp->tx_urb = usb_alloc_urb(0, GFP_KERNEL); |
728 | if (!tp->tx_urb) { |
729 | usb_free_urb(tp->rx_urb); |
730 | return 0; |
731 | } |
732 | |
733 | return 1; |
734 | } |
735 | |
736 | static void free_all_urbs(struct r8152 *tp) |
737 | { |
738 | usb_free_urb(tp->rx_urb); |
739 | usb_free_urb(tp->tx_urb); |
740 | } |
741 | |
742 | static struct net_device_stats *rtl8152_get_stats(struct net_device *dev) |
743 | { |
744 | return &dev->stats; |
745 | } |
746 | |
747 | static void read_bulk_callback(struct urb *urb) |
748 | { |
749 | struct r8152 *tp; |
750 | unsigned pkt_len; |
751 | struct sk_buff *skb; |
752 | struct net_device *netdev; |
753 | struct net_device_stats *stats; |
754 | int status = urb->status; |
755 | int result; |
756 | struct rx_desc *rx_desc; |
757 | |
758 | tp = urb->context; |
759 | if (!tp) |
760 | return; |
761 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
762 | return; |
763 | netdev = tp->netdev; |
764 | if (!netif_device_present(netdev)) |
765 | return; |
766 | |
767 | stats = rtl8152_get_stats(netdev); |
768 | switch (status) { |
769 | case 0: |
770 | break; |
771 | case -ESHUTDOWN: |
772 | set_bit(RTL8152_UNPLUG, &tp->flags); |
773 | netif_device_detach(tp->netdev); |
774 | case -ENOENT: |
775 | return; /* the urb is in unlink state */ |
776 | case -ETIME: |
777 | pr_warn_ratelimited("may be reset is needed?..\n"); |
778 | goto goon; |
779 | default: |
780 | pr_warn_ratelimited("Rx status %d\n", status); |
781 | goto goon; |
782 | } |
783 | |
784 | /* protect against short packets (tell me why we got some?!?) */ |
785 | if (urb->actual_length < sizeof(*rx_desc)) |
786 | goto goon; |
787 | |
788 | |
789 | rx_desc = (struct rx_desc *)urb->transfer_buffer; |
790 | pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; |
791 | if (urb->actual_length < sizeof(struct rx_desc) + pkt_len) |
792 | goto goon; |
793 | |
794 | skb = netdev_alloc_skb_ip_align(netdev, pkt_len); |
795 | if (!skb) |
796 | goto goon; |
797 | |
798 | memcpy(skb->data, tp->rx_skb->data + sizeof(struct rx_desc), pkt_len); |
799 | skb_put(skb, pkt_len); |
800 | skb->protocol = eth_type_trans(skb, netdev); |
801 | netif_rx(skb); |
802 | stats->rx_packets++; |
803 | stats->rx_bytes += pkt_len; |
804 | goon: |
805 | usb_fill_bulk_urb(tp->rx_urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), |
806 | tp->rx_skb->data, RTL8152_RMS + sizeof(struct rx_desc), |
807 | (usb_complete_t)read_bulk_callback, tp); |
808 | result = usb_submit_urb(tp->rx_urb, GFP_ATOMIC); |
809 | if (result == -ENODEV) { |
810 | netif_device_detach(tp->netdev); |
811 | } else if (result) { |
812 | set_bit(RX_URB_FAIL, &tp->flags); |
813 | goto resched; |
814 | } else { |
815 | clear_bit(RX_URB_FAIL, &tp->flags); |
816 | } |
817 | |
818 | return; |
819 | resched: |
820 | tasklet_schedule(&tp->tl); |
821 | } |
822 | |
823 | static void rx_fixup(unsigned long data) |
824 | { |
825 | struct r8152 *tp; |
826 | int status; |
827 | |
828 | tp = (struct r8152 *)data; |
829 | if (!test_bit(WORK_ENABLE, &tp->flags)) |
830 | return; |
831 | |
832 | status = usb_submit_urb(tp->rx_urb, GFP_ATOMIC); |
833 | if (status == -ENODEV) { |
834 | netif_device_detach(tp->netdev); |
835 | } else if (status) { |
836 | set_bit(RX_URB_FAIL, &tp->flags); |
837 | goto tlsched; |
838 | } else { |
839 | clear_bit(RX_URB_FAIL, &tp->flags); |
840 | } |
841 | |
842 | return; |
843 | tlsched: |
844 | tasklet_schedule(&tp->tl); |
845 | } |
846 | |
847 | static void write_bulk_callback(struct urb *urb) |
848 | { |
849 | struct r8152 *tp; |
850 | int status = urb->status; |
851 | |
852 | tp = urb->context; |
853 | if (!tp) |
854 | return; |
855 | dev_kfree_skb_irq(tp->tx_skb); |
856 | if (!netif_device_present(tp->netdev)) |
857 | return; |
858 | if (status) |
859 | dev_info(&urb->dev->dev, "%s: Tx status %d\n", |
860 | tp->netdev->name, status); |
861 | tp->netdev->trans_start = jiffies; |
862 | netif_wake_queue(tp->netdev); |
863 | } |
864 | |
865 | static void rtl8152_tx_timeout(struct net_device *netdev) |
866 | { |
867 | struct r8152 *tp = netdev_priv(netdev); |
868 | struct net_device_stats *stats = rtl8152_get_stats(netdev); |
869 | netif_warn(tp, tx_err, netdev, "Tx timeout.\n"); |
870 | usb_unlink_urb(tp->tx_urb); |
871 | stats->tx_errors++; |
872 | } |
873 | |
874 | static void rtl8152_set_rx_mode(struct net_device *netdev) |
875 | { |
876 | struct r8152 *tp = netdev_priv(netdev); |
877 | |
878 | if (tp->speed & LINK_STATUS) |
879 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
880 | } |
881 | |
882 | static void _rtl8152_set_rx_mode(struct net_device *netdev) |
883 | { |
884 | struct r8152 *tp = netdev_priv(netdev); |
885 | u32 tmp, *mc_filter; /* Multicast hash filter */ |
886 | u32 ocp_data; |
887 | |
888 | mc_filter = kmalloc(sizeof(u32) * 2, GFP_KERNEL); |
889 | if (!mc_filter) { |
890 | netif_err(tp, link, netdev, "out of memory"); |
891 | return; |
892 | } |
893 | |
894 | clear_bit(RTL8152_SET_RX_MODE, &tp->flags); |
895 | netif_stop_queue(netdev); |
896 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
897 | ocp_data &= ~RCR_ACPT_ALL; |
898 | ocp_data |= RCR_AB | RCR_APM; |
899 | |
900 | if (netdev->flags & IFF_PROMISC) { |
901 | /* Unconditionally log net taps. */ |
902 | netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); |
903 | ocp_data |= RCR_AM | RCR_AAP; |
904 | mc_filter[1] = mc_filter[0] = 0xffffffff; |
905 | } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || |
906 | (netdev->flags & IFF_ALLMULTI)) { |
907 | /* Too many to filter perfectly -- accept all multicasts. */ |
908 | ocp_data |= RCR_AM; |
909 | mc_filter[1] = mc_filter[0] = 0xffffffff; |
910 | } else { |
911 | struct netdev_hw_addr *ha; |
912 | |
913 | mc_filter[1] = mc_filter[0] = 0; |
914 | netdev_for_each_mc_addr(ha, netdev) { |
915 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; |
916 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
917 | ocp_data |= RCR_AM; |
918 | } |
919 | } |
920 | |
921 | tmp = mc_filter[0]; |
922 | mc_filter[0] = __cpu_to_le32(swab32(mc_filter[1])); |
923 | mc_filter[1] = __cpu_to_le32(swab32(tmp)); |
924 | |
925 | pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(u32) * 2, mc_filter); |
926 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
927 | netif_wake_queue(netdev); |
928 | kfree(mc_filter); |
929 | } |
930 | |
931 | static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, |
932 | struct net_device *netdev) |
933 | { |
934 | struct r8152 *tp = netdev_priv(netdev); |
935 | struct net_device_stats *stats = rtl8152_get_stats(netdev); |
936 | struct tx_desc *tx_desc; |
3ff25e3c |
937 | unsigned int len; |
938 | int res; |
ac718b69 |
939 | |
940 | netif_stop_queue(netdev); |
941 | len = skb->len; |
942 | if (skb_header_cloned(skb) || skb_headroom(skb) < sizeof(*tx_desc)) { |
943 | struct sk_buff *tx_skb; |
944 | |
945 | tx_skb = skb_copy_expand(skb, sizeof(*tx_desc), 0, GFP_ATOMIC); |
946 | dev_kfree_skb_any(skb); |
947 | if (!tx_skb) { |
948 | stats->tx_dropped++; |
949 | netif_wake_queue(netdev); |
950 | return NETDEV_TX_OK; |
951 | } |
952 | skb = tx_skb; |
953 | } |
954 | tx_desc = (struct tx_desc *)skb_push(skb, sizeof(*tx_desc)); |
955 | memset(tx_desc, 0, sizeof(*tx_desc)); |
956 | tx_desc->opts1 = cpu_to_le32((len & TX_LEN_MASK) | TX_FS | TX_LS); |
957 | tp->tx_skb = skb; |
958 | skb_tx_timestamp(skb); |
959 | usb_fill_bulk_urb(tp->tx_urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), |
960 | skb->data, skb->len, |
961 | (usb_complete_t)write_bulk_callback, tp); |
962 | res = usb_submit_urb(tp->tx_urb, GFP_ATOMIC); |
963 | if (res) { |
964 | /* Can we get/handle EPIPE here? */ |
965 | if (res == -ENODEV) { |
966 | netif_device_detach(tp->netdev); |
967 | } else { |
968 | netif_warn(tp, tx_err, netdev, |
969 | "failed tx_urb %d\n", res); |
970 | stats->tx_errors++; |
971 | netif_start_queue(netdev); |
972 | } |
973 | } else { |
974 | stats->tx_packets++; |
975 | stats->tx_bytes += skb->len; |
976 | } |
977 | |
978 | return NETDEV_TX_OK; |
979 | } |
980 | |
981 | static void r8152b_reset_packet_filter(struct r8152 *tp) |
982 | { |
983 | u32 ocp_data; |
984 | |
985 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); |
986 | ocp_data &= ~FMC_FCR_MCU_EN; |
987 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); |
988 | ocp_data |= FMC_FCR_MCU_EN; |
989 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); |
990 | } |
991 | |
992 | static void rtl8152_nic_reset(struct r8152 *tp) |
993 | { |
994 | int i; |
995 | |
996 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); |
997 | |
998 | for (i = 0; i < 1000; i++) { |
999 | if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) |
1000 | break; |
1001 | udelay(100); |
1002 | } |
1003 | } |
1004 | |
1005 | static inline u8 rtl8152_get_speed(struct r8152 *tp) |
1006 | { |
1007 | return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); |
1008 | } |
1009 | |
1010 | static int rtl8152_enable(struct r8152 *tp) |
1011 | { |
1012 | u32 ocp_data; |
1013 | u8 speed; |
1014 | |
1015 | speed = rtl8152_get_speed(tp); |
1016 | if (speed & _100bps) { |
1017 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); |
1018 | ocp_data &= ~EEEP_CR_EEEP_TX; |
1019 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1020 | } else { |
1021 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); |
1022 | ocp_data |= EEEP_CR_EEEP_TX; |
1023 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1024 | } |
1025 | |
1026 | r8152b_reset_packet_filter(tp); |
1027 | |
1028 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); |
1029 | ocp_data |= CR_RE | CR_TE; |
1030 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); |
1031 | |
1032 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); |
1033 | ocp_data &= ~RXDY_GATED_EN; |
1034 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); |
1035 | |
1036 | usb_fill_bulk_urb(tp->rx_urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), |
1037 | tp->rx_skb->data, RTL8152_RMS + sizeof(struct rx_desc), |
1038 | (usb_complete_t)read_bulk_callback, tp); |
1039 | |
1040 | return usb_submit_urb(tp->rx_urb, GFP_KERNEL); |
1041 | } |
1042 | |
1043 | static void rtl8152_disable(struct r8152 *tp) |
1044 | { |
1045 | u32 ocp_data; |
1046 | int i; |
1047 | |
1048 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
1049 | ocp_data &= ~RCR_ACPT_ALL; |
1050 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
1051 | |
1052 | usb_kill_urb(tp->tx_urb); |
1053 | |
1054 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); |
1055 | ocp_data |= RXDY_GATED_EN; |
1056 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); |
1057 | |
1058 | for (i = 0; i < 1000; i++) { |
1059 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
1060 | if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) |
1061 | break; |
1062 | mdelay(1); |
1063 | } |
1064 | |
1065 | for (i = 0; i < 1000; i++) { |
1066 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) |
1067 | break; |
1068 | mdelay(1); |
1069 | } |
1070 | |
1071 | usb_kill_urb(tp->rx_urb); |
1072 | |
1073 | rtl8152_nic_reset(tp); |
1074 | } |
1075 | |
1076 | static void r8152b_exit_oob(struct r8152 *tp) |
1077 | { |
1078 | u32 ocp_data; |
1079 | int i; |
1080 | |
1081 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
1082 | ocp_data &= ~RCR_ACPT_ALL; |
1083 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
1084 | |
1085 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); |
1086 | ocp_data |= RXDY_GATED_EN; |
1087 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); |
1088 | |
1089 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); |
1090 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); |
1091 | |
1092 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
1093 | ocp_data &= ~NOW_IS_OOB; |
1094 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); |
1095 | |
1096 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); |
1097 | ocp_data &= ~MCU_BORW_EN; |
1098 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); |
1099 | |
1100 | for (i = 0; i < 1000; i++) { |
1101 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
1102 | if (ocp_data & LINK_LIST_READY) |
1103 | break; |
1104 | mdelay(1); |
1105 | } |
1106 | |
1107 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); |
1108 | ocp_data |= RE_INIT_LL; |
1109 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); |
1110 | |
1111 | for (i = 0; i < 1000; i++) { |
1112 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
1113 | if (ocp_data & LINK_LIST_READY) |
1114 | break; |
1115 | mdelay(1); |
1116 | } |
1117 | |
1118 | rtl8152_nic_reset(tp); |
1119 | |
1120 | /* rx share fifo credit full threshold */ |
1121 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); |
1122 | |
1123 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT); |
1124 | ocp_data &= STAT_SPEED_MASK; |
1125 | if (ocp_data == STAT_SPEED_FULL) { |
1126 | /* rx share fifo credit near full threshold */ |
1127 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, |
1128 | RXFIFO_THR2_FULL); |
1129 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, |
1130 | RXFIFO_THR3_FULL); |
1131 | } else { |
1132 | /* rx share fifo credit near full threshold */ |
1133 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, |
1134 | RXFIFO_THR2_HIGH); |
1135 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, |
1136 | RXFIFO_THR3_HIGH); |
1137 | } |
1138 | |
1139 | /* TX share fifo free credit full threshold */ |
1140 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); |
1141 | |
1142 | ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); |
1143 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_BUF_THR); |
1144 | ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, |
1145 | TEST_MODE_DISABLE | TX_SIZE_ADJUST1); |
1146 | |
1147 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); |
1148 | ocp_data &= ~CPCR_RX_VLAN; |
1149 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); |
1150 | |
1151 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); |
1152 | |
1153 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); |
1154 | ocp_data |= TCR0_AUTO_FIFO; |
1155 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); |
1156 | } |
1157 | |
1158 | static void r8152b_enter_oob(struct r8152 *tp) |
1159 | { |
1160 | u32 ocp_data; |
1161 | int i; |
1162 | |
1163 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
1164 | ocp_data &= ~NOW_IS_OOB; |
1165 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); |
1166 | |
1167 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); |
1168 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); |
1169 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); |
1170 | |
1171 | rtl8152_disable(tp); |
1172 | |
1173 | for (i = 0; i < 1000; i++) { |
1174 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
1175 | if (ocp_data & LINK_LIST_READY) |
1176 | break; |
1177 | mdelay(1); |
1178 | } |
1179 | |
1180 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); |
1181 | ocp_data |= RE_INIT_LL; |
1182 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); |
1183 | |
1184 | for (i = 0; i < 1000; i++) { |
1185 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
1186 | if (ocp_data & LINK_LIST_READY) |
1187 | break; |
1188 | mdelay(1); |
1189 | } |
1190 | |
1191 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); |
1192 | |
1193 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); |
1194 | ocp_data |= MAGIC_EN; |
1195 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); |
1196 | |
1197 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); |
1198 | ocp_data |= CPCR_RX_VLAN; |
1199 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); |
1200 | |
1201 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); |
1202 | ocp_data |= ALDPS_PROXY_MODE; |
1203 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); |
1204 | |
1205 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
1206 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; |
1207 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); |
1208 | |
1209 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN); |
1210 | |
1211 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); |
1212 | ocp_data &= ~RXDY_GATED_EN; |
1213 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); |
1214 | |
1215 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
1216 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; |
1217 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
1218 | } |
1219 | |
1220 | static void r8152b_disable_aldps(struct r8152 *tp) |
1221 | { |
1222 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); |
1223 | msleep(20); |
1224 | } |
1225 | |
1226 | static inline void r8152b_enable_aldps(struct r8152 *tp) |
1227 | { |
1228 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | |
1229 | LINKENA | DIS_SDSAVE); |
1230 | } |
1231 | |
1232 | static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) |
1233 | { |
1234 | u16 bmcr, anar; |
1235 | int ret = 0; |
1236 | |
1237 | cancel_delayed_work_sync(&tp->schedule); |
1238 | anar = r8152_mdio_read(tp, MII_ADVERTISE); |
1239 | anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | |
1240 | ADVERTISE_100HALF | ADVERTISE_100FULL); |
1241 | |
1242 | if (autoneg == AUTONEG_DISABLE) { |
1243 | if (speed == SPEED_10) { |
1244 | bmcr = 0; |
1245 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; |
1246 | } else if (speed == SPEED_100) { |
1247 | bmcr = BMCR_SPEED100; |
1248 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; |
1249 | } else { |
1250 | ret = -EINVAL; |
1251 | goto out; |
1252 | } |
1253 | |
1254 | if (duplex == DUPLEX_FULL) |
1255 | bmcr |= BMCR_FULLDPLX; |
1256 | } else { |
1257 | if (speed == SPEED_10) { |
1258 | if (duplex == DUPLEX_FULL) |
1259 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; |
1260 | else |
1261 | anar |= ADVERTISE_10HALF; |
1262 | } else if (speed == SPEED_100) { |
1263 | if (duplex == DUPLEX_FULL) { |
1264 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; |
1265 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; |
1266 | } else { |
1267 | anar |= ADVERTISE_10HALF; |
1268 | anar |= ADVERTISE_100HALF; |
1269 | } |
1270 | } else { |
1271 | ret = -EINVAL; |
1272 | goto out; |
1273 | } |
1274 | |
1275 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; |
1276 | } |
1277 | |
1278 | r8152_mdio_write(tp, MII_ADVERTISE, anar); |
1279 | r8152_mdio_write(tp, MII_BMCR, bmcr); |
1280 | |
1281 | out: |
1282 | schedule_delayed_work(&tp->schedule, 5 * HZ); |
1283 | |
1284 | return ret; |
1285 | } |
1286 | |
1287 | static void rtl8152_down(struct r8152 *tp) |
1288 | { |
1289 | u32 ocp_data; |
1290 | |
1291 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); |
1292 | ocp_data &= ~POWER_CUT; |
1293 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); |
1294 | |
1295 | r8152b_disable_aldps(tp); |
1296 | r8152b_enter_oob(tp); |
1297 | r8152b_enable_aldps(tp); |
1298 | } |
1299 | |
1300 | static void set_carrier(struct r8152 *tp) |
1301 | { |
1302 | struct net_device *netdev = tp->netdev; |
1303 | u8 speed; |
1304 | |
1305 | speed = rtl8152_get_speed(tp); |
1306 | |
1307 | if (speed & LINK_STATUS) { |
1308 | if (!(tp->speed & LINK_STATUS)) { |
1309 | rtl8152_enable(tp); |
1310 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
1311 | netif_carrier_on(netdev); |
1312 | } |
1313 | } else { |
1314 | if (tp->speed & LINK_STATUS) { |
1315 | netif_carrier_off(netdev); |
1316 | rtl8152_disable(tp); |
1317 | } |
1318 | } |
1319 | tp->speed = speed; |
1320 | } |
1321 | |
1322 | static void rtl_work_func_t(struct work_struct *work) |
1323 | { |
1324 | struct r8152 *tp = container_of(work, struct r8152, schedule.work); |
1325 | |
1326 | if (!test_bit(WORK_ENABLE, &tp->flags)) |
1327 | goto out1; |
1328 | |
1329 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1330 | goto out1; |
1331 | |
1332 | set_carrier(tp); |
1333 | |
1334 | if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) |
1335 | _rtl8152_set_rx_mode(tp->netdev); |
1336 | |
1337 | schedule_delayed_work(&tp->schedule, HZ); |
1338 | |
1339 | out1: |
1340 | return; |
1341 | } |
1342 | |
1343 | static int rtl8152_open(struct net_device *netdev) |
1344 | { |
1345 | struct r8152 *tp = netdev_priv(netdev); |
1346 | int res = 0; |
1347 | |
1348 | tp->speed = rtl8152_get_speed(tp); |
1349 | if (tp->speed & LINK_STATUS) { |
1350 | res = rtl8152_enable(tp); |
1351 | if (res) { |
1352 | if (res == -ENODEV) |
1353 | netif_device_detach(tp->netdev); |
1354 | |
1355 | netif_err(tp, ifup, netdev, |
1356 | "rtl8152_open failed: %d\n", res); |
1357 | return res; |
1358 | } |
1359 | |
1360 | netif_carrier_on(netdev); |
1361 | } else { |
1362 | netif_stop_queue(netdev); |
1363 | netif_carrier_off(netdev); |
1364 | } |
1365 | |
1366 | rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL); |
1367 | netif_start_queue(netdev); |
1368 | set_bit(WORK_ENABLE, &tp->flags); |
1369 | schedule_delayed_work(&tp->schedule, 0); |
1370 | |
1371 | return res; |
1372 | } |
1373 | |
1374 | static int rtl8152_close(struct net_device *netdev) |
1375 | { |
1376 | struct r8152 *tp = netdev_priv(netdev); |
1377 | int res = 0; |
1378 | |
1379 | clear_bit(WORK_ENABLE, &tp->flags); |
1380 | cancel_delayed_work_sync(&tp->schedule); |
1381 | netif_stop_queue(netdev); |
1382 | rtl8152_disable(tp); |
1383 | |
1384 | return res; |
1385 | } |
1386 | |
1387 | static void rtl_clear_bp(struct r8152 *tp) |
1388 | { |
1389 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0); |
1390 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0); |
1391 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0); |
1392 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0); |
1393 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0); |
1394 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0); |
1395 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0); |
1396 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0); |
1397 | mdelay(3); |
1398 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0); |
1399 | ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0); |
1400 | } |
1401 | |
1402 | static void r8152b_enable_eee(struct r8152 *tp) |
1403 | { |
1404 | u32 ocp_data; |
1405 | |
1406 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); |
1407 | ocp_data |= EEE_RX_EN | EEE_TX_EN; |
1408 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); |
1409 | ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN | |
1410 | EEE_10_CAP | EEE_NWAY_EN | |
1411 | TX_QUIET_EN | RX_QUIET_EN | |
1412 | SDRISETIME | RG_RXLPI_MSK_HFDUP | |
1413 | SDFALLTIME); |
1414 | ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN | |
1415 | RG_LDVQUIET_EN | RG_CKRSEL | |
1416 | RG_EEEPRG_EN); |
1417 | ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH); |
1418 | ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR); |
1419 | ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR); |
1420 | ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR); |
1421 | ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA); |
1422 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); |
1423 | } |
1424 | |
1425 | static void r8152b_enable_fc(struct r8152 *tp) |
1426 | { |
1427 | u16 anar; |
1428 | |
1429 | anar = r8152_mdio_read(tp, MII_ADVERTISE); |
1430 | anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1431 | r8152_mdio_write(tp, MII_ADVERTISE, anar); |
1432 | } |
1433 | |
1434 | static void r8152b_hw_phy_cfg(struct r8152 *tp) |
1435 | { |
1436 | r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE); |
1437 | r8152b_disable_aldps(tp); |
1438 | } |
1439 | |
1440 | static void r8152b_init(struct r8152 *tp) |
1441 | { |
1442 | u32 ocp_data; |
1443 | int i; |
1444 | |
1445 | rtl_clear_bp(tp); |
1446 | |
1447 | if (tp->version == RTL_VER_01) { |
1448 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); |
1449 | ocp_data &= ~LED_MODE_MASK; |
1450 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); |
1451 | } |
1452 | |
1453 | r8152b_hw_phy_cfg(tp); |
1454 | |
1455 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); |
1456 | ocp_data &= ~POWER_CUT; |
1457 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); |
1458 | |
1459 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); |
1460 | ocp_data &= ~RWSUME_INDICATE; |
1461 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); |
1462 | |
1463 | r8152b_exit_oob(tp); |
1464 | |
1465 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); |
1466 | ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; |
1467 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); |
1468 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); |
1469 | ocp_data &= ~MCU_CLK_RATIO_MASK; |
1470 | ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; |
1471 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); |
1472 | ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | |
1473 | SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; |
1474 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); |
1475 | |
1476 | r8152b_enable_eee(tp); |
1477 | r8152b_enable_aldps(tp); |
1478 | r8152b_enable_fc(tp); |
1479 | |
1480 | r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE | |
1481 | BMCR_ANRESTART); |
1482 | for (i = 0; i < 100; i++) { |
1483 | udelay(100); |
1484 | if (!(r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET)) |
1485 | break; |
1486 | } |
1487 | |
1488 | /* disable rx aggregation */ |
1489 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
1490 | ocp_data |= RX_AGG_DISABLE; |
1491 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
1492 | } |
1493 | |
1494 | static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) |
1495 | { |
1496 | struct r8152 *tp = usb_get_intfdata(intf); |
1497 | |
1498 | netif_device_detach(tp->netdev); |
1499 | |
1500 | if (netif_running(tp->netdev)) { |
1501 | clear_bit(WORK_ENABLE, &tp->flags); |
1502 | cancel_delayed_work_sync(&tp->schedule); |
1503 | } |
1504 | |
1505 | rtl8152_down(tp); |
1506 | |
1507 | return 0; |
1508 | } |
1509 | |
1510 | static int rtl8152_resume(struct usb_interface *intf) |
1511 | { |
1512 | struct r8152 *tp = usb_get_intfdata(intf); |
1513 | |
1514 | r8152b_init(tp); |
1515 | netif_device_attach(tp->netdev); |
1516 | if (netif_running(tp->netdev)) { |
1517 | rtl8152_enable(tp); |
1518 | set_bit(WORK_ENABLE, &tp->flags); |
1519 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
1520 | schedule_delayed_work(&tp->schedule, 0); |
1521 | } |
1522 | |
1523 | return 0; |
1524 | } |
1525 | |
1526 | static void rtl8152_get_drvinfo(struct net_device *netdev, |
1527 | struct ethtool_drvinfo *info) |
1528 | { |
1529 | struct r8152 *tp = netdev_priv(netdev); |
1530 | |
1531 | strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN); |
1532 | strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN); |
1533 | usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); |
1534 | } |
1535 | |
1536 | static |
1537 | int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) |
1538 | { |
1539 | struct r8152 *tp = netdev_priv(netdev); |
1540 | |
1541 | if (!tp->mii.mdio_read) |
1542 | return -EOPNOTSUPP; |
1543 | |
1544 | return mii_ethtool_gset(&tp->mii, cmd); |
1545 | } |
1546 | |
1547 | static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1548 | { |
1549 | struct r8152 *tp = netdev_priv(dev); |
1550 | |
1551 | return rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); |
1552 | } |
1553 | |
1554 | static struct ethtool_ops ops = { |
1555 | .get_drvinfo = rtl8152_get_drvinfo, |
1556 | .get_settings = rtl8152_get_settings, |
1557 | .set_settings = rtl8152_set_settings, |
1558 | .get_link = ethtool_op_get_link, |
1559 | }; |
1560 | |
1561 | static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) |
1562 | { |
1563 | struct r8152 *tp = netdev_priv(netdev); |
1564 | struct mii_ioctl_data *data = if_mii(rq); |
1565 | int res = 0; |
1566 | |
1567 | switch (cmd) { |
1568 | case SIOCGMIIPHY: |
1569 | data->phy_id = R8152_PHY_ID; /* Internal PHY */ |
1570 | break; |
1571 | |
1572 | case SIOCGMIIREG: |
1573 | data->val_out = r8152_mdio_read(tp, data->reg_num); |
1574 | break; |
1575 | |
1576 | case SIOCSMIIREG: |
1577 | if (!capable(CAP_NET_ADMIN)) { |
1578 | res = -EPERM; |
1579 | break; |
1580 | } |
1581 | r8152_mdio_write(tp, data->reg_num, data->val_in); |
1582 | break; |
1583 | |
1584 | default: |
1585 | res = -EOPNOTSUPP; |
1586 | } |
1587 | |
1588 | return res; |
1589 | } |
1590 | |
1591 | static const struct net_device_ops rtl8152_netdev_ops = { |
1592 | .ndo_open = rtl8152_open, |
1593 | .ndo_stop = rtl8152_close, |
1594 | .ndo_do_ioctl = rtl8152_ioctl, |
1595 | .ndo_start_xmit = rtl8152_start_xmit, |
1596 | .ndo_tx_timeout = rtl8152_tx_timeout, |
1597 | .ndo_set_rx_mode = rtl8152_set_rx_mode, |
1598 | .ndo_set_mac_address = rtl8152_set_mac_address, |
1599 | |
1600 | .ndo_change_mtu = eth_change_mtu, |
1601 | .ndo_validate_addr = eth_validate_addr, |
1602 | }; |
1603 | |
1604 | static void r8152b_get_version(struct r8152 *tp) |
1605 | { |
1606 | u32 ocp_data; |
1607 | u16 version; |
1608 | |
1609 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); |
1610 | version = (u16)(ocp_data & VERSION_MASK); |
1611 | |
1612 | switch (version) { |
1613 | case 0x4c00: |
1614 | tp->version = RTL_VER_01; |
1615 | break; |
1616 | case 0x4c10: |
1617 | tp->version = RTL_VER_02; |
1618 | break; |
1619 | default: |
1620 | netif_info(tp, probe, tp->netdev, |
1621 | "Unknown version 0x%04x\n", version); |
1622 | break; |
1623 | } |
1624 | } |
1625 | |
1626 | static int rtl8152_probe(struct usb_interface *intf, |
1627 | const struct usb_device_id *id) |
1628 | { |
1629 | struct usb_device *udev = interface_to_usbdev(intf); |
1630 | struct r8152 *tp; |
1631 | struct net_device *netdev; |
1632 | |
1633 | if (udev->actconfig->desc.bConfigurationValue != 1) { |
1634 | usb_driver_set_configuration(udev, 1); |
1635 | return -ENODEV; |
1636 | } |
1637 | |
1638 | netdev = alloc_etherdev(sizeof(struct r8152)); |
1639 | if (!netdev) { |
1640 | dev_err(&intf->dev, "Out of memory"); |
1641 | return -ENOMEM; |
1642 | } |
1643 | |
1644 | tp = netdev_priv(netdev); |
1645 | tp->msg_enable = 0x7FFF; |
1646 | |
1647 | tasklet_init(&tp->tl, rx_fixup, (unsigned long)tp); |
1648 | INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); |
1649 | |
1650 | tp->udev = udev; |
1651 | tp->netdev = netdev; |
1652 | netdev->netdev_ops = &rtl8152_netdev_ops; |
1653 | netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; |
1654 | netdev->features &= ~NETIF_F_IP_CSUM; |
1655 | SET_ETHTOOL_OPS(netdev, &ops); |
1656 | tp->speed = 0; |
1657 | |
1658 | tp->mii.dev = netdev; |
1659 | tp->mii.mdio_read = read_mii_word; |
1660 | tp->mii.mdio_write = write_mii_word; |
1661 | tp->mii.phy_id_mask = 0x3f; |
1662 | tp->mii.reg_num_mask = 0x1f; |
1663 | tp->mii.phy_id = R8152_PHY_ID; |
1664 | tp->mii.supports_gmii = 0; |
1665 | |
1666 | r8152b_get_version(tp); |
1667 | r8152b_init(tp); |
1668 | set_ethernet_addr(tp); |
1669 | |
1670 | if (!alloc_all_urbs(tp)) { |
1671 | netif_err(tp, probe, netdev, "out of memory"); |
1672 | goto out; |
1673 | } |
1674 | |
1675 | tp->rx_skb = netdev_alloc_skb(netdev, |
1676 | RTL8152_RMS + sizeof(struct rx_desc)); |
1677 | if (!tp->rx_skb) |
1678 | goto out1; |
1679 | |
1680 | usb_set_intfdata(intf, tp); |
1681 | SET_NETDEV_DEV(netdev, &intf->dev); |
1682 | |
1683 | |
1684 | if (register_netdev(netdev) != 0) { |
1685 | netif_err(tp, probe, netdev, "couldn't register the device"); |
1686 | goto out2; |
1687 | } |
1688 | |
1689 | netif_info(tp, probe, netdev, "%s", DRIVER_VERSION); |
1690 | |
1691 | return 0; |
1692 | |
1693 | out2: |
1694 | usb_set_intfdata(intf, NULL); |
1695 | dev_kfree_skb(tp->rx_skb); |
1696 | out1: |
1697 | free_all_urbs(tp); |
1698 | out: |
1699 | free_netdev(netdev); |
1700 | return -EIO; |
1701 | } |
1702 | |
1703 | static void rtl8152_unload(struct r8152 *tp) |
1704 | { |
1705 | u32 ocp_data; |
1706 | |
1707 | if (tp->version != RTL_VER_01) { |
1708 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); |
1709 | ocp_data |= POWER_CUT; |
1710 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); |
1711 | } |
1712 | |
1713 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); |
1714 | ocp_data &= ~RWSUME_INDICATE; |
1715 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); |
1716 | } |
1717 | |
1718 | static void rtl8152_disconnect(struct usb_interface *intf) |
1719 | { |
1720 | struct r8152 *tp = usb_get_intfdata(intf); |
1721 | |
1722 | usb_set_intfdata(intf, NULL); |
1723 | if (tp) { |
1724 | set_bit(RTL8152_UNPLUG, &tp->flags); |
1725 | tasklet_kill(&tp->tl); |
1726 | unregister_netdev(tp->netdev); |
1727 | rtl8152_unload(tp); |
1728 | free_all_urbs(tp); |
1729 | if (tp->rx_skb) |
1730 | dev_kfree_skb(tp->rx_skb); |
1731 | free_netdev(tp->netdev); |
1732 | } |
1733 | } |
1734 | |
1735 | /* table of devices that work with this driver */ |
1736 | static struct usb_device_id rtl8152_table[] = { |
1737 | {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)}, |
1738 | {} |
1739 | }; |
1740 | |
1741 | MODULE_DEVICE_TABLE(usb, rtl8152_table); |
1742 | |
1743 | static struct usb_driver rtl8152_driver = { |
1744 | .name = MODULENAME, |
1745 | .probe = rtl8152_probe, |
1746 | .disconnect = rtl8152_disconnect, |
1747 | .id_table = rtl8152_table, |
1748 | .suspend = rtl8152_suspend, |
1749 | .resume = rtl8152_resume |
1750 | }; |
1751 | |
b4236daa |
1752 | module_usb_driver(rtl8152_driver); |
ac718b69 |
1753 | |
1754 | MODULE_AUTHOR(DRIVER_AUTHOR); |
1755 | MODULE_DESCRIPTION(DRIVER_DESC); |
1756 | MODULE_LICENSE("GPL"); |