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net/usb/r8152: enable interrupt transfer
[deliverable/linux.git] / drivers / net / usb / r8152.c
CommitLineData
ac718b69 1/*
2 * Copyright (c) 2013 Realtek Semiconductor Corp. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
10#include <linux/init.h>
11#include <linux/signal.h>
12#include <linux/slab.h>
13#include <linux/module.h>
ac718b69 14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/mii.h>
17#include <linux/ethtool.h>
18#include <linux/usb.h>
19#include <linux/crc32.h>
20#include <linux/if_vlan.h>
21#include <linux/uaccess.h>
ebc2ec48 22#include <linux/list.h>
5bd23881 23#include <linux/ip.h>
24#include <linux/ipv6.h>
ac718b69 25
26/* Version Information */
ebc2ec48 27#define DRIVER_VERSION "v1.01.0 (2013/08/12)"
ac718b69 28#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
29#define DRIVER_DESC "Realtek RTL8152 Based USB 2.0 Ethernet Adapters"
30#define MODULENAME "r8152"
31
32#define R8152_PHY_ID 32
33
34#define PLA_IDR 0xc000
35#define PLA_RCR 0xc010
36#define PLA_RMS 0xc016
37#define PLA_RXFIFO_CTRL0 0xc0a0
38#define PLA_RXFIFO_CTRL1 0xc0a4
39#define PLA_RXFIFO_CTRL2 0xc0a8
40#define PLA_FMC 0xc0b4
41#define PLA_CFG_WOL 0xc0b6
42#define PLA_MAR 0xcd00
43#define PAL_BDC_CR 0xd1a0
44#define PLA_LEDSEL 0xdd90
45#define PLA_LED_FEATURE 0xdd92
46#define PLA_PHYAR 0xde00
47#define PLA_GPHY_INTR_IMR 0xe022
48#define PLA_EEE_CR 0xe040
49#define PLA_EEEP_CR 0xe080
50#define PLA_MAC_PWR_CTRL 0xe0c0
51#define PLA_TCR0 0xe610
52#define PLA_TCR1 0xe612
53#define PLA_TXFIFO_CTRL 0xe618
54#define PLA_RSTTELLY 0xe800
55#define PLA_CR 0xe813
56#define PLA_CRWECR 0xe81c
57#define PLA_CONFIG5 0xe822
58#define PLA_PHY_PWR 0xe84c
59#define PLA_OOB_CTRL 0xe84f
60#define PLA_CPCR 0xe854
61#define PLA_MISC_0 0xe858
62#define PLA_MISC_1 0xe85a
63#define PLA_OCP_GPHY_BASE 0xe86c
64#define PLA_TELLYCNT 0xe890
65#define PLA_SFF_STS_7 0xe8de
66#define PLA_PHYSTATUS 0xe908
67#define PLA_BP_BA 0xfc26
68#define PLA_BP_0 0xfc28
69#define PLA_BP_1 0xfc2a
70#define PLA_BP_2 0xfc2c
71#define PLA_BP_3 0xfc2e
72#define PLA_BP_4 0xfc30
73#define PLA_BP_5 0xfc32
74#define PLA_BP_6 0xfc34
75#define PLA_BP_7 0xfc36
76
77#define USB_DEV_STAT 0xb808
78#define USB_USB_CTRL 0xd406
79#define USB_PHY_CTRL 0xd408
80#define USB_TX_AGG 0xd40a
81#define USB_RX_BUF_TH 0xd40c
82#define USB_USB_TIMER 0xd428
83#define USB_PM_CTRL_STATUS 0xd432
84#define USB_TX_DMA 0xd434
85#define USB_UPS_CTRL 0xd800
86#define USB_BP_BA 0xfc26
87#define USB_BP_0 0xfc28
88#define USB_BP_1 0xfc2a
89#define USB_BP_2 0xfc2c
90#define USB_BP_3 0xfc2e
91#define USB_BP_4 0xfc30
92#define USB_BP_5 0xfc32
93#define USB_BP_6 0xfc34
94#define USB_BP_7 0xfc36
95
96/* OCP Registers */
97#define OCP_ALDPS_CONFIG 0x2010
98#define OCP_EEE_CONFIG1 0x2080
99#define OCP_EEE_CONFIG2 0x2092
100#define OCP_EEE_CONFIG3 0x2094
101#define OCP_EEE_AR 0xa41a
102#define OCP_EEE_DATA 0xa41c
103
104/* PLA_RCR */
105#define RCR_AAP 0x00000001
106#define RCR_APM 0x00000002
107#define RCR_AM 0x00000004
108#define RCR_AB 0x00000008
109#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
110
111/* PLA_RXFIFO_CTRL0 */
112#define RXFIFO_THR1_NORMAL 0x00080002
113#define RXFIFO_THR1_OOB 0x01800003
114
115/* PLA_RXFIFO_CTRL1 */
116#define RXFIFO_THR2_FULL 0x00000060
117#define RXFIFO_THR2_HIGH 0x00000038
118#define RXFIFO_THR2_OOB 0x0000004a
119
120/* PLA_RXFIFO_CTRL2 */
121#define RXFIFO_THR3_FULL 0x00000078
122#define RXFIFO_THR3_HIGH 0x00000048
123#define RXFIFO_THR3_OOB 0x0000005a
124
125/* PLA_TXFIFO_CTRL */
126#define TXFIFO_THR_NORMAL 0x00400008
127
128/* PLA_FMC */
129#define FMC_FCR_MCU_EN 0x0001
130
131/* PLA_EEEP_CR */
132#define EEEP_CR_EEEP_TX 0x0002
133
134/* PLA_TCR0 */
135#define TCR0_TX_EMPTY 0x0800
136#define TCR0_AUTO_FIFO 0x0080
137
138/* PLA_TCR1 */
139#define VERSION_MASK 0x7cf0
140
141/* PLA_CR */
142#define CR_RST 0x10
143#define CR_RE 0x08
144#define CR_TE 0x04
145
146/* PLA_CRWECR */
147#define CRWECR_NORAML 0x00
148#define CRWECR_CONFIG 0xc0
149
150/* PLA_OOB_CTRL */
151#define NOW_IS_OOB 0x80
152#define TXFIFO_EMPTY 0x20
153#define RXFIFO_EMPTY 0x10
154#define LINK_LIST_READY 0x02
155#define DIS_MCU_CLROOB 0x01
156#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
157
158/* PLA_MISC_1 */
159#define RXDY_GATED_EN 0x0008
160
161/* PLA_SFF_STS_7 */
162#define RE_INIT_LL 0x8000
163#define MCU_BORW_EN 0x4000
164
165/* PLA_CPCR */
166#define CPCR_RX_VLAN 0x0040
167
168/* PLA_CFG_WOL */
169#define MAGIC_EN 0x0001
170
171/* PAL_BDC_CR */
172#define ALDPS_PROXY_MODE 0x0001
173
174/* PLA_CONFIG5 */
175#define LAN_WAKE_EN 0x0002
176
177/* PLA_LED_FEATURE */
178#define LED_MODE_MASK 0x0700
179
180/* PLA_PHY_PWR */
181#define TX_10M_IDLE_EN 0x0080
182#define PFM_PWM_SWITCH 0x0040
183
184/* PLA_MAC_PWR_CTRL */
185#define D3_CLK_GATED_EN 0x00004000
186#define MCU_CLK_RATIO 0x07010f07
187#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
188
189/* PLA_GPHY_INTR_IMR */
190#define GPHY_STS_MSK 0x0001
191#define SPEED_DOWN_MSK 0x0002
192#define SPDWN_RXDV_MSK 0x0004
193#define SPDWN_LINKCHG_MSK 0x0008
194
195/* PLA_PHYAR */
196#define PHYAR_FLAG 0x80000000
197
198/* PLA_EEE_CR */
199#define EEE_RX_EN 0x0001
200#define EEE_TX_EN 0x0002
201
202/* USB_DEV_STAT */
203#define STAT_SPEED_MASK 0x0006
204#define STAT_SPEED_HIGH 0x0000
205#define STAT_SPEED_FULL 0x0001
206
207/* USB_TX_AGG */
208#define TX_AGG_MAX_THRESHOLD 0x03
209
210/* USB_RX_BUF_TH */
211#define RX_BUF_THR 0x7a120180
212
213/* USB_TX_DMA */
214#define TEST_MODE_DISABLE 0x00000001
215#define TX_SIZE_ADJUST1 0x00000100
216
217/* USB_UPS_CTRL */
218#define POWER_CUT 0x0100
219
220/* USB_PM_CTRL_STATUS */
221#define RWSUME_INDICATE 0x0001
222
223/* USB_USB_CTRL */
224#define RX_AGG_DISABLE 0x0010
225
226/* OCP_ALDPS_CONFIG */
227#define ENPWRSAVE 0x8000
228#define ENPDNPS 0x0200
229#define LINKENA 0x0100
230#define DIS_SDSAVE 0x0010
231
232/* OCP_EEE_CONFIG1 */
233#define RG_TXLPI_MSK_HFDUP 0x8000
234#define RG_MATCLR_EN 0x4000
235#define EEE_10_CAP 0x2000
236#define EEE_NWAY_EN 0x1000
237#define TX_QUIET_EN 0x0200
238#define RX_QUIET_EN 0x0100
239#define SDRISETIME 0x0010 /* bit 4 ~ 6 */
240#define RG_RXLPI_MSK_HFDUP 0x0008
241#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
242
243/* OCP_EEE_CONFIG2 */
244#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
245#define RG_DACQUIET_EN 0x0400
246#define RG_LDVQUIET_EN 0x0200
247#define RG_CKRSEL 0x0020
248#define RG_EEEPRG_EN 0x0010
249
250/* OCP_EEE_CONFIG3 */
251#define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */
252#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
253#define MSK_PH 0x0006 /* bit 0 ~ 3 */
254
255/* OCP_EEE_AR */
256/* bit[15:14] function */
257#define FUN_ADDR 0x0000
258#define FUN_DATA 0x4000
259/* bit[4:0] device addr */
260#define DEVICE_ADDR 0x0007
261
262/* OCP_EEE_DATA */
263#define EEE_ADDR 0x003C
264#define EEE_DATA 0x0002
265
266enum rtl_register_content {
267 _100bps = 0x08,
268 _10bps = 0x04,
269 LINK_STATUS = 0x02,
270 FULL_DUP = 0x01,
271};
272
ebc2ec48 273#define RTL8152_MAX_TX 10
274#define RTL8152_MAX_RX 10
40a82917 275#define INTBUFSIZE 2
276
277#define INTR_LINK 0x0004
ebc2ec48 278
ac718b69 279#define RTL8152_REQT_READ 0xc0
280#define RTL8152_REQT_WRITE 0x40
281#define RTL8152_REQ_GET_REGS 0x05
282#define RTL8152_REQ_SET_REGS 0x05
283
284#define BYTE_EN_DWORD 0xff
285#define BYTE_EN_WORD 0x33
286#define BYTE_EN_BYTE 0x11
287#define BYTE_EN_SIX_BYTES 0x3f
288#define BYTE_EN_START_MASK 0x0f
289#define BYTE_EN_END_MASK 0xf0
290
291#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
292#define RTL8152_TX_TIMEOUT (HZ)
293
294/* rtl8152 flags */
295enum rtl8152_flags {
296 RTL8152_UNPLUG = 0,
ac718b69 297 RTL8152_SET_RX_MODE,
40a82917 298 WORK_ENABLE,
299 RTL8152_LINK_CHG,
ac718b69 300};
301
302/* Define these values to match your device */
303#define VENDOR_ID_REALTEK 0x0bda
304#define PRODUCT_ID_RTL8152 0x8152
305
306#define MCU_TYPE_PLA 0x0100
307#define MCU_TYPE_USB 0x0000
308
309struct rx_desc {
310 u32 opts1;
311#define RX_LEN_MASK 0x7fff
312 u32 opts2;
313 u32 opts3;
314 u32 opts4;
315 u32 opts5;
316 u32 opts6;
317};
318
319struct tx_desc {
320 u32 opts1;
321#define TX_FS (1 << 31) /* First segment of a packet */
322#define TX_LS (1 << 30) /* Final segment of a packet */
5bd23881 323#define TX_LEN_MASK 0x3ffff
324
ac718b69 325 u32 opts2;
5bd23881 326#define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
327#define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
328#define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
329#define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
ac718b69 330};
331
ebc2ec48 332struct rx_agg {
333 struct list_head list;
334 struct urb *urb;
335 void *context;
336 void *buffer;
337 void *head;
338};
339
340struct tx_agg {
341 struct list_head list;
342 struct urb *urb;
343 void *context;
344 void *buffer;
345 void *head;
346 u32 skb_num;
347 u32 skb_len;
348};
349
ac718b69 350struct r8152 {
351 unsigned long flags;
352 struct usb_device *udev;
353 struct tasklet_struct tl;
40a82917 354 struct usb_interface *intf;
ac718b69 355 struct net_device *netdev;
40a82917 356 struct urb *intr_urb;
ebc2ec48 357 struct tx_agg tx_info[RTL8152_MAX_TX];
358 struct rx_agg rx_info[RTL8152_MAX_RX];
359 struct list_head rx_done, tx_free;
360 struct sk_buff_head tx_queue;
361 spinlock_t rx_lock, tx_lock;
ac718b69 362 struct delayed_work schedule;
363 struct mii_if_info mii;
40a82917 364 int intr_interval;
ac718b69 365 u32 msg_enable;
366 u16 ocp_base;
40a82917 367 u8 *intr_buff;
ac718b69 368 u8 version;
369 u8 speed;
370};
371
372enum rtl_version {
373 RTL_VER_UNKNOWN = 0,
374 RTL_VER_01,
375 RTL_VER_02
376};
377
378/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
379 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
380 */
381static const int multicast_filter_limit = 32;
ebc2ec48 382static unsigned int rx_buf_sz = 16384;
ac718b69 383
384static
385int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
386{
31787f53 387 int ret;
388 void *tmp;
389
390 tmp = kmalloc(size, GFP_KERNEL);
391 if (!tmp)
392 return -ENOMEM;
393
394 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
ac718b69 395 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
31787f53 396 value, index, tmp, size, 500);
397
398 memcpy(data, tmp, size);
399 kfree(tmp);
400
401 return ret;
ac718b69 402}
403
404static
405int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
406{
31787f53 407 int ret;
408 void *tmp;
409
410 tmp = kmalloc(size, GFP_KERNEL);
411 if (!tmp)
412 return -ENOMEM;
413
414 memcpy(tmp, data, size);
415
416 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
ac718b69 417 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
31787f53 418 value, index, tmp, size, 500);
419
420 kfree(tmp);
421 return ret;
ac718b69 422}
423
424static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
425 void *data, u16 type)
426{
427 u16 limit = 64;
428 int ret = 0;
429
430 if (test_bit(RTL8152_UNPLUG, &tp->flags))
431 return -ENODEV;
432
433 /* both size and indix must be 4 bytes align */
434 if ((size & 3) || !size || (index & 3) || !data)
435 return -EPERM;
436
437 if ((u32)index + (u32)size > 0xffff)
438 return -EPERM;
439
440 while (size) {
441 if (size > limit) {
442 ret = get_registers(tp, index, type, limit, data);
443 if (ret < 0)
444 break;
445
446 index += limit;
447 data += limit;
448 size -= limit;
449 } else {
450 ret = get_registers(tp, index, type, size, data);
451 if (ret < 0)
452 break;
453
454 index += size;
455 data += size;
456 size = 0;
457 break;
458 }
459 }
460
461 return ret;
462}
463
464static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
465 u16 size, void *data, u16 type)
466{
467 int ret;
468 u16 byteen_start, byteen_end, byen;
469 u16 limit = 512;
470
471 if (test_bit(RTL8152_UNPLUG, &tp->flags))
472 return -ENODEV;
473
474 /* both size and indix must be 4 bytes align */
475 if ((size & 3) || !size || (index & 3) || !data)
476 return -EPERM;
477
478 if ((u32)index + (u32)size > 0xffff)
479 return -EPERM;
480
481 byteen_start = byteen & BYTE_EN_START_MASK;
482 byteen_end = byteen & BYTE_EN_END_MASK;
483
484 byen = byteen_start | (byteen_start << 4);
485 ret = set_registers(tp, index, type | byen, 4, data);
486 if (ret < 0)
487 goto error1;
488
489 index += 4;
490 data += 4;
491 size -= 4;
492
493 if (size) {
494 size -= 4;
495
496 while (size) {
497 if (size > limit) {
498 ret = set_registers(tp, index,
499 type | BYTE_EN_DWORD,
500 limit, data);
501 if (ret < 0)
502 goto error1;
503
504 index += limit;
505 data += limit;
506 size -= limit;
507 } else {
508 ret = set_registers(tp, index,
509 type | BYTE_EN_DWORD,
510 size, data);
511 if (ret < 0)
512 goto error1;
513
514 index += size;
515 data += size;
516 size = 0;
517 break;
518 }
519 }
520
521 byen = byteen_end | (byteen_end >> 4);
522 ret = set_registers(tp, index, type | byen, 4, data);
523 if (ret < 0)
524 goto error1;
525 }
526
527error1:
528 return ret;
529}
530
531static inline
532int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
533{
534 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
535}
536
537static inline
538int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
539{
540 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
541}
542
543static inline
544int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
545{
546 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
547}
548
549static inline
550int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
551{
552 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
553}
554
555static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
556{
c8826de8 557 __le32 data;
ac718b69 558
c8826de8 559 generic_ocp_read(tp, index, sizeof(data), &data, type);
ac718b69 560
561 return __le32_to_cpu(data);
562}
563
564static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
565{
c8826de8 566 __le32 tmp = __cpu_to_le32(data);
567
568 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
ac718b69 569}
570
571static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
572{
573 u32 data;
c8826de8 574 __le32 tmp;
ac718b69 575 u8 shift = index & 2;
576
577 index &= ~3;
578
c8826de8 579 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 580
c8826de8 581 data = __le32_to_cpu(tmp);
ac718b69 582 data >>= (shift * 8);
583 data &= 0xffff;
584
585 return (u16)data;
586}
587
588static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
589{
c8826de8 590 u32 mask = 0xffff;
591 __le32 tmp;
ac718b69 592 u16 byen = BYTE_EN_WORD;
593 u8 shift = index & 2;
594
595 data &= mask;
596
597 if (index & 2) {
598 byen <<= shift;
599 mask <<= (shift * 8);
600 data <<= (shift * 8);
601 index &= ~3;
602 }
603
c8826de8 604 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 605
c8826de8 606 data |= __le32_to_cpu(tmp) & ~mask;
607 tmp = __cpu_to_le32(data);
ac718b69 608
c8826de8 609 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 610}
611
612static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
613{
614 u32 data;
c8826de8 615 __le32 tmp;
ac718b69 616 u8 shift = index & 3;
617
618 index &= ~3;
619
c8826de8 620 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 621
c8826de8 622 data = __le32_to_cpu(tmp);
ac718b69 623 data >>= (shift * 8);
624 data &= 0xff;
625
626 return (u8)data;
627}
628
629static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
630{
c8826de8 631 u32 mask = 0xff;
632 __le32 tmp;
ac718b69 633 u16 byen = BYTE_EN_BYTE;
634 u8 shift = index & 3;
635
636 data &= mask;
637
638 if (index & 3) {
639 byen <<= shift;
640 mask <<= (shift * 8);
641 data <<= (shift * 8);
642 index &= ~3;
643 }
644
c8826de8 645 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 646
c8826de8 647 data |= __le32_to_cpu(tmp) & ~mask;
648 tmp = __cpu_to_le32(data);
ac718b69 649
c8826de8 650 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 651}
652
653static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
654{
655 u32 ocp_data;
656 int i;
657
658 ocp_data = PHYAR_FLAG | ((reg_addr & 0x1f) << 16) |
659 (value & 0xffff);
660
661 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data);
662
663 for (i = 20; i > 0; i--) {
664 udelay(25);
665 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR);
666 if (!(ocp_data & PHYAR_FLAG))
667 break;
668 }
669 udelay(20);
670}
671
672static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
673{
674 u32 ocp_data;
675 int i;
676
677 ocp_data = (reg_addr & 0x1f) << 16;
678 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data);
679
680 for (i = 20; i > 0; i--) {
681 udelay(25);
682 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR);
683 if (ocp_data & PHYAR_FLAG)
684 break;
685 }
686 udelay(20);
687
688 if (!(ocp_data & PHYAR_FLAG))
689 return -EAGAIN;
690
691 return (u16)(ocp_data & 0xffff);
692}
693
694static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
695{
696 struct r8152 *tp = netdev_priv(netdev);
697
698 if (phy_id != R8152_PHY_ID)
699 return -EINVAL;
700
701 return r8152_mdio_read(tp, reg);
702}
703
704static
705void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
706{
707 struct r8152 *tp = netdev_priv(netdev);
708
709 if (phy_id != R8152_PHY_ID)
710 return;
711
712 r8152_mdio_write(tp, reg, val);
713}
714
715static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
716{
717 u16 ocp_base, ocp_index;
718
719 ocp_base = addr & 0xf000;
720 if (ocp_base != tp->ocp_base) {
721 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
722 tp->ocp_base = ocp_base;
723 }
724
725 ocp_index = (addr & 0x0fff) | 0xb000;
726 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
727}
728
ebc2ec48 729static
730int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
731
ac718b69 732static inline void set_ethernet_addr(struct r8152 *tp)
733{
734 struct net_device *dev = tp->netdev;
31787f53 735 u8 node_id[8] = {0};
ac718b69 736
31787f53 737 if (pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id) < 0)
ac718b69 738 netif_notice(tp, probe, dev, "inet addr fail\n");
739 else {
740 memcpy(dev->dev_addr, node_id, dev->addr_len);
741 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
742 }
ac718b69 743}
744
745static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
746{
747 struct r8152 *tp = netdev_priv(netdev);
748 struct sockaddr *addr = p;
749
750 if (!is_valid_ether_addr(addr->sa_data))
751 return -EADDRNOTAVAIL;
752
753 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
754
755 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
756 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
757 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
758
759 return 0;
760}
761
ac718b69 762static struct net_device_stats *rtl8152_get_stats(struct net_device *dev)
763{
764 return &dev->stats;
765}
766
767static void read_bulk_callback(struct urb *urb)
768{
ac718b69 769 struct net_device *netdev;
ebc2ec48 770 unsigned long lockflags;
ac718b69 771 int status = urb->status;
ebc2ec48 772 struct rx_agg *agg;
773 struct r8152 *tp;
ac718b69 774 int result;
ac718b69 775
ebc2ec48 776 agg = urb->context;
777 if (!agg)
778 return;
779
780 tp = agg->context;
ac718b69 781 if (!tp)
782 return;
ebc2ec48 783
ac718b69 784 if (test_bit(RTL8152_UNPLUG, &tp->flags))
785 return;
ebc2ec48 786
787 if (!test_bit(WORK_ENABLE, &tp->flags))
788 return;
789
ac718b69 790 netdev = tp->netdev;
ebc2ec48 791 if (!netif_carrier_ok(netdev))
ac718b69 792 return;
793
ac718b69 794 switch (status) {
795 case 0:
ebc2ec48 796 if (urb->actual_length < ETH_ZLEN)
797 break;
798
799 spin_lock_irqsave(&tp->rx_lock, lockflags);
800 list_add_tail(&agg->list, &tp->rx_done);
801 spin_unlock_irqrestore(&tp->rx_lock, lockflags);
802 tasklet_schedule(&tp->tl);
803 return;
ac718b69 804 case -ESHUTDOWN:
805 set_bit(RTL8152_UNPLUG, &tp->flags);
806 netif_device_detach(tp->netdev);
ebc2ec48 807 return;
ac718b69 808 case -ENOENT:
809 return; /* the urb is in unlink state */
810 case -ETIME:
811 pr_warn_ratelimited("may be reset is needed?..\n");
ebc2ec48 812 break;
ac718b69 813 default:
814 pr_warn_ratelimited("Rx status %d\n", status);
ebc2ec48 815 break;
ac718b69 816 }
817
ebc2ec48 818 result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
ac718b69 819 if (result == -ENODEV) {
820 netif_device_detach(tp->netdev);
821 } else if (result) {
ebc2ec48 822 spin_lock_irqsave(&tp->rx_lock, lockflags);
823 list_add_tail(&agg->list, &tp->rx_done);
824 spin_unlock_irqrestore(&tp->rx_lock, lockflags);
825 tasklet_schedule(&tp->tl);
ac718b69 826 }
ac718b69 827}
828
ebc2ec48 829static void write_bulk_callback(struct urb *urb)
ac718b69 830{
ebc2ec48 831 struct net_device_stats *stats;
832 unsigned long lockflags;
833 struct tx_agg *agg;
ac718b69 834 struct r8152 *tp;
ebc2ec48 835 int status = urb->status;
ac718b69 836
ebc2ec48 837 agg = urb->context;
838 if (!agg)
ac718b69 839 return;
840
ebc2ec48 841 tp = agg->context;
842 if (!tp)
843 return;
844
845 stats = rtl8152_get_stats(tp->netdev);
846 if (status) {
847 pr_warn_ratelimited("Tx status %d\n", status);
848 stats->tx_errors += agg->skb_num;
ac718b69 849 } else {
ebc2ec48 850 stats->tx_packets += agg->skb_num;
851 stats->tx_bytes += agg->skb_len;
ac718b69 852 }
853
ebc2ec48 854 spin_lock_irqsave(&tp->tx_lock, lockflags);
855 list_add_tail(&agg->list, &tp->tx_free);
856 spin_unlock_irqrestore(&tp->tx_lock, lockflags);
857
858 if (!netif_carrier_ok(tp->netdev))
859 return;
860
861 if (!test_bit(WORK_ENABLE, &tp->flags))
862 return;
863
864 if (test_bit(RTL8152_UNPLUG, &tp->flags))
865 return;
866
867 if (!skb_queue_empty(&tp->tx_queue))
868 tasklet_schedule(&tp->tl);
ac718b69 869}
870
40a82917 871static void intr_callback(struct urb *urb)
872{
873 struct r8152 *tp;
874 __u16 *d;
875 int status = urb->status;
876 int res;
877
878 tp = urb->context;
879 if (!tp)
880 return;
881
882 if (!test_bit(WORK_ENABLE, &tp->flags))
883 return;
884
885 if (test_bit(RTL8152_UNPLUG, &tp->flags))
886 return;
887
888 switch (status) {
889 case 0: /* success */
890 break;
891 case -ECONNRESET: /* unlink */
892 case -ESHUTDOWN:
893 netif_device_detach(tp->netdev);
894 case -ENOENT:
895 return;
896 case -EOVERFLOW:
897 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
898 goto resubmit;
899 /* -EPIPE: should clear the halt */
900 default:
901 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
902 goto resubmit;
903 }
904
905 d = urb->transfer_buffer;
906 if (INTR_LINK & __le16_to_cpu(d[0])) {
907 if (!(tp->speed & LINK_STATUS)) {
908 set_bit(RTL8152_LINK_CHG, &tp->flags);
909 schedule_delayed_work(&tp->schedule, 0);
910 }
911 } else {
912 if (tp->speed & LINK_STATUS) {
913 set_bit(RTL8152_LINK_CHG, &tp->flags);
914 schedule_delayed_work(&tp->schedule, 0);
915 }
916 }
917
918resubmit:
919 res = usb_submit_urb(urb, GFP_ATOMIC);
920 if (res == -ENODEV)
921 netif_device_detach(tp->netdev);
922 else if (res)
923 netif_err(tp, intr, tp->netdev,
924 "can't resubmit intr, status %d\n", res);
925}
926
ebc2ec48 927static inline void *rx_agg_align(void *data)
928{
929 return (void *)ALIGN((uintptr_t)data, 8);
930}
931
932static inline void *tx_agg_align(void *data)
933{
934 return (void *)ALIGN((uintptr_t)data, 4);
935}
936
937static void free_all_mem(struct r8152 *tp)
938{
939 int i;
940
941 for (i = 0; i < RTL8152_MAX_RX; i++) {
942 if (tp->rx_info[i].urb) {
943 usb_free_urb(tp->rx_info[i].urb);
944 tp->rx_info[i].urb = NULL;
945 }
946
947 if (tp->rx_info[i].buffer) {
948 kfree(tp->rx_info[i].buffer);
949 tp->rx_info[i].buffer = NULL;
950 tp->rx_info[i].head = NULL;
951 }
952 }
953
954 for (i = 0; i < RTL8152_MAX_TX; i++) {
955 if (tp->tx_info[i].urb) {
956 usb_free_urb(tp->tx_info[i].urb);
957 tp->tx_info[i].urb = NULL;
958 }
959
960 if (tp->tx_info[i].buffer) {
961 kfree(tp->tx_info[i].buffer);
962 tp->tx_info[i].buffer = NULL;
963 tp->tx_info[i].head = NULL;
964 }
965 }
40a82917 966
967 if (tp->intr_urb) {
968 usb_free_urb(tp->intr_urb);
969 tp->intr_urb = NULL;
970 }
971
972 if (tp->intr_buff) {
973 kfree(tp->intr_buff);
974 tp->intr_buff = NULL;
975 }
ebc2ec48 976}
977
978static int alloc_all_mem(struct r8152 *tp)
979{
980 struct net_device *netdev = tp->netdev;
40a82917 981 struct usb_interface *intf = tp->intf;
982 struct usb_host_interface *alt = intf->cur_altsetting;
983 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
ebc2ec48 984 struct urb *urb;
985 int node, i;
986 u8 *buf;
987
988 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
989
990 spin_lock_init(&tp->rx_lock);
991 spin_lock_init(&tp->tx_lock);
992 INIT_LIST_HEAD(&tp->rx_done);
993 INIT_LIST_HEAD(&tp->tx_free);
994 skb_queue_head_init(&tp->tx_queue);
995
996 for (i = 0; i < RTL8152_MAX_RX; i++) {
997 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
998 if (!buf)
999 goto err1;
1000
1001 if (buf != rx_agg_align(buf)) {
1002 kfree(buf);
1003 buf = kmalloc_node(rx_buf_sz + 8, GFP_KERNEL, node);
1004 if (!buf)
1005 goto err1;
1006 }
1007
1008 urb = usb_alloc_urb(0, GFP_KERNEL);
1009 if (!urb) {
1010 kfree(buf);
1011 goto err1;
1012 }
1013
1014 INIT_LIST_HEAD(&tp->rx_info[i].list);
1015 tp->rx_info[i].context = tp;
1016 tp->rx_info[i].urb = urb;
1017 tp->rx_info[i].buffer = buf;
1018 tp->rx_info[i].head = rx_agg_align(buf);
1019 }
1020
1021 for (i = 0; i < RTL8152_MAX_TX; i++) {
1022 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1023 if (!buf)
1024 goto err1;
1025
1026 if (buf != tx_agg_align(buf)) {
1027 kfree(buf);
1028 buf = kmalloc_node(rx_buf_sz + 4, GFP_KERNEL, node);
1029 if (!buf)
1030 goto err1;
1031 }
1032
1033 urb = usb_alloc_urb(0, GFP_KERNEL);
1034 if (!urb) {
1035 kfree(buf);
1036 goto err1;
1037 }
1038
1039 INIT_LIST_HEAD(&tp->tx_info[i].list);
1040 tp->tx_info[i].context = tp;
1041 tp->tx_info[i].urb = urb;
1042 tp->tx_info[i].buffer = buf;
1043 tp->tx_info[i].head = tx_agg_align(buf);
1044
1045 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1046 }
1047
40a82917 1048 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1049 if (!tp->intr_urb)
1050 goto err1;
1051
1052 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1053 if (!tp->intr_buff)
1054 goto err1;
1055
1056 tp->intr_interval = (int)ep_intr->desc.bInterval;
1057 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1058 tp->intr_buff, INTBUFSIZE, intr_callback,
1059 tp, tp->intr_interval);
1060
ebc2ec48 1061 return 0;
1062
1063err1:
1064 free_all_mem(tp);
1065 return -ENOMEM;
1066}
1067
5bd23881 1068static void
1069r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, struct sk_buff *skb)
1070{
1071 memset(desc, 0, sizeof(*desc));
1072
1073 desc->opts1 = cpu_to_le32((skb->len & TX_LEN_MASK) | TX_FS | TX_LS);
1074
1075 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1076 __be16 protocol;
1077 u8 ip_protocol;
1078 u32 opts2 = 0;
1079
1080 if (skb->protocol == htons(ETH_P_8021Q))
1081 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1082 else
1083 protocol = skb->protocol;
1084
1085 switch (protocol) {
1086 case htons(ETH_P_IP):
1087 opts2 |= IPV4_CS;
1088 ip_protocol = ip_hdr(skb)->protocol;
1089 break;
1090
1091 case htons(ETH_P_IPV6):
1092 opts2 |= IPV6_CS;
1093 ip_protocol = ipv6_hdr(skb)->nexthdr;
1094 break;
1095
1096 default:
1097 ip_protocol = IPPROTO_RAW;
1098 break;
1099 }
1100
1101 if (ip_protocol == IPPROTO_TCP) {
1102 opts2 |= TCP_CS;
1103 opts2 |= (skb_transport_offset(skb) & 0x7fff) << 17;
1104 } else if (ip_protocol == IPPROTO_UDP) {
1105 opts2 |= UDP_CS;
1106 } else {
1107 WARN_ON_ONCE(1);
1108 }
1109
1110 desc->opts2 = cpu_to_le32(opts2);
1111 }
1112}
1113
ebc2ec48 1114static void rx_bottom(struct r8152 *tp)
1115{
1116 struct net_device_stats *stats;
1117 struct net_device *netdev;
1118 struct rx_agg *agg;
1119 struct rx_desc *rx_desc;
1120 unsigned long lockflags;
1121 struct list_head *cursor, *next;
1122 struct sk_buff *skb;
1123 struct urb *urb;
1124 unsigned pkt_len;
1125 int len_used;
1126 u8 *rx_data;
1127 int ret;
1128
1129 netdev = tp->netdev;
1130
1131 stats = rtl8152_get_stats(netdev);
1132
1133 spin_lock_irqsave(&tp->rx_lock, lockflags);
1134 list_for_each_safe(cursor, next, &tp->rx_done) {
1135 list_del_init(cursor);
1136 spin_unlock_irqrestore(&tp->rx_lock, lockflags);
1137
1138 agg = list_entry(cursor, struct rx_agg, list);
1139 urb = agg->urb;
1140 if (urb->actual_length < ETH_ZLEN) {
1141 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1142 spin_lock_irqsave(&tp->rx_lock, lockflags);
1143 if (ret && ret != -ENODEV) {
1144 list_add_tail(&agg->list, next);
1145 tasklet_schedule(&tp->tl);
1146 }
1147 continue;
1148 }
1149
1150 len_used = 0;
1151 rx_desc = agg->head;
1152 rx_data = agg->head;
1153 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1154 len_used += sizeof(struct rx_desc) + pkt_len;
1155
1156 while (urb->actual_length >= len_used) {
1157 if (pkt_len < ETH_ZLEN)
1158 break;
1159
1160 pkt_len -= 4; /* CRC */
1161 rx_data += sizeof(struct rx_desc);
1162
1163 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1164 if (!skb) {
1165 stats->rx_dropped++;
1166 break;
1167 }
1168 memcpy(skb->data, rx_data, pkt_len);
1169 skb_put(skb, pkt_len);
1170 skb->protocol = eth_type_trans(skb, netdev);
1171 netif_rx(skb);
1172 stats->rx_packets++;
1173 stats->rx_bytes += pkt_len;
1174
1175 rx_data = rx_agg_align(rx_data + pkt_len + 4);
1176 rx_desc = (struct rx_desc *)rx_data;
1177 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1178 len_used = (int)(rx_data - (u8 *)agg->head);
1179 len_used += sizeof(struct rx_desc) + pkt_len;
1180 }
1181
1182 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1183 spin_lock_irqsave(&tp->rx_lock, lockflags);
1184 if (ret && ret != -ENODEV) {
1185 list_add_tail(&agg->list, next);
1186 tasklet_schedule(&tp->tl);
1187 }
1188 }
1189 spin_unlock_irqrestore(&tp->rx_lock, lockflags);
1190}
1191
1192static void tx_bottom(struct r8152 *tp)
1193{
1194 struct net_device_stats *stats;
1195 struct net_device *netdev;
1196 struct tx_agg *agg;
1197 unsigned long lockflags;
1198 u32 remain, total;
1199 u8 *tx_data;
1200 int res;
1201
1202 netdev = tp->netdev;
1203
1204next_agg:
1205 agg = NULL;
1206 spin_lock_irqsave(&tp->tx_lock, lockflags);
1207 if (!skb_queue_empty(&tp->tx_queue) && !list_empty(&tp->tx_free)) {
1208 struct list_head *cursor;
1209
1210 cursor = tp->tx_free.next;
1211 list_del_init(cursor);
1212 agg = list_entry(cursor, struct tx_agg, list);
1213 }
1214 spin_unlock_irqrestore(&tp->tx_lock, lockflags);
1215
1216 if (!agg)
1217 return;
1218
1219 tx_data = agg->head;
1220 agg->skb_num = agg->skb_len = 0;
1221 remain = rx_buf_sz - sizeof(struct tx_desc);
1222 total = 0;
1223
1224 while (remain >= ETH_ZLEN) {
1225 struct tx_desc *tx_desc;
1226 struct sk_buff *skb;
1227 unsigned int len;
1228
1229 skb = skb_dequeue(&tp->tx_queue);
1230 if (!skb)
1231 break;
1232
1233 len = skb->len;
1234 if (remain < len) {
1235 skb_queue_head(&tp->tx_queue, skb);
1236 break;
1237 }
1238
1239 tx_data = tx_agg_align(tx_data);
1240 tx_desc = (struct tx_desc *)tx_data;
1241 tx_data += sizeof(*tx_desc);
1242
5bd23881 1243 r8152_tx_csum(tp, tx_desc, skb);
ebc2ec48 1244 memcpy(tx_data, skb->data, len);
1245 agg->skb_num++;
1246 agg->skb_len += len;
1247 dev_kfree_skb_any(skb);
1248
1249 tx_data += len;
1250 remain = rx_buf_sz - sizeof(*tx_desc) -
1251 (u32)(tx_agg_align(tx_data) - agg->head);
1252 }
1253
1254 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1255 agg->head, (int)(tx_data - (u8 *)agg->head),
1256 (usb_complete_t)write_bulk_callback, agg);
1257 res = usb_submit_urb(agg->urb, GFP_ATOMIC);
1258
1259 stats = rtl8152_get_stats(netdev);
1260
1261 if (res) {
1262 /* Can we get/handle EPIPE here? */
1263 if (res == -ENODEV) {
1264 netif_device_detach(netdev);
1265 } else {
1266 netif_warn(tp, tx_err, netdev,
1267 "failed tx_urb %d\n", res);
1268 stats->tx_dropped += agg->skb_num;
1269 spin_lock_irqsave(&tp->tx_lock, lockflags);
1270 list_add_tail(&agg->list, &tp->tx_free);
1271 spin_unlock_irqrestore(&tp->tx_lock, lockflags);
1272 }
1273 return;
1274 }
1275 goto next_agg;
1276}
1277
1278static void bottom_half(unsigned long data)
ac718b69 1279{
1280 struct r8152 *tp;
ac718b69 1281
ebc2ec48 1282 tp = (struct r8152 *)data;
1283
1284 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1285 return;
1286
1287 if (!test_bit(WORK_ENABLE, &tp->flags))
ac718b69 1288 return;
ebc2ec48 1289
1290 if (!netif_carrier_ok(tp->netdev))
ac718b69 1291 return;
ebc2ec48 1292
1293 rx_bottom(tp);
1294 tx_bottom(tp);
1295}
1296
1297static
1298int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1299{
1300 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1301 agg->head, rx_buf_sz,
1302 (usb_complete_t)read_bulk_callback, agg);
1303
1304 return usb_submit_urb(agg->urb, mem_flags);
ac718b69 1305}
1306
1307static void rtl8152_tx_timeout(struct net_device *netdev)
1308{
1309 struct r8152 *tp = netdev_priv(netdev);
ebc2ec48 1310 int i;
1311
ac718b69 1312 netif_warn(tp, tx_err, netdev, "Tx timeout.\n");
ebc2ec48 1313 for (i = 0; i < RTL8152_MAX_TX; i++)
1314 usb_unlink_urb(tp->tx_info[i].urb);
ac718b69 1315}
1316
1317static void rtl8152_set_rx_mode(struct net_device *netdev)
1318{
1319 struct r8152 *tp = netdev_priv(netdev);
1320
40a82917 1321 if (tp->speed & LINK_STATUS) {
ac718b69 1322 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
40a82917 1323 schedule_delayed_work(&tp->schedule, 0);
1324 }
ac718b69 1325}
1326
1327static void _rtl8152_set_rx_mode(struct net_device *netdev)
1328{
1329 struct r8152 *tp = netdev_priv(netdev);
31787f53 1330 u32 mc_filter[2]; /* Multicast hash filter */
1331 __le32 tmp[2];
ac718b69 1332 u32 ocp_data;
1333
ac718b69 1334 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1335 netif_stop_queue(netdev);
1336 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1337 ocp_data &= ~RCR_ACPT_ALL;
1338 ocp_data |= RCR_AB | RCR_APM;
1339
1340 if (netdev->flags & IFF_PROMISC) {
1341 /* Unconditionally log net taps. */
1342 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1343 ocp_data |= RCR_AM | RCR_AAP;
1344 mc_filter[1] = mc_filter[0] = 0xffffffff;
1345 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1346 (netdev->flags & IFF_ALLMULTI)) {
1347 /* Too many to filter perfectly -- accept all multicasts. */
1348 ocp_data |= RCR_AM;
1349 mc_filter[1] = mc_filter[0] = 0xffffffff;
1350 } else {
1351 struct netdev_hw_addr *ha;
1352
1353 mc_filter[1] = mc_filter[0] = 0;
1354 netdev_for_each_mc_addr(ha, netdev) {
1355 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1356 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1357 ocp_data |= RCR_AM;
1358 }
1359 }
1360
31787f53 1361 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1362 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
ac718b69 1363
31787f53 1364 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
ac718b69 1365 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1366 netif_wake_queue(netdev);
ac718b69 1367}
1368
1369static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1370 struct net_device *netdev)
1371{
1372 struct r8152 *tp = netdev_priv(netdev);
1373 struct net_device_stats *stats = rtl8152_get_stats(netdev);
ebc2ec48 1374 unsigned long lockflags;
1375 struct tx_agg *agg = NULL;
ac718b69 1376 struct tx_desc *tx_desc;
3ff25e3c 1377 unsigned int len;
ebc2ec48 1378 u8 *tx_data;
3ff25e3c 1379 int res;
ac718b69 1380
ebc2ec48 1381 skb_tx_timestamp(skb);
ac718b69 1382
ebc2ec48 1383 spin_lock_irqsave(&tp->tx_lock, lockflags);
1384 if (!list_empty(&tp->tx_free) && skb_queue_empty(&tp->tx_queue)) {
1385 struct list_head *cursor;
1386
1387 cursor = tp->tx_free.next;
1388 list_del_init(cursor);
1389 agg = list_entry(cursor, struct tx_agg, list);
ac718b69 1390 }
ebc2ec48 1391 spin_unlock_irqrestore(&tp->tx_lock, lockflags);
1392
1393 if (!agg) {
1394 skb_queue_tail(&tp->tx_queue, skb);
1395 return NETDEV_TX_OK;
1396 }
1397
1398 tx_desc = (struct tx_desc *)agg->head;
1399 tx_data = agg->head + sizeof(*tx_desc);
1400 agg->skb_num = agg->skb_len = 0;
1401
1402 len = skb->len;
5bd23881 1403 r8152_tx_csum(tp, tx_desc, skb);
ebc2ec48 1404 memcpy(tx_data, skb->data, len);
1405 dev_kfree_skb_any(skb);
1406 agg->skb_num++;
1407 agg->skb_len += len;
1408 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1409 agg->head, len + sizeof(*tx_desc),
1410 (usb_complete_t)write_bulk_callback, agg);
1411 res = usb_submit_urb(agg->urb, GFP_ATOMIC);
ac718b69 1412 if (res) {
1413 /* Can we get/handle EPIPE here? */
1414 if (res == -ENODEV) {
1415 netif_device_detach(tp->netdev);
1416 } else {
1417 netif_warn(tp, tx_err, netdev,
1418 "failed tx_urb %d\n", res);
ebc2ec48 1419 stats->tx_dropped++;
1420 spin_lock_irqsave(&tp->tx_lock, lockflags);
1421 list_add_tail(&agg->list, &tp->tx_free);
1422 spin_unlock_irqrestore(&tp->tx_lock, lockflags);
ac718b69 1423 }
ac718b69 1424 }
1425
1426 return NETDEV_TX_OK;
1427}
1428
1429static void r8152b_reset_packet_filter(struct r8152 *tp)
1430{
1431 u32 ocp_data;
1432
1433 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1434 ocp_data &= ~FMC_FCR_MCU_EN;
1435 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1436 ocp_data |= FMC_FCR_MCU_EN;
1437 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1438}
1439
1440static void rtl8152_nic_reset(struct r8152 *tp)
1441{
1442 int i;
1443
1444 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1445
1446 for (i = 0; i < 1000; i++) {
1447 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1448 break;
1449 udelay(100);
1450 }
1451}
1452
1453static inline u8 rtl8152_get_speed(struct r8152 *tp)
1454{
1455 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1456}
1457
1458static int rtl8152_enable(struct r8152 *tp)
1459{
ebc2ec48 1460 u32 ocp_data;
1461 int i, ret;
ac718b69 1462 u8 speed;
1463
1464 speed = rtl8152_get_speed(tp);
ebc2ec48 1465 if (speed & _10bps) {
ac718b69 1466 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 1467 ocp_data |= EEEP_CR_EEEP_TX;
ac718b69 1468 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1469 } else {
1470 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 1471 ocp_data &= ~EEEP_CR_EEEP_TX;
ac718b69 1472 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1473 }
1474
1475 r8152b_reset_packet_filter(tp);
1476
1477 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
1478 ocp_data |= CR_RE | CR_TE;
1479 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
1480
1481 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1482 ocp_data &= ~RXDY_GATED_EN;
1483 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1484
ebc2ec48 1485 INIT_LIST_HEAD(&tp->rx_done);
1486 ret = 0;
1487 for (i = 0; i < RTL8152_MAX_RX; i++) {
1488 INIT_LIST_HEAD(&tp->rx_info[i].list);
1489 ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
1490 }
ac718b69 1491
ebc2ec48 1492 return ret;
ac718b69 1493}
1494
1495static void rtl8152_disable(struct r8152 *tp)
1496{
ebc2ec48 1497 struct net_device_stats *stats = rtl8152_get_stats(tp->netdev);
1498 struct sk_buff *skb;
1499 u32 ocp_data;
1500 int i;
ac718b69 1501
1502 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1503 ocp_data &= ~RCR_ACPT_ALL;
1504 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1505
ebc2ec48 1506 while ((skb = skb_dequeue(&tp->tx_queue))) {
1507 dev_kfree_skb(skb);
1508 stats->tx_dropped++;
1509 }
1510
1511 for (i = 0; i < RTL8152_MAX_TX; i++)
1512 usb_kill_urb(tp->tx_info[i].urb);
ac718b69 1513
1514 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1515 ocp_data |= RXDY_GATED_EN;
1516 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1517
1518 for (i = 0; i < 1000; i++) {
1519 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1520 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
1521 break;
1522 mdelay(1);
1523 }
1524
1525 for (i = 0; i < 1000; i++) {
1526 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
1527 break;
1528 mdelay(1);
1529 }
1530
ebc2ec48 1531 for (i = 0; i < RTL8152_MAX_RX; i++)
1532 usb_kill_urb(tp->rx_info[i].urb);
ac718b69 1533
1534 rtl8152_nic_reset(tp);
1535}
1536
1537static void r8152b_exit_oob(struct r8152 *tp)
1538{
1539 u32 ocp_data;
1540 int i;
1541
1542 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1543 ocp_data &= ~RCR_ACPT_ALL;
1544 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1545
1546 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1547 ocp_data |= RXDY_GATED_EN;
1548 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1549
1550 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1551 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
1552
1553 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1554 ocp_data &= ~NOW_IS_OOB;
1555 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1556
1557 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1558 ocp_data &= ~MCU_BORW_EN;
1559 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1560
1561 for (i = 0; i < 1000; i++) {
1562 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1563 if (ocp_data & LINK_LIST_READY)
1564 break;
1565 mdelay(1);
1566 }
1567
1568 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1569 ocp_data |= RE_INIT_LL;
1570 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1571
1572 for (i = 0; i < 1000; i++) {
1573 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1574 if (ocp_data & LINK_LIST_READY)
1575 break;
1576 mdelay(1);
1577 }
1578
1579 rtl8152_nic_reset(tp);
1580
1581 /* rx share fifo credit full threshold */
1582 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
1583
1584 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT);
1585 ocp_data &= STAT_SPEED_MASK;
1586 if (ocp_data == STAT_SPEED_FULL) {
1587 /* rx share fifo credit near full threshold */
1588 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
1589 RXFIFO_THR2_FULL);
1590 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
1591 RXFIFO_THR3_FULL);
1592 } else {
1593 /* rx share fifo credit near full threshold */
1594 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
1595 RXFIFO_THR2_HIGH);
1596 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
1597 RXFIFO_THR3_HIGH);
1598 }
1599
1600 /* TX share fifo free credit full threshold */
1601 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
1602
1603 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
1604 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_BUF_THR);
1605 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
1606 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
1607
1608 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
1609 ocp_data &= ~CPCR_RX_VLAN;
1610 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
1611
1612 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
1613
1614 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
1615 ocp_data |= TCR0_AUTO_FIFO;
1616 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
1617}
1618
1619static void r8152b_enter_oob(struct r8152 *tp)
1620{
1621 u32 ocp_data;
1622 int i;
1623
1624 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1625 ocp_data &= ~NOW_IS_OOB;
1626 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1627
1628 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
1629 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
1630 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
1631
1632 rtl8152_disable(tp);
1633
1634 for (i = 0; i < 1000; i++) {
1635 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1636 if (ocp_data & LINK_LIST_READY)
1637 break;
1638 mdelay(1);
1639 }
1640
1641 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1642 ocp_data |= RE_INIT_LL;
1643 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1644
1645 for (i = 0; i < 1000; i++) {
1646 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1647 if (ocp_data & LINK_LIST_READY)
1648 break;
1649 mdelay(1);
1650 }
1651
1652 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
1653
1654 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
1655 ocp_data |= MAGIC_EN;
1656 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
1657
1658 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
1659 ocp_data |= CPCR_RX_VLAN;
1660 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
1661
1662 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
1663 ocp_data |= ALDPS_PROXY_MODE;
1664 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
1665
1666 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1667 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
1668 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1669
1670 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN);
1671
1672 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1673 ocp_data &= ~RXDY_GATED_EN;
1674 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1675
1676 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1677 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
1678 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1679}
1680
1681static void r8152b_disable_aldps(struct r8152 *tp)
1682{
1683 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
1684 msleep(20);
1685}
1686
1687static inline void r8152b_enable_aldps(struct r8152 *tp)
1688{
1689 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
1690 LINKENA | DIS_SDSAVE);
1691}
1692
1693static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
1694{
1695 u16 bmcr, anar;
1696 int ret = 0;
1697
1698 cancel_delayed_work_sync(&tp->schedule);
1699 anar = r8152_mdio_read(tp, MII_ADVERTISE);
1700 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1701 ADVERTISE_100HALF | ADVERTISE_100FULL);
1702
1703 if (autoneg == AUTONEG_DISABLE) {
1704 if (speed == SPEED_10) {
1705 bmcr = 0;
1706 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1707 } else if (speed == SPEED_100) {
1708 bmcr = BMCR_SPEED100;
1709 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1710 } else {
1711 ret = -EINVAL;
1712 goto out;
1713 }
1714
1715 if (duplex == DUPLEX_FULL)
1716 bmcr |= BMCR_FULLDPLX;
1717 } else {
1718 if (speed == SPEED_10) {
1719 if (duplex == DUPLEX_FULL)
1720 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1721 else
1722 anar |= ADVERTISE_10HALF;
1723 } else if (speed == SPEED_100) {
1724 if (duplex == DUPLEX_FULL) {
1725 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1726 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1727 } else {
1728 anar |= ADVERTISE_10HALF;
1729 anar |= ADVERTISE_100HALF;
1730 }
1731 } else {
1732 ret = -EINVAL;
1733 goto out;
1734 }
1735
1736 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1737 }
1738
1739 r8152_mdio_write(tp, MII_ADVERTISE, anar);
1740 r8152_mdio_write(tp, MII_BMCR, bmcr);
1741
1742out:
ac718b69 1743
1744 return ret;
1745}
1746
1747static void rtl8152_down(struct r8152 *tp)
1748{
1749 u32 ocp_data;
1750
1751 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
1752 ocp_data &= ~POWER_CUT;
1753 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
1754
1755 r8152b_disable_aldps(tp);
1756 r8152b_enter_oob(tp);
1757 r8152b_enable_aldps(tp);
1758}
1759
1760static void set_carrier(struct r8152 *tp)
1761{
1762 struct net_device *netdev = tp->netdev;
1763 u8 speed;
1764
40a82917 1765 clear_bit(RTL8152_LINK_CHG, &tp->flags);
ac718b69 1766 speed = rtl8152_get_speed(tp);
1767
1768 if (speed & LINK_STATUS) {
1769 if (!(tp->speed & LINK_STATUS)) {
1770 rtl8152_enable(tp);
1771 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1772 netif_carrier_on(netdev);
1773 }
1774 } else {
1775 if (tp->speed & LINK_STATUS) {
1776 netif_carrier_off(netdev);
ebc2ec48 1777 tasklet_disable(&tp->tl);
ac718b69 1778 rtl8152_disable(tp);
ebc2ec48 1779 tasklet_enable(&tp->tl);
ac718b69 1780 }
1781 }
1782 tp->speed = speed;
1783}
1784
1785static void rtl_work_func_t(struct work_struct *work)
1786{
1787 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
1788
1789 if (!test_bit(WORK_ENABLE, &tp->flags))
1790 goto out1;
1791
1792 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1793 goto out1;
1794
40a82917 1795 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
1796 set_carrier(tp);
ac718b69 1797
1798 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
1799 _rtl8152_set_rx_mode(tp->netdev);
1800
ac718b69 1801out1:
1802 return;
1803}
1804
1805static int rtl8152_open(struct net_device *netdev)
1806{
1807 struct r8152 *tp = netdev_priv(netdev);
1808 int res = 0;
1809
40a82917 1810 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
1811 if (res) {
1812 if (res == -ENODEV)
1813 netif_device_detach(tp->netdev);
1814 netif_warn(tp, ifup, netdev,
1815 "intr_urb submit failed: %d\n", res);
1816 return res;
ac718b69 1817 }
1818
1819 rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL);
40a82917 1820 tp->speed = 0;
1821 netif_carrier_off(netdev);
ac718b69 1822 netif_start_queue(netdev);
1823 set_bit(WORK_ENABLE, &tp->flags);
ac718b69 1824
1825 return res;
1826}
1827
1828static int rtl8152_close(struct net_device *netdev)
1829{
1830 struct r8152 *tp = netdev_priv(netdev);
1831 int res = 0;
1832
40a82917 1833 usb_kill_urb(tp->intr_urb);
ac718b69 1834 clear_bit(WORK_ENABLE, &tp->flags);
1835 cancel_delayed_work_sync(&tp->schedule);
1836 netif_stop_queue(netdev);
ebc2ec48 1837 tasklet_disable(&tp->tl);
ac718b69 1838 rtl8152_disable(tp);
ebc2ec48 1839 tasklet_enable(&tp->tl);
ac718b69 1840
1841 return res;
1842}
1843
1844static void rtl_clear_bp(struct r8152 *tp)
1845{
1846 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
1847 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
1848 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
1849 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
1850 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
1851 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
1852 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
1853 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
1854 mdelay(3);
1855 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
1856 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
1857}
1858
1859static void r8152b_enable_eee(struct r8152 *tp)
1860{
1861 u32 ocp_data;
1862
1863 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
1864 ocp_data |= EEE_RX_EN | EEE_TX_EN;
1865 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
1866 ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN |
1867 EEE_10_CAP | EEE_NWAY_EN |
1868 TX_QUIET_EN | RX_QUIET_EN |
1869 SDRISETIME | RG_RXLPI_MSK_HFDUP |
1870 SDFALLTIME);
1871 ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN |
1872 RG_LDVQUIET_EN | RG_CKRSEL |
1873 RG_EEEPRG_EN);
1874 ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH);
1875 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR);
1876 ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR);
1877 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR);
1878 ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA);
1879 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
1880}
1881
1882static void r8152b_enable_fc(struct r8152 *tp)
1883{
1884 u16 anar;
1885
1886 anar = r8152_mdio_read(tp, MII_ADVERTISE);
1887 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1888 r8152_mdio_write(tp, MII_ADVERTISE, anar);
1889}
1890
1891static void r8152b_hw_phy_cfg(struct r8152 *tp)
1892{
1893 r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE);
1894 r8152b_disable_aldps(tp);
1895}
1896
1897static void r8152b_init(struct r8152 *tp)
1898{
ebc2ec48 1899 u32 ocp_data;
1900 int i;
ac718b69 1901
1902 rtl_clear_bp(tp);
1903
1904 if (tp->version == RTL_VER_01) {
1905 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
1906 ocp_data &= ~LED_MODE_MASK;
1907 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
1908 }
1909
1910 r8152b_hw_phy_cfg(tp);
1911
1912 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
1913 ocp_data &= ~POWER_CUT;
1914 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
1915
1916 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
1917 ocp_data &= ~RWSUME_INDICATE;
1918 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
1919
1920 r8152b_exit_oob(tp);
1921
1922 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
1923 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
1924 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
1925 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
1926 ocp_data &= ~MCU_CLK_RATIO_MASK;
1927 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
1928 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
1929 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
1930 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
1931 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
1932
1933 r8152b_enable_eee(tp);
1934 r8152b_enable_aldps(tp);
1935 r8152b_enable_fc(tp);
1936
1937 r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE |
1938 BMCR_ANRESTART);
1939 for (i = 0; i < 100; i++) {
1940 udelay(100);
1941 if (!(r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET))
1942 break;
1943 }
1944
ebc2ec48 1945 /* enable rx aggregation */
ac718b69 1946 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
ebc2ec48 1947 ocp_data &= ~RX_AGG_DISABLE;
ac718b69 1948 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
1949}
1950
1951static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
1952{
1953 struct r8152 *tp = usb_get_intfdata(intf);
1954
1955 netif_device_detach(tp->netdev);
1956
1957 if (netif_running(tp->netdev)) {
1958 clear_bit(WORK_ENABLE, &tp->flags);
40a82917 1959 usb_kill_urb(tp->intr_urb);
ac718b69 1960 cancel_delayed_work_sync(&tp->schedule);
ebc2ec48 1961 tasklet_disable(&tp->tl);
ac718b69 1962 }
1963
1964 rtl8152_down(tp);
1965
1966 return 0;
1967}
1968
1969static int rtl8152_resume(struct usb_interface *intf)
1970{
1971 struct r8152 *tp = usb_get_intfdata(intf);
1972
1973 r8152b_init(tp);
1974 netif_device_attach(tp->netdev);
1975 if (netif_running(tp->netdev)) {
40a82917 1976 rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL);
1977 tp->speed = 0;
1978 netif_carrier_off(tp->netdev);
ac718b69 1979 set_bit(WORK_ENABLE, &tp->flags);
40a82917 1980 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
ebc2ec48 1981 tasklet_enable(&tp->tl);
ac718b69 1982 }
1983
1984 return 0;
1985}
1986
1987static void rtl8152_get_drvinfo(struct net_device *netdev,
1988 struct ethtool_drvinfo *info)
1989{
1990 struct r8152 *tp = netdev_priv(netdev);
1991
1992 strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN);
1993 strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN);
1994 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
1995}
1996
1997static
1998int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1999{
2000 struct r8152 *tp = netdev_priv(netdev);
2001
2002 if (!tp->mii.mdio_read)
2003 return -EOPNOTSUPP;
2004
2005 return mii_ethtool_gset(&tp->mii, cmd);
2006}
2007
2008static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2009{
2010 struct r8152 *tp = netdev_priv(dev);
2011
2012 return rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
2013}
2014
2015static struct ethtool_ops ops = {
2016 .get_drvinfo = rtl8152_get_drvinfo,
2017 .get_settings = rtl8152_get_settings,
2018 .set_settings = rtl8152_set_settings,
2019 .get_link = ethtool_op_get_link,
2020};
2021
2022static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2023{
2024 struct r8152 *tp = netdev_priv(netdev);
2025 struct mii_ioctl_data *data = if_mii(rq);
2026 int res = 0;
2027
2028 switch (cmd) {
2029 case SIOCGMIIPHY:
2030 data->phy_id = R8152_PHY_ID; /* Internal PHY */
2031 break;
2032
2033 case SIOCGMIIREG:
2034 data->val_out = r8152_mdio_read(tp, data->reg_num);
2035 break;
2036
2037 case SIOCSMIIREG:
2038 if (!capable(CAP_NET_ADMIN)) {
2039 res = -EPERM;
2040 break;
2041 }
2042 r8152_mdio_write(tp, data->reg_num, data->val_in);
2043 break;
2044
2045 default:
2046 res = -EOPNOTSUPP;
2047 }
2048
2049 return res;
2050}
2051
2052static const struct net_device_ops rtl8152_netdev_ops = {
2053 .ndo_open = rtl8152_open,
2054 .ndo_stop = rtl8152_close,
2055 .ndo_do_ioctl = rtl8152_ioctl,
2056 .ndo_start_xmit = rtl8152_start_xmit,
2057 .ndo_tx_timeout = rtl8152_tx_timeout,
2058 .ndo_set_rx_mode = rtl8152_set_rx_mode,
2059 .ndo_set_mac_address = rtl8152_set_mac_address,
2060
2061 .ndo_change_mtu = eth_change_mtu,
2062 .ndo_validate_addr = eth_validate_addr,
2063};
2064
2065static void r8152b_get_version(struct r8152 *tp)
2066{
2067 u32 ocp_data;
2068 u16 version;
2069
2070 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
2071 version = (u16)(ocp_data & VERSION_MASK);
2072
2073 switch (version) {
2074 case 0x4c00:
2075 tp->version = RTL_VER_01;
2076 break;
2077 case 0x4c10:
2078 tp->version = RTL_VER_02;
2079 break;
2080 default:
2081 netif_info(tp, probe, tp->netdev,
2082 "Unknown version 0x%04x\n", version);
2083 break;
2084 }
2085}
2086
2087static int rtl8152_probe(struct usb_interface *intf,
2088 const struct usb_device_id *id)
2089{
2090 struct usb_device *udev = interface_to_usbdev(intf);
2091 struct r8152 *tp;
2092 struct net_device *netdev;
ebc2ec48 2093 int ret;
ac718b69 2094
2095 if (udev->actconfig->desc.bConfigurationValue != 1) {
2096 usb_driver_set_configuration(udev, 1);
2097 return -ENODEV;
2098 }
2099
2100 netdev = alloc_etherdev(sizeof(struct r8152));
2101 if (!netdev) {
2102 dev_err(&intf->dev, "Out of memory");
2103 return -ENOMEM;
2104 }
2105
ebc2ec48 2106 SET_NETDEV_DEV(netdev, &intf->dev);
ac718b69 2107 tp = netdev_priv(netdev);
ebc2ec48 2108 memset(tp, 0, sizeof(*tp));
ac718b69 2109 tp->msg_enable = 0x7FFF;
2110
ebc2ec48 2111 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
ac718b69 2112 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
2113
2114 tp->udev = udev;
2115 tp->netdev = netdev;
40a82917 2116 tp->intf = intf;
ac718b69 2117 netdev->netdev_ops = &rtl8152_netdev_ops;
2118 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5bd23881 2119
2120 netdev->features |= NETIF_F_IP_CSUM;
2121 netdev->hw_features = NETIF_F_IP_CSUM;
ac718b69 2122 SET_ETHTOOL_OPS(netdev, &ops);
ac718b69 2123
2124 tp->mii.dev = netdev;
2125 tp->mii.mdio_read = read_mii_word;
2126 tp->mii.mdio_write = write_mii_word;
2127 tp->mii.phy_id_mask = 0x3f;
2128 tp->mii.reg_num_mask = 0x1f;
2129 tp->mii.phy_id = R8152_PHY_ID;
2130 tp->mii.supports_gmii = 0;
2131
2132 r8152b_get_version(tp);
2133 r8152b_init(tp);
2134 set_ethernet_addr(tp);
2135
ebc2ec48 2136 ret = alloc_all_mem(tp);
2137 if (ret)
ac718b69 2138 goto out;
ac718b69 2139
2140 usb_set_intfdata(intf, tp);
ac718b69 2141
ebc2ec48 2142 ret = register_netdev(netdev);
2143 if (ret != 0) {
ac718b69 2144 netif_err(tp, probe, netdev, "couldn't register the device");
ebc2ec48 2145 goto out1;
ac718b69 2146 }
2147
2148 netif_info(tp, probe, netdev, "%s", DRIVER_VERSION);
2149
2150 return 0;
2151
ac718b69 2152out1:
ebc2ec48 2153 usb_set_intfdata(intf, NULL);
ac718b69 2154out:
2155 free_netdev(netdev);
ebc2ec48 2156 return ret;
ac718b69 2157}
2158
2159static void rtl8152_unload(struct r8152 *tp)
2160{
2161 u32 ocp_data;
2162
2163 if (tp->version != RTL_VER_01) {
2164 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2165 ocp_data |= POWER_CUT;
2166 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2167 }
2168
2169 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2170 ocp_data &= ~RWSUME_INDICATE;
2171 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2172}
2173
2174static void rtl8152_disconnect(struct usb_interface *intf)
2175{
2176 struct r8152 *tp = usb_get_intfdata(intf);
2177
2178 usb_set_intfdata(intf, NULL);
2179 if (tp) {
2180 set_bit(RTL8152_UNPLUG, &tp->flags);
2181 tasklet_kill(&tp->tl);
2182 unregister_netdev(tp->netdev);
2183 rtl8152_unload(tp);
ebc2ec48 2184 free_all_mem(tp);
ac718b69 2185 free_netdev(tp->netdev);
2186 }
2187}
2188
2189/* table of devices that work with this driver */
2190static struct usb_device_id rtl8152_table[] = {
2191 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
2192 {}
2193};
2194
2195MODULE_DEVICE_TABLE(usb, rtl8152_table);
2196
2197static struct usb_driver rtl8152_driver = {
2198 .name = MODULENAME,
ebc2ec48 2199 .id_table = rtl8152_table,
ac718b69 2200 .probe = rtl8152_probe,
2201 .disconnect = rtl8152_disconnect,
ac718b69 2202 .suspend = rtl8152_suspend,
ebc2ec48 2203 .resume = rtl8152_resume,
2204 .reset_resume = rtl8152_resume,
ac718b69 2205};
2206
b4236daa 2207module_usb_driver(rtl8152_driver);
ac718b69 2208
2209MODULE_AUTHOR(DRIVER_AUTHOR);
2210MODULE_DESCRIPTION(DRIVER_DESC);
2211MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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