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ac718b69 | 1 | /* |
c7de7dec | 2 | * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. |
ac718b69 | 3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
ac718b69 | 10 | #include <linux/signal.h> |
11 | #include <linux/slab.h> | |
12 | #include <linux/module.h> | |
ac718b69 | 13 | #include <linux/netdevice.h> |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/mii.h> | |
16 | #include <linux/ethtool.h> | |
17 | #include <linux/usb.h> | |
18 | #include <linux/crc32.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/uaccess.h> | |
ebc2ec48 | 21 | #include <linux/list.h> |
5bd23881 | 22 | #include <linux/ip.h> |
23 | #include <linux/ipv6.h> | |
6128d1bb | 24 | #include <net/ip6_checksum.h> |
4c4a6b1b | 25 | #include <uapi/linux/mdio.h> |
26 | #include <linux/mdio.h> | |
ac718b69 | 27 | |
28 | /* Version Information */ | |
60c89071 | 29 | #define DRIVER_VERSION "v1.06.0 (2014/03/03)" |
ac718b69 | 30 | #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" |
44d942a9 | 31 | #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" |
ac718b69 | 32 | #define MODULENAME "r8152" |
33 | ||
34 | #define R8152_PHY_ID 32 | |
35 | ||
36 | #define PLA_IDR 0xc000 | |
37 | #define PLA_RCR 0xc010 | |
38 | #define PLA_RMS 0xc016 | |
39 | #define PLA_RXFIFO_CTRL0 0xc0a0 | |
40 | #define PLA_RXFIFO_CTRL1 0xc0a4 | |
41 | #define PLA_RXFIFO_CTRL2 0xc0a8 | |
42 | #define PLA_FMC 0xc0b4 | |
43 | #define PLA_CFG_WOL 0xc0b6 | |
43779f8d | 44 | #define PLA_TEREDO_CFG 0xc0bc |
ac718b69 | 45 | #define PLA_MAR 0xcd00 |
43779f8d | 46 | #define PLA_BACKUP 0xd000 |
ac718b69 | 47 | #define PAL_BDC_CR 0xd1a0 |
43779f8d | 48 | #define PLA_TEREDO_TIMER 0xd2cc |
49 | #define PLA_REALWOW_TIMER 0xd2e8 | |
ac718b69 | 50 | #define PLA_LEDSEL 0xdd90 |
51 | #define PLA_LED_FEATURE 0xdd92 | |
52 | #define PLA_PHYAR 0xde00 | |
43779f8d | 53 | #define PLA_BOOT_CTRL 0xe004 |
ac718b69 | 54 | #define PLA_GPHY_INTR_IMR 0xe022 |
55 | #define PLA_EEE_CR 0xe040 | |
56 | #define PLA_EEEP_CR 0xe080 | |
57 | #define PLA_MAC_PWR_CTRL 0xe0c0 | |
43779f8d | 58 | #define PLA_MAC_PWR_CTRL2 0xe0ca |
59 | #define PLA_MAC_PWR_CTRL3 0xe0cc | |
60 | #define PLA_MAC_PWR_CTRL4 0xe0ce | |
61 | #define PLA_WDT6_CTRL 0xe428 | |
ac718b69 | 62 | #define PLA_TCR0 0xe610 |
63 | #define PLA_TCR1 0xe612 | |
69b4b7a4 | 64 | #define PLA_MTPS 0xe615 |
ac718b69 | 65 | #define PLA_TXFIFO_CTRL 0xe618 |
4f1d4d54 | 66 | #define PLA_RSTTALLY 0xe800 |
ac718b69 | 67 | #define PLA_CR 0xe813 |
68 | #define PLA_CRWECR 0xe81c | |
21ff2e89 | 69 | #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ |
70 | #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ | |
ac718b69 | 71 | #define PLA_CONFIG5 0xe822 |
72 | #define PLA_PHY_PWR 0xe84c | |
73 | #define PLA_OOB_CTRL 0xe84f | |
74 | #define PLA_CPCR 0xe854 | |
75 | #define PLA_MISC_0 0xe858 | |
76 | #define PLA_MISC_1 0xe85a | |
77 | #define PLA_OCP_GPHY_BASE 0xe86c | |
4f1d4d54 | 78 | #define PLA_TALLYCNT 0xe890 |
ac718b69 | 79 | #define PLA_SFF_STS_7 0xe8de |
80 | #define PLA_PHYSTATUS 0xe908 | |
81 | #define PLA_BP_BA 0xfc26 | |
82 | #define PLA_BP_0 0xfc28 | |
83 | #define PLA_BP_1 0xfc2a | |
84 | #define PLA_BP_2 0xfc2c | |
85 | #define PLA_BP_3 0xfc2e | |
86 | #define PLA_BP_4 0xfc30 | |
87 | #define PLA_BP_5 0xfc32 | |
88 | #define PLA_BP_6 0xfc34 | |
89 | #define PLA_BP_7 0xfc36 | |
43779f8d | 90 | #define PLA_BP_EN 0xfc38 |
ac718b69 | 91 | |
43779f8d | 92 | #define USB_U2P3_CTRL 0xb460 |
ac718b69 | 93 | #define USB_DEV_STAT 0xb808 |
94 | #define USB_USB_CTRL 0xd406 | |
95 | #define USB_PHY_CTRL 0xd408 | |
96 | #define USB_TX_AGG 0xd40a | |
97 | #define USB_RX_BUF_TH 0xd40c | |
98 | #define USB_USB_TIMER 0xd428 | |
43779f8d | 99 | #define USB_RX_EARLY_AGG 0xd42c |
ac718b69 | 100 | #define USB_PM_CTRL_STATUS 0xd432 |
101 | #define USB_TX_DMA 0xd434 | |
43779f8d | 102 | #define USB_TOLERANCE 0xd490 |
103 | #define USB_LPM_CTRL 0xd41a | |
ac718b69 | 104 | #define USB_UPS_CTRL 0xd800 |
43779f8d | 105 | #define USB_MISC_0 0xd81a |
106 | #define USB_POWER_CUT 0xd80a | |
107 | #define USB_AFE_CTRL2 0xd824 | |
108 | #define USB_WDT11_CTRL 0xe43c | |
ac718b69 | 109 | #define USB_BP_BA 0xfc26 |
110 | #define USB_BP_0 0xfc28 | |
111 | #define USB_BP_1 0xfc2a | |
112 | #define USB_BP_2 0xfc2c | |
113 | #define USB_BP_3 0xfc2e | |
114 | #define USB_BP_4 0xfc30 | |
115 | #define USB_BP_5 0xfc32 | |
116 | #define USB_BP_6 0xfc34 | |
117 | #define USB_BP_7 0xfc36 | |
43779f8d | 118 | #define USB_BP_EN 0xfc38 |
ac718b69 | 119 | |
120 | /* OCP Registers */ | |
121 | #define OCP_ALDPS_CONFIG 0x2010 | |
122 | #define OCP_EEE_CONFIG1 0x2080 | |
123 | #define OCP_EEE_CONFIG2 0x2092 | |
124 | #define OCP_EEE_CONFIG3 0x2094 | |
ac244d3e | 125 | #define OCP_BASE_MII 0xa400 |
ac718b69 | 126 | #define OCP_EEE_AR 0xa41a |
127 | #define OCP_EEE_DATA 0xa41c | |
43779f8d | 128 | #define OCP_PHY_STATUS 0xa420 |
129 | #define OCP_POWER_CFG 0xa430 | |
130 | #define OCP_EEE_CFG 0xa432 | |
131 | #define OCP_SRAM_ADDR 0xa436 | |
132 | #define OCP_SRAM_DATA 0xa438 | |
133 | #define OCP_DOWN_SPEED 0xa442 | |
4c4a6b1b | 134 | #define OCP_EEE_ADV 0xa5d0 |
43779f8d | 135 | #define OCP_ADC_CFG 0xbc06 |
136 | ||
137 | /* SRAM Register */ | |
138 | #define SRAM_LPF_CFG 0x8012 | |
139 | #define SRAM_10M_AMP1 0x8080 | |
140 | #define SRAM_10M_AMP2 0x8082 | |
141 | #define SRAM_IMPEDANCE 0x8084 | |
ac718b69 | 142 | |
143 | /* PLA_RCR */ | |
144 | #define RCR_AAP 0x00000001 | |
145 | #define RCR_APM 0x00000002 | |
146 | #define RCR_AM 0x00000004 | |
147 | #define RCR_AB 0x00000008 | |
148 | #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) | |
149 | ||
150 | /* PLA_RXFIFO_CTRL0 */ | |
151 | #define RXFIFO_THR1_NORMAL 0x00080002 | |
152 | #define RXFIFO_THR1_OOB 0x01800003 | |
153 | ||
154 | /* PLA_RXFIFO_CTRL1 */ | |
155 | #define RXFIFO_THR2_FULL 0x00000060 | |
156 | #define RXFIFO_THR2_HIGH 0x00000038 | |
157 | #define RXFIFO_THR2_OOB 0x0000004a | |
43779f8d | 158 | #define RXFIFO_THR2_NORMAL 0x00a0 |
ac718b69 | 159 | |
160 | /* PLA_RXFIFO_CTRL2 */ | |
161 | #define RXFIFO_THR3_FULL 0x00000078 | |
162 | #define RXFIFO_THR3_HIGH 0x00000048 | |
163 | #define RXFIFO_THR3_OOB 0x0000005a | |
43779f8d | 164 | #define RXFIFO_THR3_NORMAL 0x0110 |
ac718b69 | 165 | |
166 | /* PLA_TXFIFO_CTRL */ | |
167 | #define TXFIFO_THR_NORMAL 0x00400008 | |
43779f8d | 168 | #define TXFIFO_THR_NORMAL2 0x01000008 |
ac718b69 | 169 | |
170 | /* PLA_FMC */ | |
171 | #define FMC_FCR_MCU_EN 0x0001 | |
172 | ||
173 | /* PLA_EEEP_CR */ | |
174 | #define EEEP_CR_EEEP_TX 0x0002 | |
175 | ||
43779f8d | 176 | /* PLA_WDT6_CTRL */ |
177 | #define WDT6_SET_MODE 0x0010 | |
178 | ||
ac718b69 | 179 | /* PLA_TCR0 */ |
180 | #define TCR0_TX_EMPTY 0x0800 | |
181 | #define TCR0_AUTO_FIFO 0x0080 | |
182 | ||
183 | /* PLA_TCR1 */ | |
184 | #define VERSION_MASK 0x7cf0 | |
185 | ||
69b4b7a4 | 186 | /* PLA_MTPS */ |
187 | #define MTPS_JUMBO (12 * 1024 / 64) | |
188 | #define MTPS_DEFAULT (6 * 1024 / 64) | |
189 | ||
4f1d4d54 | 190 | /* PLA_RSTTALLY */ |
191 | #define TALLY_RESET 0x0001 | |
192 | ||
ac718b69 | 193 | /* PLA_CR */ |
194 | #define CR_RST 0x10 | |
195 | #define CR_RE 0x08 | |
196 | #define CR_TE 0x04 | |
197 | ||
198 | /* PLA_CRWECR */ | |
199 | #define CRWECR_NORAML 0x00 | |
200 | #define CRWECR_CONFIG 0xc0 | |
201 | ||
202 | /* PLA_OOB_CTRL */ | |
203 | #define NOW_IS_OOB 0x80 | |
204 | #define TXFIFO_EMPTY 0x20 | |
205 | #define RXFIFO_EMPTY 0x10 | |
206 | #define LINK_LIST_READY 0x02 | |
207 | #define DIS_MCU_CLROOB 0x01 | |
208 | #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) | |
209 | ||
210 | /* PLA_MISC_1 */ | |
211 | #define RXDY_GATED_EN 0x0008 | |
212 | ||
213 | /* PLA_SFF_STS_7 */ | |
214 | #define RE_INIT_LL 0x8000 | |
215 | #define MCU_BORW_EN 0x4000 | |
216 | ||
217 | /* PLA_CPCR */ | |
218 | #define CPCR_RX_VLAN 0x0040 | |
219 | ||
220 | /* PLA_CFG_WOL */ | |
221 | #define MAGIC_EN 0x0001 | |
222 | ||
43779f8d | 223 | /* PLA_TEREDO_CFG */ |
224 | #define TEREDO_SEL 0x8000 | |
225 | #define TEREDO_WAKE_MASK 0x7f00 | |
226 | #define TEREDO_RS_EVENT_MASK 0x00fe | |
227 | #define OOB_TEREDO_EN 0x0001 | |
228 | ||
ac718b69 | 229 | /* PAL_BDC_CR */ |
230 | #define ALDPS_PROXY_MODE 0x0001 | |
231 | ||
21ff2e89 | 232 | /* PLA_CONFIG34 */ |
233 | #define LINK_ON_WAKE_EN 0x0010 | |
234 | #define LINK_OFF_WAKE_EN 0x0008 | |
235 | ||
ac718b69 | 236 | /* PLA_CONFIG5 */ |
21ff2e89 | 237 | #define BWF_EN 0x0040 |
238 | #define MWF_EN 0x0020 | |
239 | #define UWF_EN 0x0010 | |
ac718b69 | 240 | #define LAN_WAKE_EN 0x0002 |
241 | ||
242 | /* PLA_LED_FEATURE */ | |
243 | #define LED_MODE_MASK 0x0700 | |
244 | ||
245 | /* PLA_PHY_PWR */ | |
246 | #define TX_10M_IDLE_EN 0x0080 | |
247 | #define PFM_PWM_SWITCH 0x0040 | |
248 | ||
249 | /* PLA_MAC_PWR_CTRL */ | |
250 | #define D3_CLK_GATED_EN 0x00004000 | |
251 | #define MCU_CLK_RATIO 0x07010f07 | |
252 | #define MCU_CLK_RATIO_MASK 0x0f0f0f0f | |
43779f8d | 253 | #define ALDPS_SPDWN_RATIO 0x0f87 |
254 | ||
255 | /* PLA_MAC_PWR_CTRL2 */ | |
256 | #define EEE_SPDWN_RATIO 0x8007 | |
257 | ||
258 | /* PLA_MAC_PWR_CTRL3 */ | |
259 | #define PKT_AVAIL_SPDWN_EN 0x0100 | |
260 | #define SUSPEND_SPDWN_EN 0x0004 | |
261 | #define U1U2_SPDWN_EN 0x0002 | |
262 | #define L1_SPDWN_EN 0x0001 | |
263 | ||
264 | /* PLA_MAC_PWR_CTRL4 */ | |
265 | #define PWRSAVE_SPDWN_EN 0x1000 | |
266 | #define RXDV_SPDWN_EN 0x0800 | |
267 | #define TX10MIDLE_EN 0x0100 | |
268 | #define TP100_SPDWN_EN 0x0020 | |
269 | #define TP500_SPDWN_EN 0x0010 | |
270 | #define TP1000_SPDWN_EN 0x0008 | |
271 | #define EEE_SPDWN_EN 0x0001 | |
ac718b69 | 272 | |
273 | /* PLA_GPHY_INTR_IMR */ | |
274 | #define GPHY_STS_MSK 0x0001 | |
275 | #define SPEED_DOWN_MSK 0x0002 | |
276 | #define SPDWN_RXDV_MSK 0x0004 | |
277 | #define SPDWN_LINKCHG_MSK 0x0008 | |
278 | ||
279 | /* PLA_PHYAR */ | |
280 | #define PHYAR_FLAG 0x80000000 | |
281 | ||
282 | /* PLA_EEE_CR */ | |
283 | #define EEE_RX_EN 0x0001 | |
284 | #define EEE_TX_EN 0x0002 | |
285 | ||
43779f8d | 286 | /* PLA_BOOT_CTRL */ |
287 | #define AUTOLOAD_DONE 0x0002 | |
288 | ||
ac718b69 | 289 | /* USB_DEV_STAT */ |
290 | #define STAT_SPEED_MASK 0x0006 | |
291 | #define STAT_SPEED_HIGH 0x0000 | |
a3cc465d | 292 | #define STAT_SPEED_FULL 0x0002 |
ac718b69 | 293 | |
294 | /* USB_TX_AGG */ | |
295 | #define TX_AGG_MAX_THRESHOLD 0x03 | |
296 | ||
297 | /* USB_RX_BUF_TH */ | |
43779f8d | 298 | #define RX_THR_SUPPER 0x0c350180 |
8e1f51bd | 299 | #define RX_THR_HIGH 0x7a120180 |
43779f8d | 300 | #define RX_THR_SLOW 0xffff0180 |
ac718b69 | 301 | |
302 | /* USB_TX_DMA */ | |
303 | #define TEST_MODE_DISABLE 0x00000001 | |
304 | #define TX_SIZE_ADJUST1 0x00000100 | |
305 | ||
306 | /* USB_UPS_CTRL */ | |
307 | #define POWER_CUT 0x0100 | |
308 | ||
309 | /* USB_PM_CTRL_STATUS */ | |
8e1f51bd | 310 | #define RESUME_INDICATE 0x0001 |
ac718b69 | 311 | |
312 | /* USB_USB_CTRL */ | |
313 | #define RX_AGG_DISABLE 0x0010 | |
314 | ||
43779f8d | 315 | /* USB_U2P3_CTRL */ |
316 | #define U2P3_ENABLE 0x0001 | |
317 | ||
318 | /* USB_POWER_CUT */ | |
319 | #define PWR_EN 0x0001 | |
320 | #define PHASE2_EN 0x0008 | |
321 | ||
322 | /* USB_MISC_0 */ | |
323 | #define PCUT_STATUS 0x0001 | |
324 | ||
325 | /* USB_RX_EARLY_AGG */ | |
326 | #define EARLY_AGG_SUPPER 0x0e832981 | |
327 | #define EARLY_AGG_HIGH 0x0e837a12 | |
328 | #define EARLY_AGG_SLOW 0x0e83ffff | |
329 | ||
330 | /* USB_WDT11_CTRL */ | |
331 | #define TIMER11_EN 0x0001 | |
332 | ||
333 | /* USB_LPM_CTRL */ | |
334 | #define LPM_TIMER_MASK 0x0c | |
335 | #define LPM_TIMER_500MS 0x04 /* 500 ms */ | |
336 | #define LPM_TIMER_500US 0x0c /* 500 us */ | |
337 | ||
338 | /* USB_AFE_CTRL2 */ | |
339 | #define SEN_VAL_MASK 0xf800 | |
340 | #define SEN_VAL_NORMAL 0xa000 | |
341 | #define SEL_RXIDLE 0x0100 | |
342 | ||
ac718b69 | 343 | /* OCP_ALDPS_CONFIG */ |
344 | #define ENPWRSAVE 0x8000 | |
345 | #define ENPDNPS 0x0200 | |
346 | #define LINKENA 0x0100 | |
347 | #define DIS_SDSAVE 0x0010 | |
348 | ||
43779f8d | 349 | /* OCP_PHY_STATUS */ |
350 | #define PHY_STAT_MASK 0x0007 | |
351 | #define PHY_STAT_LAN_ON 3 | |
352 | #define PHY_STAT_PWRDN 5 | |
353 | ||
354 | /* OCP_POWER_CFG */ | |
355 | #define EEE_CLKDIV_EN 0x8000 | |
356 | #define EN_ALDPS 0x0004 | |
357 | #define EN_10M_PLLOFF 0x0001 | |
358 | ||
ac718b69 | 359 | /* OCP_EEE_CONFIG1 */ |
360 | #define RG_TXLPI_MSK_HFDUP 0x8000 | |
361 | #define RG_MATCLR_EN 0x4000 | |
362 | #define EEE_10_CAP 0x2000 | |
363 | #define EEE_NWAY_EN 0x1000 | |
364 | #define TX_QUIET_EN 0x0200 | |
365 | #define RX_QUIET_EN 0x0100 | |
4c4a6b1b | 366 | #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ |
ac718b69 | 367 | #define RG_RXLPI_MSK_HFDUP 0x0008 |
368 | #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ | |
369 | ||
370 | /* OCP_EEE_CONFIG2 */ | |
371 | #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ | |
372 | #define RG_DACQUIET_EN 0x0400 | |
373 | #define RG_LDVQUIET_EN 0x0200 | |
374 | #define RG_CKRSEL 0x0020 | |
375 | #define RG_EEEPRG_EN 0x0010 | |
376 | ||
377 | /* OCP_EEE_CONFIG3 */ | |
4c4a6b1b | 378 | #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ |
ac718b69 | 379 | #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ |
380 | #define MSK_PH 0x0006 /* bit 0 ~ 3 */ | |
381 | ||
382 | /* OCP_EEE_AR */ | |
383 | /* bit[15:14] function */ | |
384 | #define FUN_ADDR 0x0000 | |
385 | #define FUN_DATA 0x4000 | |
386 | /* bit[4:0] device addr */ | |
ac718b69 | 387 | |
43779f8d | 388 | /* OCP_EEE_CFG */ |
389 | #define CTAP_SHORT_EN 0x0040 | |
390 | #define EEE10_EN 0x0010 | |
391 | ||
392 | /* OCP_DOWN_SPEED */ | |
393 | #define EN_10M_BGOFF 0x0080 | |
394 | ||
43779f8d | 395 | /* OCP_ADC_CFG */ |
396 | #define CKADSEL_L 0x0100 | |
397 | #define ADC_EN 0x0080 | |
398 | #define EN_EMI_L 0x0040 | |
399 | ||
400 | /* SRAM_LPF_CFG */ | |
401 | #define LPF_AUTO_TUNE 0x8000 | |
402 | ||
403 | /* SRAM_10M_AMP1 */ | |
404 | #define GDAC_IB_UPALL 0x0008 | |
405 | ||
406 | /* SRAM_10M_AMP2 */ | |
407 | #define AMP_DN 0x0200 | |
408 | ||
409 | /* SRAM_IMPEDANCE */ | |
410 | #define RX_DRIVING_MASK 0x6000 | |
411 | ||
ac718b69 | 412 | enum rtl_register_content { |
43779f8d | 413 | _1000bps = 0x10, |
ac718b69 | 414 | _100bps = 0x08, |
415 | _10bps = 0x04, | |
416 | LINK_STATUS = 0x02, | |
417 | FULL_DUP = 0x01, | |
418 | }; | |
419 | ||
1764bcd9 | 420 | #define RTL8152_MAX_TX 4 |
ebc2ec48 | 421 | #define RTL8152_MAX_RX 10 |
40a82917 | 422 | #define INTBUFSIZE 2 |
8e1f51bd | 423 | #define CRC_SIZE 4 |
424 | #define TX_ALIGN 4 | |
425 | #define RX_ALIGN 8 | |
40a82917 | 426 | |
427 | #define INTR_LINK 0x0004 | |
ebc2ec48 | 428 | |
ac718b69 | 429 | #define RTL8152_REQT_READ 0xc0 |
430 | #define RTL8152_REQT_WRITE 0x40 | |
431 | #define RTL8152_REQ_GET_REGS 0x05 | |
432 | #define RTL8152_REQ_SET_REGS 0x05 | |
433 | ||
434 | #define BYTE_EN_DWORD 0xff | |
435 | #define BYTE_EN_WORD 0x33 | |
436 | #define BYTE_EN_BYTE 0x11 | |
437 | #define BYTE_EN_SIX_BYTES 0x3f | |
438 | #define BYTE_EN_START_MASK 0x0f | |
439 | #define BYTE_EN_END_MASK 0xf0 | |
440 | ||
69b4b7a4 | 441 | #define RTL8153_MAX_PACKET 9216 /* 9K */ |
442 | #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN) | |
ac718b69 | 443 | #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) |
69b4b7a4 | 444 | #define RTL8153_RMS RTL8153_MAX_PACKET |
b8125404 | 445 | #define RTL8152_TX_TIMEOUT (5 * HZ) |
ac718b69 | 446 | |
447 | /* rtl8152 flags */ | |
448 | enum rtl8152_flags { | |
449 | RTL8152_UNPLUG = 0, | |
ac718b69 | 450 | RTL8152_SET_RX_MODE, |
40a82917 | 451 | WORK_ENABLE, |
452 | RTL8152_LINK_CHG, | |
9a4be1bd | 453 | SELECTIVE_SUSPEND, |
aa66a5f1 | 454 | PHY_RESET, |
0c3121fc | 455 | SCHEDULE_TASKLET, |
ac718b69 | 456 | }; |
457 | ||
458 | /* Define these values to match your device */ | |
459 | #define VENDOR_ID_REALTEK 0x0bda | |
460 | #define PRODUCT_ID_RTL8152 0x8152 | |
43779f8d | 461 | #define PRODUCT_ID_RTL8153 0x8153 |
462 | ||
463 | #define VENDOR_ID_SAMSUNG 0x04e8 | |
464 | #define PRODUCT_ID_SAMSUNG 0xa101 | |
ac718b69 | 465 | |
466 | #define MCU_TYPE_PLA 0x0100 | |
467 | #define MCU_TYPE_USB 0x0000 | |
468 | ||
c7de7dec | 469 | #define REALTEK_USB_DEVICE(vend, prod) \ |
470 | USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC) | |
471 | ||
4f1d4d54 | 472 | struct tally_counter { |
473 | __le64 tx_packets; | |
474 | __le64 rx_packets; | |
475 | __le64 tx_errors; | |
476 | __le32 rx_errors; | |
477 | __le16 rx_missed; | |
478 | __le16 align_errors; | |
479 | __le32 tx_one_collision; | |
480 | __le32 tx_multi_collision; | |
481 | __le64 rx_unicast; | |
482 | __le64 rx_broadcast; | |
483 | __le32 rx_multicast; | |
484 | __le16 tx_aborted; | |
485 | __le16 tx_underun; | |
486 | }; | |
487 | ||
ac718b69 | 488 | struct rx_desc { |
500b6d7e | 489 | __le32 opts1; |
ac718b69 | 490 | #define RX_LEN_MASK 0x7fff |
565cab0a | 491 | |
500b6d7e | 492 | __le32 opts2; |
565cab0a | 493 | #define RD_UDP_CS (1 << 23) |
494 | #define RD_TCP_CS (1 << 22) | |
6128d1bb | 495 | #define RD_IPV6_CS (1 << 20) |
565cab0a | 496 | #define RD_IPV4_CS (1 << 19) |
497 | ||
500b6d7e | 498 | __le32 opts3; |
565cab0a | 499 | #define IPF (1 << 23) /* IP checksum fail */ |
500 | #define UDPF (1 << 22) /* UDP checksum fail */ | |
501 | #define TCPF (1 << 21) /* TCP checksum fail */ | |
c5554298 | 502 | #define RX_VLAN_TAG (1 << 16) |
565cab0a | 503 | |
500b6d7e | 504 | __le32 opts4; |
505 | __le32 opts5; | |
506 | __le32 opts6; | |
ac718b69 | 507 | }; |
508 | ||
509 | struct tx_desc { | |
500b6d7e | 510 | __le32 opts1; |
ac718b69 | 511 | #define TX_FS (1 << 31) /* First segment of a packet */ |
512 | #define TX_LS (1 << 30) /* Final segment of a packet */ | |
60c89071 | 513 | #define GTSENDV4 (1 << 28) |
6128d1bb | 514 | #define GTSENDV6 (1 << 27) |
60c89071 | 515 | #define GTTCPHO_SHIFT 18 |
6128d1bb | 516 | #define GTTCPHO_MAX 0x7fU |
60c89071 | 517 | #define TX_LEN_MAX 0x3ffffU |
5bd23881 | 518 | |
500b6d7e | 519 | __le32 opts2; |
5bd23881 | 520 | #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */ |
521 | #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */ | |
522 | #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */ | |
523 | #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */ | |
60c89071 | 524 | #define MSS_SHIFT 17 |
525 | #define MSS_MAX 0x7ffU | |
526 | #define TCPHO_SHIFT 17 | |
6128d1bb | 527 | #define TCPHO_MAX 0x7ffU |
c5554298 | 528 | #define TX_VLAN_TAG (1 << 16) |
ac718b69 | 529 | }; |
530 | ||
dff4e8ad | 531 | struct r8152; |
532 | ||
ebc2ec48 | 533 | struct rx_agg { |
534 | struct list_head list; | |
535 | struct urb *urb; | |
dff4e8ad | 536 | struct r8152 *context; |
ebc2ec48 | 537 | void *buffer; |
538 | void *head; | |
539 | }; | |
540 | ||
541 | struct tx_agg { | |
542 | struct list_head list; | |
543 | struct urb *urb; | |
dff4e8ad | 544 | struct r8152 *context; |
ebc2ec48 | 545 | void *buffer; |
546 | void *head; | |
547 | u32 skb_num; | |
548 | u32 skb_len; | |
549 | }; | |
550 | ||
ac718b69 | 551 | struct r8152 { |
552 | unsigned long flags; | |
553 | struct usb_device *udev; | |
554 | struct tasklet_struct tl; | |
40a82917 | 555 | struct usb_interface *intf; |
ac718b69 | 556 | struct net_device *netdev; |
40a82917 | 557 | struct urb *intr_urb; |
ebc2ec48 | 558 | struct tx_agg tx_info[RTL8152_MAX_TX]; |
559 | struct rx_agg rx_info[RTL8152_MAX_RX]; | |
560 | struct list_head rx_done, tx_free; | |
561 | struct sk_buff_head tx_queue; | |
562 | spinlock_t rx_lock, tx_lock; | |
ac718b69 | 563 | struct delayed_work schedule; |
564 | struct mii_if_info mii; | |
c81229c9 | 565 | |
566 | struct rtl_ops { | |
567 | void (*init)(struct r8152 *); | |
568 | int (*enable)(struct r8152 *); | |
569 | void (*disable)(struct r8152 *); | |
7e9da481 | 570 | void (*up)(struct r8152 *); |
c81229c9 | 571 | void (*down)(struct r8152 *); |
572 | void (*unload)(struct r8152 *); | |
573 | } rtl_ops; | |
574 | ||
40a82917 | 575 | int intr_interval; |
21ff2e89 | 576 | u32 saved_wolopts; |
ac718b69 | 577 | u32 msg_enable; |
dd1b119c | 578 | u32 tx_qlen; |
ac718b69 | 579 | u16 ocp_base; |
40a82917 | 580 | u8 *intr_buff; |
ac718b69 | 581 | u8 version; |
582 | u8 speed; | |
583 | }; | |
584 | ||
585 | enum rtl_version { | |
586 | RTL_VER_UNKNOWN = 0, | |
587 | RTL_VER_01, | |
43779f8d | 588 | RTL_VER_02, |
589 | RTL_VER_03, | |
590 | RTL_VER_04, | |
591 | RTL_VER_05, | |
592 | RTL_VER_MAX | |
ac718b69 | 593 | }; |
594 | ||
60c89071 | 595 | enum tx_csum_stat { |
596 | TX_CSUM_SUCCESS = 0, | |
597 | TX_CSUM_TSO, | |
598 | TX_CSUM_NONE | |
599 | }; | |
600 | ||
ac718b69 | 601 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
602 | * The RTL chips use a 64 element hash table based on the Ethernet CRC. | |
603 | */ | |
604 | static const int multicast_filter_limit = 32; | |
52aec126 | 605 | static unsigned int agg_buf_sz = 16384; |
ac718b69 | 606 | |
52aec126 | 607 | #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ |
60c89071 | 608 | VLAN_ETH_HLEN - VLAN_HLEN) |
609 | ||
ac718b69 | 610 | static |
611 | int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
612 | { | |
31787f53 | 613 | int ret; |
614 | void *tmp; | |
615 | ||
616 | tmp = kmalloc(size, GFP_KERNEL); | |
617 | if (!tmp) | |
618 | return -ENOMEM; | |
619 | ||
620 | ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), | |
b209af99 | 621 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, |
622 | value, index, tmp, size, 500); | |
31787f53 | 623 | |
624 | memcpy(data, tmp, size); | |
625 | kfree(tmp); | |
626 | ||
627 | return ret; | |
ac718b69 | 628 | } |
629 | ||
630 | static | |
631 | int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
632 | { | |
31787f53 | 633 | int ret; |
634 | void *tmp; | |
635 | ||
c4438f03 | 636 | tmp = kmemdup(data, size, GFP_KERNEL); |
31787f53 | 637 | if (!tmp) |
638 | return -ENOMEM; | |
639 | ||
31787f53 | 640 | ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), |
b209af99 | 641 | RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, |
642 | value, index, tmp, size, 500); | |
31787f53 | 643 | |
644 | kfree(tmp); | |
db8515ef | 645 | |
31787f53 | 646 | return ret; |
ac718b69 | 647 | } |
648 | ||
649 | static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, | |
b209af99 | 650 | void *data, u16 type) |
ac718b69 | 651 | { |
45f4a19f | 652 | u16 limit = 64; |
653 | int ret = 0; | |
ac718b69 | 654 | |
655 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
656 | return -ENODEV; | |
657 | ||
658 | /* both size and indix must be 4 bytes align */ | |
659 | if ((size & 3) || !size || (index & 3) || !data) | |
660 | return -EPERM; | |
661 | ||
662 | if ((u32)index + (u32)size > 0xffff) | |
663 | return -EPERM; | |
664 | ||
665 | while (size) { | |
666 | if (size > limit) { | |
667 | ret = get_registers(tp, index, type, limit, data); | |
668 | if (ret < 0) | |
669 | break; | |
670 | ||
671 | index += limit; | |
672 | data += limit; | |
673 | size -= limit; | |
674 | } else { | |
675 | ret = get_registers(tp, index, type, size, data); | |
676 | if (ret < 0) | |
677 | break; | |
678 | ||
679 | index += size; | |
680 | data += size; | |
681 | size = 0; | |
682 | break; | |
683 | } | |
684 | } | |
685 | ||
686 | return ret; | |
687 | } | |
688 | ||
689 | static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, | |
b209af99 | 690 | u16 size, void *data, u16 type) |
ac718b69 | 691 | { |
45f4a19f | 692 | int ret; |
693 | u16 byteen_start, byteen_end, byen; | |
694 | u16 limit = 512; | |
ac718b69 | 695 | |
696 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
697 | return -ENODEV; | |
698 | ||
699 | /* both size and indix must be 4 bytes align */ | |
700 | if ((size & 3) || !size || (index & 3) || !data) | |
701 | return -EPERM; | |
702 | ||
703 | if ((u32)index + (u32)size > 0xffff) | |
704 | return -EPERM; | |
705 | ||
706 | byteen_start = byteen & BYTE_EN_START_MASK; | |
707 | byteen_end = byteen & BYTE_EN_END_MASK; | |
708 | ||
709 | byen = byteen_start | (byteen_start << 4); | |
710 | ret = set_registers(tp, index, type | byen, 4, data); | |
711 | if (ret < 0) | |
712 | goto error1; | |
713 | ||
714 | index += 4; | |
715 | data += 4; | |
716 | size -= 4; | |
717 | ||
718 | if (size) { | |
719 | size -= 4; | |
720 | ||
721 | while (size) { | |
722 | if (size > limit) { | |
723 | ret = set_registers(tp, index, | |
b209af99 | 724 | type | BYTE_EN_DWORD, |
725 | limit, data); | |
ac718b69 | 726 | if (ret < 0) |
727 | goto error1; | |
728 | ||
729 | index += limit; | |
730 | data += limit; | |
731 | size -= limit; | |
732 | } else { | |
733 | ret = set_registers(tp, index, | |
b209af99 | 734 | type | BYTE_EN_DWORD, |
735 | size, data); | |
ac718b69 | 736 | if (ret < 0) |
737 | goto error1; | |
738 | ||
739 | index += size; | |
740 | data += size; | |
741 | size = 0; | |
742 | break; | |
743 | } | |
744 | } | |
745 | ||
746 | byen = byteen_end | (byteen_end >> 4); | |
747 | ret = set_registers(tp, index, type | byen, 4, data); | |
748 | if (ret < 0) | |
749 | goto error1; | |
750 | } | |
751 | ||
752 | error1: | |
753 | return ret; | |
754 | } | |
755 | ||
756 | static inline | |
757 | int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
758 | { | |
759 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); | |
760 | } | |
761 | ||
762 | static inline | |
763 | int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
764 | { | |
765 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); | |
766 | } | |
767 | ||
768 | static inline | |
769 | int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
770 | { | |
771 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); | |
772 | } | |
773 | ||
774 | static inline | |
775 | int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
776 | { | |
777 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); | |
778 | } | |
779 | ||
780 | static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) | |
781 | { | |
c8826de8 | 782 | __le32 data; |
ac718b69 | 783 | |
c8826de8 | 784 | generic_ocp_read(tp, index, sizeof(data), &data, type); |
ac718b69 | 785 | |
786 | return __le32_to_cpu(data); | |
787 | } | |
788 | ||
789 | static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) | |
790 | { | |
c8826de8 | 791 | __le32 tmp = __cpu_to_le32(data); |
792 | ||
793 | generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); | |
ac718b69 | 794 | } |
795 | ||
796 | static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) | |
797 | { | |
798 | u32 data; | |
c8826de8 | 799 | __le32 tmp; |
ac718b69 | 800 | u8 shift = index & 2; |
801 | ||
802 | index &= ~3; | |
803 | ||
c8826de8 | 804 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 805 | |
c8826de8 | 806 | data = __le32_to_cpu(tmp); |
ac718b69 | 807 | data >>= (shift * 8); |
808 | data &= 0xffff; | |
809 | ||
810 | return (u16)data; | |
811 | } | |
812 | ||
813 | static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) | |
814 | { | |
c8826de8 | 815 | u32 mask = 0xffff; |
816 | __le32 tmp; | |
ac718b69 | 817 | u16 byen = BYTE_EN_WORD; |
818 | u8 shift = index & 2; | |
819 | ||
820 | data &= mask; | |
821 | ||
822 | if (index & 2) { | |
823 | byen <<= shift; | |
824 | mask <<= (shift * 8); | |
825 | data <<= (shift * 8); | |
826 | index &= ~3; | |
827 | } | |
828 | ||
c8826de8 | 829 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 830 | |
c8826de8 | 831 | data |= __le32_to_cpu(tmp) & ~mask; |
832 | tmp = __cpu_to_le32(data); | |
ac718b69 | 833 | |
c8826de8 | 834 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 835 | } |
836 | ||
837 | static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) | |
838 | { | |
839 | u32 data; | |
c8826de8 | 840 | __le32 tmp; |
ac718b69 | 841 | u8 shift = index & 3; |
842 | ||
843 | index &= ~3; | |
844 | ||
c8826de8 | 845 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 846 | |
c8826de8 | 847 | data = __le32_to_cpu(tmp); |
ac718b69 | 848 | data >>= (shift * 8); |
849 | data &= 0xff; | |
850 | ||
851 | return (u8)data; | |
852 | } | |
853 | ||
854 | static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) | |
855 | { | |
c8826de8 | 856 | u32 mask = 0xff; |
857 | __le32 tmp; | |
ac718b69 | 858 | u16 byen = BYTE_EN_BYTE; |
859 | u8 shift = index & 3; | |
860 | ||
861 | data &= mask; | |
862 | ||
863 | if (index & 3) { | |
864 | byen <<= shift; | |
865 | mask <<= (shift * 8); | |
866 | data <<= (shift * 8); | |
867 | index &= ~3; | |
868 | } | |
869 | ||
c8826de8 | 870 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 871 | |
c8826de8 | 872 | data |= __le32_to_cpu(tmp) & ~mask; |
873 | tmp = __cpu_to_le32(data); | |
ac718b69 | 874 | |
c8826de8 | 875 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 876 | } |
877 | ||
ac244d3e | 878 | static u16 ocp_reg_read(struct r8152 *tp, u16 addr) |
e3fe0b1a | 879 | { |
880 | u16 ocp_base, ocp_index; | |
881 | ||
882 | ocp_base = addr & 0xf000; | |
883 | if (ocp_base != tp->ocp_base) { | |
884 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
885 | tp->ocp_base = ocp_base; | |
886 | } | |
887 | ||
888 | ocp_index = (addr & 0x0fff) | 0xb000; | |
ac244d3e | 889 | return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); |
e3fe0b1a | 890 | } |
891 | ||
ac244d3e | 892 | static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) |
ac718b69 | 893 | { |
ac244d3e | 894 | u16 ocp_base, ocp_index; |
ac718b69 | 895 | |
ac244d3e | 896 | ocp_base = addr & 0xf000; |
897 | if (ocp_base != tp->ocp_base) { | |
898 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
899 | tp->ocp_base = ocp_base; | |
ac718b69 | 900 | } |
ac244d3e | 901 | |
902 | ocp_index = (addr & 0x0fff) | 0xb000; | |
903 | ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); | |
ac718b69 | 904 | } |
905 | ||
ac244d3e | 906 | static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) |
ac718b69 | 907 | { |
ac244d3e | 908 | ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); |
909 | } | |
ac718b69 | 910 | |
ac244d3e | 911 | static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) |
912 | { | |
913 | return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); | |
ac718b69 | 914 | } |
915 | ||
43779f8d | 916 | static void sram_write(struct r8152 *tp, u16 addr, u16 data) |
917 | { | |
918 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
919 | ocp_reg_write(tp, OCP_SRAM_DATA, data); | |
920 | } | |
921 | ||
922 | static u16 sram_read(struct r8152 *tp, u16 addr) | |
923 | { | |
924 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
925 | return ocp_reg_read(tp, OCP_SRAM_DATA); | |
926 | } | |
927 | ||
ac718b69 | 928 | static int read_mii_word(struct net_device *netdev, int phy_id, int reg) |
929 | { | |
930 | struct r8152 *tp = netdev_priv(netdev); | |
9a4be1bd | 931 | int ret; |
ac718b69 | 932 | |
6871438c | 933 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
934 | return -ENODEV; | |
935 | ||
ac718b69 | 936 | if (phy_id != R8152_PHY_ID) |
937 | return -EINVAL; | |
938 | ||
9a4be1bd | 939 | ret = usb_autopm_get_interface(tp->intf); |
940 | if (ret < 0) | |
941 | goto out; | |
942 | ||
943 | ret = r8152_mdio_read(tp, reg); | |
944 | ||
945 | usb_autopm_put_interface(tp->intf); | |
946 | ||
947 | out: | |
948 | return ret; | |
ac718b69 | 949 | } |
950 | ||
951 | static | |
952 | void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) | |
953 | { | |
954 | struct r8152 *tp = netdev_priv(netdev); | |
955 | ||
6871438c | 956 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
957 | return; | |
958 | ||
ac718b69 | 959 | if (phy_id != R8152_PHY_ID) |
960 | return; | |
961 | ||
9a4be1bd | 962 | if (usb_autopm_get_interface(tp->intf) < 0) |
963 | return; | |
964 | ||
ac718b69 | 965 | r8152_mdio_write(tp, reg, val); |
9a4be1bd | 966 | |
967 | usb_autopm_put_interface(tp->intf); | |
ac718b69 | 968 | } |
969 | ||
b209af99 | 970 | static int |
971 | r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); | |
ebc2ec48 | 972 | |
8ba789ab | 973 | static int rtl8152_set_mac_address(struct net_device *netdev, void *p) |
974 | { | |
975 | struct r8152 *tp = netdev_priv(netdev); | |
976 | struct sockaddr *addr = p; | |
977 | ||
978 | if (!is_valid_ether_addr(addr->sa_data)) | |
979 | return -EADDRNOTAVAIL; | |
980 | ||
981 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
982 | ||
983 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
984 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); | |
985 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
986 | ||
987 | return 0; | |
988 | } | |
989 | ||
179bb6d7 | 990 | static int set_ethernet_addr(struct r8152 *tp) |
ac718b69 | 991 | { |
992 | struct net_device *dev = tp->netdev; | |
179bb6d7 | 993 | struct sockaddr sa; |
8a91c824 | 994 | int ret; |
ac718b69 | 995 | |
8a91c824 | 996 | if (tp->version == RTL_VER_01) |
179bb6d7 | 997 | ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data); |
8a91c824 | 998 | else |
179bb6d7 | 999 | ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data); |
8a91c824 | 1000 | |
1001 | if (ret < 0) { | |
179bb6d7 | 1002 | netif_err(tp, probe, dev, "Get ether addr fail\n"); |
1003 | } else if (!is_valid_ether_addr(sa.sa_data)) { | |
1004 | netif_err(tp, probe, dev, "Invalid ether addr %pM\n", | |
1005 | sa.sa_data); | |
1006 | eth_hw_addr_random(dev); | |
1007 | ether_addr_copy(sa.sa_data, dev->dev_addr); | |
1008 | ret = rtl8152_set_mac_address(dev, &sa); | |
1009 | netif_info(tp, probe, dev, "Random ether addr %pM\n", | |
1010 | sa.sa_data); | |
8a91c824 | 1011 | } else { |
179bb6d7 | 1012 | if (tp->version == RTL_VER_01) |
1013 | ether_addr_copy(dev->dev_addr, sa.sa_data); | |
1014 | else | |
1015 | ret = rtl8152_set_mac_address(dev, &sa); | |
ac718b69 | 1016 | } |
179bb6d7 | 1017 | |
1018 | return ret; | |
ac718b69 | 1019 | } |
1020 | ||
ac718b69 | 1021 | static void read_bulk_callback(struct urb *urb) |
1022 | { | |
ac718b69 | 1023 | struct net_device *netdev; |
ac718b69 | 1024 | int status = urb->status; |
ebc2ec48 | 1025 | struct rx_agg *agg; |
1026 | struct r8152 *tp; | |
ac718b69 | 1027 | int result; |
ac718b69 | 1028 | |
ebc2ec48 | 1029 | agg = urb->context; |
1030 | if (!agg) | |
1031 | return; | |
1032 | ||
1033 | tp = agg->context; | |
ac718b69 | 1034 | if (!tp) |
1035 | return; | |
ebc2ec48 | 1036 | |
ac718b69 | 1037 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1038 | return; | |
ebc2ec48 | 1039 | |
1040 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1041 | return; | |
1042 | ||
ac718b69 | 1043 | netdev = tp->netdev; |
7559fb2f | 1044 | |
1045 | /* When link down, the driver would cancel all bulks. */ | |
1046 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1047 | if (!netif_carrier_ok(netdev)) |
ac718b69 | 1048 | return; |
1049 | ||
9a4be1bd | 1050 | usb_mark_last_busy(tp->udev); |
1051 | ||
ac718b69 | 1052 | switch (status) { |
1053 | case 0: | |
ebc2ec48 | 1054 | if (urb->actual_length < ETH_ZLEN) |
1055 | break; | |
1056 | ||
2685d410 | 1057 | spin_lock(&tp->rx_lock); |
ebc2ec48 | 1058 | list_add_tail(&agg->list, &tp->rx_done); |
2685d410 | 1059 | spin_unlock(&tp->rx_lock); |
ebc2ec48 | 1060 | tasklet_schedule(&tp->tl); |
1061 | return; | |
ac718b69 | 1062 | case -ESHUTDOWN: |
1063 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
1064 | netif_device_detach(tp->netdev); | |
ebc2ec48 | 1065 | return; |
ac718b69 | 1066 | case -ENOENT: |
1067 | return; /* the urb is in unlink state */ | |
1068 | case -ETIME: | |
4a8deae2 HW |
1069 | if (net_ratelimit()) |
1070 | netdev_warn(netdev, "maybe reset is needed?\n"); | |
ebc2ec48 | 1071 | break; |
ac718b69 | 1072 | default: |
4a8deae2 HW |
1073 | if (net_ratelimit()) |
1074 | netdev_warn(netdev, "Rx status %d\n", status); | |
ebc2ec48 | 1075 | break; |
ac718b69 | 1076 | } |
1077 | ||
ebc2ec48 | 1078 | result = r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ac718b69 | 1079 | if (result == -ENODEV) { |
1080 | netif_device_detach(tp->netdev); | |
1081 | } else if (result) { | |
2685d410 | 1082 | spin_lock(&tp->rx_lock); |
ebc2ec48 | 1083 | list_add_tail(&agg->list, &tp->rx_done); |
2685d410 | 1084 | spin_unlock(&tp->rx_lock); |
ebc2ec48 | 1085 | tasklet_schedule(&tp->tl); |
ac718b69 | 1086 | } |
ac718b69 | 1087 | } |
1088 | ||
ebc2ec48 | 1089 | static void write_bulk_callback(struct urb *urb) |
ac718b69 | 1090 | { |
ebc2ec48 | 1091 | struct net_device_stats *stats; |
d104eafa | 1092 | struct net_device *netdev; |
ebc2ec48 | 1093 | struct tx_agg *agg; |
ac718b69 | 1094 | struct r8152 *tp; |
ebc2ec48 | 1095 | int status = urb->status; |
ac718b69 | 1096 | |
ebc2ec48 | 1097 | agg = urb->context; |
1098 | if (!agg) | |
ac718b69 | 1099 | return; |
1100 | ||
ebc2ec48 | 1101 | tp = agg->context; |
1102 | if (!tp) | |
1103 | return; | |
1104 | ||
d104eafa | 1105 | netdev = tp->netdev; |
05e0f1aa | 1106 | stats = &netdev->stats; |
ebc2ec48 | 1107 | if (status) { |
4a8deae2 | 1108 | if (net_ratelimit()) |
d104eafa | 1109 | netdev_warn(netdev, "Tx status %d\n", status); |
ebc2ec48 | 1110 | stats->tx_errors += agg->skb_num; |
ac718b69 | 1111 | } else { |
ebc2ec48 | 1112 | stats->tx_packets += agg->skb_num; |
1113 | stats->tx_bytes += agg->skb_len; | |
ac718b69 | 1114 | } |
1115 | ||
2685d410 | 1116 | spin_lock(&tp->tx_lock); |
ebc2ec48 | 1117 | list_add_tail(&agg->list, &tp->tx_free); |
2685d410 | 1118 | spin_unlock(&tp->tx_lock); |
ebc2ec48 | 1119 | |
9a4be1bd | 1120 | usb_autopm_put_interface_async(tp->intf); |
1121 | ||
d104eafa | 1122 | if (!netif_carrier_ok(netdev)) |
ebc2ec48 | 1123 | return; |
1124 | ||
1125 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1126 | return; | |
1127 | ||
1128 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1129 | return; | |
1130 | ||
1131 | if (!skb_queue_empty(&tp->tx_queue)) | |
0c3121fc | 1132 | tasklet_schedule(&tp->tl); |
ac718b69 | 1133 | } |
1134 | ||
40a82917 | 1135 | static void intr_callback(struct urb *urb) |
1136 | { | |
1137 | struct r8152 *tp; | |
500b6d7e | 1138 | __le16 *d; |
40a82917 | 1139 | int status = urb->status; |
1140 | int res; | |
1141 | ||
1142 | tp = urb->context; | |
1143 | if (!tp) | |
1144 | return; | |
1145 | ||
1146 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1147 | return; | |
1148 | ||
1149 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1150 | return; | |
1151 | ||
1152 | switch (status) { | |
1153 | case 0: /* success */ | |
1154 | break; | |
1155 | case -ECONNRESET: /* unlink */ | |
1156 | case -ESHUTDOWN: | |
1157 | netif_device_detach(tp->netdev); | |
1158 | case -ENOENT: | |
1159 | return; | |
1160 | case -EOVERFLOW: | |
1161 | netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); | |
1162 | goto resubmit; | |
1163 | /* -EPIPE: should clear the halt */ | |
1164 | default: | |
1165 | netif_info(tp, intr, tp->netdev, "intr status %d\n", status); | |
1166 | goto resubmit; | |
1167 | } | |
1168 | ||
1169 | d = urb->transfer_buffer; | |
1170 | if (INTR_LINK & __le16_to_cpu(d[0])) { | |
1171 | if (!(tp->speed & LINK_STATUS)) { | |
1172 | set_bit(RTL8152_LINK_CHG, &tp->flags); | |
1173 | schedule_delayed_work(&tp->schedule, 0); | |
1174 | } | |
1175 | } else { | |
1176 | if (tp->speed & LINK_STATUS) { | |
1177 | set_bit(RTL8152_LINK_CHG, &tp->flags); | |
1178 | schedule_delayed_work(&tp->schedule, 0); | |
1179 | } | |
1180 | } | |
1181 | ||
1182 | resubmit: | |
1183 | res = usb_submit_urb(urb, GFP_ATOMIC); | |
1184 | if (res == -ENODEV) | |
1185 | netif_device_detach(tp->netdev); | |
1186 | else if (res) | |
1187 | netif_err(tp, intr, tp->netdev, | |
4a8deae2 | 1188 | "can't resubmit intr, status %d\n", res); |
40a82917 | 1189 | } |
1190 | ||
ebc2ec48 | 1191 | static inline void *rx_agg_align(void *data) |
1192 | { | |
8e1f51bd | 1193 | return (void *)ALIGN((uintptr_t)data, RX_ALIGN); |
ebc2ec48 | 1194 | } |
1195 | ||
1196 | static inline void *tx_agg_align(void *data) | |
1197 | { | |
8e1f51bd | 1198 | return (void *)ALIGN((uintptr_t)data, TX_ALIGN); |
ebc2ec48 | 1199 | } |
1200 | ||
1201 | static void free_all_mem(struct r8152 *tp) | |
1202 | { | |
1203 | int i; | |
1204 | ||
1205 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
9629e3c0 | 1206 | usb_free_urb(tp->rx_info[i].urb); |
1207 | tp->rx_info[i].urb = NULL; | |
ebc2ec48 | 1208 | |
9629e3c0 | 1209 | kfree(tp->rx_info[i].buffer); |
1210 | tp->rx_info[i].buffer = NULL; | |
1211 | tp->rx_info[i].head = NULL; | |
ebc2ec48 | 1212 | } |
1213 | ||
1214 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
9629e3c0 | 1215 | usb_free_urb(tp->tx_info[i].urb); |
1216 | tp->tx_info[i].urb = NULL; | |
ebc2ec48 | 1217 | |
9629e3c0 | 1218 | kfree(tp->tx_info[i].buffer); |
1219 | tp->tx_info[i].buffer = NULL; | |
1220 | tp->tx_info[i].head = NULL; | |
ebc2ec48 | 1221 | } |
40a82917 | 1222 | |
9629e3c0 | 1223 | usb_free_urb(tp->intr_urb); |
1224 | tp->intr_urb = NULL; | |
40a82917 | 1225 | |
9629e3c0 | 1226 | kfree(tp->intr_buff); |
1227 | tp->intr_buff = NULL; | |
ebc2ec48 | 1228 | } |
1229 | ||
1230 | static int alloc_all_mem(struct r8152 *tp) | |
1231 | { | |
1232 | struct net_device *netdev = tp->netdev; | |
40a82917 | 1233 | struct usb_interface *intf = tp->intf; |
1234 | struct usb_host_interface *alt = intf->cur_altsetting; | |
1235 | struct usb_host_endpoint *ep_intr = alt->endpoint + 2; | |
ebc2ec48 | 1236 | struct urb *urb; |
1237 | int node, i; | |
1238 | u8 *buf; | |
1239 | ||
1240 | node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; | |
1241 | ||
1242 | spin_lock_init(&tp->rx_lock); | |
1243 | spin_lock_init(&tp->tx_lock); | |
1244 | INIT_LIST_HEAD(&tp->rx_done); | |
1245 | INIT_LIST_HEAD(&tp->tx_free); | |
1246 | skb_queue_head_init(&tp->tx_queue); | |
1247 | ||
1248 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
52aec126 | 1249 | buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); |
ebc2ec48 | 1250 | if (!buf) |
1251 | goto err1; | |
1252 | ||
1253 | if (buf != rx_agg_align(buf)) { | |
1254 | kfree(buf); | |
52aec126 | 1255 | buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, |
8e1f51bd | 1256 | node); |
ebc2ec48 | 1257 | if (!buf) |
1258 | goto err1; | |
1259 | } | |
1260 | ||
1261 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1262 | if (!urb) { | |
1263 | kfree(buf); | |
1264 | goto err1; | |
1265 | } | |
1266 | ||
1267 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1268 | tp->rx_info[i].context = tp; | |
1269 | tp->rx_info[i].urb = urb; | |
1270 | tp->rx_info[i].buffer = buf; | |
1271 | tp->rx_info[i].head = rx_agg_align(buf); | |
1272 | } | |
1273 | ||
1274 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
52aec126 | 1275 | buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); |
ebc2ec48 | 1276 | if (!buf) |
1277 | goto err1; | |
1278 | ||
1279 | if (buf != tx_agg_align(buf)) { | |
1280 | kfree(buf); | |
52aec126 | 1281 | buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, |
8e1f51bd | 1282 | node); |
ebc2ec48 | 1283 | if (!buf) |
1284 | goto err1; | |
1285 | } | |
1286 | ||
1287 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1288 | if (!urb) { | |
1289 | kfree(buf); | |
1290 | goto err1; | |
1291 | } | |
1292 | ||
1293 | INIT_LIST_HEAD(&tp->tx_info[i].list); | |
1294 | tp->tx_info[i].context = tp; | |
1295 | tp->tx_info[i].urb = urb; | |
1296 | tp->tx_info[i].buffer = buf; | |
1297 | tp->tx_info[i].head = tx_agg_align(buf); | |
1298 | ||
1299 | list_add_tail(&tp->tx_info[i].list, &tp->tx_free); | |
1300 | } | |
1301 | ||
40a82917 | 1302 | tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); |
1303 | if (!tp->intr_urb) | |
1304 | goto err1; | |
1305 | ||
1306 | tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); | |
1307 | if (!tp->intr_buff) | |
1308 | goto err1; | |
1309 | ||
1310 | tp->intr_interval = (int)ep_intr->desc.bInterval; | |
1311 | usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), | |
b209af99 | 1312 | tp->intr_buff, INTBUFSIZE, intr_callback, |
1313 | tp, tp->intr_interval); | |
40a82917 | 1314 | |
ebc2ec48 | 1315 | return 0; |
1316 | ||
1317 | err1: | |
1318 | free_all_mem(tp); | |
1319 | return -ENOMEM; | |
1320 | } | |
1321 | ||
0de98f6c | 1322 | static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) |
1323 | { | |
1324 | struct tx_agg *agg = NULL; | |
1325 | unsigned long flags; | |
1326 | ||
21949ab7 | 1327 | if (list_empty(&tp->tx_free)) |
1328 | return NULL; | |
1329 | ||
0de98f6c | 1330 | spin_lock_irqsave(&tp->tx_lock, flags); |
1331 | if (!list_empty(&tp->tx_free)) { | |
1332 | struct list_head *cursor; | |
1333 | ||
1334 | cursor = tp->tx_free.next; | |
1335 | list_del_init(cursor); | |
1336 | agg = list_entry(cursor, struct tx_agg, list); | |
1337 | } | |
1338 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1339 | ||
1340 | return agg; | |
1341 | } | |
1342 | ||
60c89071 | 1343 | static inline __be16 get_protocol(struct sk_buff *skb) |
5bd23881 | 1344 | { |
60c89071 | 1345 | __be16 protocol; |
5bd23881 | 1346 | |
60c89071 | 1347 | if (skb->protocol == htons(ETH_P_8021Q)) |
1348 | protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; | |
1349 | else | |
1350 | protocol = skb->protocol; | |
5bd23881 | 1351 | |
60c89071 | 1352 | return protocol; |
1353 | } | |
5bd23881 | 1354 | |
b209af99 | 1355 | /* r8152_csum_workaround() |
6128d1bb | 1356 | * The hw limites the value the transport offset. When the offset is out of the |
1357 | * range, calculate the checksum by sw. | |
1358 | */ | |
1359 | static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, | |
1360 | struct sk_buff_head *list) | |
1361 | { | |
1362 | if (skb_shinfo(skb)->gso_size) { | |
1363 | netdev_features_t features = tp->netdev->features; | |
1364 | struct sk_buff_head seg_list; | |
1365 | struct sk_buff *segs, *nskb; | |
1366 | ||
a91d45f1 | 1367 | features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); |
6128d1bb | 1368 | segs = skb_gso_segment(skb, features); |
1369 | if (IS_ERR(segs) || !segs) | |
1370 | goto drop; | |
1371 | ||
1372 | __skb_queue_head_init(&seg_list); | |
1373 | ||
1374 | do { | |
1375 | nskb = segs; | |
1376 | segs = segs->next; | |
1377 | nskb->next = NULL; | |
1378 | __skb_queue_tail(&seg_list, nskb); | |
1379 | } while (segs); | |
1380 | ||
1381 | skb_queue_splice(&seg_list, list); | |
1382 | dev_kfree_skb(skb); | |
1383 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1384 | if (skb_checksum_help(skb) < 0) | |
1385 | goto drop; | |
1386 | ||
1387 | __skb_queue_head(list, skb); | |
1388 | } else { | |
1389 | struct net_device_stats *stats; | |
1390 | ||
1391 | drop: | |
1392 | stats = &tp->netdev->stats; | |
1393 | stats->tx_dropped++; | |
1394 | dev_kfree_skb(skb); | |
1395 | } | |
1396 | } | |
1397 | ||
b209af99 | 1398 | /* msdn_giant_send_check() |
6128d1bb | 1399 | * According to the document of microsoft, the TCP Pseudo Header excludes the |
1400 | * packet length for IPv6 TCP large packets. | |
1401 | */ | |
1402 | static int msdn_giant_send_check(struct sk_buff *skb) | |
1403 | { | |
1404 | const struct ipv6hdr *ipv6h; | |
1405 | struct tcphdr *th; | |
fcb308d5 | 1406 | int ret; |
1407 | ||
1408 | ret = skb_cow_head(skb, 0); | |
1409 | if (ret) | |
1410 | return ret; | |
6128d1bb | 1411 | |
1412 | ipv6h = ipv6_hdr(skb); | |
1413 | th = tcp_hdr(skb); | |
1414 | ||
1415 | th->check = 0; | |
1416 | th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); | |
1417 | ||
fcb308d5 | 1418 | return ret; |
6128d1bb | 1419 | } |
1420 | ||
c5554298 | 1421 | static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) |
1422 | { | |
1423 | if (vlan_tx_tag_present(skb)) { | |
1424 | u32 opts2; | |
1425 | ||
1426 | opts2 = TX_VLAN_TAG | swab16(vlan_tx_tag_get(skb)); | |
1427 | desc->opts2 |= cpu_to_le32(opts2); | |
1428 | } | |
1429 | } | |
1430 | ||
1431 | static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) | |
1432 | { | |
1433 | u32 opts2 = le32_to_cpu(desc->opts2); | |
1434 | ||
1435 | if (opts2 & RX_VLAN_TAG) | |
1436 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), | |
1437 | swab16(opts2 & 0xffff)); | |
1438 | } | |
1439 | ||
60c89071 | 1440 | static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, |
1441 | struct sk_buff *skb, u32 len, u32 transport_offset) | |
1442 | { | |
1443 | u32 mss = skb_shinfo(skb)->gso_size; | |
1444 | u32 opts1, opts2 = 0; | |
1445 | int ret = TX_CSUM_SUCCESS; | |
1446 | ||
1447 | WARN_ON_ONCE(len > TX_LEN_MAX); | |
1448 | ||
1449 | opts1 = len | TX_FS | TX_LS; | |
1450 | ||
1451 | if (mss) { | |
6128d1bb | 1452 | if (transport_offset > GTTCPHO_MAX) { |
1453 | netif_warn(tp, tx_err, tp->netdev, | |
1454 | "Invalid transport offset 0x%x for TSO\n", | |
1455 | transport_offset); | |
1456 | ret = TX_CSUM_TSO; | |
1457 | goto unavailable; | |
1458 | } | |
1459 | ||
60c89071 | 1460 | switch (get_protocol(skb)) { |
1461 | case htons(ETH_P_IP): | |
1462 | opts1 |= GTSENDV4; | |
1463 | break; | |
1464 | ||
6128d1bb | 1465 | case htons(ETH_P_IPV6): |
fcb308d5 | 1466 | if (msdn_giant_send_check(skb)) { |
1467 | ret = TX_CSUM_TSO; | |
1468 | goto unavailable; | |
1469 | } | |
6128d1bb | 1470 | opts1 |= GTSENDV6; |
6128d1bb | 1471 | break; |
1472 | ||
60c89071 | 1473 | default: |
1474 | WARN_ON_ONCE(1); | |
1475 | break; | |
1476 | } | |
1477 | ||
1478 | opts1 |= transport_offset << GTTCPHO_SHIFT; | |
1479 | opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; | |
1480 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1481 | u8 ip_protocol; | |
5bd23881 | 1482 | |
6128d1bb | 1483 | if (transport_offset > TCPHO_MAX) { |
1484 | netif_warn(tp, tx_err, tp->netdev, | |
1485 | "Invalid transport offset 0x%x\n", | |
1486 | transport_offset); | |
1487 | ret = TX_CSUM_NONE; | |
1488 | goto unavailable; | |
1489 | } | |
1490 | ||
60c89071 | 1491 | switch (get_protocol(skb)) { |
5bd23881 | 1492 | case htons(ETH_P_IP): |
1493 | opts2 |= IPV4_CS; | |
1494 | ip_protocol = ip_hdr(skb)->protocol; | |
1495 | break; | |
1496 | ||
1497 | case htons(ETH_P_IPV6): | |
1498 | opts2 |= IPV6_CS; | |
1499 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
1500 | break; | |
1501 | ||
1502 | default: | |
1503 | ip_protocol = IPPROTO_RAW; | |
1504 | break; | |
1505 | } | |
1506 | ||
60c89071 | 1507 | if (ip_protocol == IPPROTO_TCP) |
5bd23881 | 1508 | opts2 |= TCP_CS; |
60c89071 | 1509 | else if (ip_protocol == IPPROTO_UDP) |
5bd23881 | 1510 | opts2 |= UDP_CS; |
60c89071 | 1511 | else |
5bd23881 | 1512 | WARN_ON_ONCE(1); |
5bd23881 | 1513 | |
60c89071 | 1514 | opts2 |= transport_offset << TCPHO_SHIFT; |
5bd23881 | 1515 | } |
60c89071 | 1516 | |
1517 | desc->opts2 = cpu_to_le32(opts2); | |
1518 | desc->opts1 = cpu_to_le32(opts1); | |
1519 | ||
6128d1bb | 1520 | unavailable: |
60c89071 | 1521 | return ret; |
5bd23881 | 1522 | } |
1523 | ||
b1379d9a | 1524 | static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) |
1525 | { | |
d84130a1 | 1526 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
9a4be1bd | 1527 | int remain, ret; |
b1379d9a | 1528 | u8 *tx_data; |
1529 | ||
d84130a1 | 1530 | __skb_queue_head_init(&skb_head); |
0c3121fc | 1531 | spin_lock(&tx_queue->lock); |
d84130a1 | 1532 | skb_queue_splice_init(tx_queue, &skb_head); |
0c3121fc | 1533 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1534 | |
b1379d9a | 1535 | tx_data = agg->head; |
b209af99 | 1536 | agg->skb_num = 0; |
1537 | agg->skb_len = 0; | |
52aec126 | 1538 | remain = agg_buf_sz; |
b1379d9a | 1539 | |
7937f9e5 | 1540 | while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { |
b1379d9a | 1541 | struct tx_desc *tx_desc; |
1542 | struct sk_buff *skb; | |
1543 | unsigned int len; | |
60c89071 | 1544 | u32 offset; |
b1379d9a | 1545 | |
d84130a1 | 1546 | skb = __skb_dequeue(&skb_head); |
b1379d9a | 1547 | if (!skb) |
1548 | break; | |
1549 | ||
60c89071 | 1550 | len = skb->len + sizeof(*tx_desc); |
1551 | ||
1552 | if (len > remain) { | |
d84130a1 | 1553 | __skb_queue_head(&skb_head, skb); |
b1379d9a | 1554 | break; |
1555 | } | |
1556 | ||
7937f9e5 | 1557 | tx_data = tx_agg_align(tx_data); |
b1379d9a | 1558 | tx_desc = (struct tx_desc *)tx_data; |
60c89071 | 1559 | |
1560 | offset = (u32)skb_transport_offset(skb); | |
1561 | ||
6128d1bb | 1562 | if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { |
1563 | r8152_csum_workaround(tp, skb, &skb_head); | |
1564 | continue; | |
1565 | } | |
60c89071 | 1566 | |
c5554298 | 1567 | rtl_tx_vlan_tag(tx_desc, skb); |
1568 | ||
b1379d9a | 1569 | tx_data += sizeof(*tx_desc); |
1570 | ||
60c89071 | 1571 | len = skb->len; |
1572 | if (skb_copy_bits(skb, 0, tx_data, len) < 0) { | |
1573 | struct net_device_stats *stats = &tp->netdev->stats; | |
1574 | ||
1575 | stats->tx_dropped++; | |
1576 | dev_kfree_skb_any(skb); | |
1577 | tx_data -= sizeof(*tx_desc); | |
1578 | continue; | |
1579 | } | |
1580 | ||
1581 | tx_data += len; | |
b1379d9a | 1582 | agg->skb_len += len; |
60c89071 | 1583 | agg->skb_num++; |
1584 | ||
b1379d9a | 1585 | dev_kfree_skb_any(skb); |
1586 | ||
52aec126 | 1587 | remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); |
b1379d9a | 1588 | } |
1589 | ||
d84130a1 | 1590 | if (!skb_queue_empty(&skb_head)) { |
0c3121fc | 1591 | spin_lock(&tx_queue->lock); |
d84130a1 | 1592 | skb_queue_splice(&skb_head, tx_queue); |
0c3121fc | 1593 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1594 | } |
1595 | ||
0c3121fc | 1596 | netif_tx_lock(tp->netdev); |
dd1b119c | 1597 | |
1598 | if (netif_queue_stopped(tp->netdev) && | |
1599 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) | |
1600 | netif_wake_queue(tp->netdev); | |
1601 | ||
0c3121fc | 1602 | netif_tx_unlock(tp->netdev); |
9a4be1bd | 1603 | |
0c3121fc | 1604 | ret = usb_autopm_get_interface_async(tp->intf); |
9a4be1bd | 1605 | if (ret < 0) |
1606 | goto out_tx_fill; | |
dd1b119c | 1607 | |
b1379d9a | 1608 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), |
1609 | agg->head, (int)(tx_data - (u8 *)agg->head), | |
1610 | (usb_complete_t)write_bulk_callback, agg); | |
1611 | ||
0c3121fc | 1612 | ret = usb_submit_urb(agg->urb, GFP_ATOMIC); |
9a4be1bd | 1613 | if (ret < 0) |
0c3121fc | 1614 | usb_autopm_put_interface_async(tp->intf); |
9a4be1bd | 1615 | |
1616 | out_tx_fill: | |
1617 | return ret; | |
b1379d9a | 1618 | } |
1619 | ||
565cab0a | 1620 | static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) |
1621 | { | |
1622 | u8 checksum = CHECKSUM_NONE; | |
1623 | u32 opts2, opts3; | |
1624 | ||
1625 | if (tp->version == RTL_VER_01) | |
1626 | goto return_result; | |
1627 | ||
1628 | opts2 = le32_to_cpu(rx_desc->opts2); | |
1629 | opts3 = le32_to_cpu(rx_desc->opts3); | |
1630 | ||
1631 | if (opts2 & RD_IPV4_CS) { | |
1632 | if (opts3 & IPF) | |
1633 | checksum = CHECKSUM_NONE; | |
1634 | else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) | |
1635 | checksum = CHECKSUM_NONE; | |
1636 | else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) | |
1637 | checksum = CHECKSUM_NONE; | |
1638 | else | |
1639 | checksum = CHECKSUM_UNNECESSARY; | |
6128d1bb | 1640 | } else if (RD_IPV6_CS) { |
1641 | if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) | |
1642 | checksum = CHECKSUM_UNNECESSARY; | |
1643 | else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) | |
1644 | checksum = CHECKSUM_UNNECESSARY; | |
565cab0a | 1645 | } |
1646 | ||
1647 | return_result: | |
1648 | return checksum; | |
1649 | } | |
1650 | ||
ebc2ec48 | 1651 | static void rx_bottom(struct r8152 *tp) |
1652 | { | |
a5a4f468 | 1653 | unsigned long flags; |
d84130a1 | 1654 | struct list_head *cursor, *next, rx_queue; |
ebc2ec48 | 1655 | |
d84130a1 | 1656 | if (list_empty(&tp->rx_done)) |
1657 | return; | |
1658 | ||
1659 | INIT_LIST_HEAD(&rx_queue); | |
a5a4f468 | 1660 | spin_lock_irqsave(&tp->rx_lock, flags); |
d84130a1 | 1661 | list_splice_init(&tp->rx_done, &rx_queue); |
1662 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
1663 | ||
1664 | list_for_each_safe(cursor, next, &rx_queue) { | |
43a4478d | 1665 | struct rx_desc *rx_desc; |
1666 | struct rx_agg *agg; | |
43a4478d | 1667 | int len_used = 0; |
1668 | struct urb *urb; | |
1669 | u8 *rx_data; | |
1670 | int ret; | |
1671 | ||
ebc2ec48 | 1672 | list_del_init(cursor); |
ebc2ec48 | 1673 | |
1674 | agg = list_entry(cursor, struct rx_agg, list); | |
1675 | urb = agg->urb; | |
0de98f6c | 1676 | if (urb->actual_length < ETH_ZLEN) |
1677 | goto submit; | |
ebc2ec48 | 1678 | |
ebc2ec48 | 1679 | rx_desc = agg->head; |
1680 | rx_data = agg->head; | |
7937f9e5 | 1681 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1682 | |
7937f9e5 | 1683 | while (urb->actual_length > len_used) { |
43a4478d | 1684 | struct net_device *netdev = tp->netdev; |
05e0f1aa | 1685 | struct net_device_stats *stats = &netdev->stats; |
7937f9e5 | 1686 | unsigned int pkt_len; |
43a4478d | 1687 | struct sk_buff *skb; |
1688 | ||
7937f9e5 | 1689 | pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; |
ebc2ec48 | 1690 | if (pkt_len < ETH_ZLEN) |
1691 | break; | |
1692 | ||
7937f9e5 | 1693 | len_used += pkt_len; |
1694 | if (urb->actual_length < len_used) | |
1695 | break; | |
1696 | ||
8e1f51bd | 1697 | pkt_len -= CRC_SIZE; |
ebc2ec48 | 1698 | rx_data += sizeof(struct rx_desc); |
1699 | ||
1700 | skb = netdev_alloc_skb_ip_align(netdev, pkt_len); | |
1701 | if (!skb) { | |
1702 | stats->rx_dropped++; | |
5e2f7485 | 1703 | goto find_next_rx; |
ebc2ec48 | 1704 | } |
565cab0a | 1705 | |
1706 | skb->ip_summed = r8152_rx_csum(tp, rx_desc); | |
ebc2ec48 | 1707 | memcpy(skb->data, rx_data, pkt_len); |
1708 | skb_put(skb, pkt_len); | |
1709 | skb->protocol = eth_type_trans(skb, netdev); | |
c5554298 | 1710 | rtl_rx_vlan_tag(rx_desc, skb); |
9d9aafa1 | 1711 | netif_receive_skb(skb); |
ebc2ec48 | 1712 | stats->rx_packets++; |
1713 | stats->rx_bytes += pkt_len; | |
1714 | ||
5e2f7485 | 1715 | find_next_rx: |
8e1f51bd | 1716 | rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); |
ebc2ec48 | 1717 | rx_desc = (struct rx_desc *)rx_data; |
ebc2ec48 | 1718 | len_used = (int)(rx_data - (u8 *)agg->head); |
7937f9e5 | 1719 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1720 | } |
1721 | ||
0de98f6c | 1722 | submit: |
ebc2ec48 | 1723 | ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ebc2ec48 | 1724 | if (ret && ret != -ENODEV) { |
d84130a1 | 1725 | spin_lock_irqsave(&tp->rx_lock, flags); |
1726 | list_add_tail(&agg->list, &tp->rx_done); | |
1727 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
ebc2ec48 | 1728 | tasklet_schedule(&tp->tl); |
1729 | } | |
1730 | } | |
ebc2ec48 | 1731 | } |
1732 | ||
1733 | static void tx_bottom(struct r8152 *tp) | |
1734 | { | |
ebc2ec48 | 1735 | int res; |
1736 | ||
b1379d9a | 1737 | do { |
1738 | struct tx_agg *agg; | |
ebc2ec48 | 1739 | |
b1379d9a | 1740 | if (skb_queue_empty(&tp->tx_queue)) |
ebc2ec48 | 1741 | break; |
1742 | ||
b1379d9a | 1743 | agg = r8152_get_tx_agg(tp); |
1744 | if (!agg) | |
ebc2ec48 | 1745 | break; |
ebc2ec48 | 1746 | |
b1379d9a | 1747 | res = r8152_tx_agg_fill(tp, agg); |
1748 | if (res) { | |
05e0f1aa | 1749 | struct net_device *netdev = tp->netdev; |
ebc2ec48 | 1750 | |
b1379d9a | 1751 | if (res == -ENODEV) { |
1752 | netif_device_detach(netdev); | |
1753 | } else { | |
05e0f1aa | 1754 | struct net_device_stats *stats = &netdev->stats; |
1755 | unsigned long flags; | |
1756 | ||
b1379d9a | 1757 | netif_warn(tp, tx_err, netdev, |
1758 | "failed tx_urb %d\n", res); | |
1759 | stats->tx_dropped += agg->skb_num; | |
db8515ef | 1760 | |
b1379d9a | 1761 | spin_lock_irqsave(&tp->tx_lock, flags); |
1762 | list_add_tail(&agg->list, &tp->tx_free); | |
1763 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1764 | } | |
ebc2ec48 | 1765 | } |
b1379d9a | 1766 | } while (res == 0); |
ebc2ec48 | 1767 | } |
1768 | ||
1769 | static void bottom_half(unsigned long data) | |
ac718b69 | 1770 | { |
1771 | struct r8152 *tp; | |
ac718b69 | 1772 | |
ebc2ec48 | 1773 | tp = (struct r8152 *)data; |
1774 | ||
1775 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1776 | return; | |
1777 | ||
1778 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
ac718b69 | 1779 | return; |
ebc2ec48 | 1780 | |
7559fb2f | 1781 | /* When link down, the driver would cancel all bulks. */ |
1782 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1783 | if (!netif_carrier_ok(tp->netdev)) |
ac718b69 | 1784 | return; |
ebc2ec48 | 1785 | |
1786 | rx_bottom(tp); | |
0c3121fc | 1787 | tx_bottom(tp); |
ebc2ec48 | 1788 | } |
1789 | ||
1790 | static | |
1791 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) | |
1792 | { | |
1793 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), | |
52aec126 | 1794 | agg->head, agg_buf_sz, |
b209af99 | 1795 | (usb_complete_t)read_bulk_callback, agg); |
ebc2ec48 | 1796 | |
1797 | return usb_submit_urb(agg->urb, mem_flags); | |
ac718b69 | 1798 | } |
1799 | ||
00a5e360 | 1800 | static void rtl_drop_queued_tx(struct r8152 *tp) |
1801 | { | |
1802 | struct net_device_stats *stats = &tp->netdev->stats; | |
d84130a1 | 1803 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
00a5e360 | 1804 | struct sk_buff *skb; |
1805 | ||
d84130a1 | 1806 | if (skb_queue_empty(tx_queue)) |
1807 | return; | |
1808 | ||
1809 | __skb_queue_head_init(&skb_head); | |
2685d410 | 1810 | spin_lock_bh(&tx_queue->lock); |
d84130a1 | 1811 | skb_queue_splice_init(tx_queue, &skb_head); |
2685d410 | 1812 | spin_unlock_bh(&tx_queue->lock); |
d84130a1 | 1813 | |
1814 | while ((skb = __skb_dequeue(&skb_head))) { | |
00a5e360 | 1815 | dev_kfree_skb(skb); |
1816 | stats->tx_dropped++; | |
1817 | } | |
1818 | } | |
1819 | ||
ac718b69 | 1820 | static void rtl8152_tx_timeout(struct net_device *netdev) |
1821 | { | |
1822 | struct r8152 *tp = netdev_priv(netdev); | |
ebc2ec48 | 1823 | int i; |
1824 | ||
4a8deae2 | 1825 | netif_warn(tp, tx_err, netdev, "Tx timeout\n"); |
ebc2ec48 | 1826 | for (i = 0; i < RTL8152_MAX_TX; i++) |
1827 | usb_unlink_urb(tp->tx_info[i].urb); | |
ac718b69 | 1828 | } |
1829 | ||
1830 | static void rtl8152_set_rx_mode(struct net_device *netdev) | |
1831 | { | |
1832 | struct r8152 *tp = netdev_priv(netdev); | |
1833 | ||
40a82917 | 1834 | if (tp->speed & LINK_STATUS) { |
ac718b69 | 1835 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
40a82917 | 1836 | schedule_delayed_work(&tp->schedule, 0); |
1837 | } | |
ac718b69 | 1838 | } |
1839 | ||
1840 | static void _rtl8152_set_rx_mode(struct net_device *netdev) | |
1841 | { | |
1842 | struct r8152 *tp = netdev_priv(netdev); | |
31787f53 | 1843 | u32 mc_filter[2]; /* Multicast hash filter */ |
1844 | __le32 tmp[2]; | |
ac718b69 | 1845 | u32 ocp_data; |
1846 | ||
ac718b69 | 1847 | clear_bit(RTL8152_SET_RX_MODE, &tp->flags); |
1848 | netif_stop_queue(netdev); | |
1849 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1850 | ocp_data &= ~RCR_ACPT_ALL; | |
1851 | ocp_data |= RCR_AB | RCR_APM; | |
1852 | ||
1853 | if (netdev->flags & IFF_PROMISC) { | |
1854 | /* Unconditionally log net taps. */ | |
1855 | netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); | |
1856 | ocp_data |= RCR_AM | RCR_AAP; | |
b209af99 | 1857 | mc_filter[1] = 0xffffffff; |
1858 | mc_filter[0] = 0xffffffff; | |
ac718b69 | 1859 | } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || |
1860 | (netdev->flags & IFF_ALLMULTI)) { | |
1861 | /* Too many to filter perfectly -- accept all multicasts. */ | |
1862 | ocp_data |= RCR_AM; | |
b209af99 | 1863 | mc_filter[1] = 0xffffffff; |
1864 | mc_filter[0] = 0xffffffff; | |
ac718b69 | 1865 | } else { |
1866 | struct netdev_hw_addr *ha; | |
1867 | ||
b209af99 | 1868 | mc_filter[1] = 0; |
1869 | mc_filter[0] = 0; | |
ac718b69 | 1870 | netdev_for_each_mc_addr(ha, netdev) { |
1871 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
b209af99 | 1872 | |
ac718b69 | 1873 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
1874 | ocp_data |= RCR_AM; | |
1875 | } | |
1876 | } | |
1877 | ||
31787f53 | 1878 | tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); |
1879 | tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); | |
ac718b69 | 1880 | |
31787f53 | 1881 | pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); |
ac718b69 | 1882 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
1883 | netif_wake_queue(netdev); | |
ac718b69 | 1884 | } |
1885 | ||
1886 | static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, | |
b209af99 | 1887 | struct net_device *netdev) |
ac718b69 | 1888 | { |
1889 | struct r8152 *tp = netdev_priv(netdev); | |
ac718b69 | 1890 | |
ebc2ec48 | 1891 | skb_tx_timestamp(skb); |
ac718b69 | 1892 | |
61598788 | 1893 | skb_queue_tail(&tp->tx_queue, skb); |
ebc2ec48 | 1894 | |
0c3121fc | 1895 | if (!list_empty(&tp->tx_free)) { |
1896 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { | |
1897 | set_bit(SCHEDULE_TASKLET, &tp->flags); | |
1898 | schedule_delayed_work(&tp->schedule, 0); | |
1899 | } else { | |
1900 | usb_mark_last_busy(tp->udev); | |
1901 | tasklet_schedule(&tp->tl); | |
1902 | } | |
b209af99 | 1903 | } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { |
dd1b119c | 1904 | netif_stop_queue(netdev); |
b209af99 | 1905 | } |
dd1b119c | 1906 | |
ac718b69 | 1907 | return NETDEV_TX_OK; |
1908 | } | |
1909 | ||
1910 | static void r8152b_reset_packet_filter(struct r8152 *tp) | |
1911 | { | |
1912 | u32 ocp_data; | |
1913 | ||
1914 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); | |
1915 | ocp_data &= ~FMC_FCR_MCU_EN; | |
1916 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
1917 | ocp_data |= FMC_FCR_MCU_EN; | |
1918 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
1919 | } | |
1920 | ||
1921 | static void rtl8152_nic_reset(struct r8152 *tp) | |
1922 | { | |
1923 | int i; | |
1924 | ||
1925 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); | |
1926 | ||
1927 | for (i = 0; i < 1000; i++) { | |
1928 | if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) | |
1929 | break; | |
b209af99 | 1930 | usleep_range(100, 400); |
ac718b69 | 1931 | } |
1932 | } | |
1933 | ||
dd1b119c | 1934 | static void set_tx_qlen(struct r8152 *tp) |
1935 | { | |
1936 | struct net_device *netdev = tp->netdev; | |
1937 | ||
52aec126 | 1938 | tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + |
1939 | sizeof(struct tx_desc)); | |
dd1b119c | 1940 | } |
1941 | ||
ac718b69 | 1942 | static inline u8 rtl8152_get_speed(struct r8152 *tp) |
1943 | { | |
1944 | return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); | |
1945 | } | |
1946 | ||
507605a8 | 1947 | static void rtl_set_eee_plus(struct r8152 *tp) |
ac718b69 | 1948 | { |
ebc2ec48 | 1949 | u32 ocp_data; |
ac718b69 | 1950 | u8 speed; |
1951 | ||
1952 | speed = rtl8152_get_speed(tp); | |
ebc2ec48 | 1953 | if (speed & _10bps) { |
ac718b69 | 1954 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); |
ebc2ec48 | 1955 | ocp_data |= EEEP_CR_EEEP_TX; |
ac718b69 | 1956 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1957 | } else { | |
1958 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); | |
ebc2ec48 | 1959 | ocp_data &= ~EEEP_CR_EEEP_TX; |
ac718b69 | 1960 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1961 | } | |
507605a8 | 1962 | } |
1963 | ||
00a5e360 | 1964 | static void rxdy_gated_en(struct r8152 *tp, bool enable) |
1965 | { | |
1966 | u32 ocp_data; | |
1967 | ||
1968 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); | |
1969 | if (enable) | |
1970 | ocp_data |= RXDY_GATED_EN; | |
1971 | else | |
1972 | ocp_data &= ~RXDY_GATED_EN; | |
1973 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); | |
1974 | } | |
1975 | ||
507605a8 | 1976 | static int rtl_enable(struct r8152 *tp) |
1977 | { | |
1978 | u32 ocp_data; | |
1979 | int i, ret; | |
ac718b69 | 1980 | |
1981 | r8152b_reset_packet_filter(tp); | |
1982 | ||
1983 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); | |
1984 | ocp_data |= CR_RE | CR_TE; | |
1985 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); | |
1986 | ||
00a5e360 | 1987 | rxdy_gated_en(tp, false); |
ac718b69 | 1988 | |
ebc2ec48 | 1989 | INIT_LIST_HEAD(&tp->rx_done); |
1990 | ret = 0; | |
1991 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
1992 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1993 | ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); | |
1994 | } | |
ac718b69 | 1995 | |
ebc2ec48 | 1996 | return ret; |
ac718b69 | 1997 | } |
1998 | ||
507605a8 | 1999 | static int rtl8152_enable(struct r8152 *tp) |
2000 | { | |
6871438c | 2001 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2002 | return -ENODEV; | |
2003 | ||
507605a8 | 2004 | set_tx_qlen(tp); |
2005 | rtl_set_eee_plus(tp); | |
2006 | ||
2007 | return rtl_enable(tp); | |
2008 | } | |
2009 | ||
43779f8d | 2010 | static void r8153_set_rx_agg(struct r8152 *tp) |
2011 | { | |
2012 | u8 speed; | |
2013 | ||
2014 | speed = rtl8152_get_speed(tp); | |
2015 | if (speed & _1000bps) { | |
2016 | if (tp->udev->speed == USB_SPEED_SUPER) { | |
2017 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, | |
2018 | RX_THR_SUPPER); | |
2019 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
2020 | EARLY_AGG_SUPPER); | |
2021 | } else { | |
2022 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, | |
2023 | RX_THR_HIGH); | |
2024 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
2025 | EARLY_AGG_HIGH); | |
2026 | } | |
2027 | } else { | |
2028 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW); | |
2029 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
2030 | EARLY_AGG_SLOW); | |
2031 | } | |
2032 | } | |
2033 | ||
2034 | static int rtl8153_enable(struct r8152 *tp) | |
2035 | { | |
6871438c | 2036 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2037 | return -ENODEV; | |
2038 | ||
43779f8d | 2039 | set_tx_qlen(tp); |
2040 | rtl_set_eee_plus(tp); | |
2041 | r8153_set_rx_agg(tp); | |
2042 | ||
2043 | return rtl_enable(tp); | |
2044 | } | |
2045 | ||
d70b1137 | 2046 | static void rtl_disable(struct r8152 *tp) |
ac718b69 | 2047 | { |
ebc2ec48 | 2048 | u32 ocp_data; |
2049 | int i; | |
ac718b69 | 2050 | |
6871438c | 2051 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2052 | rtl_drop_queued_tx(tp); | |
2053 | return; | |
2054 | } | |
2055 | ||
ac718b69 | 2056 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
2057 | ocp_data &= ~RCR_ACPT_ALL; | |
2058 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2059 | ||
00a5e360 | 2060 | rtl_drop_queued_tx(tp); |
ebc2ec48 | 2061 | |
2062 | for (i = 0; i < RTL8152_MAX_TX; i++) | |
2063 | usb_kill_urb(tp->tx_info[i].urb); | |
ac718b69 | 2064 | |
00a5e360 | 2065 | rxdy_gated_en(tp, true); |
ac718b69 | 2066 | |
2067 | for (i = 0; i < 1000; i++) { | |
2068 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2069 | if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) | |
2070 | break; | |
8ddfa077 | 2071 | usleep_range(1000, 2000); |
ac718b69 | 2072 | } |
2073 | ||
2074 | for (i = 0; i < 1000; i++) { | |
2075 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) | |
2076 | break; | |
8ddfa077 | 2077 | usleep_range(1000, 2000); |
ac718b69 | 2078 | } |
2079 | ||
ebc2ec48 | 2080 | for (i = 0; i < RTL8152_MAX_RX; i++) |
2081 | usb_kill_urb(tp->rx_info[i].urb); | |
ac718b69 | 2082 | |
2083 | rtl8152_nic_reset(tp); | |
2084 | } | |
2085 | ||
00a5e360 | 2086 | static void r8152_power_cut_en(struct r8152 *tp, bool enable) |
2087 | { | |
2088 | u32 ocp_data; | |
2089 | ||
2090 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); | |
2091 | if (enable) | |
2092 | ocp_data |= POWER_CUT; | |
2093 | else | |
2094 | ocp_data &= ~POWER_CUT; | |
2095 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); | |
2096 | ||
2097 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); | |
2098 | ocp_data &= ~RESUME_INDICATE; | |
2099 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); | |
00a5e360 | 2100 | } |
2101 | ||
c5554298 | 2102 | static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) |
2103 | { | |
2104 | u32 ocp_data; | |
2105 | ||
2106 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2107 | if (enable) | |
2108 | ocp_data |= CPCR_RX_VLAN; | |
2109 | else | |
2110 | ocp_data &= ~CPCR_RX_VLAN; | |
2111 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2112 | } | |
2113 | ||
2114 | static int rtl8152_set_features(struct net_device *dev, | |
2115 | netdev_features_t features) | |
2116 | { | |
2117 | netdev_features_t changed = features ^ dev->features; | |
2118 | struct r8152 *tp = netdev_priv(dev); | |
2119 | ||
2120 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) { | |
2121 | if (features & NETIF_F_HW_VLAN_CTAG_RX) | |
2122 | rtl_rx_vlan_en(tp, true); | |
2123 | else | |
2124 | rtl_rx_vlan_en(tp, false); | |
2125 | } | |
2126 | ||
2127 | return 0; | |
2128 | } | |
2129 | ||
21ff2e89 | 2130 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
2131 | ||
2132 | static u32 __rtl_get_wol(struct r8152 *tp) | |
2133 | { | |
2134 | u32 ocp_data; | |
2135 | u32 wolopts = 0; | |
2136 | ||
2137 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2138 | if (!(ocp_data & LAN_WAKE_EN)) | |
2139 | return 0; | |
2140 | ||
2141 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2142 | if (ocp_data & LINK_ON_WAKE_EN) | |
2143 | wolopts |= WAKE_PHY; | |
2144 | ||
2145 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2146 | if (ocp_data & UWF_EN) | |
2147 | wolopts |= WAKE_UCAST; | |
2148 | if (ocp_data & BWF_EN) | |
2149 | wolopts |= WAKE_BCAST; | |
2150 | if (ocp_data & MWF_EN) | |
2151 | wolopts |= WAKE_MCAST; | |
2152 | ||
2153 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2154 | if (ocp_data & MAGIC_EN) | |
2155 | wolopts |= WAKE_MAGIC; | |
2156 | ||
2157 | return wolopts; | |
2158 | } | |
2159 | ||
2160 | static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) | |
2161 | { | |
2162 | u32 ocp_data; | |
2163 | ||
2164 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2165 | ||
2166 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2167 | ocp_data &= ~LINK_ON_WAKE_EN; | |
2168 | if (wolopts & WAKE_PHY) | |
2169 | ocp_data |= LINK_ON_WAKE_EN; | |
2170 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2171 | ||
2172 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2173 | ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN); | |
2174 | if (wolopts & WAKE_UCAST) | |
2175 | ocp_data |= UWF_EN; | |
2176 | if (wolopts & WAKE_BCAST) | |
2177 | ocp_data |= BWF_EN; | |
2178 | if (wolopts & WAKE_MCAST) | |
2179 | ocp_data |= MWF_EN; | |
2180 | if (wolopts & WAKE_ANY) | |
2181 | ocp_data |= LAN_WAKE_EN; | |
2182 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); | |
2183 | ||
2184 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2185 | ||
2186 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2187 | ocp_data &= ~MAGIC_EN; | |
2188 | if (wolopts & WAKE_MAGIC) | |
2189 | ocp_data |= MAGIC_EN; | |
2190 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); | |
2191 | ||
2192 | if (wolopts & WAKE_ANY) | |
2193 | device_set_wakeup_enable(&tp->udev->dev, true); | |
2194 | else | |
2195 | device_set_wakeup_enable(&tp->udev->dev, false); | |
2196 | } | |
2197 | ||
9a4be1bd | 2198 | static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) |
2199 | { | |
2200 | if (enable) { | |
2201 | u32 ocp_data; | |
2202 | ||
2203 | __rtl_set_wol(tp, WAKE_ANY); | |
2204 | ||
2205 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2206 | ||
2207 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2208 | ocp_data |= LINK_OFF_WAKE_EN; | |
2209 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2210 | ||
2211 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2212 | } else { | |
2213 | __rtl_set_wol(tp, tp->saved_wolopts); | |
2214 | } | |
2215 | } | |
2216 | ||
aa66a5f1 | 2217 | static void rtl_phy_reset(struct r8152 *tp) |
2218 | { | |
2219 | u16 data; | |
2220 | int i; | |
2221 | ||
2222 | clear_bit(PHY_RESET, &tp->flags); | |
2223 | ||
2224 | data = r8152_mdio_read(tp, MII_BMCR); | |
2225 | ||
2226 | /* don't reset again before the previous one complete */ | |
2227 | if (data & BMCR_RESET) | |
2228 | return; | |
2229 | ||
2230 | data |= BMCR_RESET; | |
2231 | r8152_mdio_write(tp, MII_BMCR, data); | |
2232 | ||
2233 | for (i = 0; i < 50; i++) { | |
2234 | msleep(20); | |
2235 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
2236 | break; | |
2237 | } | |
2238 | } | |
2239 | ||
4349968a | 2240 | static void rtl_clear_bp(struct r8152 *tp) |
2241 | { | |
2242 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0); | |
2243 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0); | |
2244 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0); | |
2245 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0); | |
2246 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0); | |
2247 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0); | |
2248 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0); | |
2249 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0); | |
8ddfa077 | 2250 | usleep_range(3000, 6000); |
4349968a | 2251 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0); |
2252 | ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0); | |
2253 | } | |
2254 | ||
2255 | static void r8153_clear_bp(struct r8152 *tp) | |
2256 | { | |
2257 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0); | |
2258 | ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0); | |
2259 | rtl_clear_bp(tp); | |
2260 | } | |
2261 | ||
2262 | static void r8153_teredo_off(struct r8152 *tp) | |
2263 | { | |
2264 | u32 ocp_data; | |
2265 | ||
2266 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
2267 | ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); | |
2268 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2269 | ||
2270 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); | |
2271 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); | |
2272 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); | |
2273 | } | |
2274 | ||
2275 | static void r8152b_disable_aldps(struct r8152 *tp) | |
2276 | { | |
2277 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); | |
2278 | msleep(20); | |
2279 | } | |
2280 | ||
2281 | static inline void r8152b_enable_aldps(struct r8152 *tp) | |
2282 | { | |
2283 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | | |
2284 | LINKENA | DIS_SDSAVE); | |
2285 | } | |
2286 | ||
d70b1137 | 2287 | static void rtl8152_disable(struct r8152 *tp) |
2288 | { | |
2289 | r8152b_disable_aldps(tp); | |
2290 | rtl_disable(tp); | |
2291 | r8152b_enable_aldps(tp); | |
2292 | } | |
2293 | ||
4349968a | 2294 | static void r8152b_hw_phy_cfg(struct r8152 *tp) |
2295 | { | |
f0cbe0ac | 2296 | u16 data; |
2297 | ||
2298 | data = r8152_mdio_read(tp, MII_BMCR); | |
2299 | if (data & BMCR_PDOWN) { | |
2300 | data &= ~BMCR_PDOWN; | |
2301 | r8152_mdio_write(tp, MII_BMCR, data); | |
2302 | } | |
2303 | ||
7e9da481 | 2304 | rtl_clear_bp(tp); |
2305 | ||
aa66a5f1 | 2306 | set_bit(PHY_RESET, &tp->flags); |
4349968a | 2307 | } |
2308 | ||
ac718b69 | 2309 | static void r8152b_exit_oob(struct r8152 *tp) |
2310 | { | |
db8515ef | 2311 | u32 ocp_data; |
2312 | int i; | |
ac718b69 | 2313 | |
2314 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2315 | ocp_data &= ~RCR_ACPT_ALL; | |
2316 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2317 | ||
00a5e360 | 2318 | rxdy_gated_en(tp, true); |
da9bd117 | 2319 | r8153_teredo_off(tp); |
7e9da481 | 2320 | r8152b_hw_phy_cfg(tp); |
ac718b69 | 2321 | |
2322 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2323 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); | |
2324 | ||
2325 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2326 | ocp_data &= ~NOW_IS_OOB; | |
2327 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2328 | ||
2329 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2330 | ocp_data &= ~MCU_BORW_EN; | |
2331 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2332 | ||
2333 | for (i = 0; i < 1000; i++) { | |
2334 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2335 | if (ocp_data & LINK_LIST_READY) | |
2336 | break; | |
8ddfa077 | 2337 | usleep_range(1000, 2000); |
ac718b69 | 2338 | } |
2339 | ||
2340 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2341 | ocp_data |= RE_INIT_LL; | |
2342 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2343 | ||
2344 | for (i = 0; i < 1000; i++) { | |
2345 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2346 | if (ocp_data & LINK_LIST_READY) | |
2347 | break; | |
8ddfa077 | 2348 | usleep_range(1000, 2000); |
ac718b69 | 2349 | } |
2350 | ||
2351 | rtl8152_nic_reset(tp); | |
2352 | ||
2353 | /* rx share fifo credit full threshold */ | |
2354 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2355 | ||
a3cc465d | 2356 | if (tp->udev->speed == USB_SPEED_FULL || |
2357 | tp->udev->speed == USB_SPEED_LOW) { | |
ac718b69 | 2358 | /* rx share fifo credit near full threshold */ |
2359 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2360 | RXFIFO_THR2_FULL); | |
2361 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2362 | RXFIFO_THR3_FULL); | |
2363 | } else { | |
2364 | /* rx share fifo credit near full threshold */ | |
2365 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2366 | RXFIFO_THR2_HIGH); | |
2367 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2368 | RXFIFO_THR3_HIGH); | |
2369 | } | |
2370 | ||
2371 | /* TX share fifo free credit full threshold */ | |
2372 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); | |
2373 | ||
2374 | ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); | |
8e1f51bd | 2375 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); |
ac718b69 | 2376 | ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, |
2377 | TEST_MODE_DISABLE | TX_SIZE_ADJUST1); | |
2378 | ||
c5554298 | 2379 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
ac718b69 | 2380 | |
2381 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2382 | ||
2383 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2384 | ocp_data |= TCR0_AUTO_FIFO; | |
2385 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2386 | } | |
2387 | ||
2388 | static void r8152b_enter_oob(struct r8152 *tp) | |
2389 | { | |
45f4a19f | 2390 | u32 ocp_data; |
2391 | int i; | |
ac718b69 | 2392 | |
2393 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2394 | ocp_data &= ~NOW_IS_OOB; | |
2395 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2396 | ||
2397 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); | |
2398 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); | |
2399 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); | |
2400 | ||
d70b1137 | 2401 | rtl_disable(tp); |
ac718b69 | 2402 | |
2403 | for (i = 0; i < 1000; i++) { | |
2404 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2405 | if (ocp_data & LINK_LIST_READY) | |
2406 | break; | |
8ddfa077 | 2407 | usleep_range(1000, 2000); |
ac718b69 | 2408 | } |
2409 | ||
2410 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2411 | ocp_data |= RE_INIT_LL; | |
2412 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2413 | ||
2414 | for (i = 0; i < 1000; i++) { | |
2415 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2416 | if (ocp_data & LINK_LIST_READY) | |
2417 | break; | |
8ddfa077 | 2418 | usleep_range(1000, 2000); |
ac718b69 | 2419 | } |
2420 | ||
2421 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2422 | ||
c5554298 | 2423 | rtl_rx_vlan_en(tp, true); |
ac718b69 | 2424 | |
2425 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2426 | ocp_data |= ALDPS_PROXY_MODE; | |
2427 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2428 | ||
2429 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2430 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2431 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2432 | ||
00a5e360 | 2433 | rxdy_gated_en(tp, false); |
ac718b69 | 2434 | |
2435 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2436 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2437 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2438 | } | |
2439 | ||
43779f8d | 2440 | static void r8153_hw_phy_cfg(struct r8152 *tp) |
2441 | { | |
2442 | u32 ocp_data; | |
2443 | u16 data; | |
2444 | ||
2445 | ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); | |
f0cbe0ac | 2446 | data = r8152_mdio_read(tp, MII_BMCR); |
2447 | if (data & BMCR_PDOWN) { | |
2448 | data &= ~BMCR_PDOWN; | |
2449 | r8152_mdio_write(tp, MII_BMCR, data); | |
2450 | } | |
43779f8d | 2451 | |
7e9da481 | 2452 | r8153_clear_bp(tp); |
2453 | ||
43779f8d | 2454 | if (tp->version == RTL_VER_03) { |
2455 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
2456 | data &= ~CTAP_SHORT_EN; | |
2457 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
2458 | } | |
2459 | ||
2460 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2461 | data |= EEE_CLKDIV_EN; | |
2462 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2463 | ||
2464 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
2465 | data |= EN_10M_BGOFF; | |
2466 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
2467 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2468 | data |= EN_10M_PLLOFF; | |
2469 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2470 | data = sram_read(tp, SRAM_IMPEDANCE); | |
2471 | data &= ~RX_DRIVING_MASK; | |
2472 | sram_write(tp, SRAM_IMPEDANCE, data); | |
2473 | ||
2474 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
2475 | ocp_data |= PFM_PWM_SWITCH; | |
2476 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
2477 | ||
2478 | data = sram_read(tp, SRAM_LPF_CFG); | |
2479 | data |= LPF_AUTO_TUNE; | |
2480 | sram_write(tp, SRAM_LPF_CFG, data); | |
2481 | ||
2482 | data = sram_read(tp, SRAM_10M_AMP1); | |
2483 | data |= GDAC_IB_UPALL; | |
2484 | sram_write(tp, SRAM_10M_AMP1, data); | |
2485 | data = sram_read(tp, SRAM_10M_AMP2); | |
2486 | data |= AMP_DN; | |
2487 | sram_write(tp, SRAM_10M_AMP2, data); | |
aa66a5f1 | 2488 | |
2489 | set_bit(PHY_RESET, &tp->flags); | |
43779f8d | 2490 | } |
2491 | ||
b9702723 | 2492 | static void r8153_u1u2en(struct r8152 *tp, bool enable) |
43779f8d | 2493 | { |
2494 | u8 u1u2[8]; | |
2495 | ||
2496 | if (enable) | |
2497 | memset(u1u2, 0xff, sizeof(u1u2)); | |
2498 | else | |
2499 | memset(u1u2, 0x00, sizeof(u1u2)); | |
2500 | ||
2501 | usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); | |
2502 | } | |
2503 | ||
b9702723 | 2504 | static void r8153_u2p3en(struct r8152 *tp, bool enable) |
43779f8d | 2505 | { |
2506 | u32 ocp_data; | |
2507 | ||
2508 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); | |
2509 | if (enable) | |
2510 | ocp_data |= U2P3_ENABLE; | |
2511 | else | |
2512 | ocp_data &= ~U2P3_ENABLE; | |
2513 | ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); | |
2514 | } | |
2515 | ||
b9702723 | 2516 | static void r8153_power_cut_en(struct r8152 *tp, bool enable) |
43779f8d | 2517 | { |
2518 | u32 ocp_data; | |
2519 | ||
2520 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
2521 | if (enable) | |
2522 | ocp_data |= PWR_EN | PHASE2_EN; | |
2523 | else | |
2524 | ocp_data &= ~(PWR_EN | PHASE2_EN); | |
2525 | ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
2526 | ||
2527 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
2528 | ocp_data &= ~PCUT_STATUS; | |
2529 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
2530 | } | |
2531 | ||
43779f8d | 2532 | static void r8153_first_init(struct r8152 *tp) |
2533 | { | |
2534 | u32 ocp_data; | |
2535 | int i; | |
2536 | ||
00a5e360 | 2537 | rxdy_gated_en(tp, true); |
43779f8d | 2538 | r8153_teredo_off(tp); |
2539 | ||
2540 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2541 | ocp_data &= ~RCR_ACPT_ALL; | |
2542 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2543 | ||
2544 | r8153_hw_phy_cfg(tp); | |
2545 | ||
2546 | rtl8152_nic_reset(tp); | |
2547 | ||
2548 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2549 | ocp_data &= ~NOW_IS_OOB; | |
2550 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2551 | ||
2552 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2553 | ocp_data &= ~MCU_BORW_EN; | |
2554 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2555 | ||
2556 | for (i = 0; i < 1000; i++) { | |
2557 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2558 | if (ocp_data & LINK_LIST_READY) | |
2559 | break; | |
8ddfa077 | 2560 | usleep_range(1000, 2000); |
43779f8d | 2561 | } |
2562 | ||
2563 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2564 | ocp_data |= RE_INIT_LL; | |
2565 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2566 | ||
2567 | for (i = 0; i < 1000; i++) { | |
2568 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2569 | if (ocp_data & LINK_LIST_READY) | |
2570 | break; | |
8ddfa077 | 2571 | usleep_range(1000, 2000); |
43779f8d | 2572 | } |
2573 | ||
c5554298 | 2574 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
43779f8d | 2575 | |
69b4b7a4 | 2576 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); |
2577 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); | |
43779f8d | 2578 | |
2579 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2580 | ocp_data |= TCR0_AUTO_FIFO; | |
2581 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2582 | ||
2583 | rtl8152_nic_reset(tp); | |
2584 | ||
2585 | /* rx share fifo credit full threshold */ | |
2586 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2587 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); | |
2588 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); | |
2589 | /* TX share fifo free credit full threshold */ | |
2590 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); | |
2591 | ||
9629e3c0 | 2592 | /* rx aggregation */ |
43779f8d | 2593 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
2594 | ocp_data &= ~RX_AGG_DISABLE; | |
2595 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
2596 | } | |
2597 | ||
2598 | static void r8153_enter_oob(struct r8152 *tp) | |
2599 | { | |
2600 | u32 ocp_data; | |
2601 | int i; | |
2602 | ||
2603 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2604 | ocp_data &= ~NOW_IS_OOB; | |
2605 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2606 | ||
d70b1137 | 2607 | rtl_disable(tp); |
43779f8d | 2608 | |
2609 | for (i = 0; i < 1000; i++) { | |
2610 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2611 | if (ocp_data & LINK_LIST_READY) | |
2612 | break; | |
8ddfa077 | 2613 | usleep_range(1000, 2000); |
43779f8d | 2614 | } |
2615 | ||
2616 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2617 | ocp_data |= RE_INIT_LL; | |
2618 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2619 | ||
2620 | for (i = 0; i < 1000; i++) { | |
2621 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2622 | if (ocp_data & LINK_LIST_READY) | |
2623 | break; | |
8ddfa077 | 2624 | usleep_range(1000, 2000); |
43779f8d | 2625 | } |
2626 | ||
69b4b7a4 | 2627 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); |
43779f8d | 2628 | |
43779f8d | 2629 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); |
2630 | ocp_data &= ~TEREDO_WAKE_MASK; | |
2631 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2632 | ||
c5554298 | 2633 | rtl_rx_vlan_en(tp, true); |
43779f8d | 2634 | |
2635 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2636 | ocp_data |= ALDPS_PROXY_MODE; | |
2637 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2638 | ||
2639 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2640 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2641 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2642 | ||
00a5e360 | 2643 | rxdy_gated_en(tp, false); |
43779f8d | 2644 | |
2645 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2646 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2647 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2648 | } | |
2649 | ||
2650 | static void r8153_disable_aldps(struct r8152 *tp) | |
2651 | { | |
2652 | u16 data; | |
2653 | ||
2654 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2655 | data &= ~EN_ALDPS; | |
2656 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2657 | msleep(20); | |
2658 | } | |
2659 | ||
2660 | static void r8153_enable_aldps(struct r8152 *tp) | |
2661 | { | |
2662 | u16 data; | |
2663 | ||
2664 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2665 | data |= EN_ALDPS; | |
2666 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2667 | } | |
2668 | ||
d70b1137 | 2669 | static void rtl8153_disable(struct r8152 *tp) |
2670 | { | |
2671 | r8153_disable_aldps(tp); | |
2672 | rtl_disable(tp); | |
2673 | r8153_enable_aldps(tp); | |
2674 | } | |
2675 | ||
ac718b69 | 2676 | static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) |
2677 | { | |
43779f8d | 2678 | u16 bmcr, anar, gbcr; |
ac718b69 | 2679 | int ret = 0; |
2680 | ||
2681 | cancel_delayed_work_sync(&tp->schedule); | |
2682 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
2683 | anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | | |
2684 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
43779f8d | 2685 | if (tp->mii.supports_gmii) { |
2686 | gbcr = r8152_mdio_read(tp, MII_CTRL1000); | |
2687 | gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); | |
2688 | } else { | |
2689 | gbcr = 0; | |
2690 | } | |
ac718b69 | 2691 | |
2692 | if (autoneg == AUTONEG_DISABLE) { | |
2693 | if (speed == SPEED_10) { | |
2694 | bmcr = 0; | |
2695 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2696 | } else if (speed == SPEED_100) { | |
2697 | bmcr = BMCR_SPEED100; | |
2698 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
43779f8d | 2699 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2700 | bmcr = BMCR_SPEED1000; | |
2701 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
ac718b69 | 2702 | } else { |
2703 | ret = -EINVAL; | |
2704 | goto out; | |
2705 | } | |
2706 | ||
2707 | if (duplex == DUPLEX_FULL) | |
2708 | bmcr |= BMCR_FULLDPLX; | |
2709 | } else { | |
2710 | if (speed == SPEED_10) { | |
2711 | if (duplex == DUPLEX_FULL) | |
2712 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2713 | else | |
2714 | anar |= ADVERTISE_10HALF; | |
2715 | } else if (speed == SPEED_100) { | |
2716 | if (duplex == DUPLEX_FULL) { | |
2717 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2718 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2719 | } else { | |
2720 | anar |= ADVERTISE_10HALF; | |
2721 | anar |= ADVERTISE_100HALF; | |
2722 | } | |
43779f8d | 2723 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2724 | if (duplex == DUPLEX_FULL) { | |
2725 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2726 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2727 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
2728 | } else { | |
2729 | anar |= ADVERTISE_10HALF; | |
2730 | anar |= ADVERTISE_100HALF; | |
2731 | gbcr |= ADVERTISE_1000HALF; | |
2732 | } | |
ac718b69 | 2733 | } else { |
2734 | ret = -EINVAL; | |
2735 | goto out; | |
2736 | } | |
2737 | ||
2738 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; | |
2739 | } | |
2740 | ||
aa66a5f1 | 2741 | if (test_bit(PHY_RESET, &tp->flags)) |
2742 | bmcr |= BMCR_RESET; | |
2743 | ||
43779f8d | 2744 | if (tp->mii.supports_gmii) |
2745 | r8152_mdio_write(tp, MII_CTRL1000, gbcr); | |
2746 | ||
ac718b69 | 2747 | r8152_mdio_write(tp, MII_ADVERTISE, anar); |
2748 | r8152_mdio_write(tp, MII_BMCR, bmcr); | |
2749 | ||
aa66a5f1 | 2750 | if (test_bit(PHY_RESET, &tp->flags)) { |
2751 | int i; | |
2752 | ||
2753 | clear_bit(PHY_RESET, &tp->flags); | |
2754 | for (i = 0; i < 50; i++) { | |
2755 | msleep(20); | |
2756 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
2757 | break; | |
2758 | } | |
2759 | } | |
2760 | ||
ac718b69 | 2761 | out: |
ac718b69 | 2762 | |
2763 | return ret; | |
2764 | } | |
2765 | ||
d70b1137 | 2766 | static void rtl8152_up(struct r8152 *tp) |
2767 | { | |
2768 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
2769 | return; | |
2770 | ||
2771 | r8152b_disable_aldps(tp); | |
2772 | r8152b_exit_oob(tp); | |
2773 | r8152b_enable_aldps(tp); | |
2774 | } | |
2775 | ||
ac718b69 | 2776 | static void rtl8152_down(struct r8152 *tp) |
2777 | { | |
6871438c | 2778 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2779 | rtl_drop_queued_tx(tp); | |
2780 | return; | |
2781 | } | |
2782 | ||
00a5e360 | 2783 | r8152_power_cut_en(tp, false); |
ac718b69 | 2784 | r8152b_disable_aldps(tp); |
2785 | r8152b_enter_oob(tp); | |
2786 | r8152b_enable_aldps(tp); | |
2787 | } | |
2788 | ||
d70b1137 | 2789 | static void rtl8153_up(struct r8152 *tp) |
2790 | { | |
2791 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
2792 | return; | |
2793 | ||
2794 | r8153_disable_aldps(tp); | |
2795 | r8153_first_init(tp); | |
2796 | r8153_enable_aldps(tp); | |
2797 | } | |
2798 | ||
43779f8d | 2799 | static void rtl8153_down(struct r8152 *tp) |
2800 | { | |
6871438c | 2801 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2802 | rtl_drop_queued_tx(tp); | |
2803 | return; | |
2804 | } | |
2805 | ||
b9702723 | 2806 | r8153_u1u2en(tp, false); |
2807 | r8153_power_cut_en(tp, false); | |
43779f8d | 2808 | r8153_disable_aldps(tp); |
2809 | r8153_enter_oob(tp); | |
2810 | r8153_enable_aldps(tp); | |
2811 | } | |
2812 | ||
ac718b69 | 2813 | static void set_carrier(struct r8152 *tp) |
2814 | { | |
2815 | struct net_device *netdev = tp->netdev; | |
2816 | u8 speed; | |
2817 | ||
40a82917 | 2818 | clear_bit(RTL8152_LINK_CHG, &tp->flags); |
ac718b69 | 2819 | speed = rtl8152_get_speed(tp); |
2820 | ||
2821 | if (speed & LINK_STATUS) { | |
2822 | if (!(tp->speed & LINK_STATUS)) { | |
c81229c9 | 2823 | tp->rtl_ops.enable(tp); |
ac718b69 | 2824 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
2825 | netif_carrier_on(netdev); | |
2826 | } | |
2827 | } else { | |
2828 | if (tp->speed & LINK_STATUS) { | |
2829 | netif_carrier_off(netdev); | |
ebc2ec48 | 2830 | tasklet_disable(&tp->tl); |
c81229c9 | 2831 | tp->rtl_ops.disable(tp); |
ebc2ec48 | 2832 | tasklet_enable(&tp->tl); |
ac718b69 | 2833 | } |
2834 | } | |
2835 | tp->speed = speed; | |
2836 | } | |
2837 | ||
2838 | static void rtl_work_func_t(struct work_struct *work) | |
2839 | { | |
2840 | struct r8152 *tp = container_of(work, struct r8152, schedule.work); | |
2841 | ||
9a4be1bd | 2842 | if (usb_autopm_get_interface(tp->intf) < 0) |
2843 | return; | |
2844 | ||
ac718b69 | 2845 | if (!test_bit(WORK_ENABLE, &tp->flags)) |
2846 | goto out1; | |
2847 | ||
2848 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
2849 | goto out1; | |
2850 | ||
40a82917 | 2851 | if (test_bit(RTL8152_LINK_CHG, &tp->flags)) |
2852 | set_carrier(tp); | |
ac718b69 | 2853 | |
2854 | if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) | |
2855 | _rtl8152_set_rx_mode(tp->netdev); | |
2856 | ||
0c3121fc | 2857 | if (test_bit(SCHEDULE_TASKLET, &tp->flags) && |
2858 | (tp->speed & LINK_STATUS)) { | |
2859 | clear_bit(SCHEDULE_TASKLET, &tp->flags); | |
2860 | tasklet_schedule(&tp->tl); | |
2861 | } | |
aa66a5f1 | 2862 | |
2863 | if (test_bit(PHY_RESET, &tp->flags)) | |
2864 | rtl_phy_reset(tp); | |
2865 | ||
ac718b69 | 2866 | out1: |
9a4be1bd | 2867 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 2868 | } |
2869 | ||
2870 | static int rtl8152_open(struct net_device *netdev) | |
2871 | { | |
2872 | struct r8152 *tp = netdev_priv(netdev); | |
2873 | int res = 0; | |
2874 | ||
7e9da481 | 2875 | res = alloc_all_mem(tp); |
2876 | if (res) | |
2877 | goto out; | |
2878 | ||
9a4be1bd | 2879 | res = usb_autopm_get_interface(tp->intf); |
2880 | if (res < 0) { | |
2881 | free_all_mem(tp); | |
2882 | goto out; | |
2883 | } | |
2884 | ||
2885 | /* The WORK_ENABLE may be set when autoresume occurs */ | |
2886 | if (test_bit(WORK_ENABLE, &tp->flags)) { | |
2887 | clear_bit(WORK_ENABLE, &tp->flags); | |
2888 | usb_kill_urb(tp->intr_urb); | |
2889 | cancel_delayed_work_sync(&tp->schedule); | |
2890 | if (tp->speed & LINK_STATUS) | |
2891 | tp->rtl_ops.disable(tp); | |
2892 | } | |
2893 | ||
7e9da481 | 2894 | tp->rtl_ops.up(tp); |
2895 | ||
3d55f44f | 2896 | rtl8152_set_speed(tp, AUTONEG_ENABLE, |
2897 | tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, | |
2898 | DUPLEX_FULL); | |
2899 | tp->speed = 0; | |
2900 | netif_carrier_off(netdev); | |
2901 | netif_start_queue(netdev); | |
2902 | set_bit(WORK_ENABLE, &tp->flags); | |
db8515ef | 2903 | |
40a82917 | 2904 | res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
2905 | if (res) { | |
2906 | if (res == -ENODEV) | |
2907 | netif_device_detach(tp->netdev); | |
4a8deae2 HW |
2908 | netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", |
2909 | res); | |
7e9da481 | 2910 | free_all_mem(tp); |
ac718b69 | 2911 | } |
2912 | ||
9a4be1bd | 2913 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 2914 | |
7e9da481 | 2915 | out: |
ac718b69 | 2916 | return res; |
2917 | } | |
2918 | ||
2919 | static int rtl8152_close(struct net_device *netdev) | |
2920 | { | |
2921 | struct r8152 *tp = netdev_priv(netdev); | |
2922 | int res = 0; | |
2923 | ||
2924 | clear_bit(WORK_ENABLE, &tp->flags); | |
3d55f44f | 2925 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 2926 | cancel_delayed_work_sync(&tp->schedule); |
2927 | netif_stop_queue(netdev); | |
9a4be1bd | 2928 | |
2929 | res = usb_autopm_get_interface(tp->intf); | |
2930 | if (res < 0) { | |
2931 | rtl_drop_queued_tx(tp); | |
2932 | } else { | |
b209af99 | 2933 | /* The autosuspend may have been enabled and wouldn't |
9a4be1bd | 2934 | * be disable when autoresume occurs, because the |
2935 | * netif_running() would be false. | |
2936 | */ | |
2937 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { | |
2938 | rtl_runtime_suspend_enable(tp, false); | |
2939 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
2940 | } | |
2941 | ||
2942 | tasklet_disable(&tp->tl); | |
2943 | tp->rtl_ops.down(tp); | |
2944 | tasklet_enable(&tp->tl); | |
2945 | usb_autopm_put_interface(tp->intf); | |
2946 | } | |
ac718b69 | 2947 | |
7e9da481 | 2948 | free_all_mem(tp); |
2949 | ||
ac718b69 | 2950 | return res; |
2951 | } | |
2952 | ||
ac718b69 | 2953 | static void r8152b_enable_eee(struct r8152 *tp) |
2954 | { | |
45f4a19f | 2955 | u32 ocp_data; |
ac718b69 | 2956 | |
2957 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
2958 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
2959 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
2960 | ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN | | |
2961 | EEE_10_CAP | EEE_NWAY_EN | | |
2962 | TX_QUIET_EN | RX_QUIET_EN | | |
4c4a6b1b | 2963 | sd_rise_time(1) | RG_RXLPI_MSK_HFDUP | |
ac718b69 | 2964 | SDFALLTIME); |
2965 | ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN | | |
2966 | RG_LDVQUIET_EN | RG_CKRSEL | | |
2967 | RG_EEEPRG_EN); | |
4c4a6b1b | 2968 | ocp_reg_write(tp, OCP_EEE_CONFIG3, fast_snr(42) | RG_LFS_SEL | MSK_PH); |
2969 | ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | MDIO_MMD_AN); | |
2970 | ocp_reg_write(tp, OCP_EEE_DATA, MDIO_AN_EEE_ADV); | |
2971 | ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | MDIO_MMD_AN); | |
2972 | ocp_reg_write(tp, OCP_EEE_DATA, MDIO_EEE_100TX); | |
ac718b69 | 2973 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); |
2974 | } | |
2975 | ||
43779f8d | 2976 | static void r8153_enable_eee(struct r8152 *tp) |
2977 | { | |
2978 | u32 ocp_data; | |
2979 | u16 data; | |
2980 | ||
2981 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
2982 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
2983 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
2984 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
2985 | data |= EEE10_EN; | |
2986 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
4c4a6b1b | 2987 | data = ocp_reg_read(tp, OCP_EEE_ADV); |
2988 | data |= MDIO_EEE_1000T | MDIO_EEE_100TX; | |
2989 | ocp_reg_write(tp, OCP_EEE_ADV, data); | |
43779f8d | 2990 | } |
2991 | ||
ac718b69 | 2992 | static void r8152b_enable_fc(struct r8152 *tp) |
2993 | { | |
2994 | u16 anar; | |
2995 | ||
2996 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
2997 | anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
2998 | r8152_mdio_write(tp, MII_ADVERTISE, anar); | |
2999 | } | |
3000 | ||
4f1d4d54 | 3001 | static void rtl_tally_reset(struct r8152 *tp) |
3002 | { | |
3003 | u32 ocp_data; | |
3004 | ||
3005 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); | |
3006 | ocp_data |= TALLY_RESET; | |
3007 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); | |
3008 | } | |
3009 | ||
ac718b69 | 3010 | static void r8152b_init(struct r8152 *tp) |
3011 | { | |
ebc2ec48 | 3012 | u32 ocp_data; |
ac718b69 | 3013 | |
6871438c | 3014 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3015 | return; | |
3016 | ||
d70b1137 | 3017 | r8152b_disable_aldps(tp); |
3018 | ||
ac718b69 | 3019 | if (tp->version == RTL_VER_01) { |
3020 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); | |
3021 | ocp_data &= ~LED_MODE_MASK; | |
3022 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
3023 | } | |
3024 | ||
00a5e360 | 3025 | r8152_power_cut_en(tp, false); |
ac718b69 | 3026 | |
ac718b69 | 3027 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); |
3028 | ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; | |
3029 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
3030 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); | |
3031 | ocp_data &= ~MCU_CLK_RATIO_MASK; | |
3032 | ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; | |
3033 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); | |
3034 | ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | | |
3035 | SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; | |
3036 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); | |
3037 | ||
3038 | r8152b_enable_eee(tp); | |
3039 | r8152b_enable_aldps(tp); | |
3040 | r8152b_enable_fc(tp); | |
4f1d4d54 | 3041 | rtl_tally_reset(tp); |
ac718b69 | 3042 | |
ebc2ec48 | 3043 | /* enable rx aggregation */ |
ac718b69 | 3044 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
ebc2ec48 | 3045 | ocp_data &= ~RX_AGG_DISABLE; |
ac718b69 | 3046 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
3047 | } | |
3048 | ||
43779f8d | 3049 | static void r8153_init(struct r8152 *tp) |
3050 | { | |
3051 | u32 ocp_data; | |
3052 | int i; | |
3053 | ||
6871438c | 3054 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3055 | return; | |
3056 | ||
d70b1137 | 3057 | r8153_disable_aldps(tp); |
b9702723 | 3058 | r8153_u1u2en(tp, false); |
43779f8d | 3059 | |
3060 | for (i = 0; i < 500; i++) { | |
3061 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
3062 | AUTOLOAD_DONE) | |
3063 | break; | |
3064 | msleep(20); | |
3065 | } | |
3066 | ||
3067 | for (i = 0; i < 500; i++) { | |
3068 | ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; | |
3069 | if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) | |
3070 | break; | |
3071 | msleep(20); | |
3072 | } | |
3073 | ||
b9702723 | 3074 | r8153_u2p3en(tp, false); |
43779f8d | 3075 | |
3076 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); | |
3077 | ocp_data &= ~TIMER11_EN; | |
3078 | ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); | |
3079 | ||
43779f8d | 3080 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); |
3081 | ocp_data &= ~LED_MODE_MASK; | |
3082 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
3083 | ||
3084 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL); | |
3085 | ocp_data &= ~LPM_TIMER_MASK; | |
3086 | if (tp->udev->speed == USB_SPEED_SUPER) | |
3087 | ocp_data |= LPM_TIMER_500US; | |
3088 | else | |
3089 | ocp_data |= LPM_TIMER_500MS; | |
3090 | ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); | |
3091 | ||
3092 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); | |
3093 | ocp_data &= ~SEN_VAL_MASK; | |
3094 | ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; | |
3095 | ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); | |
3096 | ||
b9702723 | 3097 | r8153_power_cut_en(tp, false); |
3098 | r8153_u1u2en(tp, true); | |
43779f8d | 3099 | |
43779f8d | 3100 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO); |
3101 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO); | |
3102 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, | |
3103 | PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | | |
3104 | U1U2_SPDWN_EN | L1_SPDWN_EN); | |
3105 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, | |
3106 | PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | | |
3107 | TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN | | |
3108 | EEE_SPDWN_EN); | |
3109 | ||
3110 | r8153_enable_eee(tp); | |
3111 | r8153_enable_aldps(tp); | |
3112 | r8152b_enable_fc(tp); | |
4f1d4d54 | 3113 | rtl_tally_reset(tp); |
43779f8d | 3114 | } |
3115 | ||
ac718b69 | 3116 | static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) |
3117 | { | |
3118 | struct r8152 *tp = usb_get_intfdata(intf); | |
3119 | ||
9a4be1bd | 3120 | if (PMSG_IS_AUTO(message)) |
3121 | set_bit(SELECTIVE_SUSPEND, &tp->flags); | |
3122 | else | |
3123 | netif_device_detach(tp->netdev); | |
ac718b69 | 3124 | |
3125 | if (netif_running(tp->netdev)) { | |
3126 | clear_bit(WORK_ENABLE, &tp->flags); | |
40a82917 | 3127 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 3128 | cancel_delayed_work_sync(&tp->schedule); |
9a4be1bd | 3129 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
3130 | rtl_runtime_suspend_enable(tp, true); | |
3131 | } else { | |
3132 | tasklet_disable(&tp->tl); | |
3133 | tp->rtl_ops.down(tp); | |
3134 | tasklet_enable(&tp->tl); | |
3135 | } | |
ac718b69 | 3136 | } |
3137 | ||
ac718b69 | 3138 | return 0; |
3139 | } | |
3140 | ||
3141 | static int rtl8152_resume(struct usb_interface *intf) | |
3142 | { | |
3143 | struct r8152 *tp = usb_get_intfdata(intf); | |
3144 | ||
9a4be1bd | 3145 | if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
3146 | tp->rtl_ops.init(tp); | |
3147 | netif_device_attach(tp->netdev); | |
3148 | } | |
3149 | ||
ac718b69 | 3150 | if (netif_running(tp->netdev)) { |
9a4be1bd | 3151 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
3152 | rtl_runtime_suspend_enable(tp, false); | |
3153 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
3154 | if (tp->speed & LINK_STATUS) | |
3155 | tp->rtl_ops.disable(tp); | |
3156 | } else { | |
3157 | tp->rtl_ops.up(tp); | |
3158 | rtl8152_set_speed(tp, AUTONEG_ENABLE, | |
b209af99 | 3159 | tp->mii.supports_gmii ? |
3160 | SPEED_1000 : SPEED_100, | |
3161 | DUPLEX_FULL); | |
9a4be1bd | 3162 | } |
40a82917 | 3163 | tp->speed = 0; |
3164 | netif_carrier_off(tp->netdev); | |
ac718b69 | 3165 | set_bit(WORK_ENABLE, &tp->flags); |
40a82917 | 3166 | usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
ac718b69 | 3167 | } |
3168 | ||
3169 | return 0; | |
3170 | } | |
3171 | ||
21ff2e89 | 3172 | static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
3173 | { | |
3174 | struct r8152 *tp = netdev_priv(dev); | |
3175 | ||
9a4be1bd | 3176 | if (usb_autopm_get_interface(tp->intf) < 0) |
3177 | return; | |
3178 | ||
21ff2e89 | 3179 | wol->supported = WAKE_ANY; |
3180 | wol->wolopts = __rtl_get_wol(tp); | |
9a4be1bd | 3181 | |
3182 | usb_autopm_put_interface(tp->intf); | |
21ff2e89 | 3183 | } |
3184 | ||
3185 | static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
3186 | { | |
3187 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 3188 | int ret; |
3189 | ||
3190 | ret = usb_autopm_get_interface(tp->intf); | |
3191 | if (ret < 0) | |
3192 | goto out_set_wol; | |
21ff2e89 | 3193 | |
3194 | __rtl_set_wol(tp, wol->wolopts); | |
3195 | tp->saved_wolopts = wol->wolopts & WAKE_ANY; | |
3196 | ||
9a4be1bd | 3197 | usb_autopm_put_interface(tp->intf); |
3198 | ||
3199 | out_set_wol: | |
3200 | return ret; | |
21ff2e89 | 3201 | } |
3202 | ||
a5ec27c1 | 3203 | static u32 rtl8152_get_msglevel(struct net_device *dev) |
3204 | { | |
3205 | struct r8152 *tp = netdev_priv(dev); | |
3206 | ||
3207 | return tp->msg_enable; | |
3208 | } | |
3209 | ||
3210 | static void rtl8152_set_msglevel(struct net_device *dev, u32 value) | |
3211 | { | |
3212 | struct r8152 *tp = netdev_priv(dev); | |
3213 | ||
3214 | tp->msg_enable = value; | |
3215 | } | |
3216 | ||
ac718b69 | 3217 | static void rtl8152_get_drvinfo(struct net_device *netdev, |
3218 | struct ethtool_drvinfo *info) | |
3219 | { | |
3220 | struct r8152 *tp = netdev_priv(netdev); | |
3221 | ||
b0b46c77 | 3222 | strlcpy(info->driver, MODULENAME, sizeof(info->driver)); |
3223 | strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); | |
ac718b69 | 3224 | usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); |
3225 | } | |
3226 | ||
3227 | static | |
3228 | int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) | |
3229 | { | |
3230 | struct r8152 *tp = netdev_priv(netdev); | |
3231 | ||
3232 | if (!tp->mii.mdio_read) | |
3233 | return -EOPNOTSUPP; | |
3234 | ||
3235 | return mii_ethtool_gset(&tp->mii, cmd); | |
3236 | } | |
3237 | ||
3238 | static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
3239 | { | |
3240 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 3241 | int ret; |
3242 | ||
3243 | ret = usb_autopm_get_interface(tp->intf); | |
3244 | if (ret < 0) | |
3245 | goto out; | |
ac718b69 | 3246 | |
9a4be1bd | 3247 | ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); |
3248 | ||
3249 | usb_autopm_put_interface(tp->intf); | |
3250 | ||
3251 | out: | |
3252 | return ret; | |
ac718b69 | 3253 | } |
3254 | ||
4f1d4d54 | 3255 | static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { |
3256 | "tx_packets", | |
3257 | "rx_packets", | |
3258 | "tx_errors", | |
3259 | "rx_errors", | |
3260 | "rx_missed", | |
3261 | "align_errors", | |
3262 | "tx_single_collisions", | |
3263 | "tx_multi_collisions", | |
3264 | "rx_unicast", | |
3265 | "rx_broadcast", | |
3266 | "rx_multicast", | |
3267 | "tx_aborted", | |
3268 | "tx_underrun", | |
3269 | }; | |
3270 | ||
3271 | static int rtl8152_get_sset_count(struct net_device *dev, int sset) | |
3272 | { | |
3273 | switch (sset) { | |
3274 | case ETH_SS_STATS: | |
3275 | return ARRAY_SIZE(rtl8152_gstrings); | |
3276 | default: | |
3277 | return -EOPNOTSUPP; | |
3278 | } | |
3279 | } | |
3280 | ||
3281 | static void rtl8152_get_ethtool_stats(struct net_device *dev, | |
3282 | struct ethtool_stats *stats, u64 *data) | |
3283 | { | |
3284 | struct r8152 *tp = netdev_priv(dev); | |
3285 | struct tally_counter tally; | |
3286 | ||
0b030244 | 3287 | if (usb_autopm_get_interface(tp->intf) < 0) |
3288 | return; | |
3289 | ||
4f1d4d54 | 3290 | generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); |
3291 | ||
0b030244 | 3292 | usb_autopm_put_interface(tp->intf); |
3293 | ||
4f1d4d54 | 3294 | data[0] = le64_to_cpu(tally.tx_packets); |
3295 | data[1] = le64_to_cpu(tally.rx_packets); | |
3296 | data[2] = le64_to_cpu(tally.tx_errors); | |
3297 | data[3] = le32_to_cpu(tally.rx_errors); | |
3298 | data[4] = le16_to_cpu(tally.rx_missed); | |
3299 | data[5] = le16_to_cpu(tally.align_errors); | |
3300 | data[6] = le32_to_cpu(tally.tx_one_collision); | |
3301 | data[7] = le32_to_cpu(tally.tx_multi_collision); | |
3302 | data[8] = le64_to_cpu(tally.rx_unicast); | |
3303 | data[9] = le64_to_cpu(tally.rx_broadcast); | |
3304 | data[10] = le32_to_cpu(tally.rx_multicast); | |
3305 | data[11] = le16_to_cpu(tally.tx_aborted); | |
3306 | data[12] = le16_to_cpu(tally.tx_underun); | |
3307 | } | |
3308 | ||
3309 | static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
3310 | { | |
3311 | switch (stringset) { | |
3312 | case ETH_SS_STATS: | |
3313 | memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); | |
3314 | break; | |
3315 | } | |
3316 | } | |
3317 | ||
ac718b69 | 3318 | static struct ethtool_ops ops = { |
3319 | .get_drvinfo = rtl8152_get_drvinfo, | |
3320 | .get_settings = rtl8152_get_settings, | |
3321 | .set_settings = rtl8152_set_settings, | |
3322 | .get_link = ethtool_op_get_link, | |
a5ec27c1 | 3323 | .get_msglevel = rtl8152_get_msglevel, |
3324 | .set_msglevel = rtl8152_set_msglevel, | |
21ff2e89 | 3325 | .get_wol = rtl8152_get_wol, |
3326 | .set_wol = rtl8152_set_wol, | |
4f1d4d54 | 3327 | .get_strings = rtl8152_get_strings, |
3328 | .get_sset_count = rtl8152_get_sset_count, | |
3329 | .get_ethtool_stats = rtl8152_get_ethtool_stats, | |
ac718b69 | 3330 | }; |
3331 | ||
3332 | static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) | |
3333 | { | |
3334 | struct r8152 *tp = netdev_priv(netdev); | |
3335 | struct mii_ioctl_data *data = if_mii(rq); | |
9a4be1bd | 3336 | int res; |
3337 | ||
6871438c | 3338 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3339 | return -ENODEV; | |
3340 | ||
9a4be1bd | 3341 | res = usb_autopm_get_interface(tp->intf); |
3342 | if (res < 0) | |
3343 | goto out; | |
ac718b69 | 3344 | |
3345 | switch (cmd) { | |
3346 | case SIOCGMIIPHY: | |
3347 | data->phy_id = R8152_PHY_ID; /* Internal PHY */ | |
3348 | break; | |
3349 | ||
3350 | case SIOCGMIIREG: | |
3351 | data->val_out = r8152_mdio_read(tp, data->reg_num); | |
3352 | break; | |
3353 | ||
3354 | case SIOCSMIIREG: | |
3355 | if (!capable(CAP_NET_ADMIN)) { | |
3356 | res = -EPERM; | |
3357 | break; | |
3358 | } | |
3359 | r8152_mdio_write(tp, data->reg_num, data->val_in); | |
3360 | break; | |
3361 | ||
3362 | default: | |
3363 | res = -EOPNOTSUPP; | |
3364 | } | |
3365 | ||
9a4be1bd | 3366 | usb_autopm_put_interface(tp->intf); |
3367 | ||
3368 | out: | |
ac718b69 | 3369 | return res; |
3370 | } | |
3371 | ||
69b4b7a4 | 3372 | static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) |
3373 | { | |
3374 | struct r8152 *tp = netdev_priv(dev); | |
3375 | ||
3376 | switch (tp->version) { | |
3377 | case RTL_VER_01: | |
3378 | case RTL_VER_02: | |
3379 | return eth_change_mtu(dev, new_mtu); | |
3380 | default: | |
3381 | break; | |
3382 | } | |
3383 | ||
3384 | if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU) | |
3385 | return -EINVAL; | |
3386 | ||
3387 | dev->mtu = new_mtu; | |
3388 | ||
3389 | return 0; | |
3390 | } | |
3391 | ||
ac718b69 | 3392 | static const struct net_device_ops rtl8152_netdev_ops = { |
3393 | .ndo_open = rtl8152_open, | |
3394 | .ndo_stop = rtl8152_close, | |
3395 | .ndo_do_ioctl = rtl8152_ioctl, | |
3396 | .ndo_start_xmit = rtl8152_start_xmit, | |
3397 | .ndo_tx_timeout = rtl8152_tx_timeout, | |
c5554298 | 3398 | .ndo_set_features = rtl8152_set_features, |
ac718b69 | 3399 | .ndo_set_rx_mode = rtl8152_set_rx_mode, |
3400 | .ndo_set_mac_address = rtl8152_set_mac_address, | |
69b4b7a4 | 3401 | .ndo_change_mtu = rtl8152_change_mtu, |
ac718b69 | 3402 | .ndo_validate_addr = eth_validate_addr, |
3403 | }; | |
3404 | ||
3405 | static void r8152b_get_version(struct r8152 *tp) | |
3406 | { | |
3407 | u32 ocp_data; | |
3408 | u16 version; | |
3409 | ||
3410 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); | |
3411 | version = (u16)(ocp_data & VERSION_MASK); | |
3412 | ||
3413 | switch (version) { | |
3414 | case 0x4c00: | |
3415 | tp->version = RTL_VER_01; | |
3416 | break; | |
3417 | case 0x4c10: | |
3418 | tp->version = RTL_VER_02; | |
3419 | break; | |
43779f8d | 3420 | case 0x5c00: |
3421 | tp->version = RTL_VER_03; | |
3422 | tp->mii.supports_gmii = 1; | |
3423 | break; | |
3424 | case 0x5c10: | |
3425 | tp->version = RTL_VER_04; | |
3426 | tp->mii.supports_gmii = 1; | |
3427 | break; | |
3428 | case 0x5c20: | |
3429 | tp->version = RTL_VER_05; | |
3430 | tp->mii.supports_gmii = 1; | |
3431 | break; | |
ac718b69 | 3432 | default: |
3433 | netif_info(tp, probe, tp->netdev, | |
3434 | "Unknown version 0x%04x\n", version); | |
3435 | break; | |
3436 | } | |
3437 | } | |
3438 | ||
e3fe0b1a | 3439 | static void rtl8152_unload(struct r8152 *tp) |
3440 | { | |
6871438c | 3441 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3442 | return; | |
3443 | ||
00a5e360 | 3444 | if (tp->version != RTL_VER_01) |
3445 | r8152_power_cut_en(tp, true); | |
e3fe0b1a | 3446 | } |
3447 | ||
43779f8d | 3448 | static void rtl8153_unload(struct r8152 *tp) |
3449 | { | |
6871438c | 3450 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3451 | return; | |
3452 | ||
b9702723 | 3453 | r8153_power_cut_en(tp, true); |
43779f8d | 3454 | } |
3455 | ||
31ca1dec | 3456 | static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id) |
c81229c9 | 3457 | { |
3458 | struct rtl_ops *ops = &tp->rtl_ops; | |
31ca1dec | 3459 | int ret = -ENODEV; |
c81229c9 | 3460 | |
3461 | switch (id->idVendor) { | |
3462 | case VENDOR_ID_REALTEK: | |
3463 | switch (id->idProduct) { | |
3464 | case PRODUCT_ID_RTL8152: | |
3465 | ops->init = r8152b_init; | |
3466 | ops->enable = rtl8152_enable; | |
3467 | ops->disable = rtl8152_disable; | |
d70b1137 | 3468 | ops->up = rtl8152_up; |
c81229c9 | 3469 | ops->down = rtl8152_down; |
3470 | ops->unload = rtl8152_unload; | |
31ca1dec | 3471 | ret = 0; |
c81229c9 | 3472 | break; |
43779f8d | 3473 | case PRODUCT_ID_RTL8153: |
3474 | ops->init = r8153_init; | |
3475 | ops->enable = rtl8153_enable; | |
d70b1137 | 3476 | ops->disable = rtl8153_disable; |
3477 | ops->up = rtl8153_up; | |
43779f8d | 3478 | ops->down = rtl8153_down; |
3479 | ops->unload = rtl8153_unload; | |
31ca1dec | 3480 | ret = 0; |
43779f8d | 3481 | break; |
3482 | default: | |
43779f8d | 3483 | break; |
3484 | } | |
3485 | break; | |
3486 | ||
3487 | case VENDOR_ID_SAMSUNG: | |
3488 | switch (id->idProduct) { | |
3489 | case PRODUCT_ID_SAMSUNG: | |
3490 | ops->init = r8153_init; | |
3491 | ops->enable = rtl8153_enable; | |
d70b1137 | 3492 | ops->disable = rtl8153_disable; |
3493 | ops->up = rtl8153_up; | |
43779f8d | 3494 | ops->down = rtl8153_down; |
3495 | ops->unload = rtl8153_unload; | |
31ca1dec | 3496 | ret = 0; |
43779f8d | 3497 | break; |
c81229c9 | 3498 | default: |
c81229c9 | 3499 | break; |
3500 | } | |
3501 | break; | |
3502 | ||
3503 | default: | |
c81229c9 | 3504 | break; |
3505 | } | |
3506 | ||
31ca1dec | 3507 | if (ret) |
3508 | netif_err(tp, probe, tp->netdev, "Unknown Device\n"); | |
3509 | ||
c81229c9 | 3510 | return ret; |
3511 | } | |
3512 | ||
ac718b69 | 3513 | static int rtl8152_probe(struct usb_interface *intf, |
3514 | const struct usb_device_id *id) | |
3515 | { | |
3516 | struct usb_device *udev = interface_to_usbdev(intf); | |
3517 | struct r8152 *tp; | |
3518 | struct net_device *netdev; | |
ebc2ec48 | 3519 | int ret; |
ac718b69 | 3520 | |
10c32717 | 3521 | if (udev->actconfig->desc.bConfigurationValue != 1) { |
3522 | usb_driver_set_configuration(udev, 1); | |
3523 | return -ENODEV; | |
3524 | } | |
3525 | ||
3526 | usb_reset_device(udev); | |
ac718b69 | 3527 | netdev = alloc_etherdev(sizeof(struct r8152)); |
3528 | if (!netdev) { | |
4a8deae2 | 3529 | dev_err(&intf->dev, "Out of memory\n"); |
ac718b69 | 3530 | return -ENOMEM; |
3531 | } | |
3532 | ||
ebc2ec48 | 3533 | SET_NETDEV_DEV(netdev, &intf->dev); |
ac718b69 | 3534 | tp = netdev_priv(netdev); |
3535 | tp->msg_enable = 0x7FFF; | |
3536 | ||
e3ad412a | 3537 | tp->udev = udev; |
3538 | tp->netdev = netdev; | |
3539 | tp->intf = intf; | |
3540 | ||
31ca1dec | 3541 | ret = rtl_ops_init(tp, id); |
3542 | if (ret) | |
3543 | goto out; | |
c81229c9 | 3544 | |
ebc2ec48 | 3545 | tasklet_init(&tp->tl, bottom_half, (unsigned long)tp); |
ac718b69 | 3546 | INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); |
3547 | ||
ac718b69 | 3548 | netdev->netdev_ops = &rtl8152_netdev_ops; |
3549 | netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; | |
5bd23881 | 3550 | |
60c89071 | 3551 | netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 3552 | NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | |
c5554298 | 3553 | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | |
3554 | NETIF_F_HW_VLAN_CTAG_TX; | |
60c89071 | 3555 | netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 3556 | NETIF_F_TSO | NETIF_F_FRAGLIST | |
c5554298 | 3557 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | |
3558 | NETIF_F_HW_VLAN_CTAG_RX | | |
3559 | NETIF_F_HW_VLAN_CTAG_TX; | |
3560 | netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | | |
3561 | NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | | |
3562 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6; | |
db8515ef | 3563 | |
7ad24ea4 | 3564 | netdev->ethtool_ops = &ops; |
60c89071 | 3565 | netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); |
ac718b69 | 3566 | |
3567 | tp->mii.dev = netdev; | |
3568 | tp->mii.mdio_read = read_mii_word; | |
3569 | tp->mii.mdio_write = write_mii_word; | |
3570 | tp->mii.phy_id_mask = 0x3f; | |
3571 | tp->mii.reg_num_mask = 0x1f; | |
3572 | tp->mii.phy_id = R8152_PHY_ID; | |
3573 | tp->mii.supports_gmii = 0; | |
3574 | ||
9a4be1bd | 3575 | intf->needs_remote_wakeup = 1; |
3576 | ||
ac718b69 | 3577 | r8152b_get_version(tp); |
c81229c9 | 3578 | tp->rtl_ops.init(tp); |
ac718b69 | 3579 | set_ethernet_addr(tp); |
3580 | ||
ac718b69 | 3581 | usb_set_intfdata(intf, tp); |
ac718b69 | 3582 | |
ebc2ec48 | 3583 | ret = register_netdev(netdev); |
3584 | if (ret != 0) { | |
4a8deae2 | 3585 | netif_err(tp, probe, netdev, "couldn't register the device\n"); |
ebc2ec48 | 3586 | goto out1; |
ac718b69 | 3587 | } |
3588 | ||
21ff2e89 | 3589 | tp->saved_wolopts = __rtl_get_wol(tp); |
3590 | if (tp->saved_wolopts) | |
3591 | device_set_wakeup_enable(&udev->dev, true); | |
3592 | else | |
3593 | device_set_wakeup_enable(&udev->dev, false); | |
3594 | ||
4a8deae2 | 3595 | netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); |
ac718b69 | 3596 | |
3597 | return 0; | |
3598 | ||
ac718b69 | 3599 | out1: |
ebc2ec48 | 3600 | usb_set_intfdata(intf, NULL); |
ac718b69 | 3601 | out: |
3602 | free_netdev(netdev); | |
ebc2ec48 | 3603 | return ret; |
ac718b69 | 3604 | } |
3605 | ||
ac718b69 | 3606 | static void rtl8152_disconnect(struct usb_interface *intf) |
3607 | { | |
3608 | struct r8152 *tp = usb_get_intfdata(intf); | |
3609 | ||
3610 | usb_set_intfdata(intf, NULL); | |
3611 | if (tp) { | |
3612 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
3613 | tasklet_kill(&tp->tl); | |
3614 | unregister_netdev(tp->netdev); | |
c81229c9 | 3615 | tp->rtl_ops.unload(tp); |
ac718b69 | 3616 | free_netdev(tp->netdev); |
3617 | } | |
3618 | } | |
3619 | ||
3620 | /* table of devices that work with this driver */ | |
3621 | static struct usb_device_id rtl8152_table[] = { | |
10c32717 | 3622 | {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)}, |
3623 | {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)}, | |
3624 | {USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)}, | |
ac718b69 | 3625 | {} |
3626 | }; | |
3627 | ||
3628 | MODULE_DEVICE_TABLE(usb, rtl8152_table); | |
3629 | ||
3630 | static struct usb_driver rtl8152_driver = { | |
3631 | .name = MODULENAME, | |
ebc2ec48 | 3632 | .id_table = rtl8152_table, |
ac718b69 | 3633 | .probe = rtl8152_probe, |
3634 | .disconnect = rtl8152_disconnect, | |
ac718b69 | 3635 | .suspend = rtl8152_suspend, |
ebc2ec48 | 3636 | .resume = rtl8152_resume, |
3637 | .reset_resume = rtl8152_resume, | |
9a4be1bd | 3638 | .supports_autosuspend = 1, |
a634782f | 3639 | .disable_hub_initiated_lpm = 1, |
ac718b69 | 3640 | }; |
3641 | ||
b4236daa | 3642 | module_usb_driver(rtl8152_driver); |
ac718b69 | 3643 | |
3644 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
3645 | MODULE_DESCRIPTION(DRIVER_DESC); | |
3646 | MODULE_LICENSE("GPL"); |