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ac718b69 | 1 | /* |
c7de7dec | 2 | * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. |
ac718b69 | 3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
ac718b69 | 10 | #include <linux/signal.h> |
11 | #include <linux/slab.h> | |
12 | #include <linux/module.h> | |
ac718b69 | 13 | #include <linux/netdevice.h> |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/mii.h> | |
16 | #include <linux/ethtool.h> | |
17 | #include <linux/usb.h> | |
18 | #include <linux/crc32.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/uaccess.h> | |
ebc2ec48 | 21 | #include <linux/list.h> |
5bd23881 | 22 | #include <linux/ip.h> |
23 | #include <linux/ipv6.h> | |
6128d1bb | 24 | #include <net/ip6_checksum.h> |
4c4a6b1b | 25 | #include <uapi/linux/mdio.h> |
26 | #include <linux/mdio.h> | |
d9a28c5b | 27 | #include <linux/usb/cdc.h> |
5ee3c60c | 28 | #include <linux/suspend.h> |
ac718b69 | 29 | |
d0942473 | 30 | /* Information for net-next */ |
31 | #define NETNEXT_VERSION "08" | |
32 | ||
33 | /* Information for net */ | |
5ee3c60c | 34 | #define NET_VERSION "3" |
d0942473 | 35 | |
36 | #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION | |
ac718b69 | 37 | #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" |
44d942a9 | 38 | #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" |
ac718b69 | 39 | #define MODULENAME "r8152" |
40 | ||
41 | #define R8152_PHY_ID 32 | |
42 | ||
43 | #define PLA_IDR 0xc000 | |
44 | #define PLA_RCR 0xc010 | |
45 | #define PLA_RMS 0xc016 | |
46 | #define PLA_RXFIFO_CTRL0 0xc0a0 | |
47 | #define PLA_RXFIFO_CTRL1 0xc0a4 | |
48 | #define PLA_RXFIFO_CTRL2 0xc0a8 | |
65bab84c | 49 | #define PLA_DMY_REG0 0xc0b0 |
ac718b69 | 50 | #define PLA_FMC 0xc0b4 |
51 | #define PLA_CFG_WOL 0xc0b6 | |
43779f8d | 52 | #define PLA_TEREDO_CFG 0xc0bc |
ac718b69 | 53 | #define PLA_MAR 0xcd00 |
43779f8d | 54 | #define PLA_BACKUP 0xd000 |
ac718b69 | 55 | #define PAL_BDC_CR 0xd1a0 |
43779f8d | 56 | #define PLA_TEREDO_TIMER 0xd2cc |
57 | #define PLA_REALWOW_TIMER 0xd2e8 | |
ac718b69 | 58 | #define PLA_LEDSEL 0xdd90 |
59 | #define PLA_LED_FEATURE 0xdd92 | |
60 | #define PLA_PHYAR 0xde00 | |
43779f8d | 61 | #define PLA_BOOT_CTRL 0xe004 |
ac718b69 | 62 | #define PLA_GPHY_INTR_IMR 0xe022 |
63 | #define PLA_EEE_CR 0xe040 | |
64 | #define PLA_EEEP_CR 0xe080 | |
65 | #define PLA_MAC_PWR_CTRL 0xe0c0 | |
43779f8d | 66 | #define PLA_MAC_PWR_CTRL2 0xe0ca |
67 | #define PLA_MAC_PWR_CTRL3 0xe0cc | |
68 | #define PLA_MAC_PWR_CTRL4 0xe0ce | |
69 | #define PLA_WDT6_CTRL 0xe428 | |
ac718b69 | 70 | #define PLA_TCR0 0xe610 |
71 | #define PLA_TCR1 0xe612 | |
69b4b7a4 | 72 | #define PLA_MTPS 0xe615 |
ac718b69 | 73 | #define PLA_TXFIFO_CTRL 0xe618 |
4f1d4d54 | 74 | #define PLA_RSTTALLY 0xe800 |
ac718b69 | 75 | #define PLA_CR 0xe813 |
76 | #define PLA_CRWECR 0xe81c | |
21ff2e89 | 77 | #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ |
78 | #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ | |
ac718b69 | 79 | #define PLA_CONFIG5 0xe822 |
80 | #define PLA_PHY_PWR 0xe84c | |
81 | #define PLA_OOB_CTRL 0xe84f | |
82 | #define PLA_CPCR 0xe854 | |
83 | #define PLA_MISC_0 0xe858 | |
84 | #define PLA_MISC_1 0xe85a | |
85 | #define PLA_OCP_GPHY_BASE 0xe86c | |
4f1d4d54 | 86 | #define PLA_TALLYCNT 0xe890 |
ac718b69 | 87 | #define PLA_SFF_STS_7 0xe8de |
88 | #define PLA_PHYSTATUS 0xe908 | |
89 | #define PLA_BP_BA 0xfc26 | |
90 | #define PLA_BP_0 0xfc28 | |
91 | #define PLA_BP_1 0xfc2a | |
92 | #define PLA_BP_2 0xfc2c | |
93 | #define PLA_BP_3 0xfc2e | |
94 | #define PLA_BP_4 0xfc30 | |
95 | #define PLA_BP_5 0xfc32 | |
96 | #define PLA_BP_6 0xfc34 | |
97 | #define PLA_BP_7 0xfc36 | |
43779f8d | 98 | #define PLA_BP_EN 0xfc38 |
ac718b69 | 99 | |
65bab84c | 100 | #define USB_USB2PHY 0xb41e |
101 | #define USB_SSPHYLINK2 0xb428 | |
43779f8d | 102 | #define USB_U2P3_CTRL 0xb460 |
65bab84c | 103 | #define USB_CSR_DUMMY1 0xb464 |
104 | #define USB_CSR_DUMMY2 0xb466 | |
ac718b69 | 105 | #define USB_DEV_STAT 0xb808 |
65bab84c | 106 | #define USB_CONNECT_TIMER 0xcbf8 |
107 | #define USB_BURST_SIZE 0xcfc0 | |
ac718b69 | 108 | #define USB_USB_CTRL 0xd406 |
109 | #define USB_PHY_CTRL 0xd408 | |
110 | #define USB_TX_AGG 0xd40a | |
111 | #define USB_RX_BUF_TH 0xd40c | |
112 | #define USB_USB_TIMER 0xd428 | |
464ec10a | 113 | #define USB_RX_EARLY_TIMEOUT 0xd42c |
114 | #define USB_RX_EARLY_SIZE 0xd42e | |
ac718b69 | 115 | #define USB_PM_CTRL_STATUS 0xd432 |
116 | #define USB_TX_DMA 0xd434 | |
43779f8d | 117 | #define USB_TOLERANCE 0xd490 |
118 | #define USB_LPM_CTRL 0xd41a | |
ac718b69 | 119 | #define USB_UPS_CTRL 0xd800 |
43779f8d | 120 | #define USB_MISC_0 0xd81a |
121 | #define USB_POWER_CUT 0xd80a | |
122 | #define USB_AFE_CTRL2 0xd824 | |
123 | #define USB_WDT11_CTRL 0xe43c | |
ac718b69 | 124 | #define USB_BP_BA 0xfc26 |
125 | #define USB_BP_0 0xfc28 | |
126 | #define USB_BP_1 0xfc2a | |
127 | #define USB_BP_2 0xfc2c | |
128 | #define USB_BP_3 0xfc2e | |
129 | #define USB_BP_4 0xfc30 | |
130 | #define USB_BP_5 0xfc32 | |
131 | #define USB_BP_6 0xfc34 | |
132 | #define USB_BP_7 0xfc36 | |
43779f8d | 133 | #define USB_BP_EN 0xfc38 |
ac718b69 | 134 | |
135 | /* OCP Registers */ | |
136 | #define OCP_ALDPS_CONFIG 0x2010 | |
137 | #define OCP_EEE_CONFIG1 0x2080 | |
138 | #define OCP_EEE_CONFIG2 0x2092 | |
139 | #define OCP_EEE_CONFIG3 0x2094 | |
ac244d3e | 140 | #define OCP_BASE_MII 0xa400 |
ac718b69 | 141 | #define OCP_EEE_AR 0xa41a |
142 | #define OCP_EEE_DATA 0xa41c | |
43779f8d | 143 | #define OCP_PHY_STATUS 0xa420 |
144 | #define OCP_POWER_CFG 0xa430 | |
145 | #define OCP_EEE_CFG 0xa432 | |
146 | #define OCP_SRAM_ADDR 0xa436 | |
147 | #define OCP_SRAM_DATA 0xa438 | |
148 | #define OCP_DOWN_SPEED 0xa442 | |
df35d283 | 149 | #define OCP_EEE_ABLE 0xa5c4 |
4c4a6b1b | 150 | #define OCP_EEE_ADV 0xa5d0 |
df35d283 | 151 | #define OCP_EEE_LPABLE 0xa5d2 |
2dd49e0f | 152 | #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ |
43779f8d | 153 | #define OCP_ADC_CFG 0xbc06 |
154 | ||
155 | /* SRAM Register */ | |
156 | #define SRAM_LPF_CFG 0x8012 | |
157 | #define SRAM_10M_AMP1 0x8080 | |
158 | #define SRAM_10M_AMP2 0x8082 | |
159 | #define SRAM_IMPEDANCE 0x8084 | |
ac718b69 | 160 | |
161 | /* PLA_RCR */ | |
162 | #define RCR_AAP 0x00000001 | |
163 | #define RCR_APM 0x00000002 | |
164 | #define RCR_AM 0x00000004 | |
165 | #define RCR_AB 0x00000008 | |
166 | #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) | |
167 | ||
168 | /* PLA_RXFIFO_CTRL0 */ | |
169 | #define RXFIFO_THR1_NORMAL 0x00080002 | |
170 | #define RXFIFO_THR1_OOB 0x01800003 | |
171 | ||
172 | /* PLA_RXFIFO_CTRL1 */ | |
173 | #define RXFIFO_THR2_FULL 0x00000060 | |
174 | #define RXFIFO_THR2_HIGH 0x00000038 | |
175 | #define RXFIFO_THR2_OOB 0x0000004a | |
43779f8d | 176 | #define RXFIFO_THR2_NORMAL 0x00a0 |
ac718b69 | 177 | |
178 | /* PLA_RXFIFO_CTRL2 */ | |
179 | #define RXFIFO_THR3_FULL 0x00000078 | |
180 | #define RXFIFO_THR3_HIGH 0x00000048 | |
181 | #define RXFIFO_THR3_OOB 0x0000005a | |
43779f8d | 182 | #define RXFIFO_THR3_NORMAL 0x0110 |
ac718b69 | 183 | |
184 | /* PLA_TXFIFO_CTRL */ | |
185 | #define TXFIFO_THR_NORMAL 0x00400008 | |
43779f8d | 186 | #define TXFIFO_THR_NORMAL2 0x01000008 |
ac718b69 | 187 | |
65bab84c | 188 | /* PLA_DMY_REG0 */ |
189 | #define ECM_ALDPS 0x0002 | |
190 | ||
ac718b69 | 191 | /* PLA_FMC */ |
192 | #define FMC_FCR_MCU_EN 0x0001 | |
193 | ||
194 | /* PLA_EEEP_CR */ | |
195 | #define EEEP_CR_EEEP_TX 0x0002 | |
196 | ||
43779f8d | 197 | /* PLA_WDT6_CTRL */ |
198 | #define WDT6_SET_MODE 0x0010 | |
199 | ||
ac718b69 | 200 | /* PLA_TCR0 */ |
201 | #define TCR0_TX_EMPTY 0x0800 | |
202 | #define TCR0_AUTO_FIFO 0x0080 | |
203 | ||
204 | /* PLA_TCR1 */ | |
205 | #define VERSION_MASK 0x7cf0 | |
206 | ||
69b4b7a4 | 207 | /* PLA_MTPS */ |
208 | #define MTPS_JUMBO (12 * 1024 / 64) | |
209 | #define MTPS_DEFAULT (6 * 1024 / 64) | |
210 | ||
4f1d4d54 | 211 | /* PLA_RSTTALLY */ |
212 | #define TALLY_RESET 0x0001 | |
213 | ||
ac718b69 | 214 | /* PLA_CR */ |
215 | #define CR_RST 0x10 | |
216 | #define CR_RE 0x08 | |
217 | #define CR_TE 0x04 | |
218 | ||
219 | /* PLA_CRWECR */ | |
220 | #define CRWECR_NORAML 0x00 | |
221 | #define CRWECR_CONFIG 0xc0 | |
222 | ||
223 | /* PLA_OOB_CTRL */ | |
224 | #define NOW_IS_OOB 0x80 | |
225 | #define TXFIFO_EMPTY 0x20 | |
226 | #define RXFIFO_EMPTY 0x10 | |
227 | #define LINK_LIST_READY 0x02 | |
228 | #define DIS_MCU_CLROOB 0x01 | |
229 | #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) | |
230 | ||
231 | /* PLA_MISC_1 */ | |
232 | #define RXDY_GATED_EN 0x0008 | |
233 | ||
234 | /* PLA_SFF_STS_7 */ | |
235 | #define RE_INIT_LL 0x8000 | |
236 | #define MCU_BORW_EN 0x4000 | |
237 | ||
238 | /* PLA_CPCR */ | |
239 | #define CPCR_RX_VLAN 0x0040 | |
240 | ||
241 | /* PLA_CFG_WOL */ | |
242 | #define MAGIC_EN 0x0001 | |
243 | ||
43779f8d | 244 | /* PLA_TEREDO_CFG */ |
245 | #define TEREDO_SEL 0x8000 | |
246 | #define TEREDO_WAKE_MASK 0x7f00 | |
247 | #define TEREDO_RS_EVENT_MASK 0x00fe | |
248 | #define OOB_TEREDO_EN 0x0001 | |
249 | ||
ac718b69 | 250 | /* PAL_BDC_CR */ |
251 | #define ALDPS_PROXY_MODE 0x0001 | |
252 | ||
21ff2e89 | 253 | /* PLA_CONFIG34 */ |
254 | #define LINK_ON_WAKE_EN 0x0010 | |
255 | #define LINK_OFF_WAKE_EN 0x0008 | |
256 | ||
ac718b69 | 257 | /* PLA_CONFIG5 */ |
21ff2e89 | 258 | #define BWF_EN 0x0040 |
259 | #define MWF_EN 0x0020 | |
260 | #define UWF_EN 0x0010 | |
ac718b69 | 261 | #define LAN_WAKE_EN 0x0002 |
262 | ||
263 | /* PLA_LED_FEATURE */ | |
264 | #define LED_MODE_MASK 0x0700 | |
265 | ||
266 | /* PLA_PHY_PWR */ | |
267 | #define TX_10M_IDLE_EN 0x0080 | |
268 | #define PFM_PWM_SWITCH 0x0040 | |
269 | ||
270 | /* PLA_MAC_PWR_CTRL */ | |
271 | #define D3_CLK_GATED_EN 0x00004000 | |
272 | #define MCU_CLK_RATIO 0x07010f07 | |
273 | #define MCU_CLK_RATIO_MASK 0x0f0f0f0f | |
43779f8d | 274 | #define ALDPS_SPDWN_RATIO 0x0f87 |
275 | ||
276 | /* PLA_MAC_PWR_CTRL2 */ | |
277 | #define EEE_SPDWN_RATIO 0x8007 | |
278 | ||
279 | /* PLA_MAC_PWR_CTRL3 */ | |
280 | #define PKT_AVAIL_SPDWN_EN 0x0100 | |
281 | #define SUSPEND_SPDWN_EN 0x0004 | |
282 | #define U1U2_SPDWN_EN 0x0002 | |
283 | #define L1_SPDWN_EN 0x0001 | |
284 | ||
285 | /* PLA_MAC_PWR_CTRL4 */ | |
286 | #define PWRSAVE_SPDWN_EN 0x1000 | |
287 | #define RXDV_SPDWN_EN 0x0800 | |
288 | #define TX10MIDLE_EN 0x0100 | |
289 | #define TP100_SPDWN_EN 0x0020 | |
290 | #define TP500_SPDWN_EN 0x0010 | |
291 | #define TP1000_SPDWN_EN 0x0008 | |
292 | #define EEE_SPDWN_EN 0x0001 | |
ac718b69 | 293 | |
294 | /* PLA_GPHY_INTR_IMR */ | |
295 | #define GPHY_STS_MSK 0x0001 | |
296 | #define SPEED_DOWN_MSK 0x0002 | |
297 | #define SPDWN_RXDV_MSK 0x0004 | |
298 | #define SPDWN_LINKCHG_MSK 0x0008 | |
299 | ||
300 | /* PLA_PHYAR */ | |
301 | #define PHYAR_FLAG 0x80000000 | |
302 | ||
303 | /* PLA_EEE_CR */ | |
304 | #define EEE_RX_EN 0x0001 | |
305 | #define EEE_TX_EN 0x0002 | |
306 | ||
43779f8d | 307 | /* PLA_BOOT_CTRL */ |
308 | #define AUTOLOAD_DONE 0x0002 | |
309 | ||
65bab84c | 310 | /* USB_USB2PHY */ |
311 | #define USB2PHY_SUSPEND 0x0001 | |
312 | #define USB2PHY_L1 0x0002 | |
313 | ||
314 | /* USB_SSPHYLINK2 */ | |
315 | #define pwd_dn_scale_mask 0x3ffe | |
316 | #define pwd_dn_scale(x) ((x) << 1) | |
317 | ||
318 | /* USB_CSR_DUMMY1 */ | |
319 | #define DYNAMIC_BURST 0x0001 | |
320 | ||
321 | /* USB_CSR_DUMMY2 */ | |
322 | #define EP4_FULL_FC 0x0001 | |
323 | ||
ac718b69 | 324 | /* USB_DEV_STAT */ |
325 | #define STAT_SPEED_MASK 0x0006 | |
326 | #define STAT_SPEED_HIGH 0x0000 | |
a3cc465d | 327 | #define STAT_SPEED_FULL 0x0002 |
ac718b69 | 328 | |
329 | /* USB_TX_AGG */ | |
330 | #define TX_AGG_MAX_THRESHOLD 0x03 | |
331 | ||
332 | /* USB_RX_BUF_TH */ | |
43779f8d | 333 | #define RX_THR_SUPPER 0x0c350180 |
8e1f51bd | 334 | #define RX_THR_HIGH 0x7a120180 |
43779f8d | 335 | #define RX_THR_SLOW 0xffff0180 |
ac718b69 | 336 | |
337 | /* USB_TX_DMA */ | |
338 | #define TEST_MODE_DISABLE 0x00000001 | |
339 | #define TX_SIZE_ADJUST1 0x00000100 | |
340 | ||
341 | /* USB_UPS_CTRL */ | |
342 | #define POWER_CUT 0x0100 | |
343 | ||
344 | /* USB_PM_CTRL_STATUS */ | |
8e1f51bd | 345 | #define RESUME_INDICATE 0x0001 |
ac718b69 | 346 | |
347 | /* USB_USB_CTRL */ | |
348 | #define RX_AGG_DISABLE 0x0010 | |
e90fba8d | 349 | #define RX_ZERO_EN 0x0080 |
ac718b69 | 350 | |
43779f8d | 351 | /* USB_U2P3_CTRL */ |
352 | #define U2P3_ENABLE 0x0001 | |
353 | ||
354 | /* USB_POWER_CUT */ | |
355 | #define PWR_EN 0x0001 | |
356 | #define PHASE2_EN 0x0008 | |
357 | ||
358 | /* USB_MISC_0 */ | |
359 | #define PCUT_STATUS 0x0001 | |
360 | ||
464ec10a | 361 | /* USB_RX_EARLY_TIMEOUT */ |
362 | #define COALESCE_SUPER 85000U | |
363 | #define COALESCE_HIGH 250000U | |
364 | #define COALESCE_SLOW 524280U | |
43779f8d | 365 | |
366 | /* USB_WDT11_CTRL */ | |
367 | #define TIMER11_EN 0x0001 | |
368 | ||
369 | /* USB_LPM_CTRL */ | |
65bab84c | 370 | /* bit 4 ~ 5: fifo empty boundary */ |
371 | #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ | |
372 | /* bit 2 ~ 3: LMP timer */ | |
43779f8d | 373 | #define LPM_TIMER_MASK 0x0c |
374 | #define LPM_TIMER_500MS 0x04 /* 500 ms */ | |
375 | #define LPM_TIMER_500US 0x0c /* 500 us */ | |
65bab84c | 376 | #define ROK_EXIT_LPM 0x02 |
43779f8d | 377 | |
378 | /* USB_AFE_CTRL2 */ | |
379 | #define SEN_VAL_MASK 0xf800 | |
380 | #define SEN_VAL_NORMAL 0xa000 | |
381 | #define SEL_RXIDLE 0x0100 | |
382 | ||
ac718b69 | 383 | /* OCP_ALDPS_CONFIG */ |
384 | #define ENPWRSAVE 0x8000 | |
385 | #define ENPDNPS 0x0200 | |
386 | #define LINKENA 0x0100 | |
387 | #define DIS_SDSAVE 0x0010 | |
388 | ||
43779f8d | 389 | /* OCP_PHY_STATUS */ |
390 | #define PHY_STAT_MASK 0x0007 | |
391 | #define PHY_STAT_LAN_ON 3 | |
392 | #define PHY_STAT_PWRDN 5 | |
393 | ||
394 | /* OCP_POWER_CFG */ | |
395 | #define EEE_CLKDIV_EN 0x8000 | |
396 | #define EN_ALDPS 0x0004 | |
397 | #define EN_10M_PLLOFF 0x0001 | |
398 | ||
ac718b69 | 399 | /* OCP_EEE_CONFIG1 */ |
400 | #define RG_TXLPI_MSK_HFDUP 0x8000 | |
401 | #define RG_MATCLR_EN 0x4000 | |
402 | #define EEE_10_CAP 0x2000 | |
403 | #define EEE_NWAY_EN 0x1000 | |
404 | #define TX_QUIET_EN 0x0200 | |
405 | #define RX_QUIET_EN 0x0100 | |
d24f6134 | 406 | #define sd_rise_time_mask 0x0070 |
4c4a6b1b | 407 | #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ |
ac718b69 | 408 | #define RG_RXLPI_MSK_HFDUP 0x0008 |
409 | #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ | |
410 | ||
411 | /* OCP_EEE_CONFIG2 */ | |
412 | #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ | |
413 | #define RG_DACQUIET_EN 0x0400 | |
414 | #define RG_LDVQUIET_EN 0x0200 | |
415 | #define RG_CKRSEL 0x0020 | |
416 | #define RG_EEEPRG_EN 0x0010 | |
417 | ||
418 | /* OCP_EEE_CONFIG3 */ | |
d24f6134 | 419 | #define fast_snr_mask 0xff80 |
4c4a6b1b | 420 | #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ |
ac718b69 | 421 | #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ |
422 | #define MSK_PH 0x0006 /* bit 0 ~ 3 */ | |
423 | ||
424 | /* OCP_EEE_AR */ | |
425 | /* bit[15:14] function */ | |
426 | #define FUN_ADDR 0x0000 | |
427 | #define FUN_DATA 0x4000 | |
428 | /* bit[4:0] device addr */ | |
ac718b69 | 429 | |
43779f8d | 430 | /* OCP_EEE_CFG */ |
431 | #define CTAP_SHORT_EN 0x0040 | |
432 | #define EEE10_EN 0x0010 | |
433 | ||
434 | /* OCP_DOWN_SPEED */ | |
435 | #define EN_10M_BGOFF 0x0080 | |
436 | ||
2dd49e0f | 437 | /* OCP_PHY_STATE */ |
438 | #define TXDIS_STATE 0x01 | |
439 | #define ABD_STATE 0x02 | |
440 | ||
43779f8d | 441 | /* OCP_ADC_CFG */ |
442 | #define CKADSEL_L 0x0100 | |
443 | #define ADC_EN 0x0080 | |
444 | #define EN_EMI_L 0x0040 | |
445 | ||
446 | /* SRAM_LPF_CFG */ | |
447 | #define LPF_AUTO_TUNE 0x8000 | |
448 | ||
449 | /* SRAM_10M_AMP1 */ | |
450 | #define GDAC_IB_UPALL 0x0008 | |
451 | ||
452 | /* SRAM_10M_AMP2 */ | |
453 | #define AMP_DN 0x0200 | |
454 | ||
455 | /* SRAM_IMPEDANCE */ | |
456 | #define RX_DRIVING_MASK 0x6000 | |
457 | ||
ac718b69 | 458 | enum rtl_register_content { |
43779f8d | 459 | _1000bps = 0x10, |
ac718b69 | 460 | _100bps = 0x08, |
461 | _10bps = 0x04, | |
462 | LINK_STATUS = 0x02, | |
463 | FULL_DUP = 0x01, | |
464 | }; | |
465 | ||
1764bcd9 | 466 | #define RTL8152_MAX_TX 4 |
ebc2ec48 | 467 | #define RTL8152_MAX_RX 10 |
40a82917 | 468 | #define INTBUFSIZE 2 |
8e1f51bd | 469 | #define CRC_SIZE 4 |
470 | #define TX_ALIGN 4 | |
471 | #define RX_ALIGN 8 | |
40a82917 | 472 | |
473 | #define INTR_LINK 0x0004 | |
ebc2ec48 | 474 | |
ac718b69 | 475 | #define RTL8152_REQT_READ 0xc0 |
476 | #define RTL8152_REQT_WRITE 0x40 | |
477 | #define RTL8152_REQ_GET_REGS 0x05 | |
478 | #define RTL8152_REQ_SET_REGS 0x05 | |
479 | ||
480 | #define BYTE_EN_DWORD 0xff | |
481 | #define BYTE_EN_WORD 0x33 | |
482 | #define BYTE_EN_BYTE 0x11 | |
483 | #define BYTE_EN_SIX_BYTES 0x3f | |
484 | #define BYTE_EN_START_MASK 0x0f | |
485 | #define BYTE_EN_END_MASK 0xf0 | |
486 | ||
69b4b7a4 | 487 | #define RTL8153_MAX_PACKET 9216 /* 9K */ |
488 | #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN) | |
ac718b69 | 489 | #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) |
69b4b7a4 | 490 | #define RTL8153_RMS RTL8153_MAX_PACKET |
b8125404 | 491 | #define RTL8152_TX_TIMEOUT (5 * HZ) |
d823ab68 | 492 | #define RTL8152_NAPI_WEIGHT 64 |
ac718b69 | 493 | |
494 | /* rtl8152 flags */ | |
495 | enum rtl8152_flags { | |
496 | RTL8152_UNPLUG = 0, | |
ac718b69 | 497 | RTL8152_SET_RX_MODE, |
40a82917 | 498 | WORK_ENABLE, |
499 | RTL8152_LINK_CHG, | |
9a4be1bd | 500 | SELECTIVE_SUSPEND, |
aa66a5f1 | 501 | PHY_RESET, |
d823ab68 | 502 | SCHEDULE_NAPI, |
ac718b69 | 503 | }; |
504 | ||
505 | /* Define these values to match your device */ | |
506 | #define VENDOR_ID_REALTEK 0x0bda | |
43779f8d | 507 | #define VENDOR_ID_SAMSUNG 0x04e8 |
347eec34 | 508 | #define VENDOR_ID_LENOVO 0x17ef |
d065c3c1 | 509 | #define VENDOR_ID_NVIDIA 0x0955 |
ac718b69 | 510 | |
511 | #define MCU_TYPE_PLA 0x0100 | |
512 | #define MCU_TYPE_USB 0x0000 | |
513 | ||
4f1d4d54 | 514 | struct tally_counter { |
515 | __le64 tx_packets; | |
516 | __le64 rx_packets; | |
517 | __le64 tx_errors; | |
518 | __le32 rx_errors; | |
519 | __le16 rx_missed; | |
520 | __le16 align_errors; | |
521 | __le32 tx_one_collision; | |
522 | __le32 tx_multi_collision; | |
523 | __le64 rx_unicast; | |
524 | __le64 rx_broadcast; | |
525 | __le32 rx_multicast; | |
526 | __le16 tx_aborted; | |
f37119c5 | 527 | __le16 tx_underrun; |
4f1d4d54 | 528 | }; |
529 | ||
ac718b69 | 530 | struct rx_desc { |
500b6d7e | 531 | __le32 opts1; |
ac718b69 | 532 | #define RX_LEN_MASK 0x7fff |
565cab0a | 533 | |
500b6d7e | 534 | __le32 opts2; |
f5aaaa6d | 535 | #define RD_UDP_CS BIT(23) |
536 | #define RD_TCP_CS BIT(22) | |
537 | #define RD_IPV6_CS BIT(20) | |
538 | #define RD_IPV4_CS BIT(19) | |
565cab0a | 539 | |
500b6d7e | 540 | __le32 opts3; |
f5aaaa6d | 541 | #define IPF BIT(23) /* IP checksum fail */ |
542 | #define UDPF BIT(22) /* UDP checksum fail */ | |
543 | #define TCPF BIT(21) /* TCP checksum fail */ | |
544 | #define RX_VLAN_TAG BIT(16) | |
565cab0a | 545 | |
500b6d7e | 546 | __le32 opts4; |
547 | __le32 opts5; | |
548 | __le32 opts6; | |
ac718b69 | 549 | }; |
550 | ||
551 | struct tx_desc { | |
500b6d7e | 552 | __le32 opts1; |
f5aaaa6d | 553 | #define TX_FS BIT(31) /* First segment of a packet */ |
554 | #define TX_LS BIT(30) /* Final segment of a packet */ | |
555 | #define GTSENDV4 BIT(28) | |
556 | #define GTSENDV6 BIT(27) | |
60c89071 | 557 | #define GTTCPHO_SHIFT 18 |
6128d1bb | 558 | #define GTTCPHO_MAX 0x7fU |
60c89071 | 559 | #define TX_LEN_MAX 0x3ffffU |
5bd23881 | 560 | |
500b6d7e | 561 | __le32 opts2; |
f5aaaa6d | 562 | #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ |
563 | #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ | |
564 | #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ | |
565 | #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ | |
60c89071 | 566 | #define MSS_SHIFT 17 |
567 | #define MSS_MAX 0x7ffU | |
568 | #define TCPHO_SHIFT 17 | |
6128d1bb | 569 | #define TCPHO_MAX 0x7ffU |
f5aaaa6d | 570 | #define TX_VLAN_TAG BIT(16) |
ac718b69 | 571 | }; |
572 | ||
dff4e8ad | 573 | struct r8152; |
574 | ||
ebc2ec48 | 575 | struct rx_agg { |
576 | struct list_head list; | |
577 | struct urb *urb; | |
dff4e8ad | 578 | struct r8152 *context; |
ebc2ec48 | 579 | void *buffer; |
580 | void *head; | |
581 | }; | |
582 | ||
583 | struct tx_agg { | |
584 | struct list_head list; | |
585 | struct urb *urb; | |
dff4e8ad | 586 | struct r8152 *context; |
ebc2ec48 | 587 | void *buffer; |
588 | void *head; | |
589 | u32 skb_num; | |
590 | u32 skb_len; | |
591 | }; | |
592 | ||
ac718b69 | 593 | struct r8152 { |
594 | unsigned long flags; | |
595 | struct usb_device *udev; | |
d823ab68 | 596 | struct napi_struct napi; |
40a82917 | 597 | struct usb_interface *intf; |
ac718b69 | 598 | struct net_device *netdev; |
40a82917 | 599 | struct urb *intr_urb; |
ebc2ec48 | 600 | struct tx_agg tx_info[RTL8152_MAX_TX]; |
601 | struct rx_agg rx_info[RTL8152_MAX_RX]; | |
602 | struct list_head rx_done, tx_free; | |
d823ab68 | 603 | struct sk_buff_head tx_queue, rx_queue; |
ebc2ec48 | 604 | spinlock_t rx_lock, tx_lock; |
ac718b69 | 605 | struct delayed_work schedule; |
606 | struct mii_if_info mii; | |
b5403273 | 607 | struct mutex control; /* use for hw setting */ |
5ee3c60c | 608 | #ifdef CONFIG_PM_SLEEP |
609 | struct notifier_block pm_notifier; | |
610 | #endif | |
c81229c9 | 611 | |
612 | struct rtl_ops { | |
613 | void (*init)(struct r8152 *); | |
614 | int (*enable)(struct r8152 *); | |
615 | void (*disable)(struct r8152 *); | |
7e9da481 | 616 | void (*up)(struct r8152 *); |
c81229c9 | 617 | void (*down)(struct r8152 *); |
618 | void (*unload)(struct r8152 *); | |
df35d283 | 619 | int (*eee_get)(struct r8152 *, struct ethtool_eee *); |
620 | int (*eee_set)(struct r8152 *, struct ethtool_eee *); | |
2dd49e0f | 621 | bool (*in_nway)(struct r8152 *); |
c81229c9 | 622 | } rtl_ops; |
623 | ||
40a82917 | 624 | int intr_interval; |
21ff2e89 | 625 | u32 saved_wolopts; |
ac718b69 | 626 | u32 msg_enable; |
dd1b119c | 627 | u32 tx_qlen; |
464ec10a | 628 | u32 coalesce; |
ac718b69 | 629 | u16 ocp_base; |
40a82917 | 630 | u8 *intr_buff; |
ac718b69 | 631 | u8 version; |
ac718b69 | 632 | }; |
633 | ||
634 | enum rtl_version { | |
635 | RTL_VER_UNKNOWN = 0, | |
636 | RTL_VER_01, | |
43779f8d | 637 | RTL_VER_02, |
638 | RTL_VER_03, | |
639 | RTL_VER_04, | |
640 | RTL_VER_05, | |
fb02eb4a | 641 | RTL_VER_06, |
43779f8d | 642 | RTL_VER_MAX |
ac718b69 | 643 | }; |
644 | ||
60c89071 | 645 | enum tx_csum_stat { |
646 | TX_CSUM_SUCCESS = 0, | |
647 | TX_CSUM_TSO, | |
648 | TX_CSUM_NONE | |
649 | }; | |
650 | ||
ac718b69 | 651 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
652 | * The RTL chips use a 64 element hash table based on the Ethernet CRC. | |
653 | */ | |
654 | static const int multicast_filter_limit = 32; | |
52aec126 | 655 | static unsigned int agg_buf_sz = 16384; |
ac718b69 | 656 | |
52aec126 | 657 | #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ |
60c89071 | 658 | VLAN_ETH_HLEN - VLAN_HLEN) |
659 | ||
ac718b69 | 660 | static |
661 | int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
662 | { | |
31787f53 | 663 | int ret; |
664 | void *tmp; | |
665 | ||
666 | tmp = kmalloc(size, GFP_KERNEL); | |
667 | if (!tmp) | |
668 | return -ENOMEM; | |
669 | ||
670 | ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), | |
b209af99 | 671 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, |
672 | value, index, tmp, size, 500); | |
31787f53 | 673 | |
674 | memcpy(data, tmp, size); | |
675 | kfree(tmp); | |
676 | ||
677 | return ret; | |
ac718b69 | 678 | } |
679 | ||
680 | static | |
681 | int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
682 | { | |
31787f53 | 683 | int ret; |
684 | void *tmp; | |
685 | ||
c4438f03 | 686 | tmp = kmemdup(data, size, GFP_KERNEL); |
31787f53 | 687 | if (!tmp) |
688 | return -ENOMEM; | |
689 | ||
31787f53 | 690 | ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), |
b209af99 | 691 | RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, |
692 | value, index, tmp, size, 500); | |
31787f53 | 693 | |
694 | kfree(tmp); | |
db8515ef | 695 | |
31787f53 | 696 | return ret; |
ac718b69 | 697 | } |
698 | ||
699 | static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, | |
b209af99 | 700 | void *data, u16 type) |
ac718b69 | 701 | { |
45f4a19f | 702 | u16 limit = 64; |
703 | int ret = 0; | |
ac718b69 | 704 | |
705 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
706 | return -ENODEV; | |
707 | ||
708 | /* both size and indix must be 4 bytes align */ | |
709 | if ((size & 3) || !size || (index & 3) || !data) | |
710 | return -EPERM; | |
711 | ||
712 | if ((u32)index + (u32)size > 0xffff) | |
713 | return -EPERM; | |
714 | ||
715 | while (size) { | |
716 | if (size > limit) { | |
717 | ret = get_registers(tp, index, type, limit, data); | |
718 | if (ret < 0) | |
719 | break; | |
720 | ||
721 | index += limit; | |
722 | data += limit; | |
723 | size -= limit; | |
724 | } else { | |
725 | ret = get_registers(tp, index, type, size, data); | |
726 | if (ret < 0) | |
727 | break; | |
728 | ||
729 | index += size; | |
730 | data += size; | |
731 | size = 0; | |
732 | break; | |
733 | } | |
734 | } | |
735 | ||
67610496 | 736 | if (ret == -ENODEV) |
737 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
738 | ||
ac718b69 | 739 | return ret; |
740 | } | |
741 | ||
742 | static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, | |
b209af99 | 743 | u16 size, void *data, u16 type) |
ac718b69 | 744 | { |
45f4a19f | 745 | int ret; |
746 | u16 byteen_start, byteen_end, byen; | |
747 | u16 limit = 512; | |
ac718b69 | 748 | |
749 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
750 | return -ENODEV; | |
751 | ||
752 | /* both size and indix must be 4 bytes align */ | |
753 | if ((size & 3) || !size || (index & 3) || !data) | |
754 | return -EPERM; | |
755 | ||
756 | if ((u32)index + (u32)size > 0xffff) | |
757 | return -EPERM; | |
758 | ||
759 | byteen_start = byteen & BYTE_EN_START_MASK; | |
760 | byteen_end = byteen & BYTE_EN_END_MASK; | |
761 | ||
762 | byen = byteen_start | (byteen_start << 4); | |
763 | ret = set_registers(tp, index, type | byen, 4, data); | |
764 | if (ret < 0) | |
765 | goto error1; | |
766 | ||
767 | index += 4; | |
768 | data += 4; | |
769 | size -= 4; | |
770 | ||
771 | if (size) { | |
772 | size -= 4; | |
773 | ||
774 | while (size) { | |
775 | if (size > limit) { | |
776 | ret = set_registers(tp, index, | |
b209af99 | 777 | type | BYTE_EN_DWORD, |
778 | limit, data); | |
ac718b69 | 779 | if (ret < 0) |
780 | goto error1; | |
781 | ||
782 | index += limit; | |
783 | data += limit; | |
784 | size -= limit; | |
785 | } else { | |
786 | ret = set_registers(tp, index, | |
b209af99 | 787 | type | BYTE_EN_DWORD, |
788 | size, data); | |
ac718b69 | 789 | if (ret < 0) |
790 | goto error1; | |
791 | ||
792 | index += size; | |
793 | data += size; | |
794 | size = 0; | |
795 | break; | |
796 | } | |
797 | } | |
798 | ||
799 | byen = byteen_end | (byteen_end >> 4); | |
800 | ret = set_registers(tp, index, type | byen, 4, data); | |
801 | if (ret < 0) | |
802 | goto error1; | |
803 | } | |
804 | ||
805 | error1: | |
67610496 | 806 | if (ret == -ENODEV) |
807 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
808 | ||
ac718b69 | 809 | return ret; |
810 | } | |
811 | ||
812 | static inline | |
813 | int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
814 | { | |
815 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); | |
816 | } | |
817 | ||
818 | static inline | |
819 | int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
820 | { | |
821 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); | |
822 | } | |
823 | ||
824 | static inline | |
825 | int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
826 | { | |
827 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); | |
828 | } | |
829 | ||
830 | static inline | |
831 | int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
832 | { | |
833 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); | |
834 | } | |
835 | ||
836 | static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) | |
837 | { | |
c8826de8 | 838 | __le32 data; |
ac718b69 | 839 | |
c8826de8 | 840 | generic_ocp_read(tp, index, sizeof(data), &data, type); |
ac718b69 | 841 | |
842 | return __le32_to_cpu(data); | |
843 | } | |
844 | ||
845 | static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) | |
846 | { | |
c8826de8 | 847 | __le32 tmp = __cpu_to_le32(data); |
848 | ||
849 | generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); | |
ac718b69 | 850 | } |
851 | ||
852 | static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) | |
853 | { | |
854 | u32 data; | |
c8826de8 | 855 | __le32 tmp; |
ac718b69 | 856 | u8 shift = index & 2; |
857 | ||
858 | index &= ~3; | |
859 | ||
c8826de8 | 860 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 861 | |
c8826de8 | 862 | data = __le32_to_cpu(tmp); |
ac718b69 | 863 | data >>= (shift * 8); |
864 | data &= 0xffff; | |
865 | ||
866 | return (u16)data; | |
867 | } | |
868 | ||
869 | static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) | |
870 | { | |
c8826de8 | 871 | u32 mask = 0xffff; |
872 | __le32 tmp; | |
ac718b69 | 873 | u16 byen = BYTE_EN_WORD; |
874 | u8 shift = index & 2; | |
875 | ||
876 | data &= mask; | |
877 | ||
878 | if (index & 2) { | |
879 | byen <<= shift; | |
880 | mask <<= (shift * 8); | |
881 | data <<= (shift * 8); | |
882 | index &= ~3; | |
883 | } | |
884 | ||
c8826de8 | 885 | tmp = __cpu_to_le32(data); |
ac718b69 | 886 | |
c8826de8 | 887 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 888 | } |
889 | ||
890 | static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) | |
891 | { | |
892 | u32 data; | |
c8826de8 | 893 | __le32 tmp; |
ac718b69 | 894 | u8 shift = index & 3; |
895 | ||
896 | index &= ~3; | |
897 | ||
c8826de8 | 898 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 899 | |
c8826de8 | 900 | data = __le32_to_cpu(tmp); |
ac718b69 | 901 | data >>= (shift * 8); |
902 | data &= 0xff; | |
903 | ||
904 | return (u8)data; | |
905 | } | |
906 | ||
907 | static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) | |
908 | { | |
c8826de8 | 909 | u32 mask = 0xff; |
910 | __le32 tmp; | |
ac718b69 | 911 | u16 byen = BYTE_EN_BYTE; |
912 | u8 shift = index & 3; | |
913 | ||
914 | data &= mask; | |
915 | ||
916 | if (index & 3) { | |
917 | byen <<= shift; | |
918 | mask <<= (shift * 8); | |
919 | data <<= (shift * 8); | |
920 | index &= ~3; | |
921 | } | |
922 | ||
c8826de8 | 923 | tmp = __cpu_to_le32(data); |
ac718b69 | 924 | |
c8826de8 | 925 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 926 | } |
927 | ||
ac244d3e | 928 | static u16 ocp_reg_read(struct r8152 *tp, u16 addr) |
e3fe0b1a | 929 | { |
930 | u16 ocp_base, ocp_index; | |
931 | ||
932 | ocp_base = addr & 0xf000; | |
933 | if (ocp_base != tp->ocp_base) { | |
934 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
935 | tp->ocp_base = ocp_base; | |
936 | } | |
937 | ||
938 | ocp_index = (addr & 0x0fff) | 0xb000; | |
ac244d3e | 939 | return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); |
e3fe0b1a | 940 | } |
941 | ||
ac244d3e | 942 | static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) |
ac718b69 | 943 | { |
ac244d3e | 944 | u16 ocp_base, ocp_index; |
ac718b69 | 945 | |
ac244d3e | 946 | ocp_base = addr & 0xf000; |
947 | if (ocp_base != tp->ocp_base) { | |
948 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
949 | tp->ocp_base = ocp_base; | |
ac718b69 | 950 | } |
ac244d3e | 951 | |
952 | ocp_index = (addr & 0x0fff) | 0xb000; | |
953 | ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); | |
ac718b69 | 954 | } |
955 | ||
ac244d3e | 956 | static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) |
ac718b69 | 957 | { |
ac244d3e | 958 | ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); |
959 | } | |
ac718b69 | 960 | |
ac244d3e | 961 | static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) |
962 | { | |
963 | return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); | |
ac718b69 | 964 | } |
965 | ||
43779f8d | 966 | static void sram_write(struct r8152 *tp, u16 addr, u16 data) |
967 | { | |
968 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
969 | ocp_reg_write(tp, OCP_SRAM_DATA, data); | |
970 | } | |
971 | ||
ac718b69 | 972 | static int read_mii_word(struct net_device *netdev, int phy_id, int reg) |
973 | { | |
974 | struct r8152 *tp = netdev_priv(netdev); | |
9a4be1bd | 975 | int ret; |
ac718b69 | 976 | |
6871438c | 977 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
978 | return -ENODEV; | |
979 | ||
ac718b69 | 980 | if (phy_id != R8152_PHY_ID) |
981 | return -EINVAL; | |
982 | ||
9a4be1bd | 983 | ret = r8152_mdio_read(tp, reg); |
984 | ||
9a4be1bd | 985 | return ret; |
ac718b69 | 986 | } |
987 | ||
988 | static | |
989 | void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) | |
990 | { | |
991 | struct r8152 *tp = netdev_priv(netdev); | |
992 | ||
6871438c | 993 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
994 | return; | |
995 | ||
ac718b69 | 996 | if (phy_id != R8152_PHY_ID) |
997 | return; | |
998 | ||
999 | r8152_mdio_write(tp, reg, val); | |
1000 | } | |
1001 | ||
b209af99 | 1002 | static int |
1003 | r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); | |
ebc2ec48 | 1004 | |
8ba789ab | 1005 | static int rtl8152_set_mac_address(struct net_device *netdev, void *p) |
1006 | { | |
1007 | struct r8152 *tp = netdev_priv(netdev); | |
1008 | struct sockaddr *addr = p; | |
ea6a7112 | 1009 | int ret = -EADDRNOTAVAIL; |
8ba789ab | 1010 | |
1011 | if (!is_valid_ether_addr(addr->sa_data)) | |
ea6a7112 | 1012 | goto out1; |
1013 | ||
1014 | ret = usb_autopm_get_interface(tp->intf); | |
1015 | if (ret < 0) | |
1016 | goto out1; | |
8ba789ab | 1017 | |
b5403273 | 1018 | mutex_lock(&tp->control); |
1019 | ||
8ba789ab | 1020 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); |
1021 | ||
1022 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
1023 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); | |
1024 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
1025 | ||
b5403273 | 1026 | mutex_unlock(&tp->control); |
1027 | ||
ea6a7112 | 1028 | usb_autopm_put_interface(tp->intf); |
1029 | out1: | |
1030 | return ret; | |
8ba789ab | 1031 | } |
1032 | ||
179bb6d7 | 1033 | static int set_ethernet_addr(struct r8152 *tp) |
ac718b69 | 1034 | { |
1035 | struct net_device *dev = tp->netdev; | |
179bb6d7 | 1036 | struct sockaddr sa; |
8a91c824 | 1037 | int ret; |
ac718b69 | 1038 | |
8a91c824 | 1039 | if (tp->version == RTL_VER_01) |
179bb6d7 | 1040 | ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data); |
8a91c824 | 1041 | else |
179bb6d7 | 1042 | ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data); |
8a91c824 | 1043 | |
1044 | if (ret < 0) { | |
179bb6d7 | 1045 | netif_err(tp, probe, dev, "Get ether addr fail\n"); |
1046 | } else if (!is_valid_ether_addr(sa.sa_data)) { | |
1047 | netif_err(tp, probe, dev, "Invalid ether addr %pM\n", | |
1048 | sa.sa_data); | |
1049 | eth_hw_addr_random(dev); | |
1050 | ether_addr_copy(sa.sa_data, dev->dev_addr); | |
1051 | ret = rtl8152_set_mac_address(dev, &sa); | |
1052 | netif_info(tp, probe, dev, "Random ether addr %pM\n", | |
1053 | sa.sa_data); | |
8a91c824 | 1054 | } else { |
179bb6d7 | 1055 | if (tp->version == RTL_VER_01) |
1056 | ether_addr_copy(dev->dev_addr, sa.sa_data); | |
1057 | else | |
1058 | ret = rtl8152_set_mac_address(dev, &sa); | |
ac718b69 | 1059 | } |
179bb6d7 | 1060 | |
1061 | return ret; | |
ac718b69 | 1062 | } |
1063 | ||
ac718b69 | 1064 | static void read_bulk_callback(struct urb *urb) |
1065 | { | |
ac718b69 | 1066 | struct net_device *netdev; |
ac718b69 | 1067 | int status = urb->status; |
ebc2ec48 | 1068 | struct rx_agg *agg; |
1069 | struct r8152 *tp; | |
ac718b69 | 1070 | |
ebc2ec48 | 1071 | agg = urb->context; |
1072 | if (!agg) | |
1073 | return; | |
1074 | ||
1075 | tp = agg->context; | |
ac718b69 | 1076 | if (!tp) |
1077 | return; | |
ebc2ec48 | 1078 | |
ac718b69 | 1079 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1080 | return; | |
ebc2ec48 | 1081 | |
1082 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1083 | return; | |
1084 | ||
ac718b69 | 1085 | netdev = tp->netdev; |
7559fb2f | 1086 | |
1087 | /* When link down, the driver would cancel all bulks. */ | |
1088 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1089 | if (!netif_carrier_ok(netdev)) |
ac718b69 | 1090 | return; |
1091 | ||
9a4be1bd | 1092 | usb_mark_last_busy(tp->udev); |
1093 | ||
ac718b69 | 1094 | switch (status) { |
1095 | case 0: | |
ebc2ec48 | 1096 | if (urb->actual_length < ETH_ZLEN) |
1097 | break; | |
1098 | ||
2685d410 | 1099 | spin_lock(&tp->rx_lock); |
ebc2ec48 | 1100 | list_add_tail(&agg->list, &tp->rx_done); |
2685d410 | 1101 | spin_unlock(&tp->rx_lock); |
d823ab68 | 1102 | napi_schedule(&tp->napi); |
ebc2ec48 | 1103 | return; |
ac718b69 | 1104 | case -ESHUTDOWN: |
1105 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
1106 | netif_device_detach(tp->netdev); | |
ebc2ec48 | 1107 | return; |
ac718b69 | 1108 | case -ENOENT: |
1109 | return; /* the urb is in unlink state */ | |
1110 | case -ETIME: | |
4a8deae2 HW |
1111 | if (net_ratelimit()) |
1112 | netdev_warn(netdev, "maybe reset is needed?\n"); | |
ebc2ec48 | 1113 | break; |
ac718b69 | 1114 | default: |
4a8deae2 HW |
1115 | if (net_ratelimit()) |
1116 | netdev_warn(netdev, "Rx status %d\n", status); | |
ebc2ec48 | 1117 | break; |
ac718b69 | 1118 | } |
1119 | ||
a0fccd48 | 1120 | r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ac718b69 | 1121 | } |
1122 | ||
ebc2ec48 | 1123 | static void write_bulk_callback(struct urb *urb) |
ac718b69 | 1124 | { |
ebc2ec48 | 1125 | struct net_device_stats *stats; |
d104eafa | 1126 | struct net_device *netdev; |
ebc2ec48 | 1127 | struct tx_agg *agg; |
ac718b69 | 1128 | struct r8152 *tp; |
ebc2ec48 | 1129 | int status = urb->status; |
ac718b69 | 1130 | |
ebc2ec48 | 1131 | agg = urb->context; |
1132 | if (!agg) | |
ac718b69 | 1133 | return; |
1134 | ||
ebc2ec48 | 1135 | tp = agg->context; |
1136 | if (!tp) | |
1137 | return; | |
1138 | ||
d104eafa | 1139 | netdev = tp->netdev; |
05e0f1aa | 1140 | stats = &netdev->stats; |
ebc2ec48 | 1141 | if (status) { |
4a8deae2 | 1142 | if (net_ratelimit()) |
d104eafa | 1143 | netdev_warn(netdev, "Tx status %d\n", status); |
ebc2ec48 | 1144 | stats->tx_errors += agg->skb_num; |
ac718b69 | 1145 | } else { |
ebc2ec48 | 1146 | stats->tx_packets += agg->skb_num; |
1147 | stats->tx_bytes += agg->skb_len; | |
ac718b69 | 1148 | } |
1149 | ||
2685d410 | 1150 | spin_lock(&tp->tx_lock); |
ebc2ec48 | 1151 | list_add_tail(&agg->list, &tp->tx_free); |
2685d410 | 1152 | spin_unlock(&tp->tx_lock); |
ebc2ec48 | 1153 | |
9a4be1bd | 1154 | usb_autopm_put_interface_async(tp->intf); |
1155 | ||
d104eafa | 1156 | if (!netif_carrier_ok(netdev)) |
ebc2ec48 | 1157 | return; |
1158 | ||
1159 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1160 | return; | |
1161 | ||
1162 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1163 | return; | |
1164 | ||
1165 | if (!skb_queue_empty(&tp->tx_queue)) | |
d823ab68 | 1166 | napi_schedule(&tp->napi); |
ac718b69 | 1167 | } |
1168 | ||
40a82917 | 1169 | static void intr_callback(struct urb *urb) |
1170 | { | |
1171 | struct r8152 *tp; | |
500b6d7e | 1172 | __le16 *d; |
40a82917 | 1173 | int status = urb->status; |
1174 | int res; | |
1175 | ||
1176 | tp = urb->context; | |
1177 | if (!tp) | |
1178 | return; | |
1179 | ||
1180 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1181 | return; | |
1182 | ||
1183 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1184 | return; | |
1185 | ||
1186 | switch (status) { | |
1187 | case 0: /* success */ | |
1188 | break; | |
1189 | case -ECONNRESET: /* unlink */ | |
1190 | case -ESHUTDOWN: | |
1191 | netif_device_detach(tp->netdev); | |
1192 | case -ENOENT: | |
d59c876d | 1193 | case -EPROTO: |
1194 | netif_info(tp, intr, tp->netdev, | |
1195 | "Stop submitting intr, status %d\n", status); | |
40a82917 | 1196 | return; |
1197 | case -EOVERFLOW: | |
1198 | netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); | |
1199 | goto resubmit; | |
1200 | /* -EPIPE: should clear the halt */ | |
1201 | default: | |
1202 | netif_info(tp, intr, tp->netdev, "intr status %d\n", status); | |
1203 | goto resubmit; | |
1204 | } | |
1205 | ||
1206 | d = urb->transfer_buffer; | |
1207 | if (INTR_LINK & __le16_to_cpu(d[0])) { | |
51d979fa | 1208 | if (!netif_carrier_ok(tp->netdev)) { |
40a82917 | 1209 | set_bit(RTL8152_LINK_CHG, &tp->flags); |
1210 | schedule_delayed_work(&tp->schedule, 0); | |
1211 | } | |
1212 | } else { | |
51d979fa | 1213 | if (netif_carrier_ok(tp->netdev)) { |
40a82917 | 1214 | set_bit(RTL8152_LINK_CHG, &tp->flags); |
1215 | schedule_delayed_work(&tp->schedule, 0); | |
1216 | } | |
1217 | } | |
1218 | ||
1219 | resubmit: | |
1220 | res = usb_submit_urb(urb, GFP_ATOMIC); | |
67610496 | 1221 | if (res == -ENODEV) { |
1222 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
40a82917 | 1223 | netif_device_detach(tp->netdev); |
67610496 | 1224 | } else if (res) { |
40a82917 | 1225 | netif_err(tp, intr, tp->netdev, |
4a8deae2 | 1226 | "can't resubmit intr, status %d\n", res); |
67610496 | 1227 | } |
40a82917 | 1228 | } |
1229 | ||
ebc2ec48 | 1230 | static inline void *rx_agg_align(void *data) |
1231 | { | |
8e1f51bd | 1232 | return (void *)ALIGN((uintptr_t)data, RX_ALIGN); |
ebc2ec48 | 1233 | } |
1234 | ||
1235 | static inline void *tx_agg_align(void *data) | |
1236 | { | |
8e1f51bd | 1237 | return (void *)ALIGN((uintptr_t)data, TX_ALIGN); |
ebc2ec48 | 1238 | } |
1239 | ||
1240 | static void free_all_mem(struct r8152 *tp) | |
1241 | { | |
1242 | int i; | |
1243 | ||
1244 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
9629e3c0 | 1245 | usb_free_urb(tp->rx_info[i].urb); |
1246 | tp->rx_info[i].urb = NULL; | |
ebc2ec48 | 1247 | |
9629e3c0 | 1248 | kfree(tp->rx_info[i].buffer); |
1249 | tp->rx_info[i].buffer = NULL; | |
1250 | tp->rx_info[i].head = NULL; | |
ebc2ec48 | 1251 | } |
1252 | ||
1253 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
9629e3c0 | 1254 | usb_free_urb(tp->tx_info[i].urb); |
1255 | tp->tx_info[i].urb = NULL; | |
ebc2ec48 | 1256 | |
9629e3c0 | 1257 | kfree(tp->tx_info[i].buffer); |
1258 | tp->tx_info[i].buffer = NULL; | |
1259 | tp->tx_info[i].head = NULL; | |
ebc2ec48 | 1260 | } |
40a82917 | 1261 | |
9629e3c0 | 1262 | usb_free_urb(tp->intr_urb); |
1263 | tp->intr_urb = NULL; | |
40a82917 | 1264 | |
9629e3c0 | 1265 | kfree(tp->intr_buff); |
1266 | tp->intr_buff = NULL; | |
ebc2ec48 | 1267 | } |
1268 | ||
1269 | static int alloc_all_mem(struct r8152 *tp) | |
1270 | { | |
1271 | struct net_device *netdev = tp->netdev; | |
40a82917 | 1272 | struct usb_interface *intf = tp->intf; |
1273 | struct usb_host_interface *alt = intf->cur_altsetting; | |
1274 | struct usb_host_endpoint *ep_intr = alt->endpoint + 2; | |
ebc2ec48 | 1275 | struct urb *urb; |
1276 | int node, i; | |
1277 | u8 *buf; | |
1278 | ||
1279 | node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; | |
1280 | ||
1281 | spin_lock_init(&tp->rx_lock); | |
1282 | spin_lock_init(&tp->tx_lock); | |
ebc2ec48 | 1283 | INIT_LIST_HEAD(&tp->tx_free); |
1284 | skb_queue_head_init(&tp->tx_queue); | |
d823ab68 | 1285 | skb_queue_head_init(&tp->rx_queue); |
ebc2ec48 | 1286 | |
1287 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
52aec126 | 1288 | buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); |
ebc2ec48 | 1289 | if (!buf) |
1290 | goto err1; | |
1291 | ||
1292 | if (buf != rx_agg_align(buf)) { | |
1293 | kfree(buf); | |
52aec126 | 1294 | buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, |
8e1f51bd | 1295 | node); |
ebc2ec48 | 1296 | if (!buf) |
1297 | goto err1; | |
1298 | } | |
1299 | ||
1300 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1301 | if (!urb) { | |
1302 | kfree(buf); | |
1303 | goto err1; | |
1304 | } | |
1305 | ||
1306 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1307 | tp->rx_info[i].context = tp; | |
1308 | tp->rx_info[i].urb = urb; | |
1309 | tp->rx_info[i].buffer = buf; | |
1310 | tp->rx_info[i].head = rx_agg_align(buf); | |
1311 | } | |
1312 | ||
1313 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
52aec126 | 1314 | buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); |
ebc2ec48 | 1315 | if (!buf) |
1316 | goto err1; | |
1317 | ||
1318 | if (buf != tx_agg_align(buf)) { | |
1319 | kfree(buf); | |
52aec126 | 1320 | buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, |
8e1f51bd | 1321 | node); |
ebc2ec48 | 1322 | if (!buf) |
1323 | goto err1; | |
1324 | } | |
1325 | ||
1326 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1327 | if (!urb) { | |
1328 | kfree(buf); | |
1329 | goto err1; | |
1330 | } | |
1331 | ||
1332 | INIT_LIST_HEAD(&tp->tx_info[i].list); | |
1333 | tp->tx_info[i].context = tp; | |
1334 | tp->tx_info[i].urb = urb; | |
1335 | tp->tx_info[i].buffer = buf; | |
1336 | tp->tx_info[i].head = tx_agg_align(buf); | |
1337 | ||
1338 | list_add_tail(&tp->tx_info[i].list, &tp->tx_free); | |
1339 | } | |
1340 | ||
40a82917 | 1341 | tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); |
1342 | if (!tp->intr_urb) | |
1343 | goto err1; | |
1344 | ||
1345 | tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); | |
1346 | if (!tp->intr_buff) | |
1347 | goto err1; | |
1348 | ||
1349 | tp->intr_interval = (int)ep_intr->desc.bInterval; | |
1350 | usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), | |
b209af99 | 1351 | tp->intr_buff, INTBUFSIZE, intr_callback, |
1352 | tp, tp->intr_interval); | |
40a82917 | 1353 | |
ebc2ec48 | 1354 | return 0; |
1355 | ||
1356 | err1: | |
1357 | free_all_mem(tp); | |
1358 | return -ENOMEM; | |
1359 | } | |
1360 | ||
0de98f6c | 1361 | static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) |
1362 | { | |
1363 | struct tx_agg *agg = NULL; | |
1364 | unsigned long flags; | |
1365 | ||
21949ab7 | 1366 | if (list_empty(&tp->tx_free)) |
1367 | return NULL; | |
1368 | ||
0de98f6c | 1369 | spin_lock_irqsave(&tp->tx_lock, flags); |
1370 | if (!list_empty(&tp->tx_free)) { | |
1371 | struct list_head *cursor; | |
1372 | ||
1373 | cursor = tp->tx_free.next; | |
1374 | list_del_init(cursor); | |
1375 | agg = list_entry(cursor, struct tx_agg, list); | |
1376 | } | |
1377 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1378 | ||
1379 | return agg; | |
1380 | } | |
1381 | ||
b209af99 | 1382 | /* r8152_csum_workaround() |
6128d1bb | 1383 | * The hw limites the value the transport offset. When the offset is out of the |
1384 | * range, calculate the checksum by sw. | |
1385 | */ | |
1386 | static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, | |
1387 | struct sk_buff_head *list) | |
1388 | { | |
1389 | if (skb_shinfo(skb)->gso_size) { | |
1390 | netdev_features_t features = tp->netdev->features; | |
1391 | struct sk_buff_head seg_list; | |
1392 | struct sk_buff *segs, *nskb; | |
1393 | ||
a91d45f1 | 1394 | features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); |
6128d1bb | 1395 | segs = skb_gso_segment(skb, features); |
1396 | if (IS_ERR(segs) || !segs) | |
1397 | goto drop; | |
1398 | ||
1399 | __skb_queue_head_init(&seg_list); | |
1400 | ||
1401 | do { | |
1402 | nskb = segs; | |
1403 | segs = segs->next; | |
1404 | nskb->next = NULL; | |
1405 | __skb_queue_tail(&seg_list, nskb); | |
1406 | } while (segs); | |
1407 | ||
1408 | skb_queue_splice(&seg_list, list); | |
1409 | dev_kfree_skb(skb); | |
1410 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1411 | if (skb_checksum_help(skb) < 0) | |
1412 | goto drop; | |
1413 | ||
1414 | __skb_queue_head(list, skb); | |
1415 | } else { | |
1416 | struct net_device_stats *stats; | |
1417 | ||
1418 | drop: | |
1419 | stats = &tp->netdev->stats; | |
1420 | stats->tx_dropped++; | |
1421 | dev_kfree_skb(skb); | |
1422 | } | |
1423 | } | |
1424 | ||
b209af99 | 1425 | /* msdn_giant_send_check() |
6128d1bb | 1426 | * According to the document of microsoft, the TCP Pseudo Header excludes the |
1427 | * packet length for IPv6 TCP large packets. | |
1428 | */ | |
1429 | static int msdn_giant_send_check(struct sk_buff *skb) | |
1430 | { | |
1431 | const struct ipv6hdr *ipv6h; | |
1432 | struct tcphdr *th; | |
fcb308d5 | 1433 | int ret; |
1434 | ||
1435 | ret = skb_cow_head(skb, 0); | |
1436 | if (ret) | |
1437 | return ret; | |
6128d1bb | 1438 | |
1439 | ipv6h = ipv6_hdr(skb); | |
1440 | th = tcp_hdr(skb); | |
1441 | ||
1442 | th->check = 0; | |
1443 | th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); | |
1444 | ||
fcb308d5 | 1445 | return ret; |
6128d1bb | 1446 | } |
1447 | ||
c5554298 | 1448 | static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) |
1449 | { | |
df8a39de | 1450 | if (skb_vlan_tag_present(skb)) { |
c5554298 | 1451 | u32 opts2; |
1452 | ||
df8a39de | 1453 | opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); |
c5554298 | 1454 | desc->opts2 |= cpu_to_le32(opts2); |
1455 | } | |
1456 | } | |
1457 | ||
1458 | static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) | |
1459 | { | |
1460 | u32 opts2 = le32_to_cpu(desc->opts2); | |
1461 | ||
1462 | if (opts2 & RX_VLAN_TAG) | |
1463 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), | |
1464 | swab16(opts2 & 0xffff)); | |
1465 | } | |
1466 | ||
60c89071 | 1467 | static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, |
1468 | struct sk_buff *skb, u32 len, u32 transport_offset) | |
1469 | { | |
1470 | u32 mss = skb_shinfo(skb)->gso_size; | |
1471 | u32 opts1, opts2 = 0; | |
1472 | int ret = TX_CSUM_SUCCESS; | |
1473 | ||
1474 | WARN_ON_ONCE(len > TX_LEN_MAX); | |
1475 | ||
1476 | opts1 = len | TX_FS | TX_LS; | |
1477 | ||
1478 | if (mss) { | |
6128d1bb | 1479 | if (transport_offset > GTTCPHO_MAX) { |
1480 | netif_warn(tp, tx_err, tp->netdev, | |
1481 | "Invalid transport offset 0x%x for TSO\n", | |
1482 | transport_offset); | |
1483 | ret = TX_CSUM_TSO; | |
1484 | goto unavailable; | |
1485 | } | |
1486 | ||
6e74d174 | 1487 | switch (vlan_get_protocol(skb)) { |
60c89071 | 1488 | case htons(ETH_P_IP): |
1489 | opts1 |= GTSENDV4; | |
1490 | break; | |
1491 | ||
6128d1bb | 1492 | case htons(ETH_P_IPV6): |
fcb308d5 | 1493 | if (msdn_giant_send_check(skb)) { |
1494 | ret = TX_CSUM_TSO; | |
1495 | goto unavailable; | |
1496 | } | |
6128d1bb | 1497 | opts1 |= GTSENDV6; |
6128d1bb | 1498 | break; |
1499 | ||
60c89071 | 1500 | default: |
1501 | WARN_ON_ONCE(1); | |
1502 | break; | |
1503 | } | |
1504 | ||
1505 | opts1 |= transport_offset << GTTCPHO_SHIFT; | |
1506 | opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; | |
1507 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1508 | u8 ip_protocol; | |
5bd23881 | 1509 | |
6128d1bb | 1510 | if (transport_offset > TCPHO_MAX) { |
1511 | netif_warn(tp, tx_err, tp->netdev, | |
1512 | "Invalid transport offset 0x%x\n", | |
1513 | transport_offset); | |
1514 | ret = TX_CSUM_NONE; | |
1515 | goto unavailable; | |
1516 | } | |
1517 | ||
6e74d174 | 1518 | switch (vlan_get_protocol(skb)) { |
5bd23881 | 1519 | case htons(ETH_P_IP): |
1520 | opts2 |= IPV4_CS; | |
1521 | ip_protocol = ip_hdr(skb)->protocol; | |
1522 | break; | |
1523 | ||
1524 | case htons(ETH_P_IPV6): | |
1525 | opts2 |= IPV6_CS; | |
1526 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
1527 | break; | |
1528 | ||
1529 | default: | |
1530 | ip_protocol = IPPROTO_RAW; | |
1531 | break; | |
1532 | } | |
1533 | ||
60c89071 | 1534 | if (ip_protocol == IPPROTO_TCP) |
5bd23881 | 1535 | opts2 |= TCP_CS; |
60c89071 | 1536 | else if (ip_protocol == IPPROTO_UDP) |
5bd23881 | 1537 | opts2 |= UDP_CS; |
60c89071 | 1538 | else |
5bd23881 | 1539 | WARN_ON_ONCE(1); |
5bd23881 | 1540 | |
60c89071 | 1541 | opts2 |= transport_offset << TCPHO_SHIFT; |
5bd23881 | 1542 | } |
60c89071 | 1543 | |
1544 | desc->opts2 = cpu_to_le32(opts2); | |
1545 | desc->opts1 = cpu_to_le32(opts1); | |
1546 | ||
6128d1bb | 1547 | unavailable: |
60c89071 | 1548 | return ret; |
5bd23881 | 1549 | } |
1550 | ||
b1379d9a | 1551 | static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) |
1552 | { | |
d84130a1 | 1553 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
9a4be1bd | 1554 | int remain, ret; |
b1379d9a | 1555 | u8 *tx_data; |
1556 | ||
d84130a1 | 1557 | __skb_queue_head_init(&skb_head); |
0c3121fc | 1558 | spin_lock(&tx_queue->lock); |
d84130a1 | 1559 | skb_queue_splice_init(tx_queue, &skb_head); |
0c3121fc | 1560 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1561 | |
b1379d9a | 1562 | tx_data = agg->head; |
b209af99 | 1563 | agg->skb_num = 0; |
1564 | agg->skb_len = 0; | |
52aec126 | 1565 | remain = agg_buf_sz; |
b1379d9a | 1566 | |
7937f9e5 | 1567 | while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { |
b1379d9a | 1568 | struct tx_desc *tx_desc; |
1569 | struct sk_buff *skb; | |
1570 | unsigned int len; | |
60c89071 | 1571 | u32 offset; |
b1379d9a | 1572 | |
d84130a1 | 1573 | skb = __skb_dequeue(&skb_head); |
b1379d9a | 1574 | if (!skb) |
1575 | break; | |
1576 | ||
60c89071 | 1577 | len = skb->len + sizeof(*tx_desc); |
1578 | ||
1579 | if (len > remain) { | |
d84130a1 | 1580 | __skb_queue_head(&skb_head, skb); |
b1379d9a | 1581 | break; |
1582 | } | |
1583 | ||
7937f9e5 | 1584 | tx_data = tx_agg_align(tx_data); |
b1379d9a | 1585 | tx_desc = (struct tx_desc *)tx_data; |
60c89071 | 1586 | |
1587 | offset = (u32)skb_transport_offset(skb); | |
1588 | ||
6128d1bb | 1589 | if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { |
1590 | r8152_csum_workaround(tp, skb, &skb_head); | |
1591 | continue; | |
1592 | } | |
60c89071 | 1593 | |
c5554298 | 1594 | rtl_tx_vlan_tag(tx_desc, skb); |
1595 | ||
b1379d9a | 1596 | tx_data += sizeof(*tx_desc); |
1597 | ||
60c89071 | 1598 | len = skb->len; |
1599 | if (skb_copy_bits(skb, 0, tx_data, len) < 0) { | |
1600 | struct net_device_stats *stats = &tp->netdev->stats; | |
1601 | ||
1602 | stats->tx_dropped++; | |
1603 | dev_kfree_skb_any(skb); | |
1604 | tx_data -= sizeof(*tx_desc); | |
1605 | continue; | |
1606 | } | |
1607 | ||
1608 | tx_data += len; | |
b1379d9a | 1609 | agg->skb_len += len; |
60c89071 | 1610 | agg->skb_num++; |
1611 | ||
b1379d9a | 1612 | dev_kfree_skb_any(skb); |
1613 | ||
52aec126 | 1614 | remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); |
b1379d9a | 1615 | } |
1616 | ||
d84130a1 | 1617 | if (!skb_queue_empty(&skb_head)) { |
0c3121fc | 1618 | spin_lock(&tx_queue->lock); |
d84130a1 | 1619 | skb_queue_splice(&skb_head, tx_queue); |
0c3121fc | 1620 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1621 | } |
1622 | ||
0c3121fc | 1623 | netif_tx_lock(tp->netdev); |
dd1b119c | 1624 | |
1625 | if (netif_queue_stopped(tp->netdev) && | |
1626 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) | |
1627 | netif_wake_queue(tp->netdev); | |
1628 | ||
0c3121fc | 1629 | netif_tx_unlock(tp->netdev); |
9a4be1bd | 1630 | |
0c3121fc | 1631 | ret = usb_autopm_get_interface_async(tp->intf); |
9a4be1bd | 1632 | if (ret < 0) |
1633 | goto out_tx_fill; | |
dd1b119c | 1634 | |
b1379d9a | 1635 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), |
1636 | agg->head, (int)(tx_data - (u8 *)agg->head), | |
1637 | (usb_complete_t)write_bulk_callback, agg); | |
1638 | ||
0c3121fc | 1639 | ret = usb_submit_urb(agg->urb, GFP_ATOMIC); |
9a4be1bd | 1640 | if (ret < 0) |
0c3121fc | 1641 | usb_autopm_put_interface_async(tp->intf); |
9a4be1bd | 1642 | |
1643 | out_tx_fill: | |
1644 | return ret; | |
b1379d9a | 1645 | } |
1646 | ||
565cab0a | 1647 | static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) |
1648 | { | |
1649 | u8 checksum = CHECKSUM_NONE; | |
1650 | u32 opts2, opts3; | |
1651 | ||
1652 | if (tp->version == RTL_VER_01) | |
1653 | goto return_result; | |
1654 | ||
1655 | opts2 = le32_to_cpu(rx_desc->opts2); | |
1656 | opts3 = le32_to_cpu(rx_desc->opts3); | |
1657 | ||
1658 | if (opts2 & RD_IPV4_CS) { | |
1659 | if (opts3 & IPF) | |
1660 | checksum = CHECKSUM_NONE; | |
1661 | else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) | |
1662 | checksum = CHECKSUM_NONE; | |
1663 | else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) | |
1664 | checksum = CHECKSUM_NONE; | |
1665 | else | |
1666 | checksum = CHECKSUM_UNNECESSARY; | |
6128d1bb | 1667 | } else if (RD_IPV6_CS) { |
1668 | if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) | |
1669 | checksum = CHECKSUM_UNNECESSARY; | |
1670 | else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) | |
1671 | checksum = CHECKSUM_UNNECESSARY; | |
565cab0a | 1672 | } |
1673 | ||
1674 | return_result: | |
1675 | return checksum; | |
1676 | } | |
1677 | ||
d823ab68 | 1678 | static int rx_bottom(struct r8152 *tp, int budget) |
ebc2ec48 | 1679 | { |
a5a4f468 | 1680 | unsigned long flags; |
d84130a1 | 1681 | struct list_head *cursor, *next, rx_queue; |
e1a2ca92 | 1682 | int ret = 0, work_done = 0; |
d823ab68 | 1683 | |
1684 | if (!skb_queue_empty(&tp->rx_queue)) { | |
1685 | while (work_done < budget) { | |
1686 | struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); | |
1687 | struct net_device *netdev = tp->netdev; | |
1688 | struct net_device_stats *stats = &netdev->stats; | |
1689 | unsigned int pkt_len; | |
1690 | ||
1691 | if (!skb) | |
1692 | break; | |
1693 | ||
1694 | pkt_len = skb->len; | |
1695 | napi_gro_receive(&tp->napi, skb); | |
1696 | work_done++; | |
1697 | stats->rx_packets++; | |
1698 | stats->rx_bytes += pkt_len; | |
1699 | } | |
1700 | } | |
ebc2ec48 | 1701 | |
d84130a1 | 1702 | if (list_empty(&tp->rx_done)) |
d823ab68 | 1703 | goto out1; |
d84130a1 | 1704 | |
1705 | INIT_LIST_HEAD(&rx_queue); | |
a5a4f468 | 1706 | spin_lock_irqsave(&tp->rx_lock, flags); |
d84130a1 | 1707 | list_splice_init(&tp->rx_done, &rx_queue); |
1708 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
1709 | ||
1710 | list_for_each_safe(cursor, next, &rx_queue) { | |
43a4478d | 1711 | struct rx_desc *rx_desc; |
1712 | struct rx_agg *agg; | |
43a4478d | 1713 | int len_used = 0; |
1714 | struct urb *urb; | |
1715 | u8 *rx_data; | |
43a4478d | 1716 | |
ebc2ec48 | 1717 | list_del_init(cursor); |
ebc2ec48 | 1718 | |
1719 | agg = list_entry(cursor, struct rx_agg, list); | |
1720 | urb = agg->urb; | |
0de98f6c | 1721 | if (urb->actual_length < ETH_ZLEN) |
1722 | goto submit; | |
ebc2ec48 | 1723 | |
ebc2ec48 | 1724 | rx_desc = agg->head; |
1725 | rx_data = agg->head; | |
7937f9e5 | 1726 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1727 | |
7937f9e5 | 1728 | while (urb->actual_length > len_used) { |
43a4478d | 1729 | struct net_device *netdev = tp->netdev; |
05e0f1aa | 1730 | struct net_device_stats *stats = &netdev->stats; |
7937f9e5 | 1731 | unsigned int pkt_len; |
43a4478d | 1732 | struct sk_buff *skb; |
1733 | ||
7937f9e5 | 1734 | pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; |
ebc2ec48 | 1735 | if (pkt_len < ETH_ZLEN) |
1736 | break; | |
1737 | ||
7937f9e5 | 1738 | len_used += pkt_len; |
1739 | if (urb->actual_length < len_used) | |
1740 | break; | |
1741 | ||
8e1f51bd | 1742 | pkt_len -= CRC_SIZE; |
ebc2ec48 | 1743 | rx_data += sizeof(struct rx_desc); |
1744 | ||
1745 | skb = netdev_alloc_skb_ip_align(netdev, pkt_len); | |
1746 | if (!skb) { | |
1747 | stats->rx_dropped++; | |
5e2f7485 | 1748 | goto find_next_rx; |
ebc2ec48 | 1749 | } |
565cab0a | 1750 | |
1751 | skb->ip_summed = r8152_rx_csum(tp, rx_desc); | |
ebc2ec48 | 1752 | memcpy(skb->data, rx_data, pkt_len); |
1753 | skb_put(skb, pkt_len); | |
1754 | skb->protocol = eth_type_trans(skb, netdev); | |
c5554298 | 1755 | rtl_rx_vlan_tag(rx_desc, skb); |
d823ab68 | 1756 | if (work_done < budget) { |
1757 | napi_gro_receive(&tp->napi, skb); | |
1758 | work_done++; | |
1759 | stats->rx_packets++; | |
1760 | stats->rx_bytes += pkt_len; | |
1761 | } else { | |
1762 | __skb_queue_tail(&tp->rx_queue, skb); | |
1763 | } | |
ebc2ec48 | 1764 | |
5e2f7485 | 1765 | find_next_rx: |
8e1f51bd | 1766 | rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); |
ebc2ec48 | 1767 | rx_desc = (struct rx_desc *)rx_data; |
ebc2ec48 | 1768 | len_used = (int)(rx_data - (u8 *)agg->head); |
7937f9e5 | 1769 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1770 | } |
1771 | ||
0de98f6c | 1772 | submit: |
e1a2ca92 | 1773 | if (!ret) { |
1774 | ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); | |
1775 | } else { | |
1776 | urb->actual_length = 0; | |
1777 | list_add_tail(&agg->list, next); | |
1778 | } | |
1779 | } | |
1780 | ||
1781 | if (!list_empty(&rx_queue)) { | |
1782 | spin_lock_irqsave(&tp->rx_lock, flags); | |
1783 | list_splice_tail(&rx_queue, &tp->rx_done); | |
1784 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
ebc2ec48 | 1785 | } |
d823ab68 | 1786 | |
1787 | out1: | |
1788 | return work_done; | |
ebc2ec48 | 1789 | } |
1790 | ||
1791 | static void tx_bottom(struct r8152 *tp) | |
1792 | { | |
ebc2ec48 | 1793 | int res; |
1794 | ||
b1379d9a | 1795 | do { |
1796 | struct tx_agg *agg; | |
ebc2ec48 | 1797 | |
b1379d9a | 1798 | if (skb_queue_empty(&tp->tx_queue)) |
ebc2ec48 | 1799 | break; |
1800 | ||
b1379d9a | 1801 | agg = r8152_get_tx_agg(tp); |
1802 | if (!agg) | |
ebc2ec48 | 1803 | break; |
ebc2ec48 | 1804 | |
b1379d9a | 1805 | res = r8152_tx_agg_fill(tp, agg); |
1806 | if (res) { | |
05e0f1aa | 1807 | struct net_device *netdev = tp->netdev; |
ebc2ec48 | 1808 | |
b1379d9a | 1809 | if (res == -ENODEV) { |
67610496 | 1810 | set_bit(RTL8152_UNPLUG, &tp->flags); |
b1379d9a | 1811 | netif_device_detach(netdev); |
1812 | } else { | |
05e0f1aa | 1813 | struct net_device_stats *stats = &netdev->stats; |
1814 | unsigned long flags; | |
1815 | ||
b1379d9a | 1816 | netif_warn(tp, tx_err, netdev, |
1817 | "failed tx_urb %d\n", res); | |
1818 | stats->tx_dropped += agg->skb_num; | |
db8515ef | 1819 | |
b1379d9a | 1820 | spin_lock_irqsave(&tp->tx_lock, flags); |
1821 | list_add_tail(&agg->list, &tp->tx_free); | |
1822 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1823 | } | |
ebc2ec48 | 1824 | } |
b1379d9a | 1825 | } while (res == 0); |
ebc2ec48 | 1826 | } |
1827 | ||
d823ab68 | 1828 | static void bottom_half(struct r8152 *tp) |
ac718b69 | 1829 | { |
ebc2ec48 | 1830 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1831 | return; | |
1832 | ||
1833 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
ac718b69 | 1834 | return; |
ebc2ec48 | 1835 | |
7559fb2f | 1836 | /* When link down, the driver would cancel all bulks. */ |
1837 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1838 | if (!netif_carrier_ok(tp->netdev)) |
ac718b69 | 1839 | return; |
ebc2ec48 | 1840 | |
d823ab68 | 1841 | clear_bit(SCHEDULE_NAPI, &tp->flags); |
9451a11c | 1842 | |
0c3121fc | 1843 | tx_bottom(tp); |
ebc2ec48 | 1844 | } |
1845 | ||
d823ab68 | 1846 | static int r8152_poll(struct napi_struct *napi, int budget) |
1847 | { | |
1848 | struct r8152 *tp = container_of(napi, struct r8152, napi); | |
1849 | int work_done; | |
1850 | ||
1851 | work_done = rx_bottom(tp, budget); | |
1852 | bottom_half(tp); | |
1853 | ||
1854 | if (work_done < budget) { | |
1855 | napi_complete(napi); | |
1856 | if (!list_empty(&tp->rx_done)) | |
1857 | napi_schedule(napi); | |
1858 | } | |
1859 | ||
1860 | return work_done; | |
1861 | } | |
1862 | ||
ebc2ec48 | 1863 | static |
1864 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) | |
1865 | { | |
a0fccd48 | 1866 | int ret; |
1867 | ||
ef827a5b | 1868 | /* The rx would be stopped, so skip submitting */ |
1869 | if (test_bit(RTL8152_UNPLUG, &tp->flags) || | |
1870 | !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) | |
1871 | return 0; | |
1872 | ||
ebc2ec48 | 1873 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), |
52aec126 | 1874 | agg->head, agg_buf_sz, |
b209af99 | 1875 | (usb_complete_t)read_bulk_callback, agg); |
ebc2ec48 | 1876 | |
a0fccd48 | 1877 | ret = usb_submit_urb(agg->urb, mem_flags); |
1878 | if (ret == -ENODEV) { | |
1879 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
1880 | netif_device_detach(tp->netdev); | |
1881 | } else if (ret) { | |
1882 | struct urb *urb = agg->urb; | |
1883 | unsigned long flags; | |
1884 | ||
1885 | urb->actual_length = 0; | |
1886 | spin_lock_irqsave(&tp->rx_lock, flags); | |
1887 | list_add_tail(&agg->list, &tp->rx_done); | |
1888 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
d823ab68 | 1889 | |
1890 | netif_err(tp, rx_err, tp->netdev, | |
1891 | "Couldn't submit rx[%p], ret = %d\n", agg, ret); | |
1892 | ||
1893 | napi_schedule(&tp->napi); | |
a0fccd48 | 1894 | } |
1895 | ||
1896 | return ret; | |
ac718b69 | 1897 | } |
1898 | ||
00a5e360 | 1899 | static void rtl_drop_queued_tx(struct r8152 *tp) |
1900 | { | |
1901 | struct net_device_stats *stats = &tp->netdev->stats; | |
d84130a1 | 1902 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
00a5e360 | 1903 | struct sk_buff *skb; |
1904 | ||
d84130a1 | 1905 | if (skb_queue_empty(tx_queue)) |
1906 | return; | |
1907 | ||
1908 | __skb_queue_head_init(&skb_head); | |
2685d410 | 1909 | spin_lock_bh(&tx_queue->lock); |
d84130a1 | 1910 | skb_queue_splice_init(tx_queue, &skb_head); |
2685d410 | 1911 | spin_unlock_bh(&tx_queue->lock); |
d84130a1 | 1912 | |
1913 | while ((skb = __skb_dequeue(&skb_head))) { | |
00a5e360 | 1914 | dev_kfree_skb(skb); |
1915 | stats->tx_dropped++; | |
1916 | } | |
1917 | } | |
1918 | ||
ac718b69 | 1919 | static void rtl8152_tx_timeout(struct net_device *netdev) |
1920 | { | |
1921 | struct r8152 *tp = netdev_priv(netdev); | |
ebc2ec48 | 1922 | |
4a8deae2 | 1923 | netif_warn(tp, tx_err, netdev, "Tx timeout\n"); |
37608f3e | 1924 | |
1925 | usb_queue_reset_device(tp->intf); | |
ac718b69 | 1926 | } |
1927 | ||
1928 | static void rtl8152_set_rx_mode(struct net_device *netdev) | |
1929 | { | |
1930 | struct r8152 *tp = netdev_priv(netdev); | |
1931 | ||
51d979fa | 1932 | if (netif_carrier_ok(netdev)) { |
ac718b69 | 1933 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
40a82917 | 1934 | schedule_delayed_work(&tp->schedule, 0); |
1935 | } | |
ac718b69 | 1936 | } |
1937 | ||
1938 | static void _rtl8152_set_rx_mode(struct net_device *netdev) | |
1939 | { | |
1940 | struct r8152 *tp = netdev_priv(netdev); | |
31787f53 | 1941 | u32 mc_filter[2]; /* Multicast hash filter */ |
1942 | __le32 tmp[2]; | |
ac718b69 | 1943 | u32 ocp_data; |
1944 | ||
ac718b69 | 1945 | netif_stop_queue(netdev); |
1946 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1947 | ocp_data &= ~RCR_ACPT_ALL; | |
1948 | ocp_data |= RCR_AB | RCR_APM; | |
1949 | ||
1950 | if (netdev->flags & IFF_PROMISC) { | |
1951 | /* Unconditionally log net taps. */ | |
1952 | netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); | |
1953 | ocp_data |= RCR_AM | RCR_AAP; | |
b209af99 | 1954 | mc_filter[1] = 0xffffffff; |
1955 | mc_filter[0] = 0xffffffff; | |
ac718b69 | 1956 | } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || |
1957 | (netdev->flags & IFF_ALLMULTI)) { | |
1958 | /* Too many to filter perfectly -- accept all multicasts. */ | |
1959 | ocp_data |= RCR_AM; | |
b209af99 | 1960 | mc_filter[1] = 0xffffffff; |
1961 | mc_filter[0] = 0xffffffff; | |
ac718b69 | 1962 | } else { |
1963 | struct netdev_hw_addr *ha; | |
1964 | ||
b209af99 | 1965 | mc_filter[1] = 0; |
1966 | mc_filter[0] = 0; | |
ac718b69 | 1967 | netdev_for_each_mc_addr(ha, netdev) { |
1968 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
b209af99 | 1969 | |
ac718b69 | 1970 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
1971 | ocp_data |= RCR_AM; | |
1972 | } | |
1973 | } | |
1974 | ||
31787f53 | 1975 | tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); |
1976 | tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); | |
ac718b69 | 1977 | |
31787f53 | 1978 | pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); |
ac718b69 | 1979 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
1980 | netif_wake_queue(netdev); | |
ac718b69 | 1981 | } |
1982 | ||
a5e31255 | 1983 | static netdev_features_t |
1984 | rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, | |
1985 | netdev_features_t features) | |
1986 | { | |
1987 | u32 mss = skb_shinfo(skb)->gso_size; | |
1988 | int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; | |
1989 | int offset = skb_transport_offset(skb); | |
1990 | ||
1991 | if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) | |
a188222b | 1992 | features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); |
a5e31255 | 1993 | else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) |
1994 | features &= ~NETIF_F_GSO_MASK; | |
1995 | ||
1996 | return features; | |
1997 | } | |
1998 | ||
ac718b69 | 1999 | static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, |
b209af99 | 2000 | struct net_device *netdev) |
ac718b69 | 2001 | { |
2002 | struct r8152 *tp = netdev_priv(netdev); | |
ac718b69 | 2003 | |
ebc2ec48 | 2004 | skb_tx_timestamp(skb); |
ac718b69 | 2005 | |
61598788 | 2006 | skb_queue_tail(&tp->tx_queue, skb); |
ebc2ec48 | 2007 | |
0c3121fc | 2008 | if (!list_empty(&tp->tx_free)) { |
2009 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { | |
d823ab68 | 2010 | set_bit(SCHEDULE_NAPI, &tp->flags); |
0c3121fc | 2011 | schedule_delayed_work(&tp->schedule, 0); |
2012 | } else { | |
2013 | usb_mark_last_busy(tp->udev); | |
d823ab68 | 2014 | napi_schedule(&tp->napi); |
0c3121fc | 2015 | } |
b209af99 | 2016 | } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { |
dd1b119c | 2017 | netif_stop_queue(netdev); |
b209af99 | 2018 | } |
dd1b119c | 2019 | |
ac718b69 | 2020 | return NETDEV_TX_OK; |
2021 | } | |
2022 | ||
2023 | static void r8152b_reset_packet_filter(struct r8152 *tp) | |
2024 | { | |
2025 | u32 ocp_data; | |
2026 | ||
2027 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); | |
2028 | ocp_data &= ~FMC_FCR_MCU_EN; | |
2029 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
2030 | ocp_data |= FMC_FCR_MCU_EN; | |
2031 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
2032 | } | |
2033 | ||
2034 | static void rtl8152_nic_reset(struct r8152 *tp) | |
2035 | { | |
2036 | int i; | |
2037 | ||
2038 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); | |
2039 | ||
2040 | for (i = 0; i < 1000; i++) { | |
2041 | if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) | |
2042 | break; | |
b209af99 | 2043 | usleep_range(100, 400); |
ac718b69 | 2044 | } |
2045 | } | |
2046 | ||
dd1b119c | 2047 | static void set_tx_qlen(struct r8152 *tp) |
2048 | { | |
2049 | struct net_device *netdev = tp->netdev; | |
2050 | ||
52aec126 | 2051 | tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + |
2052 | sizeof(struct tx_desc)); | |
dd1b119c | 2053 | } |
2054 | ||
ac718b69 | 2055 | static inline u8 rtl8152_get_speed(struct r8152 *tp) |
2056 | { | |
2057 | return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); | |
2058 | } | |
2059 | ||
507605a8 | 2060 | static void rtl_set_eee_plus(struct r8152 *tp) |
ac718b69 | 2061 | { |
ebc2ec48 | 2062 | u32 ocp_data; |
ac718b69 | 2063 | u8 speed; |
2064 | ||
2065 | speed = rtl8152_get_speed(tp); | |
ebc2ec48 | 2066 | if (speed & _10bps) { |
ac718b69 | 2067 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); |
ebc2ec48 | 2068 | ocp_data |= EEEP_CR_EEEP_TX; |
ac718b69 | 2069 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
2070 | } else { | |
2071 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); | |
ebc2ec48 | 2072 | ocp_data &= ~EEEP_CR_EEEP_TX; |
ac718b69 | 2073 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
2074 | } | |
507605a8 | 2075 | } |
2076 | ||
00a5e360 | 2077 | static void rxdy_gated_en(struct r8152 *tp, bool enable) |
2078 | { | |
2079 | u32 ocp_data; | |
2080 | ||
2081 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); | |
2082 | if (enable) | |
2083 | ocp_data |= RXDY_GATED_EN; | |
2084 | else | |
2085 | ocp_data &= ~RXDY_GATED_EN; | |
2086 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); | |
2087 | } | |
2088 | ||
445f7f4d | 2089 | static int rtl_start_rx(struct r8152 *tp) |
2090 | { | |
2091 | int i, ret = 0; | |
2092 | ||
2093 | INIT_LIST_HEAD(&tp->rx_done); | |
2094 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
2095 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
2096 | ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); | |
2097 | if (ret) | |
2098 | break; | |
2099 | } | |
2100 | ||
7bcf4f60 | 2101 | if (ret && ++i < RTL8152_MAX_RX) { |
2102 | struct list_head rx_queue; | |
2103 | unsigned long flags; | |
2104 | ||
2105 | INIT_LIST_HEAD(&rx_queue); | |
2106 | ||
2107 | do { | |
2108 | struct rx_agg *agg = &tp->rx_info[i++]; | |
2109 | struct urb *urb = agg->urb; | |
2110 | ||
2111 | urb->actual_length = 0; | |
2112 | list_add_tail(&agg->list, &rx_queue); | |
2113 | } while (i < RTL8152_MAX_RX); | |
2114 | ||
2115 | spin_lock_irqsave(&tp->rx_lock, flags); | |
2116 | list_splice_tail(&rx_queue, &tp->rx_done); | |
2117 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
2118 | } | |
2119 | ||
445f7f4d | 2120 | return ret; |
2121 | } | |
2122 | ||
2123 | static int rtl_stop_rx(struct r8152 *tp) | |
2124 | { | |
2125 | int i; | |
2126 | ||
2127 | for (i = 0; i < RTL8152_MAX_RX; i++) | |
2128 | usb_kill_urb(tp->rx_info[i].urb); | |
2129 | ||
d823ab68 | 2130 | while (!skb_queue_empty(&tp->rx_queue)) |
2131 | dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); | |
2132 | ||
445f7f4d | 2133 | return 0; |
2134 | } | |
2135 | ||
507605a8 | 2136 | static int rtl_enable(struct r8152 *tp) |
2137 | { | |
2138 | u32 ocp_data; | |
ac718b69 | 2139 | |
2140 | r8152b_reset_packet_filter(tp); | |
2141 | ||
2142 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); | |
2143 | ocp_data |= CR_RE | CR_TE; | |
2144 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); | |
2145 | ||
00a5e360 | 2146 | rxdy_gated_en(tp, false); |
ac718b69 | 2147 | |
aa2e0926 | 2148 | return 0; |
ac718b69 | 2149 | } |
2150 | ||
507605a8 | 2151 | static int rtl8152_enable(struct r8152 *tp) |
2152 | { | |
6871438c | 2153 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2154 | return -ENODEV; | |
2155 | ||
507605a8 | 2156 | set_tx_qlen(tp); |
2157 | rtl_set_eee_plus(tp); | |
2158 | ||
2159 | return rtl_enable(tp); | |
2160 | } | |
2161 | ||
464ec10a | 2162 | static void r8153_set_rx_early_timeout(struct r8152 *tp) |
43779f8d | 2163 | { |
464ec10a | 2164 | u32 ocp_data = tp->coalesce / 8; |
43779f8d | 2165 | |
464ec10a | 2166 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data); |
2167 | } | |
2168 | ||
2169 | static void r8153_set_rx_early_size(struct r8152 *tp) | |
2170 | { | |
2171 | u32 mtu = tp->netdev->mtu; | |
2172 | u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 4; | |
2173 | ||
2174 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data); | |
43779f8d | 2175 | } |
2176 | ||
2177 | static int rtl8153_enable(struct r8152 *tp) | |
2178 | { | |
6871438c | 2179 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2180 | return -ENODEV; | |
2181 | ||
b214396f | 2182 | usb_disable_lpm(tp->udev); |
43779f8d | 2183 | set_tx_qlen(tp); |
2184 | rtl_set_eee_plus(tp); | |
464ec10a | 2185 | r8153_set_rx_early_timeout(tp); |
2186 | r8153_set_rx_early_size(tp); | |
43779f8d | 2187 | |
2188 | return rtl_enable(tp); | |
2189 | } | |
2190 | ||
d70b1137 | 2191 | static void rtl_disable(struct r8152 *tp) |
ac718b69 | 2192 | { |
ebc2ec48 | 2193 | u32 ocp_data; |
2194 | int i; | |
ac718b69 | 2195 | |
6871438c | 2196 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2197 | rtl_drop_queued_tx(tp); | |
2198 | return; | |
2199 | } | |
2200 | ||
ac718b69 | 2201 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
2202 | ocp_data &= ~RCR_ACPT_ALL; | |
2203 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2204 | ||
00a5e360 | 2205 | rtl_drop_queued_tx(tp); |
ebc2ec48 | 2206 | |
2207 | for (i = 0; i < RTL8152_MAX_TX; i++) | |
2208 | usb_kill_urb(tp->tx_info[i].urb); | |
ac718b69 | 2209 | |
00a5e360 | 2210 | rxdy_gated_en(tp, true); |
ac718b69 | 2211 | |
2212 | for (i = 0; i < 1000; i++) { | |
2213 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2214 | if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) | |
2215 | break; | |
8ddfa077 | 2216 | usleep_range(1000, 2000); |
ac718b69 | 2217 | } |
2218 | ||
2219 | for (i = 0; i < 1000; i++) { | |
2220 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) | |
2221 | break; | |
8ddfa077 | 2222 | usleep_range(1000, 2000); |
ac718b69 | 2223 | } |
2224 | ||
445f7f4d | 2225 | rtl_stop_rx(tp); |
ac718b69 | 2226 | |
2227 | rtl8152_nic_reset(tp); | |
2228 | } | |
2229 | ||
00a5e360 | 2230 | static void r8152_power_cut_en(struct r8152 *tp, bool enable) |
2231 | { | |
2232 | u32 ocp_data; | |
2233 | ||
2234 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); | |
2235 | if (enable) | |
2236 | ocp_data |= POWER_CUT; | |
2237 | else | |
2238 | ocp_data &= ~POWER_CUT; | |
2239 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); | |
2240 | ||
2241 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); | |
2242 | ocp_data &= ~RESUME_INDICATE; | |
2243 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); | |
00a5e360 | 2244 | } |
2245 | ||
c5554298 | 2246 | static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) |
2247 | { | |
2248 | u32 ocp_data; | |
2249 | ||
2250 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2251 | if (enable) | |
2252 | ocp_data |= CPCR_RX_VLAN; | |
2253 | else | |
2254 | ocp_data &= ~CPCR_RX_VLAN; | |
2255 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2256 | } | |
2257 | ||
2258 | static int rtl8152_set_features(struct net_device *dev, | |
2259 | netdev_features_t features) | |
2260 | { | |
2261 | netdev_features_t changed = features ^ dev->features; | |
2262 | struct r8152 *tp = netdev_priv(dev); | |
405f8a0e | 2263 | int ret; |
2264 | ||
2265 | ret = usb_autopm_get_interface(tp->intf); | |
2266 | if (ret < 0) | |
2267 | goto out; | |
c5554298 | 2268 | |
b5403273 | 2269 | mutex_lock(&tp->control); |
2270 | ||
c5554298 | 2271 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) { |
2272 | if (features & NETIF_F_HW_VLAN_CTAG_RX) | |
2273 | rtl_rx_vlan_en(tp, true); | |
2274 | else | |
2275 | rtl_rx_vlan_en(tp, false); | |
2276 | } | |
2277 | ||
b5403273 | 2278 | mutex_unlock(&tp->control); |
2279 | ||
405f8a0e | 2280 | usb_autopm_put_interface(tp->intf); |
2281 | ||
2282 | out: | |
2283 | return ret; | |
c5554298 | 2284 | } |
2285 | ||
21ff2e89 | 2286 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
2287 | ||
2288 | static u32 __rtl_get_wol(struct r8152 *tp) | |
2289 | { | |
2290 | u32 ocp_data; | |
2291 | u32 wolopts = 0; | |
2292 | ||
2293 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2294 | if (!(ocp_data & LAN_WAKE_EN)) | |
2295 | return 0; | |
2296 | ||
2297 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2298 | if (ocp_data & LINK_ON_WAKE_EN) | |
2299 | wolopts |= WAKE_PHY; | |
2300 | ||
2301 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2302 | if (ocp_data & UWF_EN) | |
2303 | wolopts |= WAKE_UCAST; | |
2304 | if (ocp_data & BWF_EN) | |
2305 | wolopts |= WAKE_BCAST; | |
2306 | if (ocp_data & MWF_EN) | |
2307 | wolopts |= WAKE_MCAST; | |
2308 | ||
2309 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2310 | if (ocp_data & MAGIC_EN) | |
2311 | wolopts |= WAKE_MAGIC; | |
2312 | ||
2313 | return wolopts; | |
2314 | } | |
2315 | ||
2316 | static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) | |
2317 | { | |
2318 | u32 ocp_data; | |
2319 | ||
2320 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2321 | ||
2322 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2323 | ocp_data &= ~LINK_ON_WAKE_EN; | |
2324 | if (wolopts & WAKE_PHY) | |
2325 | ocp_data |= LINK_ON_WAKE_EN; | |
2326 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2327 | ||
2328 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2329 | ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN); | |
2330 | if (wolopts & WAKE_UCAST) | |
2331 | ocp_data |= UWF_EN; | |
2332 | if (wolopts & WAKE_BCAST) | |
2333 | ocp_data |= BWF_EN; | |
2334 | if (wolopts & WAKE_MCAST) | |
2335 | ocp_data |= MWF_EN; | |
2336 | if (wolopts & WAKE_ANY) | |
2337 | ocp_data |= LAN_WAKE_EN; | |
2338 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); | |
2339 | ||
2340 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2341 | ||
2342 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2343 | ocp_data &= ~MAGIC_EN; | |
2344 | if (wolopts & WAKE_MAGIC) | |
2345 | ocp_data |= MAGIC_EN; | |
2346 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); | |
2347 | ||
2348 | if (wolopts & WAKE_ANY) | |
2349 | device_set_wakeup_enable(&tp->udev->dev, true); | |
2350 | else | |
2351 | device_set_wakeup_enable(&tp->udev->dev, false); | |
2352 | } | |
2353 | ||
b214396f | 2354 | static void r8153_u1u2en(struct r8152 *tp, bool enable) |
2355 | { | |
2356 | u8 u1u2[8]; | |
2357 | ||
2358 | if (enable) | |
2359 | memset(u1u2, 0xff, sizeof(u1u2)); | |
2360 | else | |
2361 | memset(u1u2, 0x00, sizeof(u1u2)); | |
2362 | ||
2363 | usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); | |
2364 | } | |
2365 | ||
2366 | static void r8153_u2p3en(struct r8152 *tp, bool enable) | |
2367 | { | |
2368 | u32 ocp_data; | |
2369 | ||
2370 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); | |
2371 | if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04) | |
2372 | ocp_data |= U2P3_ENABLE; | |
2373 | else | |
2374 | ocp_data &= ~U2P3_ENABLE; | |
2375 | ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); | |
2376 | } | |
2377 | ||
2378 | static void r8153_power_cut_en(struct r8152 *tp, bool enable) | |
2379 | { | |
2380 | u32 ocp_data; | |
2381 | ||
2382 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
2383 | if (enable) | |
2384 | ocp_data |= PWR_EN | PHASE2_EN; | |
2385 | else | |
2386 | ocp_data &= ~(PWR_EN | PHASE2_EN); | |
2387 | ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
2388 | ||
2389 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
2390 | ocp_data &= ~PCUT_STATUS; | |
2391 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
2392 | } | |
2393 | ||
7daed8dc | 2394 | static bool rtl_can_wakeup(struct r8152 *tp) |
2395 | { | |
2396 | struct usb_device *udev = tp->udev; | |
2397 | ||
2398 | return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); | |
2399 | } | |
2400 | ||
9a4be1bd | 2401 | static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) |
2402 | { | |
2403 | if (enable) { | |
2404 | u32 ocp_data; | |
2405 | ||
b214396f | 2406 | r8153_u1u2en(tp, false); |
2407 | r8153_u2p3en(tp, false); | |
2408 | ||
9a4be1bd | 2409 | __rtl_set_wol(tp, WAKE_ANY); |
2410 | ||
2411 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2412 | ||
2413 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2414 | ocp_data |= LINK_OFF_WAKE_EN; | |
2415 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2416 | ||
2417 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2418 | } else { | |
2419 | __rtl_set_wol(tp, tp->saved_wolopts); | |
b214396f | 2420 | r8153_u2p3en(tp, true); |
2421 | r8153_u1u2en(tp, true); | |
9a4be1bd | 2422 | } |
2423 | } | |
2424 | ||
aa66a5f1 | 2425 | static void rtl_phy_reset(struct r8152 *tp) |
2426 | { | |
2427 | u16 data; | |
2428 | int i; | |
2429 | ||
aa66a5f1 | 2430 | data = r8152_mdio_read(tp, MII_BMCR); |
2431 | ||
2432 | /* don't reset again before the previous one complete */ | |
2433 | if (data & BMCR_RESET) | |
2434 | return; | |
2435 | ||
2436 | data |= BMCR_RESET; | |
2437 | r8152_mdio_write(tp, MII_BMCR, data); | |
2438 | ||
2439 | for (i = 0; i < 50; i++) { | |
2440 | msleep(20); | |
2441 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
2442 | break; | |
2443 | } | |
2444 | } | |
2445 | ||
4349968a | 2446 | static void r8153_teredo_off(struct r8152 *tp) |
2447 | { | |
2448 | u32 ocp_data; | |
2449 | ||
2450 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
2451 | ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); | |
2452 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2453 | ||
2454 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); | |
2455 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); | |
2456 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); | |
2457 | } | |
2458 | ||
cda9fb01 | 2459 | static void r8152_aldps_en(struct r8152 *tp, bool enable) |
4349968a | 2460 | { |
cda9fb01 | 2461 | if (enable) { |
2462 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | | |
2463 | LINKENA | DIS_SDSAVE); | |
2464 | } else { | |
2465 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | | |
2466 | DIS_SDSAVE); | |
2467 | msleep(20); | |
2468 | } | |
4349968a | 2469 | } |
2470 | ||
d70b1137 | 2471 | static void rtl8152_disable(struct r8152 *tp) |
2472 | { | |
cda9fb01 | 2473 | r8152_aldps_en(tp, false); |
d70b1137 | 2474 | rtl_disable(tp); |
cda9fb01 | 2475 | r8152_aldps_en(tp, true); |
d70b1137 | 2476 | } |
2477 | ||
4349968a | 2478 | static void r8152b_hw_phy_cfg(struct r8152 *tp) |
2479 | { | |
f0cbe0ac | 2480 | u16 data; |
2481 | ||
2482 | data = r8152_mdio_read(tp, MII_BMCR); | |
2483 | if (data & BMCR_PDOWN) { | |
2484 | data &= ~BMCR_PDOWN; | |
2485 | r8152_mdio_write(tp, MII_BMCR, data); | |
2486 | } | |
2487 | ||
aa66a5f1 | 2488 | set_bit(PHY_RESET, &tp->flags); |
4349968a | 2489 | } |
2490 | ||
ac718b69 | 2491 | static void r8152b_exit_oob(struct r8152 *tp) |
2492 | { | |
db8515ef | 2493 | u32 ocp_data; |
2494 | int i; | |
ac718b69 | 2495 | |
2496 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2497 | ocp_data &= ~RCR_ACPT_ALL; | |
2498 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2499 | ||
00a5e360 | 2500 | rxdy_gated_en(tp, true); |
da9bd117 | 2501 | r8153_teredo_off(tp); |
7e9da481 | 2502 | r8152b_hw_phy_cfg(tp); |
ac718b69 | 2503 | |
2504 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2505 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); | |
2506 | ||
2507 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2508 | ocp_data &= ~NOW_IS_OOB; | |
2509 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2510 | ||
2511 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2512 | ocp_data &= ~MCU_BORW_EN; | |
2513 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2514 | ||
2515 | for (i = 0; i < 1000; i++) { | |
2516 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2517 | if (ocp_data & LINK_LIST_READY) | |
2518 | break; | |
8ddfa077 | 2519 | usleep_range(1000, 2000); |
ac718b69 | 2520 | } |
2521 | ||
2522 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2523 | ocp_data |= RE_INIT_LL; | |
2524 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2525 | ||
2526 | for (i = 0; i < 1000; i++) { | |
2527 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2528 | if (ocp_data & LINK_LIST_READY) | |
2529 | break; | |
8ddfa077 | 2530 | usleep_range(1000, 2000); |
ac718b69 | 2531 | } |
2532 | ||
2533 | rtl8152_nic_reset(tp); | |
2534 | ||
2535 | /* rx share fifo credit full threshold */ | |
2536 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2537 | ||
a3cc465d | 2538 | if (tp->udev->speed == USB_SPEED_FULL || |
2539 | tp->udev->speed == USB_SPEED_LOW) { | |
ac718b69 | 2540 | /* rx share fifo credit near full threshold */ |
2541 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2542 | RXFIFO_THR2_FULL); | |
2543 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2544 | RXFIFO_THR3_FULL); | |
2545 | } else { | |
2546 | /* rx share fifo credit near full threshold */ | |
2547 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2548 | RXFIFO_THR2_HIGH); | |
2549 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2550 | RXFIFO_THR3_HIGH); | |
2551 | } | |
2552 | ||
2553 | /* TX share fifo free credit full threshold */ | |
2554 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); | |
2555 | ||
2556 | ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); | |
8e1f51bd | 2557 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); |
ac718b69 | 2558 | ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, |
2559 | TEST_MODE_DISABLE | TX_SIZE_ADJUST1); | |
2560 | ||
c5554298 | 2561 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
ac718b69 | 2562 | |
2563 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2564 | ||
2565 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2566 | ocp_data |= TCR0_AUTO_FIFO; | |
2567 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2568 | } | |
2569 | ||
2570 | static void r8152b_enter_oob(struct r8152 *tp) | |
2571 | { | |
45f4a19f | 2572 | u32 ocp_data; |
2573 | int i; | |
ac718b69 | 2574 | |
2575 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2576 | ocp_data &= ~NOW_IS_OOB; | |
2577 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2578 | ||
2579 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); | |
2580 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); | |
2581 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); | |
2582 | ||
d70b1137 | 2583 | rtl_disable(tp); |
ac718b69 | 2584 | |
2585 | for (i = 0; i < 1000; i++) { | |
2586 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2587 | if (ocp_data & LINK_LIST_READY) | |
2588 | break; | |
8ddfa077 | 2589 | usleep_range(1000, 2000); |
ac718b69 | 2590 | } |
2591 | ||
2592 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2593 | ocp_data |= RE_INIT_LL; | |
2594 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2595 | ||
2596 | for (i = 0; i < 1000; i++) { | |
2597 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2598 | if (ocp_data & LINK_LIST_READY) | |
2599 | break; | |
8ddfa077 | 2600 | usleep_range(1000, 2000); |
ac718b69 | 2601 | } |
2602 | ||
2603 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2604 | ||
c5554298 | 2605 | rtl_rx_vlan_en(tp, true); |
ac718b69 | 2606 | |
2607 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2608 | ocp_data |= ALDPS_PROXY_MODE; | |
2609 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2610 | ||
2611 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2612 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2613 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2614 | ||
00a5e360 | 2615 | rxdy_gated_en(tp, false); |
ac718b69 | 2616 | |
2617 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2618 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2619 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2620 | } | |
2621 | ||
43779f8d | 2622 | static void r8153_hw_phy_cfg(struct r8152 *tp) |
2623 | { | |
2624 | u32 ocp_data; | |
2625 | u16 data; | |
2626 | ||
fb02eb4a | 2627 | if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || |
2628 | tp->version == RTL_VER_05) | |
2629 | ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); | |
2630 | ||
f0cbe0ac | 2631 | data = r8152_mdio_read(tp, MII_BMCR); |
2632 | if (data & BMCR_PDOWN) { | |
2633 | data &= ~BMCR_PDOWN; | |
2634 | r8152_mdio_write(tp, MII_BMCR, data); | |
2635 | } | |
43779f8d | 2636 | |
2637 | if (tp->version == RTL_VER_03) { | |
2638 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
2639 | data &= ~CTAP_SHORT_EN; | |
2640 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
2641 | } | |
2642 | ||
2643 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2644 | data |= EEE_CLKDIV_EN; | |
2645 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2646 | ||
2647 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
2648 | data |= EN_10M_BGOFF; | |
2649 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
2650 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2651 | data |= EN_10M_PLLOFF; | |
2652 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
b4d99def | 2653 | sram_write(tp, SRAM_IMPEDANCE, 0x0b13); |
43779f8d | 2654 | |
2655 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
2656 | ocp_data |= PFM_PWM_SWITCH; | |
2657 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
2658 | ||
b4d99def | 2659 | /* Enable LPF corner auto tune */ |
2660 | sram_write(tp, SRAM_LPF_CFG, 0xf70f); | |
43779f8d | 2661 | |
b4d99def | 2662 | /* Adjust 10M Amplitude */ |
2663 | sram_write(tp, SRAM_10M_AMP1, 0x00af); | |
2664 | sram_write(tp, SRAM_10M_AMP2, 0x0208); | |
aa66a5f1 | 2665 | |
2666 | set_bit(PHY_RESET, &tp->flags); | |
43779f8d | 2667 | } |
2668 | ||
43779f8d | 2669 | static void r8153_first_init(struct r8152 *tp) |
2670 | { | |
2671 | u32 ocp_data; | |
2672 | int i; | |
2673 | ||
00a5e360 | 2674 | rxdy_gated_en(tp, true); |
43779f8d | 2675 | r8153_teredo_off(tp); |
2676 | ||
2677 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2678 | ocp_data &= ~RCR_ACPT_ALL; | |
2679 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2680 | ||
2681 | r8153_hw_phy_cfg(tp); | |
2682 | ||
2683 | rtl8152_nic_reset(tp); | |
2684 | ||
2685 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2686 | ocp_data &= ~NOW_IS_OOB; | |
2687 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2688 | ||
2689 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2690 | ocp_data &= ~MCU_BORW_EN; | |
2691 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2692 | ||
2693 | for (i = 0; i < 1000; i++) { | |
2694 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2695 | if (ocp_data & LINK_LIST_READY) | |
2696 | break; | |
8ddfa077 | 2697 | usleep_range(1000, 2000); |
43779f8d | 2698 | } |
2699 | ||
2700 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2701 | ocp_data |= RE_INIT_LL; | |
2702 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2703 | ||
2704 | for (i = 0; i < 1000; i++) { | |
2705 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2706 | if (ocp_data & LINK_LIST_READY) | |
2707 | break; | |
8ddfa077 | 2708 | usleep_range(1000, 2000); |
43779f8d | 2709 | } |
2710 | ||
c5554298 | 2711 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
43779f8d | 2712 | |
69b4b7a4 | 2713 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); |
2714 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); | |
43779f8d | 2715 | |
2716 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2717 | ocp_data |= TCR0_AUTO_FIFO; | |
2718 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2719 | ||
2720 | rtl8152_nic_reset(tp); | |
2721 | ||
2722 | /* rx share fifo credit full threshold */ | |
2723 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2724 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); | |
2725 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); | |
2726 | /* TX share fifo free credit full threshold */ | |
2727 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); | |
2728 | ||
9629e3c0 | 2729 | /* rx aggregation */ |
43779f8d | 2730 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
e90fba8d | 2731 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); |
43779f8d | 2732 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
2733 | } | |
2734 | ||
2735 | static void r8153_enter_oob(struct r8152 *tp) | |
2736 | { | |
2737 | u32 ocp_data; | |
2738 | int i; | |
2739 | ||
2740 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2741 | ocp_data &= ~NOW_IS_OOB; | |
2742 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2743 | ||
d70b1137 | 2744 | rtl_disable(tp); |
43779f8d | 2745 | |
2746 | for (i = 0; i < 1000; i++) { | |
2747 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2748 | if (ocp_data & LINK_LIST_READY) | |
2749 | break; | |
8ddfa077 | 2750 | usleep_range(1000, 2000); |
43779f8d | 2751 | } |
2752 | ||
2753 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2754 | ocp_data |= RE_INIT_LL; | |
2755 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2756 | ||
2757 | for (i = 0; i < 1000; i++) { | |
2758 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2759 | if (ocp_data & LINK_LIST_READY) | |
2760 | break; | |
8ddfa077 | 2761 | usleep_range(1000, 2000); |
43779f8d | 2762 | } |
2763 | ||
69b4b7a4 | 2764 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); |
43779f8d | 2765 | |
43779f8d | 2766 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); |
2767 | ocp_data &= ~TEREDO_WAKE_MASK; | |
2768 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2769 | ||
c5554298 | 2770 | rtl_rx_vlan_en(tp, true); |
43779f8d | 2771 | |
2772 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2773 | ocp_data |= ALDPS_PROXY_MODE; | |
2774 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2775 | ||
2776 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2777 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2778 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2779 | ||
00a5e360 | 2780 | rxdy_gated_en(tp, false); |
43779f8d | 2781 | |
2782 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2783 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2784 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2785 | } | |
2786 | ||
cda9fb01 | 2787 | static void r8153_aldps_en(struct r8152 *tp, bool enable) |
43779f8d | 2788 | { |
2789 | u16 data; | |
2790 | ||
2791 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
cda9fb01 | 2792 | if (enable) { |
2793 | data |= EN_ALDPS; | |
2794 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2795 | } else { | |
2796 | data &= ~EN_ALDPS; | |
2797 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2798 | msleep(20); | |
2799 | } | |
43779f8d | 2800 | } |
2801 | ||
d70b1137 | 2802 | static void rtl8153_disable(struct r8152 *tp) |
2803 | { | |
cda9fb01 | 2804 | r8153_aldps_en(tp, false); |
d70b1137 | 2805 | rtl_disable(tp); |
cda9fb01 | 2806 | r8153_aldps_en(tp, true); |
b214396f | 2807 | usb_enable_lpm(tp->udev); |
d70b1137 | 2808 | } |
2809 | ||
ac718b69 | 2810 | static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) |
2811 | { | |
43779f8d | 2812 | u16 bmcr, anar, gbcr; |
ac718b69 | 2813 | int ret = 0; |
2814 | ||
2815 | cancel_delayed_work_sync(&tp->schedule); | |
2816 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
2817 | anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | | |
2818 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
43779f8d | 2819 | if (tp->mii.supports_gmii) { |
2820 | gbcr = r8152_mdio_read(tp, MII_CTRL1000); | |
2821 | gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); | |
2822 | } else { | |
2823 | gbcr = 0; | |
2824 | } | |
ac718b69 | 2825 | |
2826 | if (autoneg == AUTONEG_DISABLE) { | |
2827 | if (speed == SPEED_10) { | |
2828 | bmcr = 0; | |
2829 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2830 | } else if (speed == SPEED_100) { | |
2831 | bmcr = BMCR_SPEED100; | |
2832 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
43779f8d | 2833 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2834 | bmcr = BMCR_SPEED1000; | |
2835 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
ac718b69 | 2836 | } else { |
2837 | ret = -EINVAL; | |
2838 | goto out; | |
2839 | } | |
2840 | ||
2841 | if (duplex == DUPLEX_FULL) | |
2842 | bmcr |= BMCR_FULLDPLX; | |
2843 | } else { | |
2844 | if (speed == SPEED_10) { | |
2845 | if (duplex == DUPLEX_FULL) | |
2846 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2847 | else | |
2848 | anar |= ADVERTISE_10HALF; | |
2849 | } else if (speed == SPEED_100) { | |
2850 | if (duplex == DUPLEX_FULL) { | |
2851 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2852 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2853 | } else { | |
2854 | anar |= ADVERTISE_10HALF; | |
2855 | anar |= ADVERTISE_100HALF; | |
2856 | } | |
43779f8d | 2857 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2858 | if (duplex == DUPLEX_FULL) { | |
2859 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2860 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2861 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
2862 | } else { | |
2863 | anar |= ADVERTISE_10HALF; | |
2864 | anar |= ADVERTISE_100HALF; | |
2865 | gbcr |= ADVERTISE_1000HALF; | |
2866 | } | |
ac718b69 | 2867 | } else { |
2868 | ret = -EINVAL; | |
2869 | goto out; | |
2870 | } | |
2871 | ||
2872 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; | |
2873 | } | |
2874 | ||
aa66a5f1 | 2875 | if (test_bit(PHY_RESET, &tp->flags)) |
2876 | bmcr |= BMCR_RESET; | |
2877 | ||
43779f8d | 2878 | if (tp->mii.supports_gmii) |
2879 | r8152_mdio_write(tp, MII_CTRL1000, gbcr); | |
2880 | ||
ac718b69 | 2881 | r8152_mdio_write(tp, MII_ADVERTISE, anar); |
2882 | r8152_mdio_write(tp, MII_BMCR, bmcr); | |
2883 | ||
216a8349 | 2884 | if (test_and_clear_bit(PHY_RESET, &tp->flags)) { |
aa66a5f1 | 2885 | int i; |
2886 | ||
aa66a5f1 | 2887 | for (i = 0; i < 50; i++) { |
2888 | msleep(20); | |
2889 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
2890 | break; | |
2891 | } | |
2892 | } | |
2893 | ||
ac718b69 | 2894 | out: |
ac718b69 | 2895 | return ret; |
2896 | } | |
2897 | ||
d70b1137 | 2898 | static void rtl8152_up(struct r8152 *tp) |
2899 | { | |
2900 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
2901 | return; | |
2902 | ||
cda9fb01 | 2903 | r8152_aldps_en(tp, false); |
d70b1137 | 2904 | r8152b_exit_oob(tp); |
cda9fb01 | 2905 | r8152_aldps_en(tp, true); |
d70b1137 | 2906 | } |
2907 | ||
ac718b69 | 2908 | static void rtl8152_down(struct r8152 *tp) |
2909 | { | |
6871438c | 2910 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2911 | rtl_drop_queued_tx(tp); | |
2912 | return; | |
2913 | } | |
2914 | ||
00a5e360 | 2915 | r8152_power_cut_en(tp, false); |
cda9fb01 | 2916 | r8152_aldps_en(tp, false); |
ac718b69 | 2917 | r8152b_enter_oob(tp); |
cda9fb01 | 2918 | r8152_aldps_en(tp, true); |
ac718b69 | 2919 | } |
2920 | ||
d70b1137 | 2921 | static void rtl8153_up(struct r8152 *tp) |
2922 | { | |
2923 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
2924 | return; | |
2925 | ||
b214396f | 2926 | r8153_u1u2en(tp, false); |
cda9fb01 | 2927 | r8153_aldps_en(tp, false); |
d70b1137 | 2928 | r8153_first_init(tp); |
cda9fb01 | 2929 | r8153_aldps_en(tp, true); |
b214396f | 2930 | r8153_u2p3en(tp, true); |
2931 | r8153_u1u2en(tp, true); | |
2932 | usb_enable_lpm(tp->udev); | |
d70b1137 | 2933 | } |
2934 | ||
43779f8d | 2935 | static void rtl8153_down(struct r8152 *tp) |
2936 | { | |
6871438c | 2937 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2938 | rtl_drop_queued_tx(tp); | |
2939 | return; | |
2940 | } | |
2941 | ||
b9702723 | 2942 | r8153_u1u2en(tp, false); |
b214396f | 2943 | r8153_u2p3en(tp, false); |
b9702723 | 2944 | r8153_power_cut_en(tp, false); |
cda9fb01 | 2945 | r8153_aldps_en(tp, false); |
43779f8d | 2946 | r8153_enter_oob(tp); |
cda9fb01 | 2947 | r8153_aldps_en(tp, true); |
43779f8d | 2948 | } |
2949 | ||
2dd49e0f | 2950 | static bool rtl8152_in_nway(struct r8152 *tp) |
2951 | { | |
2952 | u16 nway_state; | |
2953 | ||
2954 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); | |
2955 | tp->ocp_base = 0x2000; | |
2956 | ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ | |
2957 | nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); | |
2958 | ||
2959 | /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ | |
2960 | if (nway_state & 0xc000) | |
2961 | return false; | |
2962 | else | |
2963 | return true; | |
2964 | } | |
2965 | ||
2966 | static bool rtl8153_in_nway(struct r8152 *tp) | |
2967 | { | |
2968 | u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; | |
2969 | ||
2970 | if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) | |
2971 | return false; | |
2972 | else | |
2973 | return true; | |
2974 | } | |
2975 | ||
ac718b69 | 2976 | static void set_carrier(struct r8152 *tp) |
2977 | { | |
2978 | struct net_device *netdev = tp->netdev; | |
2979 | u8 speed; | |
2980 | ||
2981 | speed = rtl8152_get_speed(tp); | |
2982 | ||
2983 | if (speed & LINK_STATUS) { | |
51d979fa | 2984 | if (!netif_carrier_ok(netdev)) { |
c81229c9 | 2985 | tp->rtl_ops.enable(tp); |
ac718b69 | 2986 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
41cec84c | 2987 | napi_disable(&tp->napi); |
ac718b69 | 2988 | netif_carrier_on(netdev); |
aa2e0926 | 2989 | rtl_start_rx(tp); |
41cec84c | 2990 | napi_enable(&tp->napi); |
ac718b69 | 2991 | } |
2992 | } else { | |
51d979fa | 2993 | if (netif_carrier_ok(netdev)) { |
ac718b69 | 2994 | netif_carrier_off(netdev); |
d823ab68 | 2995 | napi_disable(&tp->napi); |
c81229c9 | 2996 | tp->rtl_ops.disable(tp); |
d823ab68 | 2997 | napi_enable(&tp->napi); |
ac718b69 | 2998 | } |
2999 | } | |
ac718b69 | 3000 | } |
3001 | ||
3002 | static void rtl_work_func_t(struct work_struct *work) | |
3003 | { | |
3004 | struct r8152 *tp = container_of(work, struct r8152, schedule.work); | |
3005 | ||
a1f83fee | 3006 | /* If the device is unplugged or !netif_running(), the workqueue |
3007 | * doesn't need to wake the device, and could return directly. | |
3008 | */ | |
3009 | if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) | |
3010 | return; | |
3011 | ||
9a4be1bd | 3012 | if (usb_autopm_get_interface(tp->intf) < 0) |
3013 | return; | |
3014 | ||
ac718b69 | 3015 | if (!test_bit(WORK_ENABLE, &tp->flags)) |
3016 | goto out1; | |
3017 | ||
b5403273 | 3018 | if (!mutex_trylock(&tp->control)) { |
3019 | schedule_delayed_work(&tp->schedule, 0); | |
3020 | goto out1; | |
3021 | } | |
3022 | ||
216a8349 | 3023 | if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags)) |
40a82917 | 3024 | set_carrier(tp); |
ac718b69 | 3025 | |
216a8349 | 3026 | if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) |
ac718b69 | 3027 | _rtl8152_set_rx_mode(tp->netdev); |
3028 | ||
d823ab68 | 3029 | /* don't schedule napi before linking */ |
216a8349 | 3030 | if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) && |
3031 | netif_carrier_ok(tp->netdev)) | |
d823ab68 | 3032 | napi_schedule(&tp->napi); |
aa66a5f1 | 3033 | |
216a8349 | 3034 | if (test_and_clear_bit(PHY_RESET, &tp->flags)) |
aa66a5f1 | 3035 | rtl_phy_reset(tp); |
3036 | ||
b5403273 | 3037 | mutex_unlock(&tp->control); |
3038 | ||
ac718b69 | 3039 | out1: |
9a4be1bd | 3040 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 3041 | } |
3042 | ||
5ee3c60c | 3043 | #ifdef CONFIG_PM_SLEEP |
3044 | static int rtl_notifier(struct notifier_block *nb, unsigned long action, | |
3045 | void *data) | |
3046 | { | |
3047 | struct r8152 *tp = container_of(nb, struct r8152, pm_notifier); | |
3048 | ||
3049 | switch (action) { | |
3050 | case PM_HIBERNATION_PREPARE: | |
3051 | case PM_SUSPEND_PREPARE: | |
3052 | usb_autopm_get_interface(tp->intf); | |
3053 | break; | |
3054 | ||
3055 | case PM_POST_HIBERNATION: | |
3056 | case PM_POST_SUSPEND: | |
3057 | usb_autopm_put_interface(tp->intf); | |
3058 | break; | |
3059 | ||
3060 | case PM_POST_RESTORE: | |
3061 | case PM_RESTORE_PREPARE: | |
3062 | default: | |
3063 | break; | |
3064 | } | |
3065 | ||
3066 | return NOTIFY_DONE; | |
3067 | } | |
3068 | #endif | |
3069 | ||
ac718b69 | 3070 | static int rtl8152_open(struct net_device *netdev) |
3071 | { | |
3072 | struct r8152 *tp = netdev_priv(netdev); | |
3073 | int res = 0; | |
3074 | ||
7e9da481 | 3075 | res = alloc_all_mem(tp); |
3076 | if (res) | |
3077 | goto out; | |
3078 | ||
51d979fa | 3079 | netif_carrier_off(netdev); |
f4c7476b | 3080 | |
9a4be1bd | 3081 | res = usb_autopm_get_interface(tp->intf); |
3082 | if (res < 0) { | |
3083 | free_all_mem(tp); | |
3084 | goto out; | |
3085 | } | |
3086 | ||
b5403273 | 3087 | mutex_lock(&tp->control); |
3088 | ||
7e9da481 | 3089 | tp->rtl_ops.up(tp); |
3090 | ||
3d55f44f | 3091 | rtl8152_set_speed(tp, AUTONEG_ENABLE, |
3092 | tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, | |
3093 | DUPLEX_FULL); | |
3d55f44f | 3094 | netif_carrier_off(netdev); |
3095 | netif_start_queue(netdev); | |
3096 | set_bit(WORK_ENABLE, &tp->flags); | |
db8515ef | 3097 | |
40a82917 | 3098 | res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
3099 | if (res) { | |
3100 | if (res == -ENODEV) | |
3101 | netif_device_detach(tp->netdev); | |
4a8deae2 HW |
3102 | netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", |
3103 | res); | |
7e9da481 | 3104 | free_all_mem(tp); |
93ffbeab | 3105 | } else { |
d823ab68 | 3106 | napi_enable(&tp->napi); |
ac718b69 | 3107 | } |
3108 | ||
b5403273 | 3109 | mutex_unlock(&tp->control); |
3110 | ||
9a4be1bd | 3111 | usb_autopm_put_interface(tp->intf); |
5ee3c60c | 3112 | #ifdef CONFIG_PM_SLEEP |
3113 | tp->pm_notifier.notifier_call = rtl_notifier; | |
3114 | register_pm_notifier(&tp->pm_notifier); | |
3115 | #endif | |
ac718b69 | 3116 | |
7e9da481 | 3117 | out: |
ac718b69 | 3118 | return res; |
3119 | } | |
3120 | ||
3121 | static int rtl8152_close(struct net_device *netdev) | |
3122 | { | |
3123 | struct r8152 *tp = netdev_priv(netdev); | |
3124 | int res = 0; | |
3125 | ||
5ee3c60c | 3126 | #ifdef CONFIG_PM_SLEEP |
3127 | unregister_pm_notifier(&tp->pm_notifier); | |
3128 | #endif | |
d823ab68 | 3129 | napi_disable(&tp->napi); |
ac718b69 | 3130 | clear_bit(WORK_ENABLE, &tp->flags); |
3d55f44f | 3131 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 3132 | cancel_delayed_work_sync(&tp->schedule); |
3133 | netif_stop_queue(netdev); | |
9a4be1bd | 3134 | |
3135 | res = usb_autopm_get_interface(tp->intf); | |
53543db5 | 3136 | if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { |
9a4be1bd | 3137 | rtl_drop_queued_tx(tp); |
d823ab68 | 3138 | rtl_stop_rx(tp); |
9a4be1bd | 3139 | } else { |
b5403273 | 3140 | mutex_lock(&tp->control); |
3141 | ||
9a4be1bd | 3142 | tp->rtl_ops.down(tp); |
b5403273 | 3143 | |
3144 | mutex_unlock(&tp->control); | |
3145 | ||
9a4be1bd | 3146 | usb_autopm_put_interface(tp->intf); |
3147 | } | |
ac718b69 | 3148 | |
7e9da481 | 3149 | free_all_mem(tp); |
3150 | ||
ac718b69 | 3151 | return res; |
3152 | } | |
3153 | ||
d24f6134 | 3154 | static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) |
3155 | { | |
3156 | ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); | |
3157 | ocp_reg_write(tp, OCP_EEE_DATA, reg); | |
3158 | ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); | |
3159 | } | |
3160 | ||
3161 | static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) | |
3162 | { | |
3163 | u16 data; | |
3164 | ||
3165 | r8152_mmd_indirect(tp, dev, reg); | |
3166 | data = ocp_reg_read(tp, OCP_EEE_DATA); | |
3167 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
3168 | ||
3169 | return data; | |
3170 | } | |
3171 | ||
3172 | static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) | |
ac718b69 | 3173 | { |
d24f6134 | 3174 | r8152_mmd_indirect(tp, dev, reg); |
3175 | ocp_reg_write(tp, OCP_EEE_DATA, data); | |
3176 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
3177 | } | |
3178 | ||
3179 | static void r8152_eee_en(struct r8152 *tp, bool enable) | |
3180 | { | |
3181 | u16 config1, config2, config3; | |
45f4a19f | 3182 | u32 ocp_data; |
ac718b69 | 3183 | |
3184 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
d24f6134 | 3185 | config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; |
3186 | config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); | |
3187 | config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; | |
3188 | ||
3189 | if (enable) { | |
3190 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
3191 | config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; | |
3192 | config1 |= sd_rise_time(1); | |
3193 | config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; | |
3194 | config3 |= fast_snr(42); | |
3195 | } else { | |
3196 | ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); | |
3197 | config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | | |
3198 | RX_QUIET_EN); | |
3199 | config1 |= sd_rise_time(7); | |
3200 | config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); | |
3201 | config3 |= fast_snr(511); | |
3202 | } | |
3203 | ||
ac718b69 | 3204 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); |
d24f6134 | 3205 | ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); |
3206 | ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); | |
3207 | ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); | |
ac718b69 | 3208 | } |
3209 | ||
d24f6134 | 3210 | static void r8152b_enable_eee(struct r8152 *tp) |
3211 | { | |
3212 | r8152_eee_en(tp, true); | |
3213 | r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); | |
3214 | } | |
3215 | ||
3216 | static void r8153_eee_en(struct r8152 *tp, bool enable) | |
43779f8d | 3217 | { |
3218 | u32 ocp_data; | |
d24f6134 | 3219 | u16 config; |
43779f8d | 3220 | |
3221 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
d24f6134 | 3222 | config = ocp_reg_read(tp, OCP_EEE_CFG); |
3223 | ||
3224 | if (enable) { | |
3225 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
3226 | config |= EEE10_EN; | |
3227 | } else { | |
3228 | ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); | |
3229 | config &= ~EEE10_EN; | |
3230 | } | |
3231 | ||
43779f8d | 3232 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); |
d24f6134 | 3233 | ocp_reg_write(tp, OCP_EEE_CFG, config); |
3234 | } | |
3235 | ||
3236 | static void r8153_enable_eee(struct r8152 *tp) | |
3237 | { | |
3238 | r8153_eee_en(tp, true); | |
3239 | ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); | |
43779f8d | 3240 | } |
3241 | ||
ac718b69 | 3242 | static void r8152b_enable_fc(struct r8152 *tp) |
3243 | { | |
3244 | u16 anar; | |
3245 | ||
3246 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
3247 | anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
3248 | r8152_mdio_write(tp, MII_ADVERTISE, anar); | |
3249 | } | |
3250 | ||
4f1d4d54 | 3251 | static void rtl_tally_reset(struct r8152 *tp) |
3252 | { | |
3253 | u32 ocp_data; | |
3254 | ||
3255 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); | |
3256 | ocp_data |= TALLY_RESET; | |
3257 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); | |
3258 | } | |
3259 | ||
ac718b69 | 3260 | static void r8152b_init(struct r8152 *tp) |
3261 | { | |
ebc2ec48 | 3262 | u32 ocp_data; |
ac718b69 | 3263 | |
6871438c | 3264 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3265 | return; | |
3266 | ||
cda9fb01 | 3267 | r8152_aldps_en(tp, false); |
d70b1137 | 3268 | |
ac718b69 | 3269 | if (tp->version == RTL_VER_01) { |
3270 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); | |
3271 | ocp_data &= ~LED_MODE_MASK; | |
3272 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
3273 | } | |
3274 | ||
00a5e360 | 3275 | r8152_power_cut_en(tp, false); |
ac718b69 | 3276 | |
ac718b69 | 3277 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); |
3278 | ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; | |
3279 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
3280 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); | |
3281 | ocp_data &= ~MCU_CLK_RATIO_MASK; | |
3282 | ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; | |
3283 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); | |
3284 | ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | | |
3285 | SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; | |
3286 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); | |
3287 | ||
3288 | r8152b_enable_eee(tp); | |
cda9fb01 | 3289 | r8152_aldps_en(tp, true); |
ac718b69 | 3290 | r8152b_enable_fc(tp); |
4f1d4d54 | 3291 | rtl_tally_reset(tp); |
ac718b69 | 3292 | |
ebc2ec48 | 3293 | /* enable rx aggregation */ |
ac718b69 | 3294 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
e90fba8d | 3295 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); |
ac718b69 | 3296 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
3297 | } | |
3298 | ||
43779f8d | 3299 | static void r8153_init(struct r8152 *tp) |
3300 | { | |
3301 | u32 ocp_data; | |
3302 | int i; | |
3303 | ||
6871438c | 3304 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3305 | return; | |
3306 | ||
cda9fb01 | 3307 | r8153_aldps_en(tp, false); |
b9702723 | 3308 | r8153_u1u2en(tp, false); |
43779f8d | 3309 | |
3310 | for (i = 0; i < 500; i++) { | |
3311 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
3312 | AUTOLOAD_DONE) | |
3313 | break; | |
3314 | msleep(20); | |
3315 | } | |
3316 | ||
3317 | for (i = 0; i < 500; i++) { | |
3318 | ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; | |
3319 | if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) | |
3320 | break; | |
3321 | msleep(20); | |
3322 | } | |
3323 | ||
b214396f | 3324 | usb_disable_lpm(tp->udev); |
b9702723 | 3325 | r8153_u2p3en(tp, false); |
43779f8d | 3326 | |
65bab84c | 3327 | if (tp->version == RTL_VER_04) { |
3328 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); | |
3329 | ocp_data &= ~pwd_dn_scale_mask; | |
3330 | ocp_data |= pwd_dn_scale(96); | |
3331 | ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); | |
3332 | ||
3333 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); | |
3334 | ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; | |
3335 | ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); | |
3336 | } else if (tp->version == RTL_VER_05) { | |
3337 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); | |
3338 | ocp_data &= ~ECM_ALDPS; | |
3339 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); | |
3340 | ||
fb02eb4a | 3341 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); |
3342 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) | |
3343 | ocp_data &= ~DYNAMIC_BURST; | |
3344 | else | |
3345 | ocp_data |= DYNAMIC_BURST; | |
3346 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); | |
3347 | } else if (tp->version == RTL_VER_06) { | |
65bab84c | 3348 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); |
3349 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) | |
3350 | ocp_data &= ~DYNAMIC_BURST; | |
3351 | else | |
3352 | ocp_data |= DYNAMIC_BURST; | |
3353 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); | |
3354 | } | |
3355 | ||
3356 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); | |
3357 | ocp_data |= EP4_FULL_FC; | |
3358 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); | |
3359 | ||
43779f8d | 3360 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); |
3361 | ocp_data &= ~TIMER11_EN; | |
3362 | ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); | |
3363 | ||
43779f8d | 3364 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); |
3365 | ocp_data &= ~LED_MODE_MASK; | |
3366 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
3367 | ||
65bab84c | 3368 | ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; |
2b84af94 | 3369 | if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) |
43779f8d | 3370 | ocp_data |= LPM_TIMER_500MS; |
34203e25 | 3371 | else |
3372 | ocp_data |= LPM_TIMER_500US; | |
43779f8d | 3373 | ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); |
3374 | ||
3375 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); | |
3376 | ocp_data &= ~SEN_VAL_MASK; | |
3377 | ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; | |
3378 | ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); | |
3379 | ||
65bab84c | 3380 | ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); |
3381 | ||
b9702723 | 3382 | r8153_power_cut_en(tp, false); |
3383 | r8153_u1u2en(tp, true); | |
43779f8d | 3384 | |
4e384ac1 | 3385 | /* MAC clock speed down */ |
3386 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0); | |
3387 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0); | |
3388 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0); | |
3389 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0); | |
43779f8d | 3390 | |
3391 | r8153_enable_eee(tp); | |
cda9fb01 | 3392 | r8153_aldps_en(tp, true); |
43779f8d | 3393 | r8152b_enable_fc(tp); |
4f1d4d54 | 3394 | rtl_tally_reset(tp); |
b214396f | 3395 | r8153_u2p3en(tp, true); |
43779f8d | 3396 | } |
3397 | ||
e501139a | 3398 | static int rtl8152_pre_reset(struct usb_interface *intf) |
3399 | { | |
3400 | struct r8152 *tp = usb_get_intfdata(intf); | |
3401 | struct net_device *netdev; | |
3402 | ||
3403 | if (!tp) | |
3404 | return 0; | |
3405 | ||
3406 | netdev = tp->netdev; | |
3407 | if (!netif_running(netdev)) | |
3408 | return 0; | |
3409 | ||
3410 | napi_disable(&tp->napi); | |
3411 | clear_bit(WORK_ENABLE, &tp->flags); | |
3412 | usb_kill_urb(tp->intr_urb); | |
3413 | cancel_delayed_work_sync(&tp->schedule); | |
3414 | if (netif_carrier_ok(netdev)) { | |
3415 | netif_stop_queue(netdev); | |
3416 | mutex_lock(&tp->control); | |
3417 | tp->rtl_ops.disable(tp); | |
3418 | mutex_unlock(&tp->control); | |
3419 | } | |
3420 | ||
3421 | return 0; | |
3422 | } | |
3423 | ||
3424 | static int rtl8152_post_reset(struct usb_interface *intf) | |
3425 | { | |
3426 | struct r8152 *tp = usb_get_intfdata(intf); | |
3427 | struct net_device *netdev; | |
3428 | ||
3429 | if (!tp) | |
3430 | return 0; | |
3431 | ||
3432 | netdev = tp->netdev; | |
3433 | if (!netif_running(netdev)) | |
3434 | return 0; | |
3435 | ||
3436 | set_bit(WORK_ENABLE, &tp->flags); | |
3437 | if (netif_carrier_ok(netdev)) { | |
3438 | mutex_lock(&tp->control); | |
3439 | tp->rtl_ops.enable(tp); | |
3440 | rtl8152_set_rx_mode(netdev); | |
3441 | mutex_unlock(&tp->control); | |
3442 | netif_wake_queue(netdev); | |
3443 | } | |
3444 | ||
3445 | napi_enable(&tp->napi); | |
3446 | ||
3447 | return 0; | |
43779f8d | 3448 | } |
3449 | ||
2dd49e0f | 3450 | static bool delay_autosuspend(struct r8152 *tp) |
3451 | { | |
3452 | bool sw_linking = !!netif_carrier_ok(tp->netdev); | |
3453 | bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); | |
3454 | ||
3455 | /* This means a linking change occurs and the driver doesn't detect it, | |
3456 | * yet. If the driver has disabled tx/rx and hw is linking on, the | |
3457 | * device wouldn't wake up by receiving any packet. | |
3458 | */ | |
3459 | if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) | |
3460 | return true; | |
3461 | ||
3462 | /* If the linking down is occurred by nway, the device may miss the | |
3463 | * linking change event. And it wouldn't wake when linking on. | |
3464 | */ | |
3465 | if (!sw_linking && tp->rtl_ops.in_nway(tp)) | |
3466 | return true; | |
3467 | else | |
3468 | return false; | |
3469 | } | |
3470 | ||
ac718b69 | 3471 | static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) |
3472 | { | |
3473 | struct r8152 *tp = usb_get_intfdata(intf); | |
6cc69f2a | 3474 | struct net_device *netdev = tp->netdev; |
3475 | int ret = 0; | |
ac718b69 | 3476 | |
b5403273 | 3477 | mutex_lock(&tp->control); |
3478 | ||
6cc69f2a | 3479 | if (PMSG_IS_AUTO(message)) { |
2dd49e0f | 3480 | if (netif_running(netdev) && delay_autosuspend(tp)) { |
6cc69f2a | 3481 | ret = -EBUSY; |
3482 | goto out1; | |
3483 | } | |
3484 | ||
9a4be1bd | 3485 | set_bit(SELECTIVE_SUSPEND, &tp->flags); |
6cc69f2a | 3486 | } else { |
3487 | netif_device_detach(netdev); | |
3488 | } | |
ac718b69 | 3489 | |
e3bd1a81 | 3490 | if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { |
ac718b69 | 3491 | clear_bit(WORK_ENABLE, &tp->flags); |
40a82917 | 3492 | usb_kill_urb(tp->intr_urb); |
d823ab68 | 3493 | napi_disable(&tp->napi); |
9a4be1bd | 3494 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
445f7f4d | 3495 | rtl_stop_rx(tp); |
9a4be1bd | 3496 | rtl_runtime_suspend_enable(tp, true); |
3497 | } else { | |
6cc69f2a | 3498 | cancel_delayed_work_sync(&tp->schedule); |
9a4be1bd | 3499 | tp->rtl_ops.down(tp); |
9a4be1bd | 3500 | } |
d823ab68 | 3501 | napi_enable(&tp->napi); |
ac718b69 | 3502 | } |
6cc69f2a | 3503 | out1: |
b5403273 | 3504 | mutex_unlock(&tp->control); |
3505 | ||
6cc69f2a | 3506 | return ret; |
ac718b69 | 3507 | } |
3508 | ||
3509 | static int rtl8152_resume(struct usb_interface *intf) | |
3510 | { | |
3511 | struct r8152 *tp = usb_get_intfdata(intf); | |
3512 | ||
b5403273 | 3513 | mutex_lock(&tp->control); |
3514 | ||
9a4be1bd | 3515 | if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
3516 | tp->rtl_ops.init(tp); | |
3517 | netif_device_attach(tp->netdev); | |
3518 | } | |
3519 | ||
90186af4 | 3520 | if (netif_running(tp->netdev) && tp->netdev->flags & IFF_UP) { |
9a4be1bd | 3521 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
3522 | rtl_runtime_suspend_enable(tp, false); | |
3523 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
41cec84c | 3524 | napi_disable(&tp->napi); |
445f7f4d | 3525 | set_bit(WORK_ENABLE, &tp->flags); |
51d979fa | 3526 | if (netif_carrier_ok(tp->netdev)) |
445f7f4d | 3527 | rtl_start_rx(tp); |
41cec84c | 3528 | napi_enable(&tp->napi); |
9a4be1bd | 3529 | } else { |
3530 | tp->rtl_ops.up(tp); | |
3531 | rtl8152_set_speed(tp, AUTONEG_ENABLE, | |
b209af99 | 3532 | tp->mii.supports_gmii ? |
3533 | SPEED_1000 : SPEED_100, | |
3534 | DUPLEX_FULL); | |
445f7f4d | 3535 | netif_carrier_off(tp->netdev); |
3536 | set_bit(WORK_ENABLE, &tp->flags); | |
9a4be1bd | 3537 | } |
40a82917 | 3538 | usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
923e1ee3 | 3539 | } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
90186af4 PW |
3540 | if (tp->netdev->flags & IFF_UP) |
3541 | rtl_runtime_suspend_enable(tp, false); | |
923e1ee3 | 3542 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); |
ac718b69 | 3543 | } |
3544 | ||
b5403273 | 3545 | mutex_unlock(&tp->control); |
3546 | ||
ac718b69 | 3547 | return 0; |
3548 | } | |
3549 | ||
7ec2541a | 3550 | static int rtl8152_reset_resume(struct usb_interface *intf) |
3551 | { | |
3552 | struct r8152 *tp = usb_get_intfdata(intf); | |
3553 | ||
3554 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
3555 | return rtl8152_resume(intf); | |
3556 | } | |
3557 | ||
21ff2e89 | 3558 | static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
3559 | { | |
3560 | struct r8152 *tp = netdev_priv(dev); | |
3561 | ||
9a4be1bd | 3562 | if (usb_autopm_get_interface(tp->intf) < 0) |
3563 | return; | |
3564 | ||
7daed8dc | 3565 | if (!rtl_can_wakeup(tp)) { |
3566 | wol->supported = 0; | |
3567 | wol->wolopts = 0; | |
3568 | } else { | |
3569 | mutex_lock(&tp->control); | |
3570 | wol->supported = WAKE_ANY; | |
3571 | wol->wolopts = __rtl_get_wol(tp); | |
3572 | mutex_unlock(&tp->control); | |
3573 | } | |
b5403273 | 3574 | |
9a4be1bd | 3575 | usb_autopm_put_interface(tp->intf); |
21ff2e89 | 3576 | } |
3577 | ||
3578 | static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
3579 | { | |
3580 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 3581 | int ret; |
3582 | ||
7daed8dc | 3583 | if (!rtl_can_wakeup(tp)) |
3584 | return -EOPNOTSUPP; | |
3585 | ||
9a4be1bd | 3586 | ret = usb_autopm_get_interface(tp->intf); |
3587 | if (ret < 0) | |
3588 | goto out_set_wol; | |
21ff2e89 | 3589 | |
b5403273 | 3590 | mutex_lock(&tp->control); |
3591 | ||
21ff2e89 | 3592 | __rtl_set_wol(tp, wol->wolopts); |
3593 | tp->saved_wolopts = wol->wolopts & WAKE_ANY; | |
3594 | ||
b5403273 | 3595 | mutex_unlock(&tp->control); |
3596 | ||
9a4be1bd | 3597 | usb_autopm_put_interface(tp->intf); |
3598 | ||
3599 | out_set_wol: | |
3600 | return ret; | |
21ff2e89 | 3601 | } |
3602 | ||
a5ec27c1 | 3603 | static u32 rtl8152_get_msglevel(struct net_device *dev) |
3604 | { | |
3605 | struct r8152 *tp = netdev_priv(dev); | |
3606 | ||
3607 | return tp->msg_enable; | |
3608 | } | |
3609 | ||
3610 | static void rtl8152_set_msglevel(struct net_device *dev, u32 value) | |
3611 | { | |
3612 | struct r8152 *tp = netdev_priv(dev); | |
3613 | ||
3614 | tp->msg_enable = value; | |
3615 | } | |
3616 | ||
ac718b69 | 3617 | static void rtl8152_get_drvinfo(struct net_device *netdev, |
3618 | struct ethtool_drvinfo *info) | |
3619 | { | |
3620 | struct r8152 *tp = netdev_priv(netdev); | |
3621 | ||
b0b46c77 | 3622 | strlcpy(info->driver, MODULENAME, sizeof(info->driver)); |
3623 | strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); | |
ac718b69 | 3624 | usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); |
3625 | } | |
3626 | ||
3627 | static | |
3628 | int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) | |
3629 | { | |
3630 | struct r8152 *tp = netdev_priv(netdev); | |
8d4a4d72 | 3631 | int ret; |
ac718b69 | 3632 | |
3633 | if (!tp->mii.mdio_read) | |
3634 | return -EOPNOTSUPP; | |
3635 | ||
8d4a4d72 | 3636 | ret = usb_autopm_get_interface(tp->intf); |
3637 | if (ret < 0) | |
3638 | goto out; | |
3639 | ||
b5403273 | 3640 | mutex_lock(&tp->control); |
3641 | ||
8d4a4d72 | 3642 | ret = mii_ethtool_gset(&tp->mii, cmd); |
3643 | ||
b5403273 | 3644 | mutex_unlock(&tp->control); |
3645 | ||
8d4a4d72 | 3646 | usb_autopm_put_interface(tp->intf); |
3647 | ||
3648 | out: | |
3649 | return ret; | |
ac718b69 | 3650 | } |
3651 | ||
3652 | static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
3653 | { | |
3654 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 3655 | int ret; |
3656 | ||
3657 | ret = usb_autopm_get_interface(tp->intf); | |
3658 | if (ret < 0) | |
3659 | goto out; | |
ac718b69 | 3660 | |
b5403273 | 3661 | mutex_lock(&tp->control); |
3662 | ||
9a4be1bd | 3663 | ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); |
3664 | ||
b5403273 | 3665 | mutex_unlock(&tp->control); |
3666 | ||
9a4be1bd | 3667 | usb_autopm_put_interface(tp->intf); |
3668 | ||
3669 | out: | |
3670 | return ret; | |
ac718b69 | 3671 | } |
3672 | ||
4f1d4d54 | 3673 | static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { |
3674 | "tx_packets", | |
3675 | "rx_packets", | |
3676 | "tx_errors", | |
3677 | "rx_errors", | |
3678 | "rx_missed", | |
3679 | "align_errors", | |
3680 | "tx_single_collisions", | |
3681 | "tx_multi_collisions", | |
3682 | "rx_unicast", | |
3683 | "rx_broadcast", | |
3684 | "rx_multicast", | |
3685 | "tx_aborted", | |
3686 | "tx_underrun", | |
3687 | }; | |
3688 | ||
3689 | static int rtl8152_get_sset_count(struct net_device *dev, int sset) | |
3690 | { | |
3691 | switch (sset) { | |
3692 | case ETH_SS_STATS: | |
3693 | return ARRAY_SIZE(rtl8152_gstrings); | |
3694 | default: | |
3695 | return -EOPNOTSUPP; | |
3696 | } | |
3697 | } | |
3698 | ||
3699 | static void rtl8152_get_ethtool_stats(struct net_device *dev, | |
3700 | struct ethtool_stats *stats, u64 *data) | |
3701 | { | |
3702 | struct r8152 *tp = netdev_priv(dev); | |
3703 | struct tally_counter tally; | |
3704 | ||
0b030244 | 3705 | if (usb_autopm_get_interface(tp->intf) < 0) |
3706 | return; | |
3707 | ||
4f1d4d54 | 3708 | generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); |
3709 | ||
0b030244 | 3710 | usb_autopm_put_interface(tp->intf); |
3711 | ||
4f1d4d54 | 3712 | data[0] = le64_to_cpu(tally.tx_packets); |
3713 | data[1] = le64_to_cpu(tally.rx_packets); | |
3714 | data[2] = le64_to_cpu(tally.tx_errors); | |
3715 | data[3] = le32_to_cpu(tally.rx_errors); | |
3716 | data[4] = le16_to_cpu(tally.rx_missed); | |
3717 | data[5] = le16_to_cpu(tally.align_errors); | |
3718 | data[6] = le32_to_cpu(tally.tx_one_collision); | |
3719 | data[7] = le32_to_cpu(tally.tx_multi_collision); | |
3720 | data[8] = le64_to_cpu(tally.rx_unicast); | |
3721 | data[9] = le64_to_cpu(tally.rx_broadcast); | |
3722 | data[10] = le32_to_cpu(tally.rx_multicast); | |
3723 | data[11] = le16_to_cpu(tally.tx_aborted); | |
f37119c5 | 3724 | data[12] = le16_to_cpu(tally.tx_underrun); |
4f1d4d54 | 3725 | } |
3726 | ||
3727 | static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
3728 | { | |
3729 | switch (stringset) { | |
3730 | case ETH_SS_STATS: | |
3731 | memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); | |
3732 | break; | |
3733 | } | |
3734 | } | |
3735 | ||
df35d283 | 3736 | static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) |
3737 | { | |
3738 | u32 ocp_data, lp, adv, supported = 0; | |
3739 | u16 val; | |
3740 | ||
3741 | val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); | |
3742 | supported = mmd_eee_cap_to_ethtool_sup_t(val); | |
3743 | ||
3744 | val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); | |
3745 | adv = mmd_eee_adv_to_ethtool_adv_t(val); | |
3746 | ||
3747 | val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); | |
3748 | lp = mmd_eee_adv_to_ethtool_adv_t(val); | |
3749 | ||
3750 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
3751 | ocp_data &= EEE_RX_EN | EEE_TX_EN; | |
3752 | ||
3753 | eee->eee_enabled = !!ocp_data; | |
3754 | eee->eee_active = !!(supported & adv & lp); | |
3755 | eee->supported = supported; | |
3756 | eee->advertised = adv; | |
3757 | eee->lp_advertised = lp; | |
3758 | ||
3759 | return 0; | |
3760 | } | |
3761 | ||
3762 | static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
3763 | { | |
3764 | u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); | |
3765 | ||
3766 | r8152_eee_en(tp, eee->eee_enabled); | |
3767 | ||
3768 | if (!eee->eee_enabled) | |
3769 | val = 0; | |
3770 | ||
3771 | r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); | |
3772 | ||
3773 | return 0; | |
3774 | } | |
3775 | ||
3776 | static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
3777 | { | |
3778 | u32 ocp_data, lp, adv, supported = 0; | |
3779 | u16 val; | |
3780 | ||
3781 | val = ocp_reg_read(tp, OCP_EEE_ABLE); | |
3782 | supported = mmd_eee_cap_to_ethtool_sup_t(val); | |
3783 | ||
3784 | val = ocp_reg_read(tp, OCP_EEE_ADV); | |
3785 | adv = mmd_eee_adv_to_ethtool_adv_t(val); | |
3786 | ||
3787 | val = ocp_reg_read(tp, OCP_EEE_LPABLE); | |
3788 | lp = mmd_eee_adv_to_ethtool_adv_t(val); | |
3789 | ||
3790 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
3791 | ocp_data &= EEE_RX_EN | EEE_TX_EN; | |
3792 | ||
3793 | eee->eee_enabled = !!ocp_data; | |
3794 | eee->eee_active = !!(supported & adv & lp); | |
3795 | eee->supported = supported; | |
3796 | eee->advertised = adv; | |
3797 | eee->lp_advertised = lp; | |
3798 | ||
3799 | return 0; | |
3800 | } | |
3801 | ||
3802 | static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
3803 | { | |
3804 | u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); | |
3805 | ||
3806 | r8153_eee_en(tp, eee->eee_enabled); | |
3807 | ||
3808 | if (!eee->eee_enabled) | |
3809 | val = 0; | |
3810 | ||
3811 | ocp_reg_write(tp, OCP_EEE_ADV, val); | |
3812 | ||
3813 | return 0; | |
3814 | } | |
3815 | ||
3816 | static int | |
3817 | rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) | |
3818 | { | |
3819 | struct r8152 *tp = netdev_priv(net); | |
3820 | int ret; | |
3821 | ||
3822 | ret = usb_autopm_get_interface(tp->intf); | |
3823 | if (ret < 0) | |
3824 | goto out; | |
3825 | ||
b5403273 | 3826 | mutex_lock(&tp->control); |
3827 | ||
df35d283 | 3828 | ret = tp->rtl_ops.eee_get(tp, edata); |
3829 | ||
b5403273 | 3830 | mutex_unlock(&tp->control); |
3831 | ||
df35d283 | 3832 | usb_autopm_put_interface(tp->intf); |
3833 | ||
3834 | out: | |
3835 | return ret; | |
3836 | } | |
3837 | ||
3838 | static int | |
3839 | rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) | |
3840 | { | |
3841 | struct r8152 *tp = netdev_priv(net); | |
3842 | int ret; | |
3843 | ||
3844 | ret = usb_autopm_get_interface(tp->intf); | |
3845 | if (ret < 0) | |
3846 | goto out; | |
3847 | ||
b5403273 | 3848 | mutex_lock(&tp->control); |
3849 | ||
df35d283 | 3850 | ret = tp->rtl_ops.eee_set(tp, edata); |
9d31a7b9 | 3851 | if (!ret) |
3852 | ret = mii_nway_restart(&tp->mii); | |
df35d283 | 3853 | |
b5403273 | 3854 | mutex_unlock(&tp->control); |
3855 | ||
df35d283 | 3856 | usb_autopm_put_interface(tp->intf); |
3857 | ||
3858 | out: | |
3859 | return ret; | |
3860 | } | |
3861 | ||
8884f507 | 3862 | static int rtl8152_nway_reset(struct net_device *dev) |
3863 | { | |
3864 | struct r8152 *tp = netdev_priv(dev); | |
3865 | int ret; | |
3866 | ||
3867 | ret = usb_autopm_get_interface(tp->intf); | |
3868 | if (ret < 0) | |
3869 | goto out; | |
3870 | ||
3871 | mutex_lock(&tp->control); | |
3872 | ||
3873 | ret = mii_nway_restart(&tp->mii); | |
3874 | ||
3875 | mutex_unlock(&tp->control); | |
3876 | ||
3877 | usb_autopm_put_interface(tp->intf); | |
3878 | ||
3879 | out: | |
3880 | return ret; | |
3881 | } | |
3882 | ||
efb3dd88 | 3883 | static int rtl8152_get_coalesce(struct net_device *netdev, |
3884 | struct ethtool_coalesce *coalesce) | |
3885 | { | |
3886 | struct r8152 *tp = netdev_priv(netdev); | |
3887 | ||
3888 | switch (tp->version) { | |
3889 | case RTL_VER_01: | |
3890 | case RTL_VER_02: | |
3891 | return -EOPNOTSUPP; | |
3892 | default: | |
3893 | break; | |
3894 | } | |
3895 | ||
3896 | coalesce->rx_coalesce_usecs = tp->coalesce; | |
3897 | ||
3898 | return 0; | |
3899 | } | |
3900 | ||
3901 | static int rtl8152_set_coalesce(struct net_device *netdev, | |
3902 | struct ethtool_coalesce *coalesce) | |
3903 | { | |
3904 | struct r8152 *tp = netdev_priv(netdev); | |
3905 | int ret; | |
3906 | ||
3907 | switch (tp->version) { | |
3908 | case RTL_VER_01: | |
3909 | case RTL_VER_02: | |
3910 | return -EOPNOTSUPP; | |
3911 | default: | |
3912 | break; | |
3913 | } | |
3914 | ||
3915 | if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) | |
3916 | return -EINVAL; | |
3917 | ||
3918 | ret = usb_autopm_get_interface(tp->intf); | |
3919 | if (ret < 0) | |
3920 | return ret; | |
3921 | ||
3922 | mutex_lock(&tp->control); | |
3923 | ||
3924 | if (tp->coalesce != coalesce->rx_coalesce_usecs) { | |
3925 | tp->coalesce = coalesce->rx_coalesce_usecs; | |
3926 | ||
3927 | if (netif_running(tp->netdev) && netif_carrier_ok(netdev)) | |
3928 | r8153_set_rx_early_timeout(tp); | |
3929 | } | |
3930 | ||
3931 | mutex_unlock(&tp->control); | |
3932 | ||
3933 | usb_autopm_put_interface(tp->intf); | |
3934 | ||
3935 | return ret; | |
3936 | } | |
3937 | ||
ac718b69 | 3938 | static struct ethtool_ops ops = { |
3939 | .get_drvinfo = rtl8152_get_drvinfo, | |
3940 | .get_settings = rtl8152_get_settings, | |
3941 | .set_settings = rtl8152_set_settings, | |
3942 | .get_link = ethtool_op_get_link, | |
8884f507 | 3943 | .nway_reset = rtl8152_nway_reset, |
a5ec27c1 | 3944 | .get_msglevel = rtl8152_get_msglevel, |
3945 | .set_msglevel = rtl8152_set_msglevel, | |
21ff2e89 | 3946 | .get_wol = rtl8152_get_wol, |
3947 | .set_wol = rtl8152_set_wol, | |
4f1d4d54 | 3948 | .get_strings = rtl8152_get_strings, |
3949 | .get_sset_count = rtl8152_get_sset_count, | |
3950 | .get_ethtool_stats = rtl8152_get_ethtool_stats, | |
efb3dd88 | 3951 | .get_coalesce = rtl8152_get_coalesce, |
3952 | .set_coalesce = rtl8152_set_coalesce, | |
df35d283 | 3953 | .get_eee = rtl_ethtool_get_eee, |
3954 | .set_eee = rtl_ethtool_set_eee, | |
ac718b69 | 3955 | }; |
3956 | ||
3957 | static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) | |
3958 | { | |
3959 | struct r8152 *tp = netdev_priv(netdev); | |
3960 | struct mii_ioctl_data *data = if_mii(rq); | |
9a4be1bd | 3961 | int res; |
3962 | ||
6871438c | 3963 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3964 | return -ENODEV; | |
3965 | ||
9a4be1bd | 3966 | res = usb_autopm_get_interface(tp->intf); |
3967 | if (res < 0) | |
3968 | goto out; | |
ac718b69 | 3969 | |
3970 | switch (cmd) { | |
3971 | case SIOCGMIIPHY: | |
3972 | data->phy_id = R8152_PHY_ID; /* Internal PHY */ | |
3973 | break; | |
3974 | ||
3975 | case SIOCGMIIREG: | |
b5403273 | 3976 | mutex_lock(&tp->control); |
ac718b69 | 3977 | data->val_out = r8152_mdio_read(tp, data->reg_num); |
b5403273 | 3978 | mutex_unlock(&tp->control); |
ac718b69 | 3979 | break; |
3980 | ||
3981 | case SIOCSMIIREG: | |
3982 | if (!capable(CAP_NET_ADMIN)) { | |
3983 | res = -EPERM; | |
3984 | break; | |
3985 | } | |
b5403273 | 3986 | mutex_lock(&tp->control); |
ac718b69 | 3987 | r8152_mdio_write(tp, data->reg_num, data->val_in); |
b5403273 | 3988 | mutex_unlock(&tp->control); |
ac718b69 | 3989 | break; |
3990 | ||
3991 | default: | |
3992 | res = -EOPNOTSUPP; | |
3993 | } | |
3994 | ||
9a4be1bd | 3995 | usb_autopm_put_interface(tp->intf); |
3996 | ||
3997 | out: | |
ac718b69 | 3998 | return res; |
3999 | } | |
4000 | ||
69b4b7a4 | 4001 | static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) |
4002 | { | |
4003 | struct r8152 *tp = netdev_priv(dev); | |
396e2e23 | 4004 | int ret; |
69b4b7a4 | 4005 | |
4006 | switch (tp->version) { | |
4007 | case RTL_VER_01: | |
4008 | case RTL_VER_02: | |
4009 | return eth_change_mtu(dev, new_mtu); | |
4010 | default: | |
4011 | break; | |
4012 | } | |
4013 | ||
4014 | if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU) | |
4015 | return -EINVAL; | |
4016 | ||
396e2e23 | 4017 | ret = usb_autopm_get_interface(tp->intf); |
4018 | if (ret < 0) | |
4019 | return ret; | |
4020 | ||
4021 | mutex_lock(&tp->control); | |
4022 | ||
69b4b7a4 | 4023 | dev->mtu = new_mtu; |
4024 | ||
396e2e23 | 4025 | if (netif_running(dev) && netif_carrier_ok(dev)) |
4026 | r8153_set_rx_early_size(tp); | |
4027 | ||
4028 | mutex_unlock(&tp->control); | |
4029 | ||
4030 | usb_autopm_put_interface(tp->intf); | |
4031 | ||
4032 | return ret; | |
69b4b7a4 | 4033 | } |
4034 | ||
ac718b69 | 4035 | static const struct net_device_ops rtl8152_netdev_ops = { |
4036 | .ndo_open = rtl8152_open, | |
4037 | .ndo_stop = rtl8152_close, | |
4038 | .ndo_do_ioctl = rtl8152_ioctl, | |
4039 | .ndo_start_xmit = rtl8152_start_xmit, | |
4040 | .ndo_tx_timeout = rtl8152_tx_timeout, | |
c5554298 | 4041 | .ndo_set_features = rtl8152_set_features, |
ac718b69 | 4042 | .ndo_set_rx_mode = rtl8152_set_rx_mode, |
4043 | .ndo_set_mac_address = rtl8152_set_mac_address, | |
69b4b7a4 | 4044 | .ndo_change_mtu = rtl8152_change_mtu, |
ac718b69 | 4045 | .ndo_validate_addr = eth_validate_addr, |
a5e31255 | 4046 | .ndo_features_check = rtl8152_features_check, |
ac718b69 | 4047 | }; |
4048 | ||
4049 | static void r8152b_get_version(struct r8152 *tp) | |
4050 | { | |
4051 | u32 ocp_data; | |
4052 | u16 version; | |
4053 | ||
4054 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); | |
4055 | version = (u16)(ocp_data & VERSION_MASK); | |
4056 | ||
4057 | switch (version) { | |
4058 | case 0x4c00: | |
4059 | tp->version = RTL_VER_01; | |
4060 | break; | |
4061 | case 0x4c10: | |
4062 | tp->version = RTL_VER_02; | |
4063 | break; | |
43779f8d | 4064 | case 0x5c00: |
4065 | tp->version = RTL_VER_03; | |
4066 | tp->mii.supports_gmii = 1; | |
4067 | break; | |
4068 | case 0x5c10: | |
4069 | tp->version = RTL_VER_04; | |
4070 | tp->mii.supports_gmii = 1; | |
4071 | break; | |
4072 | case 0x5c20: | |
4073 | tp->version = RTL_VER_05; | |
4074 | tp->mii.supports_gmii = 1; | |
4075 | break; | |
fb02eb4a | 4076 | case 0x5c30: |
4077 | tp->version = RTL_VER_06; | |
4078 | tp->mii.supports_gmii = 1; | |
4079 | break; | |
ac718b69 | 4080 | default: |
4081 | netif_info(tp, probe, tp->netdev, | |
4082 | "Unknown version 0x%04x\n", version); | |
4083 | break; | |
4084 | } | |
4085 | } | |
4086 | ||
e3fe0b1a | 4087 | static void rtl8152_unload(struct r8152 *tp) |
4088 | { | |
6871438c | 4089 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
4090 | return; | |
4091 | ||
00a5e360 | 4092 | if (tp->version != RTL_VER_01) |
4093 | r8152_power_cut_en(tp, true); | |
e3fe0b1a | 4094 | } |
4095 | ||
43779f8d | 4096 | static void rtl8153_unload(struct r8152 *tp) |
4097 | { | |
6871438c | 4098 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
4099 | return; | |
4100 | ||
49be1723 | 4101 | r8153_power_cut_en(tp, false); |
43779f8d | 4102 | } |
4103 | ||
55b65475 | 4104 | static int rtl_ops_init(struct r8152 *tp) |
c81229c9 | 4105 | { |
4106 | struct rtl_ops *ops = &tp->rtl_ops; | |
55b65475 | 4107 | int ret = 0; |
4108 | ||
4109 | switch (tp->version) { | |
4110 | case RTL_VER_01: | |
4111 | case RTL_VER_02: | |
4112 | ops->init = r8152b_init; | |
4113 | ops->enable = rtl8152_enable; | |
4114 | ops->disable = rtl8152_disable; | |
4115 | ops->up = rtl8152_up; | |
4116 | ops->down = rtl8152_down; | |
4117 | ops->unload = rtl8152_unload; | |
4118 | ops->eee_get = r8152_get_eee; | |
4119 | ops->eee_set = r8152_set_eee; | |
2dd49e0f | 4120 | ops->in_nway = rtl8152_in_nway; |
43779f8d | 4121 | break; |
4122 | ||
55b65475 | 4123 | case RTL_VER_03: |
4124 | case RTL_VER_04: | |
4125 | case RTL_VER_05: | |
fb02eb4a | 4126 | case RTL_VER_06: |
55b65475 | 4127 | ops->init = r8153_init; |
4128 | ops->enable = rtl8153_enable; | |
4129 | ops->disable = rtl8153_disable; | |
4130 | ops->up = rtl8153_up; | |
4131 | ops->down = rtl8153_down; | |
4132 | ops->unload = rtl8153_unload; | |
4133 | ops->eee_get = r8153_get_eee; | |
4134 | ops->eee_set = r8153_set_eee; | |
2dd49e0f | 4135 | ops->in_nway = rtl8153_in_nway; |
c81229c9 | 4136 | break; |
4137 | ||
4138 | default: | |
55b65475 | 4139 | ret = -ENODEV; |
4140 | netif_err(tp, probe, tp->netdev, "Unknown Device\n"); | |
c81229c9 | 4141 | break; |
4142 | } | |
4143 | ||
4144 | return ret; | |
4145 | } | |
4146 | ||
ac718b69 | 4147 | static int rtl8152_probe(struct usb_interface *intf, |
4148 | const struct usb_device_id *id) | |
4149 | { | |
4150 | struct usb_device *udev = interface_to_usbdev(intf); | |
4151 | struct r8152 *tp; | |
4152 | struct net_device *netdev; | |
ebc2ec48 | 4153 | int ret; |
ac718b69 | 4154 | |
10c32717 | 4155 | if (udev->actconfig->desc.bConfigurationValue != 1) { |
4156 | usb_driver_set_configuration(udev, 1); | |
4157 | return -ENODEV; | |
4158 | } | |
4159 | ||
4160 | usb_reset_device(udev); | |
ac718b69 | 4161 | netdev = alloc_etherdev(sizeof(struct r8152)); |
4162 | if (!netdev) { | |
4a8deae2 | 4163 | dev_err(&intf->dev, "Out of memory\n"); |
ac718b69 | 4164 | return -ENOMEM; |
4165 | } | |
4166 | ||
ebc2ec48 | 4167 | SET_NETDEV_DEV(netdev, &intf->dev); |
ac718b69 | 4168 | tp = netdev_priv(netdev); |
4169 | tp->msg_enable = 0x7FFF; | |
4170 | ||
e3ad412a | 4171 | tp->udev = udev; |
4172 | tp->netdev = netdev; | |
4173 | tp->intf = intf; | |
4174 | ||
82cf94cb | 4175 | r8152b_get_version(tp); |
55b65475 | 4176 | ret = rtl_ops_init(tp); |
31ca1dec | 4177 | if (ret) |
4178 | goto out; | |
c81229c9 | 4179 | |
b5403273 | 4180 | mutex_init(&tp->control); |
ac718b69 | 4181 | INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); |
4182 | ||
ac718b69 | 4183 | netdev->netdev_ops = &rtl8152_netdev_ops; |
4184 | netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; | |
5bd23881 | 4185 | |
60c89071 | 4186 | netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 4187 | NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | |
c5554298 | 4188 | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | |
4189 | NETIF_F_HW_VLAN_CTAG_TX; | |
60c89071 | 4190 | netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 4191 | NETIF_F_TSO | NETIF_F_FRAGLIST | |
c5554298 | 4192 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | |
ccc39faf | 4193 | NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; |
c5554298 | 4194 | netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | |
4195 | NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | | |
4196 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6; | |
db8515ef | 4197 | |
7ad24ea4 | 4198 | netdev->ethtool_ops = &ops; |
60c89071 | 4199 | netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); |
ac718b69 | 4200 | |
4201 | tp->mii.dev = netdev; | |
4202 | tp->mii.mdio_read = read_mii_word; | |
4203 | tp->mii.mdio_write = write_mii_word; | |
4204 | tp->mii.phy_id_mask = 0x3f; | |
4205 | tp->mii.reg_num_mask = 0x1f; | |
4206 | tp->mii.phy_id = R8152_PHY_ID; | |
ac718b69 | 4207 | |
464ec10a | 4208 | switch (udev->speed) { |
4209 | case USB_SPEED_SUPER: | |
2b84af94 | 4210 | case USB_SPEED_SUPER_PLUS: |
464ec10a | 4211 | tp->coalesce = COALESCE_SUPER; |
4212 | break; | |
4213 | case USB_SPEED_HIGH: | |
4214 | tp->coalesce = COALESCE_HIGH; | |
4215 | break; | |
4216 | default: | |
4217 | tp->coalesce = COALESCE_SLOW; | |
4218 | break; | |
4219 | } | |
4220 | ||
9a4be1bd | 4221 | intf->needs_remote_wakeup = 1; |
4222 | ||
c81229c9 | 4223 | tp->rtl_ops.init(tp); |
ac718b69 | 4224 | set_ethernet_addr(tp); |
4225 | ||
ac718b69 | 4226 | usb_set_intfdata(intf, tp); |
d823ab68 | 4227 | netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); |
ac718b69 | 4228 | |
ebc2ec48 | 4229 | ret = register_netdev(netdev); |
4230 | if (ret != 0) { | |
4a8deae2 | 4231 | netif_err(tp, probe, netdev, "couldn't register the device\n"); |
ebc2ec48 | 4232 | goto out1; |
ac718b69 | 4233 | } |
4234 | ||
7daed8dc | 4235 | if (!rtl_can_wakeup(tp)) |
4236 | __rtl_set_wol(tp, 0); | |
4237 | ||
21ff2e89 | 4238 | tp->saved_wolopts = __rtl_get_wol(tp); |
4239 | if (tp->saved_wolopts) | |
4240 | device_set_wakeup_enable(&udev->dev, true); | |
4241 | else | |
4242 | device_set_wakeup_enable(&udev->dev, false); | |
4243 | ||
4a8deae2 | 4244 | netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); |
ac718b69 | 4245 | |
4246 | return 0; | |
4247 | ||
ac718b69 | 4248 | out1: |
d823ab68 | 4249 | netif_napi_del(&tp->napi); |
ebc2ec48 | 4250 | usb_set_intfdata(intf, NULL); |
ac718b69 | 4251 | out: |
4252 | free_netdev(netdev); | |
ebc2ec48 | 4253 | return ret; |
ac718b69 | 4254 | } |
4255 | ||
ac718b69 | 4256 | static void rtl8152_disconnect(struct usb_interface *intf) |
4257 | { | |
4258 | struct r8152 *tp = usb_get_intfdata(intf); | |
4259 | ||
4260 | usb_set_intfdata(intf, NULL); | |
4261 | if (tp) { | |
f561de33 | 4262 | struct usb_device *udev = tp->udev; |
4263 | ||
4264 | if (udev->state == USB_STATE_NOTATTACHED) | |
4265 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
4266 | ||
d823ab68 | 4267 | netif_napi_del(&tp->napi); |
ac718b69 | 4268 | unregister_netdev(tp->netdev); |
c81229c9 | 4269 | tp->rtl_ops.unload(tp); |
ac718b69 | 4270 | free_netdev(tp->netdev); |
4271 | } | |
4272 | } | |
4273 | ||
d9a28c5b | 4274 | #define REALTEK_USB_DEVICE(vend, prod) \ |
4275 | .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ | |
4276 | USB_DEVICE_ID_MATCH_INT_CLASS, \ | |
4277 | .idVendor = (vend), \ | |
4278 | .idProduct = (prod), \ | |
4279 | .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ | |
4280 | }, \ | |
4281 | { \ | |
4282 | .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ | |
4283 | USB_DEVICE_ID_MATCH_DEVICE, \ | |
4284 | .idVendor = (vend), \ | |
4285 | .idProduct = (prod), \ | |
4286 | .bInterfaceClass = USB_CLASS_COMM, \ | |
4287 | .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ | |
4288 | .bInterfaceProtocol = USB_CDC_PROTO_NONE | |
4289 | ||
ac718b69 | 4290 | /* table of devices that work with this driver */ |
4291 | static struct usb_device_id rtl8152_table[] = { | |
d9a28c5b | 4292 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, |
4293 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, | |
4294 | {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, | |
347eec34 | 4295 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, |
1006da19 | 4296 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, |
d065c3c1 | 4297 | {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)}, |
ac718b69 | 4298 | {} |
4299 | }; | |
4300 | ||
4301 | MODULE_DEVICE_TABLE(usb, rtl8152_table); | |
4302 | ||
4303 | static struct usb_driver rtl8152_driver = { | |
4304 | .name = MODULENAME, | |
ebc2ec48 | 4305 | .id_table = rtl8152_table, |
ac718b69 | 4306 | .probe = rtl8152_probe, |
4307 | .disconnect = rtl8152_disconnect, | |
ac718b69 | 4308 | .suspend = rtl8152_suspend, |
ebc2ec48 | 4309 | .resume = rtl8152_resume, |
7ec2541a | 4310 | .reset_resume = rtl8152_reset_resume, |
e501139a | 4311 | .pre_reset = rtl8152_pre_reset, |
4312 | .post_reset = rtl8152_post_reset, | |
9a4be1bd | 4313 | .supports_autosuspend = 1, |
a634782f | 4314 | .disable_hub_initiated_lpm = 1, |
ac718b69 | 4315 | }; |
4316 | ||
b4236daa | 4317 | module_usb_driver(rtl8152_driver); |
ac718b69 | 4318 | |
4319 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
4320 | MODULE_DESCRIPTION(DRIVER_DESC); | |
4321 | MODULE_LICENSE("GPL"); |