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ac718b69 | 1 | /* |
c7de7dec | 2 | * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. |
ac718b69 | 3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
ac718b69 | 10 | #include <linux/signal.h> |
11 | #include <linux/slab.h> | |
12 | #include <linux/module.h> | |
ac718b69 | 13 | #include <linux/netdevice.h> |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/mii.h> | |
16 | #include <linux/ethtool.h> | |
17 | #include <linux/usb.h> | |
18 | #include <linux/crc32.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/uaccess.h> | |
ebc2ec48 | 21 | #include <linux/list.h> |
5bd23881 | 22 | #include <linux/ip.h> |
23 | #include <linux/ipv6.h> | |
6128d1bb | 24 | #include <net/ip6_checksum.h> |
4c4a6b1b | 25 | #include <uapi/linux/mdio.h> |
26 | #include <linux/mdio.h> | |
d9a28c5b | 27 | #include <linux/usb/cdc.h> |
ac718b69 | 28 | |
29 | /* Version Information */ | |
37608f3e | 30 | #define DRIVER_VERSION "v1.08.1 (2015/07/28)" |
ac718b69 | 31 | #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" |
44d942a9 | 32 | #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" |
ac718b69 | 33 | #define MODULENAME "r8152" |
34 | ||
35 | #define R8152_PHY_ID 32 | |
36 | ||
37 | #define PLA_IDR 0xc000 | |
38 | #define PLA_RCR 0xc010 | |
39 | #define PLA_RMS 0xc016 | |
40 | #define PLA_RXFIFO_CTRL0 0xc0a0 | |
41 | #define PLA_RXFIFO_CTRL1 0xc0a4 | |
42 | #define PLA_RXFIFO_CTRL2 0xc0a8 | |
65bab84c | 43 | #define PLA_DMY_REG0 0xc0b0 |
ac718b69 | 44 | #define PLA_FMC 0xc0b4 |
45 | #define PLA_CFG_WOL 0xc0b6 | |
43779f8d | 46 | #define PLA_TEREDO_CFG 0xc0bc |
ac718b69 | 47 | #define PLA_MAR 0xcd00 |
43779f8d | 48 | #define PLA_BACKUP 0xd000 |
ac718b69 | 49 | #define PAL_BDC_CR 0xd1a0 |
43779f8d | 50 | #define PLA_TEREDO_TIMER 0xd2cc |
51 | #define PLA_REALWOW_TIMER 0xd2e8 | |
ac718b69 | 52 | #define PLA_LEDSEL 0xdd90 |
53 | #define PLA_LED_FEATURE 0xdd92 | |
54 | #define PLA_PHYAR 0xde00 | |
43779f8d | 55 | #define PLA_BOOT_CTRL 0xe004 |
ac718b69 | 56 | #define PLA_GPHY_INTR_IMR 0xe022 |
57 | #define PLA_EEE_CR 0xe040 | |
58 | #define PLA_EEEP_CR 0xe080 | |
59 | #define PLA_MAC_PWR_CTRL 0xe0c0 | |
43779f8d | 60 | #define PLA_MAC_PWR_CTRL2 0xe0ca |
61 | #define PLA_MAC_PWR_CTRL3 0xe0cc | |
62 | #define PLA_MAC_PWR_CTRL4 0xe0ce | |
63 | #define PLA_WDT6_CTRL 0xe428 | |
ac718b69 | 64 | #define PLA_TCR0 0xe610 |
65 | #define PLA_TCR1 0xe612 | |
69b4b7a4 | 66 | #define PLA_MTPS 0xe615 |
ac718b69 | 67 | #define PLA_TXFIFO_CTRL 0xe618 |
4f1d4d54 | 68 | #define PLA_RSTTALLY 0xe800 |
ac718b69 | 69 | #define PLA_CR 0xe813 |
70 | #define PLA_CRWECR 0xe81c | |
21ff2e89 | 71 | #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ |
72 | #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ | |
ac718b69 | 73 | #define PLA_CONFIG5 0xe822 |
74 | #define PLA_PHY_PWR 0xe84c | |
75 | #define PLA_OOB_CTRL 0xe84f | |
76 | #define PLA_CPCR 0xe854 | |
77 | #define PLA_MISC_0 0xe858 | |
78 | #define PLA_MISC_1 0xe85a | |
79 | #define PLA_OCP_GPHY_BASE 0xe86c | |
4f1d4d54 | 80 | #define PLA_TALLYCNT 0xe890 |
ac718b69 | 81 | #define PLA_SFF_STS_7 0xe8de |
82 | #define PLA_PHYSTATUS 0xe908 | |
83 | #define PLA_BP_BA 0xfc26 | |
84 | #define PLA_BP_0 0xfc28 | |
85 | #define PLA_BP_1 0xfc2a | |
86 | #define PLA_BP_2 0xfc2c | |
87 | #define PLA_BP_3 0xfc2e | |
88 | #define PLA_BP_4 0xfc30 | |
89 | #define PLA_BP_5 0xfc32 | |
90 | #define PLA_BP_6 0xfc34 | |
91 | #define PLA_BP_7 0xfc36 | |
43779f8d | 92 | #define PLA_BP_EN 0xfc38 |
ac718b69 | 93 | |
65bab84c | 94 | #define USB_USB2PHY 0xb41e |
95 | #define USB_SSPHYLINK2 0xb428 | |
43779f8d | 96 | #define USB_U2P3_CTRL 0xb460 |
65bab84c | 97 | #define USB_CSR_DUMMY1 0xb464 |
98 | #define USB_CSR_DUMMY2 0xb466 | |
ac718b69 | 99 | #define USB_DEV_STAT 0xb808 |
65bab84c | 100 | #define USB_CONNECT_TIMER 0xcbf8 |
101 | #define USB_BURST_SIZE 0xcfc0 | |
ac718b69 | 102 | #define USB_USB_CTRL 0xd406 |
103 | #define USB_PHY_CTRL 0xd408 | |
104 | #define USB_TX_AGG 0xd40a | |
105 | #define USB_RX_BUF_TH 0xd40c | |
106 | #define USB_USB_TIMER 0xd428 | |
464ec10a | 107 | #define USB_RX_EARLY_TIMEOUT 0xd42c |
108 | #define USB_RX_EARLY_SIZE 0xd42e | |
ac718b69 | 109 | #define USB_PM_CTRL_STATUS 0xd432 |
110 | #define USB_TX_DMA 0xd434 | |
43779f8d | 111 | #define USB_TOLERANCE 0xd490 |
112 | #define USB_LPM_CTRL 0xd41a | |
ac718b69 | 113 | #define USB_UPS_CTRL 0xd800 |
43779f8d | 114 | #define USB_MISC_0 0xd81a |
115 | #define USB_POWER_CUT 0xd80a | |
116 | #define USB_AFE_CTRL2 0xd824 | |
117 | #define USB_WDT11_CTRL 0xe43c | |
ac718b69 | 118 | #define USB_BP_BA 0xfc26 |
119 | #define USB_BP_0 0xfc28 | |
120 | #define USB_BP_1 0xfc2a | |
121 | #define USB_BP_2 0xfc2c | |
122 | #define USB_BP_3 0xfc2e | |
123 | #define USB_BP_4 0xfc30 | |
124 | #define USB_BP_5 0xfc32 | |
125 | #define USB_BP_6 0xfc34 | |
126 | #define USB_BP_7 0xfc36 | |
43779f8d | 127 | #define USB_BP_EN 0xfc38 |
ac718b69 | 128 | |
129 | /* OCP Registers */ | |
130 | #define OCP_ALDPS_CONFIG 0x2010 | |
131 | #define OCP_EEE_CONFIG1 0x2080 | |
132 | #define OCP_EEE_CONFIG2 0x2092 | |
133 | #define OCP_EEE_CONFIG3 0x2094 | |
ac244d3e | 134 | #define OCP_BASE_MII 0xa400 |
ac718b69 | 135 | #define OCP_EEE_AR 0xa41a |
136 | #define OCP_EEE_DATA 0xa41c | |
43779f8d | 137 | #define OCP_PHY_STATUS 0xa420 |
138 | #define OCP_POWER_CFG 0xa430 | |
139 | #define OCP_EEE_CFG 0xa432 | |
140 | #define OCP_SRAM_ADDR 0xa436 | |
141 | #define OCP_SRAM_DATA 0xa438 | |
142 | #define OCP_DOWN_SPEED 0xa442 | |
df35d283 | 143 | #define OCP_EEE_ABLE 0xa5c4 |
4c4a6b1b | 144 | #define OCP_EEE_ADV 0xa5d0 |
df35d283 | 145 | #define OCP_EEE_LPABLE 0xa5d2 |
43779f8d | 146 | #define OCP_ADC_CFG 0xbc06 |
147 | ||
148 | /* SRAM Register */ | |
149 | #define SRAM_LPF_CFG 0x8012 | |
150 | #define SRAM_10M_AMP1 0x8080 | |
151 | #define SRAM_10M_AMP2 0x8082 | |
152 | #define SRAM_IMPEDANCE 0x8084 | |
ac718b69 | 153 | |
154 | /* PLA_RCR */ | |
155 | #define RCR_AAP 0x00000001 | |
156 | #define RCR_APM 0x00000002 | |
157 | #define RCR_AM 0x00000004 | |
158 | #define RCR_AB 0x00000008 | |
159 | #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) | |
160 | ||
161 | /* PLA_RXFIFO_CTRL0 */ | |
162 | #define RXFIFO_THR1_NORMAL 0x00080002 | |
163 | #define RXFIFO_THR1_OOB 0x01800003 | |
164 | ||
165 | /* PLA_RXFIFO_CTRL1 */ | |
166 | #define RXFIFO_THR2_FULL 0x00000060 | |
167 | #define RXFIFO_THR2_HIGH 0x00000038 | |
168 | #define RXFIFO_THR2_OOB 0x0000004a | |
43779f8d | 169 | #define RXFIFO_THR2_NORMAL 0x00a0 |
ac718b69 | 170 | |
171 | /* PLA_RXFIFO_CTRL2 */ | |
172 | #define RXFIFO_THR3_FULL 0x00000078 | |
173 | #define RXFIFO_THR3_HIGH 0x00000048 | |
174 | #define RXFIFO_THR3_OOB 0x0000005a | |
43779f8d | 175 | #define RXFIFO_THR3_NORMAL 0x0110 |
ac718b69 | 176 | |
177 | /* PLA_TXFIFO_CTRL */ | |
178 | #define TXFIFO_THR_NORMAL 0x00400008 | |
43779f8d | 179 | #define TXFIFO_THR_NORMAL2 0x01000008 |
ac718b69 | 180 | |
65bab84c | 181 | /* PLA_DMY_REG0 */ |
182 | #define ECM_ALDPS 0x0002 | |
183 | ||
ac718b69 | 184 | /* PLA_FMC */ |
185 | #define FMC_FCR_MCU_EN 0x0001 | |
186 | ||
187 | /* PLA_EEEP_CR */ | |
188 | #define EEEP_CR_EEEP_TX 0x0002 | |
189 | ||
43779f8d | 190 | /* PLA_WDT6_CTRL */ |
191 | #define WDT6_SET_MODE 0x0010 | |
192 | ||
ac718b69 | 193 | /* PLA_TCR0 */ |
194 | #define TCR0_TX_EMPTY 0x0800 | |
195 | #define TCR0_AUTO_FIFO 0x0080 | |
196 | ||
197 | /* PLA_TCR1 */ | |
198 | #define VERSION_MASK 0x7cf0 | |
199 | ||
69b4b7a4 | 200 | /* PLA_MTPS */ |
201 | #define MTPS_JUMBO (12 * 1024 / 64) | |
202 | #define MTPS_DEFAULT (6 * 1024 / 64) | |
203 | ||
4f1d4d54 | 204 | /* PLA_RSTTALLY */ |
205 | #define TALLY_RESET 0x0001 | |
206 | ||
ac718b69 | 207 | /* PLA_CR */ |
208 | #define CR_RST 0x10 | |
209 | #define CR_RE 0x08 | |
210 | #define CR_TE 0x04 | |
211 | ||
212 | /* PLA_CRWECR */ | |
213 | #define CRWECR_NORAML 0x00 | |
214 | #define CRWECR_CONFIG 0xc0 | |
215 | ||
216 | /* PLA_OOB_CTRL */ | |
217 | #define NOW_IS_OOB 0x80 | |
218 | #define TXFIFO_EMPTY 0x20 | |
219 | #define RXFIFO_EMPTY 0x10 | |
220 | #define LINK_LIST_READY 0x02 | |
221 | #define DIS_MCU_CLROOB 0x01 | |
222 | #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) | |
223 | ||
224 | /* PLA_MISC_1 */ | |
225 | #define RXDY_GATED_EN 0x0008 | |
226 | ||
227 | /* PLA_SFF_STS_7 */ | |
228 | #define RE_INIT_LL 0x8000 | |
229 | #define MCU_BORW_EN 0x4000 | |
230 | ||
231 | /* PLA_CPCR */ | |
232 | #define CPCR_RX_VLAN 0x0040 | |
233 | ||
234 | /* PLA_CFG_WOL */ | |
235 | #define MAGIC_EN 0x0001 | |
236 | ||
43779f8d | 237 | /* PLA_TEREDO_CFG */ |
238 | #define TEREDO_SEL 0x8000 | |
239 | #define TEREDO_WAKE_MASK 0x7f00 | |
240 | #define TEREDO_RS_EVENT_MASK 0x00fe | |
241 | #define OOB_TEREDO_EN 0x0001 | |
242 | ||
ac718b69 | 243 | /* PAL_BDC_CR */ |
244 | #define ALDPS_PROXY_MODE 0x0001 | |
245 | ||
21ff2e89 | 246 | /* PLA_CONFIG34 */ |
247 | #define LINK_ON_WAKE_EN 0x0010 | |
248 | #define LINK_OFF_WAKE_EN 0x0008 | |
249 | ||
ac718b69 | 250 | /* PLA_CONFIG5 */ |
21ff2e89 | 251 | #define BWF_EN 0x0040 |
252 | #define MWF_EN 0x0020 | |
253 | #define UWF_EN 0x0010 | |
ac718b69 | 254 | #define LAN_WAKE_EN 0x0002 |
255 | ||
256 | /* PLA_LED_FEATURE */ | |
257 | #define LED_MODE_MASK 0x0700 | |
258 | ||
259 | /* PLA_PHY_PWR */ | |
260 | #define TX_10M_IDLE_EN 0x0080 | |
261 | #define PFM_PWM_SWITCH 0x0040 | |
262 | ||
263 | /* PLA_MAC_PWR_CTRL */ | |
264 | #define D3_CLK_GATED_EN 0x00004000 | |
265 | #define MCU_CLK_RATIO 0x07010f07 | |
266 | #define MCU_CLK_RATIO_MASK 0x0f0f0f0f | |
43779f8d | 267 | #define ALDPS_SPDWN_RATIO 0x0f87 |
268 | ||
269 | /* PLA_MAC_PWR_CTRL2 */ | |
270 | #define EEE_SPDWN_RATIO 0x8007 | |
271 | ||
272 | /* PLA_MAC_PWR_CTRL3 */ | |
273 | #define PKT_AVAIL_SPDWN_EN 0x0100 | |
274 | #define SUSPEND_SPDWN_EN 0x0004 | |
275 | #define U1U2_SPDWN_EN 0x0002 | |
276 | #define L1_SPDWN_EN 0x0001 | |
277 | ||
278 | /* PLA_MAC_PWR_CTRL4 */ | |
279 | #define PWRSAVE_SPDWN_EN 0x1000 | |
280 | #define RXDV_SPDWN_EN 0x0800 | |
281 | #define TX10MIDLE_EN 0x0100 | |
282 | #define TP100_SPDWN_EN 0x0020 | |
283 | #define TP500_SPDWN_EN 0x0010 | |
284 | #define TP1000_SPDWN_EN 0x0008 | |
285 | #define EEE_SPDWN_EN 0x0001 | |
ac718b69 | 286 | |
287 | /* PLA_GPHY_INTR_IMR */ | |
288 | #define GPHY_STS_MSK 0x0001 | |
289 | #define SPEED_DOWN_MSK 0x0002 | |
290 | #define SPDWN_RXDV_MSK 0x0004 | |
291 | #define SPDWN_LINKCHG_MSK 0x0008 | |
292 | ||
293 | /* PLA_PHYAR */ | |
294 | #define PHYAR_FLAG 0x80000000 | |
295 | ||
296 | /* PLA_EEE_CR */ | |
297 | #define EEE_RX_EN 0x0001 | |
298 | #define EEE_TX_EN 0x0002 | |
299 | ||
43779f8d | 300 | /* PLA_BOOT_CTRL */ |
301 | #define AUTOLOAD_DONE 0x0002 | |
302 | ||
65bab84c | 303 | /* USB_USB2PHY */ |
304 | #define USB2PHY_SUSPEND 0x0001 | |
305 | #define USB2PHY_L1 0x0002 | |
306 | ||
307 | /* USB_SSPHYLINK2 */ | |
308 | #define pwd_dn_scale_mask 0x3ffe | |
309 | #define pwd_dn_scale(x) ((x) << 1) | |
310 | ||
311 | /* USB_CSR_DUMMY1 */ | |
312 | #define DYNAMIC_BURST 0x0001 | |
313 | ||
314 | /* USB_CSR_DUMMY2 */ | |
315 | #define EP4_FULL_FC 0x0001 | |
316 | ||
ac718b69 | 317 | /* USB_DEV_STAT */ |
318 | #define STAT_SPEED_MASK 0x0006 | |
319 | #define STAT_SPEED_HIGH 0x0000 | |
a3cc465d | 320 | #define STAT_SPEED_FULL 0x0002 |
ac718b69 | 321 | |
322 | /* USB_TX_AGG */ | |
323 | #define TX_AGG_MAX_THRESHOLD 0x03 | |
324 | ||
325 | /* USB_RX_BUF_TH */ | |
43779f8d | 326 | #define RX_THR_SUPPER 0x0c350180 |
8e1f51bd | 327 | #define RX_THR_HIGH 0x7a120180 |
43779f8d | 328 | #define RX_THR_SLOW 0xffff0180 |
ac718b69 | 329 | |
330 | /* USB_TX_DMA */ | |
331 | #define TEST_MODE_DISABLE 0x00000001 | |
332 | #define TX_SIZE_ADJUST1 0x00000100 | |
333 | ||
334 | /* USB_UPS_CTRL */ | |
335 | #define POWER_CUT 0x0100 | |
336 | ||
337 | /* USB_PM_CTRL_STATUS */ | |
8e1f51bd | 338 | #define RESUME_INDICATE 0x0001 |
ac718b69 | 339 | |
340 | /* USB_USB_CTRL */ | |
341 | #define RX_AGG_DISABLE 0x0010 | |
e90fba8d | 342 | #define RX_ZERO_EN 0x0080 |
ac718b69 | 343 | |
43779f8d | 344 | /* USB_U2P3_CTRL */ |
345 | #define U2P3_ENABLE 0x0001 | |
346 | ||
347 | /* USB_POWER_CUT */ | |
348 | #define PWR_EN 0x0001 | |
349 | #define PHASE2_EN 0x0008 | |
350 | ||
351 | /* USB_MISC_0 */ | |
352 | #define PCUT_STATUS 0x0001 | |
353 | ||
464ec10a | 354 | /* USB_RX_EARLY_TIMEOUT */ |
355 | #define COALESCE_SUPER 85000U | |
356 | #define COALESCE_HIGH 250000U | |
357 | #define COALESCE_SLOW 524280U | |
43779f8d | 358 | |
359 | /* USB_WDT11_CTRL */ | |
360 | #define TIMER11_EN 0x0001 | |
361 | ||
362 | /* USB_LPM_CTRL */ | |
65bab84c | 363 | /* bit 4 ~ 5: fifo empty boundary */ |
364 | #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ | |
365 | /* bit 2 ~ 3: LMP timer */ | |
43779f8d | 366 | #define LPM_TIMER_MASK 0x0c |
367 | #define LPM_TIMER_500MS 0x04 /* 500 ms */ | |
368 | #define LPM_TIMER_500US 0x0c /* 500 us */ | |
65bab84c | 369 | #define ROK_EXIT_LPM 0x02 |
43779f8d | 370 | |
371 | /* USB_AFE_CTRL2 */ | |
372 | #define SEN_VAL_MASK 0xf800 | |
373 | #define SEN_VAL_NORMAL 0xa000 | |
374 | #define SEL_RXIDLE 0x0100 | |
375 | ||
ac718b69 | 376 | /* OCP_ALDPS_CONFIG */ |
377 | #define ENPWRSAVE 0x8000 | |
378 | #define ENPDNPS 0x0200 | |
379 | #define LINKENA 0x0100 | |
380 | #define DIS_SDSAVE 0x0010 | |
381 | ||
43779f8d | 382 | /* OCP_PHY_STATUS */ |
383 | #define PHY_STAT_MASK 0x0007 | |
384 | #define PHY_STAT_LAN_ON 3 | |
385 | #define PHY_STAT_PWRDN 5 | |
386 | ||
387 | /* OCP_POWER_CFG */ | |
388 | #define EEE_CLKDIV_EN 0x8000 | |
389 | #define EN_ALDPS 0x0004 | |
390 | #define EN_10M_PLLOFF 0x0001 | |
391 | ||
ac718b69 | 392 | /* OCP_EEE_CONFIG1 */ |
393 | #define RG_TXLPI_MSK_HFDUP 0x8000 | |
394 | #define RG_MATCLR_EN 0x4000 | |
395 | #define EEE_10_CAP 0x2000 | |
396 | #define EEE_NWAY_EN 0x1000 | |
397 | #define TX_QUIET_EN 0x0200 | |
398 | #define RX_QUIET_EN 0x0100 | |
d24f6134 | 399 | #define sd_rise_time_mask 0x0070 |
4c4a6b1b | 400 | #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ |
ac718b69 | 401 | #define RG_RXLPI_MSK_HFDUP 0x0008 |
402 | #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ | |
403 | ||
404 | /* OCP_EEE_CONFIG2 */ | |
405 | #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ | |
406 | #define RG_DACQUIET_EN 0x0400 | |
407 | #define RG_LDVQUIET_EN 0x0200 | |
408 | #define RG_CKRSEL 0x0020 | |
409 | #define RG_EEEPRG_EN 0x0010 | |
410 | ||
411 | /* OCP_EEE_CONFIG3 */ | |
d24f6134 | 412 | #define fast_snr_mask 0xff80 |
4c4a6b1b | 413 | #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ |
ac718b69 | 414 | #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ |
415 | #define MSK_PH 0x0006 /* bit 0 ~ 3 */ | |
416 | ||
417 | /* OCP_EEE_AR */ | |
418 | /* bit[15:14] function */ | |
419 | #define FUN_ADDR 0x0000 | |
420 | #define FUN_DATA 0x4000 | |
421 | /* bit[4:0] device addr */ | |
ac718b69 | 422 | |
43779f8d | 423 | /* OCP_EEE_CFG */ |
424 | #define CTAP_SHORT_EN 0x0040 | |
425 | #define EEE10_EN 0x0010 | |
426 | ||
427 | /* OCP_DOWN_SPEED */ | |
428 | #define EN_10M_BGOFF 0x0080 | |
429 | ||
43779f8d | 430 | /* OCP_ADC_CFG */ |
431 | #define CKADSEL_L 0x0100 | |
432 | #define ADC_EN 0x0080 | |
433 | #define EN_EMI_L 0x0040 | |
434 | ||
435 | /* SRAM_LPF_CFG */ | |
436 | #define LPF_AUTO_TUNE 0x8000 | |
437 | ||
438 | /* SRAM_10M_AMP1 */ | |
439 | #define GDAC_IB_UPALL 0x0008 | |
440 | ||
441 | /* SRAM_10M_AMP2 */ | |
442 | #define AMP_DN 0x0200 | |
443 | ||
444 | /* SRAM_IMPEDANCE */ | |
445 | #define RX_DRIVING_MASK 0x6000 | |
446 | ||
ac718b69 | 447 | enum rtl_register_content { |
43779f8d | 448 | _1000bps = 0x10, |
ac718b69 | 449 | _100bps = 0x08, |
450 | _10bps = 0x04, | |
451 | LINK_STATUS = 0x02, | |
452 | FULL_DUP = 0x01, | |
453 | }; | |
454 | ||
1764bcd9 | 455 | #define RTL8152_MAX_TX 4 |
ebc2ec48 | 456 | #define RTL8152_MAX_RX 10 |
40a82917 | 457 | #define INTBUFSIZE 2 |
8e1f51bd | 458 | #define CRC_SIZE 4 |
459 | #define TX_ALIGN 4 | |
460 | #define RX_ALIGN 8 | |
40a82917 | 461 | |
462 | #define INTR_LINK 0x0004 | |
ebc2ec48 | 463 | |
ac718b69 | 464 | #define RTL8152_REQT_READ 0xc0 |
465 | #define RTL8152_REQT_WRITE 0x40 | |
466 | #define RTL8152_REQ_GET_REGS 0x05 | |
467 | #define RTL8152_REQ_SET_REGS 0x05 | |
468 | ||
469 | #define BYTE_EN_DWORD 0xff | |
470 | #define BYTE_EN_WORD 0x33 | |
471 | #define BYTE_EN_BYTE 0x11 | |
472 | #define BYTE_EN_SIX_BYTES 0x3f | |
473 | #define BYTE_EN_START_MASK 0x0f | |
474 | #define BYTE_EN_END_MASK 0xf0 | |
475 | ||
69b4b7a4 | 476 | #define RTL8153_MAX_PACKET 9216 /* 9K */ |
477 | #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN) | |
ac718b69 | 478 | #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) |
69b4b7a4 | 479 | #define RTL8153_RMS RTL8153_MAX_PACKET |
b8125404 | 480 | #define RTL8152_TX_TIMEOUT (5 * HZ) |
d823ab68 | 481 | #define RTL8152_NAPI_WEIGHT 64 |
ac718b69 | 482 | |
483 | /* rtl8152 flags */ | |
484 | enum rtl8152_flags { | |
485 | RTL8152_UNPLUG = 0, | |
ac718b69 | 486 | RTL8152_SET_RX_MODE, |
40a82917 | 487 | WORK_ENABLE, |
488 | RTL8152_LINK_CHG, | |
9a4be1bd | 489 | SELECTIVE_SUSPEND, |
aa66a5f1 | 490 | PHY_RESET, |
d823ab68 | 491 | SCHEDULE_NAPI, |
ac718b69 | 492 | }; |
493 | ||
494 | /* Define these values to match your device */ | |
495 | #define VENDOR_ID_REALTEK 0x0bda | |
43779f8d | 496 | #define VENDOR_ID_SAMSUNG 0x04e8 |
347eec34 | 497 | #define VENDOR_ID_LENOVO 0x17ef |
d065c3c1 | 498 | #define VENDOR_ID_NVIDIA 0x0955 |
ac718b69 | 499 | |
500 | #define MCU_TYPE_PLA 0x0100 | |
501 | #define MCU_TYPE_USB 0x0000 | |
502 | ||
4f1d4d54 | 503 | struct tally_counter { |
504 | __le64 tx_packets; | |
505 | __le64 rx_packets; | |
506 | __le64 tx_errors; | |
507 | __le32 rx_errors; | |
508 | __le16 rx_missed; | |
509 | __le16 align_errors; | |
510 | __le32 tx_one_collision; | |
511 | __le32 tx_multi_collision; | |
512 | __le64 rx_unicast; | |
513 | __le64 rx_broadcast; | |
514 | __le32 rx_multicast; | |
515 | __le16 tx_aborted; | |
f37119c5 | 516 | __le16 tx_underrun; |
4f1d4d54 | 517 | }; |
518 | ||
ac718b69 | 519 | struct rx_desc { |
500b6d7e | 520 | __le32 opts1; |
ac718b69 | 521 | #define RX_LEN_MASK 0x7fff |
565cab0a | 522 | |
500b6d7e | 523 | __le32 opts2; |
f5aaaa6d | 524 | #define RD_UDP_CS BIT(23) |
525 | #define RD_TCP_CS BIT(22) | |
526 | #define RD_IPV6_CS BIT(20) | |
527 | #define RD_IPV4_CS BIT(19) | |
565cab0a | 528 | |
500b6d7e | 529 | __le32 opts3; |
f5aaaa6d | 530 | #define IPF BIT(23) /* IP checksum fail */ |
531 | #define UDPF BIT(22) /* UDP checksum fail */ | |
532 | #define TCPF BIT(21) /* TCP checksum fail */ | |
533 | #define RX_VLAN_TAG BIT(16) | |
565cab0a | 534 | |
500b6d7e | 535 | __le32 opts4; |
536 | __le32 opts5; | |
537 | __le32 opts6; | |
ac718b69 | 538 | }; |
539 | ||
540 | struct tx_desc { | |
500b6d7e | 541 | __le32 opts1; |
f5aaaa6d | 542 | #define TX_FS BIT(31) /* First segment of a packet */ |
543 | #define TX_LS BIT(30) /* Final segment of a packet */ | |
544 | #define GTSENDV4 BIT(28) | |
545 | #define GTSENDV6 BIT(27) | |
60c89071 | 546 | #define GTTCPHO_SHIFT 18 |
6128d1bb | 547 | #define GTTCPHO_MAX 0x7fU |
60c89071 | 548 | #define TX_LEN_MAX 0x3ffffU |
5bd23881 | 549 | |
500b6d7e | 550 | __le32 opts2; |
f5aaaa6d | 551 | #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ |
552 | #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ | |
553 | #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ | |
554 | #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ | |
60c89071 | 555 | #define MSS_SHIFT 17 |
556 | #define MSS_MAX 0x7ffU | |
557 | #define TCPHO_SHIFT 17 | |
6128d1bb | 558 | #define TCPHO_MAX 0x7ffU |
f5aaaa6d | 559 | #define TX_VLAN_TAG BIT(16) |
ac718b69 | 560 | }; |
561 | ||
dff4e8ad | 562 | struct r8152; |
563 | ||
ebc2ec48 | 564 | struct rx_agg { |
565 | struct list_head list; | |
566 | struct urb *urb; | |
dff4e8ad | 567 | struct r8152 *context; |
ebc2ec48 | 568 | void *buffer; |
569 | void *head; | |
570 | }; | |
571 | ||
572 | struct tx_agg { | |
573 | struct list_head list; | |
574 | struct urb *urb; | |
dff4e8ad | 575 | struct r8152 *context; |
ebc2ec48 | 576 | void *buffer; |
577 | void *head; | |
578 | u32 skb_num; | |
579 | u32 skb_len; | |
580 | }; | |
581 | ||
ac718b69 | 582 | struct r8152 { |
583 | unsigned long flags; | |
584 | struct usb_device *udev; | |
d823ab68 | 585 | struct napi_struct napi; |
40a82917 | 586 | struct usb_interface *intf; |
ac718b69 | 587 | struct net_device *netdev; |
40a82917 | 588 | struct urb *intr_urb; |
ebc2ec48 | 589 | struct tx_agg tx_info[RTL8152_MAX_TX]; |
590 | struct rx_agg rx_info[RTL8152_MAX_RX]; | |
591 | struct list_head rx_done, tx_free; | |
d823ab68 | 592 | struct sk_buff_head tx_queue, rx_queue; |
ebc2ec48 | 593 | spinlock_t rx_lock, tx_lock; |
ac718b69 | 594 | struct delayed_work schedule; |
595 | struct mii_if_info mii; | |
b5403273 | 596 | struct mutex control; /* use for hw setting */ |
c81229c9 | 597 | |
598 | struct rtl_ops { | |
599 | void (*init)(struct r8152 *); | |
600 | int (*enable)(struct r8152 *); | |
601 | void (*disable)(struct r8152 *); | |
7e9da481 | 602 | void (*up)(struct r8152 *); |
c81229c9 | 603 | void (*down)(struct r8152 *); |
604 | void (*unload)(struct r8152 *); | |
df35d283 | 605 | int (*eee_get)(struct r8152 *, struct ethtool_eee *); |
606 | int (*eee_set)(struct r8152 *, struct ethtool_eee *); | |
c81229c9 | 607 | } rtl_ops; |
608 | ||
40a82917 | 609 | int intr_interval; |
21ff2e89 | 610 | u32 saved_wolopts; |
ac718b69 | 611 | u32 msg_enable; |
dd1b119c | 612 | u32 tx_qlen; |
464ec10a | 613 | u32 coalesce; |
ac718b69 | 614 | u16 ocp_base; |
40a82917 | 615 | u8 *intr_buff; |
ac718b69 | 616 | u8 version; |
ac718b69 | 617 | }; |
618 | ||
619 | enum rtl_version { | |
620 | RTL_VER_UNKNOWN = 0, | |
621 | RTL_VER_01, | |
43779f8d | 622 | RTL_VER_02, |
623 | RTL_VER_03, | |
624 | RTL_VER_04, | |
625 | RTL_VER_05, | |
fb02eb4a | 626 | RTL_VER_06, |
43779f8d | 627 | RTL_VER_MAX |
ac718b69 | 628 | }; |
629 | ||
60c89071 | 630 | enum tx_csum_stat { |
631 | TX_CSUM_SUCCESS = 0, | |
632 | TX_CSUM_TSO, | |
633 | TX_CSUM_NONE | |
634 | }; | |
635 | ||
ac718b69 | 636 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
637 | * The RTL chips use a 64 element hash table based on the Ethernet CRC. | |
638 | */ | |
639 | static const int multicast_filter_limit = 32; | |
52aec126 | 640 | static unsigned int agg_buf_sz = 16384; |
ac718b69 | 641 | |
52aec126 | 642 | #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ |
60c89071 | 643 | VLAN_ETH_HLEN - VLAN_HLEN) |
644 | ||
ac718b69 | 645 | static |
646 | int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
647 | { | |
31787f53 | 648 | int ret; |
649 | void *tmp; | |
650 | ||
651 | tmp = kmalloc(size, GFP_KERNEL); | |
652 | if (!tmp) | |
653 | return -ENOMEM; | |
654 | ||
655 | ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), | |
b209af99 | 656 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, |
657 | value, index, tmp, size, 500); | |
31787f53 | 658 | |
659 | memcpy(data, tmp, size); | |
660 | kfree(tmp); | |
661 | ||
662 | return ret; | |
ac718b69 | 663 | } |
664 | ||
665 | static | |
666 | int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
667 | { | |
31787f53 | 668 | int ret; |
669 | void *tmp; | |
670 | ||
c4438f03 | 671 | tmp = kmemdup(data, size, GFP_KERNEL); |
31787f53 | 672 | if (!tmp) |
673 | return -ENOMEM; | |
674 | ||
31787f53 | 675 | ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), |
b209af99 | 676 | RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, |
677 | value, index, tmp, size, 500); | |
31787f53 | 678 | |
679 | kfree(tmp); | |
db8515ef | 680 | |
31787f53 | 681 | return ret; |
ac718b69 | 682 | } |
683 | ||
684 | static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, | |
b209af99 | 685 | void *data, u16 type) |
ac718b69 | 686 | { |
45f4a19f | 687 | u16 limit = 64; |
688 | int ret = 0; | |
ac718b69 | 689 | |
690 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
691 | return -ENODEV; | |
692 | ||
693 | /* both size and indix must be 4 bytes align */ | |
694 | if ((size & 3) || !size || (index & 3) || !data) | |
695 | return -EPERM; | |
696 | ||
697 | if ((u32)index + (u32)size > 0xffff) | |
698 | return -EPERM; | |
699 | ||
700 | while (size) { | |
701 | if (size > limit) { | |
702 | ret = get_registers(tp, index, type, limit, data); | |
703 | if (ret < 0) | |
704 | break; | |
705 | ||
706 | index += limit; | |
707 | data += limit; | |
708 | size -= limit; | |
709 | } else { | |
710 | ret = get_registers(tp, index, type, size, data); | |
711 | if (ret < 0) | |
712 | break; | |
713 | ||
714 | index += size; | |
715 | data += size; | |
716 | size = 0; | |
717 | break; | |
718 | } | |
719 | } | |
720 | ||
67610496 | 721 | if (ret == -ENODEV) |
722 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
723 | ||
ac718b69 | 724 | return ret; |
725 | } | |
726 | ||
727 | static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, | |
b209af99 | 728 | u16 size, void *data, u16 type) |
ac718b69 | 729 | { |
45f4a19f | 730 | int ret; |
731 | u16 byteen_start, byteen_end, byen; | |
732 | u16 limit = 512; | |
ac718b69 | 733 | |
734 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
735 | return -ENODEV; | |
736 | ||
737 | /* both size and indix must be 4 bytes align */ | |
738 | if ((size & 3) || !size || (index & 3) || !data) | |
739 | return -EPERM; | |
740 | ||
741 | if ((u32)index + (u32)size > 0xffff) | |
742 | return -EPERM; | |
743 | ||
744 | byteen_start = byteen & BYTE_EN_START_MASK; | |
745 | byteen_end = byteen & BYTE_EN_END_MASK; | |
746 | ||
747 | byen = byteen_start | (byteen_start << 4); | |
748 | ret = set_registers(tp, index, type | byen, 4, data); | |
749 | if (ret < 0) | |
750 | goto error1; | |
751 | ||
752 | index += 4; | |
753 | data += 4; | |
754 | size -= 4; | |
755 | ||
756 | if (size) { | |
757 | size -= 4; | |
758 | ||
759 | while (size) { | |
760 | if (size > limit) { | |
761 | ret = set_registers(tp, index, | |
b209af99 | 762 | type | BYTE_EN_DWORD, |
763 | limit, data); | |
ac718b69 | 764 | if (ret < 0) |
765 | goto error1; | |
766 | ||
767 | index += limit; | |
768 | data += limit; | |
769 | size -= limit; | |
770 | } else { | |
771 | ret = set_registers(tp, index, | |
b209af99 | 772 | type | BYTE_EN_DWORD, |
773 | size, data); | |
ac718b69 | 774 | if (ret < 0) |
775 | goto error1; | |
776 | ||
777 | index += size; | |
778 | data += size; | |
779 | size = 0; | |
780 | break; | |
781 | } | |
782 | } | |
783 | ||
784 | byen = byteen_end | (byteen_end >> 4); | |
785 | ret = set_registers(tp, index, type | byen, 4, data); | |
786 | if (ret < 0) | |
787 | goto error1; | |
788 | } | |
789 | ||
790 | error1: | |
67610496 | 791 | if (ret == -ENODEV) |
792 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
793 | ||
ac718b69 | 794 | return ret; |
795 | } | |
796 | ||
797 | static inline | |
798 | int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
799 | { | |
800 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); | |
801 | } | |
802 | ||
803 | static inline | |
804 | int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
805 | { | |
806 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); | |
807 | } | |
808 | ||
809 | static inline | |
810 | int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
811 | { | |
812 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); | |
813 | } | |
814 | ||
815 | static inline | |
816 | int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
817 | { | |
818 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); | |
819 | } | |
820 | ||
821 | static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) | |
822 | { | |
c8826de8 | 823 | __le32 data; |
ac718b69 | 824 | |
c8826de8 | 825 | generic_ocp_read(tp, index, sizeof(data), &data, type); |
ac718b69 | 826 | |
827 | return __le32_to_cpu(data); | |
828 | } | |
829 | ||
830 | static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) | |
831 | { | |
c8826de8 | 832 | __le32 tmp = __cpu_to_le32(data); |
833 | ||
834 | generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); | |
ac718b69 | 835 | } |
836 | ||
837 | static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) | |
838 | { | |
839 | u32 data; | |
c8826de8 | 840 | __le32 tmp; |
ac718b69 | 841 | u8 shift = index & 2; |
842 | ||
843 | index &= ~3; | |
844 | ||
c8826de8 | 845 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 846 | |
c8826de8 | 847 | data = __le32_to_cpu(tmp); |
ac718b69 | 848 | data >>= (shift * 8); |
849 | data &= 0xffff; | |
850 | ||
851 | return (u16)data; | |
852 | } | |
853 | ||
854 | static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) | |
855 | { | |
c8826de8 | 856 | u32 mask = 0xffff; |
857 | __le32 tmp; | |
ac718b69 | 858 | u16 byen = BYTE_EN_WORD; |
859 | u8 shift = index & 2; | |
860 | ||
861 | data &= mask; | |
862 | ||
863 | if (index & 2) { | |
864 | byen <<= shift; | |
865 | mask <<= (shift * 8); | |
866 | data <<= (shift * 8); | |
867 | index &= ~3; | |
868 | } | |
869 | ||
c8826de8 | 870 | tmp = __cpu_to_le32(data); |
ac718b69 | 871 | |
c8826de8 | 872 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 873 | } |
874 | ||
875 | static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) | |
876 | { | |
877 | u32 data; | |
c8826de8 | 878 | __le32 tmp; |
ac718b69 | 879 | u8 shift = index & 3; |
880 | ||
881 | index &= ~3; | |
882 | ||
c8826de8 | 883 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 884 | |
c8826de8 | 885 | data = __le32_to_cpu(tmp); |
ac718b69 | 886 | data >>= (shift * 8); |
887 | data &= 0xff; | |
888 | ||
889 | return (u8)data; | |
890 | } | |
891 | ||
892 | static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) | |
893 | { | |
c8826de8 | 894 | u32 mask = 0xff; |
895 | __le32 tmp; | |
ac718b69 | 896 | u16 byen = BYTE_EN_BYTE; |
897 | u8 shift = index & 3; | |
898 | ||
899 | data &= mask; | |
900 | ||
901 | if (index & 3) { | |
902 | byen <<= shift; | |
903 | mask <<= (shift * 8); | |
904 | data <<= (shift * 8); | |
905 | index &= ~3; | |
906 | } | |
907 | ||
c8826de8 | 908 | tmp = __cpu_to_le32(data); |
ac718b69 | 909 | |
c8826de8 | 910 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 911 | } |
912 | ||
ac244d3e | 913 | static u16 ocp_reg_read(struct r8152 *tp, u16 addr) |
e3fe0b1a | 914 | { |
915 | u16 ocp_base, ocp_index; | |
916 | ||
917 | ocp_base = addr & 0xf000; | |
918 | if (ocp_base != tp->ocp_base) { | |
919 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
920 | tp->ocp_base = ocp_base; | |
921 | } | |
922 | ||
923 | ocp_index = (addr & 0x0fff) | 0xb000; | |
ac244d3e | 924 | return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); |
e3fe0b1a | 925 | } |
926 | ||
ac244d3e | 927 | static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) |
ac718b69 | 928 | { |
ac244d3e | 929 | u16 ocp_base, ocp_index; |
ac718b69 | 930 | |
ac244d3e | 931 | ocp_base = addr & 0xf000; |
932 | if (ocp_base != tp->ocp_base) { | |
933 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
934 | tp->ocp_base = ocp_base; | |
ac718b69 | 935 | } |
ac244d3e | 936 | |
937 | ocp_index = (addr & 0x0fff) | 0xb000; | |
938 | ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); | |
ac718b69 | 939 | } |
940 | ||
ac244d3e | 941 | static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) |
ac718b69 | 942 | { |
ac244d3e | 943 | ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); |
944 | } | |
ac718b69 | 945 | |
ac244d3e | 946 | static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) |
947 | { | |
948 | return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); | |
ac718b69 | 949 | } |
950 | ||
43779f8d | 951 | static void sram_write(struct r8152 *tp, u16 addr, u16 data) |
952 | { | |
953 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
954 | ocp_reg_write(tp, OCP_SRAM_DATA, data); | |
955 | } | |
956 | ||
ac718b69 | 957 | static int read_mii_word(struct net_device *netdev, int phy_id, int reg) |
958 | { | |
959 | struct r8152 *tp = netdev_priv(netdev); | |
9a4be1bd | 960 | int ret; |
ac718b69 | 961 | |
6871438c | 962 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
963 | return -ENODEV; | |
964 | ||
ac718b69 | 965 | if (phy_id != R8152_PHY_ID) |
966 | return -EINVAL; | |
967 | ||
9a4be1bd | 968 | ret = r8152_mdio_read(tp, reg); |
969 | ||
9a4be1bd | 970 | return ret; |
ac718b69 | 971 | } |
972 | ||
973 | static | |
974 | void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) | |
975 | { | |
976 | struct r8152 *tp = netdev_priv(netdev); | |
977 | ||
6871438c | 978 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
979 | return; | |
980 | ||
ac718b69 | 981 | if (phy_id != R8152_PHY_ID) |
982 | return; | |
983 | ||
984 | r8152_mdio_write(tp, reg, val); | |
985 | } | |
986 | ||
b209af99 | 987 | static int |
988 | r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); | |
ebc2ec48 | 989 | |
8ba789ab | 990 | static int rtl8152_set_mac_address(struct net_device *netdev, void *p) |
991 | { | |
992 | struct r8152 *tp = netdev_priv(netdev); | |
993 | struct sockaddr *addr = p; | |
ea6a7112 | 994 | int ret = -EADDRNOTAVAIL; |
8ba789ab | 995 | |
996 | if (!is_valid_ether_addr(addr->sa_data)) | |
ea6a7112 | 997 | goto out1; |
998 | ||
999 | ret = usb_autopm_get_interface(tp->intf); | |
1000 | if (ret < 0) | |
1001 | goto out1; | |
8ba789ab | 1002 | |
b5403273 | 1003 | mutex_lock(&tp->control); |
1004 | ||
8ba789ab | 1005 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); |
1006 | ||
1007 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
1008 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); | |
1009 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
1010 | ||
b5403273 | 1011 | mutex_unlock(&tp->control); |
1012 | ||
ea6a7112 | 1013 | usb_autopm_put_interface(tp->intf); |
1014 | out1: | |
1015 | return ret; | |
8ba789ab | 1016 | } |
1017 | ||
179bb6d7 | 1018 | static int set_ethernet_addr(struct r8152 *tp) |
ac718b69 | 1019 | { |
1020 | struct net_device *dev = tp->netdev; | |
179bb6d7 | 1021 | struct sockaddr sa; |
8a91c824 | 1022 | int ret; |
ac718b69 | 1023 | |
8a91c824 | 1024 | if (tp->version == RTL_VER_01) |
179bb6d7 | 1025 | ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data); |
8a91c824 | 1026 | else |
179bb6d7 | 1027 | ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data); |
8a91c824 | 1028 | |
1029 | if (ret < 0) { | |
179bb6d7 | 1030 | netif_err(tp, probe, dev, "Get ether addr fail\n"); |
1031 | } else if (!is_valid_ether_addr(sa.sa_data)) { | |
1032 | netif_err(tp, probe, dev, "Invalid ether addr %pM\n", | |
1033 | sa.sa_data); | |
1034 | eth_hw_addr_random(dev); | |
1035 | ether_addr_copy(sa.sa_data, dev->dev_addr); | |
1036 | ret = rtl8152_set_mac_address(dev, &sa); | |
1037 | netif_info(tp, probe, dev, "Random ether addr %pM\n", | |
1038 | sa.sa_data); | |
8a91c824 | 1039 | } else { |
179bb6d7 | 1040 | if (tp->version == RTL_VER_01) |
1041 | ether_addr_copy(dev->dev_addr, sa.sa_data); | |
1042 | else | |
1043 | ret = rtl8152_set_mac_address(dev, &sa); | |
ac718b69 | 1044 | } |
179bb6d7 | 1045 | |
1046 | return ret; | |
ac718b69 | 1047 | } |
1048 | ||
ac718b69 | 1049 | static void read_bulk_callback(struct urb *urb) |
1050 | { | |
ac718b69 | 1051 | struct net_device *netdev; |
ac718b69 | 1052 | int status = urb->status; |
ebc2ec48 | 1053 | struct rx_agg *agg; |
1054 | struct r8152 *tp; | |
ac718b69 | 1055 | |
ebc2ec48 | 1056 | agg = urb->context; |
1057 | if (!agg) | |
1058 | return; | |
1059 | ||
1060 | tp = agg->context; | |
ac718b69 | 1061 | if (!tp) |
1062 | return; | |
ebc2ec48 | 1063 | |
ac718b69 | 1064 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1065 | return; | |
ebc2ec48 | 1066 | |
1067 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1068 | return; | |
1069 | ||
ac718b69 | 1070 | netdev = tp->netdev; |
7559fb2f | 1071 | |
1072 | /* When link down, the driver would cancel all bulks. */ | |
1073 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1074 | if (!netif_carrier_ok(netdev)) |
ac718b69 | 1075 | return; |
1076 | ||
9a4be1bd | 1077 | usb_mark_last_busy(tp->udev); |
1078 | ||
ac718b69 | 1079 | switch (status) { |
1080 | case 0: | |
ebc2ec48 | 1081 | if (urb->actual_length < ETH_ZLEN) |
1082 | break; | |
1083 | ||
2685d410 | 1084 | spin_lock(&tp->rx_lock); |
ebc2ec48 | 1085 | list_add_tail(&agg->list, &tp->rx_done); |
2685d410 | 1086 | spin_unlock(&tp->rx_lock); |
d823ab68 | 1087 | napi_schedule(&tp->napi); |
ebc2ec48 | 1088 | return; |
ac718b69 | 1089 | case -ESHUTDOWN: |
1090 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
1091 | netif_device_detach(tp->netdev); | |
ebc2ec48 | 1092 | return; |
ac718b69 | 1093 | case -ENOENT: |
1094 | return; /* the urb is in unlink state */ | |
1095 | case -ETIME: | |
4a8deae2 HW |
1096 | if (net_ratelimit()) |
1097 | netdev_warn(netdev, "maybe reset is needed?\n"); | |
ebc2ec48 | 1098 | break; |
ac718b69 | 1099 | default: |
4a8deae2 HW |
1100 | if (net_ratelimit()) |
1101 | netdev_warn(netdev, "Rx status %d\n", status); | |
ebc2ec48 | 1102 | break; |
ac718b69 | 1103 | } |
1104 | ||
a0fccd48 | 1105 | r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ac718b69 | 1106 | } |
1107 | ||
ebc2ec48 | 1108 | static void write_bulk_callback(struct urb *urb) |
ac718b69 | 1109 | { |
ebc2ec48 | 1110 | struct net_device_stats *stats; |
d104eafa | 1111 | struct net_device *netdev; |
ebc2ec48 | 1112 | struct tx_agg *agg; |
ac718b69 | 1113 | struct r8152 *tp; |
ebc2ec48 | 1114 | int status = urb->status; |
ac718b69 | 1115 | |
ebc2ec48 | 1116 | agg = urb->context; |
1117 | if (!agg) | |
ac718b69 | 1118 | return; |
1119 | ||
ebc2ec48 | 1120 | tp = agg->context; |
1121 | if (!tp) | |
1122 | return; | |
1123 | ||
d104eafa | 1124 | netdev = tp->netdev; |
05e0f1aa | 1125 | stats = &netdev->stats; |
ebc2ec48 | 1126 | if (status) { |
4a8deae2 | 1127 | if (net_ratelimit()) |
d104eafa | 1128 | netdev_warn(netdev, "Tx status %d\n", status); |
ebc2ec48 | 1129 | stats->tx_errors += agg->skb_num; |
ac718b69 | 1130 | } else { |
ebc2ec48 | 1131 | stats->tx_packets += agg->skb_num; |
1132 | stats->tx_bytes += agg->skb_len; | |
ac718b69 | 1133 | } |
1134 | ||
2685d410 | 1135 | spin_lock(&tp->tx_lock); |
ebc2ec48 | 1136 | list_add_tail(&agg->list, &tp->tx_free); |
2685d410 | 1137 | spin_unlock(&tp->tx_lock); |
ebc2ec48 | 1138 | |
9a4be1bd | 1139 | usb_autopm_put_interface_async(tp->intf); |
1140 | ||
d104eafa | 1141 | if (!netif_carrier_ok(netdev)) |
ebc2ec48 | 1142 | return; |
1143 | ||
1144 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1145 | return; | |
1146 | ||
1147 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1148 | return; | |
1149 | ||
1150 | if (!skb_queue_empty(&tp->tx_queue)) | |
d823ab68 | 1151 | napi_schedule(&tp->napi); |
ac718b69 | 1152 | } |
1153 | ||
40a82917 | 1154 | static void intr_callback(struct urb *urb) |
1155 | { | |
1156 | struct r8152 *tp; | |
500b6d7e | 1157 | __le16 *d; |
40a82917 | 1158 | int status = urb->status; |
1159 | int res; | |
1160 | ||
1161 | tp = urb->context; | |
1162 | if (!tp) | |
1163 | return; | |
1164 | ||
1165 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1166 | return; | |
1167 | ||
1168 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1169 | return; | |
1170 | ||
1171 | switch (status) { | |
1172 | case 0: /* success */ | |
1173 | break; | |
1174 | case -ECONNRESET: /* unlink */ | |
1175 | case -ESHUTDOWN: | |
1176 | netif_device_detach(tp->netdev); | |
1177 | case -ENOENT: | |
d59c876d | 1178 | case -EPROTO: |
1179 | netif_info(tp, intr, tp->netdev, | |
1180 | "Stop submitting intr, status %d\n", status); | |
40a82917 | 1181 | return; |
1182 | case -EOVERFLOW: | |
1183 | netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); | |
1184 | goto resubmit; | |
1185 | /* -EPIPE: should clear the halt */ | |
1186 | default: | |
1187 | netif_info(tp, intr, tp->netdev, "intr status %d\n", status); | |
1188 | goto resubmit; | |
1189 | } | |
1190 | ||
1191 | d = urb->transfer_buffer; | |
1192 | if (INTR_LINK & __le16_to_cpu(d[0])) { | |
51d979fa | 1193 | if (!netif_carrier_ok(tp->netdev)) { |
40a82917 | 1194 | set_bit(RTL8152_LINK_CHG, &tp->flags); |
1195 | schedule_delayed_work(&tp->schedule, 0); | |
1196 | } | |
1197 | } else { | |
51d979fa | 1198 | if (netif_carrier_ok(tp->netdev)) { |
40a82917 | 1199 | set_bit(RTL8152_LINK_CHG, &tp->flags); |
1200 | schedule_delayed_work(&tp->schedule, 0); | |
1201 | } | |
1202 | } | |
1203 | ||
1204 | resubmit: | |
1205 | res = usb_submit_urb(urb, GFP_ATOMIC); | |
67610496 | 1206 | if (res == -ENODEV) { |
1207 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
40a82917 | 1208 | netif_device_detach(tp->netdev); |
67610496 | 1209 | } else if (res) { |
40a82917 | 1210 | netif_err(tp, intr, tp->netdev, |
4a8deae2 | 1211 | "can't resubmit intr, status %d\n", res); |
67610496 | 1212 | } |
40a82917 | 1213 | } |
1214 | ||
ebc2ec48 | 1215 | static inline void *rx_agg_align(void *data) |
1216 | { | |
8e1f51bd | 1217 | return (void *)ALIGN((uintptr_t)data, RX_ALIGN); |
ebc2ec48 | 1218 | } |
1219 | ||
1220 | static inline void *tx_agg_align(void *data) | |
1221 | { | |
8e1f51bd | 1222 | return (void *)ALIGN((uintptr_t)data, TX_ALIGN); |
ebc2ec48 | 1223 | } |
1224 | ||
1225 | static void free_all_mem(struct r8152 *tp) | |
1226 | { | |
1227 | int i; | |
1228 | ||
1229 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
9629e3c0 | 1230 | usb_free_urb(tp->rx_info[i].urb); |
1231 | tp->rx_info[i].urb = NULL; | |
ebc2ec48 | 1232 | |
9629e3c0 | 1233 | kfree(tp->rx_info[i].buffer); |
1234 | tp->rx_info[i].buffer = NULL; | |
1235 | tp->rx_info[i].head = NULL; | |
ebc2ec48 | 1236 | } |
1237 | ||
1238 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
9629e3c0 | 1239 | usb_free_urb(tp->tx_info[i].urb); |
1240 | tp->tx_info[i].urb = NULL; | |
ebc2ec48 | 1241 | |
9629e3c0 | 1242 | kfree(tp->tx_info[i].buffer); |
1243 | tp->tx_info[i].buffer = NULL; | |
1244 | tp->tx_info[i].head = NULL; | |
ebc2ec48 | 1245 | } |
40a82917 | 1246 | |
9629e3c0 | 1247 | usb_free_urb(tp->intr_urb); |
1248 | tp->intr_urb = NULL; | |
40a82917 | 1249 | |
9629e3c0 | 1250 | kfree(tp->intr_buff); |
1251 | tp->intr_buff = NULL; | |
ebc2ec48 | 1252 | } |
1253 | ||
1254 | static int alloc_all_mem(struct r8152 *tp) | |
1255 | { | |
1256 | struct net_device *netdev = tp->netdev; | |
40a82917 | 1257 | struct usb_interface *intf = tp->intf; |
1258 | struct usb_host_interface *alt = intf->cur_altsetting; | |
1259 | struct usb_host_endpoint *ep_intr = alt->endpoint + 2; | |
ebc2ec48 | 1260 | struct urb *urb; |
1261 | int node, i; | |
1262 | u8 *buf; | |
1263 | ||
1264 | node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; | |
1265 | ||
1266 | spin_lock_init(&tp->rx_lock); | |
1267 | spin_lock_init(&tp->tx_lock); | |
ebc2ec48 | 1268 | INIT_LIST_HEAD(&tp->tx_free); |
1269 | skb_queue_head_init(&tp->tx_queue); | |
d823ab68 | 1270 | skb_queue_head_init(&tp->rx_queue); |
ebc2ec48 | 1271 | |
1272 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
52aec126 | 1273 | buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); |
ebc2ec48 | 1274 | if (!buf) |
1275 | goto err1; | |
1276 | ||
1277 | if (buf != rx_agg_align(buf)) { | |
1278 | kfree(buf); | |
52aec126 | 1279 | buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, |
8e1f51bd | 1280 | node); |
ebc2ec48 | 1281 | if (!buf) |
1282 | goto err1; | |
1283 | } | |
1284 | ||
1285 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1286 | if (!urb) { | |
1287 | kfree(buf); | |
1288 | goto err1; | |
1289 | } | |
1290 | ||
1291 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1292 | tp->rx_info[i].context = tp; | |
1293 | tp->rx_info[i].urb = urb; | |
1294 | tp->rx_info[i].buffer = buf; | |
1295 | tp->rx_info[i].head = rx_agg_align(buf); | |
1296 | } | |
1297 | ||
1298 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
52aec126 | 1299 | buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); |
ebc2ec48 | 1300 | if (!buf) |
1301 | goto err1; | |
1302 | ||
1303 | if (buf != tx_agg_align(buf)) { | |
1304 | kfree(buf); | |
52aec126 | 1305 | buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, |
8e1f51bd | 1306 | node); |
ebc2ec48 | 1307 | if (!buf) |
1308 | goto err1; | |
1309 | } | |
1310 | ||
1311 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1312 | if (!urb) { | |
1313 | kfree(buf); | |
1314 | goto err1; | |
1315 | } | |
1316 | ||
1317 | INIT_LIST_HEAD(&tp->tx_info[i].list); | |
1318 | tp->tx_info[i].context = tp; | |
1319 | tp->tx_info[i].urb = urb; | |
1320 | tp->tx_info[i].buffer = buf; | |
1321 | tp->tx_info[i].head = tx_agg_align(buf); | |
1322 | ||
1323 | list_add_tail(&tp->tx_info[i].list, &tp->tx_free); | |
1324 | } | |
1325 | ||
40a82917 | 1326 | tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); |
1327 | if (!tp->intr_urb) | |
1328 | goto err1; | |
1329 | ||
1330 | tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); | |
1331 | if (!tp->intr_buff) | |
1332 | goto err1; | |
1333 | ||
1334 | tp->intr_interval = (int)ep_intr->desc.bInterval; | |
1335 | usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), | |
b209af99 | 1336 | tp->intr_buff, INTBUFSIZE, intr_callback, |
1337 | tp, tp->intr_interval); | |
40a82917 | 1338 | |
ebc2ec48 | 1339 | return 0; |
1340 | ||
1341 | err1: | |
1342 | free_all_mem(tp); | |
1343 | return -ENOMEM; | |
1344 | } | |
1345 | ||
0de98f6c | 1346 | static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) |
1347 | { | |
1348 | struct tx_agg *agg = NULL; | |
1349 | unsigned long flags; | |
1350 | ||
21949ab7 | 1351 | if (list_empty(&tp->tx_free)) |
1352 | return NULL; | |
1353 | ||
0de98f6c | 1354 | spin_lock_irqsave(&tp->tx_lock, flags); |
1355 | if (!list_empty(&tp->tx_free)) { | |
1356 | struct list_head *cursor; | |
1357 | ||
1358 | cursor = tp->tx_free.next; | |
1359 | list_del_init(cursor); | |
1360 | agg = list_entry(cursor, struct tx_agg, list); | |
1361 | } | |
1362 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1363 | ||
1364 | return agg; | |
1365 | } | |
1366 | ||
b209af99 | 1367 | /* r8152_csum_workaround() |
6128d1bb | 1368 | * The hw limites the value the transport offset. When the offset is out of the |
1369 | * range, calculate the checksum by sw. | |
1370 | */ | |
1371 | static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, | |
1372 | struct sk_buff_head *list) | |
1373 | { | |
1374 | if (skb_shinfo(skb)->gso_size) { | |
1375 | netdev_features_t features = tp->netdev->features; | |
1376 | struct sk_buff_head seg_list; | |
1377 | struct sk_buff *segs, *nskb; | |
1378 | ||
a91d45f1 | 1379 | features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); |
6128d1bb | 1380 | segs = skb_gso_segment(skb, features); |
1381 | if (IS_ERR(segs) || !segs) | |
1382 | goto drop; | |
1383 | ||
1384 | __skb_queue_head_init(&seg_list); | |
1385 | ||
1386 | do { | |
1387 | nskb = segs; | |
1388 | segs = segs->next; | |
1389 | nskb->next = NULL; | |
1390 | __skb_queue_tail(&seg_list, nskb); | |
1391 | } while (segs); | |
1392 | ||
1393 | skb_queue_splice(&seg_list, list); | |
1394 | dev_kfree_skb(skb); | |
1395 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1396 | if (skb_checksum_help(skb) < 0) | |
1397 | goto drop; | |
1398 | ||
1399 | __skb_queue_head(list, skb); | |
1400 | } else { | |
1401 | struct net_device_stats *stats; | |
1402 | ||
1403 | drop: | |
1404 | stats = &tp->netdev->stats; | |
1405 | stats->tx_dropped++; | |
1406 | dev_kfree_skb(skb); | |
1407 | } | |
1408 | } | |
1409 | ||
b209af99 | 1410 | /* msdn_giant_send_check() |
6128d1bb | 1411 | * According to the document of microsoft, the TCP Pseudo Header excludes the |
1412 | * packet length for IPv6 TCP large packets. | |
1413 | */ | |
1414 | static int msdn_giant_send_check(struct sk_buff *skb) | |
1415 | { | |
1416 | const struct ipv6hdr *ipv6h; | |
1417 | struct tcphdr *th; | |
fcb308d5 | 1418 | int ret; |
1419 | ||
1420 | ret = skb_cow_head(skb, 0); | |
1421 | if (ret) | |
1422 | return ret; | |
6128d1bb | 1423 | |
1424 | ipv6h = ipv6_hdr(skb); | |
1425 | th = tcp_hdr(skb); | |
1426 | ||
1427 | th->check = 0; | |
1428 | th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); | |
1429 | ||
fcb308d5 | 1430 | return ret; |
6128d1bb | 1431 | } |
1432 | ||
c5554298 | 1433 | static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) |
1434 | { | |
df8a39de | 1435 | if (skb_vlan_tag_present(skb)) { |
c5554298 | 1436 | u32 opts2; |
1437 | ||
df8a39de | 1438 | opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); |
c5554298 | 1439 | desc->opts2 |= cpu_to_le32(opts2); |
1440 | } | |
1441 | } | |
1442 | ||
1443 | static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) | |
1444 | { | |
1445 | u32 opts2 = le32_to_cpu(desc->opts2); | |
1446 | ||
1447 | if (opts2 & RX_VLAN_TAG) | |
1448 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), | |
1449 | swab16(opts2 & 0xffff)); | |
1450 | } | |
1451 | ||
60c89071 | 1452 | static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, |
1453 | struct sk_buff *skb, u32 len, u32 transport_offset) | |
1454 | { | |
1455 | u32 mss = skb_shinfo(skb)->gso_size; | |
1456 | u32 opts1, opts2 = 0; | |
1457 | int ret = TX_CSUM_SUCCESS; | |
1458 | ||
1459 | WARN_ON_ONCE(len > TX_LEN_MAX); | |
1460 | ||
1461 | opts1 = len | TX_FS | TX_LS; | |
1462 | ||
1463 | if (mss) { | |
6128d1bb | 1464 | if (transport_offset > GTTCPHO_MAX) { |
1465 | netif_warn(tp, tx_err, tp->netdev, | |
1466 | "Invalid transport offset 0x%x for TSO\n", | |
1467 | transport_offset); | |
1468 | ret = TX_CSUM_TSO; | |
1469 | goto unavailable; | |
1470 | } | |
1471 | ||
6e74d174 | 1472 | switch (vlan_get_protocol(skb)) { |
60c89071 | 1473 | case htons(ETH_P_IP): |
1474 | opts1 |= GTSENDV4; | |
1475 | break; | |
1476 | ||
6128d1bb | 1477 | case htons(ETH_P_IPV6): |
fcb308d5 | 1478 | if (msdn_giant_send_check(skb)) { |
1479 | ret = TX_CSUM_TSO; | |
1480 | goto unavailable; | |
1481 | } | |
6128d1bb | 1482 | opts1 |= GTSENDV6; |
6128d1bb | 1483 | break; |
1484 | ||
60c89071 | 1485 | default: |
1486 | WARN_ON_ONCE(1); | |
1487 | break; | |
1488 | } | |
1489 | ||
1490 | opts1 |= transport_offset << GTTCPHO_SHIFT; | |
1491 | opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; | |
1492 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1493 | u8 ip_protocol; | |
5bd23881 | 1494 | |
6128d1bb | 1495 | if (transport_offset > TCPHO_MAX) { |
1496 | netif_warn(tp, tx_err, tp->netdev, | |
1497 | "Invalid transport offset 0x%x\n", | |
1498 | transport_offset); | |
1499 | ret = TX_CSUM_NONE; | |
1500 | goto unavailable; | |
1501 | } | |
1502 | ||
6e74d174 | 1503 | switch (vlan_get_protocol(skb)) { |
5bd23881 | 1504 | case htons(ETH_P_IP): |
1505 | opts2 |= IPV4_CS; | |
1506 | ip_protocol = ip_hdr(skb)->protocol; | |
1507 | break; | |
1508 | ||
1509 | case htons(ETH_P_IPV6): | |
1510 | opts2 |= IPV6_CS; | |
1511 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
1512 | break; | |
1513 | ||
1514 | default: | |
1515 | ip_protocol = IPPROTO_RAW; | |
1516 | break; | |
1517 | } | |
1518 | ||
60c89071 | 1519 | if (ip_protocol == IPPROTO_TCP) |
5bd23881 | 1520 | opts2 |= TCP_CS; |
60c89071 | 1521 | else if (ip_protocol == IPPROTO_UDP) |
5bd23881 | 1522 | opts2 |= UDP_CS; |
60c89071 | 1523 | else |
5bd23881 | 1524 | WARN_ON_ONCE(1); |
5bd23881 | 1525 | |
60c89071 | 1526 | opts2 |= transport_offset << TCPHO_SHIFT; |
5bd23881 | 1527 | } |
60c89071 | 1528 | |
1529 | desc->opts2 = cpu_to_le32(opts2); | |
1530 | desc->opts1 = cpu_to_le32(opts1); | |
1531 | ||
6128d1bb | 1532 | unavailable: |
60c89071 | 1533 | return ret; |
5bd23881 | 1534 | } |
1535 | ||
b1379d9a | 1536 | static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) |
1537 | { | |
d84130a1 | 1538 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
9a4be1bd | 1539 | int remain, ret; |
b1379d9a | 1540 | u8 *tx_data; |
1541 | ||
d84130a1 | 1542 | __skb_queue_head_init(&skb_head); |
0c3121fc | 1543 | spin_lock(&tx_queue->lock); |
d84130a1 | 1544 | skb_queue_splice_init(tx_queue, &skb_head); |
0c3121fc | 1545 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1546 | |
b1379d9a | 1547 | tx_data = agg->head; |
b209af99 | 1548 | agg->skb_num = 0; |
1549 | agg->skb_len = 0; | |
52aec126 | 1550 | remain = agg_buf_sz; |
b1379d9a | 1551 | |
7937f9e5 | 1552 | while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { |
b1379d9a | 1553 | struct tx_desc *tx_desc; |
1554 | struct sk_buff *skb; | |
1555 | unsigned int len; | |
60c89071 | 1556 | u32 offset; |
b1379d9a | 1557 | |
d84130a1 | 1558 | skb = __skb_dequeue(&skb_head); |
b1379d9a | 1559 | if (!skb) |
1560 | break; | |
1561 | ||
60c89071 | 1562 | len = skb->len + sizeof(*tx_desc); |
1563 | ||
1564 | if (len > remain) { | |
d84130a1 | 1565 | __skb_queue_head(&skb_head, skb); |
b1379d9a | 1566 | break; |
1567 | } | |
1568 | ||
7937f9e5 | 1569 | tx_data = tx_agg_align(tx_data); |
b1379d9a | 1570 | tx_desc = (struct tx_desc *)tx_data; |
60c89071 | 1571 | |
1572 | offset = (u32)skb_transport_offset(skb); | |
1573 | ||
6128d1bb | 1574 | if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { |
1575 | r8152_csum_workaround(tp, skb, &skb_head); | |
1576 | continue; | |
1577 | } | |
60c89071 | 1578 | |
c5554298 | 1579 | rtl_tx_vlan_tag(tx_desc, skb); |
1580 | ||
b1379d9a | 1581 | tx_data += sizeof(*tx_desc); |
1582 | ||
60c89071 | 1583 | len = skb->len; |
1584 | if (skb_copy_bits(skb, 0, tx_data, len) < 0) { | |
1585 | struct net_device_stats *stats = &tp->netdev->stats; | |
1586 | ||
1587 | stats->tx_dropped++; | |
1588 | dev_kfree_skb_any(skb); | |
1589 | tx_data -= sizeof(*tx_desc); | |
1590 | continue; | |
1591 | } | |
1592 | ||
1593 | tx_data += len; | |
b1379d9a | 1594 | agg->skb_len += len; |
60c89071 | 1595 | agg->skb_num++; |
1596 | ||
b1379d9a | 1597 | dev_kfree_skb_any(skb); |
1598 | ||
52aec126 | 1599 | remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); |
b1379d9a | 1600 | } |
1601 | ||
d84130a1 | 1602 | if (!skb_queue_empty(&skb_head)) { |
0c3121fc | 1603 | spin_lock(&tx_queue->lock); |
d84130a1 | 1604 | skb_queue_splice(&skb_head, tx_queue); |
0c3121fc | 1605 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1606 | } |
1607 | ||
0c3121fc | 1608 | netif_tx_lock(tp->netdev); |
dd1b119c | 1609 | |
1610 | if (netif_queue_stopped(tp->netdev) && | |
1611 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) | |
1612 | netif_wake_queue(tp->netdev); | |
1613 | ||
0c3121fc | 1614 | netif_tx_unlock(tp->netdev); |
9a4be1bd | 1615 | |
0c3121fc | 1616 | ret = usb_autopm_get_interface_async(tp->intf); |
9a4be1bd | 1617 | if (ret < 0) |
1618 | goto out_tx_fill; | |
dd1b119c | 1619 | |
b1379d9a | 1620 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), |
1621 | agg->head, (int)(tx_data - (u8 *)agg->head), | |
1622 | (usb_complete_t)write_bulk_callback, agg); | |
1623 | ||
0c3121fc | 1624 | ret = usb_submit_urb(agg->urb, GFP_ATOMIC); |
9a4be1bd | 1625 | if (ret < 0) |
0c3121fc | 1626 | usb_autopm_put_interface_async(tp->intf); |
9a4be1bd | 1627 | |
1628 | out_tx_fill: | |
1629 | return ret; | |
b1379d9a | 1630 | } |
1631 | ||
565cab0a | 1632 | static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) |
1633 | { | |
1634 | u8 checksum = CHECKSUM_NONE; | |
1635 | u32 opts2, opts3; | |
1636 | ||
1637 | if (tp->version == RTL_VER_01) | |
1638 | goto return_result; | |
1639 | ||
1640 | opts2 = le32_to_cpu(rx_desc->opts2); | |
1641 | opts3 = le32_to_cpu(rx_desc->opts3); | |
1642 | ||
1643 | if (opts2 & RD_IPV4_CS) { | |
1644 | if (opts3 & IPF) | |
1645 | checksum = CHECKSUM_NONE; | |
1646 | else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) | |
1647 | checksum = CHECKSUM_NONE; | |
1648 | else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) | |
1649 | checksum = CHECKSUM_NONE; | |
1650 | else | |
1651 | checksum = CHECKSUM_UNNECESSARY; | |
6128d1bb | 1652 | } else if (RD_IPV6_CS) { |
1653 | if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) | |
1654 | checksum = CHECKSUM_UNNECESSARY; | |
1655 | else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) | |
1656 | checksum = CHECKSUM_UNNECESSARY; | |
565cab0a | 1657 | } |
1658 | ||
1659 | return_result: | |
1660 | return checksum; | |
1661 | } | |
1662 | ||
d823ab68 | 1663 | static int rx_bottom(struct r8152 *tp, int budget) |
ebc2ec48 | 1664 | { |
a5a4f468 | 1665 | unsigned long flags; |
d84130a1 | 1666 | struct list_head *cursor, *next, rx_queue; |
e1a2ca92 | 1667 | int ret = 0, work_done = 0; |
d823ab68 | 1668 | |
1669 | if (!skb_queue_empty(&tp->rx_queue)) { | |
1670 | while (work_done < budget) { | |
1671 | struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); | |
1672 | struct net_device *netdev = tp->netdev; | |
1673 | struct net_device_stats *stats = &netdev->stats; | |
1674 | unsigned int pkt_len; | |
1675 | ||
1676 | if (!skb) | |
1677 | break; | |
1678 | ||
1679 | pkt_len = skb->len; | |
1680 | napi_gro_receive(&tp->napi, skb); | |
1681 | work_done++; | |
1682 | stats->rx_packets++; | |
1683 | stats->rx_bytes += pkt_len; | |
1684 | } | |
1685 | } | |
ebc2ec48 | 1686 | |
d84130a1 | 1687 | if (list_empty(&tp->rx_done)) |
d823ab68 | 1688 | goto out1; |
d84130a1 | 1689 | |
1690 | INIT_LIST_HEAD(&rx_queue); | |
a5a4f468 | 1691 | spin_lock_irqsave(&tp->rx_lock, flags); |
d84130a1 | 1692 | list_splice_init(&tp->rx_done, &rx_queue); |
1693 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
1694 | ||
1695 | list_for_each_safe(cursor, next, &rx_queue) { | |
43a4478d | 1696 | struct rx_desc *rx_desc; |
1697 | struct rx_agg *agg; | |
43a4478d | 1698 | int len_used = 0; |
1699 | struct urb *urb; | |
1700 | u8 *rx_data; | |
43a4478d | 1701 | |
ebc2ec48 | 1702 | list_del_init(cursor); |
ebc2ec48 | 1703 | |
1704 | agg = list_entry(cursor, struct rx_agg, list); | |
1705 | urb = agg->urb; | |
0de98f6c | 1706 | if (urb->actual_length < ETH_ZLEN) |
1707 | goto submit; | |
ebc2ec48 | 1708 | |
ebc2ec48 | 1709 | rx_desc = agg->head; |
1710 | rx_data = agg->head; | |
7937f9e5 | 1711 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1712 | |
7937f9e5 | 1713 | while (urb->actual_length > len_used) { |
43a4478d | 1714 | struct net_device *netdev = tp->netdev; |
05e0f1aa | 1715 | struct net_device_stats *stats = &netdev->stats; |
7937f9e5 | 1716 | unsigned int pkt_len; |
43a4478d | 1717 | struct sk_buff *skb; |
1718 | ||
7937f9e5 | 1719 | pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; |
ebc2ec48 | 1720 | if (pkt_len < ETH_ZLEN) |
1721 | break; | |
1722 | ||
7937f9e5 | 1723 | len_used += pkt_len; |
1724 | if (urb->actual_length < len_used) | |
1725 | break; | |
1726 | ||
8e1f51bd | 1727 | pkt_len -= CRC_SIZE; |
ebc2ec48 | 1728 | rx_data += sizeof(struct rx_desc); |
1729 | ||
1730 | skb = netdev_alloc_skb_ip_align(netdev, pkt_len); | |
1731 | if (!skb) { | |
1732 | stats->rx_dropped++; | |
5e2f7485 | 1733 | goto find_next_rx; |
ebc2ec48 | 1734 | } |
565cab0a | 1735 | |
1736 | skb->ip_summed = r8152_rx_csum(tp, rx_desc); | |
ebc2ec48 | 1737 | memcpy(skb->data, rx_data, pkt_len); |
1738 | skb_put(skb, pkt_len); | |
1739 | skb->protocol = eth_type_trans(skb, netdev); | |
c5554298 | 1740 | rtl_rx_vlan_tag(rx_desc, skb); |
d823ab68 | 1741 | if (work_done < budget) { |
1742 | napi_gro_receive(&tp->napi, skb); | |
1743 | work_done++; | |
1744 | stats->rx_packets++; | |
1745 | stats->rx_bytes += pkt_len; | |
1746 | } else { | |
1747 | __skb_queue_tail(&tp->rx_queue, skb); | |
1748 | } | |
ebc2ec48 | 1749 | |
5e2f7485 | 1750 | find_next_rx: |
8e1f51bd | 1751 | rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); |
ebc2ec48 | 1752 | rx_desc = (struct rx_desc *)rx_data; |
ebc2ec48 | 1753 | len_used = (int)(rx_data - (u8 *)agg->head); |
7937f9e5 | 1754 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1755 | } |
1756 | ||
0de98f6c | 1757 | submit: |
e1a2ca92 | 1758 | if (!ret) { |
1759 | ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); | |
1760 | } else { | |
1761 | urb->actual_length = 0; | |
1762 | list_add_tail(&agg->list, next); | |
1763 | } | |
1764 | } | |
1765 | ||
1766 | if (!list_empty(&rx_queue)) { | |
1767 | spin_lock_irqsave(&tp->rx_lock, flags); | |
1768 | list_splice_tail(&rx_queue, &tp->rx_done); | |
1769 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
ebc2ec48 | 1770 | } |
d823ab68 | 1771 | |
1772 | out1: | |
1773 | return work_done; | |
ebc2ec48 | 1774 | } |
1775 | ||
1776 | static void tx_bottom(struct r8152 *tp) | |
1777 | { | |
ebc2ec48 | 1778 | int res; |
1779 | ||
b1379d9a | 1780 | do { |
1781 | struct tx_agg *agg; | |
ebc2ec48 | 1782 | |
b1379d9a | 1783 | if (skb_queue_empty(&tp->tx_queue)) |
ebc2ec48 | 1784 | break; |
1785 | ||
b1379d9a | 1786 | agg = r8152_get_tx_agg(tp); |
1787 | if (!agg) | |
ebc2ec48 | 1788 | break; |
ebc2ec48 | 1789 | |
b1379d9a | 1790 | res = r8152_tx_agg_fill(tp, agg); |
1791 | if (res) { | |
05e0f1aa | 1792 | struct net_device *netdev = tp->netdev; |
ebc2ec48 | 1793 | |
b1379d9a | 1794 | if (res == -ENODEV) { |
67610496 | 1795 | set_bit(RTL8152_UNPLUG, &tp->flags); |
b1379d9a | 1796 | netif_device_detach(netdev); |
1797 | } else { | |
05e0f1aa | 1798 | struct net_device_stats *stats = &netdev->stats; |
1799 | unsigned long flags; | |
1800 | ||
b1379d9a | 1801 | netif_warn(tp, tx_err, netdev, |
1802 | "failed tx_urb %d\n", res); | |
1803 | stats->tx_dropped += agg->skb_num; | |
db8515ef | 1804 | |
b1379d9a | 1805 | spin_lock_irqsave(&tp->tx_lock, flags); |
1806 | list_add_tail(&agg->list, &tp->tx_free); | |
1807 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1808 | } | |
ebc2ec48 | 1809 | } |
b1379d9a | 1810 | } while (res == 0); |
ebc2ec48 | 1811 | } |
1812 | ||
d823ab68 | 1813 | static void bottom_half(struct r8152 *tp) |
ac718b69 | 1814 | { |
ebc2ec48 | 1815 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1816 | return; | |
1817 | ||
1818 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
ac718b69 | 1819 | return; |
ebc2ec48 | 1820 | |
7559fb2f | 1821 | /* When link down, the driver would cancel all bulks. */ |
1822 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1823 | if (!netif_carrier_ok(tp->netdev)) |
ac718b69 | 1824 | return; |
ebc2ec48 | 1825 | |
d823ab68 | 1826 | clear_bit(SCHEDULE_NAPI, &tp->flags); |
9451a11c | 1827 | |
0c3121fc | 1828 | tx_bottom(tp); |
ebc2ec48 | 1829 | } |
1830 | ||
d823ab68 | 1831 | static int r8152_poll(struct napi_struct *napi, int budget) |
1832 | { | |
1833 | struct r8152 *tp = container_of(napi, struct r8152, napi); | |
1834 | int work_done; | |
1835 | ||
1836 | work_done = rx_bottom(tp, budget); | |
1837 | bottom_half(tp); | |
1838 | ||
1839 | if (work_done < budget) { | |
1840 | napi_complete(napi); | |
1841 | if (!list_empty(&tp->rx_done)) | |
1842 | napi_schedule(napi); | |
1843 | } | |
1844 | ||
1845 | return work_done; | |
1846 | } | |
1847 | ||
ebc2ec48 | 1848 | static |
1849 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) | |
1850 | { | |
a0fccd48 | 1851 | int ret; |
1852 | ||
ef827a5b | 1853 | /* The rx would be stopped, so skip submitting */ |
1854 | if (test_bit(RTL8152_UNPLUG, &tp->flags) || | |
1855 | !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) | |
1856 | return 0; | |
1857 | ||
ebc2ec48 | 1858 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), |
52aec126 | 1859 | agg->head, agg_buf_sz, |
b209af99 | 1860 | (usb_complete_t)read_bulk_callback, agg); |
ebc2ec48 | 1861 | |
a0fccd48 | 1862 | ret = usb_submit_urb(agg->urb, mem_flags); |
1863 | if (ret == -ENODEV) { | |
1864 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
1865 | netif_device_detach(tp->netdev); | |
1866 | } else if (ret) { | |
1867 | struct urb *urb = agg->urb; | |
1868 | unsigned long flags; | |
1869 | ||
1870 | urb->actual_length = 0; | |
1871 | spin_lock_irqsave(&tp->rx_lock, flags); | |
1872 | list_add_tail(&agg->list, &tp->rx_done); | |
1873 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
d823ab68 | 1874 | |
1875 | netif_err(tp, rx_err, tp->netdev, | |
1876 | "Couldn't submit rx[%p], ret = %d\n", agg, ret); | |
1877 | ||
1878 | napi_schedule(&tp->napi); | |
a0fccd48 | 1879 | } |
1880 | ||
1881 | return ret; | |
ac718b69 | 1882 | } |
1883 | ||
00a5e360 | 1884 | static void rtl_drop_queued_tx(struct r8152 *tp) |
1885 | { | |
1886 | struct net_device_stats *stats = &tp->netdev->stats; | |
d84130a1 | 1887 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
00a5e360 | 1888 | struct sk_buff *skb; |
1889 | ||
d84130a1 | 1890 | if (skb_queue_empty(tx_queue)) |
1891 | return; | |
1892 | ||
1893 | __skb_queue_head_init(&skb_head); | |
2685d410 | 1894 | spin_lock_bh(&tx_queue->lock); |
d84130a1 | 1895 | skb_queue_splice_init(tx_queue, &skb_head); |
2685d410 | 1896 | spin_unlock_bh(&tx_queue->lock); |
d84130a1 | 1897 | |
1898 | while ((skb = __skb_dequeue(&skb_head))) { | |
00a5e360 | 1899 | dev_kfree_skb(skb); |
1900 | stats->tx_dropped++; | |
1901 | } | |
1902 | } | |
1903 | ||
ac718b69 | 1904 | static void rtl8152_tx_timeout(struct net_device *netdev) |
1905 | { | |
1906 | struct r8152 *tp = netdev_priv(netdev); | |
ebc2ec48 | 1907 | |
4a8deae2 | 1908 | netif_warn(tp, tx_err, netdev, "Tx timeout\n"); |
37608f3e | 1909 | |
1910 | usb_queue_reset_device(tp->intf); | |
ac718b69 | 1911 | } |
1912 | ||
1913 | static void rtl8152_set_rx_mode(struct net_device *netdev) | |
1914 | { | |
1915 | struct r8152 *tp = netdev_priv(netdev); | |
1916 | ||
51d979fa | 1917 | if (netif_carrier_ok(netdev)) { |
ac718b69 | 1918 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
40a82917 | 1919 | schedule_delayed_work(&tp->schedule, 0); |
1920 | } | |
ac718b69 | 1921 | } |
1922 | ||
1923 | static void _rtl8152_set_rx_mode(struct net_device *netdev) | |
1924 | { | |
1925 | struct r8152 *tp = netdev_priv(netdev); | |
31787f53 | 1926 | u32 mc_filter[2]; /* Multicast hash filter */ |
1927 | __le32 tmp[2]; | |
ac718b69 | 1928 | u32 ocp_data; |
1929 | ||
ac718b69 | 1930 | clear_bit(RTL8152_SET_RX_MODE, &tp->flags); |
1931 | netif_stop_queue(netdev); | |
1932 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1933 | ocp_data &= ~RCR_ACPT_ALL; | |
1934 | ocp_data |= RCR_AB | RCR_APM; | |
1935 | ||
1936 | if (netdev->flags & IFF_PROMISC) { | |
1937 | /* Unconditionally log net taps. */ | |
1938 | netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); | |
1939 | ocp_data |= RCR_AM | RCR_AAP; | |
b209af99 | 1940 | mc_filter[1] = 0xffffffff; |
1941 | mc_filter[0] = 0xffffffff; | |
ac718b69 | 1942 | } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || |
1943 | (netdev->flags & IFF_ALLMULTI)) { | |
1944 | /* Too many to filter perfectly -- accept all multicasts. */ | |
1945 | ocp_data |= RCR_AM; | |
b209af99 | 1946 | mc_filter[1] = 0xffffffff; |
1947 | mc_filter[0] = 0xffffffff; | |
ac718b69 | 1948 | } else { |
1949 | struct netdev_hw_addr *ha; | |
1950 | ||
b209af99 | 1951 | mc_filter[1] = 0; |
1952 | mc_filter[0] = 0; | |
ac718b69 | 1953 | netdev_for_each_mc_addr(ha, netdev) { |
1954 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
b209af99 | 1955 | |
ac718b69 | 1956 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
1957 | ocp_data |= RCR_AM; | |
1958 | } | |
1959 | } | |
1960 | ||
31787f53 | 1961 | tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); |
1962 | tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); | |
ac718b69 | 1963 | |
31787f53 | 1964 | pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); |
ac718b69 | 1965 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
1966 | netif_wake_queue(netdev); | |
ac718b69 | 1967 | } |
1968 | ||
a5e31255 | 1969 | static netdev_features_t |
1970 | rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, | |
1971 | netdev_features_t features) | |
1972 | { | |
1973 | u32 mss = skb_shinfo(skb)->gso_size; | |
1974 | int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; | |
1975 | int offset = skb_transport_offset(skb); | |
1976 | ||
1977 | if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) | |
1978 | features &= ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK); | |
1979 | else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) | |
1980 | features &= ~NETIF_F_GSO_MASK; | |
1981 | ||
1982 | return features; | |
1983 | } | |
1984 | ||
ac718b69 | 1985 | static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, |
b209af99 | 1986 | struct net_device *netdev) |
ac718b69 | 1987 | { |
1988 | struct r8152 *tp = netdev_priv(netdev); | |
ac718b69 | 1989 | |
ebc2ec48 | 1990 | skb_tx_timestamp(skb); |
ac718b69 | 1991 | |
61598788 | 1992 | skb_queue_tail(&tp->tx_queue, skb); |
ebc2ec48 | 1993 | |
0c3121fc | 1994 | if (!list_empty(&tp->tx_free)) { |
1995 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { | |
d823ab68 | 1996 | set_bit(SCHEDULE_NAPI, &tp->flags); |
0c3121fc | 1997 | schedule_delayed_work(&tp->schedule, 0); |
1998 | } else { | |
1999 | usb_mark_last_busy(tp->udev); | |
d823ab68 | 2000 | napi_schedule(&tp->napi); |
0c3121fc | 2001 | } |
b209af99 | 2002 | } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { |
dd1b119c | 2003 | netif_stop_queue(netdev); |
b209af99 | 2004 | } |
dd1b119c | 2005 | |
ac718b69 | 2006 | return NETDEV_TX_OK; |
2007 | } | |
2008 | ||
2009 | static void r8152b_reset_packet_filter(struct r8152 *tp) | |
2010 | { | |
2011 | u32 ocp_data; | |
2012 | ||
2013 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); | |
2014 | ocp_data &= ~FMC_FCR_MCU_EN; | |
2015 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
2016 | ocp_data |= FMC_FCR_MCU_EN; | |
2017 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
2018 | } | |
2019 | ||
2020 | static void rtl8152_nic_reset(struct r8152 *tp) | |
2021 | { | |
2022 | int i; | |
2023 | ||
2024 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); | |
2025 | ||
2026 | for (i = 0; i < 1000; i++) { | |
2027 | if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) | |
2028 | break; | |
b209af99 | 2029 | usleep_range(100, 400); |
ac718b69 | 2030 | } |
2031 | } | |
2032 | ||
dd1b119c | 2033 | static void set_tx_qlen(struct r8152 *tp) |
2034 | { | |
2035 | struct net_device *netdev = tp->netdev; | |
2036 | ||
52aec126 | 2037 | tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + |
2038 | sizeof(struct tx_desc)); | |
dd1b119c | 2039 | } |
2040 | ||
ac718b69 | 2041 | static inline u8 rtl8152_get_speed(struct r8152 *tp) |
2042 | { | |
2043 | return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); | |
2044 | } | |
2045 | ||
507605a8 | 2046 | static void rtl_set_eee_plus(struct r8152 *tp) |
ac718b69 | 2047 | { |
ebc2ec48 | 2048 | u32 ocp_data; |
ac718b69 | 2049 | u8 speed; |
2050 | ||
2051 | speed = rtl8152_get_speed(tp); | |
ebc2ec48 | 2052 | if (speed & _10bps) { |
ac718b69 | 2053 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); |
ebc2ec48 | 2054 | ocp_data |= EEEP_CR_EEEP_TX; |
ac718b69 | 2055 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
2056 | } else { | |
2057 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); | |
ebc2ec48 | 2058 | ocp_data &= ~EEEP_CR_EEEP_TX; |
ac718b69 | 2059 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
2060 | } | |
507605a8 | 2061 | } |
2062 | ||
00a5e360 | 2063 | static void rxdy_gated_en(struct r8152 *tp, bool enable) |
2064 | { | |
2065 | u32 ocp_data; | |
2066 | ||
2067 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); | |
2068 | if (enable) | |
2069 | ocp_data |= RXDY_GATED_EN; | |
2070 | else | |
2071 | ocp_data &= ~RXDY_GATED_EN; | |
2072 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); | |
2073 | } | |
2074 | ||
445f7f4d | 2075 | static int rtl_start_rx(struct r8152 *tp) |
2076 | { | |
2077 | int i, ret = 0; | |
2078 | ||
2079 | INIT_LIST_HEAD(&tp->rx_done); | |
2080 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
2081 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
2082 | ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); | |
2083 | if (ret) | |
2084 | break; | |
2085 | } | |
2086 | ||
7bcf4f60 | 2087 | if (ret && ++i < RTL8152_MAX_RX) { |
2088 | struct list_head rx_queue; | |
2089 | unsigned long flags; | |
2090 | ||
2091 | INIT_LIST_HEAD(&rx_queue); | |
2092 | ||
2093 | do { | |
2094 | struct rx_agg *agg = &tp->rx_info[i++]; | |
2095 | struct urb *urb = agg->urb; | |
2096 | ||
2097 | urb->actual_length = 0; | |
2098 | list_add_tail(&agg->list, &rx_queue); | |
2099 | } while (i < RTL8152_MAX_RX); | |
2100 | ||
2101 | spin_lock_irqsave(&tp->rx_lock, flags); | |
2102 | list_splice_tail(&rx_queue, &tp->rx_done); | |
2103 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
2104 | } | |
2105 | ||
445f7f4d | 2106 | return ret; |
2107 | } | |
2108 | ||
2109 | static int rtl_stop_rx(struct r8152 *tp) | |
2110 | { | |
2111 | int i; | |
2112 | ||
2113 | for (i = 0; i < RTL8152_MAX_RX; i++) | |
2114 | usb_kill_urb(tp->rx_info[i].urb); | |
2115 | ||
d823ab68 | 2116 | while (!skb_queue_empty(&tp->rx_queue)) |
2117 | dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); | |
2118 | ||
445f7f4d | 2119 | return 0; |
2120 | } | |
2121 | ||
507605a8 | 2122 | static int rtl_enable(struct r8152 *tp) |
2123 | { | |
2124 | u32 ocp_data; | |
ac718b69 | 2125 | |
2126 | r8152b_reset_packet_filter(tp); | |
2127 | ||
2128 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); | |
2129 | ocp_data |= CR_RE | CR_TE; | |
2130 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); | |
2131 | ||
00a5e360 | 2132 | rxdy_gated_en(tp, false); |
ac718b69 | 2133 | |
aa2e0926 | 2134 | return 0; |
ac718b69 | 2135 | } |
2136 | ||
507605a8 | 2137 | static int rtl8152_enable(struct r8152 *tp) |
2138 | { | |
6871438c | 2139 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2140 | return -ENODEV; | |
2141 | ||
507605a8 | 2142 | set_tx_qlen(tp); |
2143 | rtl_set_eee_plus(tp); | |
2144 | ||
2145 | return rtl_enable(tp); | |
2146 | } | |
2147 | ||
464ec10a | 2148 | static void r8153_set_rx_early_timeout(struct r8152 *tp) |
43779f8d | 2149 | { |
464ec10a | 2150 | u32 ocp_data = tp->coalesce / 8; |
43779f8d | 2151 | |
464ec10a | 2152 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data); |
2153 | } | |
2154 | ||
2155 | static void r8153_set_rx_early_size(struct r8152 *tp) | |
2156 | { | |
2157 | u32 mtu = tp->netdev->mtu; | |
2158 | u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 4; | |
2159 | ||
2160 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data); | |
43779f8d | 2161 | } |
2162 | ||
2163 | static int rtl8153_enable(struct r8152 *tp) | |
2164 | { | |
6871438c | 2165 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2166 | return -ENODEV; | |
2167 | ||
b214396f | 2168 | usb_disable_lpm(tp->udev); |
43779f8d | 2169 | set_tx_qlen(tp); |
2170 | rtl_set_eee_plus(tp); | |
464ec10a | 2171 | r8153_set_rx_early_timeout(tp); |
2172 | r8153_set_rx_early_size(tp); | |
43779f8d | 2173 | |
2174 | return rtl_enable(tp); | |
2175 | } | |
2176 | ||
d70b1137 | 2177 | static void rtl_disable(struct r8152 *tp) |
ac718b69 | 2178 | { |
ebc2ec48 | 2179 | u32 ocp_data; |
2180 | int i; | |
ac718b69 | 2181 | |
6871438c | 2182 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2183 | rtl_drop_queued_tx(tp); | |
2184 | return; | |
2185 | } | |
2186 | ||
ac718b69 | 2187 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
2188 | ocp_data &= ~RCR_ACPT_ALL; | |
2189 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2190 | ||
00a5e360 | 2191 | rtl_drop_queued_tx(tp); |
ebc2ec48 | 2192 | |
2193 | for (i = 0; i < RTL8152_MAX_TX; i++) | |
2194 | usb_kill_urb(tp->tx_info[i].urb); | |
ac718b69 | 2195 | |
00a5e360 | 2196 | rxdy_gated_en(tp, true); |
ac718b69 | 2197 | |
2198 | for (i = 0; i < 1000; i++) { | |
2199 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2200 | if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) | |
2201 | break; | |
8ddfa077 | 2202 | usleep_range(1000, 2000); |
ac718b69 | 2203 | } |
2204 | ||
2205 | for (i = 0; i < 1000; i++) { | |
2206 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) | |
2207 | break; | |
8ddfa077 | 2208 | usleep_range(1000, 2000); |
ac718b69 | 2209 | } |
2210 | ||
445f7f4d | 2211 | rtl_stop_rx(tp); |
ac718b69 | 2212 | |
2213 | rtl8152_nic_reset(tp); | |
2214 | } | |
2215 | ||
00a5e360 | 2216 | static void r8152_power_cut_en(struct r8152 *tp, bool enable) |
2217 | { | |
2218 | u32 ocp_data; | |
2219 | ||
2220 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); | |
2221 | if (enable) | |
2222 | ocp_data |= POWER_CUT; | |
2223 | else | |
2224 | ocp_data &= ~POWER_CUT; | |
2225 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); | |
2226 | ||
2227 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); | |
2228 | ocp_data &= ~RESUME_INDICATE; | |
2229 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); | |
00a5e360 | 2230 | } |
2231 | ||
c5554298 | 2232 | static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) |
2233 | { | |
2234 | u32 ocp_data; | |
2235 | ||
2236 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2237 | if (enable) | |
2238 | ocp_data |= CPCR_RX_VLAN; | |
2239 | else | |
2240 | ocp_data &= ~CPCR_RX_VLAN; | |
2241 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2242 | } | |
2243 | ||
2244 | static int rtl8152_set_features(struct net_device *dev, | |
2245 | netdev_features_t features) | |
2246 | { | |
2247 | netdev_features_t changed = features ^ dev->features; | |
2248 | struct r8152 *tp = netdev_priv(dev); | |
405f8a0e | 2249 | int ret; |
2250 | ||
2251 | ret = usb_autopm_get_interface(tp->intf); | |
2252 | if (ret < 0) | |
2253 | goto out; | |
c5554298 | 2254 | |
b5403273 | 2255 | mutex_lock(&tp->control); |
2256 | ||
c5554298 | 2257 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) { |
2258 | if (features & NETIF_F_HW_VLAN_CTAG_RX) | |
2259 | rtl_rx_vlan_en(tp, true); | |
2260 | else | |
2261 | rtl_rx_vlan_en(tp, false); | |
2262 | } | |
2263 | ||
b5403273 | 2264 | mutex_unlock(&tp->control); |
2265 | ||
405f8a0e | 2266 | usb_autopm_put_interface(tp->intf); |
2267 | ||
2268 | out: | |
2269 | return ret; | |
c5554298 | 2270 | } |
2271 | ||
21ff2e89 | 2272 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
2273 | ||
2274 | static u32 __rtl_get_wol(struct r8152 *tp) | |
2275 | { | |
2276 | u32 ocp_data; | |
2277 | u32 wolopts = 0; | |
2278 | ||
2279 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2280 | if (!(ocp_data & LAN_WAKE_EN)) | |
2281 | return 0; | |
2282 | ||
2283 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2284 | if (ocp_data & LINK_ON_WAKE_EN) | |
2285 | wolopts |= WAKE_PHY; | |
2286 | ||
2287 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2288 | if (ocp_data & UWF_EN) | |
2289 | wolopts |= WAKE_UCAST; | |
2290 | if (ocp_data & BWF_EN) | |
2291 | wolopts |= WAKE_BCAST; | |
2292 | if (ocp_data & MWF_EN) | |
2293 | wolopts |= WAKE_MCAST; | |
2294 | ||
2295 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2296 | if (ocp_data & MAGIC_EN) | |
2297 | wolopts |= WAKE_MAGIC; | |
2298 | ||
2299 | return wolopts; | |
2300 | } | |
2301 | ||
2302 | static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) | |
2303 | { | |
2304 | u32 ocp_data; | |
2305 | ||
2306 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2307 | ||
2308 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2309 | ocp_data &= ~LINK_ON_WAKE_EN; | |
2310 | if (wolopts & WAKE_PHY) | |
2311 | ocp_data |= LINK_ON_WAKE_EN; | |
2312 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2313 | ||
2314 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2315 | ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN); | |
2316 | if (wolopts & WAKE_UCAST) | |
2317 | ocp_data |= UWF_EN; | |
2318 | if (wolopts & WAKE_BCAST) | |
2319 | ocp_data |= BWF_EN; | |
2320 | if (wolopts & WAKE_MCAST) | |
2321 | ocp_data |= MWF_EN; | |
2322 | if (wolopts & WAKE_ANY) | |
2323 | ocp_data |= LAN_WAKE_EN; | |
2324 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); | |
2325 | ||
2326 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2327 | ||
2328 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2329 | ocp_data &= ~MAGIC_EN; | |
2330 | if (wolopts & WAKE_MAGIC) | |
2331 | ocp_data |= MAGIC_EN; | |
2332 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); | |
2333 | ||
2334 | if (wolopts & WAKE_ANY) | |
2335 | device_set_wakeup_enable(&tp->udev->dev, true); | |
2336 | else | |
2337 | device_set_wakeup_enable(&tp->udev->dev, false); | |
2338 | } | |
2339 | ||
b214396f | 2340 | static void r8153_u1u2en(struct r8152 *tp, bool enable) |
2341 | { | |
2342 | u8 u1u2[8]; | |
2343 | ||
2344 | if (enable) | |
2345 | memset(u1u2, 0xff, sizeof(u1u2)); | |
2346 | else | |
2347 | memset(u1u2, 0x00, sizeof(u1u2)); | |
2348 | ||
2349 | usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); | |
2350 | } | |
2351 | ||
2352 | static void r8153_u2p3en(struct r8152 *tp, bool enable) | |
2353 | { | |
2354 | u32 ocp_data; | |
2355 | ||
2356 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); | |
2357 | if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04) | |
2358 | ocp_data |= U2P3_ENABLE; | |
2359 | else | |
2360 | ocp_data &= ~U2P3_ENABLE; | |
2361 | ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); | |
2362 | } | |
2363 | ||
2364 | static void r8153_power_cut_en(struct r8152 *tp, bool enable) | |
2365 | { | |
2366 | u32 ocp_data; | |
2367 | ||
2368 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
2369 | if (enable) | |
2370 | ocp_data |= PWR_EN | PHASE2_EN; | |
2371 | else | |
2372 | ocp_data &= ~(PWR_EN | PHASE2_EN); | |
2373 | ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
2374 | ||
2375 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
2376 | ocp_data &= ~PCUT_STATUS; | |
2377 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
2378 | } | |
2379 | ||
7daed8dc | 2380 | static bool rtl_can_wakeup(struct r8152 *tp) |
2381 | { | |
2382 | struct usb_device *udev = tp->udev; | |
2383 | ||
2384 | return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); | |
2385 | } | |
2386 | ||
9a4be1bd | 2387 | static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) |
2388 | { | |
2389 | if (enable) { | |
2390 | u32 ocp_data; | |
2391 | ||
b214396f | 2392 | r8153_u1u2en(tp, false); |
2393 | r8153_u2p3en(tp, false); | |
2394 | ||
9a4be1bd | 2395 | __rtl_set_wol(tp, WAKE_ANY); |
2396 | ||
2397 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2398 | ||
2399 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2400 | ocp_data |= LINK_OFF_WAKE_EN; | |
2401 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2402 | ||
2403 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2404 | } else { | |
2405 | __rtl_set_wol(tp, tp->saved_wolopts); | |
b214396f | 2406 | r8153_u2p3en(tp, true); |
2407 | r8153_u1u2en(tp, true); | |
9a4be1bd | 2408 | } |
2409 | } | |
2410 | ||
aa66a5f1 | 2411 | static void rtl_phy_reset(struct r8152 *tp) |
2412 | { | |
2413 | u16 data; | |
2414 | int i; | |
2415 | ||
2416 | clear_bit(PHY_RESET, &tp->flags); | |
2417 | ||
2418 | data = r8152_mdio_read(tp, MII_BMCR); | |
2419 | ||
2420 | /* don't reset again before the previous one complete */ | |
2421 | if (data & BMCR_RESET) | |
2422 | return; | |
2423 | ||
2424 | data |= BMCR_RESET; | |
2425 | r8152_mdio_write(tp, MII_BMCR, data); | |
2426 | ||
2427 | for (i = 0; i < 50; i++) { | |
2428 | msleep(20); | |
2429 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
2430 | break; | |
2431 | } | |
2432 | } | |
2433 | ||
4349968a | 2434 | static void r8153_teredo_off(struct r8152 *tp) |
2435 | { | |
2436 | u32 ocp_data; | |
2437 | ||
2438 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
2439 | ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); | |
2440 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2441 | ||
2442 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); | |
2443 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); | |
2444 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); | |
2445 | } | |
2446 | ||
2447 | static void r8152b_disable_aldps(struct r8152 *tp) | |
2448 | { | |
2449 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); | |
2450 | msleep(20); | |
2451 | } | |
2452 | ||
2453 | static inline void r8152b_enable_aldps(struct r8152 *tp) | |
2454 | { | |
2455 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | | |
2456 | LINKENA | DIS_SDSAVE); | |
2457 | } | |
2458 | ||
d70b1137 | 2459 | static void rtl8152_disable(struct r8152 *tp) |
2460 | { | |
2461 | r8152b_disable_aldps(tp); | |
2462 | rtl_disable(tp); | |
2463 | r8152b_enable_aldps(tp); | |
2464 | } | |
2465 | ||
4349968a | 2466 | static void r8152b_hw_phy_cfg(struct r8152 *tp) |
2467 | { | |
f0cbe0ac | 2468 | u16 data; |
2469 | ||
2470 | data = r8152_mdio_read(tp, MII_BMCR); | |
2471 | if (data & BMCR_PDOWN) { | |
2472 | data &= ~BMCR_PDOWN; | |
2473 | r8152_mdio_write(tp, MII_BMCR, data); | |
2474 | } | |
2475 | ||
aa66a5f1 | 2476 | set_bit(PHY_RESET, &tp->flags); |
4349968a | 2477 | } |
2478 | ||
ac718b69 | 2479 | static void r8152b_exit_oob(struct r8152 *tp) |
2480 | { | |
db8515ef | 2481 | u32 ocp_data; |
2482 | int i; | |
ac718b69 | 2483 | |
2484 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2485 | ocp_data &= ~RCR_ACPT_ALL; | |
2486 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2487 | ||
00a5e360 | 2488 | rxdy_gated_en(tp, true); |
da9bd117 | 2489 | r8153_teredo_off(tp); |
7e9da481 | 2490 | r8152b_hw_phy_cfg(tp); |
ac718b69 | 2491 | |
2492 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2493 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); | |
2494 | ||
2495 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2496 | ocp_data &= ~NOW_IS_OOB; | |
2497 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2498 | ||
2499 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2500 | ocp_data &= ~MCU_BORW_EN; | |
2501 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2502 | ||
2503 | for (i = 0; i < 1000; i++) { | |
2504 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2505 | if (ocp_data & LINK_LIST_READY) | |
2506 | break; | |
8ddfa077 | 2507 | usleep_range(1000, 2000); |
ac718b69 | 2508 | } |
2509 | ||
2510 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2511 | ocp_data |= RE_INIT_LL; | |
2512 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2513 | ||
2514 | for (i = 0; i < 1000; i++) { | |
2515 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2516 | if (ocp_data & LINK_LIST_READY) | |
2517 | break; | |
8ddfa077 | 2518 | usleep_range(1000, 2000); |
ac718b69 | 2519 | } |
2520 | ||
2521 | rtl8152_nic_reset(tp); | |
2522 | ||
2523 | /* rx share fifo credit full threshold */ | |
2524 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2525 | ||
a3cc465d | 2526 | if (tp->udev->speed == USB_SPEED_FULL || |
2527 | tp->udev->speed == USB_SPEED_LOW) { | |
ac718b69 | 2528 | /* rx share fifo credit near full threshold */ |
2529 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2530 | RXFIFO_THR2_FULL); | |
2531 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2532 | RXFIFO_THR3_FULL); | |
2533 | } else { | |
2534 | /* rx share fifo credit near full threshold */ | |
2535 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2536 | RXFIFO_THR2_HIGH); | |
2537 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2538 | RXFIFO_THR3_HIGH); | |
2539 | } | |
2540 | ||
2541 | /* TX share fifo free credit full threshold */ | |
2542 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); | |
2543 | ||
2544 | ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); | |
8e1f51bd | 2545 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); |
ac718b69 | 2546 | ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, |
2547 | TEST_MODE_DISABLE | TX_SIZE_ADJUST1); | |
2548 | ||
c5554298 | 2549 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
ac718b69 | 2550 | |
2551 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2552 | ||
2553 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2554 | ocp_data |= TCR0_AUTO_FIFO; | |
2555 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2556 | } | |
2557 | ||
2558 | static void r8152b_enter_oob(struct r8152 *tp) | |
2559 | { | |
45f4a19f | 2560 | u32 ocp_data; |
2561 | int i; | |
ac718b69 | 2562 | |
2563 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2564 | ocp_data &= ~NOW_IS_OOB; | |
2565 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2566 | ||
2567 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); | |
2568 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); | |
2569 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); | |
2570 | ||
d70b1137 | 2571 | rtl_disable(tp); |
ac718b69 | 2572 | |
2573 | for (i = 0; i < 1000; i++) { | |
2574 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2575 | if (ocp_data & LINK_LIST_READY) | |
2576 | break; | |
8ddfa077 | 2577 | usleep_range(1000, 2000); |
ac718b69 | 2578 | } |
2579 | ||
2580 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2581 | ocp_data |= RE_INIT_LL; | |
2582 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2583 | ||
2584 | for (i = 0; i < 1000; i++) { | |
2585 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2586 | if (ocp_data & LINK_LIST_READY) | |
2587 | break; | |
8ddfa077 | 2588 | usleep_range(1000, 2000); |
ac718b69 | 2589 | } |
2590 | ||
2591 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2592 | ||
c5554298 | 2593 | rtl_rx_vlan_en(tp, true); |
ac718b69 | 2594 | |
2595 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2596 | ocp_data |= ALDPS_PROXY_MODE; | |
2597 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2598 | ||
2599 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2600 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2601 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2602 | ||
00a5e360 | 2603 | rxdy_gated_en(tp, false); |
ac718b69 | 2604 | |
2605 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2606 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2607 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2608 | } | |
2609 | ||
43779f8d | 2610 | static void r8153_hw_phy_cfg(struct r8152 *tp) |
2611 | { | |
2612 | u32 ocp_data; | |
2613 | u16 data; | |
2614 | ||
fb02eb4a | 2615 | if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || |
2616 | tp->version == RTL_VER_05) | |
2617 | ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); | |
2618 | ||
f0cbe0ac | 2619 | data = r8152_mdio_read(tp, MII_BMCR); |
2620 | if (data & BMCR_PDOWN) { | |
2621 | data &= ~BMCR_PDOWN; | |
2622 | r8152_mdio_write(tp, MII_BMCR, data); | |
2623 | } | |
43779f8d | 2624 | |
2625 | if (tp->version == RTL_VER_03) { | |
2626 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
2627 | data &= ~CTAP_SHORT_EN; | |
2628 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
2629 | } | |
2630 | ||
2631 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2632 | data |= EEE_CLKDIV_EN; | |
2633 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2634 | ||
2635 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
2636 | data |= EN_10M_BGOFF; | |
2637 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
2638 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2639 | data |= EN_10M_PLLOFF; | |
2640 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
b4d99def | 2641 | sram_write(tp, SRAM_IMPEDANCE, 0x0b13); |
43779f8d | 2642 | |
2643 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
2644 | ocp_data |= PFM_PWM_SWITCH; | |
2645 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
2646 | ||
b4d99def | 2647 | /* Enable LPF corner auto tune */ |
2648 | sram_write(tp, SRAM_LPF_CFG, 0xf70f); | |
43779f8d | 2649 | |
b4d99def | 2650 | /* Adjust 10M Amplitude */ |
2651 | sram_write(tp, SRAM_10M_AMP1, 0x00af); | |
2652 | sram_write(tp, SRAM_10M_AMP2, 0x0208); | |
aa66a5f1 | 2653 | |
2654 | set_bit(PHY_RESET, &tp->flags); | |
43779f8d | 2655 | } |
2656 | ||
43779f8d | 2657 | static void r8153_first_init(struct r8152 *tp) |
2658 | { | |
2659 | u32 ocp_data; | |
2660 | int i; | |
2661 | ||
00a5e360 | 2662 | rxdy_gated_en(tp, true); |
43779f8d | 2663 | r8153_teredo_off(tp); |
2664 | ||
2665 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2666 | ocp_data &= ~RCR_ACPT_ALL; | |
2667 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2668 | ||
2669 | r8153_hw_phy_cfg(tp); | |
2670 | ||
2671 | rtl8152_nic_reset(tp); | |
2672 | ||
2673 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2674 | ocp_data &= ~NOW_IS_OOB; | |
2675 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2676 | ||
2677 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2678 | ocp_data &= ~MCU_BORW_EN; | |
2679 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2680 | ||
2681 | for (i = 0; i < 1000; i++) { | |
2682 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2683 | if (ocp_data & LINK_LIST_READY) | |
2684 | break; | |
8ddfa077 | 2685 | usleep_range(1000, 2000); |
43779f8d | 2686 | } |
2687 | ||
2688 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2689 | ocp_data |= RE_INIT_LL; | |
2690 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2691 | ||
2692 | for (i = 0; i < 1000; i++) { | |
2693 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2694 | if (ocp_data & LINK_LIST_READY) | |
2695 | break; | |
8ddfa077 | 2696 | usleep_range(1000, 2000); |
43779f8d | 2697 | } |
2698 | ||
c5554298 | 2699 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
43779f8d | 2700 | |
69b4b7a4 | 2701 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); |
2702 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); | |
43779f8d | 2703 | |
2704 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2705 | ocp_data |= TCR0_AUTO_FIFO; | |
2706 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2707 | ||
2708 | rtl8152_nic_reset(tp); | |
2709 | ||
2710 | /* rx share fifo credit full threshold */ | |
2711 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2712 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); | |
2713 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); | |
2714 | /* TX share fifo free credit full threshold */ | |
2715 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); | |
2716 | ||
9629e3c0 | 2717 | /* rx aggregation */ |
43779f8d | 2718 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
e90fba8d | 2719 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); |
43779f8d | 2720 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
2721 | } | |
2722 | ||
2723 | static void r8153_enter_oob(struct r8152 *tp) | |
2724 | { | |
2725 | u32 ocp_data; | |
2726 | int i; | |
2727 | ||
2728 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2729 | ocp_data &= ~NOW_IS_OOB; | |
2730 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2731 | ||
d70b1137 | 2732 | rtl_disable(tp); |
43779f8d | 2733 | |
2734 | for (i = 0; i < 1000; i++) { | |
2735 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2736 | if (ocp_data & LINK_LIST_READY) | |
2737 | break; | |
8ddfa077 | 2738 | usleep_range(1000, 2000); |
43779f8d | 2739 | } |
2740 | ||
2741 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2742 | ocp_data |= RE_INIT_LL; | |
2743 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2744 | ||
2745 | for (i = 0; i < 1000; i++) { | |
2746 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2747 | if (ocp_data & LINK_LIST_READY) | |
2748 | break; | |
8ddfa077 | 2749 | usleep_range(1000, 2000); |
43779f8d | 2750 | } |
2751 | ||
69b4b7a4 | 2752 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); |
43779f8d | 2753 | |
43779f8d | 2754 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); |
2755 | ocp_data &= ~TEREDO_WAKE_MASK; | |
2756 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2757 | ||
c5554298 | 2758 | rtl_rx_vlan_en(tp, true); |
43779f8d | 2759 | |
2760 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2761 | ocp_data |= ALDPS_PROXY_MODE; | |
2762 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2763 | ||
2764 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2765 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2766 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2767 | ||
00a5e360 | 2768 | rxdy_gated_en(tp, false); |
43779f8d | 2769 | |
2770 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2771 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2772 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2773 | } | |
2774 | ||
2775 | static void r8153_disable_aldps(struct r8152 *tp) | |
2776 | { | |
2777 | u16 data; | |
2778 | ||
2779 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2780 | data &= ~EN_ALDPS; | |
2781 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2782 | msleep(20); | |
2783 | } | |
2784 | ||
2785 | static void r8153_enable_aldps(struct r8152 *tp) | |
2786 | { | |
2787 | u16 data; | |
2788 | ||
2789 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2790 | data |= EN_ALDPS; | |
2791 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2792 | } | |
2793 | ||
d70b1137 | 2794 | static void rtl8153_disable(struct r8152 *tp) |
2795 | { | |
2796 | r8153_disable_aldps(tp); | |
2797 | rtl_disable(tp); | |
2798 | r8153_enable_aldps(tp); | |
b214396f | 2799 | usb_enable_lpm(tp->udev); |
d70b1137 | 2800 | } |
2801 | ||
ac718b69 | 2802 | static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) |
2803 | { | |
43779f8d | 2804 | u16 bmcr, anar, gbcr; |
ac718b69 | 2805 | int ret = 0; |
2806 | ||
2807 | cancel_delayed_work_sync(&tp->schedule); | |
2808 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
2809 | anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | | |
2810 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
43779f8d | 2811 | if (tp->mii.supports_gmii) { |
2812 | gbcr = r8152_mdio_read(tp, MII_CTRL1000); | |
2813 | gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); | |
2814 | } else { | |
2815 | gbcr = 0; | |
2816 | } | |
ac718b69 | 2817 | |
2818 | if (autoneg == AUTONEG_DISABLE) { | |
2819 | if (speed == SPEED_10) { | |
2820 | bmcr = 0; | |
2821 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2822 | } else if (speed == SPEED_100) { | |
2823 | bmcr = BMCR_SPEED100; | |
2824 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
43779f8d | 2825 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2826 | bmcr = BMCR_SPEED1000; | |
2827 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
ac718b69 | 2828 | } else { |
2829 | ret = -EINVAL; | |
2830 | goto out; | |
2831 | } | |
2832 | ||
2833 | if (duplex == DUPLEX_FULL) | |
2834 | bmcr |= BMCR_FULLDPLX; | |
2835 | } else { | |
2836 | if (speed == SPEED_10) { | |
2837 | if (duplex == DUPLEX_FULL) | |
2838 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2839 | else | |
2840 | anar |= ADVERTISE_10HALF; | |
2841 | } else if (speed == SPEED_100) { | |
2842 | if (duplex == DUPLEX_FULL) { | |
2843 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2844 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2845 | } else { | |
2846 | anar |= ADVERTISE_10HALF; | |
2847 | anar |= ADVERTISE_100HALF; | |
2848 | } | |
43779f8d | 2849 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2850 | if (duplex == DUPLEX_FULL) { | |
2851 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2852 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2853 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
2854 | } else { | |
2855 | anar |= ADVERTISE_10HALF; | |
2856 | anar |= ADVERTISE_100HALF; | |
2857 | gbcr |= ADVERTISE_1000HALF; | |
2858 | } | |
ac718b69 | 2859 | } else { |
2860 | ret = -EINVAL; | |
2861 | goto out; | |
2862 | } | |
2863 | ||
2864 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; | |
2865 | } | |
2866 | ||
aa66a5f1 | 2867 | if (test_bit(PHY_RESET, &tp->flags)) |
2868 | bmcr |= BMCR_RESET; | |
2869 | ||
43779f8d | 2870 | if (tp->mii.supports_gmii) |
2871 | r8152_mdio_write(tp, MII_CTRL1000, gbcr); | |
2872 | ||
ac718b69 | 2873 | r8152_mdio_write(tp, MII_ADVERTISE, anar); |
2874 | r8152_mdio_write(tp, MII_BMCR, bmcr); | |
2875 | ||
aa66a5f1 | 2876 | if (test_bit(PHY_RESET, &tp->flags)) { |
2877 | int i; | |
2878 | ||
2879 | clear_bit(PHY_RESET, &tp->flags); | |
2880 | for (i = 0; i < 50; i++) { | |
2881 | msleep(20); | |
2882 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
2883 | break; | |
2884 | } | |
2885 | } | |
2886 | ||
ac718b69 | 2887 | out: |
ac718b69 | 2888 | |
2889 | return ret; | |
2890 | } | |
2891 | ||
d70b1137 | 2892 | static void rtl8152_up(struct r8152 *tp) |
2893 | { | |
2894 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
2895 | return; | |
2896 | ||
2897 | r8152b_disable_aldps(tp); | |
2898 | r8152b_exit_oob(tp); | |
2899 | r8152b_enable_aldps(tp); | |
2900 | } | |
2901 | ||
ac718b69 | 2902 | static void rtl8152_down(struct r8152 *tp) |
2903 | { | |
6871438c | 2904 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2905 | rtl_drop_queued_tx(tp); | |
2906 | return; | |
2907 | } | |
2908 | ||
00a5e360 | 2909 | r8152_power_cut_en(tp, false); |
ac718b69 | 2910 | r8152b_disable_aldps(tp); |
2911 | r8152b_enter_oob(tp); | |
2912 | r8152b_enable_aldps(tp); | |
2913 | } | |
2914 | ||
d70b1137 | 2915 | static void rtl8153_up(struct r8152 *tp) |
2916 | { | |
2917 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
2918 | return; | |
2919 | ||
b214396f | 2920 | r8153_u1u2en(tp, false); |
d70b1137 | 2921 | r8153_disable_aldps(tp); |
2922 | r8153_first_init(tp); | |
2923 | r8153_enable_aldps(tp); | |
b214396f | 2924 | r8153_u2p3en(tp, true); |
2925 | r8153_u1u2en(tp, true); | |
2926 | usb_enable_lpm(tp->udev); | |
d70b1137 | 2927 | } |
2928 | ||
43779f8d | 2929 | static void rtl8153_down(struct r8152 *tp) |
2930 | { | |
6871438c | 2931 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2932 | rtl_drop_queued_tx(tp); | |
2933 | return; | |
2934 | } | |
2935 | ||
b9702723 | 2936 | r8153_u1u2en(tp, false); |
b214396f | 2937 | r8153_u2p3en(tp, false); |
b9702723 | 2938 | r8153_power_cut_en(tp, false); |
43779f8d | 2939 | r8153_disable_aldps(tp); |
2940 | r8153_enter_oob(tp); | |
2941 | r8153_enable_aldps(tp); | |
2942 | } | |
2943 | ||
ac718b69 | 2944 | static void set_carrier(struct r8152 *tp) |
2945 | { | |
2946 | struct net_device *netdev = tp->netdev; | |
2947 | u8 speed; | |
2948 | ||
40a82917 | 2949 | clear_bit(RTL8152_LINK_CHG, &tp->flags); |
ac718b69 | 2950 | speed = rtl8152_get_speed(tp); |
2951 | ||
2952 | if (speed & LINK_STATUS) { | |
51d979fa | 2953 | if (!netif_carrier_ok(netdev)) { |
c81229c9 | 2954 | tp->rtl_ops.enable(tp); |
ac718b69 | 2955 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
41cec84c | 2956 | napi_disable(&tp->napi); |
ac718b69 | 2957 | netif_carrier_on(netdev); |
aa2e0926 | 2958 | rtl_start_rx(tp); |
41cec84c | 2959 | napi_enable(&tp->napi); |
ac718b69 | 2960 | } |
2961 | } else { | |
51d979fa | 2962 | if (netif_carrier_ok(netdev)) { |
ac718b69 | 2963 | netif_carrier_off(netdev); |
d823ab68 | 2964 | napi_disable(&tp->napi); |
c81229c9 | 2965 | tp->rtl_ops.disable(tp); |
d823ab68 | 2966 | napi_enable(&tp->napi); |
ac718b69 | 2967 | } |
2968 | } | |
ac718b69 | 2969 | } |
2970 | ||
2971 | static void rtl_work_func_t(struct work_struct *work) | |
2972 | { | |
2973 | struct r8152 *tp = container_of(work, struct r8152, schedule.work); | |
2974 | ||
a1f83fee | 2975 | /* If the device is unplugged or !netif_running(), the workqueue |
2976 | * doesn't need to wake the device, and could return directly. | |
2977 | */ | |
2978 | if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) | |
2979 | return; | |
2980 | ||
9a4be1bd | 2981 | if (usb_autopm_get_interface(tp->intf) < 0) |
2982 | return; | |
2983 | ||
ac718b69 | 2984 | if (!test_bit(WORK_ENABLE, &tp->flags)) |
2985 | goto out1; | |
2986 | ||
b5403273 | 2987 | if (!mutex_trylock(&tp->control)) { |
2988 | schedule_delayed_work(&tp->schedule, 0); | |
2989 | goto out1; | |
2990 | } | |
2991 | ||
40a82917 | 2992 | if (test_bit(RTL8152_LINK_CHG, &tp->flags)) |
2993 | set_carrier(tp); | |
ac718b69 | 2994 | |
2995 | if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) | |
2996 | _rtl8152_set_rx_mode(tp->netdev); | |
2997 | ||
d823ab68 | 2998 | /* don't schedule napi before linking */ |
2999 | if (test_bit(SCHEDULE_NAPI, &tp->flags) && | |
51d979fa | 3000 | netif_carrier_ok(tp->netdev)) { |
d823ab68 | 3001 | clear_bit(SCHEDULE_NAPI, &tp->flags); |
3002 | napi_schedule(&tp->napi); | |
0c3121fc | 3003 | } |
aa66a5f1 | 3004 | |
3005 | if (test_bit(PHY_RESET, &tp->flags)) | |
3006 | rtl_phy_reset(tp); | |
3007 | ||
b5403273 | 3008 | mutex_unlock(&tp->control); |
3009 | ||
ac718b69 | 3010 | out1: |
9a4be1bd | 3011 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 3012 | } |
3013 | ||
3014 | static int rtl8152_open(struct net_device *netdev) | |
3015 | { | |
3016 | struct r8152 *tp = netdev_priv(netdev); | |
3017 | int res = 0; | |
3018 | ||
7e9da481 | 3019 | res = alloc_all_mem(tp); |
3020 | if (res) | |
3021 | goto out; | |
3022 | ||
51d979fa | 3023 | netif_carrier_off(netdev); |
f4c7476b | 3024 | |
9a4be1bd | 3025 | res = usb_autopm_get_interface(tp->intf); |
3026 | if (res < 0) { | |
3027 | free_all_mem(tp); | |
3028 | goto out; | |
3029 | } | |
3030 | ||
b5403273 | 3031 | mutex_lock(&tp->control); |
3032 | ||
9a4be1bd | 3033 | /* The WORK_ENABLE may be set when autoresume occurs */ |
3034 | if (test_bit(WORK_ENABLE, &tp->flags)) { | |
3035 | clear_bit(WORK_ENABLE, &tp->flags); | |
3036 | usb_kill_urb(tp->intr_urb); | |
3037 | cancel_delayed_work_sync(&tp->schedule); | |
f4c7476b | 3038 | |
3039 | /* disable the tx/rx, if the workqueue has enabled them. */ | |
51d979fa | 3040 | if (netif_carrier_ok(netdev)) |
9a4be1bd | 3041 | tp->rtl_ops.disable(tp); |
3042 | } | |
3043 | ||
7e9da481 | 3044 | tp->rtl_ops.up(tp); |
3045 | ||
3d55f44f | 3046 | rtl8152_set_speed(tp, AUTONEG_ENABLE, |
3047 | tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, | |
3048 | DUPLEX_FULL); | |
3d55f44f | 3049 | netif_carrier_off(netdev); |
3050 | netif_start_queue(netdev); | |
3051 | set_bit(WORK_ENABLE, &tp->flags); | |
db8515ef | 3052 | |
40a82917 | 3053 | res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
3054 | if (res) { | |
3055 | if (res == -ENODEV) | |
3056 | netif_device_detach(tp->netdev); | |
4a8deae2 HW |
3057 | netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", |
3058 | res); | |
7e9da481 | 3059 | free_all_mem(tp); |
93ffbeab | 3060 | } else { |
d823ab68 | 3061 | napi_enable(&tp->napi); |
ac718b69 | 3062 | } |
3063 | ||
b5403273 | 3064 | mutex_unlock(&tp->control); |
3065 | ||
9a4be1bd | 3066 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 3067 | |
7e9da481 | 3068 | out: |
ac718b69 | 3069 | return res; |
3070 | } | |
3071 | ||
3072 | static int rtl8152_close(struct net_device *netdev) | |
3073 | { | |
3074 | struct r8152 *tp = netdev_priv(netdev); | |
3075 | int res = 0; | |
3076 | ||
d823ab68 | 3077 | napi_disable(&tp->napi); |
ac718b69 | 3078 | clear_bit(WORK_ENABLE, &tp->flags); |
3d55f44f | 3079 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 3080 | cancel_delayed_work_sync(&tp->schedule); |
3081 | netif_stop_queue(netdev); | |
9a4be1bd | 3082 | |
3083 | res = usb_autopm_get_interface(tp->intf); | |
53543db5 | 3084 | if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { |
9a4be1bd | 3085 | rtl_drop_queued_tx(tp); |
d823ab68 | 3086 | rtl_stop_rx(tp); |
9a4be1bd | 3087 | } else { |
b5403273 | 3088 | mutex_lock(&tp->control); |
3089 | ||
b209af99 | 3090 | /* The autosuspend may have been enabled and wouldn't |
9a4be1bd | 3091 | * be disable when autoresume occurs, because the |
3092 | * netif_running() would be false. | |
3093 | */ | |
923e1ee3 | 3094 | rtl_runtime_suspend_enable(tp, false); |
9a4be1bd | 3095 | |
9a4be1bd | 3096 | tp->rtl_ops.down(tp); |
b5403273 | 3097 | |
3098 | mutex_unlock(&tp->control); | |
3099 | ||
9a4be1bd | 3100 | usb_autopm_put_interface(tp->intf); |
3101 | } | |
ac718b69 | 3102 | |
7e9da481 | 3103 | free_all_mem(tp); |
3104 | ||
ac718b69 | 3105 | return res; |
3106 | } | |
3107 | ||
d24f6134 | 3108 | static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) |
3109 | { | |
3110 | ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); | |
3111 | ocp_reg_write(tp, OCP_EEE_DATA, reg); | |
3112 | ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); | |
3113 | } | |
3114 | ||
3115 | static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) | |
3116 | { | |
3117 | u16 data; | |
3118 | ||
3119 | r8152_mmd_indirect(tp, dev, reg); | |
3120 | data = ocp_reg_read(tp, OCP_EEE_DATA); | |
3121 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
3122 | ||
3123 | return data; | |
3124 | } | |
3125 | ||
3126 | static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) | |
ac718b69 | 3127 | { |
d24f6134 | 3128 | r8152_mmd_indirect(tp, dev, reg); |
3129 | ocp_reg_write(tp, OCP_EEE_DATA, data); | |
3130 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
3131 | } | |
3132 | ||
3133 | static void r8152_eee_en(struct r8152 *tp, bool enable) | |
3134 | { | |
3135 | u16 config1, config2, config3; | |
45f4a19f | 3136 | u32 ocp_data; |
ac718b69 | 3137 | |
3138 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
d24f6134 | 3139 | config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; |
3140 | config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); | |
3141 | config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; | |
3142 | ||
3143 | if (enable) { | |
3144 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
3145 | config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; | |
3146 | config1 |= sd_rise_time(1); | |
3147 | config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; | |
3148 | config3 |= fast_snr(42); | |
3149 | } else { | |
3150 | ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); | |
3151 | config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | | |
3152 | RX_QUIET_EN); | |
3153 | config1 |= sd_rise_time(7); | |
3154 | config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); | |
3155 | config3 |= fast_snr(511); | |
3156 | } | |
3157 | ||
ac718b69 | 3158 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); |
d24f6134 | 3159 | ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); |
3160 | ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); | |
3161 | ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); | |
ac718b69 | 3162 | } |
3163 | ||
d24f6134 | 3164 | static void r8152b_enable_eee(struct r8152 *tp) |
3165 | { | |
3166 | r8152_eee_en(tp, true); | |
3167 | r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); | |
3168 | } | |
3169 | ||
3170 | static void r8153_eee_en(struct r8152 *tp, bool enable) | |
43779f8d | 3171 | { |
3172 | u32 ocp_data; | |
d24f6134 | 3173 | u16 config; |
43779f8d | 3174 | |
3175 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
d24f6134 | 3176 | config = ocp_reg_read(tp, OCP_EEE_CFG); |
3177 | ||
3178 | if (enable) { | |
3179 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
3180 | config |= EEE10_EN; | |
3181 | } else { | |
3182 | ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); | |
3183 | config &= ~EEE10_EN; | |
3184 | } | |
3185 | ||
43779f8d | 3186 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); |
d24f6134 | 3187 | ocp_reg_write(tp, OCP_EEE_CFG, config); |
3188 | } | |
3189 | ||
3190 | static void r8153_enable_eee(struct r8152 *tp) | |
3191 | { | |
3192 | r8153_eee_en(tp, true); | |
3193 | ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); | |
43779f8d | 3194 | } |
3195 | ||
ac718b69 | 3196 | static void r8152b_enable_fc(struct r8152 *tp) |
3197 | { | |
3198 | u16 anar; | |
3199 | ||
3200 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
3201 | anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
3202 | r8152_mdio_write(tp, MII_ADVERTISE, anar); | |
3203 | } | |
3204 | ||
4f1d4d54 | 3205 | static void rtl_tally_reset(struct r8152 *tp) |
3206 | { | |
3207 | u32 ocp_data; | |
3208 | ||
3209 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); | |
3210 | ocp_data |= TALLY_RESET; | |
3211 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); | |
3212 | } | |
3213 | ||
ac718b69 | 3214 | static void r8152b_init(struct r8152 *tp) |
3215 | { | |
ebc2ec48 | 3216 | u32 ocp_data; |
ac718b69 | 3217 | |
6871438c | 3218 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3219 | return; | |
3220 | ||
d70b1137 | 3221 | r8152b_disable_aldps(tp); |
3222 | ||
ac718b69 | 3223 | if (tp->version == RTL_VER_01) { |
3224 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); | |
3225 | ocp_data &= ~LED_MODE_MASK; | |
3226 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
3227 | } | |
3228 | ||
00a5e360 | 3229 | r8152_power_cut_en(tp, false); |
ac718b69 | 3230 | |
ac718b69 | 3231 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); |
3232 | ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; | |
3233 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
3234 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); | |
3235 | ocp_data &= ~MCU_CLK_RATIO_MASK; | |
3236 | ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; | |
3237 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); | |
3238 | ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | | |
3239 | SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; | |
3240 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); | |
3241 | ||
3242 | r8152b_enable_eee(tp); | |
3243 | r8152b_enable_aldps(tp); | |
3244 | r8152b_enable_fc(tp); | |
4f1d4d54 | 3245 | rtl_tally_reset(tp); |
ac718b69 | 3246 | |
ebc2ec48 | 3247 | /* enable rx aggregation */ |
ac718b69 | 3248 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
e90fba8d | 3249 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); |
ac718b69 | 3250 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
3251 | } | |
3252 | ||
43779f8d | 3253 | static void r8153_init(struct r8152 *tp) |
3254 | { | |
3255 | u32 ocp_data; | |
3256 | int i; | |
3257 | ||
6871438c | 3258 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3259 | return; | |
3260 | ||
d70b1137 | 3261 | r8153_disable_aldps(tp); |
b9702723 | 3262 | r8153_u1u2en(tp, false); |
43779f8d | 3263 | |
3264 | for (i = 0; i < 500; i++) { | |
3265 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
3266 | AUTOLOAD_DONE) | |
3267 | break; | |
3268 | msleep(20); | |
3269 | } | |
3270 | ||
3271 | for (i = 0; i < 500; i++) { | |
3272 | ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; | |
3273 | if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) | |
3274 | break; | |
3275 | msleep(20); | |
3276 | } | |
3277 | ||
b214396f | 3278 | usb_disable_lpm(tp->udev); |
b9702723 | 3279 | r8153_u2p3en(tp, false); |
43779f8d | 3280 | |
65bab84c | 3281 | if (tp->version == RTL_VER_04) { |
3282 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); | |
3283 | ocp_data &= ~pwd_dn_scale_mask; | |
3284 | ocp_data |= pwd_dn_scale(96); | |
3285 | ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); | |
3286 | ||
3287 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); | |
3288 | ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; | |
3289 | ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); | |
3290 | } else if (tp->version == RTL_VER_05) { | |
3291 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); | |
3292 | ocp_data &= ~ECM_ALDPS; | |
3293 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); | |
3294 | ||
fb02eb4a | 3295 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); |
3296 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) | |
3297 | ocp_data &= ~DYNAMIC_BURST; | |
3298 | else | |
3299 | ocp_data |= DYNAMIC_BURST; | |
3300 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); | |
3301 | } else if (tp->version == RTL_VER_06) { | |
65bab84c | 3302 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); |
3303 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) | |
3304 | ocp_data &= ~DYNAMIC_BURST; | |
3305 | else | |
3306 | ocp_data |= DYNAMIC_BURST; | |
3307 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); | |
3308 | } | |
3309 | ||
3310 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); | |
3311 | ocp_data |= EP4_FULL_FC; | |
3312 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); | |
3313 | ||
43779f8d | 3314 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); |
3315 | ocp_data &= ~TIMER11_EN; | |
3316 | ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); | |
3317 | ||
43779f8d | 3318 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); |
3319 | ocp_data &= ~LED_MODE_MASK; | |
3320 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
3321 | ||
65bab84c | 3322 | ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; |
34203e25 | 3323 | if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER) |
43779f8d | 3324 | ocp_data |= LPM_TIMER_500MS; |
34203e25 | 3325 | else |
3326 | ocp_data |= LPM_TIMER_500US; | |
43779f8d | 3327 | ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); |
3328 | ||
3329 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); | |
3330 | ocp_data &= ~SEN_VAL_MASK; | |
3331 | ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; | |
3332 | ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); | |
3333 | ||
65bab84c | 3334 | ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); |
3335 | ||
b9702723 | 3336 | r8153_power_cut_en(tp, false); |
3337 | r8153_u1u2en(tp, true); | |
43779f8d | 3338 | |
43779f8d | 3339 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO); |
3340 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO); | |
3341 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, | |
3342 | PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | | |
3343 | U1U2_SPDWN_EN | L1_SPDWN_EN); | |
3344 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, | |
3345 | PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | | |
3346 | TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN | | |
3347 | EEE_SPDWN_EN); | |
3348 | ||
3349 | r8153_enable_eee(tp); | |
3350 | r8153_enable_aldps(tp); | |
3351 | r8152b_enable_fc(tp); | |
4f1d4d54 | 3352 | rtl_tally_reset(tp); |
b214396f | 3353 | r8153_u2p3en(tp, true); |
43779f8d | 3354 | } |
3355 | ||
e501139a | 3356 | static int rtl8152_pre_reset(struct usb_interface *intf) |
3357 | { | |
3358 | struct r8152 *tp = usb_get_intfdata(intf); | |
3359 | struct net_device *netdev; | |
3360 | ||
3361 | if (!tp) | |
3362 | return 0; | |
3363 | ||
3364 | netdev = tp->netdev; | |
3365 | if (!netif_running(netdev)) | |
3366 | return 0; | |
3367 | ||
3368 | napi_disable(&tp->napi); | |
3369 | clear_bit(WORK_ENABLE, &tp->flags); | |
3370 | usb_kill_urb(tp->intr_urb); | |
3371 | cancel_delayed_work_sync(&tp->schedule); | |
3372 | if (netif_carrier_ok(netdev)) { | |
3373 | netif_stop_queue(netdev); | |
3374 | mutex_lock(&tp->control); | |
3375 | tp->rtl_ops.disable(tp); | |
3376 | mutex_unlock(&tp->control); | |
3377 | } | |
3378 | ||
3379 | return 0; | |
3380 | } | |
3381 | ||
3382 | static int rtl8152_post_reset(struct usb_interface *intf) | |
3383 | { | |
3384 | struct r8152 *tp = usb_get_intfdata(intf); | |
3385 | struct net_device *netdev; | |
3386 | ||
3387 | if (!tp) | |
3388 | return 0; | |
3389 | ||
3390 | netdev = tp->netdev; | |
3391 | if (!netif_running(netdev)) | |
3392 | return 0; | |
3393 | ||
3394 | set_bit(WORK_ENABLE, &tp->flags); | |
3395 | if (netif_carrier_ok(netdev)) { | |
3396 | mutex_lock(&tp->control); | |
3397 | tp->rtl_ops.enable(tp); | |
3398 | rtl8152_set_rx_mode(netdev); | |
3399 | mutex_unlock(&tp->control); | |
3400 | netif_wake_queue(netdev); | |
3401 | } | |
3402 | ||
3403 | napi_enable(&tp->napi); | |
3404 | ||
3405 | return 0; | |
43779f8d | 3406 | } |
3407 | ||
ac718b69 | 3408 | static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) |
3409 | { | |
3410 | struct r8152 *tp = usb_get_intfdata(intf); | |
6cc69f2a | 3411 | struct net_device *netdev = tp->netdev; |
3412 | int ret = 0; | |
ac718b69 | 3413 | |
b5403273 | 3414 | mutex_lock(&tp->control); |
3415 | ||
6cc69f2a | 3416 | if (PMSG_IS_AUTO(message)) { |
3417 | if (netif_running(netdev) && work_busy(&tp->schedule.work)) { | |
3418 | ret = -EBUSY; | |
3419 | goto out1; | |
3420 | } | |
3421 | ||
9a4be1bd | 3422 | set_bit(SELECTIVE_SUSPEND, &tp->flags); |
6cc69f2a | 3423 | } else { |
3424 | netif_device_detach(netdev); | |
3425 | } | |
ac718b69 | 3426 | |
e3bd1a81 | 3427 | if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { |
ac718b69 | 3428 | clear_bit(WORK_ENABLE, &tp->flags); |
40a82917 | 3429 | usb_kill_urb(tp->intr_urb); |
d823ab68 | 3430 | napi_disable(&tp->napi); |
9a4be1bd | 3431 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
445f7f4d | 3432 | rtl_stop_rx(tp); |
9a4be1bd | 3433 | rtl_runtime_suspend_enable(tp, true); |
3434 | } else { | |
6cc69f2a | 3435 | cancel_delayed_work_sync(&tp->schedule); |
9a4be1bd | 3436 | tp->rtl_ops.down(tp); |
9a4be1bd | 3437 | } |
d823ab68 | 3438 | napi_enable(&tp->napi); |
ac718b69 | 3439 | } |
6cc69f2a | 3440 | out1: |
b5403273 | 3441 | mutex_unlock(&tp->control); |
3442 | ||
6cc69f2a | 3443 | return ret; |
ac718b69 | 3444 | } |
3445 | ||
3446 | static int rtl8152_resume(struct usb_interface *intf) | |
3447 | { | |
3448 | struct r8152 *tp = usb_get_intfdata(intf); | |
3449 | ||
b5403273 | 3450 | mutex_lock(&tp->control); |
3451 | ||
9a4be1bd | 3452 | if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
3453 | tp->rtl_ops.init(tp); | |
3454 | netif_device_attach(tp->netdev); | |
3455 | } | |
3456 | ||
ac718b69 | 3457 | if (netif_running(tp->netdev)) { |
9a4be1bd | 3458 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
3459 | rtl_runtime_suspend_enable(tp, false); | |
3460 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
41cec84c | 3461 | napi_disable(&tp->napi); |
445f7f4d | 3462 | set_bit(WORK_ENABLE, &tp->flags); |
51d979fa | 3463 | if (netif_carrier_ok(tp->netdev)) |
445f7f4d | 3464 | rtl_start_rx(tp); |
41cec84c | 3465 | napi_enable(&tp->napi); |
9a4be1bd | 3466 | } else { |
3467 | tp->rtl_ops.up(tp); | |
3468 | rtl8152_set_speed(tp, AUTONEG_ENABLE, | |
b209af99 | 3469 | tp->mii.supports_gmii ? |
3470 | SPEED_1000 : SPEED_100, | |
3471 | DUPLEX_FULL); | |
445f7f4d | 3472 | netif_carrier_off(tp->netdev); |
3473 | set_bit(WORK_ENABLE, &tp->flags); | |
9a4be1bd | 3474 | } |
40a82917 | 3475 | usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
923e1ee3 | 3476 | } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
3477 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
ac718b69 | 3478 | } |
3479 | ||
b5403273 | 3480 | mutex_unlock(&tp->control); |
3481 | ||
ac718b69 | 3482 | return 0; |
3483 | } | |
3484 | ||
21ff2e89 | 3485 | static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
3486 | { | |
3487 | struct r8152 *tp = netdev_priv(dev); | |
3488 | ||
9a4be1bd | 3489 | if (usb_autopm_get_interface(tp->intf) < 0) |
3490 | return; | |
3491 | ||
7daed8dc | 3492 | if (!rtl_can_wakeup(tp)) { |
3493 | wol->supported = 0; | |
3494 | wol->wolopts = 0; | |
3495 | } else { | |
3496 | mutex_lock(&tp->control); | |
3497 | wol->supported = WAKE_ANY; | |
3498 | wol->wolopts = __rtl_get_wol(tp); | |
3499 | mutex_unlock(&tp->control); | |
3500 | } | |
b5403273 | 3501 | |
9a4be1bd | 3502 | usb_autopm_put_interface(tp->intf); |
21ff2e89 | 3503 | } |
3504 | ||
3505 | static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
3506 | { | |
3507 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 3508 | int ret; |
3509 | ||
7daed8dc | 3510 | if (!rtl_can_wakeup(tp)) |
3511 | return -EOPNOTSUPP; | |
3512 | ||
9a4be1bd | 3513 | ret = usb_autopm_get_interface(tp->intf); |
3514 | if (ret < 0) | |
3515 | goto out_set_wol; | |
21ff2e89 | 3516 | |
b5403273 | 3517 | mutex_lock(&tp->control); |
3518 | ||
21ff2e89 | 3519 | __rtl_set_wol(tp, wol->wolopts); |
3520 | tp->saved_wolopts = wol->wolopts & WAKE_ANY; | |
3521 | ||
b5403273 | 3522 | mutex_unlock(&tp->control); |
3523 | ||
9a4be1bd | 3524 | usb_autopm_put_interface(tp->intf); |
3525 | ||
3526 | out_set_wol: | |
3527 | return ret; | |
21ff2e89 | 3528 | } |
3529 | ||
a5ec27c1 | 3530 | static u32 rtl8152_get_msglevel(struct net_device *dev) |
3531 | { | |
3532 | struct r8152 *tp = netdev_priv(dev); | |
3533 | ||
3534 | return tp->msg_enable; | |
3535 | } | |
3536 | ||
3537 | static void rtl8152_set_msglevel(struct net_device *dev, u32 value) | |
3538 | { | |
3539 | struct r8152 *tp = netdev_priv(dev); | |
3540 | ||
3541 | tp->msg_enable = value; | |
3542 | } | |
3543 | ||
ac718b69 | 3544 | static void rtl8152_get_drvinfo(struct net_device *netdev, |
3545 | struct ethtool_drvinfo *info) | |
3546 | { | |
3547 | struct r8152 *tp = netdev_priv(netdev); | |
3548 | ||
b0b46c77 | 3549 | strlcpy(info->driver, MODULENAME, sizeof(info->driver)); |
3550 | strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); | |
ac718b69 | 3551 | usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); |
3552 | } | |
3553 | ||
3554 | static | |
3555 | int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) | |
3556 | { | |
3557 | struct r8152 *tp = netdev_priv(netdev); | |
8d4a4d72 | 3558 | int ret; |
ac718b69 | 3559 | |
3560 | if (!tp->mii.mdio_read) | |
3561 | return -EOPNOTSUPP; | |
3562 | ||
8d4a4d72 | 3563 | ret = usb_autopm_get_interface(tp->intf); |
3564 | if (ret < 0) | |
3565 | goto out; | |
3566 | ||
b5403273 | 3567 | mutex_lock(&tp->control); |
3568 | ||
8d4a4d72 | 3569 | ret = mii_ethtool_gset(&tp->mii, cmd); |
3570 | ||
b5403273 | 3571 | mutex_unlock(&tp->control); |
3572 | ||
8d4a4d72 | 3573 | usb_autopm_put_interface(tp->intf); |
3574 | ||
3575 | out: | |
3576 | return ret; | |
ac718b69 | 3577 | } |
3578 | ||
3579 | static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
3580 | { | |
3581 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 3582 | int ret; |
3583 | ||
3584 | ret = usb_autopm_get_interface(tp->intf); | |
3585 | if (ret < 0) | |
3586 | goto out; | |
ac718b69 | 3587 | |
b5403273 | 3588 | mutex_lock(&tp->control); |
3589 | ||
9a4be1bd | 3590 | ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); |
3591 | ||
b5403273 | 3592 | mutex_unlock(&tp->control); |
3593 | ||
9a4be1bd | 3594 | usb_autopm_put_interface(tp->intf); |
3595 | ||
3596 | out: | |
3597 | return ret; | |
ac718b69 | 3598 | } |
3599 | ||
4f1d4d54 | 3600 | static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { |
3601 | "tx_packets", | |
3602 | "rx_packets", | |
3603 | "tx_errors", | |
3604 | "rx_errors", | |
3605 | "rx_missed", | |
3606 | "align_errors", | |
3607 | "tx_single_collisions", | |
3608 | "tx_multi_collisions", | |
3609 | "rx_unicast", | |
3610 | "rx_broadcast", | |
3611 | "rx_multicast", | |
3612 | "tx_aborted", | |
3613 | "tx_underrun", | |
3614 | }; | |
3615 | ||
3616 | static int rtl8152_get_sset_count(struct net_device *dev, int sset) | |
3617 | { | |
3618 | switch (sset) { | |
3619 | case ETH_SS_STATS: | |
3620 | return ARRAY_SIZE(rtl8152_gstrings); | |
3621 | default: | |
3622 | return -EOPNOTSUPP; | |
3623 | } | |
3624 | } | |
3625 | ||
3626 | static void rtl8152_get_ethtool_stats(struct net_device *dev, | |
3627 | struct ethtool_stats *stats, u64 *data) | |
3628 | { | |
3629 | struct r8152 *tp = netdev_priv(dev); | |
3630 | struct tally_counter tally; | |
3631 | ||
0b030244 | 3632 | if (usb_autopm_get_interface(tp->intf) < 0) |
3633 | return; | |
3634 | ||
4f1d4d54 | 3635 | generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); |
3636 | ||
0b030244 | 3637 | usb_autopm_put_interface(tp->intf); |
3638 | ||
4f1d4d54 | 3639 | data[0] = le64_to_cpu(tally.tx_packets); |
3640 | data[1] = le64_to_cpu(tally.rx_packets); | |
3641 | data[2] = le64_to_cpu(tally.tx_errors); | |
3642 | data[3] = le32_to_cpu(tally.rx_errors); | |
3643 | data[4] = le16_to_cpu(tally.rx_missed); | |
3644 | data[5] = le16_to_cpu(tally.align_errors); | |
3645 | data[6] = le32_to_cpu(tally.tx_one_collision); | |
3646 | data[7] = le32_to_cpu(tally.tx_multi_collision); | |
3647 | data[8] = le64_to_cpu(tally.rx_unicast); | |
3648 | data[9] = le64_to_cpu(tally.rx_broadcast); | |
3649 | data[10] = le32_to_cpu(tally.rx_multicast); | |
3650 | data[11] = le16_to_cpu(tally.tx_aborted); | |
f37119c5 | 3651 | data[12] = le16_to_cpu(tally.tx_underrun); |
4f1d4d54 | 3652 | } |
3653 | ||
3654 | static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
3655 | { | |
3656 | switch (stringset) { | |
3657 | case ETH_SS_STATS: | |
3658 | memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); | |
3659 | break; | |
3660 | } | |
3661 | } | |
3662 | ||
df35d283 | 3663 | static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) |
3664 | { | |
3665 | u32 ocp_data, lp, adv, supported = 0; | |
3666 | u16 val; | |
3667 | ||
3668 | val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); | |
3669 | supported = mmd_eee_cap_to_ethtool_sup_t(val); | |
3670 | ||
3671 | val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); | |
3672 | adv = mmd_eee_adv_to_ethtool_adv_t(val); | |
3673 | ||
3674 | val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); | |
3675 | lp = mmd_eee_adv_to_ethtool_adv_t(val); | |
3676 | ||
3677 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
3678 | ocp_data &= EEE_RX_EN | EEE_TX_EN; | |
3679 | ||
3680 | eee->eee_enabled = !!ocp_data; | |
3681 | eee->eee_active = !!(supported & adv & lp); | |
3682 | eee->supported = supported; | |
3683 | eee->advertised = adv; | |
3684 | eee->lp_advertised = lp; | |
3685 | ||
3686 | return 0; | |
3687 | } | |
3688 | ||
3689 | static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
3690 | { | |
3691 | u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); | |
3692 | ||
3693 | r8152_eee_en(tp, eee->eee_enabled); | |
3694 | ||
3695 | if (!eee->eee_enabled) | |
3696 | val = 0; | |
3697 | ||
3698 | r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); | |
3699 | ||
3700 | return 0; | |
3701 | } | |
3702 | ||
3703 | static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
3704 | { | |
3705 | u32 ocp_data, lp, adv, supported = 0; | |
3706 | u16 val; | |
3707 | ||
3708 | val = ocp_reg_read(tp, OCP_EEE_ABLE); | |
3709 | supported = mmd_eee_cap_to_ethtool_sup_t(val); | |
3710 | ||
3711 | val = ocp_reg_read(tp, OCP_EEE_ADV); | |
3712 | adv = mmd_eee_adv_to_ethtool_adv_t(val); | |
3713 | ||
3714 | val = ocp_reg_read(tp, OCP_EEE_LPABLE); | |
3715 | lp = mmd_eee_adv_to_ethtool_adv_t(val); | |
3716 | ||
3717 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
3718 | ocp_data &= EEE_RX_EN | EEE_TX_EN; | |
3719 | ||
3720 | eee->eee_enabled = !!ocp_data; | |
3721 | eee->eee_active = !!(supported & adv & lp); | |
3722 | eee->supported = supported; | |
3723 | eee->advertised = adv; | |
3724 | eee->lp_advertised = lp; | |
3725 | ||
3726 | return 0; | |
3727 | } | |
3728 | ||
3729 | static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
3730 | { | |
3731 | u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); | |
3732 | ||
3733 | r8153_eee_en(tp, eee->eee_enabled); | |
3734 | ||
3735 | if (!eee->eee_enabled) | |
3736 | val = 0; | |
3737 | ||
3738 | ocp_reg_write(tp, OCP_EEE_ADV, val); | |
3739 | ||
3740 | return 0; | |
3741 | } | |
3742 | ||
3743 | static int | |
3744 | rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) | |
3745 | { | |
3746 | struct r8152 *tp = netdev_priv(net); | |
3747 | int ret; | |
3748 | ||
3749 | ret = usb_autopm_get_interface(tp->intf); | |
3750 | if (ret < 0) | |
3751 | goto out; | |
3752 | ||
b5403273 | 3753 | mutex_lock(&tp->control); |
3754 | ||
df35d283 | 3755 | ret = tp->rtl_ops.eee_get(tp, edata); |
3756 | ||
b5403273 | 3757 | mutex_unlock(&tp->control); |
3758 | ||
df35d283 | 3759 | usb_autopm_put_interface(tp->intf); |
3760 | ||
3761 | out: | |
3762 | return ret; | |
3763 | } | |
3764 | ||
3765 | static int | |
3766 | rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) | |
3767 | { | |
3768 | struct r8152 *tp = netdev_priv(net); | |
3769 | int ret; | |
3770 | ||
3771 | ret = usb_autopm_get_interface(tp->intf); | |
3772 | if (ret < 0) | |
3773 | goto out; | |
3774 | ||
b5403273 | 3775 | mutex_lock(&tp->control); |
3776 | ||
df35d283 | 3777 | ret = tp->rtl_ops.eee_set(tp, edata); |
9d31a7b9 | 3778 | if (!ret) |
3779 | ret = mii_nway_restart(&tp->mii); | |
df35d283 | 3780 | |
b5403273 | 3781 | mutex_unlock(&tp->control); |
3782 | ||
df35d283 | 3783 | usb_autopm_put_interface(tp->intf); |
3784 | ||
3785 | out: | |
3786 | return ret; | |
3787 | } | |
3788 | ||
8884f507 | 3789 | static int rtl8152_nway_reset(struct net_device *dev) |
3790 | { | |
3791 | struct r8152 *tp = netdev_priv(dev); | |
3792 | int ret; | |
3793 | ||
3794 | ret = usb_autopm_get_interface(tp->intf); | |
3795 | if (ret < 0) | |
3796 | goto out; | |
3797 | ||
3798 | mutex_lock(&tp->control); | |
3799 | ||
3800 | ret = mii_nway_restart(&tp->mii); | |
3801 | ||
3802 | mutex_unlock(&tp->control); | |
3803 | ||
3804 | usb_autopm_put_interface(tp->intf); | |
3805 | ||
3806 | out: | |
3807 | return ret; | |
3808 | } | |
3809 | ||
efb3dd88 | 3810 | static int rtl8152_get_coalesce(struct net_device *netdev, |
3811 | struct ethtool_coalesce *coalesce) | |
3812 | { | |
3813 | struct r8152 *tp = netdev_priv(netdev); | |
3814 | ||
3815 | switch (tp->version) { | |
3816 | case RTL_VER_01: | |
3817 | case RTL_VER_02: | |
3818 | return -EOPNOTSUPP; | |
3819 | default: | |
3820 | break; | |
3821 | } | |
3822 | ||
3823 | coalesce->rx_coalesce_usecs = tp->coalesce; | |
3824 | ||
3825 | return 0; | |
3826 | } | |
3827 | ||
3828 | static int rtl8152_set_coalesce(struct net_device *netdev, | |
3829 | struct ethtool_coalesce *coalesce) | |
3830 | { | |
3831 | struct r8152 *tp = netdev_priv(netdev); | |
3832 | int ret; | |
3833 | ||
3834 | switch (tp->version) { | |
3835 | case RTL_VER_01: | |
3836 | case RTL_VER_02: | |
3837 | return -EOPNOTSUPP; | |
3838 | default: | |
3839 | break; | |
3840 | } | |
3841 | ||
3842 | if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) | |
3843 | return -EINVAL; | |
3844 | ||
3845 | ret = usb_autopm_get_interface(tp->intf); | |
3846 | if (ret < 0) | |
3847 | return ret; | |
3848 | ||
3849 | mutex_lock(&tp->control); | |
3850 | ||
3851 | if (tp->coalesce != coalesce->rx_coalesce_usecs) { | |
3852 | tp->coalesce = coalesce->rx_coalesce_usecs; | |
3853 | ||
3854 | if (netif_running(tp->netdev) && netif_carrier_ok(netdev)) | |
3855 | r8153_set_rx_early_timeout(tp); | |
3856 | } | |
3857 | ||
3858 | mutex_unlock(&tp->control); | |
3859 | ||
3860 | usb_autopm_put_interface(tp->intf); | |
3861 | ||
3862 | return ret; | |
3863 | } | |
3864 | ||
ac718b69 | 3865 | static struct ethtool_ops ops = { |
3866 | .get_drvinfo = rtl8152_get_drvinfo, | |
3867 | .get_settings = rtl8152_get_settings, | |
3868 | .set_settings = rtl8152_set_settings, | |
3869 | .get_link = ethtool_op_get_link, | |
8884f507 | 3870 | .nway_reset = rtl8152_nway_reset, |
a5ec27c1 | 3871 | .get_msglevel = rtl8152_get_msglevel, |
3872 | .set_msglevel = rtl8152_set_msglevel, | |
21ff2e89 | 3873 | .get_wol = rtl8152_get_wol, |
3874 | .set_wol = rtl8152_set_wol, | |
4f1d4d54 | 3875 | .get_strings = rtl8152_get_strings, |
3876 | .get_sset_count = rtl8152_get_sset_count, | |
3877 | .get_ethtool_stats = rtl8152_get_ethtool_stats, | |
efb3dd88 | 3878 | .get_coalesce = rtl8152_get_coalesce, |
3879 | .set_coalesce = rtl8152_set_coalesce, | |
df35d283 | 3880 | .get_eee = rtl_ethtool_get_eee, |
3881 | .set_eee = rtl_ethtool_set_eee, | |
ac718b69 | 3882 | }; |
3883 | ||
3884 | static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) | |
3885 | { | |
3886 | struct r8152 *tp = netdev_priv(netdev); | |
3887 | struct mii_ioctl_data *data = if_mii(rq); | |
9a4be1bd | 3888 | int res; |
3889 | ||
6871438c | 3890 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3891 | return -ENODEV; | |
3892 | ||
9a4be1bd | 3893 | res = usb_autopm_get_interface(tp->intf); |
3894 | if (res < 0) | |
3895 | goto out; | |
ac718b69 | 3896 | |
3897 | switch (cmd) { | |
3898 | case SIOCGMIIPHY: | |
3899 | data->phy_id = R8152_PHY_ID; /* Internal PHY */ | |
3900 | break; | |
3901 | ||
3902 | case SIOCGMIIREG: | |
b5403273 | 3903 | mutex_lock(&tp->control); |
ac718b69 | 3904 | data->val_out = r8152_mdio_read(tp, data->reg_num); |
b5403273 | 3905 | mutex_unlock(&tp->control); |
ac718b69 | 3906 | break; |
3907 | ||
3908 | case SIOCSMIIREG: | |
3909 | if (!capable(CAP_NET_ADMIN)) { | |
3910 | res = -EPERM; | |
3911 | break; | |
3912 | } | |
b5403273 | 3913 | mutex_lock(&tp->control); |
ac718b69 | 3914 | r8152_mdio_write(tp, data->reg_num, data->val_in); |
b5403273 | 3915 | mutex_unlock(&tp->control); |
ac718b69 | 3916 | break; |
3917 | ||
3918 | default: | |
3919 | res = -EOPNOTSUPP; | |
3920 | } | |
3921 | ||
9a4be1bd | 3922 | usb_autopm_put_interface(tp->intf); |
3923 | ||
3924 | out: | |
ac718b69 | 3925 | return res; |
3926 | } | |
3927 | ||
69b4b7a4 | 3928 | static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) |
3929 | { | |
3930 | struct r8152 *tp = netdev_priv(dev); | |
396e2e23 | 3931 | int ret; |
69b4b7a4 | 3932 | |
3933 | switch (tp->version) { | |
3934 | case RTL_VER_01: | |
3935 | case RTL_VER_02: | |
3936 | return eth_change_mtu(dev, new_mtu); | |
3937 | default: | |
3938 | break; | |
3939 | } | |
3940 | ||
3941 | if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU) | |
3942 | return -EINVAL; | |
3943 | ||
396e2e23 | 3944 | ret = usb_autopm_get_interface(tp->intf); |
3945 | if (ret < 0) | |
3946 | return ret; | |
3947 | ||
3948 | mutex_lock(&tp->control); | |
3949 | ||
69b4b7a4 | 3950 | dev->mtu = new_mtu; |
3951 | ||
396e2e23 | 3952 | if (netif_running(dev) && netif_carrier_ok(dev)) |
3953 | r8153_set_rx_early_size(tp); | |
3954 | ||
3955 | mutex_unlock(&tp->control); | |
3956 | ||
3957 | usb_autopm_put_interface(tp->intf); | |
3958 | ||
3959 | return ret; | |
69b4b7a4 | 3960 | } |
3961 | ||
ac718b69 | 3962 | static const struct net_device_ops rtl8152_netdev_ops = { |
3963 | .ndo_open = rtl8152_open, | |
3964 | .ndo_stop = rtl8152_close, | |
3965 | .ndo_do_ioctl = rtl8152_ioctl, | |
3966 | .ndo_start_xmit = rtl8152_start_xmit, | |
3967 | .ndo_tx_timeout = rtl8152_tx_timeout, | |
c5554298 | 3968 | .ndo_set_features = rtl8152_set_features, |
ac718b69 | 3969 | .ndo_set_rx_mode = rtl8152_set_rx_mode, |
3970 | .ndo_set_mac_address = rtl8152_set_mac_address, | |
69b4b7a4 | 3971 | .ndo_change_mtu = rtl8152_change_mtu, |
ac718b69 | 3972 | .ndo_validate_addr = eth_validate_addr, |
a5e31255 | 3973 | .ndo_features_check = rtl8152_features_check, |
ac718b69 | 3974 | }; |
3975 | ||
3976 | static void r8152b_get_version(struct r8152 *tp) | |
3977 | { | |
3978 | u32 ocp_data; | |
3979 | u16 version; | |
3980 | ||
3981 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); | |
3982 | version = (u16)(ocp_data & VERSION_MASK); | |
3983 | ||
3984 | switch (version) { | |
3985 | case 0x4c00: | |
3986 | tp->version = RTL_VER_01; | |
3987 | break; | |
3988 | case 0x4c10: | |
3989 | tp->version = RTL_VER_02; | |
3990 | break; | |
43779f8d | 3991 | case 0x5c00: |
3992 | tp->version = RTL_VER_03; | |
3993 | tp->mii.supports_gmii = 1; | |
3994 | break; | |
3995 | case 0x5c10: | |
3996 | tp->version = RTL_VER_04; | |
3997 | tp->mii.supports_gmii = 1; | |
3998 | break; | |
3999 | case 0x5c20: | |
4000 | tp->version = RTL_VER_05; | |
4001 | tp->mii.supports_gmii = 1; | |
4002 | break; | |
fb02eb4a | 4003 | case 0x5c30: |
4004 | tp->version = RTL_VER_06; | |
4005 | tp->mii.supports_gmii = 1; | |
4006 | break; | |
ac718b69 | 4007 | default: |
4008 | netif_info(tp, probe, tp->netdev, | |
4009 | "Unknown version 0x%04x\n", version); | |
4010 | break; | |
4011 | } | |
4012 | } | |
4013 | ||
e3fe0b1a | 4014 | static void rtl8152_unload(struct r8152 *tp) |
4015 | { | |
6871438c | 4016 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
4017 | return; | |
4018 | ||
00a5e360 | 4019 | if (tp->version != RTL_VER_01) |
4020 | r8152_power_cut_en(tp, true); | |
e3fe0b1a | 4021 | } |
4022 | ||
43779f8d | 4023 | static void rtl8153_unload(struct r8152 *tp) |
4024 | { | |
6871438c | 4025 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
4026 | return; | |
4027 | ||
49be1723 | 4028 | r8153_power_cut_en(tp, false); |
43779f8d | 4029 | } |
4030 | ||
55b65475 | 4031 | static int rtl_ops_init(struct r8152 *tp) |
c81229c9 | 4032 | { |
4033 | struct rtl_ops *ops = &tp->rtl_ops; | |
55b65475 | 4034 | int ret = 0; |
4035 | ||
4036 | switch (tp->version) { | |
4037 | case RTL_VER_01: | |
4038 | case RTL_VER_02: | |
4039 | ops->init = r8152b_init; | |
4040 | ops->enable = rtl8152_enable; | |
4041 | ops->disable = rtl8152_disable; | |
4042 | ops->up = rtl8152_up; | |
4043 | ops->down = rtl8152_down; | |
4044 | ops->unload = rtl8152_unload; | |
4045 | ops->eee_get = r8152_get_eee; | |
4046 | ops->eee_set = r8152_set_eee; | |
43779f8d | 4047 | break; |
4048 | ||
55b65475 | 4049 | case RTL_VER_03: |
4050 | case RTL_VER_04: | |
4051 | case RTL_VER_05: | |
fb02eb4a | 4052 | case RTL_VER_06: |
55b65475 | 4053 | ops->init = r8153_init; |
4054 | ops->enable = rtl8153_enable; | |
4055 | ops->disable = rtl8153_disable; | |
4056 | ops->up = rtl8153_up; | |
4057 | ops->down = rtl8153_down; | |
4058 | ops->unload = rtl8153_unload; | |
4059 | ops->eee_get = r8153_get_eee; | |
4060 | ops->eee_set = r8153_set_eee; | |
c81229c9 | 4061 | break; |
4062 | ||
4063 | default: | |
55b65475 | 4064 | ret = -ENODEV; |
4065 | netif_err(tp, probe, tp->netdev, "Unknown Device\n"); | |
c81229c9 | 4066 | break; |
4067 | } | |
4068 | ||
4069 | return ret; | |
4070 | } | |
4071 | ||
ac718b69 | 4072 | static int rtl8152_probe(struct usb_interface *intf, |
4073 | const struct usb_device_id *id) | |
4074 | { | |
4075 | struct usb_device *udev = interface_to_usbdev(intf); | |
4076 | struct r8152 *tp; | |
4077 | struct net_device *netdev; | |
ebc2ec48 | 4078 | int ret; |
ac718b69 | 4079 | |
10c32717 | 4080 | if (udev->actconfig->desc.bConfigurationValue != 1) { |
4081 | usb_driver_set_configuration(udev, 1); | |
4082 | return -ENODEV; | |
4083 | } | |
4084 | ||
4085 | usb_reset_device(udev); | |
ac718b69 | 4086 | netdev = alloc_etherdev(sizeof(struct r8152)); |
4087 | if (!netdev) { | |
4a8deae2 | 4088 | dev_err(&intf->dev, "Out of memory\n"); |
ac718b69 | 4089 | return -ENOMEM; |
4090 | } | |
4091 | ||
ebc2ec48 | 4092 | SET_NETDEV_DEV(netdev, &intf->dev); |
ac718b69 | 4093 | tp = netdev_priv(netdev); |
4094 | tp->msg_enable = 0x7FFF; | |
4095 | ||
e3ad412a | 4096 | tp->udev = udev; |
4097 | tp->netdev = netdev; | |
4098 | tp->intf = intf; | |
4099 | ||
82cf94cb | 4100 | r8152b_get_version(tp); |
55b65475 | 4101 | ret = rtl_ops_init(tp); |
31ca1dec | 4102 | if (ret) |
4103 | goto out; | |
c81229c9 | 4104 | |
b5403273 | 4105 | mutex_init(&tp->control); |
ac718b69 | 4106 | INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); |
4107 | ||
ac718b69 | 4108 | netdev->netdev_ops = &rtl8152_netdev_ops; |
4109 | netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; | |
5bd23881 | 4110 | |
60c89071 | 4111 | netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 4112 | NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | |
c5554298 | 4113 | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | |
4114 | NETIF_F_HW_VLAN_CTAG_TX; | |
60c89071 | 4115 | netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 4116 | NETIF_F_TSO | NETIF_F_FRAGLIST | |
c5554298 | 4117 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | |
ccc39faf | 4118 | NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; |
c5554298 | 4119 | netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | |
4120 | NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | | |
4121 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6; | |
db8515ef | 4122 | |
7ad24ea4 | 4123 | netdev->ethtool_ops = &ops; |
60c89071 | 4124 | netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); |
ac718b69 | 4125 | |
4126 | tp->mii.dev = netdev; | |
4127 | tp->mii.mdio_read = read_mii_word; | |
4128 | tp->mii.mdio_write = write_mii_word; | |
4129 | tp->mii.phy_id_mask = 0x3f; | |
4130 | tp->mii.reg_num_mask = 0x1f; | |
4131 | tp->mii.phy_id = R8152_PHY_ID; | |
ac718b69 | 4132 | |
464ec10a | 4133 | switch (udev->speed) { |
4134 | case USB_SPEED_SUPER: | |
4135 | tp->coalesce = COALESCE_SUPER; | |
4136 | break; | |
4137 | case USB_SPEED_HIGH: | |
4138 | tp->coalesce = COALESCE_HIGH; | |
4139 | break; | |
4140 | default: | |
4141 | tp->coalesce = COALESCE_SLOW; | |
4142 | break; | |
4143 | } | |
4144 | ||
9a4be1bd | 4145 | intf->needs_remote_wakeup = 1; |
4146 | ||
c81229c9 | 4147 | tp->rtl_ops.init(tp); |
ac718b69 | 4148 | set_ethernet_addr(tp); |
4149 | ||
ac718b69 | 4150 | usb_set_intfdata(intf, tp); |
d823ab68 | 4151 | netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); |
ac718b69 | 4152 | |
ebc2ec48 | 4153 | ret = register_netdev(netdev); |
4154 | if (ret != 0) { | |
4a8deae2 | 4155 | netif_err(tp, probe, netdev, "couldn't register the device\n"); |
ebc2ec48 | 4156 | goto out1; |
ac718b69 | 4157 | } |
4158 | ||
7daed8dc | 4159 | if (!rtl_can_wakeup(tp)) |
4160 | __rtl_set_wol(tp, 0); | |
4161 | ||
21ff2e89 | 4162 | tp->saved_wolopts = __rtl_get_wol(tp); |
4163 | if (tp->saved_wolopts) | |
4164 | device_set_wakeup_enable(&udev->dev, true); | |
4165 | else | |
4166 | device_set_wakeup_enable(&udev->dev, false); | |
4167 | ||
4a8deae2 | 4168 | netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); |
ac718b69 | 4169 | |
4170 | return 0; | |
4171 | ||
ac718b69 | 4172 | out1: |
d823ab68 | 4173 | netif_napi_del(&tp->napi); |
ebc2ec48 | 4174 | usb_set_intfdata(intf, NULL); |
ac718b69 | 4175 | out: |
4176 | free_netdev(netdev); | |
ebc2ec48 | 4177 | return ret; |
ac718b69 | 4178 | } |
4179 | ||
ac718b69 | 4180 | static void rtl8152_disconnect(struct usb_interface *intf) |
4181 | { | |
4182 | struct r8152 *tp = usb_get_intfdata(intf); | |
4183 | ||
4184 | usb_set_intfdata(intf, NULL); | |
4185 | if (tp) { | |
f561de33 | 4186 | struct usb_device *udev = tp->udev; |
4187 | ||
4188 | if (udev->state == USB_STATE_NOTATTACHED) | |
4189 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
4190 | ||
d823ab68 | 4191 | netif_napi_del(&tp->napi); |
ac718b69 | 4192 | unregister_netdev(tp->netdev); |
c81229c9 | 4193 | tp->rtl_ops.unload(tp); |
ac718b69 | 4194 | free_netdev(tp->netdev); |
4195 | } | |
4196 | } | |
4197 | ||
d9a28c5b | 4198 | #define REALTEK_USB_DEVICE(vend, prod) \ |
4199 | .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ | |
4200 | USB_DEVICE_ID_MATCH_INT_CLASS, \ | |
4201 | .idVendor = (vend), \ | |
4202 | .idProduct = (prod), \ | |
4203 | .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ | |
4204 | }, \ | |
4205 | { \ | |
4206 | .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ | |
4207 | USB_DEVICE_ID_MATCH_DEVICE, \ | |
4208 | .idVendor = (vend), \ | |
4209 | .idProduct = (prod), \ | |
4210 | .bInterfaceClass = USB_CLASS_COMM, \ | |
4211 | .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ | |
4212 | .bInterfaceProtocol = USB_CDC_PROTO_NONE | |
4213 | ||
ac718b69 | 4214 | /* table of devices that work with this driver */ |
4215 | static struct usb_device_id rtl8152_table[] = { | |
d9a28c5b | 4216 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, |
4217 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, | |
4218 | {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, | |
347eec34 | 4219 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, |
1006da19 | 4220 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, |
d065c3c1 | 4221 | {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)}, |
ac718b69 | 4222 | {} |
4223 | }; | |
4224 | ||
4225 | MODULE_DEVICE_TABLE(usb, rtl8152_table); | |
4226 | ||
4227 | static struct usb_driver rtl8152_driver = { | |
4228 | .name = MODULENAME, | |
ebc2ec48 | 4229 | .id_table = rtl8152_table, |
ac718b69 | 4230 | .probe = rtl8152_probe, |
4231 | .disconnect = rtl8152_disconnect, | |
ac718b69 | 4232 | .suspend = rtl8152_suspend, |
ebc2ec48 | 4233 | .resume = rtl8152_resume, |
4234 | .reset_resume = rtl8152_resume, | |
e501139a | 4235 | .pre_reset = rtl8152_pre_reset, |
4236 | .post_reset = rtl8152_post_reset, | |
9a4be1bd | 4237 | .supports_autosuspend = 1, |
a634782f | 4238 | .disable_hub_initiated_lpm = 1, |
ac718b69 | 4239 | }; |
4240 | ||
b4236daa | 4241 | module_usb_driver(rtl8152_driver); |
ac718b69 | 4242 | |
4243 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
4244 | MODULE_DESCRIPTION(DRIVER_DESC); | |
4245 | MODULE_LICENSE("GPL"); |