r8152: adjust usb_autopm_xxx
[deliverable/linux.git] / drivers / net / usb / r8152.c
CommitLineData
ac718b69 1/*
c7de7dec 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
ac718b69 3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
ac718b69 10#include <linux/signal.h>
11#include <linux/slab.h>
12#include <linux/module.h>
ac718b69 13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/mii.h>
16#include <linux/ethtool.h>
17#include <linux/usb.h>
18#include <linux/crc32.h>
19#include <linux/if_vlan.h>
20#include <linux/uaccess.h>
ebc2ec48 21#include <linux/list.h>
5bd23881 22#include <linux/ip.h>
23#include <linux/ipv6.h>
6128d1bb 24#include <net/ip6_checksum.h>
4c4a6b1b 25#include <uapi/linux/mdio.h>
26#include <linux/mdio.h>
ac718b69 27
28/* Version Information */
204c8704 29#define DRIVER_VERSION "v1.06.1 (2014/10/01)"
ac718b69 30#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
44d942a9 31#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
ac718b69 32#define MODULENAME "r8152"
33
34#define R8152_PHY_ID 32
35
36#define PLA_IDR 0xc000
37#define PLA_RCR 0xc010
38#define PLA_RMS 0xc016
39#define PLA_RXFIFO_CTRL0 0xc0a0
40#define PLA_RXFIFO_CTRL1 0xc0a4
41#define PLA_RXFIFO_CTRL2 0xc0a8
42#define PLA_FMC 0xc0b4
43#define PLA_CFG_WOL 0xc0b6
43779f8d 44#define PLA_TEREDO_CFG 0xc0bc
ac718b69 45#define PLA_MAR 0xcd00
43779f8d 46#define PLA_BACKUP 0xd000
ac718b69 47#define PAL_BDC_CR 0xd1a0
43779f8d 48#define PLA_TEREDO_TIMER 0xd2cc
49#define PLA_REALWOW_TIMER 0xd2e8
ac718b69 50#define PLA_LEDSEL 0xdd90
51#define PLA_LED_FEATURE 0xdd92
52#define PLA_PHYAR 0xde00
43779f8d 53#define PLA_BOOT_CTRL 0xe004
ac718b69 54#define PLA_GPHY_INTR_IMR 0xe022
55#define PLA_EEE_CR 0xe040
56#define PLA_EEEP_CR 0xe080
57#define PLA_MAC_PWR_CTRL 0xe0c0
43779f8d 58#define PLA_MAC_PWR_CTRL2 0xe0ca
59#define PLA_MAC_PWR_CTRL3 0xe0cc
60#define PLA_MAC_PWR_CTRL4 0xe0ce
61#define PLA_WDT6_CTRL 0xe428
ac718b69 62#define PLA_TCR0 0xe610
63#define PLA_TCR1 0xe612
69b4b7a4 64#define PLA_MTPS 0xe615
ac718b69 65#define PLA_TXFIFO_CTRL 0xe618
4f1d4d54 66#define PLA_RSTTALLY 0xe800
ac718b69 67#define PLA_CR 0xe813
68#define PLA_CRWECR 0xe81c
21ff2e89 69#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
70#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
ac718b69 71#define PLA_CONFIG5 0xe822
72#define PLA_PHY_PWR 0xe84c
73#define PLA_OOB_CTRL 0xe84f
74#define PLA_CPCR 0xe854
75#define PLA_MISC_0 0xe858
76#define PLA_MISC_1 0xe85a
77#define PLA_OCP_GPHY_BASE 0xe86c
4f1d4d54 78#define PLA_TALLYCNT 0xe890
ac718b69 79#define PLA_SFF_STS_7 0xe8de
80#define PLA_PHYSTATUS 0xe908
81#define PLA_BP_BA 0xfc26
82#define PLA_BP_0 0xfc28
83#define PLA_BP_1 0xfc2a
84#define PLA_BP_2 0xfc2c
85#define PLA_BP_3 0xfc2e
86#define PLA_BP_4 0xfc30
87#define PLA_BP_5 0xfc32
88#define PLA_BP_6 0xfc34
89#define PLA_BP_7 0xfc36
43779f8d 90#define PLA_BP_EN 0xfc38
ac718b69 91
43779f8d 92#define USB_U2P3_CTRL 0xb460
ac718b69 93#define USB_DEV_STAT 0xb808
94#define USB_USB_CTRL 0xd406
95#define USB_PHY_CTRL 0xd408
96#define USB_TX_AGG 0xd40a
97#define USB_RX_BUF_TH 0xd40c
98#define USB_USB_TIMER 0xd428
43779f8d 99#define USB_RX_EARLY_AGG 0xd42c
ac718b69 100#define USB_PM_CTRL_STATUS 0xd432
101#define USB_TX_DMA 0xd434
43779f8d 102#define USB_TOLERANCE 0xd490
103#define USB_LPM_CTRL 0xd41a
ac718b69 104#define USB_UPS_CTRL 0xd800
43779f8d 105#define USB_MISC_0 0xd81a
106#define USB_POWER_CUT 0xd80a
107#define USB_AFE_CTRL2 0xd824
108#define USB_WDT11_CTRL 0xe43c
ac718b69 109#define USB_BP_BA 0xfc26
110#define USB_BP_0 0xfc28
111#define USB_BP_1 0xfc2a
112#define USB_BP_2 0xfc2c
113#define USB_BP_3 0xfc2e
114#define USB_BP_4 0xfc30
115#define USB_BP_5 0xfc32
116#define USB_BP_6 0xfc34
117#define USB_BP_7 0xfc36
43779f8d 118#define USB_BP_EN 0xfc38
ac718b69 119
120/* OCP Registers */
121#define OCP_ALDPS_CONFIG 0x2010
122#define OCP_EEE_CONFIG1 0x2080
123#define OCP_EEE_CONFIG2 0x2092
124#define OCP_EEE_CONFIG3 0x2094
ac244d3e 125#define OCP_BASE_MII 0xa400
ac718b69 126#define OCP_EEE_AR 0xa41a
127#define OCP_EEE_DATA 0xa41c
43779f8d 128#define OCP_PHY_STATUS 0xa420
129#define OCP_POWER_CFG 0xa430
130#define OCP_EEE_CFG 0xa432
131#define OCP_SRAM_ADDR 0xa436
132#define OCP_SRAM_DATA 0xa438
133#define OCP_DOWN_SPEED 0xa442
df35d283 134#define OCP_EEE_ABLE 0xa5c4
4c4a6b1b 135#define OCP_EEE_ADV 0xa5d0
df35d283 136#define OCP_EEE_LPABLE 0xa5d2
43779f8d 137#define OCP_ADC_CFG 0xbc06
138
139/* SRAM Register */
140#define SRAM_LPF_CFG 0x8012
141#define SRAM_10M_AMP1 0x8080
142#define SRAM_10M_AMP2 0x8082
143#define SRAM_IMPEDANCE 0x8084
ac718b69 144
145/* PLA_RCR */
146#define RCR_AAP 0x00000001
147#define RCR_APM 0x00000002
148#define RCR_AM 0x00000004
149#define RCR_AB 0x00000008
150#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
151
152/* PLA_RXFIFO_CTRL0 */
153#define RXFIFO_THR1_NORMAL 0x00080002
154#define RXFIFO_THR1_OOB 0x01800003
155
156/* PLA_RXFIFO_CTRL1 */
157#define RXFIFO_THR2_FULL 0x00000060
158#define RXFIFO_THR2_HIGH 0x00000038
159#define RXFIFO_THR2_OOB 0x0000004a
43779f8d 160#define RXFIFO_THR2_NORMAL 0x00a0
ac718b69 161
162/* PLA_RXFIFO_CTRL2 */
163#define RXFIFO_THR3_FULL 0x00000078
164#define RXFIFO_THR3_HIGH 0x00000048
165#define RXFIFO_THR3_OOB 0x0000005a
43779f8d 166#define RXFIFO_THR3_NORMAL 0x0110
ac718b69 167
168/* PLA_TXFIFO_CTRL */
169#define TXFIFO_THR_NORMAL 0x00400008
43779f8d 170#define TXFIFO_THR_NORMAL2 0x01000008
ac718b69 171
172/* PLA_FMC */
173#define FMC_FCR_MCU_EN 0x0001
174
175/* PLA_EEEP_CR */
176#define EEEP_CR_EEEP_TX 0x0002
177
43779f8d 178/* PLA_WDT6_CTRL */
179#define WDT6_SET_MODE 0x0010
180
ac718b69 181/* PLA_TCR0 */
182#define TCR0_TX_EMPTY 0x0800
183#define TCR0_AUTO_FIFO 0x0080
184
185/* PLA_TCR1 */
186#define VERSION_MASK 0x7cf0
187
69b4b7a4 188/* PLA_MTPS */
189#define MTPS_JUMBO (12 * 1024 / 64)
190#define MTPS_DEFAULT (6 * 1024 / 64)
191
4f1d4d54 192/* PLA_RSTTALLY */
193#define TALLY_RESET 0x0001
194
ac718b69 195/* PLA_CR */
196#define CR_RST 0x10
197#define CR_RE 0x08
198#define CR_TE 0x04
199
200/* PLA_CRWECR */
201#define CRWECR_NORAML 0x00
202#define CRWECR_CONFIG 0xc0
203
204/* PLA_OOB_CTRL */
205#define NOW_IS_OOB 0x80
206#define TXFIFO_EMPTY 0x20
207#define RXFIFO_EMPTY 0x10
208#define LINK_LIST_READY 0x02
209#define DIS_MCU_CLROOB 0x01
210#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
211
212/* PLA_MISC_1 */
213#define RXDY_GATED_EN 0x0008
214
215/* PLA_SFF_STS_7 */
216#define RE_INIT_LL 0x8000
217#define MCU_BORW_EN 0x4000
218
219/* PLA_CPCR */
220#define CPCR_RX_VLAN 0x0040
221
222/* PLA_CFG_WOL */
223#define MAGIC_EN 0x0001
224
43779f8d 225/* PLA_TEREDO_CFG */
226#define TEREDO_SEL 0x8000
227#define TEREDO_WAKE_MASK 0x7f00
228#define TEREDO_RS_EVENT_MASK 0x00fe
229#define OOB_TEREDO_EN 0x0001
230
ac718b69 231/* PAL_BDC_CR */
232#define ALDPS_PROXY_MODE 0x0001
233
21ff2e89 234/* PLA_CONFIG34 */
235#define LINK_ON_WAKE_EN 0x0010
236#define LINK_OFF_WAKE_EN 0x0008
237
ac718b69 238/* PLA_CONFIG5 */
21ff2e89 239#define BWF_EN 0x0040
240#define MWF_EN 0x0020
241#define UWF_EN 0x0010
ac718b69 242#define LAN_WAKE_EN 0x0002
243
244/* PLA_LED_FEATURE */
245#define LED_MODE_MASK 0x0700
246
247/* PLA_PHY_PWR */
248#define TX_10M_IDLE_EN 0x0080
249#define PFM_PWM_SWITCH 0x0040
250
251/* PLA_MAC_PWR_CTRL */
252#define D3_CLK_GATED_EN 0x00004000
253#define MCU_CLK_RATIO 0x07010f07
254#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
43779f8d 255#define ALDPS_SPDWN_RATIO 0x0f87
256
257/* PLA_MAC_PWR_CTRL2 */
258#define EEE_SPDWN_RATIO 0x8007
259
260/* PLA_MAC_PWR_CTRL3 */
261#define PKT_AVAIL_SPDWN_EN 0x0100
262#define SUSPEND_SPDWN_EN 0x0004
263#define U1U2_SPDWN_EN 0x0002
264#define L1_SPDWN_EN 0x0001
265
266/* PLA_MAC_PWR_CTRL4 */
267#define PWRSAVE_SPDWN_EN 0x1000
268#define RXDV_SPDWN_EN 0x0800
269#define TX10MIDLE_EN 0x0100
270#define TP100_SPDWN_EN 0x0020
271#define TP500_SPDWN_EN 0x0010
272#define TP1000_SPDWN_EN 0x0008
273#define EEE_SPDWN_EN 0x0001
ac718b69 274
275/* PLA_GPHY_INTR_IMR */
276#define GPHY_STS_MSK 0x0001
277#define SPEED_DOWN_MSK 0x0002
278#define SPDWN_RXDV_MSK 0x0004
279#define SPDWN_LINKCHG_MSK 0x0008
280
281/* PLA_PHYAR */
282#define PHYAR_FLAG 0x80000000
283
284/* PLA_EEE_CR */
285#define EEE_RX_EN 0x0001
286#define EEE_TX_EN 0x0002
287
43779f8d 288/* PLA_BOOT_CTRL */
289#define AUTOLOAD_DONE 0x0002
290
ac718b69 291/* USB_DEV_STAT */
292#define STAT_SPEED_MASK 0x0006
293#define STAT_SPEED_HIGH 0x0000
a3cc465d 294#define STAT_SPEED_FULL 0x0002
ac718b69 295
296/* USB_TX_AGG */
297#define TX_AGG_MAX_THRESHOLD 0x03
298
299/* USB_RX_BUF_TH */
43779f8d 300#define RX_THR_SUPPER 0x0c350180
8e1f51bd 301#define RX_THR_HIGH 0x7a120180
43779f8d 302#define RX_THR_SLOW 0xffff0180
ac718b69 303
304/* USB_TX_DMA */
305#define TEST_MODE_DISABLE 0x00000001
306#define TX_SIZE_ADJUST1 0x00000100
307
308/* USB_UPS_CTRL */
309#define POWER_CUT 0x0100
310
311/* USB_PM_CTRL_STATUS */
8e1f51bd 312#define RESUME_INDICATE 0x0001
ac718b69 313
314/* USB_USB_CTRL */
315#define RX_AGG_DISABLE 0x0010
316
43779f8d 317/* USB_U2P3_CTRL */
318#define U2P3_ENABLE 0x0001
319
320/* USB_POWER_CUT */
321#define PWR_EN 0x0001
322#define PHASE2_EN 0x0008
323
324/* USB_MISC_0 */
325#define PCUT_STATUS 0x0001
326
327/* USB_RX_EARLY_AGG */
328#define EARLY_AGG_SUPPER 0x0e832981
329#define EARLY_AGG_HIGH 0x0e837a12
330#define EARLY_AGG_SLOW 0x0e83ffff
331
332/* USB_WDT11_CTRL */
333#define TIMER11_EN 0x0001
334
335/* USB_LPM_CTRL */
336#define LPM_TIMER_MASK 0x0c
337#define LPM_TIMER_500MS 0x04 /* 500 ms */
338#define LPM_TIMER_500US 0x0c /* 500 us */
339
340/* USB_AFE_CTRL2 */
341#define SEN_VAL_MASK 0xf800
342#define SEN_VAL_NORMAL 0xa000
343#define SEL_RXIDLE 0x0100
344
ac718b69 345/* OCP_ALDPS_CONFIG */
346#define ENPWRSAVE 0x8000
347#define ENPDNPS 0x0200
348#define LINKENA 0x0100
349#define DIS_SDSAVE 0x0010
350
43779f8d 351/* OCP_PHY_STATUS */
352#define PHY_STAT_MASK 0x0007
353#define PHY_STAT_LAN_ON 3
354#define PHY_STAT_PWRDN 5
355
356/* OCP_POWER_CFG */
357#define EEE_CLKDIV_EN 0x8000
358#define EN_ALDPS 0x0004
359#define EN_10M_PLLOFF 0x0001
360
ac718b69 361/* OCP_EEE_CONFIG1 */
362#define RG_TXLPI_MSK_HFDUP 0x8000
363#define RG_MATCLR_EN 0x4000
364#define EEE_10_CAP 0x2000
365#define EEE_NWAY_EN 0x1000
366#define TX_QUIET_EN 0x0200
367#define RX_QUIET_EN 0x0100
d24f6134 368#define sd_rise_time_mask 0x0070
4c4a6b1b 369#define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
ac718b69 370#define RG_RXLPI_MSK_HFDUP 0x0008
371#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
372
373/* OCP_EEE_CONFIG2 */
374#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
375#define RG_DACQUIET_EN 0x0400
376#define RG_LDVQUIET_EN 0x0200
377#define RG_CKRSEL 0x0020
378#define RG_EEEPRG_EN 0x0010
379
380/* OCP_EEE_CONFIG3 */
d24f6134 381#define fast_snr_mask 0xff80
4c4a6b1b 382#define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
ac718b69 383#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
384#define MSK_PH 0x0006 /* bit 0 ~ 3 */
385
386/* OCP_EEE_AR */
387/* bit[15:14] function */
388#define FUN_ADDR 0x0000
389#define FUN_DATA 0x4000
390/* bit[4:0] device addr */
ac718b69 391
43779f8d 392/* OCP_EEE_CFG */
393#define CTAP_SHORT_EN 0x0040
394#define EEE10_EN 0x0010
395
396/* OCP_DOWN_SPEED */
397#define EN_10M_BGOFF 0x0080
398
43779f8d 399/* OCP_ADC_CFG */
400#define CKADSEL_L 0x0100
401#define ADC_EN 0x0080
402#define EN_EMI_L 0x0040
403
404/* SRAM_LPF_CFG */
405#define LPF_AUTO_TUNE 0x8000
406
407/* SRAM_10M_AMP1 */
408#define GDAC_IB_UPALL 0x0008
409
410/* SRAM_10M_AMP2 */
411#define AMP_DN 0x0200
412
413/* SRAM_IMPEDANCE */
414#define RX_DRIVING_MASK 0x6000
415
ac718b69 416enum rtl_register_content {
43779f8d 417 _1000bps = 0x10,
ac718b69 418 _100bps = 0x08,
419 _10bps = 0x04,
420 LINK_STATUS = 0x02,
421 FULL_DUP = 0x01,
422};
423
1764bcd9 424#define RTL8152_MAX_TX 4
ebc2ec48 425#define RTL8152_MAX_RX 10
40a82917 426#define INTBUFSIZE 2
8e1f51bd 427#define CRC_SIZE 4
428#define TX_ALIGN 4
429#define RX_ALIGN 8
40a82917 430
431#define INTR_LINK 0x0004
ebc2ec48 432
ac718b69 433#define RTL8152_REQT_READ 0xc0
434#define RTL8152_REQT_WRITE 0x40
435#define RTL8152_REQ_GET_REGS 0x05
436#define RTL8152_REQ_SET_REGS 0x05
437
438#define BYTE_EN_DWORD 0xff
439#define BYTE_EN_WORD 0x33
440#define BYTE_EN_BYTE 0x11
441#define BYTE_EN_SIX_BYTES 0x3f
442#define BYTE_EN_START_MASK 0x0f
443#define BYTE_EN_END_MASK 0xf0
444
69b4b7a4 445#define RTL8153_MAX_PACKET 9216 /* 9K */
446#define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
ac718b69 447#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
69b4b7a4 448#define RTL8153_RMS RTL8153_MAX_PACKET
b8125404 449#define RTL8152_TX_TIMEOUT (5 * HZ)
ac718b69 450
451/* rtl8152 flags */
452enum rtl8152_flags {
453 RTL8152_UNPLUG = 0,
ac718b69 454 RTL8152_SET_RX_MODE,
40a82917 455 WORK_ENABLE,
456 RTL8152_LINK_CHG,
9a4be1bd 457 SELECTIVE_SUSPEND,
aa66a5f1 458 PHY_RESET,
0c3121fc 459 SCHEDULE_TASKLET,
ac718b69 460};
461
462/* Define these values to match your device */
463#define VENDOR_ID_REALTEK 0x0bda
464#define PRODUCT_ID_RTL8152 0x8152
43779f8d 465#define PRODUCT_ID_RTL8153 0x8153
466
467#define VENDOR_ID_SAMSUNG 0x04e8
468#define PRODUCT_ID_SAMSUNG 0xa101
ac718b69 469
470#define MCU_TYPE_PLA 0x0100
471#define MCU_TYPE_USB 0x0000
472
c7de7dec 473#define REALTEK_USB_DEVICE(vend, prod) \
474 USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC)
475
4f1d4d54 476struct tally_counter {
477 __le64 tx_packets;
478 __le64 rx_packets;
479 __le64 tx_errors;
480 __le32 rx_errors;
481 __le16 rx_missed;
482 __le16 align_errors;
483 __le32 tx_one_collision;
484 __le32 tx_multi_collision;
485 __le64 rx_unicast;
486 __le64 rx_broadcast;
487 __le32 rx_multicast;
488 __le16 tx_aborted;
489 __le16 tx_underun;
490};
491
ac718b69 492struct rx_desc {
500b6d7e 493 __le32 opts1;
ac718b69 494#define RX_LEN_MASK 0x7fff
565cab0a 495
500b6d7e 496 __le32 opts2;
565cab0a 497#define RD_UDP_CS (1 << 23)
498#define RD_TCP_CS (1 << 22)
6128d1bb 499#define RD_IPV6_CS (1 << 20)
565cab0a 500#define RD_IPV4_CS (1 << 19)
501
500b6d7e 502 __le32 opts3;
565cab0a 503#define IPF (1 << 23) /* IP checksum fail */
504#define UDPF (1 << 22) /* UDP checksum fail */
505#define TCPF (1 << 21) /* TCP checksum fail */
c5554298 506#define RX_VLAN_TAG (1 << 16)
565cab0a 507
500b6d7e 508 __le32 opts4;
509 __le32 opts5;
510 __le32 opts6;
ac718b69 511};
512
513struct tx_desc {
500b6d7e 514 __le32 opts1;
ac718b69 515#define TX_FS (1 << 31) /* First segment of a packet */
516#define TX_LS (1 << 30) /* Final segment of a packet */
60c89071 517#define GTSENDV4 (1 << 28)
6128d1bb 518#define GTSENDV6 (1 << 27)
60c89071 519#define GTTCPHO_SHIFT 18
6128d1bb 520#define GTTCPHO_MAX 0x7fU
60c89071 521#define TX_LEN_MAX 0x3ffffU
5bd23881 522
500b6d7e 523 __le32 opts2;
5bd23881 524#define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
525#define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
526#define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
527#define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
60c89071 528#define MSS_SHIFT 17
529#define MSS_MAX 0x7ffU
530#define TCPHO_SHIFT 17
6128d1bb 531#define TCPHO_MAX 0x7ffU
c5554298 532#define TX_VLAN_TAG (1 << 16)
ac718b69 533};
534
dff4e8ad 535struct r8152;
536
ebc2ec48 537struct rx_agg {
538 struct list_head list;
539 struct urb *urb;
dff4e8ad 540 struct r8152 *context;
ebc2ec48 541 void *buffer;
542 void *head;
543};
544
545struct tx_agg {
546 struct list_head list;
547 struct urb *urb;
dff4e8ad 548 struct r8152 *context;
ebc2ec48 549 void *buffer;
550 void *head;
551 u32 skb_num;
552 u32 skb_len;
553};
554
ac718b69 555struct r8152 {
556 unsigned long flags;
557 struct usb_device *udev;
558 struct tasklet_struct tl;
40a82917 559 struct usb_interface *intf;
ac718b69 560 struct net_device *netdev;
40a82917 561 struct urb *intr_urb;
ebc2ec48 562 struct tx_agg tx_info[RTL8152_MAX_TX];
563 struct rx_agg rx_info[RTL8152_MAX_RX];
564 struct list_head rx_done, tx_free;
565 struct sk_buff_head tx_queue;
566 spinlock_t rx_lock, tx_lock;
ac718b69 567 struct delayed_work schedule;
568 struct mii_if_info mii;
c81229c9 569
570 struct rtl_ops {
571 void (*init)(struct r8152 *);
572 int (*enable)(struct r8152 *);
573 void (*disable)(struct r8152 *);
7e9da481 574 void (*up)(struct r8152 *);
c81229c9 575 void (*down)(struct r8152 *);
576 void (*unload)(struct r8152 *);
df35d283 577 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
578 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
c81229c9 579 } rtl_ops;
580
40a82917 581 int intr_interval;
21ff2e89 582 u32 saved_wolopts;
ac718b69 583 u32 msg_enable;
dd1b119c 584 u32 tx_qlen;
ac718b69 585 u16 ocp_base;
40a82917 586 u8 *intr_buff;
ac718b69 587 u8 version;
588 u8 speed;
589};
590
591enum rtl_version {
592 RTL_VER_UNKNOWN = 0,
593 RTL_VER_01,
43779f8d 594 RTL_VER_02,
595 RTL_VER_03,
596 RTL_VER_04,
597 RTL_VER_05,
598 RTL_VER_MAX
ac718b69 599};
600
60c89071 601enum tx_csum_stat {
602 TX_CSUM_SUCCESS = 0,
603 TX_CSUM_TSO,
604 TX_CSUM_NONE
605};
606
ac718b69 607/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
608 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
609 */
610static const int multicast_filter_limit = 32;
52aec126 611static unsigned int agg_buf_sz = 16384;
ac718b69 612
52aec126 613#define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
60c89071 614 VLAN_ETH_HLEN - VLAN_HLEN)
615
ac718b69 616static
617int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
618{
31787f53 619 int ret;
620 void *tmp;
621
622 tmp = kmalloc(size, GFP_KERNEL);
623 if (!tmp)
624 return -ENOMEM;
625
626 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
b209af99 627 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
628 value, index, tmp, size, 500);
31787f53 629
630 memcpy(data, tmp, size);
631 kfree(tmp);
632
633 return ret;
ac718b69 634}
635
636static
637int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
638{
31787f53 639 int ret;
640 void *tmp;
641
c4438f03 642 tmp = kmemdup(data, size, GFP_KERNEL);
31787f53 643 if (!tmp)
644 return -ENOMEM;
645
31787f53 646 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
b209af99 647 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
648 value, index, tmp, size, 500);
31787f53 649
650 kfree(tmp);
db8515ef 651
31787f53 652 return ret;
ac718b69 653}
654
655static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
b209af99 656 void *data, u16 type)
ac718b69 657{
45f4a19f 658 u16 limit = 64;
659 int ret = 0;
ac718b69 660
661 if (test_bit(RTL8152_UNPLUG, &tp->flags))
662 return -ENODEV;
663
664 /* both size and indix must be 4 bytes align */
665 if ((size & 3) || !size || (index & 3) || !data)
666 return -EPERM;
667
668 if ((u32)index + (u32)size > 0xffff)
669 return -EPERM;
670
671 while (size) {
672 if (size > limit) {
673 ret = get_registers(tp, index, type, limit, data);
674 if (ret < 0)
675 break;
676
677 index += limit;
678 data += limit;
679 size -= limit;
680 } else {
681 ret = get_registers(tp, index, type, size, data);
682 if (ret < 0)
683 break;
684
685 index += size;
686 data += size;
687 size = 0;
688 break;
689 }
690 }
691
692 return ret;
693}
694
695static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
b209af99 696 u16 size, void *data, u16 type)
ac718b69 697{
45f4a19f 698 int ret;
699 u16 byteen_start, byteen_end, byen;
700 u16 limit = 512;
ac718b69 701
702 if (test_bit(RTL8152_UNPLUG, &tp->flags))
703 return -ENODEV;
704
705 /* both size and indix must be 4 bytes align */
706 if ((size & 3) || !size || (index & 3) || !data)
707 return -EPERM;
708
709 if ((u32)index + (u32)size > 0xffff)
710 return -EPERM;
711
712 byteen_start = byteen & BYTE_EN_START_MASK;
713 byteen_end = byteen & BYTE_EN_END_MASK;
714
715 byen = byteen_start | (byteen_start << 4);
716 ret = set_registers(tp, index, type | byen, 4, data);
717 if (ret < 0)
718 goto error1;
719
720 index += 4;
721 data += 4;
722 size -= 4;
723
724 if (size) {
725 size -= 4;
726
727 while (size) {
728 if (size > limit) {
729 ret = set_registers(tp, index,
b209af99 730 type | BYTE_EN_DWORD,
731 limit, data);
ac718b69 732 if (ret < 0)
733 goto error1;
734
735 index += limit;
736 data += limit;
737 size -= limit;
738 } else {
739 ret = set_registers(tp, index,
b209af99 740 type | BYTE_EN_DWORD,
741 size, data);
ac718b69 742 if (ret < 0)
743 goto error1;
744
745 index += size;
746 data += size;
747 size = 0;
748 break;
749 }
750 }
751
752 byen = byteen_end | (byteen_end >> 4);
753 ret = set_registers(tp, index, type | byen, 4, data);
754 if (ret < 0)
755 goto error1;
756 }
757
758error1:
759 return ret;
760}
761
762static inline
763int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
764{
765 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
766}
767
768static inline
769int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
770{
771 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
772}
773
774static inline
775int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
776{
777 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
778}
779
780static inline
781int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
782{
783 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
784}
785
786static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
787{
c8826de8 788 __le32 data;
ac718b69 789
c8826de8 790 generic_ocp_read(tp, index, sizeof(data), &data, type);
ac718b69 791
792 return __le32_to_cpu(data);
793}
794
795static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
796{
c8826de8 797 __le32 tmp = __cpu_to_le32(data);
798
799 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
ac718b69 800}
801
802static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
803{
804 u32 data;
c8826de8 805 __le32 tmp;
ac718b69 806 u8 shift = index & 2;
807
808 index &= ~3;
809
c8826de8 810 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 811
c8826de8 812 data = __le32_to_cpu(tmp);
ac718b69 813 data >>= (shift * 8);
814 data &= 0xffff;
815
816 return (u16)data;
817}
818
819static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
820{
c8826de8 821 u32 mask = 0xffff;
822 __le32 tmp;
ac718b69 823 u16 byen = BYTE_EN_WORD;
824 u8 shift = index & 2;
825
826 data &= mask;
827
828 if (index & 2) {
829 byen <<= shift;
830 mask <<= (shift * 8);
831 data <<= (shift * 8);
832 index &= ~3;
833 }
834
c8826de8 835 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 836
c8826de8 837 data |= __le32_to_cpu(tmp) & ~mask;
838 tmp = __cpu_to_le32(data);
ac718b69 839
c8826de8 840 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 841}
842
843static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
844{
845 u32 data;
c8826de8 846 __le32 tmp;
ac718b69 847 u8 shift = index & 3;
848
849 index &= ~3;
850
c8826de8 851 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 852
c8826de8 853 data = __le32_to_cpu(tmp);
ac718b69 854 data >>= (shift * 8);
855 data &= 0xff;
856
857 return (u8)data;
858}
859
860static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
861{
c8826de8 862 u32 mask = 0xff;
863 __le32 tmp;
ac718b69 864 u16 byen = BYTE_EN_BYTE;
865 u8 shift = index & 3;
866
867 data &= mask;
868
869 if (index & 3) {
870 byen <<= shift;
871 mask <<= (shift * 8);
872 data <<= (shift * 8);
873 index &= ~3;
874 }
875
c8826de8 876 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 877
c8826de8 878 data |= __le32_to_cpu(tmp) & ~mask;
879 tmp = __cpu_to_le32(data);
ac718b69 880
c8826de8 881 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 882}
883
ac244d3e 884static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
e3fe0b1a 885{
886 u16 ocp_base, ocp_index;
887
888 ocp_base = addr & 0xf000;
889 if (ocp_base != tp->ocp_base) {
890 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
891 tp->ocp_base = ocp_base;
892 }
893
894 ocp_index = (addr & 0x0fff) | 0xb000;
ac244d3e 895 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
e3fe0b1a 896}
897
ac244d3e 898static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
ac718b69 899{
ac244d3e 900 u16 ocp_base, ocp_index;
ac718b69 901
ac244d3e 902 ocp_base = addr & 0xf000;
903 if (ocp_base != tp->ocp_base) {
904 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
905 tp->ocp_base = ocp_base;
ac718b69 906 }
ac244d3e 907
908 ocp_index = (addr & 0x0fff) | 0xb000;
909 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
ac718b69 910}
911
ac244d3e 912static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
ac718b69 913{
ac244d3e 914 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
915}
ac718b69 916
ac244d3e 917static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
918{
919 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
ac718b69 920}
921
43779f8d 922static void sram_write(struct r8152 *tp, u16 addr, u16 data)
923{
924 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
925 ocp_reg_write(tp, OCP_SRAM_DATA, data);
926}
927
928static u16 sram_read(struct r8152 *tp, u16 addr)
929{
930 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
931 return ocp_reg_read(tp, OCP_SRAM_DATA);
932}
933
ac718b69 934static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
935{
936 struct r8152 *tp = netdev_priv(netdev);
9a4be1bd 937 int ret;
ac718b69 938
6871438c 939 if (test_bit(RTL8152_UNPLUG, &tp->flags))
940 return -ENODEV;
941
ac718b69 942 if (phy_id != R8152_PHY_ID)
943 return -EINVAL;
944
9a4be1bd 945 ret = r8152_mdio_read(tp, reg);
946
9a4be1bd 947 return ret;
ac718b69 948}
949
950static
951void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
952{
953 struct r8152 *tp = netdev_priv(netdev);
954
6871438c 955 if (test_bit(RTL8152_UNPLUG, &tp->flags))
956 return;
957
ac718b69 958 if (phy_id != R8152_PHY_ID)
959 return;
960
961 r8152_mdio_write(tp, reg, val);
962}
963
b209af99 964static int
965r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
ebc2ec48 966
8ba789ab 967static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
968{
969 struct r8152 *tp = netdev_priv(netdev);
970 struct sockaddr *addr = p;
ea6a7112 971 int ret = -EADDRNOTAVAIL;
8ba789ab 972
973 if (!is_valid_ether_addr(addr->sa_data))
ea6a7112 974 goto out1;
975
976 ret = usb_autopm_get_interface(tp->intf);
977 if (ret < 0)
978 goto out1;
8ba789ab 979
980 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
981
982 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
983 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
984 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
985
ea6a7112 986 usb_autopm_put_interface(tp->intf);
987out1:
988 return ret;
8ba789ab 989}
990
179bb6d7 991static int set_ethernet_addr(struct r8152 *tp)
ac718b69 992{
993 struct net_device *dev = tp->netdev;
179bb6d7 994 struct sockaddr sa;
8a91c824 995 int ret;
ac718b69 996
8a91c824 997 if (tp->version == RTL_VER_01)
179bb6d7 998 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
8a91c824 999 else
179bb6d7 1000 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
8a91c824 1001
1002 if (ret < 0) {
179bb6d7 1003 netif_err(tp, probe, dev, "Get ether addr fail\n");
1004 } else if (!is_valid_ether_addr(sa.sa_data)) {
1005 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1006 sa.sa_data);
1007 eth_hw_addr_random(dev);
1008 ether_addr_copy(sa.sa_data, dev->dev_addr);
1009 ret = rtl8152_set_mac_address(dev, &sa);
1010 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1011 sa.sa_data);
8a91c824 1012 } else {
179bb6d7 1013 if (tp->version == RTL_VER_01)
1014 ether_addr_copy(dev->dev_addr, sa.sa_data);
1015 else
1016 ret = rtl8152_set_mac_address(dev, &sa);
ac718b69 1017 }
179bb6d7 1018
1019 return ret;
ac718b69 1020}
1021
ac718b69 1022static void read_bulk_callback(struct urb *urb)
1023{
ac718b69 1024 struct net_device *netdev;
ac718b69 1025 int status = urb->status;
ebc2ec48 1026 struct rx_agg *agg;
1027 struct r8152 *tp;
ac718b69 1028 int result;
ac718b69 1029
ebc2ec48 1030 agg = urb->context;
1031 if (!agg)
1032 return;
1033
1034 tp = agg->context;
ac718b69 1035 if (!tp)
1036 return;
ebc2ec48 1037
ac718b69 1038 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1039 return;
ebc2ec48 1040
1041 if (!test_bit(WORK_ENABLE, &tp->flags))
1042 return;
1043
ac718b69 1044 netdev = tp->netdev;
7559fb2f 1045
1046 /* When link down, the driver would cancel all bulks. */
1047 /* This avoid the re-submitting bulk */
ebc2ec48 1048 if (!netif_carrier_ok(netdev))
ac718b69 1049 return;
1050
9a4be1bd 1051 usb_mark_last_busy(tp->udev);
1052
ac718b69 1053 switch (status) {
1054 case 0:
ebc2ec48 1055 if (urb->actual_length < ETH_ZLEN)
1056 break;
1057
2685d410 1058 spin_lock(&tp->rx_lock);
ebc2ec48 1059 list_add_tail(&agg->list, &tp->rx_done);
2685d410 1060 spin_unlock(&tp->rx_lock);
ebc2ec48 1061 tasklet_schedule(&tp->tl);
1062 return;
ac718b69 1063 case -ESHUTDOWN:
1064 set_bit(RTL8152_UNPLUG, &tp->flags);
1065 netif_device_detach(tp->netdev);
ebc2ec48 1066 return;
ac718b69 1067 case -ENOENT:
1068 return; /* the urb is in unlink state */
1069 case -ETIME:
4a8deae2
HW
1070 if (net_ratelimit())
1071 netdev_warn(netdev, "maybe reset is needed?\n");
ebc2ec48 1072 break;
ac718b69 1073 default:
4a8deae2
HW
1074 if (net_ratelimit())
1075 netdev_warn(netdev, "Rx status %d\n", status);
ebc2ec48 1076 break;
ac718b69 1077 }
1078
ebc2ec48 1079 result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
ac718b69 1080 if (result == -ENODEV) {
1081 netif_device_detach(tp->netdev);
1082 } else if (result) {
2685d410 1083 spin_lock(&tp->rx_lock);
ebc2ec48 1084 list_add_tail(&agg->list, &tp->rx_done);
2685d410 1085 spin_unlock(&tp->rx_lock);
ebc2ec48 1086 tasklet_schedule(&tp->tl);
ac718b69 1087 }
ac718b69 1088}
1089
ebc2ec48 1090static void write_bulk_callback(struct urb *urb)
ac718b69 1091{
ebc2ec48 1092 struct net_device_stats *stats;
d104eafa 1093 struct net_device *netdev;
ebc2ec48 1094 struct tx_agg *agg;
ac718b69 1095 struct r8152 *tp;
ebc2ec48 1096 int status = urb->status;
ac718b69 1097
ebc2ec48 1098 agg = urb->context;
1099 if (!agg)
ac718b69 1100 return;
1101
ebc2ec48 1102 tp = agg->context;
1103 if (!tp)
1104 return;
1105
d104eafa 1106 netdev = tp->netdev;
05e0f1aa 1107 stats = &netdev->stats;
ebc2ec48 1108 if (status) {
4a8deae2 1109 if (net_ratelimit())
d104eafa 1110 netdev_warn(netdev, "Tx status %d\n", status);
ebc2ec48 1111 stats->tx_errors += agg->skb_num;
ac718b69 1112 } else {
ebc2ec48 1113 stats->tx_packets += agg->skb_num;
1114 stats->tx_bytes += agg->skb_len;
ac718b69 1115 }
1116
2685d410 1117 spin_lock(&tp->tx_lock);
ebc2ec48 1118 list_add_tail(&agg->list, &tp->tx_free);
2685d410 1119 spin_unlock(&tp->tx_lock);
ebc2ec48 1120
9a4be1bd 1121 usb_autopm_put_interface_async(tp->intf);
1122
d104eafa 1123 if (!netif_carrier_ok(netdev))
ebc2ec48 1124 return;
1125
1126 if (!test_bit(WORK_ENABLE, &tp->flags))
1127 return;
1128
1129 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1130 return;
1131
1132 if (!skb_queue_empty(&tp->tx_queue))
0c3121fc 1133 tasklet_schedule(&tp->tl);
ac718b69 1134}
1135
40a82917 1136static void intr_callback(struct urb *urb)
1137{
1138 struct r8152 *tp;
500b6d7e 1139 __le16 *d;
40a82917 1140 int status = urb->status;
1141 int res;
1142
1143 tp = urb->context;
1144 if (!tp)
1145 return;
1146
1147 if (!test_bit(WORK_ENABLE, &tp->flags))
1148 return;
1149
1150 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1151 return;
1152
1153 switch (status) {
1154 case 0: /* success */
1155 break;
1156 case -ECONNRESET: /* unlink */
1157 case -ESHUTDOWN:
1158 netif_device_detach(tp->netdev);
1159 case -ENOENT:
1160 return;
1161 case -EOVERFLOW:
1162 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1163 goto resubmit;
1164 /* -EPIPE: should clear the halt */
1165 default:
1166 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1167 goto resubmit;
1168 }
1169
1170 d = urb->transfer_buffer;
1171 if (INTR_LINK & __le16_to_cpu(d[0])) {
1172 if (!(tp->speed & LINK_STATUS)) {
1173 set_bit(RTL8152_LINK_CHG, &tp->flags);
1174 schedule_delayed_work(&tp->schedule, 0);
1175 }
1176 } else {
1177 if (tp->speed & LINK_STATUS) {
1178 set_bit(RTL8152_LINK_CHG, &tp->flags);
1179 schedule_delayed_work(&tp->schedule, 0);
1180 }
1181 }
1182
1183resubmit:
1184 res = usb_submit_urb(urb, GFP_ATOMIC);
1185 if (res == -ENODEV)
1186 netif_device_detach(tp->netdev);
1187 else if (res)
1188 netif_err(tp, intr, tp->netdev,
4a8deae2 1189 "can't resubmit intr, status %d\n", res);
40a82917 1190}
1191
ebc2ec48 1192static inline void *rx_agg_align(void *data)
1193{
8e1f51bd 1194 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
ebc2ec48 1195}
1196
1197static inline void *tx_agg_align(void *data)
1198{
8e1f51bd 1199 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
ebc2ec48 1200}
1201
1202static void free_all_mem(struct r8152 *tp)
1203{
1204 int i;
1205
1206 for (i = 0; i < RTL8152_MAX_RX; i++) {
9629e3c0 1207 usb_free_urb(tp->rx_info[i].urb);
1208 tp->rx_info[i].urb = NULL;
ebc2ec48 1209
9629e3c0 1210 kfree(tp->rx_info[i].buffer);
1211 tp->rx_info[i].buffer = NULL;
1212 tp->rx_info[i].head = NULL;
ebc2ec48 1213 }
1214
1215 for (i = 0; i < RTL8152_MAX_TX; i++) {
9629e3c0 1216 usb_free_urb(tp->tx_info[i].urb);
1217 tp->tx_info[i].urb = NULL;
ebc2ec48 1218
9629e3c0 1219 kfree(tp->tx_info[i].buffer);
1220 tp->tx_info[i].buffer = NULL;
1221 tp->tx_info[i].head = NULL;
ebc2ec48 1222 }
40a82917 1223
9629e3c0 1224 usb_free_urb(tp->intr_urb);
1225 tp->intr_urb = NULL;
40a82917 1226
9629e3c0 1227 kfree(tp->intr_buff);
1228 tp->intr_buff = NULL;
ebc2ec48 1229}
1230
1231static int alloc_all_mem(struct r8152 *tp)
1232{
1233 struct net_device *netdev = tp->netdev;
40a82917 1234 struct usb_interface *intf = tp->intf;
1235 struct usb_host_interface *alt = intf->cur_altsetting;
1236 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
ebc2ec48 1237 struct urb *urb;
1238 int node, i;
1239 u8 *buf;
1240
1241 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1242
1243 spin_lock_init(&tp->rx_lock);
1244 spin_lock_init(&tp->tx_lock);
1245 INIT_LIST_HEAD(&tp->rx_done);
1246 INIT_LIST_HEAD(&tp->tx_free);
1247 skb_queue_head_init(&tp->tx_queue);
1248
1249 for (i = 0; i < RTL8152_MAX_RX; i++) {
52aec126 1250 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
ebc2ec48 1251 if (!buf)
1252 goto err1;
1253
1254 if (buf != rx_agg_align(buf)) {
1255 kfree(buf);
52aec126 1256 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
8e1f51bd 1257 node);
ebc2ec48 1258 if (!buf)
1259 goto err1;
1260 }
1261
1262 urb = usb_alloc_urb(0, GFP_KERNEL);
1263 if (!urb) {
1264 kfree(buf);
1265 goto err1;
1266 }
1267
1268 INIT_LIST_HEAD(&tp->rx_info[i].list);
1269 tp->rx_info[i].context = tp;
1270 tp->rx_info[i].urb = urb;
1271 tp->rx_info[i].buffer = buf;
1272 tp->rx_info[i].head = rx_agg_align(buf);
1273 }
1274
1275 for (i = 0; i < RTL8152_MAX_TX; i++) {
52aec126 1276 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
ebc2ec48 1277 if (!buf)
1278 goto err1;
1279
1280 if (buf != tx_agg_align(buf)) {
1281 kfree(buf);
52aec126 1282 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
8e1f51bd 1283 node);
ebc2ec48 1284 if (!buf)
1285 goto err1;
1286 }
1287
1288 urb = usb_alloc_urb(0, GFP_KERNEL);
1289 if (!urb) {
1290 kfree(buf);
1291 goto err1;
1292 }
1293
1294 INIT_LIST_HEAD(&tp->tx_info[i].list);
1295 tp->tx_info[i].context = tp;
1296 tp->tx_info[i].urb = urb;
1297 tp->tx_info[i].buffer = buf;
1298 tp->tx_info[i].head = tx_agg_align(buf);
1299
1300 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1301 }
1302
40a82917 1303 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1304 if (!tp->intr_urb)
1305 goto err1;
1306
1307 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1308 if (!tp->intr_buff)
1309 goto err1;
1310
1311 tp->intr_interval = (int)ep_intr->desc.bInterval;
1312 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
b209af99 1313 tp->intr_buff, INTBUFSIZE, intr_callback,
1314 tp, tp->intr_interval);
40a82917 1315
ebc2ec48 1316 return 0;
1317
1318err1:
1319 free_all_mem(tp);
1320 return -ENOMEM;
1321}
1322
0de98f6c 1323static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1324{
1325 struct tx_agg *agg = NULL;
1326 unsigned long flags;
1327
21949ab7 1328 if (list_empty(&tp->tx_free))
1329 return NULL;
1330
0de98f6c 1331 spin_lock_irqsave(&tp->tx_lock, flags);
1332 if (!list_empty(&tp->tx_free)) {
1333 struct list_head *cursor;
1334
1335 cursor = tp->tx_free.next;
1336 list_del_init(cursor);
1337 agg = list_entry(cursor, struct tx_agg, list);
1338 }
1339 spin_unlock_irqrestore(&tp->tx_lock, flags);
1340
1341 return agg;
1342}
1343
60c89071 1344static inline __be16 get_protocol(struct sk_buff *skb)
5bd23881 1345{
60c89071 1346 __be16 protocol;
5bd23881 1347
60c89071 1348 if (skb->protocol == htons(ETH_P_8021Q))
1349 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1350 else
1351 protocol = skb->protocol;
5bd23881 1352
60c89071 1353 return protocol;
1354}
5bd23881 1355
b209af99 1356/* r8152_csum_workaround()
6128d1bb 1357 * The hw limites the value the transport offset. When the offset is out of the
1358 * range, calculate the checksum by sw.
1359 */
1360static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1361 struct sk_buff_head *list)
1362{
1363 if (skb_shinfo(skb)->gso_size) {
1364 netdev_features_t features = tp->netdev->features;
1365 struct sk_buff_head seg_list;
1366 struct sk_buff *segs, *nskb;
1367
a91d45f1 1368 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6128d1bb 1369 segs = skb_gso_segment(skb, features);
1370 if (IS_ERR(segs) || !segs)
1371 goto drop;
1372
1373 __skb_queue_head_init(&seg_list);
1374
1375 do {
1376 nskb = segs;
1377 segs = segs->next;
1378 nskb->next = NULL;
1379 __skb_queue_tail(&seg_list, nskb);
1380 } while (segs);
1381
1382 skb_queue_splice(&seg_list, list);
1383 dev_kfree_skb(skb);
1384 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1385 if (skb_checksum_help(skb) < 0)
1386 goto drop;
1387
1388 __skb_queue_head(list, skb);
1389 } else {
1390 struct net_device_stats *stats;
1391
1392drop:
1393 stats = &tp->netdev->stats;
1394 stats->tx_dropped++;
1395 dev_kfree_skb(skb);
1396 }
1397}
1398
b209af99 1399/* msdn_giant_send_check()
6128d1bb 1400 * According to the document of microsoft, the TCP Pseudo Header excludes the
1401 * packet length for IPv6 TCP large packets.
1402 */
1403static int msdn_giant_send_check(struct sk_buff *skb)
1404{
1405 const struct ipv6hdr *ipv6h;
1406 struct tcphdr *th;
fcb308d5 1407 int ret;
1408
1409 ret = skb_cow_head(skb, 0);
1410 if (ret)
1411 return ret;
6128d1bb 1412
1413 ipv6h = ipv6_hdr(skb);
1414 th = tcp_hdr(skb);
1415
1416 th->check = 0;
1417 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1418
fcb308d5 1419 return ret;
6128d1bb 1420}
1421
c5554298 1422static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1423{
1424 if (vlan_tx_tag_present(skb)) {
1425 u32 opts2;
1426
1427 opts2 = TX_VLAN_TAG | swab16(vlan_tx_tag_get(skb));
1428 desc->opts2 |= cpu_to_le32(opts2);
1429 }
1430}
1431
1432static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1433{
1434 u32 opts2 = le32_to_cpu(desc->opts2);
1435
1436 if (opts2 & RX_VLAN_TAG)
1437 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1438 swab16(opts2 & 0xffff));
1439}
1440
60c89071 1441static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1442 struct sk_buff *skb, u32 len, u32 transport_offset)
1443{
1444 u32 mss = skb_shinfo(skb)->gso_size;
1445 u32 opts1, opts2 = 0;
1446 int ret = TX_CSUM_SUCCESS;
1447
1448 WARN_ON_ONCE(len > TX_LEN_MAX);
1449
1450 opts1 = len | TX_FS | TX_LS;
1451
1452 if (mss) {
6128d1bb 1453 if (transport_offset > GTTCPHO_MAX) {
1454 netif_warn(tp, tx_err, tp->netdev,
1455 "Invalid transport offset 0x%x for TSO\n",
1456 transport_offset);
1457 ret = TX_CSUM_TSO;
1458 goto unavailable;
1459 }
1460
60c89071 1461 switch (get_protocol(skb)) {
1462 case htons(ETH_P_IP):
1463 opts1 |= GTSENDV4;
1464 break;
1465
6128d1bb 1466 case htons(ETH_P_IPV6):
fcb308d5 1467 if (msdn_giant_send_check(skb)) {
1468 ret = TX_CSUM_TSO;
1469 goto unavailable;
1470 }
6128d1bb 1471 opts1 |= GTSENDV6;
6128d1bb 1472 break;
1473
60c89071 1474 default:
1475 WARN_ON_ONCE(1);
1476 break;
1477 }
1478
1479 opts1 |= transport_offset << GTTCPHO_SHIFT;
1480 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1481 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1482 u8 ip_protocol;
5bd23881 1483
6128d1bb 1484 if (transport_offset > TCPHO_MAX) {
1485 netif_warn(tp, tx_err, tp->netdev,
1486 "Invalid transport offset 0x%x\n",
1487 transport_offset);
1488 ret = TX_CSUM_NONE;
1489 goto unavailable;
1490 }
1491
60c89071 1492 switch (get_protocol(skb)) {
5bd23881 1493 case htons(ETH_P_IP):
1494 opts2 |= IPV4_CS;
1495 ip_protocol = ip_hdr(skb)->protocol;
1496 break;
1497
1498 case htons(ETH_P_IPV6):
1499 opts2 |= IPV6_CS;
1500 ip_protocol = ipv6_hdr(skb)->nexthdr;
1501 break;
1502
1503 default:
1504 ip_protocol = IPPROTO_RAW;
1505 break;
1506 }
1507
60c89071 1508 if (ip_protocol == IPPROTO_TCP)
5bd23881 1509 opts2 |= TCP_CS;
60c89071 1510 else if (ip_protocol == IPPROTO_UDP)
5bd23881 1511 opts2 |= UDP_CS;
60c89071 1512 else
5bd23881 1513 WARN_ON_ONCE(1);
5bd23881 1514
60c89071 1515 opts2 |= transport_offset << TCPHO_SHIFT;
5bd23881 1516 }
60c89071 1517
1518 desc->opts2 = cpu_to_le32(opts2);
1519 desc->opts1 = cpu_to_le32(opts1);
1520
6128d1bb 1521unavailable:
60c89071 1522 return ret;
5bd23881 1523}
1524
b1379d9a 1525static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1526{
d84130a1 1527 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
9a4be1bd 1528 int remain, ret;
b1379d9a 1529 u8 *tx_data;
1530
d84130a1 1531 __skb_queue_head_init(&skb_head);
0c3121fc 1532 spin_lock(&tx_queue->lock);
d84130a1 1533 skb_queue_splice_init(tx_queue, &skb_head);
0c3121fc 1534 spin_unlock(&tx_queue->lock);
d84130a1 1535
b1379d9a 1536 tx_data = agg->head;
b209af99 1537 agg->skb_num = 0;
1538 agg->skb_len = 0;
52aec126 1539 remain = agg_buf_sz;
b1379d9a 1540
7937f9e5 1541 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
b1379d9a 1542 struct tx_desc *tx_desc;
1543 struct sk_buff *skb;
1544 unsigned int len;
60c89071 1545 u32 offset;
b1379d9a 1546
d84130a1 1547 skb = __skb_dequeue(&skb_head);
b1379d9a 1548 if (!skb)
1549 break;
1550
60c89071 1551 len = skb->len + sizeof(*tx_desc);
1552
1553 if (len > remain) {
d84130a1 1554 __skb_queue_head(&skb_head, skb);
b1379d9a 1555 break;
1556 }
1557
7937f9e5 1558 tx_data = tx_agg_align(tx_data);
b1379d9a 1559 tx_desc = (struct tx_desc *)tx_data;
60c89071 1560
1561 offset = (u32)skb_transport_offset(skb);
1562
6128d1bb 1563 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1564 r8152_csum_workaround(tp, skb, &skb_head);
1565 continue;
1566 }
60c89071 1567
c5554298 1568 rtl_tx_vlan_tag(tx_desc, skb);
1569
b1379d9a 1570 tx_data += sizeof(*tx_desc);
1571
60c89071 1572 len = skb->len;
1573 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1574 struct net_device_stats *stats = &tp->netdev->stats;
1575
1576 stats->tx_dropped++;
1577 dev_kfree_skb_any(skb);
1578 tx_data -= sizeof(*tx_desc);
1579 continue;
1580 }
1581
1582 tx_data += len;
b1379d9a 1583 agg->skb_len += len;
60c89071 1584 agg->skb_num++;
1585
b1379d9a 1586 dev_kfree_skb_any(skb);
1587
52aec126 1588 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
b1379d9a 1589 }
1590
d84130a1 1591 if (!skb_queue_empty(&skb_head)) {
0c3121fc 1592 spin_lock(&tx_queue->lock);
d84130a1 1593 skb_queue_splice(&skb_head, tx_queue);
0c3121fc 1594 spin_unlock(&tx_queue->lock);
d84130a1 1595 }
1596
0c3121fc 1597 netif_tx_lock(tp->netdev);
dd1b119c 1598
1599 if (netif_queue_stopped(tp->netdev) &&
1600 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1601 netif_wake_queue(tp->netdev);
1602
0c3121fc 1603 netif_tx_unlock(tp->netdev);
9a4be1bd 1604
0c3121fc 1605 ret = usb_autopm_get_interface_async(tp->intf);
9a4be1bd 1606 if (ret < 0)
1607 goto out_tx_fill;
dd1b119c 1608
b1379d9a 1609 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1610 agg->head, (int)(tx_data - (u8 *)agg->head),
1611 (usb_complete_t)write_bulk_callback, agg);
1612
0c3121fc 1613 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
9a4be1bd 1614 if (ret < 0)
0c3121fc 1615 usb_autopm_put_interface_async(tp->intf);
9a4be1bd 1616
1617out_tx_fill:
1618 return ret;
b1379d9a 1619}
1620
565cab0a 1621static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1622{
1623 u8 checksum = CHECKSUM_NONE;
1624 u32 opts2, opts3;
1625
1626 if (tp->version == RTL_VER_01)
1627 goto return_result;
1628
1629 opts2 = le32_to_cpu(rx_desc->opts2);
1630 opts3 = le32_to_cpu(rx_desc->opts3);
1631
1632 if (opts2 & RD_IPV4_CS) {
1633 if (opts3 & IPF)
1634 checksum = CHECKSUM_NONE;
1635 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1636 checksum = CHECKSUM_NONE;
1637 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1638 checksum = CHECKSUM_NONE;
1639 else
1640 checksum = CHECKSUM_UNNECESSARY;
6128d1bb 1641 } else if (RD_IPV6_CS) {
1642 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1643 checksum = CHECKSUM_UNNECESSARY;
1644 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1645 checksum = CHECKSUM_UNNECESSARY;
565cab0a 1646 }
1647
1648return_result:
1649 return checksum;
1650}
1651
ebc2ec48 1652static void rx_bottom(struct r8152 *tp)
1653{
a5a4f468 1654 unsigned long flags;
d84130a1 1655 struct list_head *cursor, *next, rx_queue;
ebc2ec48 1656
d84130a1 1657 if (list_empty(&tp->rx_done))
1658 return;
1659
1660 INIT_LIST_HEAD(&rx_queue);
a5a4f468 1661 spin_lock_irqsave(&tp->rx_lock, flags);
d84130a1 1662 list_splice_init(&tp->rx_done, &rx_queue);
1663 spin_unlock_irqrestore(&tp->rx_lock, flags);
1664
1665 list_for_each_safe(cursor, next, &rx_queue) {
43a4478d 1666 struct rx_desc *rx_desc;
1667 struct rx_agg *agg;
43a4478d 1668 int len_used = 0;
1669 struct urb *urb;
1670 u8 *rx_data;
1671 int ret;
1672
ebc2ec48 1673 list_del_init(cursor);
ebc2ec48 1674
1675 agg = list_entry(cursor, struct rx_agg, list);
1676 urb = agg->urb;
0de98f6c 1677 if (urb->actual_length < ETH_ZLEN)
1678 goto submit;
ebc2ec48 1679
ebc2ec48 1680 rx_desc = agg->head;
1681 rx_data = agg->head;
7937f9e5 1682 len_used += sizeof(struct rx_desc);
ebc2ec48 1683
7937f9e5 1684 while (urb->actual_length > len_used) {
43a4478d 1685 struct net_device *netdev = tp->netdev;
05e0f1aa 1686 struct net_device_stats *stats = &netdev->stats;
7937f9e5 1687 unsigned int pkt_len;
43a4478d 1688 struct sk_buff *skb;
1689
7937f9e5 1690 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
ebc2ec48 1691 if (pkt_len < ETH_ZLEN)
1692 break;
1693
7937f9e5 1694 len_used += pkt_len;
1695 if (urb->actual_length < len_used)
1696 break;
1697
8e1f51bd 1698 pkt_len -= CRC_SIZE;
ebc2ec48 1699 rx_data += sizeof(struct rx_desc);
1700
1701 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1702 if (!skb) {
1703 stats->rx_dropped++;
5e2f7485 1704 goto find_next_rx;
ebc2ec48 1705 }
565cab0a 1706
1707 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
ebc2ec48 1708 memcpy(skb->data, rx_data, pkt_len);
1709 skb_put(skb, pkt_len);
1710 skb->protocol = eth_type_trans(skb, netdev);
c5554298 1711 rtl_rx_vlan_tag(rx_desc, skb);
9d9aafa1 1712 netif_receive_skb(skb);
ebc2ec48 1713 stats->rx_packets++;
1714 stats->rx_bytes += pkt_len;
1715
5e2f7485 1716find_next_rx:
8e1f51bd 1717 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
ebc2ec48 1718 rx_desc = (struct rx_desc *)rx_data;
ebc2ec48 1719 len_used = (int)(rx_data - (u8 *)agg->head);
7937f9e5 1720 len_used += sizeof(struct rx_desc);
ebc2ec48 1721 }
1722
0de98f6c 1723submit:
ebc2ec48 1724 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
ebc2ec48 1725 if (ret && ret != -ENODEV) {
d84130a1 1726 spin_lock_irqsave(&tp->rx_lock, flags);
1727 list_add_tail(&agg->list, &tp->rx_done);
1728 spin_unlock_irqrestore(&tp->rx_lock, flags);
ebc2ec48 1729 tasklet_schedule(&tp->tl);
1730 }
1731 }
ebc2ec48 1732}
1733
1734static void tx_bottom(struct r8152 *tp)
1735{
ebc2ec48 1736 int res;
1737
b1379d9a 1738 do {
1739 struct tx_agg *agg;
ebc2ec48 1740
b1379d9a 1741 if (skb_queue_empty(&tp->tx_queue))
ebc2ec48 1742 break;
1743
b1379d9a 1744 agg = r8152_get_tx_agg(tp);
1745 if (!agg)
ebc2ec48 1746 break;
ebc2ec48 1747
b1379d9a 1748 res = r8152_tx_agg_fill(tp, agg);
1749 if (res) {
05e0f1aa 1750 struct net_device *netdev = tp->netdev;
ebc2ec48 1751
b1379d9a 1752 if (res == -ENODEV) {
1753 netif_device_detach(netdev);
1754 } else {
05e0f1aa 1755 struct net_device_stats *stats = &netdev->stats;
1756 unsigned long flags;
1757
b1379d9a 1758 netif_warn(tp, tx_err, netdev,
1759 "failed tx_urb %d\n", res);
1760 stats->tx_dropped += agg->skb_num;
db8515ef 1761
b1379d9a 1762 spin_lock_irqsave(&tp->tx_lock, flags);
1763 list_add_tail(&agg->list, &tp->tx_free);
1764 spin_unlock_irqrestore(&tp->tx_lock, flags);
1765 }
ebc2ec48 1766 }
b1379d9a 1767 } while (res == 0);
ebc2ec48 1768}
1769
1770static void bottom_half(unsigned long data)
ac718b69 1771{
1772 struct r8152 *tp;
ac718b69 1773
ebc2ec48 1774 tp = (struct r8152 *)data;
1775
1776 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1777 return;
1778
1779 if (!test_bit(WORK_ENABLE, &tp->flags))
ac718b69 1780 return;
ebc2ec48 1781
7559fb2f 1782 /* When link down, the driver would cancel all bulks. */
1783 /* This avoid the re-submitting bulk */
ebc2ec48 1784 if (!netif_carrier_ok(tp->netdev))
ac718b69 1785 return;
ebc2ec48 1786
1787 rx_bottom(tp);
0c3121fc 1788 tx_bottom(tp);
ebc2ec48 1789}
1790
1791static
1792int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1793{
1794 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
52aec126 1795 agg->head, agg_buf_sz,
b209af99 1796 (usb_complete_t)read_bulk_callback, agg);
ebc2ec48 1797
1798 return usb_submit_urb(agg->urb, mem_flags);
ac718b69 1799}
1800
00a5e360 1801static void rtl_drop_queued_tx(struct r8152 *tp)
1802{
1803 struct net_device_stats *stats = &tp->netdev->stats;
d84130a1 1804 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
00a5e360 1805 struct sk_buff *skb;
1806
d84130a1 1807 if (skb_queue_empty(tx_queue))
1808 return;
1809
1810 __skb_queue_head_init(&skb_head);
2685d410 1811 spin_lock_bh(&tx_queue->lock);
d84130a1 1812 skb_queue_splice_init(tx_queue, &skb_head);
2685d410 1813 spin_unlock_bh(&tx_queue->lock);
d84130a1 1814
1815 while ((skb = __skb_dequeue(&skb_head))) {
00a5e360 1816 dev_kfree_skb(skb);
1817 stats->tx_dropped++;
1818 }
1819}
1820
ac718b69 1821static void rtl8152_tx_timeout(struct net_device *netdev)
1822{
1823 struct r8152 *tp = netdev_priv(netdev);
ebc2ec48 1824 int i;
1825
4a8deae2 1826 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
ebc2ec48 1827 for (i = 0; i < RTL8152_MAX_TX; i++)
1828 usb_unlink_urb(tp->tx_info[i].urb);
ac718b69 1829}
1830
1831static void rtl8152_set_rx_mode(struct net_device *netdev)
1832{
1833 struct r8152 *tp = netdev_priv(netdev);
1834
40a82917 1835 if (tp->speed & LINK_STATUS) {
ac718b69 1836 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
40a82917 1837 schedule_delayed_work(&tp->schedule, 0);
1838 }
ac718b69 1839}
1840
1841static void _rtl8152_set_rx_mode(struct net_device *netdev)
1842{
1843 struct r8152 *tp = netdev_priv(netdev);
31787f53 1844 u32 mc_filter[2]; /* Multicast hash filter */
1845 __le32 tmp[2];
ac718b69 1846 u32 ocp_data;
1847
ac718b69 1848 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1849 netif_stop_queue(netdev);
1850 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1851 ocp_data &= ~RCR_ACPT_ALL;
1852 ocp_data |= RCR_AB | RCR_APM;
1853
1854 if (netdev->flags & IFF_PROMISC) {
1855 /* Unconditionally log net taps. */
1856 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1857 ocp_data |= RCR_AM | RCR_AAP;
b209af99 1858 mc_filter[1] = 0xffffffff;
1859 mc_filter[0] = 0xffffffff;
ac718b69 1860 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1861 (netdev->flags & IFF_ALLMULTI)) {
1862 /* Too many to filter perfectly -- accept all multicasts. */
1863 ocp_data |= RCR_AM;
b209af99 1864 mc_filter[1] = 0xffffffff;
1865 mc_filter[0] = 0xffffffff;
ac718b69 1866 } else {
1867 struct netdev_hw_addr *ha;
1868
b209af99 1869 mc_filter[1] = 0;
1870 mc_filter[0] = 0;
ac718b69 1871 netdev_for_each_mc_addr(ha, netdev) {
1872 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
b209af99 1873
ac718b69 1874 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1875 ocp_data |= RCR_AM;
1876 }
1877 }
1878
31787f53 1879 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1880 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
ac718b69 1881
31787f53 1882 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
ac718b69 1883 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1884 netif_wake_queue(netdev);
ac718b69 1885}
1886
1887static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
b209af99 1888 struct net_device *netdev)
ac718b69 1889{
1890 struct r8152 *tp = netdev_priv(netdev);
ac718b69 1891
ebc2ec48 1892 skb_tx_timestamp(skb);
ac718b69 1893
61598788 1894 skb_queue_tail(&tp->tx_queue, skb);
ebc2ec48 1895
0c3121fc 1896 if (!list_empty(&tp->tx_free)) {
1897 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
1898 set_bit(SCHEDULE_TASKLET, &tp->flags);
1899 schedule_delayed_work(&tp->schedule, 0);
1900 } else {
1901 usb_mark_last_busy(tp->udev);
1902 tasklet_schedule(&tp->tl);
1903 }
b209af99 1904 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
dd1b119c 1905 netif_stop_queue(netdev);
b209af99 1906 }
dd1b119c 1907
ac718b69 1908 return NETDEV_TX_OK;
1909}
1910
1911static void r8152b_reset_packet_filter(struct r8152 *tp)
1912{
1913 u32 ocp_data;
1914
1915 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1916 ocp_data &= ~FMC_FCR_MCU_EN;
1917 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1918 ocp_data |= FMC_FCR_MCU_EN;
1919 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1920}
1921
1922static void rtl8152_nic_reset(struct r8152 *tp)
1923{
1924 int i;
1925
1926 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1927
1928 for (i = 0; i < 1000; i++) {
1929 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1930 break;
b209af99 1931 usleep_range(100, 400);
ac718b69 1932 }
1933}
1934
dd1b119c 1935static void set_tx_qlen(struct r8152 *tp)
1936{
1937 struct net_device *netdev = tp->netdev;
1938
52aec126 1939 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
1940 sizeof(struct tx_desc));
dd1b119c 1941}
1942
ac718b69 1943static inline u8 rtl8152_get_speed(struct r8152 *tp)
1944{
1945 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1946}
1947
507605a8 1948static void rtl_set_eee_plus(struct r8152 *tp)
ac718b69 1949{
ebc2ec48 1950 u32 ocp_data;
ac718b69 1951 u8 speed;
1952
1953 speed = rtl8152_get_speed(tp);
ebc2ec48 1954 if (speed & _10bps) {
ac718b69 1955 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 1956 ocp_data |= EEEP_CR_EEEP_TX;
ac718b69 1957 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1958 } else {
1959 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 1960 ocp_data &= ~EEEP_CR_EEEP_TX;
ac718b69 1961 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1962 }
507605a8 1963}
1964
00a5e360 1965static void rxdy_gated_en(struct r8152 *tp, bool enable)
1966{
1967 u32 ocp_data;
1968
1969 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1970 if (enable)
1971 ocp_data |= RXDY_GATED_EN;
1972 else
1973 ocp_data &= ~RXDY_GATED_EN;
1974 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1975}
1976
445f7f4d 1977static int rtl_start_rx(struct r8152 *tp)
1978{
1979 int i, ret = 0;
1980
1981 INIT_LIST_HEAD(&tp->rx_done);
1982 for (i = 0; i < RTL8152_MAX_RX; i++) {
1983 INIT_LIST_HEAD(&tp->rx_info[i].list);
1984 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
1985 if (ret)
1986 break;
1987 }
1988
1989 return ret;
1990}
1991
1992static int rtl_stop_rx(struct r8152 *tp)
1993{
1994 int i;
1995
1996 for (i = 0; i < RTL8152_MAX_RX; i++)
1997 usb_kill_urb(tp->rx_info[i].urb);
1998
1999 return 0;
2000}
2001
507605a8 2002static int rtl_enable(struct r8152 *tp)
2003{
2004 u32 ocp_data;
ac718b69 2005
2006 r8152b_reset_packet_filter(tp);
2007
2008 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2009 ocp_data |= CR_RE | CR_TE;
2010 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2011
00a5e360 2012 rxdy_gated_en(tp, false);
ac718b69 2013
445f7f4d 2014 return rtl_start_rx(tp);
ac718b69 2015}
2016
507605a8 2017static int rtl8152_enable(struct r8152 *tp)
2018{
6871438c 2019 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2020 return -ENODEV;
2021
507605a8 2022 set_tx_qlen(tp);
2023 rtl_set_eee_plus(tp);
2024
2025 return rtl_enable(tp);
2026}
2027
43779f8d 2028static void r8153_set_rx_agg(struct r8152 *tp)
2029{
2030 u8 speed;
2031
2032 speed = rtl8152_get_speed(tp);
2033 if (speed & _1000bps) {
2034 if (tp->udev->speed == USB_SPEED_SUPER) {
2035 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2036 RX_THR_SUPPER);
2037 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2038 EARLY_AGG_SUPPER);
2039 } else {
2040 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2041 RX_THR_HIGH);
2042 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2043 EARLY_AGG_HIGH);
2044 }
2045 } else {
2046 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
2047 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2048 EARLY_AGG_SLOW);
2049 }
2050}
2051
2052static int rtl8153_enable(struct r8152 *tp)
2053{
6871438c 2054 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2055 return -ENODEV;
2056
43779f8d 2057 set_tx_qlen(tp);
2058 rtl_set_eee_plus(tp);
2059 r8153_set_rx_agg(tp);
2060
2061 return rtl_enable(tp);
2062}
2063
d70b1137 2064static void rtl_disable(struct r8152 *tp)
ac718b69 2065{
ebc2ec48 2066 u32 ocp_data;
2067 int i;
ac718b69 2068
6871438c 2069 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2070 rtl_drop_queued_tx(tp);
2071 return;
2072 }
2073
ac718b69 2074 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2075 ocp_data &= ~RCR_ACPT_ALL;
2076 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2077
00a5e360 2078 rtl_drop_queued_tx(tp);
ebc2ec48 2079
2080 for (i = 0; i < RTL8152_MAX_TX; i++)
2081 usb_kill_urb(tp->tx_info[i].urb);
ac718b69 2082
00a5e360 2083 rxdy_gated_en(tp, true);
ac718b69 2084
2085 for (i = 0; i < 1000; i++) {
2086 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2087 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2088 break;
8ddfa077 2089 usleep_range(1000, 2000);
ac718b69 2090 }
2091
2092 for (i = 0; i < 1000; i++) {
2093 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2094 break;
8ddfa077 2095 usleep_range(1000, 2000);
ac718b69 2096 }
2097
445f7f4d 2098 rtl_stop_rx(tp);
ac718b69 2099
2100 rtl8152_nic_reset(tp);
2101}
2102
00a5e360 2103static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2104{
2105 u32 ocp_data;
2106
2107 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2108 if (enable)
2109 ocp_data |= POWER_CUT;
2110 else
2111 ocp_data &= ~POWER_CUT;
2112 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2113
2114 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2115 ocp_data &= ~RESUME_INDICATE;
2116 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
00a5e360 2117}
2118
c5554298 2119static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2120{
2121 u32 ocp_data;
2122
2123 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2124 if (enable)
2125 ocp_data |= CPCR_RX_VLAN;
2126 else
2127 ocp_data &= ~CPCR_RX_VLAN;
2128 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2129}
2130
2131static int rtl8152_set_features(struct net_device *dev,
2132 netdev_features_t features)
2133{
2134 netdev_features_t changed = features ^ dev->features;
2135 struct r8152 *tp = netdev_priv(dev);
405f8a0e 2136 int ret;
2137
2138 ret = usb_autopm_get_interface(tp->intf);
2139 if (ret < 0)
2140 goto out;
c5554298 2141
2142 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2143 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2144 rtl_rx_vlan_en(tp, true);
2145 else
2146 rtl_rx_vlan_en(tp, false);
2147 }
2148
405f8a0e 2149 usb_autopm_put_interface(tp->intf);
2150
2151out:
2152 return ret;
c5554298 2153}
2154
21ff2e89 2155#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2156
2157static u32 __rtl_get_wol(struct r8152 *tp)
2158{
2159 u32 ocp_data;
2160 u32 wolopts = 0;
2161
2162 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2163 if (!(ocp_data & LAN_WAKE_EN))
2164 return 0;
2165
2166 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2167 if (ocp_data & LINK_ON_WAKE_EN)
2168 wolopts |= WAKE_PHY;
2169
2170 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2171 if (ocp_data & UWF_EN)
2172 wolopts |= WAKE_UCAST;
2173 if (ocp_data & BWF_EN)
2174 wolopts |= WAKE_BCAST;
2175 if (ocp_data & MWF_EN)
2176 wolopts |= WAKE_MCAST;
2177
2178 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2179 if (ocp_data & MAGIC_EN)
2180 wolopts |= WAKE_MAGIC;
2181
2182 return wolopts;
2183}
2184
2185static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2186{
2187 u32 ocp_data;
2188
2189 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2190
2191 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2192 ocp_data &= ~LINK_ON_WAKE_EN;
2193 if (wolopts & WAKE_PHY)
2194 ocp_data |= LINK_ON_WAKE_EN;
2195 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2196
2197 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2198 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2199 if (wolopts & WAKE_UCAST)
2200 ocp_data |= UWF_EN;
2201 if (wolopts & WAKE_BCAST)
2202 ocp_data |= BWF_EN;
2203 if (wolopts & WAKE_MCAST)
2204 ocp_data |= MWF_EN;
2205 if (wolopts & WAKE_ANY)
2206 ocp_data |= LAN_WAKE_EN;
2207 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2208
2209 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2210
2211 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2212 ocp_data &= ~MAGIC_EN;
2213 if (wolopts & WAKE_MAGIC)
2214 ocp_data |= MAGIC_EN;
2215 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2216
2217 if (wolopts & WAKE_ANY)
2218 device_set_wakeup_enable(&tp->udev->dev, true);
2219 else
2220 device_set_wakeup_enable(&tp->udev->dev, false);
2221}
2222
9a4be1bd 2223static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2224{
2225 if (enable) {
2226 u32 ocp_data;
2227
2228 __rtl_set_wol(tp, WAKE_ANY);
2229
2230 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2231
2232 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2233 ocp_data |= LINK_OFF_WAKE_EN;
2234 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2235
2236 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2237 } else {
2238 __rtl_set_wol(tp, tp->saved_wolopts);
2239 }
2240}
2241
aa66a5f1 2242static void rtl_phy_reset(struct r8152 *tp)
2243{
2244 u16 data;
2245 int i;
2246
2247 clear_bit(PHY_RESET, &tp->flags);
2248
2249 data = r8152_mdio_read(tp, MII_BMCR);
2250
2251 /* don't reset again before the previous one complete */
2252 if (data & BMCR_RESET)
2253 return;
2254
2255 data |= BMCR_RESET;
2256 r8152_mdio_write(tp, MII_BMCR, data);
2257
2258 for (i = 0; i < 50; i++) {
2259 msleep(20);
2260 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2261 break;
2262 }
2263}
2264
4349968a 2265static void r8153_teredo_off(struct r8152 *tp)
2266{
2267 u32 ocp_data;
2268
2269 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2270 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2271 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2272
2273 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2274 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2275 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2276}
2277
2278static void r8152b_disable_aldps(struct r8152 *tp)
2279{
2280 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2281 msleep(20);
2282}
2283
2284static inline void r8152b_enable_aldps(struct r8152 *tp)
2285{
2286 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2287 LINKENA | DIS_SDSAVE);
2288}
2289
d70b1137 2290static void rtl8152_disable(struct r8152 *tp)
2291{
2292 r8152b_disable_aldps(tp);
2293 rtl_disable(tp);
2294 r8152b_enable_aldps(tp);
2295}
2296
4349968a 2297static void r8152b_hw_phy_cfg(struct r8152 *tp)
2298{
f0cbe0ac 2299 u16 data;
2300
2301 data = r8152_mdio_read(tp, MII_BMCR);
2302 if (data & BMCR_PDOWN) {
2303 data &= ~BMCR_PDOWN;
2304 r8152_mdio_write(tp, MII_BMCR, data);
2305 }
2306
aa66a5f1 2307 set_bit(PHY_RESET, &tp->flags);
4349968a 2308}
2309
ac718b69 2310static void r8152b_exit_oob(struct r8152 *tp)
2311{
db8515ef 2312 u32 ocp_data;
2313 int i;
ac718b69 2314
2315 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2316 ocp_data &= ~RCR_ACPT_ALL;
2317 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2318
00a5e360 2319 rxdy_gated_en(tp, true);
da9bd117 2320 r8153_teredo_off(tp);
7e9da481 2321 r8152b_hw_phy_cfg(tp);
ac718b69 2322
2323 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2324 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2325
2326 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2327 ocp_data &= ~NOW_IS_OOB;
2328 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2329
2330 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2331 ocp_data &= ~MCU_BORW_EN;
2332 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2333
2334 for (i = 0; i < 1000; i++) {
2335 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2336 if (ocp_data & LINK_LIST_READY)
2337 break;
8ddfa077 2338 usleep_range(1000, 2000);
ac718b69 2339 }
2340
2341 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2342 ocp_data |= RE_INIT_LL;
2343 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2344
2345 for (i = 0; i < 1000; i++) {
2346 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2347 if (ocp_data & LINK_LIST_READY)
2348 break;
8ddfa077 2349 usleep_range(1000, 2000);
ac718b69 2350 }
2351
2352 rtl8152_nic_reset(tp);
2353
2354 /* rx share fifo credit full threshold */
2355 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2356
a3cc465d 2357 if (tp->udev->speed == USB_SPEED_FULL ||
2358 tp->udev->speed == USB_SPEED_LOW) {
ac718b69 2359 /* rx share fifo credit near full threshold */
2360 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2361 RXFIFO_THR2_FULL);
2362 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2363 RXFIFO_THR3_FULL);
2364 } else {
2365 /* rx share fifo credit near full threshold */
2366 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2367 RXFIFO_THR2_HIGH);
2368 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2369 RXFIFO_THR3_HIGH);
2370 }
2371
2372 /* TX share fifo free credit full threshold */
2373 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2374
2375 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
8e1f51bd 2376 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
ac718b69 2377 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2378 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2379
c5554298 2380 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
ac718b69 2381
2382 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2383
2384 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2385 ocp_data |= TCR0_AUTO_FIFO;
2386 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2387}
2388
2389static void r8152b_enter_oob(struct r8152 *tp)
2390{
45f4a19f 2391 u32 ocp_data;
2392 int i;
ac718b69 2393
2394 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2395 ocp_data &= ~NOW_IS_OOB;
2396 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2397
2398 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2399 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2400 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2401
d70b1137 2402 rtl_disable(tp);
ac718b69 2403
2404 for (i = 0; i < 1000; i++) {
2405 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2406 if (ocp_data & LINK_LIST_READY)
2407 break;
8ddfa077 2408 usleep_range(1000, 2000);
ac718b69 2409 }
2410
2411 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2412 ocp_data |= RE_INIT_LL;
2413 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2414
2415 for (i = 0; i < 1000; i++) {
2416 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2417 if (ocp_data & LINK_LIST_READY)
2418 break;
8ddfa077 2419 usleep_range(1000, 2000);
ac718b69 2420 }
2421
2422 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2423
c5554298 2424 rtl_rx_vlan_en(tp, true);
ac718b69 2425
2426 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2427 ocp_data |= ALDPS_PROXY_MODE;
2428 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2429
2430 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2431 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2432 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2433
00a5e360 2434 rxdy_gated_en(tp, false);
ac718b69 2435
2436 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2437 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2438 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2439}
2440
43779f8d 2441static void r8153_hw_phy_cfg(struct r8152 *tp)
2442{
2443 u32 ocp_data;
2444 u16 data;
2445
2446 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
f0cbe0ac 2447 data = r8152_mdio_read(tp, MII_BMCR);
2448 if (data & BMCR_PDOWN) {
2449 data &= ~BMCR_PDOWN;
2450 r8152_mdio_write(tp, MII_BMCR, data);
2451 }
43779f8d 2452
2453 if (tp->version == RTL_VER_03) {
2454 data = ocp_reg_read(tp, OCP_EEE_CFG);
2455 data &= ~CTAP_SHORT_EN;
2456 ocp_reg_write(tp, OCP_EEE_CFG, data);
2457 }
2458
2459 data = ocp_reg_read(tp, OCP_POWER_CFG);
2460 data |= EEE_CLKDIV_EN;
2461 ocp_reg_write(tp, OCP_POWER_CFG, data);
2462
2463 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2464 data |= EN_10M_BGOFF;
2465 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2466 data = ocp_reg_read(tp, OCP_POWER_CFG);
2467 data |= EN_10M_PLLOFF;
2468 ocp_reg_write(tp, OCP_POWER_CFG, data);
2469 data = sram_read(tp, SRAM_IMPEDANCE);
2470 data &= ~RX_DRIVING_MASK;
2471 sram_write(tp, SRAM_IMPEDANCE, data);
2472
2473 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2474 ocp_data |= PFM_PWM_SWITCH;
2475 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2476
2477 data = sram_read(tp, SRAM_LPF_CFG);
2478 data |= LPF_AUTO_TUNE;
2479 sram_write(tp, SRAM_LPF_CFG, data);
2480
2481 data = sram_read(tp, SRAM_10M_AMP1);
2482 data |= GDAC_IB_UPALL;
2483 sram_write(tp, SRAM_10M_AMP1, data);
2484 data = sram_read(tp, SRAM_10M_AMP2);
2485 data |= AMP_DN;
2486 sram_write(tp, SRAM_10M_AMP2, data);
aa66a5f1 2487
2488 set_bit(PHY_RESET, &tp->flags);
43779f8d 2489}
2490
b9702723 2491static void r8153_u1u2en(struct r8152 *tp, bool enable)
43779f8d 2492{
2493 u8 u1u2[8];
2494
2495 if (enable)
2496 memset(u1u2, 0xff, sizeof(u1u2));
2497 else
2498 memset(u1u2, 0x00, sizeof(u1u2));
2499
2500 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2501}
2502
b9702723 2503static void r8153_u2p3en(struct r8152 *tp, bool enable)
43779f8d 2504{
2505 u32 ocp_data;
2506
2507 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2508 if (enable)
2509 ocp_data |= U2P3_ENABLE;
2510 else
2511 ocp_data &= ~U2P3_ENABLE;
2512 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2513}
2514
b9702723 2515static void r8153_power_cut_en(struct r8152 *tp, bool enable)
43779f8d 2516{
2517 u32 ocp_data;
2518
2519 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2520 if (enable)
2521 ocp_data |= PWR_EN | PHASE2_EN;
2522 else
2523 ocp_data &= ~(PWR_EN | PHASE2_EN);
2524 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2525
2526 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2527 ocp_data &= ~PCUT_STATUS;
2528 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2529}
2530
43779f8d 2531static void r8153_first_init(struct r8152 *tp)
2532{
2533 u32 ocp_data;
2534 int i;
2535
00a5e360 2536 rxdy_gated_en(tp, true);
43779f8d 2537 r8153_teredo_off(tp);
2538
2539 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2540 ocp_data &= ~RCR_ACPT_ALL;
2541 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2542
2543 r8153_hw_phy_cfg(tp);
2544
2545 rtl8152_nic_reset(tp);
2546
2547 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2548 ocp_data &= ~NOW_IS_OOB;
2549 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2550
2551 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2552 ocp_data &= ~MCU_BORW_EN;
2553 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2554
2555 for (i = 0; i < 1000; i++) {
2556 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2557 if (ocp_data & LINK_LIST_READY)
2558 break;
8ddfa077 2559 usleep_range(1000, 2000);
43779f8d 2560 }
2561
2562 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2563 ocp_data |= RE_INIT_LL;
2564 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2565
2566 for (i = 0; i < 1000; i++) {
2567 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2568 if (ocp_data & LINK_LIST_READY)
2569 break;
8ddfa077 2570 usleep_range(1000, 2000);
43779f8d 2571 }
2572
c5554298 2573 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
43779f8d 2574
69b4b7a4 2575 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2576 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
43779f8d 2577
2578 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2579 ocp_data |= TCR0_AUTO_FIFO;
2580 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2581
2582 rtl8152_nic_reset(tp);
2583
2584 /* rx share fifo credit full threshold */
2585 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2586 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2587 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2588 /* TX share fifo free credit full threshold */
2589 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2590
9629e3c0 2591 /* rx aggregation */
43779f8d 2592 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2593 ocp_data &= ~RX_AGG_DISABLE;
2594 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2595}
2596
2597static void r8153_enter_oob(struct r8152 *tp)
2598{
2599 u32 ocp_data;
2600 int i;
2601
2602 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2603 ocp_data &= ~NOW_IS_OOB;
2604 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2605
d70b1137 2606 rtl_disable(tp);
43779f8d 2607
2608 for (i = 0; i < 1000; i++) {
2609 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2610 if (ocp_data & LINK_LIST_READY)
2611 break;
8ddfa077 2612 usleep_range(1000, 2000);
43779f8d 2613 }
2614
2615 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2616 ocp_data |= RE_INIT_LL;
2617 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2618
2619 for (i = 0; i < 1000; i++) {
2620 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2621 if (ocp_data & LINK_LIST_READY)
2622 break;
8ddfa077 2623 usleep_range(1000, 2000);
43779f8d 2624 }
2625
69b4b7a4 2626 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
43779f8d 2627
43779f8d 2628 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2629 ocp_data &= ~TEREDO_WAKE_MASK;
2630 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2631
c5554298 2632 rtl_rx_vlan_en(tp, true);
43779f8d 2633
2634 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2635 ocp_data |= ALDPS_PROXY_MODE;
2636 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2637
2638 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2639 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2640 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2641
00a5e360 2642 rxdy_gated_en(tp, false);
43779f8d 2643
2644 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2645 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2646 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2647}
2648
2649static void r8153_disable_aldps(struct r8152 *tp)
2650{
2651 u16 data;
2652
2653 data = ocp_reg_read(tp, OCP_POWER_CFG);
2654 data &= ~EN_ALDPS;
2655 ocp_reg_write(tp, OCP_POWER_CFG, data);
2656 msleep(20);
2657}
2658
2659static void r8153_enable_aldps(struct r8152 *tp)
2660{
2661 u16 data;
2662
2663 data = ocp_reg_read(tp, OCP_POWER_CFG);
2664 data |= EN_ALDPS;
2665 ocp_reg_write(tp, OCP_POWER_CFG, data);
2666}
2667
d70b1137 2668static void rtl8153_disable(struct r8152 *tp)
2669{
2670 r8153_disable_aldps(tp);
2671 rtl_disable(tp);
2672 r8153_enable_aldps(tp);
2673}
2674
ac718b69 2675static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2676{
43779f8d 2677 u16 bmcr, anar, gbcr;
ac718b69 2678 int ret = 0;
2679
2680 cancel_delayed_work_sync(&tp->schedule);
2681 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2682 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2683 ADVERTISE_100HALF | ADVERTISE_100FULL);
43779f8d 2684 if (tp->mii.supports_gmii) {
2685 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2686 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2687 } else {
2688 gbcr = 0;
2689 }
ac718b69 2690
2691 if (autoneg == AUTONEG_DISABLE) {
2692 if (speed == SPEED_10) {
2693 bmcr = 0;
2694 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2695 } else if (speed == SPEED_100) {
2696 bmcr = BMCR_SPEED100;
2697 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
43779f8d 2698 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2699 bmcr = BMCR_SPEED1000;
2700 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
ac718b69 2701 } else {
2702 ret = -EINVAL;
2703 goto out;
2704 }
2705
2706 if (duplex == DUPLEX_FULL)
2707 bmcr |= BMCR_FULLDPLX;
2708 } else {
2709 if (speed == SPEED_10) {
2710 if (duplex == DUPLEX_FULL)
2711 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2712 else
2713 anar |= ADVERTISE_10HALF;
2714 } else if (speed == SPEED_100) {
2715 if (duplex == DUPLEX_FULL) {
2716 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2717 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2718 } else {
2719 anar |= ADVERTISE_10HALF;
2720 anar |= ADVERTISE_100HALF;
2721 }
43779f8d 2722 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2723 if (duplex == DUPLEX_FULL) {
2724 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2725 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2726 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2727 } else {
2728 anar |= ADVERTISE_10HALF;
2729 anar |= ADVERTISE_100HALF;
2730 gbcr |= ADVERTISE_1000HALF;
2731 }
ac718b69 2732 } else {
2733 ret = -EINVAL;
2734 goto out;
2735 }
2736
2737 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2738 }
2739
aa66a5f1 2740 if (test_bit(PHY_RESET, &tp->flags))
2741 bmcr |= BMCR_RESET;
2742
43779f8d 2743 if (tp->mii.supports_gmii)
2744 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2745
ac718b69 2746 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2747 r8152_mdio_write(tp, MII_BMCR, bmcr);
2748
aa66a5f1 2749 if (test_bit(PHY_RESET, &tp->flags)) {
2750 int i;
2751
2752 clear_bit(PHY_RESET, &tp->flags);
2753 for (i = 0; i < 50; i++) {
2754 msleep(20);
2755 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2756 break;
2757 }
2758 }
2759
ac718b69 2760out:
ac718b69 2761
2762 return ret;
2763}
2764
d70b1137 2765static void rtl8152_up(struct r8152 *tp)
2766{
2767 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2768 return;
2769
2770 r8152b_disable_aldps(tp);
2771 r8152b_exit_oob(tp);
2772 r8152b_enable_aldps(tp);
2773}
2774
ac718b69 2775static void rtl8152_down(struct r8152 *tp)
2776{
6871438c 2777 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2778 rtl_drop_queued_tx(tp);
2779 return;
2780 }
2781
00a5e360 2782 r8152_power_cut_en(tp, false);
ac718b69 2783 r8152b_disable_aldps(tp);
2784 r8152b_enter_oob(tp);
2785 r8152b_enable_aldps(tp);
2786}
2787
d70b1137 2788static void rtl8153_up(struct r8152 *tp)
2789{
2790 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2791 return;
2792
2793 r8153_disable_aldps(tp);
2794 r8153_first_init(tp);
2795 r8153_enable_aldps(tp);
2796}
2797
43779f8d 2798static void rtl8153_down(struct r8152 *tp)
2799{
6871438c 2800 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2801 rtl_drop_queued_tx(tp);
2802 return;
2803 }
2804
b9702723 2805 r8153_u1u2en(tp, false);
2806 r8153_power_cut_en(tp, false);
43779f8d 2807 r8153_disable_aldps(tp);
2808 r8153_enter_oob(tp);
2809 r8153_enable_aldps(tp);
2810}
2811
ac718b69 2812static void set_carrier(struct r8152 *tp)
2813{
2814 struct net_device *netdev = tp->netdev;
2815 u8 speed;
2816
40a82917 2817 clear_bit(RTL8152_LINK_CHG, &tp->flags);
ac718b69 2818 speed = rtl8152_get_speed(tp);
2819
2820 if (speed & LINK_STATUS) {
2821 if (!(tp->speed & LINK_STATUS)) {
c81229c9 2822 tp->rtl_ops.enable(tp);
ac718b69 2823 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2824 netif_carrier_on(netdev);
2825 }
2826 } else {
2827 if (tp->speed & LINK_STATUS) {
2828 netif_carrier_off(netdev);
ebc2ec48 2829 tasklet_disable(&tp->tl);
c81229c9 2830 tp->rtl_ops.disable(tp);
ebc2ec48 2831 tasklet_enable(&tp->tl);
ac718b69 2832 }
2833 }
2834 tp->speed = speed;
2835}
2836
2837static void rtl_work_func_t(struct work_struct *work)
2838{
2839 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2840
9a4be1bd 2841 if (usb_autopm_get_interface(tp->intf) < 0)
2842 return;
2843
ac718b69 2844 if (!test_bit(WORK_ENABLE, &tp->flags))
2845 goto out1;
2846
2847 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2848 goto out1;
2849
40a82917 2850 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2851 set_carrier(tp);
ac718b69 2852
2853 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2854 _rtl8152_set_rx_mode(tp->netdev);
2855
0c3121fc 2856 if (test_bit(SCHEDULE_TASKLET, &tp->flags) &&
2857 (tp->speed & LINK_STATUS)) {
2858 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2859 tasklet_schedule(&tp->tl);
2860 }
aa66a5f1 2861
2862 if (test_bit(PHY_RESET, &tp->flags))
2863 rtl_phy_reset(tp);
2864
ac718b69 2865out1:
9a4be1bd 2866 usb_autopm_put_interface(tp->intf);
ac718b69 2867}
2868
2869static int rtl8152_open(struct net_device *netdev)
2870{
2871 struct r8152 *tp = netdev_priv(netdev);
2872 int res = 0;
2873
7e9da481 2874 res = alloc_all_mem(tp);
2875 if (res)
2876 goto out;
2877
9a4be1bd 2878 res = usb_autopm_get_interface(tp->intf);
2879 if (res < 0) {
2880 free_all_mem(tp);
2881 goto out;
2882 }
2883
2884 /* The WORK_ENABLE may be set when autoresume occurs */
2885 if (test_bit(WORK_ENABLE, &tp->flags)) {
2886 clear_bit(WORK_ENABLE, &tp->flags);
2887 usb_kill_urb(tp->intr_urb);
2888 cancel_delayed_work_sync(&tp->schedule);
2889 if (tp->speed & LINK_STATUS)
2890 tp->rtl_ops.disable(tp);
2891 }
2892
7e9da481 2893 tp->rtl_ops.up(tp);
2894
3d55f44f 2895 rtl8152_set_speed(tp, AUTONEG_ENABLE,
2896 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2897 DUPLEX_FULL);
2898 tp->speed = 0;
2899 netif_carrier_off(netdev);
2900 netif_start_queue(netdev);
2901 set_bit(WORK_ENABLE, &tp->flags);
db8515ef 2902
40a82917 2903 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2904 if (res) {
2905 if (res == -ENODEV)
2906 netif_device_detach(tp->netdev);
4a8deae2
HW
2907 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
2908 res);
7e9da481 2909 free_all_mem(tp);
ac718b69 2910 }
2911
9a4be1bd 2912 usb_autopm_put_interface(tp->intf);
ac718b69 2913
7e9da481 2914out:
ac718b69 2915 return res;
2916}
2917
2918static int rtl8152_close(struct net_device *netdev)
2919{
2920 struct r8152 *tp = netdev_priv(netdev);
2921 int res = 0;
2922
2923 clear_bit(WORK_ENABLE, &tp->flags);
3d55f44f 2924 usb_kill_urb(tp->intr_urb);
ac718b69 2925 cancel_delayed_work_sync(&tp->schedule);
2926 netif_stop_queue(netdev);
9a4be1bd 2927
2928 res = usb_autopm_get_interface(tp->intf);
2929 if (res < 0) {
2930 rtl_drop_queued_tx(tp);
2931 } else {
b209af99 2932 /* The autosuspend may have been enabled and wouldn't
9a4be1bd 2933 * be disable when autoresume occurs, because the
2934 * netif_running() would be false.
2935 */
2936 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2937 rtl_runtime_suspend_enable(tp, false);
2938 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
2939 }
2940
2941 tasklet_disable(&tp->tl);
2942 tp->rtl_ops.down(tp);
2943 tasklet_enable(&tp->tl);
2944 usb_autopm_put_interface(tp->intf);
2945 }
ac718b69 2946
7e9da481 2947 free_all_mem(tp);
2948
ac718b69 2949 return res;
2950}
2951
d24f6134 2952static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2953{
2954 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2955 ocp_reg_write(tp, OCP_EEE_DATA, reg);
2956 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2957}
2958
2959static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
2960{
2961 u16 data;
2962
2963 r8152_mmd_indirect(tp, dev, reg);
2964 data = ocp_reg_read(tp, OCP_EEE_DATA);
2965 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2966
2967 return data;
2968}
2969
2970static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
ac718b69 2971{
d24f6134 2972 r8152_mmd_indirect(tp, dev, reg);
2973 ocp_reg_write(tp, OCP_EEE_DATA, data);
2974 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2975}
2976
2977static void r8152_eee_en(struct r8152 *tp, bool enable)
2978{
2979 u16 config1, config2, config3;
45f4a19f 2980 u32 ocp_data;
ac718b69 2981
2982 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
d24f6134 2983 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
2984 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
2985 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
2986
2987 if (enable) {
2988 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2989 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
2990 config1 |= sd_rise_time(1);
2991 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
2992 config3 |= fast_snr(42);
2993 } else {
2994 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
2995 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
2996 RX_QUIET_EN);
2997 config1 |= sd_rise_time(7);
2998 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
2999 config3 |= fast_snr(511);
3000 }
3001
ac718b69 3002 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
d24f6134 3003 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3004 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3005 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
ac718b69 3006}
3007
d24f6134 3008static void r8152b_enable_eee(struct r8152 *tp)
3009{
3010 r8152_eee_en(tp, true);
3011 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3012}
3013
3014static void r8153_eee_en(struct r8152 *tp, bool enable)
43779f8d 3015{
3016 u32 ocp_data;
d24f6134 3017 u16 config;
43779f8d 3018
3019 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
d24f6134 3020 config = ocp_reg_read(tp, OCP_EEE_CFG);
3021
3022 if (enable) {
3023 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3024 config |= EEE10_EN;
3025 } else {
3026 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3027 config &= ~EEE10_EN;
3028 }
3029
43779f8d 3030 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
d24f6134 3031 ocp_reg_write(tp, OCP_EEE_CFG, config);
3032}
3033
3034static void r8153_enable_eee(struct r8152 *tp)
3035{
3036 r8153_eee_en(tp, true);
3037 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
43779f8d 3038}
3039
ac718b69 3040static void r8152b_enable_fc(struct r8152 *tp)
3041{
3042 u16 anar;
3043
3044 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3045 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3046 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3047}
3048
4f1d4d54 3049static void rtl_tally_reset(struct r8152 *tp)
3050{
3051 u32 ocp_data;
3052
3053 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3054 ocp_data |= TALLY_RESET;
3055 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3056}
3057
ac718b69 3058static void r8152b_init(struct r8152 *tp)
3059{
ebc2ec48 3060 u32 ocp_data;
ac718b69 3061
6871438c 3062 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3063 return;
3064
d70b1137 3065 r8152b_disable_aldps(tp);
3066
ac718b69 3067 if (tp->version == RTL_VER_01) {
3068 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3069 ocp_data &= ~LED_MODE_MASK;
3070 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3071 }
3072
00a5e360 3073 r8152_power_cut_en(tp, false);
ac718b69 3074
ac718b69 3075 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3076 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3077 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3078 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3079 ocp_data &= ~MCU_CLK_RATIO_MASK;
3080 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3081 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3082 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3083 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3084 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3085
3086 r8152b_enable_eee(tp);
3087 r8152b_enable_aldps(tp);
3088 r8152b_enable_fc(tp);
4f1d4d54 3089 rtl_tally_reset(tp);
ac718b69 3090
ebc2ec48 3091 /* enable rx aggregation */
ac718b69 3092 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
ebc2ec48 3093 ocp_data &= ~RX_AGG_DISABLE;
ac718b69 3094 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3095}
3096
43779f8d 3097static void r8153_init(struct r8152 *tp)
3098{
3099 u32 ocp_data;
3100 int i;
3101
6871438c 3102 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3103 return;
3104
d70b1137 3105 r8153_disable_aldps(tp);
b9702723 3106 r8153_u1u2en(tp, false);
43779f8d 3107
3108 for (i = 0; i < 500; i++) {
3109 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3110 AUTOLOAD_DONE)
3111 break;
3112 msleep(20);
3113 }
3114
3115 for (i = 0; i < 500; i++) {
3116 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3117 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3118 break;
3119 msleep(20);
3120 }
3121
b9702723 3122 r8153_u2p3en(tp, false);
43779f8d 3123
3124 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3125 ocp_data &= ~TIMER11_EN;
3126 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3127
43779f8d 3128 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3129 ocp_data &= ~LED_MODE_MASK;
3130 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3131
3132 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
3133 ocp_data &= ~LPM_TIMER_MASK;
3134 if (tp->udev->speed == USB_SPEED_SUPER)
3135 ocp_data |= LPM_TIMER_500US;
3136 else
3137 ocp_data |= LPM_TIMER_500MS;
3138 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3139
3140 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3141 ocp_data &= ~SEN_VAL_MASK;
3142 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3143 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3144
b9702723 3145 r8153_power_cut_en(tp, false);
3146 r8153_u1u2en(tp, true);
43779f8d 3147
43779f8d 3148 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3149 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3150 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3151 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3152 U1U2_SPDWN_EN | L1_SPDWN_EN);
3153 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3154 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3155 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3156 EEE_SPDWN_EN);
3157
3158 r8153_enable_eee(tp);
3159 r8153_enable_aldps(tp);
3160 r8152b_enable_fc(tp);
4f1d4d54 3161 rtl_tally_reset(tp);
43779f8d 3162}
3163
ac718b69 3164static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3165{
3166 struct r8152 *tp = usb_get_intfdata(intf);
3167
9a4be1bd 3168 if (PMSG_IS_AUTO(message))
3169 set_bit(SELECTIVE_SUSPEND, &tp->flags);
3170 else
3171 netif_device_detach(tp->netdev);
ac718b69 3172
3173 if (netif_running(tp->netdev)) {
3174 clear_bit(WORK_ENABLE, &tp->flags);
40a82917 3175 usb_kill_urb(tp->intr_urb);
ac718b69 3176 cancel_delayed_work_sync(&tp->schedule);
445f7f4d 3177 tasklet_disable(&tp->tl);
9a4be1bd 3178 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
445f7f4d 3179 rtl_stop_rx(tp);
9a4be1bd 3180 rtl_runtime_suspend_enable(tp, true);
3181 } else {
9a4be1bd 3182 tp->rtl_ops.down(tp);
9a4be1bd 3183 }
445f7f4d 3184 tasklet_enable(&tp->tl);
ac718b69 3185 }
3186
ac718b69 3187 return 0;
3188}
3189
3190static int rtl8152_resume(struct usb_interface *intf)
3191{
3192 struct r8152 *tp = usb_get_intfdata(intf);
3193
9a4be1bd 3194 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3195 tp->rtl_ops.init(tp);
3196 netif_device_attach(tp->netdev);
3197 }
3198
ac718b69 3199 if (netif_running(tp->netdev)) {
9a4be1bd 3200 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3201 rtl_runtime_suspend_enable(tp, false);
3202 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
445f7f4d 3203 set_bit(WORK_ENABLE, &tp->flags);
9a4be1bd 3204 if (tp->speed & LINK_STATUS)
445f7f4d 3205 rtl_start_rx(tp);
9a4be1bd 3206 } else {
3207 tp->rtl_ops.up(tp);
3208 rtl8152_set_speed(tp, AUTONEG_ENABLE,
b209af99 3209 tp->mii.supports_gmii ?
3210 SPEED_1000 : SPEED_100,
3211 DUPLEX_FULL);
445f7f4d 3212 tp->speed = 0;
3213 netif_carrier_off(tp->netdev);
3214 set_bit(WORK_ENABLE, &tp->flags);
9a4be1bd 3215 }
40a82917 3216 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
ac718b69 3217 }
3218
3219 return 0;
3220}
3221
21ff2e89 3222static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3223{
3224 struct r8152 *tp = netdev_priv(dev);
3225
9a4be1bd 3226 if (usb_autopm_get_interface(tp->intf) < 0)
3227 return;
3228
21ff2e89 3229 wol->supported = WAKE_ANY;
3230 wol->wolopts = __rtl_get_wol(tp);
9a4be1bd 3231
3232 usb_autopm_put_interface(tp->intf);
21ff2e89 3233}
3234
3235static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3236{
3237 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 3238 int ret;
3239
3240 ret = usb_autopm_get_interface(tp->intf);
3241 if (ret < 0)
3242 goto out_set_wol;
21ff2e89 3243
3244 __rtl_set_wol(tp, wol->wolopts);
3245 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3246
9a4be1bd 3247 usb_autopm_put_interface(tp->intf);
3248
3249out_set_wol:
3250 return ret;
21ff2e89 3251}
3252
a5ec27c1 3253static u32 rtl8152_get_msglevel(struct net_device *dev)
3254{
3255 struct r8152 *tp = netdev_priv(dev);
3256
3257 return tp->msg_enable;
3258}
3259
3260static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3261{
3262 struct r8152 *tp = netdev_priv(dev);
3263
3264 tp->msg_enable = value;
3265}
3266
ac718b69 3267static void rtl8152_get_drvinfo(struct net_device *netdev,
3268 struct ethtool_drvinfo *info)
3269{
3270 struct r8152 *tp = netdev_priv(netdev);
3271
b0b46c77 3272 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3273 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
ac718b69 3274 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3275}
3276
3277static
3278int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3279{
3280 struct r8152 *tp = netdev_priv(netdev);
8d4a4d72 3281 int ret;
ac718b69 3282
3283 if (!tp->mii.mdio_read)
3284 return -EOPNOTSUPP;
3285
8d4a4d72 3286 ret = usb_autopm_get_interface(tp->intf);
3287 if (ret < 0)
3288 goto out;
3289
3290 ret = mii_ethtool_gset(&tp->mii, cmd);
3291
3292 usb_autopm_put_interface(tp->intf);
3293
3294out:
3295 return ret;
ac718b69 3296}
3297
3298static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3299{
3300 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 3301 int ret;
3302
3303 ret = usb_autopm_get_interface(tp->intf);
3304 if (ret < 0)
3305 goto out;
ac718b69 3306
9a4be1bd 3307 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3308
3309 usb_autopm_put_interface(tp->intf);
3310
3311out:
3312 return ret;
ac718b69 3313}
3314
4f1d4d54 3315static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3316 "tx_packets",
3317 "rx_packets",
3318 "tx_errors",
3319 "rx_errors",
3320 "rx_missed",
3321 "align_errors",
3322 "tx_single_collisions",
3323 "tx_multi_collisions",
3324 "rx_unicast",
3325 "rx_broadcast",
3326 "rx_multicast",
3327 "tx_aborted",
3328 "tx_underrun",
3329};
3330
3331static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3332{
3333 switch (sset) {
3334 case ETH_SS_STATS:
3335 return ARRAY_SIZE(rtl8152_gstrings);
3336 default:
3337 return -EOPNOTSUPP;
3338 }
3339}
3340
3341static void rtl8152_get_ethtool_stats(struct net_device *dev,
3342 struct ethtool_stats *stats, u64 *data)
3343{
3344 struct r8152 *tp = netdev_priv(dev);
3345 struct tally_counter tally;
3346
0b030244 3347 if (usb_autopm_get_interface(tp->intf) < 0)
3348 return;
3349
4f1d4d54 3350 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3351
0b030244 3352 usb_autopm_put_interface(tp->intf);
3353
4f1d4d54 3354 data[0] = le64_to_cpu(tally.tx_packets);
3355 data[1] = le64_to_cpu(tally.rx_packets);
3356 data[2] = le64_to_cpu(tally.tx_errors);
3357 data[3] = le32_to_cpu(tally.rx_errors);
3358 data[4] = le16_to_cpu(tally.rx_missed);
3359 data[5] = le16_to_cpu(tally.align_errors);
3360 data[6] = le32_to_cpu(tally.tx_one_collision);
3361 data[7] = le32_to_cpu(tally.tx_multi_collision);
3362 data[8] = le64_to_cpu(tally.rx_unicast);
3363 data[9] = le64_to_cpu(tally.rx_broadcast);
3364 data[10] = le32_to_cpu(tally.rx_multicast);
3365 data[11] = le16_to_cpu(tally.tx_aborted);
3366 data[12] = le16_to_cpu(tally.tx_underun);
3367}
3368
3369static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3370{
3371 switch (stringset) {
3372 case ETH_SS_STATS:
3373 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3374 break;
3375 }
3376}
3377
df35d283 3378static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3379{
3380 u32 ocp_data, lp, adv, supported = 0;
3381 u16 val;
3382
3383 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3384 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3385
3386 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3387 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3388
3389 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3390 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3391
3392 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3393 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3394
3395 eee->eee_enabled = !!ocp_data;
3396 eee->eee_active = !!(supported & adv & lp);
3397 eee->supported = supported;
3398 eee->advertised = adv;
3399 eee->lp_advertised = lp;
3400
3401 return 0;
3402}
3403
3404static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3405{
3406 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3407
3408 r8152_eee_en(tp, eee->eee_enabled);
3409
3410 if (!eee->eee_enabled)
3411 val = 0;
3412
3413 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3414
3415 return 0;
3416}
3417
3418static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3419{
3420 u32 ocp_data, lp, adv, supported = 0;
3421 u16 val;
3422
3423 val = ocp_reg_read(tp, OCP_EEE_ABLE);
3424 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3425
3426 val = ocp_reg_read(tp, OCP_EEE_ADV);
3427 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3428
3429 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3430 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3431
3432 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3433 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3434
3435 eee->eee_enabled = !!ocp_data;
3436 eee->eee_active = !!(supported & adv & lp);
3437 eee->supported = supported;
3438 eee->advertised = adv;
3439 eee->lp_advertised = lp;
3440
3441 return 0;
3442}
3443
3444static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3445{
3446 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3447
3448 r8153_eee_en(tp, eee->eee_enabled);
3449
3450 if (!eee->eee_enabled)
3451 val = 0;
3452
3453 ocp_reg_write(tp, OCP_EEE_ADV, val);
3454
3455 return 0;
3456}
3457
3458static int
3459rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
3460{
3461 struct r8152 *tp = netdev_priv(net);
3462 int ret;
3463
3464 ret = usb_autopm_get_interface(tp->intf);
3465 if (ret < 0)
3466 goto out;
3467
3468 ret = tp->rtl_ops.eee_get(tp, edata);
3469
3470 usb_autopm_put_interface(tp->intf);
3471
3472out:
3473 return ret;
3474}
3475
3476static int
3477rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
3478{
3479 struct r8152 *tp = netdev_priv(net);
3480 int ret;
3481
3482 ret = usb_autopm_get_interface(tp->intf);
3483 if (ret < 0)
3484 goto out;
3485
3486 ret = tp->rtl_ops.eee_set(tp, edata);
9d31a7b9 3487 if (!ret)
3488 ret = mii_nway_restart(&tp->mii);
df35d283 3489
3490 usb_autopm_put_interface(tp->intf);
3491
3492out:
3493 return ret;
3494}
3495
ac718b69 3496static struct ethtool_ops ops = {
3497 .get_drvinfo = rtl8152_get_drvinfo,
3498 .get_settings = rtl8152_get_settings,
3499 .set_settings = rtl8152_set_settings,
3500 .get_link = ethtool_op_get_link,
a5ec27c1 3501 .get_msglevel = rtl8152_get_msglevel,
3502 .set_msglevel = rtl8152_set_msglevel,
21ff2e89 3503 .get_wol = rtl8152_get_wol,
3504 .set_wol = rtl8152_set_wol,
4f1d4d54 3505 .get_strings = rtl8152_get_strings,
3506 .get_sset_count = rtl8152_get_sset_count,
3507 .get_ethtool_stats = rtl8152_get_ethtool_stats,
df35d283 3508 .get_eee = rtl_ethtool_get_eee,
3509 .set_eee = rtl_ethtool_set_eee,
ac718b69 3510};
3511
3512static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3513{
3514 struct r8152 *tp = netdev_priv(netdev);
3515 struct mii_ioctl_data *data = if_mii(rq);
9a4be1bd 3516 int res;
3517
6871438c 3518 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3519 return -ENODEV;
3520
9a4be1bd 3521 res = usb_autopm_get_interface(tp->intf);
3522 if (res < 0)
3523 goto out;
ac718b69 3524
3525 switch (cmd) {
3526 case SIOCGMIIPHY:
3527 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3528 break;
3529
3530 case SIOCGMIIREG:
3531 data->val_out = r8152_mdio_read(tp, data->reg_num);
3532 break;
3533
3534 case SIOCSMIIREG:
3535 if (!capable(CAP_NET_ADMIN)) {
3536 res = -EPERM;
3537 break;
3538 }
3539 r8152_mdio_write(tp, data->reg_num, data->val_in);
3540 break;
3541
3542 default:
3543 res = -EOPNOTSUPP;
3544 }
3545
9a4be1bd 3546 usb_autopm_put_interface(tp->intf);
3547
3548out:
ac718b69 3549 return res;
3550}
3551
69b4b7a4 3552static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
3553{
3554 struct r8152 *tp = netdev_priv(dev);
3555
3556 switch (tp->version) {
3557 case RTL_VER_01:
3558 case RTL_VER_02:
3559 return eth_change_mtu(dev, new_mtu);
3560 default:
3561 break;
3562 }
3563
3564 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
3565 return -EINVAL;
3566
3567 dev->mtu = new_mtu;
3568
3569 return 0;
3570}
3571
ac718b69 3572static const struct net_device_ops rtl8152_netdev_ops = {
3573 .ndo_open = rtl8152_open,
3574 .ndo_stop = rtl8152_close,
3575 .ndo_do_ioctl = rtl8152_ioctl,
3576 .ndo_start_xmit = rtl8152_start_xmit,
3577 .ndo_tx_timeout = rtl8152_tx_timeout,
c5554298 3578 .ndo_set_features = rtl8152_set_features,
ac718b69 3579 .ndo_set_rx_mode = rtl8152_set_rx_mode,
3580 .ndo_set_mac_address = rtl8152_set_mac_address,
69b4b7a4 3581 .ndo_change_mtu = rtl8152_change_mtu,
ac718b69 3582 .ndo_validate_addr = eth_validate_addr,
3583};
3584
3585static void r8152b_get_version(struct r8152 *tp)
3586{
3587 u32 ocp_data;
3588 u16 version;
3589
3590 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3591 version = (u16)(ocp_data & VERSION_MASK);
3592
3593 switch (version) {
3594 case 0x4c00:
3595 tp->version = RTL_VER_01;
3596 break;
3597 case 0x4c10:
3598 tp->version = RTL_VER_02;
3599 break;
43779f8d 3600 case 0x5c00:
3601 tp->version = RTL_VER_03;
3602 tp->mii.supports_gmii = 1;
3603 break;
3604 case 0x5c10:
3605 tp->version = RTL_VER_04;
3606 tp->mii.supports_gmii = 1;
3607 break;
3608 case 0x5c20:
3609 tp->version = RTL_VER_05;
3610 tp->mii.supports_gmii = 1;
3611 break;
ac718b69 3612 default:
3613 netif_info(tp, probe, tp->netdev,
3614 "Unknown version 0x%04x\n", version);
3615 break;
3616 }
3617}
3618
e3fe0b1a 3619static void rtl8152_unload(struct r8152 *tp)
3620{
6871438c 3621 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3622 return;
3623
00a5e360 3624 if (tp->version != RTL_VER_01)
3625 r8152_power_cut_en(tp, true);
e3fe0b1a 3626}
3627
43779f8d 3628static void rtl8153_unload(struct r8152 *tp)
3629{
6871438c 3630 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3631 return;
3632
49be1723 3633 r8153_power_cut_en(tp, false);
43779f8d 3634}
3635
31ca1dec 3636static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id)
c81229c9 3637{
3638 struct rtl_ops *ops = &tp->rtl_ops;
31ca1dec 3639 int ret = -ENODEV;
c81229c9 3640
3641 switch (id->idVendor) {
3642 case VENDOR_ID_REALTEK:
3643 switch (id->idProduct) {
3644 case PRODUCT_ID_RTL8152:
3645 ops->init = r8152b_init;
3646 ops->enable = rtl8152_enable;
3647 ops->disable = rtl8152_disable;
d70b1137 3648 ops->up = rtl8152_up;
c81229c9 3649 ops->down = rtl8152_down;
3650 ops->unload = rtl8152_unload;
df35d283 3651 ops->eee_get = r8152_get_eee;
3652 ops->eee_set = r8152_set_eee;
31ca1dec 3653 ret = 0;
c81229c9 3654 break;
43779f8d 3655 case PRODUCT_ID_RTL8153:
3656 ops->init = r8153_init;
3657 ops->enable = rtl8153_enable;
d70b1137 3658 ops->disable = rtl8153_disable;
3659 ops->up = rtl8153_up;
43779f8d 3660 ops->down = rtl8153_down;
3661 ops->unload = rtl8153_unload;
df35d283 3662 ops->eee_get = r8153_get_eee;
3663 ops->eee_set = r8153_set_eee;
31ca1dec 3664 ret = 0;
43779f8d 3665 break;
3666 default:
43779f8d 3667 break;
3668 }
3669 break;
3670
3671 case VENDOR_ID_SAMSUNG:
3672 switch (id->idProduct) {
3673 case PRODUCT_ID_SAMSUNG:
3674 ops->init = r8153_init;
3675 ops->enable = rtl8153_enable;
d70b1137 3676 ops->disable = rtl8153_disable;
3677 ops->up = rtl8153_up;
43779f8d 3678 ops->down = rtl8153_down;
3679 ops->unload = rtl8153_unload;
df35d283 3680 ops->eee_get = r8153_get_eee;
3681 ops->eee_set = r8153_set_eee;
31ca1dec 3682 ret = 0;
43779f8d 3683 break;
c81229c9 3684 default:
c81229c9 3685 break;
3686 }
3687 break;
3688
3689 default:
c81229c9 3690 break;
3691 }
3692
31ca1dec 3693 if (ret)
3694 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
3695
c81229c9 3696 return ret;
3697}
3698
ac718b69 3699static int rtl8152_probe(struct usb_interface *intf,
3700 const struct usb_device_id *id)
3701{
3702 struct usb_device *udev = interface_to_usbdev(intf);
3703 struct r8152 *tp;
3704 struct net_device *netdev;
ebc2ec48 3705 int ret;
ac718b69 3706
10c32717 3707 if (udev->actconfig->desc.bConfigurationValue != 1) {
3708 usb_driver_set_configuration(udev, 1);
3709 return -ENODEV;
3710 }
3711
3712 usb_reset_device(udev);
ac718b69 3713 netdev = alloc_etherdev(sizeof(struct r8152));
3714 if (!netdev) {
4a8deae2 3715 dev_err(&intf->dev, "Out of memory\n");
ac718b69 3716 return -ENOMEM;
3717 }
3718
ebc2ec48 3719 SET_NETDEV_DEV(netdev, &intf->dev);
ac718b69 3720 tp = netdev_priv(netdev);
3721 tp->msg_enable = 0x7FFF;
3722
e3ad412a 3723 tp->udev = udev;
3724 tp->netdev = netdev;
3725 tp->intf = intf;
3726
31ca1dec 3727 ret = rtl_ops_init(tp, id);
3728 if (ret)
3729 goto out;
c81229c9 3730
ebc2ec48 3731 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
ac718b69 3732 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
3733
ac718b69 3734 netdev->netdev_ops = &rtl8152_netdev_ops;
3735 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5bd23881 3736
60c89071 3737 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6128d1bb 3738 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
c5554298 3739 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
3740 NETIF_F_HW_VLAN_CTAG_TX;
60c89071 3741 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6128d1bb 3742 NETIF_F_TSO | NETIF_F_FRAGLIST |
c5554298 3743 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
3744 NETIF_F_HW_VLAN_CTAG_RX |
3745 NETIF_F_HW_VLAN_CTAG_TX;
3746 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3747 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
3748 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
db8515ef 3749
7ad24ea4 3750 netdev->ethtool_ops = &ops;
60c89071 3751 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
ac718b69 3752
3753 tp->mii.dev = netdev;
3754 tp->mii.mdio_read = read_mii_word;
3755 tp->mii.mdio_write = write_mii_word;
3756 tp->mii.phy_id_mask = 0x3f;
3757 tp->mii.reg_num_mask = 0x1f;
3758 tp->mii.phy_id = R8152_PHY_ID;
3759 tp->mii.supports_gmii = 0;
3760
9a4be1bd 3761 intf->needs_remote_wakeup = 1;
3762
ac718b69 3763 r8152b_get_version(tp);
c81229c9 3764 tp->rtl_ops.init(tp);
ac718b69 3765 set_ethernet_addr(tp);
3766
ac718b69 3767 usb_set_intfdata(intf, tp);
ac718b69 3768
ebc2ec48 3769 ret = register_netdev(netdev);
3770 if (ret != 0) {
4a8deae2 3771 netif_err(tp, probe, netdev, "couldn't register the device\n");
ebc2ec48 3772 goto out1;
ac718b69 3773 }
3774
21ff2e89 3775 tp->saved_wolopts = __rtl_get_wol(tp);
3776 if (tp->saved_wolopts)
3777 device_set_wakeup_enable(&udev->dev, true);
3778 else
3779 device_set_wakeup_enable(&udev->dev, false);
3780
4a8deae2 3781 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
ac718b69 3782
3783 return 0;
3784
ac718b69 3785out1:
ebc2ec48 3786 usb_set_intfdata(intf, NULL);
ac718b69 3787out:
3788 free_netdev(netdev);
ebc2ec48 3789 return ret;
ac718b69 3790}
3791
ac718b69 3792static void rtl8152_disconnect(struct usb_interface *intf)
3793{
3794 struct r8152 *tp = usb_get_intfdata(intf);
3795
3796 usb_set_intfdata(intf, NULL);
3797 if (tp) {
f561de33 3798 struct usb_device *udev = tp->udev;
3799
3800 if (udev->state == USB_STATE_NOTATTACHED)
3801 set_bit(RTL8152_UNPLUG, &tp->flags);
3802
ac718b69 3803 tasklet_kill(&tp->tl);
3804 unregister_netdev(tp->netdev);
c81229c9 3805 tp->rtl_ops.unload(tp);
ac718b69 3806 free_netdev(tp->netdev);
3807 }
3808}
3809
3810/* table of devices that work with this driver */
3811static struct usb_device_id rtl8152_table[] = {
10c32717 3812 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
3813 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)},
3814 {USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)},
ac718b69 3815 {}
3816};
3817
3818MODULE_DEVICE_TABLE(usb, rtl8152_table);
3819
3820static struct usb_driver rtl8152_driver = {
3821 .name = MODULENAME,
ebc2ec48 3822 .id_table = rtl8152_table,
ac718b69 3823 .probe = rtl8152_probe,
3824 .disconnect = rtl8152_disconnect,
ac718b69 3825 .suspend = rtl8152_suspend,
ebc2ec48 3826 .resume = rtl8152_resume,
3827 .reset_resume = rtl8152_resume,
9a4be1bd 3828 .supports_autosuspend = 1,
a634782f 3829 .disable_hub_initiated_lpm = 1,
ac718b69 3830};
3831
b4236daa 3832module_usb_driver(rtl8152_driver);
ac718b69 3833
3834MODULE_AUTHOR(DRIVER_AUTHOR);
3835MODULE_DESCRIPTION(DRIVER_DESC);
3836MODULE_LICENSE("GPL");
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